commit 57aa16027864ec312b98be4f8e9e1f271d158308 Author: Timo Lang Date: Tue May 12 11:12:43 2015 +0200 Added doxygen output of current emulator branch. diff --git a/_c_m_s_i_s__m_i_s_r_a__exceptions.html b/_c_m_s_i_s__m_i_s_r_a__exceptions.html new file mode 100644 index 0000000..18a73a0 --- /dev/null +++ b/_c_m_s_i_s__m_i_s_r_a__exceptions.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: MISRA-C:2004 Compliance Exceptions + + + + + + + + + + +
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MISRA-C:2004 Compliance Exceptions
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+

CMSIS violates the following MISRA-C:2004 rules:

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    +
  • Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'.
    • +
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    +
  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers.
    • +
+
    +
  • Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code.
    • +
+
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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README.md File Reference
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/annotated.html b/annotated.html new file mode 100644 index 0000000..a6d86a2 --- /dev/null +++ b/annotated.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: Data Structures + + + + + + + + + + +
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Data Structures
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Here are the data structures with brief descriptions:
+ + + + + + + + + + + + + +
 CBlock
 CBUTTON_STRUCT
 CCHECKBOX_STRUCT
 CDIRECTORY_STRUCT
 CFILE_DATE_STRUCT
 CFILE_HANDLE
 CFILE_STRUCT
 CFILE_TIME_STRUCT
 CNUMUPDOWN_STRUCT
 CPOINT_STRUCT
 CSCREEN_S
 CTOUCH_AREA_STRUCT
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/app_8c.html b/app_8c.html new file mode 100644 index 0000000..716f2d8 --- /dev/null +++ b/app_8c.html @@ -0,0 +1,123 @@ + + + + + + +discoverpixy: common/app/app.c File Reference + + + + + + + + + + +
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+Functions
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app.c File Reference
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+
+
#include "app.h"
+#include "tft.h"
+#include "system.h"
+#include "touch.h"
+#include "screen_main.h"
+#include "filesystem.h"
+
+Include dependency graph for app.c:
+
+
+ + +
+
+ + + + + +

+Functions

void app_init ()
 
void app_process ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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app.h File Reference
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

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+Functions

void app_init ()
 
void app_process ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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app.h
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+Go to the documentation of this file.
1 #ifndef APP_H
+
2 #define APP_H
+
3 
+
9 
+
14 void app_init();
+
15 
+
20 void app_process();
+
21 
+
22 
+
25 #endif /* APP_H */
+
app_process
void app_process()
Definition: app.c:19
+
app_init
void app_init()
Definition: app.c:8
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Macros | +Functions
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+
button.c File Reference
+
+
+
#include "tft.h"
+#include "touch.h"
+#include "button.h"
+#include <string.h>
+
+Include dependency graph for button.c:
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+
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+ + + +

+Macros

#define BRIGHTNESS_VAL   3
 
+ + + + + + + + + +

+Functions

void buttons_cb (void *touchArea, TOUCH_ACTION triggeredAction)
 
bool gui_button_add (BUTTON_STRUCT *button)
 
void gui_button_redraw (BUTTON_STRUCT *button)
 
void gui_button_remove (BUTTON_STRUCT *button)
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define BRIGHTNESS_VAL   3
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void buttons_cb (void * touchArea,
TOUCH_ACTION triggeredAction 
)
+
+ +

+Here is the call graph for this function:
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+ + +
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+ +

+Here is the caller graph for this function:
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+ + +
+

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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Data Structures | +Macros | +Typedefs | +Functions
+
+
button.h File Reference
+
+
+
#include "touch.h"
+
+Include dependency graph for button.h:
+
+
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

+ + + + +

+Data Structures

struct  BUTTON_STRUCT
 
+ + + + +

+Macros

#define AUTO   0
 Use this value instead of x2, y2 in the BUTTON_STRUCT to autocalculate the button width/height. More...
 
+ + + +

+Typedefs

typedef void(* BUTTON_CALLBACK) (void *button)
 
+ + + + + + + +

+Functions

bool gui_button_add (BUTTON_STRUCT *button)
 
void gui_button_remove (BUTTON_STRUCT *button)
 
void gui_button_redraw (BUTTON_STRUCT *button)
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
button.h
+
+
+Go to the documentation of this file.
1 #ifndef BUTTON_H
+
2 #define BUTTON_H
+
3 
+
9 
+
15 
+
16 
+
17 
+
18 #include "touch.h"
+
19 
+
24 typedef void (*BUTTON_CALLBACK)(void *button);
+
25 
+
26 
+
30 typedef struct {
+
31  TOUCH_AREA_STRUCT base;
+
32  uint16_t bgcolor;
+
33  BUTTON_CALLBACK callback;
+
34  uint16_t txtcolor;
+
35  uint8_t font;
+
36  const char *text;
+
37 } BUTTON_STRUCT;
+
38 
+
39 
+
40 #define AUTO 0
+
41 
+
42 
+
47 bool gui_button_add(BUTTON_STRUCT* button);
+
48 
+
53 void gui_button_remove(BUTTON_STRUCT* button);
+
54 
+
59 void gui_button_redraw(BUTTON_STRUCT* button);
+
60 
+
61 /*
+
62 bool guiAddBitmapButton(BITMAPBUTTON_STRUCT* button);
+
63 void guiRemoveBitmapButton(BITMAPBUTTON_STRUCT* button);
+
64 void guiRedrawBitmapButton(BITMAPBUTTON_STRUCT* button);
+
65 */
+
66 
+
67 
+
68 /*
+
69 typedef struct {
+
70  TOUCH_AREA_STRUCT base;
+
71  unsigned int bgcolor;
+
72  BUTTON_CALLBACK callback; //Callback
+
73  unsigned char imgwidth;
+
74  unsigned char imgheight;
+
75  char* filename;
+
76 } BITMAPBUTTON_STRUCT;
+
77 */
+
78 //Notice that the first 3 Members are Equal, so it's possible to cast it to a BUTTON_STRUCT even if it's a BITMAPBUTTON_STRUCT (when changeing only the first 3 Members).
+
79 
+
80 
+
81 
+
84 #endif /* BUTTON_H */
+
BUTTON_STRUCT::text
const char * text
The label of the button.
Definition: button.h:36
+
gui_button_redraw
void gui_button_redraw(BUTTON_STRUCT *button)
Definition: button.c:85
+
BUTTON_STRUCT
Definition: button.h:30
+
gui_button_add
bool gui_button_add(BUTTON_STRUCT *button)
Definition: button.c:62
+
BUTTON_STRUCT::base
TOUCH_AREA_STRUCT base
Basic geometry of the button. You only need to set the x1, y1, x2, y2 members of this struct...
Definition: button.h:31
+
BUTTON_STRUCT::font
uint8_t font
The number of the font to use.
Definition: button.h:35
+
TOUCH_AREA_STRUCT
Definition: touch.h:50
+
BUTTON_STRUCT::txtcolor
uint16_t txtcolor
The 16-bit text color.
Definition: button.h:34
+ +
gui_button_remove
void gui_button_remove(BUTTON_STRUCT *button)
Definition: button.c:122
+
BUTTON_STRUCT::bgcolor
uint16_t bgcolor
The 16-bit background color of the button.
Definition: button.h:32
+
BUTTON_STRUCT::callback
BUTTON_CALLBACK callback
Callback.
Definition: button.h:33
+
BUTTON_CALLBACK
void(* BUTTON_CALLBACK)(void *button)
Definition: button.h:24
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/checkbox_8c.html b/checkbox_8c.html new file mode 100644 index 0000000..e345d2d --- /dev/null +++ b/checkbox_8c.html @@ -0,0 +1,233 @@ + + + + + + +discoverpixy: common/gui/checkbox.c File Reference + + + + + + + + + + +
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discoverpixy +
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+Macros | +Functions
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checkbox.c File Reference
+
+
+
#include "tft.h"
+#include "touch.h"
+#include "checkbox.h"
+#include <stdio.h>
+
+Include dependency graph for checkbox.c:
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+ + +
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+ + + + + + + + + +

+Macros

#define BRIGHTNESS_VAL   2
 
#define ACTIVE_COLOR   RGB(251,208,123)
 
#define BORDER_COLOR   RGB(29,82,129)
 
#define BACKGROUND_COLOR   WHITE
 
+ + + + + + + + + + + +

+Functions

void checkboxes_cb (void *touchArea, TOUCH_ACTION triggeredAction)
 
bool gui_checkbox_add (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_redraw (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_remove (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_update (CHECKBOX_STRUCT *checkbox)
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define ACTIVE_COLOR   RGB(251,208,123)
+
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+ + + + +
#define BACKGROUND_COLOR   WHITE
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#define BORDER_COLOR   RGB(29,82,129)
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#define BRIGHTNESS_VAL   2
+
+ +
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+

Function Documentation

+ +
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+ + + + + + + + + + + + + + + + + + +
void checkboxes_cb (void * touchArea,
TOUCH_ACTION triggeredAction 
)
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Data Structures | +Macros | +Typedefs | +Functions
+
+
checkbox.h File Reference
+
+
+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
+
+

Go to the source code of this file.

+ + + + +

+Data Structures

struct  CHECKBOX_STRUCT
 
+ + + +

+Macros

#define CHECKBOX_WIN_FG_COLOR   RGB(32,161,34)
 
+ + + + +

+Typedefs

typedef void(* CHECKBOX_CALLBACK) (void *checkbox, bool checked)
 Function pointer used... More...
 
+ + + + + + + + + +

+Functions

bool gui_checkbox_add (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_remove (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_update (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_redraw (CHECKBOX_STRUCT *checkbox)
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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common/gui/checkbox.h Source File + + + + + + + + + + +
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checkbox.h
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+Go to the documentation of this file.
1 #ifndef CHECKBOX_H
+
2 #define CHECKBOX_H
+
3 
+
8 
+
14 
+
15 
+
16 typedef void (*CHECKBOX_CALLBACK)(void *checkbox, bool checked);
+
17 typedef struct {
+
18  TOUCH_AREA_STRUCT base;
+
19  uint16_t fgcolor;
+
20  bool checked;
+
21  CHECKBOX_CALLBACK callback; //Callback
+
22 } CHECKBOX_STRUCT;
+
23 
+
24 
+
25 bool gui_checkbox_add(CHECKBOX_STRUCT* checkbox);
+
26 void gui_checkbox_remove(CHECKBOX_STRUCT* checkbox);
+
27 void gui_checkbox_update(CHECKBOX_STRUCT* checkbox);
+
28 void gui_checkbox_redraw(CHECKBOX_STRUCT* checkbox);
+
29 #define CHECKBOX_WIN_FG_COLOR RGB(32,161,34)
+
30 
+
33 #endif /* CHECKBOX_H */
+
gui_checkbox_add
bool gui_checkbox_add(CHECKBOX_STRUCT *checkbox)
Definition: checkbox.c:36
+
gui_checkbox_update
void gui_checkbox_update(CHECKBOX_STRUCT *checkbox)
Definition: checkbox.c:73
+
CHECKBOX_STRUCT::base
TOUCH_AREA_STRUCT base
Definition: checkbox.h:18
+
gui_checkbox_remove
void gui_checkbox_remove(CHECKBOX_STRUCT *checkbox)
Definition: checkbox.c:68
+
TOUCH_AREA_STRUCT
Definition: touch.h:50
+
CHECKBOX_STRUCT::checked
bool checked
Definition: checkbox.h:20
+
CHECKBOX_STRUCT
Definition: checkbox.h:17
+
CHECKBOX_STRUCT::callback
CHECKBOX_CALLBACK callback
Definition: checkbox.h:21
+
CHECKBOX_CALLBACK
void(* CHECKBOX_CALLBACK)(void *checkbox, bool checked)
Function pointer used...
Definition: checkbox.h:16
+
gui_checkbox_redraw
void gui_checkbox_redraw(CHECKBOX_STRUCT *checkbox)
Definition: checkbox.c:60
+
CHECKBOX_STRUCT::fgcolor
uint16_t fgcolor
Definition: checkbox.h:19
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_blobs-members.html b/class_blobs-members.html new file mode 100644 index 0000000..8a06c8e --- /dev/null +++ b/class_blobs-members.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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Blobs Member List
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This is the complete list of members for Blobs, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + +
blobify() (defined in Blobs)Blobs
blobify() (defined in Blobs)Blobs
Blobs(Qqueue *qq, uint8_t *lut) (defined in Blobs)Blobs
Blobs(Qqueue *qq, uint8_t *lut) (defined in Blobs)Blobs
getBlobs(BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen) (defined in Blobs)Blobs
getBlobs(BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen) (defined in Blobs)Blobs
getBlock(uint8_t *buf, uint32_t buflen) (defined in Blobs)Blobs
getBlock(uint8_t *buf, uint32_t buflen) (defined in Blobs)Blobs
getCCBlock(uint8_t *buf, uint32_t buflen) (defined in Blobs)Blobs
getCCBlock(uint8_t *buf, uint32_t buflen) (defined in Blobs)Blobs
getMaxBlob(uint16_t signature=0) (defined in Blobs)Blobs
getMaxBlob(uint16_t signature=0) (defined in Blobs)Blobs
getRunlengths(uint32_t **qvals, uint32_t *len) (defined in Blobs)Blobs
getRunlengths(uint32_t **qvals, uint32_t *len) (defined in Blobs)Blobs
m_clut (defined in Blobs)Blobs
m_qq (defined in Blobs)Blobs
runlengthAnalysis() (defined in Blobs)Blobs
runlengthAnalysis() (defined in Blobs)Blobs
setParams(uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode) (defined in Blobs)Blobs
setParams(uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode) (defined in Blobs)Blobs
~Blobs() (defined in Blobs)Blobs
~Blobs() (defined in Blobs)Blobs
+ +
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+ + diff --git a/class_blobs.html b/class_blobs.html new file mode 100644 index 0000000..f4d29d6 --- /dev/null +++ b/class_blobs.html @@ -0,0 +1,180 @@ + + + + + + +discoverpixy: Blobs Class Reference + + + + + + + + + + +
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+Public Member Functions | +Public Attributes | +List of all members
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Blobs Class Reference
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+Collaboration diagram for Blobs:
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Collaboration graph
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[legend]
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+Public Member Functions

+ Blobs (Qqueue *qq, uint8_t *lut)
 
+int blobify ()
 
+uint16_t getBlock (uint8_t *buf, uint32_t buflen)
 
+uint16_t getCCBlock (uint8_t *buf, uint32_t buflen)
 
+BlobA * getMaxBlob (uint16_t signature=0)
 
+void getBlobs (BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen)
 
+int setParams (uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode)
 
+int runlengthAnalysis ()
 
+void getRunlengths (uint32_t **qvals, uint32_t *len)
 
+ Blobs (Qqueue *qq, uint8_t *lut)
 
+int blobify ()
 
+uint16_t getBlock (uint8_t *buf, uint32_t buflen)
 
+uint16_t getCCBlock (uint8_t *buf, uint32_t buflen)
 
+BlobA * getMaxBlob (uint16_t signature=0)
 
+void getBlobs (BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen)
 
+int setParams (uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode)
 
+int runlengthAnalysis ()
 
+void getRunlengths (uint32_t **qvals, uint32_t *len)
 
+ + + + + +

+Public Attributes

+ColorLUT m_clut
 
+Qqueue * m_qq
 
+
The documentation for this class was generated from the following file: +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_blobs__coll__graph.map b/class_blobs__coll__graph.map new file mode 100644 index 0000000..a75a2fd --- /dev/null +++ b/class_blobs__coll__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/class_blobs__coll__graph.md5 b/class_blobs__coll__graph.md5 new file mode 100644 index 0000000..fb77362 --- /dev/null +++ b/class_blobs__coll__graph.md5 @@ -0,0 +1 @@ +0201c4d7a1346047eb178432e2c0d1d0 \ No newline at end of file diff --git a/class_blobs__coll__graph.png b/class_blobs__coll__graph.png new file mode 100644 index 0000000..971bb2d Binary files /dev/null and b/class_blobs__coll__graph.png differ diff --git a/class_c_blob-members.html b/class_c_blob-members.html new file mode 100644 index 0000000..fce85fa --- /dev/null +++ b/class_c_blob-members.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CBlob Member List
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This is the complete list of members for CBlob, including all inherited members.

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Add(const SSegment &segment) (defined in CBlob)CBlob
Add(const SSegment &segment) (defined in CBlob)CBlob
Assimilate(CBlob &futileResister) (defined in CBlob)CBlob
Assimilate(CBlob &futileResister) (defined in CBlob)CBlob
CBlob() (defined in CBlob)CBlob
CBlob() (defined in CBlob)CBlob
firstSegment (defined in CBlob)CBlob
GetArea() const (defined in CBlob)CBlobinline
GetArea() const (defined in CBlob)CBlobinline
getBBox(short &leftRet, short &topRet, short &rightRet, short &bottomRet) (defined in CBlob)CBlobinline
getBBox(short &leftRet, short &topRet, short &rightRet, short &bottomRet) (defined in CBlob)CBlobinline
lastBottom (defined in CBlob)CBlob
lastSegmentPtr (defined in CBlob)CBlob
leakcheck (defined in CBlob)CBlobstatic
left (defined in CBlob)CBlob
moments (defined in CBlob)CBlob
NewRow() (defined in CBlob)CBlob
NewRow() (defined in CBlob)CBlob
next (defined in CBlob)CBlob
nextBottom (defined in CBlob)CBlob
recordSegments (defined in CBlob)CBlobstatic
Reset() (defined in CBlob)CBlob
Reset() (defined in CBlob)CBlob
right (defined in CBlob)CBlob
testMoments (defined in CBlob)CBlobstatic
top (defined in CBlob)CBlob
UpdateBoundingBox(int newLeft, int newTop, int newRight) (defined in CBlob)CBlob
UpdateBoundingBox(int newLeft, int newTop, int newRight) (defined in CBlob)CBlob
~CBlob() (defined in CBlob)CBlob
~CBlob() (defined in CBlob)CBlob
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_c_blob.html b/class_c_blob.html new file mode 100644 index 0000000..8e55a7d --- /dev/null +++ b/class_c_blob.html @@ -0,0 +1,202 @@ + + + + + + +discoverpixy: CBlob Class Reference + + + + + + + + + + +
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CBlob Class Reference
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+
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Collaboration graph
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+Public Member Functions

+void getBBox (short &leftRet, short &topRet, short &rightRet, short &bottomRet)
 
+int GetArea () const
 
+void Reset ()
 
+void NewRow ()
 
+void Add (const SSegment &segment)
 
+void Assimilate (CBlob &futileResister)
 
+void UpdateBoundingBox (int newLeft, int newTop, int newRight)
 
+void getBBox (short &leftRet, short &topRet, short &rightRet, short &bottomRet)
 
+int GetArea () const
 
+void Reset ()
 
+void NewRow ()
 
+void Add (const SSegment &segment)
 
+void Assimilate (CBlob &futileResister)
 
+void UpdateBoundingBox (int newLeft, int newTop, int newRight)
 
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+CBlob * next
 
+SSegment lastBottom
 
+SSegment nextBottom
 
+short left
 
+short top
 
+short right
 
+SLinkedSegment * firstSegment
 
+SLinkedSegment ** lastSegmentPtr
 
+SMoments moments
 
+ + + + + + + +

+Static Public Attributes

+static int leakcheck
 
+static bool recordSegments
 
+static bool testMoments
 
+
The documentation for this class was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_c_blob__coll__graph.map b/class_c_blob__coll__graph.map new file mode 100644 index 0000000..a4dc225 --- /dev/null +++ b/class_c_blob__coll__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/class_c_blob__coll__graph.md5 b/class_c_blob__coll__graph.md5 new file mode 100644 index 0000000..25749d6 --- /dev/null +++ b/class_c_blob__coll__graph.md5 @@ -0,0 +1 @@ +a0f0e02325ad8208b808cab551c16bc1 \ No newline at end of file diff --git a/class_c_blob__coll__graph.png b/class_c_blob__coll__graph.png new file mode 100644 index 0000000..85eca6d Binary files /dev/null and b/class_c_blob__coll__graph.png differ diff --git a/class_c_blob_assembler-members.html b/class_c_blob_assembler-members.html new file mode 100644 index 0000000..c8e6c9b --- /dev/null +++ b/class_c_blob_assembler-members.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CBlobAssembler Member List
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This is the complete list of members for CBlobAssembler, including all inherited members.

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Add(const SSegment &segment) (defined in CBlobAssembler)CBlobAssembler
Add(const SSegment &segment) (defined in CBlobAssembler)CBlobAssembler
AdvanceCurrent() (defined in CBlobAssembler)CBlobAssemblerprotected
AdvanceCurrent() (defined in CBlobAssembler)CBlobAssemblerprotected
AssertFinishedSorted() (defined in CBlobAssembler)CBlobAssembler
AssertFinishedSorted() (defined in CBlobAssembler)CBlobAssembler
BlobNewRow(CBlob **ptr) (defined in CBlobAssembler)CBlobAssemblerprotected
BlobNewRow(CBlob **ptr) (defined in CBlobAssembler)CBlobAssemblerprotected
CBlobAssembler() (defined in CBlobAssembler)CBlobAssembler
CBlobAssembler() (defined in CBlobAssembler)CBlobAssembler
EndFrame() (defined in CBlobAssembler)CBlobAssembler
EndFrame() (defined in CBlobAssembler)CBlobAssembler
finishedBlobs (defined in CBlobAssembler)CBlobAssembler
keepFinishedSorted (defined in CBlobAssembler)CBlobAssemblerstatic
ListLength(const CBlob *b) (defined in CBlobAssembler)CBlobAssembler
ListLength(const CBlob *b) (defined in CBlobAssembler)CBlobAssembler
m_blobCount (defined in CBlobAssembler)CBlobAssemblerprotected
maxRowDelta (defined in CBlobAssembler)CBlobAssembler
MergeLists(CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts) (defined in CBlobAssembler)CBlobAssembler
MergeLists(CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts) (defined in CBlobAssembler)CBlobAssembler
Reset() (defined in CBlobAssembler)CBlobAssembler
Reset() (defined in CBlobAssembler)CBlobAssembler
RewindCurrent() (defined in CBlobAssembler)CBlobAssemblerprotected
RewindCurrent() (defined in CBlobAssembler)CBlobAssemblerprotected
SortFinished() (defined in CBlobAssembler)CBlobAssembler
SortFinished() (defined in CBlobAssembler)CBlobAssembler
SplitList(CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf) (defined in CBlobAssembler)CBlobAssembler
SplitList(CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf) (defined in CBlobAssembler)CBlobAssembler
~CBlobAssembler() (defined in CBlobAssembler)CBlobAssembler
~CBlobAssembler() (defined in CBlobAssembler)CBlobAssembler
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_c_blob_assembler.html b/class_c_blob_assembler.html new file mode 100644 index 0000000..9f21976 --- /dev/null +++ b/class_c_blob_assembler.html @@ -0,0 +1,210 @@ + + + + + + +discoverpixy: CBlobAssembler Class Reference + + + + + + + + + + +
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+Public Member Functions | +Public Attributes | +Static Public Attributes | +Protected Member Functions | +Protected Attributes | +List of all members
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CBlobAssembler Class Reference
+
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+Collaboration diagram for CBlobAssembler:
+
+
Collaboration graph
+ + +
[legend]
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+Public Member Functions

+void Reset ()
 
+int Add (const SSegment &segment)
 
+void EndFrame ()
 
+int ListLength (const CBlob *b)
 
+void SplitList (CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf)
 
+void MergeLists (CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts)
 
+void SortFinished ()
 
+void AssertFinishedSorted ()
 
+void Reset ()
 
+int Add (const SSegment &segment)
 
+void EndFrame ()
 
+int ListLength (const CBlob *b)
 
+void SplitList (CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf)
 
+void MergeLists (CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts)
 
+void SortFinished ()
 
+void AssertFinishedSorted ()
 
+ + + + + +

+Public Attributes

+CBlob * finishedBlobs
 
+short maxRowDelta
 
+ + + +

+Static Public Attributes

+static bool keepFinishedSorted
 
+ + + + + + + + + + + + + +

+Protected Member Functions

+void BlobNewRow (CBlob **ptr)
 
+void RewindCurrent ()
 
+void AdvanceCurrent ()
 
+void BlobNewRow (CBlob **ptr)
 
+void RewindCurrent ()
 
+void AdvanceCurrent ()
 
+ + + +

+Protected Attributes

+int m_blobCount
 
+
The documentation for this class was generated from the following file: +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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Chirp Member List
+
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+ +

This is the complete list of members for Chirp, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
assemble(uint8_t type,...) (defined in Chirp)Chirp
assemble(uint8_t type,...) (defined in Chirp)Chirp
calcCrc(uint8_t *buf, uint32_t len) (defined in Chirp)Chirpstatic
calcCrc(uint8_t *buf, uint32_t len) (defined in Chirp)Chirpstatic
call(uint8_t service, ChirpProc proc,...) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc, va_list args) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc,...) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc, va_list args) (defined in Chirp)Chirp
Chirp(bool hinterested=false, bool client=false, Link *link=NULL) (defined in Chirp)Chirp
Chirp(bool hinterested=false, bool client=false, Link *link=NULL) (defined in Chirp)Chirp
connected() (defined in Chirp)Chirp
connected() (defined in Chirp)Chirp
deserialize(uint8_t *buf, uint32_t len,...) (defined in Chirp)Chirpstatic
deserialize(uint8_t *buf, uint32_t len,...) (defined in Chirp)Chirpstatic
deserializeParse(uint8_t *buf, uint32_t len, void *args[]) (defined in Chirp)Chirpstatic
deserializeParse(uint8_t *buf, uint32_t len, void *args[]) (defined in Chirp)Chirpstatic
getArgList(uint8_t *buf, uint32_t len, uint8_t *argList) (defined in Chirp)Chirpstatic
getArgList(uint8_t *buf, uint32_t len, uint8_t *argList) (defined in Chirp)Chirpstatic
getProc(const char *procName, ProcPtr callback=0) (defined in Chirp)Chirp
getProc(const char *procName, ProcPtr callback=0) (defined in Chirp)Chirp
getProcInfo(ChirpProc proc, ProcInfo *info) (defined in Chirp)Chirp
getProcInfo(ChirpProc proc, ProcInfo *info) (defined in Chirp)Chirp
getType(const void *arg) (defined in Chirp)Chirpstatic
getType(const void *arg) (defined in Chirp)Chirpstatic
handleChirp(uint8_t type, ChirpProc proc, const void *args[]) (defined in Chirp)Chirpprotectedvirtual
handleChirp(uint8_t type, ChirpProc proc, const void *args[]) (defined in Chirp)Chirpprotectedvirtual
handleXdata(const void *data[]) (defined in Chirp)Chirpinlineprotectedvirtual
handleXdata(const void *data[]) (defined in Chirp)Chirpinlineprotectedvirtual
init(bool connect) (defined in Chirp)Chirpvirtual
init(bool connect) (defined in Chirp)Chirpvirtual
loadArgs(va_list *args, void *recvArgs[]) (defined in Chirp)Chirpstatic
loadArgs(va_list *args, void *recvArgs[]) (defined in Chirp)Chirpstatic
m_buf (defined in Chirp)Chirpprotected
m_bufSave (defined in Chirp)Chirpprotected
m_bufSize (defined in Chirp)Chirpprotected
m_client (defined in Chirp)Chirpprotected
m_dataTimeout (defined in Chirp)Chirpprotected
m_errorCorrected (defined in Chirp)Chirpprotected
m_headerLen (defined in Chirp)Chirpprotected
m_headerTimeout (defined in Chirp)Chirpprotected
m_hinformer (defined in Chirp)Chirpprotected
m_hinterested (defined in Chirp)Chirpprotected
m_idleTimeout (defined in Chirp)Chirpprotected
m_len (defined in Chirp)Chirpprotected
m_offset (defined in Chirp)Chirpprotected
m_sendTimeout (defined in Chirp)Chirpprotected
m_sharedMem (defined in Chirp)Chirpprotected
recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false) (defined in Chirp)Chirpprotected
recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false) (defined in Chirp)Chirpprotected
registerModule(const ProcModule *module) (defined in Chirp)Chirp
registerModule(const ProcModule *module) (defined in Chirp)Chirp
remoteInit(bool connect) (defined in Chirp)Chirpprotected
remoteInit(bool connect) (defined in Chirp)Chirpprotected
sendChirp(uint8_t type, ChirpProc proc) (defined in Chirp)Chirpprotectedvirtual
sendChirp(uint8_t type, ChirpProc proc) (defined in Chirp)Chirpprotectedvirtual
serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize,...) (defined in Chirp)Chirpstatic
serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize,...) (defined in Chirp)Chirpstatic
service(bool all=true) (defined in Chirp)Chirp
service(bool all=true) (defined in Chirp)Chirp
setLink(Link *link) (defined in Chirp)Chirp
setLink(Link *link) (defined in Chirp)Chirp
setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL) (defined in Chirp)Chirp
setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL) (defined in Chirp)Chirp
setRecvTimeout(uint32_t timeout) (defined in Chirp)Chirp
setRecvTimeout(uint32_t timeout) (defined in Chirp)Chirp
setSendTimeout(uint32_t timeout) (defined in Chirp)Chirp
setSendTimeout(uint32_t timeout) (defined in Chirp)Chirp
useBuffer(uint8_t *buf, uint32_t len) (defined in Chirp)Chirp
useBuffer(uint8_t *buf, uint32_t len) (defined in Chirp)Chirp
vdeserialize(uint8_t *buf, uint32_t len, va_list *args) (defined in Chirp)Chirpstatic
vdeserialize(uint8_t *buf, uint32_t len, va_list *args) (defined in Chirp)Chirpstatic
vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args) (defined in Chirp)Chirpstatic
vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args) (defined in Chirp)Chirpstatic
~Chirp() (defined in Chirp)Chirp
~Chirp() (defined in Chirp)Chirp
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_chirp.html b/class_chirp.html new file mode 100644 index 0000000..7a64225 --- /dev/null +++ b/class_chirp.html @@ -0,0 +1,348 @@ + + + + + + +discoverpixy: Chirp Class Reference + + + + + + + + + + +
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+Public Member Functions | +Static Public Member Functions | +Protected Member Functions | +Protected Attributes | +List of all members
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Chirp Class Reference
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+Inheritance diagram for Chirp:
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Inheritance graph
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+Public Member Functions

+ Chirp (bool hinterested=false, bool client=false, Link *link=NULL)
 
+virtual int init (bool connect)
 
+int setLink (Link *link)
 
+ChirpProc getProc (const char *procName, ProcPtr callback=0)
 
+int setProc (const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL)
 
+int getProcInfo (ChirpProc proc, ProcInfo *info)
 
+int registerModule (const ProcModule *module)
 
+void setSendTimeout (uint32_t timeout)
 
+void setRecvTimeout (uint32_t timeout)
 
+int call (uint8_t service, ChirpProc proc,...)
 
+int call (uint8_t service, ChirpProc proc, va_list args)
 
+int service (bool all=true)
 
+int assemble (uint8_t type,...)
 
+bool connected ()
 
+int useBuffer (uint8_t *buf, uint32_t len)
 
+ Chirp (bool hinterested=false, bool client=false, Link *link=NULL)
 
+virtual int init (bool connect)
 
+int setLink (Link *link)
 
+ChirpProc getProc (const char *procName, ProcPtr callback=0)
 
+int setProc (const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL)
 
+int getProcInfo (ChirpProc proc, ProcInfo *info)
 
+int registerModule (const ProcModule *module)
 
+void setSendTimeout (uint32_t timeout)
 
+void setRecvTimeout (uint32_t timeout)
 
+int call (uint8_t service, ChirpProc proc,...)
 
+int call (uint8_t service, ChirpProc proc, va_list args)
 
+int service (bool all=true)
 
+int assemble (uint8_t type,...)
 
+bool connected ()
 
+int useBuffer (uint8_t *buf, uint32_t len)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Static Public Member Functions

+static uint8_t getType (const void *arg)
 
+static int serialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize,...)
 
+static int deserialize (uint8_t *buf, uint32_t len,...)
 
+static int vserialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args)
 
+static int vdeserialize (uint8_t *buf, uint32_t len, va_list *args)
 
+static int deserializeParse (uint8_t *buf, uint32_t len, void *args[])
 
+static int loadArgs (va_list *args, void *recvArgs[])
 
+static int getArgList (uint8_t *buf, uint32_t len, uint8_t *argList)
 
+static uint16_t calcCrc (uint8_t *buf, uint32_t len)
 
+static uint8_t getType (const void *arg)
 
+static int serialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize,...)
 
+static int deserialize (uint8_t *buf, uint32_t len,...)
 
+static int vserialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args)
 
+static int vdeserialize (uint8_t *buf, uint32_t len, va_list *args)
 
+static int deserializeParse (uint8_t *buf, uint32_t len, void *args[])
 
+static int loadArgs (va_list *args, void *recvArgs[])
 
+static int getArgList (uint8_t *buf, uint32_t len, uint8_t *argList)
 
+static uint16_t calcCrc (uint8_t *buf, uint32_t len)
 
+ + + + + + + + + + + + + + + + + + + + + +

+Protected Member Functions

+int remoteInit (bool connect)
 
+int recvChirp (uint8_t *type, ChirpProc *proc, void *args[], bool wait=false)
 
+virtual int handleChirp (uint8_t type, ChirpProc proc, const void *args[])
 
+virtual void handleXdata (const void *data[])
 
+virtual int sendChirp (uint8_t type, ChirpProc proc)
 
+int remoteInit (bool connect)
 
+int recvChirp (uint8_t *type, ChirpProc *proc, void *args[], bool wait=false)
 
+virtual int handleChirp (uint8_t type, ChirpProc proc, const void *args[])
 
+virtual void handleXdata (const void *data[])
 
+virtual int sendChirp (uint8_t type, ChirpProc proc)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Attributes

+uint8_t * m_buf
 
+uint8_t * m_bufSave
 
+uint32_t m_len
 
+uint32_t m_offset
 
+uint32_t m_bufSize
 
+bool m_errorCorrected
 
+bool m_sharedMem
 
+bool m_hinformer
 
+bool m_hinterested
 
+bool m_client
 
+uint32_t m_headerLen
 
+uint16_t m_headerTimeout
 
+uint16_t m_dataTimeout
 
+uint16_t m_idleTimeout
 
+uint16_t m_sendTimeout
 
+
The documentation for this class was generated from the following files: +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_chirp__inherit__graph.map b/class_chirp__inherit__graph.map new file mode 100644 index 0000000..76f4ac2 --- /dev/null +++ b/class_chirp__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_chirp__inherit__graph.md5 b/class_chirp__inherit__graph.md5 new file mode 100644 index 0000000..0a4e40f --- /dev/null +++ b/class_chirp__inherit__graph.md5 @@ -0,0 +1 @@ +f728a5d57af5e94b87072962251a9006 \ No newline at end of file diff --git a/class_chirp__inherit__graph.png b/class_chirp__inherit__graph.png new file mode 100644 index 0000000..fa3430a Binary files /dev/null and b/class_chirp__inherit__graph.png differ diff --git a/class_chirp_receiver-members.html b/class_chirp_receiver-members.html new file mode 100644 index 0000000..dc5c32c --- /dev/null +++ b/class_chirp_receiver-members.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ChirpReceiver Member List
+
+
+ +

This is the complete list of members for ChirpReceiver, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
assemble(uint8_t type,...) (defined in Chirp)Chirp
assemble(uint8_t type,...) (defined in Chirp)Chirp
calcCrc(uint8_t *buf, uint32_t len) (defined in Chirp)Chirpstatic
calcCrc(uint8_t *buf, uint32_t len) (defined in Chirp)Chirpstatic
call(uint8_t service, ChirpProc proc,...) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc, va_list args) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc,...) (defined in Chirp)Chirp
call(uint8_t service, ChirpProc proc, va_list args) (defined in Chirp)Chirp
Chirp(bool hinterested=false, bool client=false, Link *link=NULL) (defined in Chirp)Chirp
Chirp(bool hinterested=false, bool client=false, Link *link=NULL) (defined in Chirp)Chirp
ChirpReceiver(USBLink *link, Interpreter *interpreter) (defined in ChirpReceiver)ChirpReceiver
ChirpReceiver(USBLink *link, Interpreter *interpreter) (defined in ChirpReceiver)ChirpReceiver
connected() (defined in Chirp)Chirp
connected() (defined in Chirp)Chirp
deserialize(uint8_t *buf, uint32_t len,...) (defined in Chirp)Chirpstatic
deserialize(uint8_t *buf, uint32_t len,...) (defined in Chirp)Chirpstatic
deserializeParse(uint8_t *buf, uint32_t len, void *args[]) (defined in Chirp)Chirpstatic
deserializeParse(uint8_t *buf, uint32_t len, void *args[]) (defined in Chirp)Chirpstatic
getArgList(uint8_t *buf, uint32_t len, uint8_t *argList) (defined in Chirp)Chirpstatic
getArgList(uint8_t *buf, uint32_t len, uint8_t *argList) (defined in Chirp)Chirpstatic
getProc(const char *procName, ProcPtr callback=0) (defined in Chirp)Chirp
getProc(const char *procName, ProcPtr callback=0) (defined in Chirp)Chirp
getProcInfo(ChirpProc proc, ProcInfo *info) (defined in Chirp)Chirp
getProcInfo(ChirpProc proc, ProcInfo *info) (defined in Chirp)Chirp
getType(const void *arg) (defined in Chirp)Chirpstatic
getType(const void *arg) (defined in Chirp)Chirpstatic
handleChirp(uint8_t type, ChirpProc proc, const void *args[]) (defined in Chirp)Chirpprotectedvirtual
handleChirp(uint8_t type, ChirpProc proc, const void *args[]) (defined in Chirp)Chirpprotectedvirtual
init(bool connect) (defined in Chirp)Chirpvirtual
init(bool connect) (defined in Chirp)Chirpvirtual
loadArgs(va_list *args, void *recvArgs[]) (defined in Chirp)Chirpstatic
loadArgs(va_list *args, void *recvArgs[]) (defined in Chirp)Chirpstatic
m_buf (defined in Chirp)Chirpprotected
m_bufSave (defined in Chirp)Chirpprotected
m_bufSize (defined in Chirp)Chirpprotected
m_client (defined in Chirp)Chirpprotected
m_dataTimeout (defined in Chirp)Chirpprotected
m_errorCorrected (defined in Chirp)Chirpprotected
m_headerLen (defined in Chirp)Chirpprotected
m_headerTimeout (defined in Chirp)Chirpprotected
m_hinformer (defined in Chirp)Chirpprotected
m_hinterested (defined in Chirp)Chirpprotected
m_idleTimeout (defined in Chirp)Chirpprotected
m_len (defined in Chirp)Chirpprotected
m_offset (defined in Chirp)Chirpprotected
m_sendTimeout (defined in Chirp)Chirpprotected
m_sharedMem (defined in Chirp)Chirpprotected
recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false) (defined in Chirp)Chirpprotected
recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false) (defined in Chirp)Chirpprotected
registerModule(const ProcModule *module) (defined in Chirp)Chirp
registerModule(const ProcModule *module) (defined in Chirp)Chirp
remoteInit(bool connect) (defined in Chirp)Chirpprotected
remoteInit(bool connect) (defined in Chirp)Chirpprotected
sendChirp(uint8_t type, ChirpProc proc) (defined in Chirp)Chirpprotectedvirtual
sendChirp(uint8_t type, ChirpProc proc) (defined in Chirp)Chirpprotectedvirtual
serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize,...) (defined in Chirp)Chirpstatic
serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize,...) (defined in Chirp)Chirpstatic
service(bool all=true) (defined in Chirp)Chirp
service(bool all=true) (defined in Chirp)Chirp
setLink(Link *link) (defined in Chirp)Chirp
setLink(Link *link) (defined in Chirp)Chirp
setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL) (defined in Chirp)Chirp
setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL) (defined in Chirp)Chirp
setRecvTimeout(uint32_t timeout) (defined in Chirp)Chirp
setRecvTimeout(uint32_t timeout) (defined in Chirp)Chirp
setSendTimeout(uint32_t timeout) (defined in Chirp)Chirp
setSendTimeout(uint32_t timeout) (defined in Chirp)Chirp
useBuffer(uint8_t *buf, uint32_t len) (defined in Chirp)Chirp
useBuffer(uint8_t *buf, uint32_t len) (defined in Chirp)Chirp
vdeserialize(uint8_t *buf, uint32_t len, va_list *args) (defined in Chirp)Chirpstatic
vdeserialize(uint8_t *buf, uint32_t len, va_list *args) (defined in Chirp)Chirpstatic
vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args) (defined in Chirp)Chirpstatic
vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args) (defined in Chirp)Chirpstatic
~Chirp() (defined in Chirp)Chirp
~Chirp() (defined in Chirp)Chirp
~ChirpReceiver() (defined in ChirpReceiver)ChirpReceivervirtual
~ChirpReceiver() (defined in ChirpReceiver)ChirpReceivervirtual
+ +
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+ + diff --git a/class_chirp_receiver.html b/class_chirp_receiver.html new file mode 100644 index 0000000..d65cc93 --- /dev/null +++ b/class_chirp_receiver.html @@ -0,0 +1,350 @@ + + + + + + +discoverpixy: ChirpReceiver Class Reference + + + + + + + + + + +
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+Public Member Functions | +List of all members
+
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ChirpReceiver Class Reference
+
+
+
+Inheritance diagram for ChirpReceiver:
+
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Inheritance graph
+ + +
[legend]
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+Collaboration diagram for ChirpReceiver:
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Collaboration graph
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+Public Member Functions

+ ChirpReceiver (USBLink *link, Interpreter *interpreter)
 
+ ChirpReceiver (USBLink *link, Interpreter *interpreter)
 
- Public Member Functions inherited from Chirp
+ Chirp (bool hinterested=false, bool client=false, Link *link=NULL)
 
+virtual int init (bool connect)
 
+int setLink (Link *link)
 
+ChirpProc getProc (const char *procName, ProcPtr callback=0)
 
+int setProc (const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL)
 
+int getProcInfo (ChirpProc proc, ProcInfo *info)
 
+int registerModule (const ProcModule *module)
 
+void setSendTimeout (uint32_t timeout)
 
+void setRecvTimeout (uint32_t timeout)
 
+int call (uint8_t service, ChirpProc proc,...)
 
+int call (uint8_t service, ChirpProc proc, va_list args)
 
+int service (bool all=true)
 
+int assemble (uint8_t type,...)
 
+bool connected ()
 
+int useBuffer (uint8_t *buf, uint32_t len)
 
+ Chirp (bool hinterested=false, bool client=false, Link *link=NULL)
 
+virtual int init (bool connect)
 
+int setLink (Link *link)
 
+ChirpProc getProc (const char *procName, ProcPtr callback=0)
 
+int setProc (const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL)
 
+int getProcInfo (ChirpProc proc, ProcInfo *info)
 
+int registerModule (const ProcModule *module)
 
+void setSendTimeout (uint32_t timeout)
 
+void setRecvTimeout (uint32_t timeout)
 
+int call (uint8_t service, ChirpProc proc,...)
 
+int call (uint8_t service, ChirpProc proc, va_list args)
 
+int service (bool all=true)
 
+int assemble (uint8_t type,...)
 
+bool connected ()
 
+int useBuffer (uint8_t *buf, uint32_t len)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Static Public Member Functions inherited from Chirp
+static uint8_t getType (const void *arg)
 
+static int serialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize,...)
 
+static int deserialize (uint8_t *buf, uint32_t len,...)
 
+static int vserialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args)
 
+static int vdeserialize (uint8_t *buf, uint32_t len, va_list *args)
 
+static int deserializeParse (uint8_t *buf, uint32_t len, void *args[])
 
+static int loadArgs (va_list *args, void *recvArgs[])
 
+static int getArgList (uint8_t *buf, uint32_t len, uint8_t *argList)
 
+static uint16_t calcCrc (uint8_t *buf, uint32_t len)
 
+static uint8_t getType (const void *arg)
 
+static int serialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize,...)
 
+static int deserialize (uint8_t *buf, uint32_t len,...)
 
+static int vserialize (Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args)
 
+static int vdeserialize (uint8_t *buf, uint32_t len, va_list *args)
 
+static int deserializeParse (uint8_t *buf, uint32_t len, void *args[])
 
+static int loadArgs (va_list *args, void *recvArgs[])
 
+static int getArgList (uint8_t *buf, uint32_t len, uint8_t *argList)
 
+static uint16_t calcCrc (uint8_t *buf, uint32_t len)
 
- Protected Member Functions inherited from Chirp
+int remoteInit (bool connect)
 
+int recvChirp (uint8_t *type, ChirpProc *proc, void *args[], bool wait=false)
 
+virtual int handleChirp (uint8_t type, ChirpProc proc, const void *args[])
 
+virtual int sendChirp (uint8_t type, ChirpProc proc)
 
+int remoteInit (bool connect)
 
+int recvChirp (uint8_t *type, ChirpProc *proc, void *args[], bool wait=false)
 
+virtual int handleChirp (uint8_t type, ChirpProc proc, const void *args[])
 
+virtual int sendChirp (uint8_t type, ChirpProc proc)
 
- Protected Attributes inherited from Chirp
+uint8_t * m_buf
 
+uint8_t * m_bufSave
 
+uint32_t m_len
 
+uint32_t m_offset
 
+uint32_t m_bufSize
 
+bool m_errorCorrected
 
+bool m_sharedMem
 
+bool m_hinformer
 
+bool m_hinterested
 
+bool m_client
 
+uint32_t m_headerLen
 
+uint16_t m_headerTimeout
 
+uint16_t m_dataTimeout
 
+uint16_t m_idleTimeout
 
+uint16_t m_sendTimeout
 
+
The documentation for this class was generated from the following files: +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_chirp_receiver__coll__graph.map b/class_chirp_receiver__coll__graph.map new file mode 100644 index 0000000..2823592 --- /dev/null +++ b/class_chirp_receiver__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_chirp_receiver__coll__graph.md5 b/class_chirp_receiver__coll__graph.md5 new file mode 100644 index 0000000..6b94963 --- /dev/null +++ b/class_chirp_receiver__coll__graph.md5 @@ -0,0 +1 @@ +18d1a08025741b0bbd1a659652184729 \ No newline at end of file diff --git a/class_chirp_receiver__coll__graph.png b/class_chirp_receiver__coll__graph.png new file mode 100644 index 0000000..11aeadf Binary files /dev/null and b/class_chirp_receiver__coll__graph.png differ diff --git a/class_chirp_receiver__inherit__graph.map b/class_chirp_receiver__inherit__graph.map new file mode 100644 index 0000000..2823592 --- /dev/null +++ b/class_chirp_receiver__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_chirp_receiver__inherit__graph.md5 b/class_chirp_receiver__inherit__graph.md5 new file mode 100644 index 0000000..6b94963 --- /dev/null +++ b/class_chirp_receiver__inherit__graph.md5 @@ -0,0 +1 @@ +18d1a08025741b0bbd1a659652184729 \ No newline at end of file diff --git a/class_chirp_receiver__inherit__graph.png b/class_chirp_receiver__inherit__graph.png new file mode 100644 index 0000000..11aeadf Binary files /dev/null and b/class_chirp_receiver__inherit__graph.png differ diff --git a/class_color_l_u_t-members.html b/class_color_l_u_t-members.html new file mode 100644 index 0000000..56c5a94 --- /dev/null +++ b/class_color_l_u_t-members.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ColorLUT Member List
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clearLUT(uint8_t signum=0) (defined in ColorLUT)ColorLUT
clearLUT(uint8_t signum=0) (defined in ColorLUT)ColorLUT
ColorLUT(uint8_t *lut) (defined in ColorLUT)ColorLUT
ColorLUT(uint8_t *lut) (defined in ColorLUT)ColorLUT
generateLUT() (defined in ColorLUT)ColorLUT
generateLUT() (defined in ColorLUT)ColorLUT
generateSignature(const Frame8 &frame, const RectA &region, uint8_t signum) (defined in ColorLUT)ColorLUT
generateSignature(const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum) (defined in ColorLUT)ColorLUT
generateSignature(const Frame8 &frame, const RectA &region, uint8_t signum) (defined in ColorLUT)ColorLUT
generateSignature(const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum) (defined in ColorLUT)ColorLUT
getSignature(uint8_t signum) (defined in ColorLUT)ColorLUT
getSignature(uint8_t signum) (defined in ColorLUT)ColorLUT
getType(uint8_t signum) (defined in ColorLUT)ColorLUT
getType(uint8_t signum) (defined in ColorLUT)ColorLUT
growRegion(const Frame8 &frame, const Point16 &seed, Points *points) (defined in ColorLUT)ColorLUT
growRegion(const Frame8 &frame, const Point16 &seed, Points *points) (defined in ColorLUT)ColorLUT
m_miny (defined in ColorLUT)ColorLUT
m_runtimeSigs (defined in ColorLUT)ColorLUT
m_signatures (defined in ColorLUT)ColorLUT
setCCGain(float gain) (defined in ColorLUT)ColorLUT
setCCGain(float gain) (defined in ColorLUT)ColorLUT
setGrowDist(uint32_t dist) (defined in ColorLUT)ColorLUT
setGrowDist(uint32_t dist) (defined in ColorLUT)ColorLUT
setMinBrightness(float miny) (defined in ColorLUT)ColorLUT
setMinBrightness(float miny) (defined in ColorLUT)ColorLUT
setSignature(uint8_t signum, const ColorSignature &sig) (defined in ColorLUT)ColorLUT
setSignature(uint8_t signum, const ColorSignature &sig) (defined in ColorLUT)ColorLUT
setSigRange(uint8_t signum, float range) (defined in ColorLUT)ColorLUT
setSigRange(uint8_t signum, float range) (defined in ColorLUT)ColorLUT
updateSignature(uint8_t signum) (defined in ColorLUT)ColorLUT
updateSignature(uint8_t signum) (defined in ColorLUT)ColorLUT
~ColorLUT() (defined in ColorLUT)ColorLUT
~ColorLUT() (defined in ColorLUT)ColorLUT
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ColorLUT Class Reference
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+Public Member Functions

+ ColorLUT (uint8_t *lut)
 
+int generateSignature (const Frame8 &frame, const RectA &region, uint8_t signum)
 
+int generateSignature (const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum)
 
+ColorSignature * getSignature (uint8_t signum)
 
+int setSignature (uint8_t signum, const ColorSignature &sig)
 
+int generateLUT ()
 
+void clearLUT (uint8_t signum=0)
 
+void updateSignature (uint8_t signum)
 
+void growRegion (const Frame8 &frame, const Point16 &seed, Points *points)
 
+void setSigRange (uint8_t signum, float range)
 
+void setMinBrightness (float miny)
 
+void setGrowDist (uint32_t dist)
 
+void setCCGain (float gain)
 
+uint32_t getType (uint8_t signum)
 
+ ColorLUT (uint8_t *lut)
 
+int generateSignature (const Frame8 &frame, const RectA &region, uint8_t signum)
 
+int generateSignature (const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum)
 
+ColorSignature * getSignature (uint8_t signum)
 
+int setSignature (uint8_t signum, const ColorSignature &sig)
 
+int generateLUT ()
 
+void clearLUT (uint8_t signum=0)
 
+void updateSignature (uint8_t signum)
 
+void growRegion (const Frame8 &frame, const Point16 &seed, Points *points)
 
+void setSigRange (uint8_t signum, float range)
 
+void setMinBrightness (float miny)
 
+void setGrowDist (uint32_t dist)
 
+void setCCGain (float gain)
 
+uint32_t getType (uint8_t signum)
 
+ + + + + + + +

+Public Attributes

+ColorSignature m_signatures [CL_NUM_SIGNATURES]
 
+RuntimeSignature m_runtimeSigs [CL_NUM_SIGNATURES]
 
+uint32_t m_miny
 
+
The documentation for this class was generated from the following file: +
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Interpreter Member List
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interpret_data(const void *data[])=0 (defined in Interpreter)Interpreterpure virtual
interpret_data(const void *data[])=0 (defined in Interpreter)Interpreterpure virtual
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Interpreter Class Referenceabstract
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+virtual void interpret_data (const void *data[])=0
 
+virtual void interpret_data (const void *data[])=0
 
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IterPixel Member List
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This is the complete list of members for IterPixel, including all inherited members.

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averageRgb(uint32_t *pixels=NULL) (defined in IterPixel)IterPixel
averageRgb(uint32_t *pixels=NULL) (defined in IterPixel)IterPixel
IterPixel(const Frame8 &frame, const RectA &region) (defined in IterPixel)IterPixel
IterPixel(const Frame8 &frame, const Points *points) (defined in IterPixel)IterPixel
IterPixel(const Frame8 &frame, const RectA &region) (defined in IterPixel)IterPixel
IterPixel(const Frame8 &frame, const Points *points) (defined in IterPixel)IterPixel
next(UVPixel *uv, RGBPixel *rgb=NULL) (defined in IterPixel)IterPixel
next(UVPixel *uv, RGBPixel *rgb=NULL) (defined in IterPixel)IterPixel
reset(bool cleari=true) (defined in IterPixel)IterPixel
reset(bool cleari=true) (defined in IterPixel)IterPixel
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+ IterPixel (const Frame8 &frame, const RectA &region)
 
+ IterPixel (const Frame8 &frame, const Points *points)
 
+bool next (UVPixel *uv, RGBPixel *rgb=NULL)
 
+bool reset (bool cleari=true)
 
+uint32_t averageRgb (uint32_t *pixels=NULL)
 
+ IterPixel (const Frame8 &frame, const RectA &region)
 
+ IterPixel (const Frame8 &frame, const Points *points)
 
+bool next (UVPixel *uv, RGBPixel *rgb=NULL)
 
+bool reset (bool cleari=true)
 
+uint32_t averageRgb (uint32_t *pixels=NULL)
 
+
The documentation for this class was generated from the following file: +
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Link Member List
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blockSize() (defined in Link)Linkinlinevirtual
blockSize() (defined in Link)Linkinlinevirtual
getBuffer(uint8_t **, uint32_t *) (defined in Link)Linkinlinevirtual
getBuffer(uint8_t **, uint32_t *) (defined in Link)Linkinlinevirtual
getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS) (defined in Link)Linkinlinevirtual
getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS) (defined in Link)Linkinlinevirtual
getTimer()=0 (defined in Link)Linkpure virtual
getTimer()=0 (defined in Link)Linkpure virtual
Link() (defined in Link)Linkinline
Link() (defined in Link)Linkinline
m_blockSize (defined in Link)Linkprotected
m_flags (defined in Link)Linkprotected
receive(uint8_t *data, uint32_t len, uint16_t timeoutMs)=0 (defined in Link)Linkpure virtual
receive(uint8_t *data, uint32_t len, uint16_t timeoutMs)=0 (defined in Link)Linkpure virtual
send(const uint8_t *data, uint32_t len, uint16_t timeoutMs)=0 (defined in Link)Linkpure virtual
send(const uint8_t *data, uint32_t len, uint16_t timeoutMs)=0 (defined in Link)Linkpure virtual
setTimer()=0 (defined in Link)Linkpure virtual
setTimer()=0 (defined in Link)Linkpure virtual
~Link() (defined in Link)Linkinline
~Link() (defined in Link)Linkinline
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Link Class Referenceabstract
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+Public Member Functions

+virtual int send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)=0
 
+virtual int receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)=0
 
+virtual void setTimer ()=0
 
+virtual uint32_t getTimer ()=0
 
+virtual uint32_t getFlags (uint8_t index=LINK_FLAG_INDEX_FLAGS)
 
+virtual uint32_t blockSize ()
 
+virtual int getBuffer (uint8_t **, uint32_t *)
 
+virtual int send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)=0
 
+virtual int receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)=0
 
+virtual void setTimer ()=0
 
+virtual uint32_t getTimer ()=0
 
+virtual uint32_t getFlags (uint8_t index=LINK_FLAG_INDEX_FLAGS)
 
+virtual uint32_t blockSize ()
 
+virtual int getBuffer (uint8_t **, uint32_t *)
 
+ + + + + +

+Protected Attributes

+uint32_t m_flags
 
+uint32_t m_blockSize
 
+
The documentation for this class was generated from the following file: +
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clear(uint16_t color) (defined in MainWindow)MainWindow
draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat) (defined in MainWindow)MainWindow
draw_char(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, QFont font, char c) (defined in MainWindow)MainWindow
draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color) (defined in MainWindow)MainWindow
draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color) (defined in MainWindow)MainWindow
draw_pixel(uint16_t x, uint16_t y, uint16_t color) (defined in MainWindow)MainWindow
draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color) (defined in MainWindow)MainWindow
fill_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color) (defined in MainWindow)MainWindow
MainWindow(QWidget *parent=0) (defined in MainWindow)MainWindowexplicit
mouseMoveEvent(QMouseEvent *evt) (defined in MainWindow)MainWindowprotected
mousePressEvent(QMouseEvent *evt) (defined in MainWindow)MainWindowprotected
mouseReleaseEvent(QMouseEvent *evt) (defined in MainWindow)MainWindowprotected
paintEvent(QPaintEvent *evt) (defined in MainWindow)MainWindowprotected
~MainWindow() (defined in MainWindow)MainWindowprotected
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MainWindow Class Reference
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#include <mainwindow.h>

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 MainWindow (QWidget *parent=0)
 
void draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void clear (uint16_t color)
 
void draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
void draw_char (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, QFont font, char c)
 
+ + + + + + + + + + + +

+Protected Member Functions

void paintEvent (QPaintEvent *evt)
 
void mousePressEvent (QMouseEvent *evt)
 
void mouseReleaseEvent (QMouseEvent *evt)
 
void mouseMoveEvent (QMouseEvent *evt)
 
 ~MainWindow ()
 
+ + + +

+Private Slots

void on_cboZoom_currentIndexChanged (int index)
 
+ + + +

+Private Member Functions

void checkAndSendEvent (QPoint pos, bool down)
 
+ + + + + + + +

+Private Attributes

QImage image
 
int currentScale
 
Ui::MainWindow * ui
 
+

Constructor & Destructor Documentation

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MainWindow (QWidget * parent = 0)
+ 		+explicit
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~MainWindow ()
+ 		+protected
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+
+

Member Function Documentation

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void checkAndSendEvent (QPoint pos,
bool down 
)
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void clear (uint16_t color)
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void draw_bitmap_unscaled (uint16_t x,
uint16_t y,
uint16_t width,
uint16_t height,
const uint16_t * dat 
)
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void draw_char (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
QFont font,
char c 
)
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void draw_circle (uint16_t x,
uint16_t y,
uint16_t r,
uint16_t color 
)
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void draw_line (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void draw_pixel (uint16_t x,
uint16_t y,
uint16_t color 
)
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void draw_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
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void fill_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void mouseMoveEvent (QMouseEvent * evt)
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void mousePressEvent (QMouseEvent * evt)
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void mouseReleaseEvent (QMouseEvent * evt)
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void on_cboZoom_currentIndexChanged (int index)
+ 		+privateslot
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void paintEvent (QPaintEvent * evt)
+ 		+protected
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Field Documentation

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int currentScale
+ 		+private
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QImage image
+ 		+private
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Ui::MainWindow* ui
+ 		+private
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+
The documentation for this class was generated from the following files: +
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+ +
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+
PixyInterpreter Member List
+
+
+ +

This is the complete list of members for PixyInterpreter, including all inherited members.

+ + + + + + + + + + + + + + + + + + + +
blocks_are_new()PixyInterpreter
blocks_are_new()PixyInterpreter
close()PixyInterpreter
close()PixyInterpreter
get_blocks(int max_blocks, Block *blocks)PixyInterpreter
get_blocks(int max_blocks, Block *blocks)PixyInterpreter
init()PixyInterpreter
init()PixyInterpreter
PixyInterpreter() (defined in PixyInterpreter)PixyInterpreter
PixyInterpreter() (defined in PixyInterpreter)PixyInterpreter
send_command(const char *name, va_list arguments)PixyInterpreter
send_command(const char *name,...)PixyInterpreter
send_command(const char *name, va_list arguments)PixyInterpreter
send_command(const char *name,...)PixyInterpreter
service() (defined in PixyInterpreter)PixyInterpreter
service() (defined in PixyInterpreter)PixyInterpreter
~PixyInterpreter() (defined in PixyInterpreter)PixyInterpreter
~PixyInterpreter() (defined in PixyInterpreter)PixyInterpreter
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Public Member Functions | +List of all members
+
+
PixyInterpreter Class Reference
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+
+
+Inheritance diagram for PixyInterpreter:
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Inheritance graph
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[legend]
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+Collaboration diagram for PixyInterpreter:
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+Public Member Functions

int init ()
 Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method. More...
 
+void close ()
 Terminates the USB connection to Pixy and the 'iterpreter' thread.
 
int blocks_are_new ()
 Get status of the block data received from Pixy. More...
 
int get_blocks (int max_blocks, Block *blocks)
 Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. More...
 
int send_command (const char *name, va_list arguments)
 Sends a command to Pixy. More...
 
int send_command (const char *name,...)
 Sends a command to Pixy. More...
 
+int service ()
 
int init ()
 Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method. More...
 
+void close ()
 Terminates the USB connection to Pixy and the 'iterpreter' thread.
 
int blocks_are_new ()
 Get status of the block data received from Pixy. More...
 
int get_blocks (int max_blocks, Block *blocks)
 Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. More...
 
int send_command (const char *name, va_list arguments)
 Sends a command to Pixy. More...
 
int send_command (const char *name,...)
 Sends a command to Pixy. More...
 
+int service ()
 
+

Member Function Documentation

+ +
+
+ + + + + + + +
int PixyInterpreter::blocks_are_new ()
+
+ +

Get status of the block data received from Pixy.

+
Returns
0 Stale Data: Block data has previously been retrieved using 'pixy_get_blocks()'.
+
+1 New Data: Pixy sent new data that has not been retrieve yet.
+ +
+
+ +
+
+ + + + + + + +
int PixyInterpreter::blocks_are_new ()
+
+ +

Get status of the block data received from Pixy.

+
Returns
0 Stale Data: Block data has previously been retrieved using 'pixy_get_blocks()'.
+
+1 New Data: Pixy sent new data that has not been retrieve yet.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::get_blocks (int max_blocks,
Block * blocks 
)
+
+ +

Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'.

+
Parameters
+ + + +
[in]max_blocksMaximum number of Blocks to copy to the address pointed to by 'blocks'.
[out]blocksAddress of an array in which to copy the blocks to. The array must be large enough to write 'max_blocks' number of Blocks to.
+
+
+
Returns
Non-negative Success: Number of blocks copied
+
+PIXY_ERROR_USB_IO USB Error: I/O
+
+PIXY_ERROR_NOT_FOUND USB Error: Pixy not found
+
+PIXY_ERROR_USB_BUSY USB Error: Busy
+
+PIXY_ERROR_USB_NO_DEVICE USB Error: No device
+
+PIXY_ERROR_INVALID_PARAMETER Invalid pararmeter specified
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::get_blocks (int max_blocks,
Block * blocks 
)
+
+ +

Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'.

+
Parameters
+ + + +
[in]max_blocksMaximum number of Blocks to copy to the address pointed to by 'blocks'.
[out]blocksAddress of an array in which to copy the blocks to. The array must be large enough to write 'max_blocks' number of Blocks to.
+
+
+
Returns
Non-negative Success: Number of blocks copied
+
+PIXY_ERROR_USB_IO USB Error: I/O
+
+PIXY_ERROR_NOT_FOUND USB Error: Pixy not found
+
+PIXY_ERROR_USB_BUSY USB Error: Busy
+
+PIXY_ERROR_USB_NO_DEVICE USB Error: No device
+
+PIXY_ERROR_INVALID_PARAMETER Invalid pararmeter specified
+ +
+
+ +
+
+ + + + + + + +
int PixyInterpreter::init ()
+
+ +

Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method.

+
Returns
0 Success
+
+-1 Error: Unable to open pixy USB device
+ +
+
+ +
+
+ + + + + + + +
int PixyInterpreter::init ()
+
+ +

Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method.

+
Returns
0 Success
+
+-1 Error: Unable to open pixy USB device
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::send_command (const char * name,
va_list arguments 
)
+
+ +

Sends a command to Pixy.

+
Parameters
+ + + +
[in]nameRemote procedure call identifier string.
[in,out]argumentsArgument list to function call.
+
+
+
Returns
-1 Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::send_command (const char * name,
va_list arguments 
)
+
+ +

Sends a command to Pixy.

+
Parameters
+ + + +
[in]nameRemote procedure call identifier string.
[in,out]argumentsArgument list to function call.
+
+
+
Returns
-1 Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::send_command (const char * name,
 ... 
)
+
+ +

Sends a command to Pixy.

+
Parameters
+ + +
[in]nameRemote procedure call identifier string.
+
+
+
Returns
-1 Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int PixyInterpreter::send_command (const char * name,
 ... 
)
+
+ +

Sends a command to Pixy.

+
Parameters
+ + +
[in]nameRemote procedure call identifier string.
+
+
+
Returns
-1 Error
+ +

+Here is the call graph for this function:
+
+
+
+

+ +

+Here is the caller graph for this function:
+
+
+
+

+ +
+
+
The documentation for this class was generated from the following files: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_pixy_interpreter__coll__graph.map b/class_pixy_interpreter__coll__graph.map new file mode 100644 index 0000000..f7086c6 --- /dev/null +++ b/class_pixy_interpreter__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_pixy_interpreter__coll__graph.md5 b/class_pixy_interpreter__coll__graph.md5 new file mode 100644 index 0000000..ad1a9d1 --- /dev/null +++ b/class_pixy_interpreter__coll__graph.md5 @@ -0,0 +1 @@ +bb868acfce302cf4c88089f1801ac294 \ No newline at end of file diff --git a/class_pixy_interpreter__coll__graph.png b/class_pixy_interpreter__coll__graph.png new file mode 100644 index 0000000..fb707b8 Binary files /dev/null and b/class_pixy_interpreter__coll__graph.png differ diff --git a/class_pixy_interpreter__inherit__graph.map b/class_pixy_interpreter__inherit__graph.map new file mode 100644 index 0000000..f7086c6 --- /dev/null +++ b/class_pixy_interpreter__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_pixy_interpreter__inherit__graph.md5 b/class_pixy_interpreter__inherit__graph.md5 new file mode 100644 index 0000000..ad1a9d1 --- /dev/null +++ b/class_pixy_interpreter__inherit__graph.md5 @@ -0,0 +1 @@ +bb868acfce302cf4c88089f1801ac294 \ No newline at end of file diff --git a/class_pixy_interpreter__inherit__graph.png b/class_pixy_interpreter__inherit__graph.png new file mode 100644 index 0000000..fb707b8 Binary files /dev/null and b/class_pixy_interpreter__inherit__graph.png differ diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.map b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.map new file mode 100644 index 0000000..692dd41 --- /dev/null +++ b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.map @@ -0,0 +1,2 @@ + + diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.md5 b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.md5 new file mode 100644 index 0000000..8d5000d --- /dev/null +++ b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.md5 @@ -0,0 +1 @@ +64ca4b2ecdd9c6dec675bf9f6c73b0da \ No newline at end of file diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.png b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.png new file mode 100644 index 0000000..8c37b0a Binary files /dev/null and b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_cgraph.png differ diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.map b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.map new file mode 100644 index 0000000..692dd41 --- /dev/null +++ b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.map @@ -0,0 +1,2 @@ + + diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.md5 b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.md5 new file mode 100644 index 0000000..ae94d4d --- /dev/null +++ b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.md5 @@ -0,0 +1 @@ +15f807b7621cd40403162a95bf2e70ea \ No newline at end of file diff --git a/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.png b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.png new file mode 100644 index 0000000..5ebf847 Binary files /dev/null and b/class_pixy_interpreter_a38852c452e38dec85dfadc257820cbaf_icgraph.png differ diff --git a/class_simple_vector-members.html b/class_simple_vector-members.html new file mode 100644 index 0000000..663e9d5 --- /dev/null +++ b/class_simple_vector-members.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
SimpleVector< Object > Member List
+
+
+ +

This is the complete list of members for SimpleVector< Object >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + +
capacity() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
capacity() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
clear() (defined in SimpleVector< Object >)SimpleVector< Object >inline
clear() (defined in SimpleVector< Object >)SimpleVector< Object >inline
data() (defined in SimpleVector< Object >)SimpleVector< Object >inline
data() (defined in SimpleVector< Object >)SimpleVector< Object >inline
empty() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
empty() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
operator[](int index) (defined in SimpleVector< Object >)SimpleVector< Object >inline
operator[](int index) const (defined in SimpleVector< Object >)SimpleVector< Object >inline
operator[](int index) (defined in SimpleVector< Object >)SimpleVector< Object >inline
operator[](int index) const (defined in SimpleVector< Object >)SimpleVector< Object >inline
pop_back() (defined in SimpleVector< Object >)SimpleVector< Object >inline
pop_back() (defined in SimpleVector< Object >)SimpleVector< Object >inline
push_back(const Object &x) (defined in SimpleVector< Object >)SimpleVector< Object >inline
push_back(const Object &x) (defined in SimpleVector< Object >)SimpleVector< Object >inline
resize(int newCapacity) (defined in SimpleVector< Object >)SimpleVector< Object >inline
resize(int newCapacity) (defined in SimpleVector< Object >)SimpleVector< Object >inline
SimpleVector(int initSize=0) (defined in SimpleVector< Object >)SimpleVector< Object >inline
SimpleVector(int initSize=0) (defined in SimpleVector< Object >)SimpleVector< Object >inline
size() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
size() const (defined in SimpleVector< Object >)SimpleVector< Object >inline
~SimpleVector() (defined in SimpleVector< Object >)SimpleVector< Object >inline
~SimpleVector() (defined in SimpleVector< Object >)SimpleVector< Object >inline
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_simple_vector.html b/class_simple_vector.html new file mode 100644 index 0000000..d93e0df --- /dev/null +++ b/class_simple_vector.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: SimpleVector< Object > Class Template Reference + + + + + + + + + + +
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+Public Member Functions | +List of all members
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SimpleVector< Object > Class Template Reference
+
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+Public Member Functions

+ SimpleVector (int initSize=0)
 
+int resize (int newCapacity)
 
+Object & operator[] (int index)
 
+const Object & operator[] (int index) const
 
+bool empty () const
 
+int size () const
 
+int capacity () const
 
+const Object * data ()
 
+int push_back (const Object &x)
 
+void pop_back ()
 
+void clear ()
 
+ SimpleVector (int initSize=0)
 
+int resize (int newCapacity)
 
+Object & operator[] (int index)
 
+const Object & operator[] (int index) const
 
+bool empty () const
 
+int size () const
 
+int capacity () const
 
+const Object * data ()
 
+int push_back (const Object &x)
 
+void pop_back ()
 
+void clear ()
 
+
The documentation for this class was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_u_s_b_link-members.html b/class_u_s_b_link-members.html new file mode 100644 index 0000000..ec9e4a6 --- /dev/null +++ b/class_u_s_b_link-members.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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USBLink Member List
+
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+ +

This is the complete list of members for USBLink, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
blockSize() (defined in Link)Linkinlinevirtual
blockSize() (defined in Link)Linkinlinevirtual
getBuffer(uint8_t **, uint32_t *) (defined in Link)Linkinlinevirtual
getBuffer(uint8_t **, uint32_t *) (defined in Link)Linkinlinevirtual
getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS) (defined in Link)Linkinlinevirtual
getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS) (defined in Link)Linkinlinevirtual
getTimer() (defined in USBLink)USBLinkvirtual
getTimer() (defined in USBLink)USBLinkvirtual
Link() (defined in Link)Linkinline
Link() (defined in Link)Linkinline
m_blockSize (defined in Link)Linkprotected
m_flags (defined in Link)Linkprotected
open() (defined in USBLink)USBLink
open() (defined in USBLink)USBLink
receive(uint8_t *data, uint32_t len, uint16_t timeoutMs) (defined in USBLink)USBLinkvirtual
receive(uint8_t *data, uint32_t len, uint16_t timeoutMs) (defined in USBLink)USBLinkvirtual
send(const uint8_t *data, uint32_t len, uint16_t timeoutMs) (defined in USBLink)USBLinkvirtual
send(const uint8_t *data, uint32_t len, uint16_t timeoutMs) (defined in USBLink)USBLinkvirtual
setTimer() (defined in USBLink)USBLinkvirtual
setTimer() (defined in USBLink)USBLinkvirtual
USBLink() (defined in USBLink)USBLink
USBLink() (defined in USBLink)USBLink
~Link() (defined in Link)Linkinline
~Link() (defined in Link)Linkinline
~USBLink() (defined in USBLink)USBLink
~USBLink() (defined in USBLink)USBLink
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_u_s_b_link.html b/class_u_s_b_link.html new file mode 100644 index 0000000..d9c5f61 --- /dev/null +++ b/class_u_s_b_link.html @@ -0,0 +1,183 @@ + + + + + + +discoverpixy: USBLink Class Reference + + + + + + + + + + +
+
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+Public Member Functions | +List of all members
+
+
USBLink Class Reference
+
+
+
+Inheritance diagram for USBLink:
+
+
Inheritance graph
+ + +
[legend]
+
+Collaboration diagram for USBLink:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+int open ()
 
+virtual int send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
+virtual int receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
+virtual void setTimer ()
 
+virtual uint32_t getTimer ()
 
+int open ()
 
+virtual int send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
+virtual int receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
+virtual void setTimer ()
 
+virtual uint32_t getTimer ()
 
- Public Member Functions inherited from Link
+virtual uint32_t getFlags (uint8_t index=LINK_FLAG_INDEX_FLAGS)
 
+virtual uint32_t blockSize ()
 
+virtual int getBuffer (uint8_t **, uint32_t *)
 
+virtual uint32_t getFlags (uint8_t index=LINK_FLAG_INDEX_FLAGS)
 
+virtual uint32_t blockSize ()
 
+virtual int getBuffer (uint8_t **, uint32_t *)
 
+ + + + + + +

+Additional Inherited Members

- Protected Attributes inherited from Link
+uint32_t m_flags
 
+uint32_t m_blockSize
 
+
The documentation for this class was generated from the following files: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_u_s_b_link__coll__graph.map b/class_u_s_b_link__coll__graph.map new file mode 100644 index 0000000..30db5e6 --- /dev/null +++ b/class_u_s_b_link__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_u_s_b_link__coll__graph.md5 b/class_u_s_b_link__coll__graph.md5 new file mode 100644 index 0000000..7ddf72b --- /dev/null +++ b/class_u_s_b_link__coll__graph.md5 @@ -0,0 +1 @@ +770df9023403955b9d9680b86b9691b6 \ No newline at end of file diff --git a/class_u_s_b_link__coll__graph.png b/class_u_s_b_link__coll__graph.png new file mode 100644 index 0000000..7f250e4 Binary files /dev/null and b/class_u_s_b_link__coll__graph.png differ diff --git a/class_u_s_b_link__inherit__graph.map b/class_u_s_b_link__inherit__graph.map new file mode 100644 index 0000000..30db5e6 --- /dev/null +++ b/class_u_s_b_link__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_u_s_b_link__inherit__graph.md5 b/class_u_s_b_link__inherit__graph.md5 new file mode 100644 index 0000000..7ddf72b --- /dev/null +++ b/class_u_s_b_link__inherit__graph.md5 @@ -0,0 +1 @@ +770df9023403955b9d9680b86b9691b6 \ No newline at end of file diff --git a/class_u_s_b_link__inherit__graph.png b/class_u_s_b_link__inherit__graph.png new file mode 100644 index 0000000..7f250e4 Binary files /dev/null and b/class_u_s_b_link__inherit__graph.png differ diff --git a/class_ui_1_1_main_window-members.html b/class_ui_1_1_main_window-members.html new file mode 100644 index 0000000..e5b353d --- /dev/null +++ b/class_ui_1_1_main_window-members.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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Ui::MainWindow Member List
+
+
+ +

This is the complete list of members for Ui::MainWindow, including all inherited members.

+ + + + + + + + + + + + +
btnExit (defined in Ui_MainWindow)Ui_MainWindow
cboZoom (defined in Ui_MainWindow)Ui_MainWindow
centralwidget (defined in Ui_MainWindow)Ui_MainWindow
horizontalLayout (defined in Ui_MainWindow)Ui_MainWindow
horizontalSpacer (defined in Ui_MainWindow)Ui_MainWindow
label (defined in Ui_MainWindow)Ui_MainWindow
line (defined in Ui_MainWindow)Ui_MainWindow
retranslateUi(QMainWindow *MainWindow) (defined in Ui_MainWindow)Ui_MainWindowinline
setupUi(QMainWindow *MainWindow) (defined in Ui_MainWindow)Ui_MainWindowinline
verticalLayout (defined in Ui_MainWindow)Ui_MainWindow
widgetDisplay (defined in Ui_MainWindow)Ui_MainWindow
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_ui_1_1_main_window.html b/class_ui_1_1_main_window.html new file mode 100644 index 0000000..642201d --- /dev/null +++ b/class_ui_1_1_main_window.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: MainWindow Class Reference + + + + + + + + + + +
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+
MainWindow Class Reference
+
+
+ +

#include <ui_mainwindow.h>

+
+Inheritance diagram for MainWindow:
+
+
Inheritance graph
+ + +
[legend]
+
+Collaboration diagram for MainWindow:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Public Member Functions inherited from Ui_MainWindow
void setupUi (QMainWindow *MainWindow)
 
void retranslateUi (QMainWindow *MainWindow)
 
- Data Fields inherited from Ui_MainWindow
QWidget * centralwidget
 
QVBoxLayout * verticalLayout
 
QHBoxLayout * horizontalLayout
 
QLabel * label
 
QComboBox * cboZoom
 
QSpacerItem * horizontalSpacer
 
QPushButton * btnExit
 
QFrame * line
 
QWidget * widgetDisplay
 
+
The documentation for this class was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:25:38 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_ui_1_1_main_window__coll__graph.map b/class_ui_1_1_main_window__coll__graph.map new file mode 100644 index 0000000..d4d6da9 --- /dev/null +++ b/class_ui_1_1_main_window__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_ui_1_1_main_window__coll__graph.md5 b/class_ui_1_1_main_window__coll__graph.md5 new file mode 100644 index 0000000..4722fcf --- /dev/null +++ b/class_ui_1_1_main_window__coll__graph.md5 @@ -0,0 +1 @@ +2c3414fbf2cffc534b2f56000ce0a8d4 \ No newline at end of file diff --git a/class_ui_1_1_main_window__coll__graph.png b/class_ui_1_1_main_window__coll__graph.png new file mode 100644 index 0000000..11704ef Binary files /dev/null and b/class_ui_1_1_main_window__coll__graph.png differ diff --git a/class_ui_1_1_main_window__inherit__graph.map b/class_ui_1_1_main_window__inherit__graph.map new file mode 100644 index 0000000..d4d6da9 --- /dev/null +++ b/class_ui_1_1_main_window__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/class_ui_1_1_main_window__inherit__graph.md5 b/class_ui_1_1_main_window__inherit__graph.md5 new file mode 100644 index 0000000..4722fcf --- /dev/null +++ b/class_ui_1_1_main_window__inherit__graph.md5 @@ -0,0 +1 @@ +2c3414fbf2cffc534b2f56000ce0a8d4 \ No newline at end of file diff --git a/class_ui_1_1_main_window__inherit__graph.png b/class_ui_1_1_main_window__inherit__graph.png new file mode 100644 index 0000000..11704ef Binary files /dev/null and b/class_ui_1_1_main_window__inherit__graph.png differ diff --git a/class_ui___main_window-members.html b/class_ui___main_window-members.html new file mode 100644 index 0000000..e7e5b7d --- /dev/null +++ b/class_ui___main_window-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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Ui_MainWindow Member List
+
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+ +

This is the complete list of members for Ui_MainWindow, including all inherited members.

+ + + + + + + + + + + + +
btnExit (defined in Ui_MainWindow)Ui_MainWindow
cboZoom (defined in Ui_MainWindow)Ui_MainWindow
centralwidget (defined in Ui_MainWindow)Ui_MainWindow
horizontalLayout (defined in Ui_MainWindow)Ui_MainWindow
horizontalSpacer (defined in Ui_MainWindow)Ui_MainWindow
label (defined in Ui_MainWindow)Ui_MainWindow
line (defined in Ui_MainWindow)Ui_MainWindow
retranslateUi(QMainWindow *MainWindow) (defined in Ui_MainWindow)Ui_MainWindowinline
setupUi(QMainWindow *MainWindow) (defined in Ui_MainWindow)Ui_MainWindowinline
verticalLayout (defined in Ui_MainWindow)Ui_MainWindow
widgetDisplay (defined in Ui_MainWindow)Ui_MainWindow
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/class_ui___main_window.html b/class_ui___main_window.html new file mode 100644 index 0000000..066f321 --- /dev/null +++ b/class_ui___main_window.html @@ -0,0 +1,328 @@ + + + + + + +discoverpixy: Ui_MainWindow Class Reference + + + + + + + + + + +
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+Public Member Functions | +Data Fields
+
+
Ui_MainWindow Class Reference
+
+
+ +

#include <ui_mainwindow.h>

+
+Inheritance diagram for Ui_MainWindow:
+
+
Inheritance graph
+ + +
[legend]
+ + + + + + +

+Public Member Functions

void setupUi (QMainWindow *MainWindow)
 
void retranslateUi (QMainWindow *MainWindow)
 
+ + + + + + + + + + + + + + + + + + + +

+Data Fields

QWidget * centralwidget
 
QVBoxLayout * verticalLayout
 
QHBoxLayout * horizontalLayout
 
QLabel * label
 
QComboBox * cboZoom
 
QSpacerItem * horizontalSpacer
 
QPushButton * btnExit
 
QFrame * line
 
QWidget * widgetDisplay
 
+

Member Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + +
void retranslateUi (QMainWindow * MainWindow)
+ 		+inline
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
void setupUi (QMainWindow * MainWindow)
+ 		+inline
+
+ +

+Here is the call graph for this function:
+
+
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+

+ +

+Here is the caller graph for this function:
+
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+ +
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Field Documentation

+ +
+
+ + + + +
QPushButton* btnExit
+
+ +
+
+ +
+
+ + + + +
QComboBox* cboZoom
+
+ +
+
+ +
+
+ + + + +
QWidget* centralwidget
+
+ +
+
+ +
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QWidget* widgetDisplay
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util::timer Member List
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This is the complete list of members for util::timer, including all inherited members.

+ + + + +
elapsed() (defined in util::timer)util::timer
reset() (defined in util::timer)util::timer
timer() (defined in util::timer)util::timer
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util::timer Class Reference
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+Public Member Functions

+void reset ()
 
+uint32_t elapsed ()
 
+
The documentation for this class was generated from the following files: +
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+ + diff --git a/closed.png b/closed.png new file mode 100644 index 0000000..98cc2c9 Binary files /dev/null and b/closed.png differ diff --git a/core__cm4_8h.html b/core__cm4_8h.html new file mode 100644 index 0000000..1b85b5a --- /dev/null +++ b/core__cm4_8h.html @@ -0,0 +1,1131 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cm4.h File Reference + + + + + + + + + + +
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core_cm4.h File Reference
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CMSIS Cortex-M4 Core Peripheral Access Layer Header File. +More...

+
#include <stdint.h>
+#include <core_cmInstr.h>
+#include <core_cmFunc.h>
+#include <core_cm4_simd.h>
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+Classes

union  APSR_Type
 Union type to access the Application Program Status Register (APSR). More...
 
union  IPSR_Type
 Union type to access the Interrupt Program Status Register (IPSR). More...
 
union  xPSR_Type
 Union type to access the Special-Purpose Program Status Registers (xPSR). More...
 
union  CONTROL_Type
 Union type to access the Control Registers (CONTROL). More...
 
struct  NVIC_Type
 Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
 
struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
struct  SCnSCB_Type
 Structure type to access the System Control and ID Register not in the SCB. More...
 
struct  SysTick_Type
 Structure type to access the System Timer (SysTick). More...
 
struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 
struct  DWT_Type
 Structure type to access the Data Watchpoint and Trace Register (DWT). More...
 
struct  TPI_Type
 Structure type to access the Trace Port Interface Register (TPI). More...
 
struct  CoreDebug_Type
 Structure type to access the Core Debug Register (CoreDebug). More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define __CORE_CM4_H_GENERIC
 
#define NVIC_STIR_INTID_Pos   0
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL << NVIC_STIR_INTID_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
 
#define SCnSCB_ACTLR_DISOOFP_Pos   9
 
#define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
 
#define SCnSCB_ACTLR_DISFPCA_Pos   8
 
#define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
 
#define SCnSCB_ACTLR_DISFOLD_Pos   2
 
#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
 
#define SCnSCB_ACTLR_DISDEFWBUF_Pos   1
 
#define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
 
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0
 
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0
 
#define SysTick_CTRL_ENABLE_Msk   (1UL << SysTick_CTRL_ENABLE_Pos)
 
#define SysTick_LOAD_RELOAD_Pos   0
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
 
#define SysTick_VAL_CURRENT_Pos   0
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
 
#define SysTick_CALIB_NOREF_Pos   31
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
 
#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
#define DWT_CTRL_NUMCOMP_Pos   28
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
 
#define DWT_CPICNT_CPICNT_Pos   0
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL << DWT_CPICNT_CPICNT_Pos)
 
#define DWT_EXCCNT_EXCCNT_Pos   0
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
 
#define DWT_LSUCNT_LSUCNT_Pos   0
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
 
#define DWT_MASK_MASK_Pos   0
 
#define DWT_MASK_MASK_Msk   (0x1FUL << DWT_MASK_MASK_Pos)
 
#define DWT_FUNCTION_MATCHED_Pos   24
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
 
#define TPI_ACPR_PRESCALER_Pos   0
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
 
#define TPI_SPPR_TXMODE_Pos   0
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL << TPI_SPPR_TXMODE_Pos)
 
#define TPI_FFSR_FtNonStop_Pos   3
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL << TPI_FFSR_FlInProg_Pos)
 
#define TPI_FFCR_TrigIn_Pos   8
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL << TPI_FIFO0_ETM0_Pos)
 
#define TPI_ITATBCTR2_ATREADY_Pos   0
 
#define TPI_ITATBCTR2_ATREADY_Msk   (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL << TPI_FIFO1_ITM0_Pos)
 
#define TPI_ITATBCTR0_ATREADY_Pos   0
 
#define TPI_ITATBCTR0_ATREADY_Msk   (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
 
#define TPI_ITCTRL_Mode_Pos   0
 
#define TPI_ITCTRL_Mode_Msk   (0x1UL << TPI_ITCTRL_Mode_Pos)
 
#define TPI_DEVID_NRZVALID_Pos   11
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
 
#define TPI_DEVTYPE_SubType_Pos   0
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL << TPI_DEVTYPE_SubType_Pos)
 
#define TPI_DEVTYPE_MajorType_Pos   4
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
 
#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define ITM_RXBUFFER_EMPTY   0x5AA55AA5
 
#define __CM4_CMSIS_VERSION_MAIN   (0x03)
 
#define __CM4_CMSIS_VERSION_SUB   (0x20)
 
#define __CM4_CMSIS_VERSION
 
#define __CORTEX_M   (0x04)
 
#define __CORE_CM4_H_DEPENDANT
 
#define __I   volatile const
 
#define __O   volatile
 
#define __IO   volatile
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set Priority Grouping. More...
 
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping (void)
 Get Priority Grouping. More...
 
__STATIC_INLINE void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable External Interrupt. More...
 
__STATIC_INLINE void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable External Interrupt. More...
 
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get Pending Interrupt. More...
 
__STATIC_INLINE void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set Pending Interrupt. More...
 
__STATIC_INLINE void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear Pending Interrupt. More...
 
__STATIC_INLINE uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get Active Interrupt. More...
 
__STATIC_INLINE void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set Interrupt Priority. More...
 
__STATIC_INLINE uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get Interrupt Priority. More...
 
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encode Priority. More...
 
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode Priority. More...
 
__STATIC_INLINE void NVIC_SystemReset (void)
 System Reset. More...
 
__STATIC_INLINE uint32_t SysTick_Config (uint32_t ticks)
 System Tick Configuration. More...
 
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 ITM Send Character. More...
 
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
 ITM Receive Character. More...
 
__STATIC_INLINE int32_t ITM_CheckChar (void)
 ITM Check Character. More...
 
+ + + +

+Variables

volatile int32_t ITM_RxBuffer
 
+

Detailed Description

+

CMSIS Cortex-M4 Core Peripheral Access Layer Header File.

+
Version
V3.20
+
Date
25. February 2013
+
Note
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CM4_CMSIS_VERSION
+
+Value:
((__CM4_CMSIS_VERSION_MAIN << 16) | \
+
__CM4_CMSIS_VERSION_SUB )
+
__CM4_CMSIS_VERSION_SUB
#define __CM4_CMSIS_VERSION_SUB
Definition: core_cm4.h:72
+
__CM4_CMSIS_VERSION_MAIN
#define __CM4_CMSIS_VERSION_MAIN
Definition: core_cm4.h:71
+

CMSIS HAL version number

+ +
+
+ +
+
+ + + + +
#define __CM4_CMSIS_VERSION_MAIN   (0x03)
+
+

[31:16] CMSIS HAL main version

+ +
+
+ +
+
+ + + + +
#define __CM4_CMSIS_VERSION_SUB   (0x20)
+
+

[15:0] CMSIS HAL sub version

+ +
+
+ +
+
+ + + + +
#define __CORE_CM4_H_DEPENDANT
+
+

__FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.

+ +
+
+ +
+
+ + + + +
#define __CORTEX_M   (0x04)
+
+

Cortex-M Core

+ +
+
+ +
+
+ + + + +
#define __I   volatile const
+
+

Defines 'read only' permissions

+ +
+
+ +
+
+ + + + +
#define __IO   volatile
+
+

Defines 'read / write' permissions

+ +
+
+ +
+
+ + + + +
#define __O   volatile
+
+

Defines 'write only' permissions

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/core__cm4_8h__dep__incl.map b/core__cm4_8h__dep__incl.map new file mode 100644 index 0000000..c5888c2 --- /dev/null +++ b/core__cm4_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/core__cm4_8h__dep__incl.md5 b/core__cm4_8h__dep__incl.md5 new file mode 100644 index 0000000..c35102a --- /dev/null +++ b/core__cm4_8h__dep__incl.md5 @@ -0,0 +1 @@ +cfc5382a24fd91561ef768e226fd0a59 \ No newline at end of file diff --git a/core__cm4_8h__dep__incl.png b/core__cm4_8h__dep__incl.png new file mode 100644 index 0000000..1708256 Binary files /dev/null and b/core__cm4_8h__dep__incl.png differ diff --git a/core__cm4_8h__incl.map b/core__cm4_8h__incl.map new file mode 100644 index 0000000..af9e042 --- /dev/null +++ b/core__cm4_8h__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/core__cm4_8h__incl.md5 b/core__cm4_8h__incl.md5 new file mode 100644 index 0000000..eca83dc --- /dev/null +++ b/core__cm4_8h__incl.md5 @@ -0,0 +1 @@ +7f4e43acaf79e7aee27b773a1e9b8f4a \ No newline at end of file diff --git a/core__cm4_8h__incl.png b/core__cm4_8h__incl.png new file mode 100644 index 0000000..48c6f53 Binary files /dev/null and b/core__cm4_8h__incl.png differ diff --git a/core__cm4_8h_source.html b/core__cm4_8h_source.html new file mode 100644 index 0000000..929d9f1 --- /dev/null +++ b/core__cm4_8h_source.html @@ -0,0 +1,1446 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cm4.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
core_cm4.h
+
+
+Go to the documentation of this file.
1 /**************************************************************************/
+
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
+
11 
+
12  All rights reserved.
+
13  Redistribution and use in source and binary forms, with or without
+
14  modification, are permitted provided that the following conditions are met:
+
15  - Redistributions of source code must retain the above copyright
+
16  notice, this list of conditions and the following disclaimer.
+
17  - Redistributions in binary form must reproduce the above copyright
+
18  notice, this list of conditions and the following disclaimer in the
+
19  documentation and/or other materials provided with the distribution.
+
20  - Neither the name of ARM nor the names of its contributors may be used
+
21  to endorse or promote products derived from this software without
+
22  specific prior written permission.
+
23  *
+
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
34  POSSIBILITY OF SUCH DAMAGE.
+
35  ---------------------------------------------------------------------------*/
+
36 
+
37 
+
38 #if defined ( __ICCARM__ )
+
39  #pragma system_include /* treat file as system include file for MISRA check */
+
40 #endif
+
41 
+
42 #ifdef __cplusplus
+
43  extern "C" {
+
44 #endif
+
45 
+
46 #ifndef __CORE_CM4_H_GENERIC
+
47 #define __CORE_CM4_H_GENERIC
+
48 
+
63 /*******************************************************************************
+
64  * CMSIS definitions
+
65  ******************************************************************************/
+
70 /* CMSIS CM4 definitions */
+
71 #define __CM4_CMSIS_VERSION_MAIN (0x03)
+
72 #define __CM4_CMSIS_VERSION_SUB (0x20)
+
73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+
74  __CM4_CMSIS_VERSION_SUB )
+
76 #define __CORTEX_M (0x04)
+
79 #if defined ( __CC_ARM )
+
80  #define __ASM __asm
+
81  #define __INLINE __inline
+
82  #define __STATIC_INLINE static __inline
+
83 
+
84 #elif defined ( __ICCARM__ )
+
85  #define __ASM __asm
+
86  #define __INLINE inline
+
87  #define __STATIC_INLINE static inline
+
88 
+
89 #elif defined ( __TMS470__ )
+
90  #define __ASM __asm
+
91  #define __STATIC_INLINE static inline
+
92 
+
93 #elif defined ( __GNUC__ )
+
94  #define __ASM __asm
+
95  #define __INLINE inline
+
96  #define __STATIC_INLINE static inline
+
97 
+
98 #elif defined ( __TASKING__ )
+
99  #define __ASM __asm
+
100  #define __INLINE inline
+
101  #define __STATIC_INLINE static inline
+
102 
+
103 #endif
+
104 
+
107 #if defined ( __CC_ARM )
+
108  #if defined __TARGET_FPU_VFP
+
109  #if (__FPU_PRESENT == 1)
+
110  #define __FPU_USED 1
+
111  #else
+
112  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+
113  #define __FPU_USED 0
+
114  #endif
+
115  #else
+
116  #define __FPU_USED 0
+
117  #endif
+
118 
+
119 #elif defined ( __ICCARM__ )
+
120  #if defined __ARMVFP__
+
121  #if (__FPU_PRESENT == 1)
+
122  #define __FPU_USED 1
+
123  #else
+
124  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+
125  #define __FPU_USED 0
+
126  #endif
+
127  #else
+
128  #define __FPU_USED 0
+
129  #endif
+
130 
+
131 #elif defined ( __TMS470__ )
+
132  #if defined __TI_VFP_SUPPORT__
+
133  #if (__FPU_PRESENT == 1)
+
134  #define __FPU_USED 1
+
135  #else
+
136  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+
137  #define __FPU_USED 0
+
138  #endif
+
139  #else
+
140  #define __FPU_USED 0
+
141  #endif
+
142 
+
143 #elif defined ( __GNUC__ )
+
144  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+
145  #if (__FPU_PRESENT == 1)
+
146  #define __FPU_USED 1
+
147  #else
+
148  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+
149  #define __FPU_USED 0
+
150  #endif
+
151  #else
+
152  #define __FPU_USED 0
+
153  #endif
+
154 
+
155 #elif defined ( __TASKING__ )
+
156  #if defined __FPU_VFP__
+
157  #if (__FPU_PRESENT == 1)
+
158  #define __FPU_USED 1
+
159  #else
+
160  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+
161  #define __FPU_USED 0
+
162  #endif
+
163  #else
+
164  #define __FPU_USED 0
+
165  #endif
+
166 #endif
+
167 
+
168 #include <stdint.h> /* standard types definitions */
+
169 #include <core_cmInstr.h> /* Core Instruction Access */
+
170 #include <core_cmFunc.h> /* Core Function Access */
+
171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
172 
+
173 #endif /* __CORE_CM4_H_GENERIC */
+
174 
+
175 #ifndef __CMSIS_GENERIC
+
176 
+
177 #ifndef __CORE_CM4_H_DEPENDANT
+
178 #define __CORE_CM4_H_DEPENDANT
+
179 
+
180 /* check device defines and use defaults */
+
181 #if defined __CHECK_DEVICE_DEFINES
+
182  #ifndef __CM4_REV
+
183  #define __CM4_REV 0x0000
+
184  #warning "__CM4_REV not defined in device header file; using default!"
+
185  #endif
+
186 
+
187  #ifndef __FPU_PRESENT
+
188  #define __FPU_PRESENT 0
+
189  #warning "__FPU_PRESENT not defined in device header file; using default!"
+
190  #endif
+
191 
+
192  #ifndef __MPU_PRESENT
+
193  #define __MPU_PRESENT 0
+
194  #warning "__MPU_PRESENT not defined in device header file; using default!"
+
195  #endif
+
196 
+
197  #ifndef __NVIC_PRIO_BITS
+
198  #define __NVIC_PRIO_BITS 4
+
199  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+
200  #endif
+
201 
+
202  #ifndef __Vendor_SysTickConfig
+
203  #define __Vendor_SysTickConfig 0
+
204  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+
205  #endif
+
206 #endif
+
207 
+
208 /* IO definitions (access restrictions to peripheral registers) */
+
216 #ifdef __cplusplus
+
217  #define __I volatile
+
218 #else
+
219  #define __I volatile const
+
220 #endif
+
221 #define __O volatile
+
222 #define __IO volatile
+
224 
+
228 /*******************************************************************************
+
229  * Register Abstraction
+
230  Core Register contain:
+
231  - Core Register
+
232  - Core NVIC Register
+
233  - Core SCB Register
+
234  - Core SysTick Register
+
235  - Core Debug Register
+
236  - Core MPU Register
+
237  - Core FPU Register
+
238  ******************************************************************************/
+
239 
+
251 typedef union
+
252 {
+
253  struct
+
254  {
+
255 #if (__CORTEX_M != 0x04)
+
256  uint32_t _reserved0:27;
+
257 #else
+
258  uint32_t _reserved0:16;
+
259  uint32_t GE:4;
+
260  uint32_t _reserved1:7;
+
261 #endif
+
262  uint32_t Q:1;
+
263  uint32_t V:1;
+
264  uint32_t C:1;
+
265  uint32_t Z:1;
+
266  uint32_t N:1;
+
267  } b;
+
268  uint32_t w;
+
269 } APSR_Type;
+
270 
+
271 
+
274 typedef union
+
275 {
+
276  struct
+
277  {
+
278  uint32_t ISR:9;
+
279  uint32_t _reserved0:23;
+
280  } b;
+
281  uint32_t w;
+
282 } IPSR_Type;
+
283 
+
284 
+
287 typedef union
+
288 {
+
289  struct
+
290  {
+
291  uint32_t ISR:9;
+
292 #if (__CORTEX_M != 0x04)
+
293  uint32_t _reserved0:15;
+
294 #else
+
295  uint32_t _reserved0:7;
+
296  uint32_t GE:4;
+
297  uint32_t _reserved1:4;
+
298 #endif
+
299  uint32_t T:1;
+
300  uint32_t IT:2;
+
301  uint32_t Q:1;
+
302  uint32_t V:1;
+
303  uint32_t C:1;
+
304  uint32_t Z:1;
+
305  uint32_t N:1;
+
306  } b;
+
307  uint32_t w;
+
308 } xPSR_Type;
+
309 
+
310 
+
313 typedef union
+
314 {
+
315  struct
+
316  {
+
317  uint32_t nPRIV:1;
+
318  uint32_t SPSEL:1;
+
319  uint32_t FPCA:1;
+
320  uint32_t _reserved0:29;
+
321  } b;
+
322  uint32_t w;
+
323 } CONTROL_Type;
+
324 
+
336 typedef struct
+
337 {
+
338  __IO uint32_t ISER[8];
+
339  uint32_t RESERVED0[24];
+
340  __IO uint32_t ICER[8];
+
341  uint32_t RSERVED1[24];
+
342  __IO uint32_t ISPR[8];
+
343  uint32_t RESERVED2[24];
+
344  __IO uint32_t ICPR[8];
+
345  uint32_t RESERVED3[24];
+
346  __IO uint32_t IABR[8];
+
347  uint32_t RESERVED4[56];
+
348  __IO uint8_t IP[240];
+
349  uint32_t RESERVED5[644];
+
350  __O uint32_t STIR;
+
351 } NVIC_Type;
+
352 
+
353 /* Software Triggered Interrupt Register Definitions */
+
354 #define NVIC_STIR_INTID_Pos 0
+
355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
+
357 
+
368 typedef struct
+
369 {
+
370  __I uint32_t CPUID;
+
371  __IO uint32_t ICSR;
+
372  __IO uint32_t VTOR;
+
373  __IO uint32_t AIRCR;
+
374  __IO uint32_t SCR;
+
375  __IO uint32_t CCR;
+
376  __IO uint8_t SHP[12];
+
377  __IO uint32_t SHCSR;
+
378  __IO uint32_t CFSR;
+
379  __IO uint32_t HFSR;
+
380  __IO uint32_t DFSR;
+
381  __IO uint32_t MMFAR;
+
382  __IO uint32_t BFAR;
+
383  __IO uint32_t AFSR;
+
384  __I uint32_t PFR[2];
+
385  __I uint32_t DFR;
+
386  __I uint32_t ADR;
+
387  __I uint32_t MMFR[4];
+
388  __I uint32_t ISAR[5];
+
389  uint32_t RESERVED0[5];
+
390  __IO uint32_t CPACR;
+
391 } SCB_Type;
+
392 
+
393 /* SCB CPUID Register Definitions */
+
394 #define SCB_CPUID_IMPLEMENTER_Pos 24
+
395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
+
397 #define SCB_CPUID_VARIANT_Pos 20
+
398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
+
400 #define SCB_CPUID_ARCHITECTURE_Pos 16
+
401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
+
403 #define SCB_CPUID_PARTNO_Pos 4
+
404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
+
406 #define SCB_CPUID_REVISION_Pos 0
+
407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
+
409 /* SCB Interrupt Control State Register Definitions */
+
410 #define SCB_ICSR_NMIPENDSET_Pos 31
+
411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
+
413 #define SCB_ICSR_PENDSVSET_Pos 28
+
414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
+
416 #define SCB_ICSR_PENDSVCLR_Pos 27
+
417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
+
419 #define SCB_ICSR_PENDSTSET_Pos 26
+
420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
+
422 #define SCB_ICSR_PENDSTCLR_Pos 25
+
423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
+
425 #define SCB_ICSR_ISRPREEMPT_Pos 23
+
426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
+
428 #define SCB_ICSR_ISRPENDING_Pos 22
+
429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
+
431 #define SCB_ICSR_VECTPENDING_Pos 12
+
432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
+
434 #define SCB_ICSR_RETTOBASE_Pos 11
+
435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
+
437 #define SCB_ICSR_VECTACTIVE_Pos 0
+
438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
+
440 /* SCB Vector Table Offset Register Definitions */
+
441 #define SCB_VTOR_TBLOFF_Pos 7
+
442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
+
444 /* SCB Application Interrupt and Reset Control Register Definitions */
+
445 #define SCB_AIRCR_VECTKEY_Pos 16
+
446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
+
448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16
+
449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
+
451 #define SCB_AIRCR_ENDIANESS_Pos 15
+
452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
+
454 #define SCB_AIRCR_PRIGROUP_Pos 8
+
455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
+
457 #define SCB_AIRCR_SYSRESETREQ_Pos 2
+
458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
+
460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1
+
461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
+
463 #define SCB_AIRCR_VECTRESET_Pos 0
+
464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
+
466 /* SCB System Control Register Definitions */
+
467 #define SCB_SCR_SEVONPEND_Pos 4
+
468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
+
470 #define SCB_SCR_SLEEPDEEP_Pos 2
+
471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
+
473 #define SCB_SCR_SLEEPONEXIT_Pos 1
+
474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
+
476 /* SCB Configuration Control Register Definitions */
+
477 #define SCB_CCR_STKALIGN_Pos 9
+
478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
+
480 #define SCB_CCR_BFHFNMIGN_Pos 8
+
481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
+
483 #define SCB_CCR_DIV_0_TRP_Pos 4
+
484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
+
486 #define SCB_CCR_UNALIGN_TRP_Pos 3
+
487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
+
489 #define SCB_CCR_USERSETMPEND_Pos 1
+
490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
+
492 #define SCB_CCR_NONBASETHRDENA_Pos 0
+
493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
+
495 /* SCB System Handler Control and State Register Definitions */
+
496 #define SCB_SHCSR_USGFAULTENA_Pos 18
+
497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
+
499 #define SCB_SHCSR_BUSFAULTENA_Pos 17
+
500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
+
502 #define SCB_SHCSR_MEMFAULTENA_Pos 16
+
503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
+
505 #define SCB_SHCSR_SVCALLPENDED_Pos 15
+
506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
+
508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14
+
509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
+
511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13
+
512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
+
514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12
+
515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
+
517 #define SCB_SHCSR_SYSTICKACT_Pos 11
+
518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
+
520 #define SCB_SHCSR_PENDSVACT_Pos 10
+
521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
+
523 #define SCB_SHCSR_MONITORACT_Pos 8
+
524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
+
526 #define SCB_SHCSR_SVCALLACT_Pos 7
+
527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
+
529 #define SCB_SHCSR_USGFAULTACT_Pos 3
+
530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
+
532 #define SCB_SHCSR_BUSFAULTACT_Pos 1
+
533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
+
535 #define SCB_SHCSR_MEMFAULTACT_Pos 0
+
536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
+
538 /* SCB Configurable Fault Status Registers Definitions */
+
539 #define SCB_CFSR_USGFAULTSR_Pos 16
+
540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
+
542 #define SCB_CFSR_BUSFAULTSR_Pos 8
+
543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
+
545 #define SCB_CFSR_MEMFAULTSR_Pos 0
+
546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
+
548 /* SCB Hard Fault Status Registers Definitions */
+
549 #define SCB_HFSR_DEBUGEVT_Pos 31
+
550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
+
552 #define SCB_HFSR_FORCED_Pos 30
+
553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
+
555 #define SCB_HFSR_VECTTBL_Pos 1
+
556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
+
558 /* SCB Debug Fault Status Register Definitions */
+
559 #define SCB_DFSR_EXTERNAL_Pos 4
+
560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
+
562 #define SCB_DFSR_VCATCH_Pos 3
+
563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
+
565 #define SCB_DFSR_DWTTRAP_Pos 2
+
566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
+
568 #define SCB_DFSR_BKPT_Pos 1
+
569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
+
571 #define SCB_DFSR_HALTED_Pos 0
+
572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
+
574 
+
585 typedef struct
+
586 {
+
587  uint32_t RESERVED0[1];
+
588  __I uint32_t ICTR;
+
589  __IO uint32_t ACTLR;
+
590 } SCnSCB_Type;
+
591 
+
592 /* Interrupt Controller Type Register Definitions */
+
593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0
+
594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
+
596 /* Auxiliary Control Register Definitions */
+
597 #define SCnSCB_ACTLR_DISOOFP_Pos 9
+
598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
+
600 #define SCnSCB_ACTLR_DISFPCA_Pos 8
+
601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
+
603 #define SCnSCB_ACTLR_DISFOLD_Pos 2
+
604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
+
606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1
+
607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
+
609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0
+
610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
+
612 
+
623 typedef struct
+
624 {
+
625  __IO uint32_t CTRL;
+
626  __IO uint32_t LOAD;
+
627  __IO uint32_t VAL;
+
628  __I uint32_t CALIB;
+
629 } SysTick_Type;
+
630 
+
631 /* SysTick Control / Status Register Definitions */
+
632 #define SysTick_CTRL_COUNTFLAG_Pos 16
+
633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
+
635 #define SysTick_CTRL_CLKSOURCE_Pos 2
+
636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
+
638 #define SysTick_CTRL_TICKINT_Pos 1
+
639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
+
641 #define SysTick_CTRL_ENABLE_Pos 0
+
642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
+
644 /* SysTick Reload Register Definitions */
+
645 #define SysTick_LOAD_RELOAD_Pos 0
+
646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
+
648 /* SysTick Current Register Definitions */
+
649 #define SysTick_VAL_CURRENT_Pos 0
+
650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
+
652 /* SysTick Calibration Register Definitions */
+
653 #define SysTick_CALIB_NOREF_Pos 31
+
654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
+
656 #define SysTick_CALIB_SKEW_Pos 30
+
657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
+
659 #define SysTick_CALIB_TENMS_Pos 0
+
660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
+
662 
+
673 typedef struct
+
674 {
+
675  __O union
+
676  {
+
677  __O uint8_t u8;
+
678  __O uint16_t u16;
+
679  __O uint32_t u32;
+
680  } PORT [32];
+
681  uint32_t RESERVED0[864];
+
682  __IO uint32_t TER;
+
683  uint32_t RESERVED1[15];
+
684  __IO uint32_t TPR;
+
685  uint32_t RESERVED2[15];
+
686  __IO uint32_t TCR;
+
687  uint32_t RESERVED3[29];
+
688  __O uint32_t IWR;
+
689  __I uint32_t IRR;
+
690  __IO uint32_t IMCR;
+
691  uint32_t RESERVED4[43];
+
692  __O uint32_t LAR;
+
693  __I uint32_t LSR;
+
694  uint32_t RESERVED5[6];
+
695  __I uint32_t PID4;
+
696  __I uint32_t PID5;
+
697  __I uint32_t PID6;
+
698  __I uint32_t PID7;
+
699  __I uint32_t PID0;
+
700  __I uint32_t PID1;
+
701  __I uint32_t PID2;
+
702  __I uint32_t PID3;
+
703  __I uint32_t CID0;
+
704  __I uint32_t CID1;
+
705  __I uint32_t CID2;
+
706  __I uint32_t CID3;
+
707 } ITM_Type;
+
708 
+
709 /* ITM Trace Privilege Register Definitions */
+
710 #define ITM_TPR_PRIVMASK_Pos 0
+
711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
+
713 /* ITM Trace Control Register Definitions */
+
714 #define ITM_TCR_BUSY_Pos 23
+
715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
+
717 #define ITM_TCR_TraceBusID_Pos 16
+
718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
+
720 #define ITM_TCR_GTSFREQ_Pos 10
+
721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
+
723 #define ITM_TCR_TSPrescale_Pos 8
+
724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
+
726 #define ITM_TCR_SWOENA_Pos 4
+
727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
+
729 #define ITM_TCR_DWTENA_Pos 3
+
730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
+
732 #define ITM_TCR_SYNCENA_Pos 2
+
733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
+
735 #define ITM_TCR_TSENA_Pos 1
+
736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
+
738 #define ITM_TCR_ITMENA_Pos 0
+
739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
+
741 /* ITM Integration Write Register Definitions */
+
742 #define ITM_IWR_ATVALIDM_Pos 0
+
743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos)
+
745 /* ITM Integration Read Register Definitions */
+
746 #define ITM_IRR_ATREADYM_Pos 0
+
747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos)
+
749 /* ITM Integration Mode Control Register Definitions */
+
750 #define ITM_IMCR_INTEGRATION_Pos 0
+
751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos)
+
753 /* ITM Lock Status Register Definitions */
+
754 #define ITM_LSR_ByteAcc_Pos 2
+
755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
+
757 #define ITM_LSR_Access_Pos 1
+
758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
+
760 #define ITM_LSR_Present_Pos 0
+
761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos)
+
763  /* end of group CMSIS_ITM */
+
764 
+
765 
+
774 typedef struct
+
775 {
+
776  __IO uint32_t CTRL;
+
777  __IO uint32_t CYCCNT;
+
778  __IO uint32_t CPICNT;
+
779  __IO uint32_t EXCCNT;
+
780  __IO uint32_t SLEEPCNT;
+
781  __IO uint32_t LSUCNT;
+
782  __IO uint32_t FOLDCNT;
+
783  __I uint32_t PCSR;
+
784  __IO uint32_t COMP0;
+
785  __IO uint32_t MASK0;
+
786  __IO uint32_t FUNCTION0;
+
787  uint32_t RESERVED0[1];
+
788  __IO uint32_t COMP1;
+
789  __IO uint32_t MASK1;
+
790  __IO uint32_t FUNCTION1;
+
791  uint32_t RESERVED1[1];
+
792  __IO uint32_t COMP2;
+
793  __IO uint32_t MASK2;
+
794  __IO uint32_t FUNCTION2;
+
795  uint32_t RESERVED2[1];
+
796  __IO uint32_t COMP3;
+
797  __IO uint32_t MASK3;
+
798  __IO uint32_t FUNCTION3;
+
799 } DWT_Type;
+
800 
+
801 /* DWT Control Register Definitions */
+
802 #define DWT_CTRL_NUMCOMP_Pos 28
+
803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
+
805 #define DWT_CTRL_NOTRCPKT_Pos 27
+
806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
+
808 #define DWT_CTRL_NOEXTTRIG_Pos 26
+
809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
+
811 #define DWT_CTRL_NOCYCCNT_Pos 25
+
812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
+
814 #define DWT_CTRL_NOPRFCNT_Pos 24
+
815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
+
817 #define DWT_CTRL_CYCEVTENA_Pos 22
+
818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
+
820 #define DWT_CTRL_FOLDEVTENA_Pos 21
+
821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
+
823 #define DWT_CTRL_LSUEVTENA_Pos 20
+
824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
+
826 #define DWT_CTRL_SLEEPEVTENA_Pos 19
+
827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
+
829 #define DWT_CTRL_EXCEVTENA_Pos 18
+
830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
+
832 #define DWT_CTRL_CPIEVTENA_Pos 17
+
833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
+
835 #define DWT_CTRL_EXCTRCENA_Pos 16
+
836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
+
838 #define DWT_CTRL_PCSAMPLENA_Pos 12
+
839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
+
841 #define DWT_CTRL_SYNCTAP_Pos 10
+
842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
+
844 #define DWT_CTRL_CYCTAP_Pos 9
+
845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
+
847 #define DWT_CTRL_POSTINIT_Pos 5
+
848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
+
850 #define DWT_CTRL_POSTPRESET_Pos 1
+
851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
+
853 #define DWT_CTRL_CYCCNTENA_Pos 0
+
854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
+
856 /* DWT CPI Count Register Definitions */
+
857 #define DWT_CPICNT_CPICNT_Pos 0
+
858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
+
860 /* DWT Exception Overhead Count Register Definitions */
+
861 #define DWT_EXCCNT_EXCCNT_Pos 0
+
862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
+
864 /* DWT Sleep Count Register Definitions */
+
865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0
+
866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
+
868 /* DWT LSU Count Register Definitions */
+
869 #define DWT_LSUCNT_LSUCNT_Pos 0
+
870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
+
872 /* DWT Folded-instruction Count Register Definitions */
+
873 #define DWT_FOLDCNT_FOLDCNT_Pos 0
+
874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
+
876 /* DWT Comparator Mask Register Definitions */
+
877 #define DWT_MASK_MASK_Pos 0
+
878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
+
880 /* DWT Comparator Function Register Definitions */
+
881 #define DWT_FUNCTION_MATCHED_Pos 24
+
882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
+
884 #define DWT_FUNCTION_DATAVADDR1_Pos 16
+
885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
+
887 #define DWT_FUNCTION_DATAVADDR0_Pos 12
+
888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
+
890 #define DWT_FUNCTION_DATAVSIZE_Pos 10
+
891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
+
893 #define DWT_FUNCTION_LNK1ENA_Pos 9
+
894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
+
896 #define DWT_FUNCTION_DATAVMATCH_Pos 8
+
897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
+
899 #define DWT_FUNCTION_CYCMATCH_Pos 7
+
900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
+
902 #define DWT_FUNCTION_EMITRANGE_Pos 5
+
903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
+
905 #define DWT_FUNCTION_FUNCTION_Pos 0
+
906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
+
908  /* end of group CMSIS_DWT */
+
909 
+
910 
+
919 typedef struct
+
920 {
+
921  __IO uint32_t SSPSR;
+
922  __IO uint32_t CSPSR;
+
923  uint32_t RESERVED0[2];
+
924  __IO uint32_t ACPR;
+
925  uint32_t RESERVED1[55];
+
926  __IO uint32_t SPPR;
+
927  uint32_t RESERVED2[131];
+
928  __I uint32_t FFSR;
+
929  __IO uint32_t FFCR;
+
930  __I uint32_t FSCR;
+
931  uint32_t RESERVED3[759];
+
932  __I uint32_t TRIGGER;
+
933  __I uint32_t FIFO0;
+
934  __I uint32_t ITATBCTR2;
+
935  uint32_t RESERVED4[1];
+
936  __I uint32_t ITATBCTR0;
+
937  __I uint32_t FIFO1;
+
938  __IO uint32_t ITCTRL;
+
939  uint32_t RESERVED5[39];
+
940  __IO uint32_t CLAIMSET;
+
941  __IO uint32_t CLAIMCLR;
+
942  uint32_t RESERVED7[8];
+
943  __I uint32_t DEVID;
+
944  __I uint32_t DEVTYPE;
+
945 } TPI_Type;
+
946 
+
947 /* TPI Asynchronous Clock Prescaler Register Definitions */
+
948 #define TPI_ACPR_PRESCALER_Pos 0
+
949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
+
951 /* TPI Selected Pin Protocol Register Definitions */
+
952 #define TPI_SPPR_TXMODE_Pos 0
+
953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
+
955 /* TPI Formatter and Flush Status Register Definitions */
+
956 #define TPI_FFSR_FtNonStop_Pos 3
+
957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
+
959 #define TPI_FFSR_TCPresent_Pos 2
+
960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
+
962 #define TPI_FFSR_FtStopped_Pos 1
+
963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
+
965 #define TPI_FFSR_FlInProg_Pos 0
+
966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
+
968 /* TPI Formatter and Flush Control Register Definitions */
+
969 #define TPI_FFCR_TrigIn_Pos 8
+
970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
+
972 #define TPI_FFCR_EnFCont_Pos 1
+
973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
+
975 /* TPI TRIGGER Register Definitions */
+
976 #define TPI_TRIGGER_TRIGGER_Pos 0
+
977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
+
979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
+
980 #define TPI_FIFO0_ITM_ATVALID_Pos 29
+
981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
+
983 #define TPI_FIFO0_ITM_bytecount_Pos 27
+
984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
+
986 #define TPI_FIFO0_ETM_ATVALID_Pos 26
+
987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
+
989 #define TPI_FIFO0_ETM_bytecount_Pos 24
+
990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
+
992 #define TPI_FIFO0_ETM2_Pos 16
+
993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
+
995 #define TPI_FIFO0_ETM1_Pos 8
+
996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
+
998 #define TPI_FIFO0_ETM0_Pos 0
+
999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
+
1001 /* TPI ITATBCTR2 Register Definitions */
+
1002 #define TPI_ITATBCTR2_ATREADY_Pos 0
+
1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
+
1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
+
1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29
+
1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
+
1009 #define TPI_FIFO1_ITM_bytecount_Pos 27
+
1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
+
1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26
+
1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
+
1015 #define TPI_FIFO1_ETM_bytecount_Pos 24
+
1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
+
1018 #define TPI_FIFO1_ITM2_Pos 16
+
1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
+
1021 #define TPI_FIFO1_ITM1_Pos 8
+
1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
+
1024 #define TPI_FIFO1_ITM0_Pos 0
+
1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
+
1027 /* TPI ITATBCTR0 Register Definitions */
+
1028 #define TPI_ITATBCTR0_ATREADY_Pos 0
+
1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
+
1031 /* TPI Integration Mode Control Register Definitions */
+
1032 #define TPI_ITCTRL_Mode_Pos 0
+
1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
+
1035 /* TPI DEVID Register Definitions */
+
1036 #define TPI_DEVID_NRZVALID_Pos 11
+
1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
+
1039 #define TPI_DEVID_MANCVALID_Pos 10
+
1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
+
1042 #define TPI_DEVID_PTINVALID_Pos 9
+
1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
+
1045 #define TPI_DEVID_MinBufSz_Pos 6
+
1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
+
1048 #define TPI_DEVID_AsynClkIn_Pos 5
+
1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
+
1051 #define TPI_DEVID_NrTraceInput_Pos 0
+
1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
+
1054 /* TPI DEVTYPE Register Definitions */
+
1055 #define TPI_DEVTYPE_SubType_Pos 0
+
1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
+
1058 #define TPI_DEVTYPE_MajorType_Pos 4
+
1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
+
1061  /* end of group CMSIS_TPI */
+
1062 
+
1063 
+
1064 #if (__MPU_PRESENT == 1)
+
1065 
+
1073 typedef struct
+
1074 {
+
1075  __I uint32_t TYPE;
+
1076  __IO uint32_t CTRL;
+
1077  __IO uint32_t RNR;
+
1078  __IO uint32_t RBAR;
+
1079  __IO uint32_t RASR;
+
1080  __IO uint32_t RBAR_A1;
+
1081  __IO uint32_t RASR_A1;
+
1082  __IO uint32_t RBAR_A2;
+
1083  __IO uint32_t RASR_A2;
+
1084  __IO uint32_t RBAR_A3;
+
1085  __IO uint32_t RASR_A3;
+
1086 } MPU_Type;
+
1087 
+
1088 /* MPU Type Register */
+
1089 #define MPU_TYPE_IREGION_Pos 16
+
1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
+
1092 #define MPU_TYPE_DREGION_Pos 8
+
1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
+
1095 #define MPU_TYPE_SEPARATE_Pos 0
+
1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos)
+
1098 /* MPU Control Register */
+
1099 #define MPU_CTRL_PRIVDEFENA_Pos 2
+
1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
+
1102 #define MPU_CTRL_HFNMIENA_Pos 1
+
1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
+
1105 #define MPU_CTRL_ENABLE_Pos 0
+
1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos)
+
1108 /* MPU Region Number Register */
+
1109 #define MPU_RNR_REGION_Pos 0
+
1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos)
+
1112 /* MPU Region Base Address Register */
+
1113 #define MPU_RBAR_ADDR_Pos 5
+
1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
+
1116 #define MPU_RBAR_VALID_Pos 4
+
1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
+
1119 #define MPU_RBAR_REGION_Pos 0
+
1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos)
+
1122 /* MPU Region Attribute and Size Register */
+
1123 #define MPU_RASR_ATTRS_Pos 16
+
1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
+
1126 #define MPU_RASR_XN_Pos 28
+
1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
+
1129 #define MPU_RASR_AP_Pos 24
+
1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
+
1132 #define MPU_RASR_TEX_Pos 19
+
1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
+
1135 #define MPU_RASR_S_Pos 18
+
1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
+
1138 #define MPU_RASR_C_Pos 17
+
1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
+
1141 #define MPU_RASR_B_Pos 16
+
1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
+
1144 #define MPU_RASR_SRD_Pos 8
+
1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
+
1147 #define MPU_RASR_SIZE_Pos 1
+
1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
+
1150 #define MPU_RASR_ENABLE_Pos 0
+
1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos)
+
1153 
+
1154 #endif
+
1155 
+
1156 
+
1157 #if (__FPU_PRESENT == 1)
+
1158 
+
1166 typedef struct
+
1167 {
+
1168  uint32_t RESERVED0[1];
+
1169  __IO uint32_t FPCCR;
+
1170  __IO uint32_t FPCAR;
+
1171  __IO uint32_t FPDSCR;
+
1172  __I uint32_t MVFR0;
+
1173  __I uint32_t MVFR1;
+
1174 } FPU_Type;
+
1175 
+
1176 /* Floating-Point Context Control Register */
+
1177 #define FPU_FPCCR_ASPEN_Pos 31
+
1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
+
1180 #define FPU_FPCCR_LSPEN_Pos 30
+
1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
+
1183 #define FPU_FPCCR_MONRDY_Pos 8
+
1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
+
1186 #define FPU_FPCCR_BFRDY_Pos 6
+
1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
+
1189 #define FPU_FPCCR_MMRDY_Pos 5
+
1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
+
1192 #define FPU_FPCCR_HFRDY_Pos 4
+
1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
+
1195 #define FPU_FPCCR_THREAD_Pos 3
+
1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
+
1198 #define FPU_FPCCR_USER_Pos 1
+
1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
+
1201 #define FPU_FPCCR_LSPACT_Pos 0
+
1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos)
+
1204 /* Floating-Point Context Address Register */
+
1205 #define FPU_FPCAR_ADDRESS_Pos 3
+
1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
+
1208 /* Floating-Point Default Status Control Register */
+
1209 #define FPU_FPDSCR_AHP_Pos 26
+
1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
+
1212 #define FPU_FPDSCR_DN_Pos 25
+
1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
+
1215 #define FPU_FPDSCR_FZ_Pos 24
+
1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
+
1218 #define FPU_FPDSCR_RMode_Pos 22
+
1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
+
1221 /* Media and FP Feature Register 0 */
+
1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28
+
1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
+
1225 #define FPU_MVFR0_Short_vectors_Pos 24
+
1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
+
1228 #define FPU_MVFR0_Square_root_Pos 20
+
1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
+
1231 #define FPU_MVFR0_Divide_Pos 16
+
1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
+
1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12
+
1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
+
1237 #define FPU_MVFR0_Double_precision_Pos 8
+
1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
+
1240 #define FPU_MVFR0_Single_precision_Pos 4
+
1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
+
1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0
+
1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)
+
1246 /* Media and FP Feature Register 1 */
+
1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28
+
1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
+
1250 #define FPU_MVFR1_FP_HPFP_Pos 24
+
1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
+
1253 #define FPU_MVFR1_D_NaN_mode_Pos 4
+
1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
+
1256 #define FPU_MVFR1_FtZ_mode_Pos 0
+
1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos)
+
1259 
+
1260 #endif
+
1261 
+
1262 
+
1271 typedef struct
+
1272 {
+
1273  __IO uint32_t DHCSR;
+
1274  __O uint32_t DCRSR;
+
1275  __IO uint32_t DCRDR;
+
1276  __IO uint32_t DEMCR;
+
1277 } CoreDebug_Type;
+
1278 
+
1279 /* Debug Halting Control and Status Register */
+
1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16
+
1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
+
1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25
+
1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
+
1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
+
1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
+
1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19
+
1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
+
1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18
+
1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
+
1295 #define CoreDebug_DHCSR_S_HALT_Pos 17
+
1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
+
1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16
+
1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
+
1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
+
1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
+
1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3
+
1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
+
1307 #define CoreDebug_DHCSR_C_STEP_Pos 2
+
1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
+
1310 #define CoreDebug_DHCSR_C_HALT_Pos 1
+
1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
+
1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0
+
1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
+
1316 /* Debug Core Register Selector Register */
+
1317 #define CoreDebug_DCRSR_REGWnR_Pos 16
+
1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
+
1320 #define CoreDebug_DCRSR_REGSEL_Pos 0
+
1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
+
1323 /* Debug Exception and Monitor Control Register */
+
1324 #define CoreDebug_DEMCR_TRCENA_Pos 24
+
1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
+
1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19
+
1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
+
1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18
+
1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
+
1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17
+
1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
+
1336 #define CoreDebug_DEMCR_MON_EN_Pos 16
+
1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
+
1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10
+
1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
+
1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9
+
1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
+
1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8
+
1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
+
1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7
+
1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
+
1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6
+
1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
+
1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5
+
1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
+
1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4
+
1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
+
1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0
+
1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
+
1363 
+
1372 /* Memory mapping of Cortex-M4 Hardware */
+
1373 #define SCS_BASE (0xE000E000UL)
+
1374 #define ITM_BASE (0xE0000000UL)
+
1375 #define DWT_BASE (0xE0001000UL)
+
1376 #define TPI_BASE (0xE0040000UL)
+
1377 #define CoreDebug_BASE (0xE000EDF0UL)
+
1378 #define SysTick_BASE (SCS_BASE + 0x0010UL)
+
1379 #define NVIC_BASE (SCS_BASE + 0x0100UL)
+
1380 #define SCB_BASE (SCS_BASE + 0x0D00UL)
+
1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
+
1383 #define SCB ((SCB_Type *) SCB_BASE )
+
1384 #define SysTick ((SysTick_Type *) SysTick_BASE )
+
1385 #define NVIC ((NVIC_Type *) NVIC_BASE )
+
1386 #define ITM ((ITM_Type *) ITM_BASE )
+
1387 #define DWT ((DWT_Type *) DWT_BASE )
+
1388 #define TPI ((TPI_Type *) TPI_BASE )
+
1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
+
1391 #if (__MPU_PRESENT == 1)
+
1392  #define MPU_BASE (SCS_BASE + 0x0D90UL)
+
1393  #define MPU ((MPU_Type *) MPU_BASE )
+
1394 #endif
+
1395 
+
1396 #if (__FPU_PRESENT == 1)
+
1397  #define FPU_BASE (SCS_BASE + 0x0F30UL)
+
1398  #define FPU ((FPU_Type *) FPU_BASE )
+
1399 #endif
+
1400 
+
1405 /*******************************************************************************
+
1406  * Hardware Abstraction Layer
+
1407  Core Function Interface contains:
+
1408  - Core NVIC Functions
+
1409  - Core SysTick Functions
+
1410  - Core Debug Functions
+
1411  - Core Register Access Functions
+
1412  ******************************************************************************/
+
1418 /* ########################## NVIC functions #################################### */
+
1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+
1436 {
+
1437  uint32_t reg_value;
+
1438  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
1439 
+
1440  reg_value = SCB->AIRCR; /* read old register configuration */
+
1441  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+
1442  reg_value = (reg_value |
+
1443  ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+
1444  (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+
1445  SCB->AIRCR = reg_value;
+
1446 }
+
1447 
+
1448 
+
1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+
1456 {
+
1457  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+
1458 }
+
1459 
+
1460 
+
1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+
1468 {
+
1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+
1470  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+
1471 }
+
1472 
+
1473 
+
1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+
1481 {
+
1482  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+
1483 }
+
1484 
+
1485 
+
1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+
1497 {
+
1498  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+
1499 }
+
1500 
+
1501 
+
1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+
1509 {
+
1510  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+
1511 }
+
1512 
+
1513 
+
1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+
1521 {
+
1522  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+
1523 }
+
1524 
+
1525 
+
1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+
1536 {
+
1537  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+
1538 }
+
1539 
+
1540 
+
1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+
1551 {
+
1552  if(IRQn < 0) {
+
1553  SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+
1554  else {
+
1555  NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+
1556 }
+
1557 
+
1558 
+
1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+
1571 {
+
1572 
+
1573  if(IRQn < 0) {
+
1574  return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+
1575  else {
+
1576  return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+
1577 }
+
1578 
+
1579 
+
1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+
1593 {
+
1594  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
1595  uint32_t PreemptPriorityBits;
+
1596  uint32_t SubPriorityBits;
+
1597 
+
1598  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+
1599  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
1600 
+
1601  return (
+
1602  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+
1603  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+
1604  );
+
1605 }
+
1606 
+
1607 
+
1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+
1621 {
+
1622  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
1623  uint32_t PreemptPriorityBits;
+
1624  uint32_t SubPriorityBits;
+
1625 
+
1626  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+
1627  SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
1628 
+
1629  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+
1630  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+
1631 }
+
1632 
+
1633 
+
1638 __STATIC_INLINE void NVIC_SystemReset(void)
+
1639 {
+
1640  __DSB(); /* Ensure all outstanding memory accesses included
+
1641  buffered write are completed before reset */
+
1642  SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+
1643  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+
1644  SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+
1645  __DSB(); /* Ensure completion of memory access */
+
1646  while(1); /* wait until reset */
+
1647 }
+
1648 
+
1653 /* ################################## SysTick function ############################################ */
+
1660 #if (__Vendor_SysTickConfig == 0)
+
1661 
+
1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+
1678 {
+
1679  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
1680 
+
1681  SysTick->LOAD = ticks - 1; /* set reload register */
+
1682  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+
1683  SysTick->VAL = 0; /* Load the SysTick Counter Value */
+
1684  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+
1685  SysTick_CTRL_TICKINT_Msk |
+
1686  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+
1687  return (0); /* Function successful */
+
1688 }
+
1689 
+
1690 #endif
+
1691 
+
1696 /* ##################################### Debug In/Output function ########################################### */
+
1703 extern volatile int32_t ITM_RxBuffer;
+
1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5
+
1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+
1718 {
+
1719  if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+
1720  (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+
1721  {
+
1722  while (ITM->PORT[0].u32 == 0);
+
1723  ITM->PORT[0].u8 = (uint8_t) ch;
+
1724  }
+
1725  return (ch);
+
1726 }
+
1727 
+
1728 
+
1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+
1737  int32_t ch = -1; /* no character available */
+
1738 
+
1739  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+
1740  ch = ITM_RxBuffer;
+
1741  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+
1742  }
+
1743 
+
1744  return (ch);
+
1745 }
+
1746 
+
1747 
+
1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
+
1756 
+
1757  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+
1758  return (0); /* no character available */
+
1759  } else {
+
1760  return (1); /* character available */
+
1761  }
+
1762 }
+
1763 
+
1766 #endif /* __CORE_CM4_H_DEPENDANT */
+
1767 
+
1768 #endif /* __CMSIS_GENERIC */
+
1769 
+
1770 #ifdef __cplusplus
+
1771 }
+
1772 #endif
+
SysTick_Type::VAL
__IO uint32_t VAL
Definition: core_cm4.h:627
+
ITM
#define ITM
Definition: core_cm4.h:1386
+
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
+
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm4.h:774
+
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f4xx.h:166
+
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm4.h:455
+
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm4.h:1496
+
TPI_Type::CLAIMCLR
__IO uint32_t CLAIMCLR
Definition: core_cm4.h:941
+
ITM_Type::u8
__O uint8_t u8
Definition: core_cm4.h:677
+
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm4.h:1508
+
SCB_Type::CPACR
__IO uint32_t CPACR
Definition: core_cm4.h:390
+
SCB_Type::CFSR
__IO uint32_t CFSR
Definition: core_cm4.h:378
+
TPI_Type::FSCR
__I uint32_t FSCR
Definition: core_cm4.h:930
+
ITM_Type::IRR
__I uint32_t IRR
Definition: core_cm4.h:689
+
TPI_Type::DEVID
__I uint32_t DEVID
Definition: core_cm4.h:943
+
ITM_Type::CID0
__I uint32_t CID0
Definition: core_cm4.h:703
+
ITM_Type::PID4
__I uint32_t PID4
Definition: core_cm4.h:695
+
TPI_Type::FIFO0
__I uint32_t FIFO0
Definition: core_cm4.h:933
+
__I
#define __I
Definition: core_cm4.h:219
+
SCB_Type::DFSR
__IO uint32_t DFSR
Definition: core_cm4.h:380
+
SCB_Type::MMFAR
__IO uint32_t MMFAR
Definition: core_cm4.h:381
+
ITM_Type::TER
__IO uint32_t TER
Definition: core_cm4.h:682
+
SCB_Type::CPUID
__I uint32_t CPUID
Definition: core_cm4.h:370
+
SCB_Type::BFAR
__IO uint32_t BFAR
Definition: core_cm4.h:382
+
DWT_Type::COMP1
__IO uint32_t COMP1
Definition: core_cm4.h:788
+
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm4.h:1455
+
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm4.h:446
+
DWT_Type::COMP0
__IO uint32_t COMP0
Definition: core_cm4.h:784
+
DWT_Type::COMP2
__IO uint32_t COMP2
Definition: core_cm4.h:792
+
ITM_Type::CID2
__I uint32_t CID2
Definition: core_cm4.h:705
+
SCB_Type::HFSR
__IO uint32_t HFSR
Definition: core_cm4.h:379
+
SysTick
#define SysTick
Definition: core_cm4.h:1384
+
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm4.h:1704
+
TPI_Type::FFCR
__IO uint32_t FFCR
Definition: core_cm4.h:929
+
ITM_Type::CID3
__I uint32_t CID3
Definition: core_cm4.h:706
+
IRQn
IRQn
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f4xx.h:174
+
__IO
#define __IO
Definition: core_cm4.h:222
+
DWT_Type::LSUCNT
__IO uint32_t LSUCNT
Definition: core_cm4.h:781
+
TPI_Type::ACPR
__IO uint32_t ACPR
Definition: core_cm4.h:924
+
ITM_Type::TCR
__IO uint32_t TCR
Definition: core_cm4.h:686
+
SCB_Type::SHCSR
__IO uint32_t SHCSR
Definition: core_cm4.h:377
+
TPI_Type::CLAIMSET
__IO uint32_t CLAIMSET
Definition: core_cm4.h:940
+
__O
#define __O
Definition: core_cm4.h:221
+
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
+
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm4.h:1736
+
ITM_Type::u16
__O uint16_t u16
Definition: core_cm4.h:678
+
ITM_Type::u32
__O uint32_t u32
Definition: core_cm4.h:679
+
DWT_Type::MASK0
__IO uint32_t MASK0
Definition: core_cm4.h:785
+
DWT_Type::FUNCTION3
__IO uint32_t FUNCTION3
Definition: core_cm4.h:798
+
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm4.h:274
+
ITM_Type::PID0
__I uint32_t PID0
Definition: core_cm4.h:699
+
CONTROL_Type::w
uint32_t w
Definition: core_cm4.h:322
+
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm4.h:919
+
SCnSCB_Type::ICTR
__I uint32_t ICTR
Definition: core_cm4.h:588
+
TPI_Type::SPPR
__IO uint32_t SPPR
Definition: core_cm4.h:926
+
TPI_Type::FFSR
__I uint32_t FFSR
Definition: core_cm4.h:928
+
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm4.h:1755
+
DWT_Type::FUNCTION2
__IO uint32_t FUNCTION2
Definition: core_cm4.h:794
+
ITM_Type::PID5
__I uint32_t PID5
Definition: core_cm4.h:696
+
SCB_Type::AFSR
__IO uint32_t AFSR
Definition: core_cm4.h:383
+
TPI_Type::SSPSR
__IO uint32_t SSPSR
Definition: core_cm4.h:921
+
ITM_Type::PID2
__I uint32_t PID2
Definition: core_cm4.h:701
+
CoreDebug_Type::DEMCR
__IO uint32_t DEMCR
Definition: core_cm4.h:1276
+
DWT_Type::EXCCNT
__IO uint32_t EXCCNT
Definition: core_cm4.h:779
+
DWT_Type::COMP3
__IO uint32_t COMP3
Definition: core_cm4.h:796
+
NVIC
#define NVIC
Definition: core_cm4.h:1385
+
SysTick_Type::LOAD
__IO uint32_t LOAD
Definition: core_cm4.h:626
+
SCB_Type::VTOR
__IO uint32_t VTOR
Definition: core_cm4.h:372
+
ITM_Type::PID3
__I uint32_t PID3
Definition: core_cm4.h:702
+
SysTick_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm4.h:625
+
xPSR_Type::w
uint32_t w
Definition: core_cm4.h:307
+
TPI_Type::ITCTRL
__IO uint32_t ITCTRL
Definition: core_cm4.h:938
+
ITM_Type::IWR
__O uint32_t IWR
Definition: core_cm4.h:688
+
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm4.h:1467
+
DWT_Type::PCSR
__I uint32_t PCSR
Definition: core_cm4.h:783
+
core_cm4_simd.h
CMSIS Cortex-M4 SIMD Header File.
+
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm4.h:1271
+
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm4.h:368
+
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm4.h:739
+
SCB_Type::DFR
__I uint32_t DFR
Definition: core_cm4.h:385
+
SCB
#define SCB
Definition: core_cm4.h:1383
+
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm4.h:673
+
IPSR_Type::w
uint32_t w
Definition: core_cm4.h:281
+
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
+
CoreDebug_Type::DCRSR
__O uint32_t DCRSR
Definition: core_cm4.h:1274
+
ITM_Type::LAR
__O uint32_t LAR
Definition: core_cm4.h:692
+
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm4.h:1435
+
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm4.h:1677
+
ITM_Type::LSR
__I uint32_t LSR
Definition: core_cm4.h:693
+
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm4.h:1570
+
SCB_Type::SCR
__IO uint32_t SCR
Definition: core_cm4.h:374
+
APSR_Type::w
uint32_t w
Definition: core_cm4.h:268
+
DWT_Type::FUNCTION1
__IO uint32_t FUNCTION1
Definition: core_cm4.h:790
+
DWT_Type::CYCCNT
__IO uint32_t CYCCNT
Definition: core_cm4.h:777
+
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm4.h:454
+
SysTick_Type::CALIB
__I uint32_t CALIB
Definition: core_cm4.h:628
+
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm4.h:585
+
ITM_Type::CID1
__I uint32_t CID1
Definition: core_cm4.h:704
+
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm4.h:1550
+
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm4.h:336
+
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm4.h:623
+
ITM_Type::PID1
__I uint32_t PID1
Definition: core_cm4.h:700
+
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm4.h:445
+
TPI_Type::TRIGGER
__I uint32_t TRIGGER
Definition: core_cm4.h:932
+
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm4.h:1638
+
SCB_Type::AIRCR
__IO uint32_t AIRCR
Definition: core_cm4.h:373
+
CoreDebug_Type::DCRDR
__IO uint32_t DCRDR
Definition: core_cm4.h:1275
+
TPI_Type::DEVTYPE
__I uint32_t DEVTYPE
Definition: core_cm4.h:944
+
NVIC_Type::STIR
__O uint32_t STIR
Definition: core_cm4.h:350
+
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm4.h:458
+
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm4.h:251
+
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Decode Priority.
Definition: core_cm4.h:1620
+
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm4.h:1480
+
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm4.h:646
+
DWT_Type::MASK3
__IO uint32_t MASK3
Definition: core_cm4.h:797
+
DWT_Type::MASK2
__IO uint32_t MASK2
Definition: core_cm4.h:793
+
TPI_Type::ITATBCTR0
__I uint32_t ITATBCTR0
Definition: core_cm4.h:936
+
TPI_Type::FIFO1
__I uint32_t FIFO1
Definition: core_cm4.h:937
+
SCnSCB_Type::ACTLR
__IO uint32_t ACTLR
Definition: core_cm4.h:589
+
DWT_Type::CTRL
__IO uint32_t CTRL
Definition: core_cm4.h:776
+
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm4.h:313
+
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:636
+
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:642
+
DWT_Type::MASK1
__IO uint32_t MASK1
Definition: core_cm4.h:789
+
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm4.h:1520
+
DWT_Type::FOLDCNT
__IO uint32_t FOLDCNT
Definition: core_cm4.h:782
+
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm4.h:1592
+
SCB_Type::CCR
__IO uint32_t CCR
Definition: core_cm4.h:375
+
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
+
CoreDebug_Type::DHCSR
__IO uint32_t DHCSR
Definition: core_cm4.h:1273
+
DWT_Type::FUNCTION0
__IO uint32_t FUNCTION0
Definition: core_cm4.h:786
+
TPI_Type::CSPSR
__IO uint32_t CSPSR
Definition: core_cm4.h:922
+
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm4.h:1535
+
DWT_Type::CPICNT
__IO uint32_t CPICNT
Definition: core_cm4.h:778
+
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm4.h:287
+
ITM_Type::TPR
__IO uint32_t TPR
Definition: core_cm4.h:684
+
SCB_Type::ICSR
__IO uint32_t ICSR
Definition: core_cm4.h:371
+
ITM_Type::IMCR
__IO uint32_t IMCR
Definition: core_cm4.h:690
+
ITM_Type::PID7
__I uint32_t PID7
Definition: core_cm4.h:698
+
DWT_Type::SLEEPCNT
__IO uint32_t SLEEPCNT
Definition: core_cm4.h:780
+
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:639
+
TPI_Type::ITATBCTR2
__I uint32_t ITATBCTR2
Definition: core_cm4.h:934
+
ITM_Type::PID6
__I uint32_t PID6
Definition: core_cm4.h:697
+
SCB_Type::ADR
__I uint32_t ADR
Definition: core_cm4.h:386
+
SysTick_IRQn
Definition: stm32f4xx.h:184
+
+ +
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+ + diff --git a/core__cm4__simd_8h.html b/core__cm4__simd_8h.html new file mode 100644 index 0000000..1f33068 --- /dev/null +++ b/core__cm4__simd_8h.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cm4_simd.h File Reference + + + + + + + + + + +
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+

CMSIS Cortex-M4 SIMD Header File.

+
Version
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+
Date
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+
Note
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
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core_cm4_simd.h
+
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+Go to the documentation of this file.
1 /**************************************************************************/
+
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
+
11 
+
12  All rights reserved.
+
13  Redistribution and use in source and binary forms, with or without
+
14  modification, are permitted provided that the following conditions are met:
+
15  - Redistributions of source code must retain the above copyright
+
16  notice, this list of conditions and the following disclaimer.
+
17  - Redistributions in binary form must reproduce the above copyright
+
18  notice, this list of conditions and the following disclaimer in the
+
19  documentation and/or other materials provided with the distribution.
+
20  - Neither the name of ARM nor the names of its contributors may be used
+
21  to endorse or promote products derived from this software without
+
22  specific prior written permission.
+
23  *
+
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
34  POSSIBILITY OF SUCH DAMAGE.
+
35  ---------------------------------------------------------------------------*/
+
36 
+
37 
+
38 #ifdef __cplusplus
+
39  extern "C" {
+
40 #endif
+
41 
+
42 #ifndef __CORE_CM4_SIMD_H
+
43 #define __CORE_CM4_SIMD_H
+
44 
+
45 
+
46 /*******************************************************************************
+
47  * Hardware Abstraction Layer
+
48  ******************************************************************************/
+
49 
+
50 
+
51 /* ################### Compiler specific Intrinsics ########################### */
+
57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
58 /* ARM armcc specific functions */
+
59 
+
60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+
61 #define __SADD8 __sadd8
+
62 #define __QADD8 __qadd8
+
63 #define __SHADD8 __shadd8
+
64 #define __UADD8 __uadd8
+
65 #define __UQADD8 __uqadd8
+
66 #define __UHADD8 __uhadd8
+
67 #define __SSUB8 __ssub8
+
68 #define __QSUB8 __qsub8
+
69 #define __SHSUB8 __shsub8
+
70 #define __USUB8 __usub8
+
71 #define __UQSUB8 __uqsub8
+
72 #define __UHSUB8 __uhsub8
+
73 #define __SADD16 __sadd16
+
74 #define __QADD16 __qadd16
+
75 #define __SHADD16 __shadd16
+
76 #define __UADD16 __uadd16
+
77 #define __UQADD16 __uqadd16
+
78 #define __UHADD16 __uhadd16
+
79 #define __SSUB16 __ssub16
+
80 #define __QSUB16 __qsub16
+
81 #define __SHSUB16 __shsub16
+
82 #define __USUB16 __usub16
+
83 #define __UQSUB16 __uqsub16
+
84 #define __UHSUB16 __uhsub16
+
85 #define __SASX __sasx
+
86 #define __QASX __qasx
+
87 #define __SHASX __shasx
+
88 #define __UASX __uasx
+
89 #define __UQASX __uqasx
+
90 #define __UHASX __uhasx
+
91 #define __SSAX __ssax
+
92 #define __QSAX __qsax
+
93 #define __SHSAX __shsax
+
94 #define __USAX __usax
+
95 #define __UQSAX __uqsax
+
96 #define __UHSAX __uhsax
+
97 #define __USAD8 __usad8
+
98 #define __USADA8 __usada8
+
99 #define __SSAT16 __ssat16
+
100 #define __USAT16 __usat16
+
101 #define __UXTB16 __uxtb16
+
102 #define __UXTAB16 __uxtab16
+
103 #define __SXTB16 __sxtb16
+
104 #define __SXTAB16 __sxtab16
+
105 #define __SMUAD __smuad
+
106 #define __SMUADX __smuadx
+
107 #define __SMLAD __smlad
+
108 #define __SMLADX __smladx
+
109 #define __SMLALD __smlald
+
110 #define __SMLALDX __smlaldx
+
111 #define __SMUSD __smusd
+
112 #define __SMUSDX __smusdx
+
113 #define __SMLSD __smlsd
+
114 #define __SMLSDX __smlsdx
+
115 #define __SMLSLD __smlsld
+
116 #define __SMLSLDX __smlsldx
+
117 #define __SEL __sel
+
118 #define __QADD __qadd
+
119 #define __QSUB __qsub
+
120 
+
121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+
122  ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
123 
+
124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+
125  ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
126 
+
127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+
128  ((int64_t)(ARG3) << 32) ) >> 32))
+
129 
+
130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
131 
+
132 
+
133 
+
134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+
135 /* IAR iccarm specific functions */
+
136 
+
137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+
138 #include <cmsis_iar.h>
+
139 
+
140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
141 
+
142 
+
143 
+
144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+
145 /* TI CCS specific functions */
+
146 
+
147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+
148 #include <cmsis_ccs.h>
+
149 
+
150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
151 
+
152 
+
153 
+
154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+
155 /* GNU gcc specific functions */
+
156 
+
157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+
158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+
159 {
+
160  uint32_t result;
+
161 
+
162  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
163  return(result);
+
164 }
+
165 
+
166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+
167 {
+
168  uint32_t result;
+
169 
+
170  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
171  return(result);
+
172 }
+
173 
+
174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+
175 {
+
176  uint32_t result;
+
177 
+
178  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
179  return(result);
+
180 }
+
181 
+
182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+
183 {
+
184  uint32_t result;
+
185 
+
186  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
187  return(result);
+
188 }
+
189 
+
190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+
191 {
+
192  uint32_t result;
+
193 
+
194  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
195  return(result);
+
196 }
+
197 
+
198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+
199 {
+
200  uint32_t result;
+
201 
+
202  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
203  return(result);
+
204 }
+
205 
+
206 
+
207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+
208 {
+
209  uint32_t result;
+
210 
+
211  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
212  return(result);
+
213 }
+
214 
+
215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+
216 {
+
217  uint32_t result;
+
218 
+
219  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
220  return(result);
+
221 }
+
222 
+
223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+
224 {
+
225  uint32_t result;
+
226 
+
227  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
228  return(result);
+
229 }
+
230 
+
231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+
232 {
+
233  uint32_t result;
+
234 
+
235  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
236  return(result);
+
237 }
+
238 
+
239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+
240 {
+
241  uint32_t result;
+
242 
+
243  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
244  return(result);
+
245 }
+
246 
+
247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+
248 {
+
249  uint32_t result;
+
250 
+
251  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
252  return(result);
+
253 }
+
254 
+
255 
+
256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+
257 {
+
258  uint32_t result;
+
259 
+
260  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
261  return(result);
+
262 }
+
263 
+
264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+
265 {
+
266  uint32_t result;
+
267 
+
268  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
269  return(result);
+
270 }
+
271 
+
272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+
273 {
+
274  uint32_t result;
+
275 
+
276  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
277  return(result);
+
278 }
+
279 
+
280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+
281 {
+
282  uint32_t result;
+
283 
+
284  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
285  return(result);
+
286 }
+
287 
+
288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+
289 {
+
290  uint32_t result;
+
291 
+
292  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
293  return(result);
+
294 }
+
295 
+
296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+
297 {
+
298  uint32_t result;
+
299 
+
300  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
301  return(result);
+
302 }
+
303 
+
304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+
305 {
+
306  uint32_t result;
+
307 
+
308  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
309  return(result);
+
310 }
+
311 
+
312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+
313 {
+
314  uint32_t result;
+
315 
+
316  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
317  return(result);
+
318 }
+
319 
+
320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+
321 {
+
322  uint32_t result;
+
323 
+
324  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
325  return(result);
+
326 }
+
327 
+
328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+
329 {
+
330  uint32_t result;
+
331 
+
332  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
333  return(result);
+
334 }
+
335 
+
336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+
337 {
+
338  uint32_t result;
+
339 
+
340  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
341  return(result);
+
342 }
+
343 
+
344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+
345 {
+
346  uint32_t result;
+
347 
+
348  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
349  return(result);
+
350 }
+
351 
+
352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+
353 {
+
354  uint32_t result;
+
355 
+
356  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
357  return(result);
+
358 }
+
359 
+
360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+
361 {
+
362  uint32_t result;
+
363 
+
364  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
365  return(result);
+
366 }
+
367 
+
368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+
369 {
+
370  uint32_t result;
+
371 
+
372  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
373  return(result);
+
374 }
+
375 
+
376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+
377 {
+
378  uint32_t result;
+
379 
+
380  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
381  return(result);
+
382 }
+
383 
+
384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+
385 {
+
386  uint32_t result;
+
387 
+
388  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
389  return(result);
+
390 }
+
391 
+
392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+
393 {
+
394  uint32_t result;
+
395 
+
396  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
397  return(result);
+
398 }
+
399 
+
400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+
401 {
+
402  uint32_t result;
+
403 
+
404  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
405  return(result);
+
406 }
+
407 
+
408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+
409 {
+
410  uint32_t result;
+
411 
+
412  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
413  return(result);
+
414 }
+
415 
+
416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+
417 {
+
418  uint32_t result;
+
419 
+
420  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
421  return(result);
+
422 }
+
423 
+
424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+
425 {
+
426  uint32_t result;
+
427 
+
428  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
429  return(result);
+
430 }
+
431 
+
432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+
433 {
+
434  uint32_t result;
+
435 
+
436  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
437  return(result);
+
438 }
+
439 
+
440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+
441 {
+
442  uint32_t result;
+
443 
+
444  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
445  return(result);
+
446 }
+
447 
+
448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+
449 {
+
450  uint32_t result;
+
451 
+
452  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
453  return(result);
+
454 }
+
455 
+
456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+
457 {
+
458  uint32_t result;
+
459 
+
460  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+
461  return(result);
+
462 }
+
463 
+
464 #define __SSAT16(ARG1,ARG2) \
+
465 ({ \
+
466  uint32_t __RES, __ARG1 = (ARG1); \
+
467  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+
468  __RES; \
+
469  })
+
470 
+
471 #define __USAT16(ARG1,ARG2) \
+
472 ({ \
+
473  uint32_t __RES, __ARG1 = (ARG1); \
+
474  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+
475  __RES; \
+
476  })
+
477 
+
478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+
479 {
+
480  uint32_t result;
+
481 
+
482  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+
483  return(result);
+
484 }
+
485 
+
486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+
487 {
+
488  uint32_t result;
+
489 
+
490  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
491  return(result);
+
492 }
+
493 
+
494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+
495 {
+
496  uint32_t result;
+
497 
+
498  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+
499  return(result);
+
500 }
+
501 
+
502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+
503 {
+
504  uint32_t result;
+
505 
+
506  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
507  return(result);
+
508 }
+
509 
+
510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+
511 {
+
512  uint32_t result;
+
513 
+
514  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
515  return(result);
+
516 }
+
517 
+
518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+
519 {
+
520  uint32_t result;
+
521 
+
522  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
523  return(result);
+
524 }
+
525 
+
526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+
527 {
+
528  uint32_t result;
+
529 
+
530  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+
531  return(result);
+
532 }
+
533 
+
534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+
535 {
+
536  uint32_t result;
+
537 
+
538  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+
539  return(result);
+
540 }
+
541 
+
542 #define __SMLALD(ARG1,ARG2,ARG3) \
+
543 ({ \
+
544  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+
545  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+
546  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+
547  })
+
548 
+
549 #define __SMLALDX(ARG1,ARG2,ARG3) \
+
550 ({ \
+
551  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+
552  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+
553  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+
554  })
+
555 
+
556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+
557 {
+
558  uint32_t result;
+
559 
+
560  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
561  return(result);
+
562 }
+
563 
+
564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+
565 {
+
566  uint32_t result;
+
567 
+
568  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
569  return(result);
+
570 }
+
571 
+
572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+
573 {
+
574  uint32_t result;
+
575 
+
576  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+
577  return(result);
+
578 }
+
579 
+
580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+
581 {
+
582  uint32_t result;
+
583 
+
584  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+
585  return(result);
+
586 }
+
587 
+
588 #define __SMLSLD(ARG1,ARG2,ARG3) \
+
589 ({ \
+
590  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+
591  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+
592  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+
593  })
+
594 
+
595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
+
596 ({ \
+
597  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+
598  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+
599  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+
600  })
+
601 
+
602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+
603 {
+
604  uint32_t result;
+
605 
+
606  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
607  return(result);
+
608 }
+
609 
+
610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+
611 {
+
612  uint32_t result;
+
613 
+
614  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
615  return(result);
+
616 }
+
617 
+
618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+
619 {
+
620  uint32_t result;
+
621 
+
622  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+
623  return(result);
+
624 }
+
625 
+
626 #define __PKHBT(ARG1,ARG2,ARG3) \
+
627 ({ \
+
628  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+
629  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+
630  __RES; \
+
631  })
+
632 
+
633 #define __PKHTB(ARG1,ARG2,ARG3) \
+
634 ({ \
+
635  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+
636  if (ARG3 == 0) \
+
637  __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+
638  else \
+
639  __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+
640  __RES; \
+
641  })
+
642 
+
643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+
644 {
+
645  int32_t result;
+
646 
+
647  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+
648  return(result);
+
649 }
+
650 
+
651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
652 
+
653 
+
654 
+
655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+
656 /* TASKING carm specific functions */
+
657 
+
658 
+
659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+
660 /* not yet supported */
+
661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
662 
+
663 
+
664 #endif
+
665 
+
669 #endif /* __CORE_CM4_SIMD_H */
+
670 
+
671 #ifdef __cplusplus
+
672 }
+
673 #endif
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/core__cm_func_8h.html b/core__cm_func_8h.html new file mode 100644 index 0000000..2216f35 --- /dev/null +++ b/core__cm_func_8h.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cmFunc.h File Reference + + + + + + + + + + +
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core_cmFunc.h File Reference
+
+
+ +

CMSIS Cortex-M Core Function Access Header File. +More...

+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
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+

Detailed Description

+

CMSIS Cortex-M Core Function Access Header File.

+
Version
V3.20
+
Date
25. February 2013
+
Note
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/core__cm_func_8h__dep__incl.map b/core__cm_func_8h__dep__incl.map new file mode 100644 index 0000000..c3edcec --- /dev/null +++ b/core__cm_func_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/core__cm_func_8h__dep__incl.md5 b/core__cm_func_8h__dep__incl.md5 new file mode 100644 index 0000000..bd8eb72 --- /dev/null +++ b/core__cm_func_8h__dep__incl.md5 @@ -0,0 +1 @@ +aad051d8dc04d599bb9dfdbe231a50dd \ No newline at end of file diff --git a/core__cm_func_8h__dep__incl.png b/core__cm_func_8h__dep__incl.png new file mode 100644 index 0000000..bc4bb45 Binary files /dev/null and b/core__cm_func_8h__dep__incl.png differ diff --git a/core__cm_func_8h_source.html b/core__cm_func_8h_source.html new file mode 100644 index 0000000..1ba178c --- /dev/null +++ b/core__cm_func_8h_source.html @@ -0,0 +1,487 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cmFunc.h Source File + + + + + + + + + + +
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core_cmFunc.h
+
+
+Go to the documentation of this file.
1 /**************************************************************************/
+
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
+
11 
+
12  All rights reserved.
+
13  Redistribution and use in source and binary forms, with or without
+
14  modification, are permitted provided that the following conditions are met:
+
15  - Redistributions of source code must retain the above copyright
+
16  notice, this list of conditions and the following disclaimer.
+
17  - Redistributions in binary form must reproduce the above copyright
+
18  notice, this list of conditions and the following disclaimer in the
+
19  documentation and/or other materials provided with the distribution.
+
20  - Neither the name of ARM nor the names of its contributors may be used
+
21  to endorse or promote products derived from this software without
+
22  specific prior written permission.
+
23  *
+
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
34  POSSIBILITY OF SUCH DAMAGE.
+
35  ---------------------------------------------------------------------------*/
+
36 
+
37 
+
38 #ifndef __CORE_CMFUNC_H
+
39 #define __CORE_CMFUNC_H
+
40 
+
41 
+
42 /* ########################### Core Function Access ########################### */
+
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
49 /* ARM armcc specific functions */
+
50 
+
51 #if (__ARMCC_VERSION < 400677)
+
52  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+
53 #endif
+
54 
+
55 /* intrinsic void __enable_irq(); */
+
56 /* intrinsic void __disable_irq(); */
+
57 
+
64 __STATIC_INLINE uint32_t __get_CONTROL(void)
+
65 {
+
66  register uint32_t __regControl __ASM("control");
+
67  return(__regControl);
+
68 }
+
69 
+
70 
+
77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
+
78 {
+
79  register uint32_t __regControl __ASM("control");
+
80  __regControl = control;
+
81 }
+
82 
+
83 
+
90 __STATIC_INLINE uint32_t __get_IPSR(void)
+
91 {
+
92  register uint32_t __regIPSR __ASM("ipsr");
+
93  return(__regIPSR);
+
94 }
+
95 
+
96 
+
103 __STATIC_INLINE uint32_t __get_APSR(void)
+
104 {
+
105  register uint32_t __regAPSR __ASM("apsr");
+
106  return(__regAPSR);
+
107 }
+
108 
+
109 
+
116 __STATIC_INLINE uint32_t __get_xPSR(void)
+
117 {
+
118  register uint32_t __regXPSR __ASM("xpsr");
+
119  return(__regXPSR);
+
120 }
+
121 
+
122 
+
129 __STATIC_INLINE uint32_t __get_PSP(void)
+
130 {
+
131  register uint32_t __regProcessStackPointer __ASM("psp");
+
132  return(__regProcessStackPointer);
+
133 }
+
134 
+
135 
+
142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+
143 {
+
144  register uint32_t __regProcessStackPointer __ASM("psp");
+
145  __regProcessStackPointer = topOfProcStack;
+
146 }
+
147 
+
148 
+
155 __STATIC_INLINE uint32_t __get_MSP(void)
+
156 {
+
157  register uint32_t __regMainStackPointer __ASM("msp");
+
158  return(__regMainStackPointer);
+
159 }
+
160 
+
161 
+
168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+
169 {
+
170  register uint32_t __regMainStackPointer __ASM("msp");
+
171  __regMainStackPointer = topOfMainStack;
+
172 }
+
173 
+
174 
+
181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
+
182 {
+
183  register uint32_t __regPriMask __ASM("primask");
+
184  return(__regPriMask);
+
185 }
+
186 
+
187 
+
194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+
195 {
+
196  register uint32_t __regPriMask __ASM("primask");
+
197  __regPriMask = (priMask);
+
198 }
+
199 
+
200 
+
201 #if (__CORTEX_M >= 0x03)
+
202 
+
208 #define __enable_fault_irq __enable_fiq
+
209 
+
210 
+
216 #define __disable_fault_irq __disable_fiq
+
217 
+
218 
+
225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
+
226 {
+
227  register uint32_t __regBasePri __ASM("basepri");
+
228  return(__regBasePri);
+
229 }
+
230 
+
231 
+
238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+
239 {
+
240  register uint32_t __regBasePri __ASM("basepri");
+
241  __regBasePri = (basePri & 0xff);
+
242 }
+
243 
+
244 
+
251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+
252 {
+
253  register uint32_t __regFaultMask __ASM("faultmask");
+
254  return(__regFaultMask);
+
255 }
+
256 
+
257 
+
264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+
265 {
+
266  register uint32_t __regFaultMask __ASM("faultmask");
+
267  __regFaultMask = (faultMask & (uint32_t)1);
+
268 }
+
269 
+
270 #endif /* (__CORTEX_M >= 0x03) */
+
271 
+
272 
+
273 #if (__CORTEX_M == 0x04)
+
274 
+
281 __STATIC_INLINE uint32_t __get_FPSCR(void)
+
282 {
+
283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+
284  register uint32_t __regfpscr __ASM("fpscr");
+
285  return(__regfpscr);
+
286 #else
+
287  return(0);
+
288 #endif
+
289 }
+
290 
+
291 
+
298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+
299 {
+
300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+
301  register uint32_t __regfpscr __ASM("fpscr");
+
302  __regfpscr = (fpscr);
+
303 #endif
+
304 }
+
305 
+
306 #endif /* (__CORTEX_M == 0x04) */
+
307 
+
308 
+
309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+
310 /* IAR iccarm specific functions */
+
311 
+
312 #include <cmsis_iar.h>
+
313 
+
314 
+
315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+
316 /* TI CCS specific functions */
+
317 
+
318 #include <cmsis_ccs.h>
+
319 
+
320 
+
321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+
322 /* GNU gcc specific functions */
+
323 
+
329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+
330 {
+
331  __ASM volatile ("cpsie i" : : : "memory");
+
332 }
+
333 
+
334 
+
340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+
341 {
+
342  __ASM volatile ("cpsid i" : : : "memory");
+
343 }
+
344 
+
345 
+
352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+
353 {
+
354  uint32_t result;
+
355 
+
356  __ASM volatile ("MRS %0, control" : "=r" (result) );
+
357  return(result);
+
358 }
+
359 
+
360 
+
367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+
368 {
+
369  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+
370 }
+
371 
+
372 
+
379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+
380 {
+
381  uint32_t result;
+
382 
+
383  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+
384  return(result);
+
385 }
+
386 
+
387 
+
394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+
395 {
+
396  uint32_t result;
+
397 
+
398  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+
399  return(result);
+
400 }
+
401 
+
402 
+
409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+
410 {
+
411  uint32_t result;
+
412 
+
413  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+
414  return(result);
+
415 }
+
416 
+
417 
+
424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+
425 {
+
426  register uint32_t result;
+
427 
+
428  __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+
429  return(result);
+
430 }
+
431 
+
432 
+
439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+
440 {
+
441  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+
442 }
+
443 
+
444 
+
451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+
452 {
+
453  register uint32_t result;
+
454 
+
455  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+
456  return(result);
+
457 }
+
458 
+
459 
+
466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+
467 {
+
468  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+
469 }
+
470 
+
471 
+
478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+
479 {
+
480  uint32_t result;
+
481 
+
482  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+
483  return(result);
+
484 }
+
485 
+
486 
+
493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+
494 {
+
495  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+
496 }
+
497 
+
498 
+
499 #if (__CORTEX_M >= 0x03)
+
500 
+
506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+
507 {
+
508  __ASM volatile ("cpsie f" : : : "memory");
+
509 }
+
510 
+
511 
+
517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+
518 {
+
519  __ASM volatile ("cpsid f" : : : "memory");
+
520 }
+
521 
+
522 
+
529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+
530 {
+
531  uint32_t result;
+
532 
+
533  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+
534  return(result);
+
535 }
+
536 
+
537 
+
544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+
545 {
+
546  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+
547 }
+
548 
+
549 
+
556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+
557 {
+
558  uint32_t result;
+
559 
+
560  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+
561  return(result);
+
562 }
+
563 
+
564 
+
571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+
572 {
+
573  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+
574 }
+
575 
+
576 #endif /* (__CORTEX_M >= 0x03) */
+
577 
+
578 
+
579 #if (__CORTEX_M == 0x04)
+
580 
+
587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+
588 {
+
589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+
590  uint32_t result;
+
591 
+
592  /* Empty asm statement works as a scheduling barrier */
+
593  __ASM volatile ("");
+
594  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+
595  __ASM volatile ("");
+
596  return(result);
+
597 #else
+
598  return(0);
+
599 #endif
+
600 }
+
601 
+
602 
+
609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+
610 {
+
611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+
612  /* Empty asm statement works as a scheduling barrier */
+
613  __ASM volatile ("");
+
614  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+
615  __ASM volatile ("");
+
616 #endif
+
617 }
+
618 
+
619 #endif /* (__CORTEX_M == 0x04) */
+
620 
+
621 
+
622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+
623 /* TASKING carm specific functions */
+
624 
+
625 /*
+
626  * The CMSIS functions have been implemented as intrinsics in the compiler.
+
627  * Please use "carm -?i" to get an up to date list of all instrinsics,
+
628  * Including the CMSIS ones.
+
629  */
+
630 
+
631 #endif
+
632 
+
636 #endif /* __CORE_CMFUNC_H */
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/core__cm_instr_8h.html b/core__cm_instr_8h.html new file mode 100644 index 0000000..8ec4412 --- /dev/null +++ b/core__cm_instr_8h.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cmInstr.h File Reference + + + + + + + + + + +
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core_cmInstr.h File Reference
+
+
+ +

CMSIS Cortex-M Core Instruction Access Header File. +More...

+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
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+

Go to the source code of this file.

+

Detailed Description

+

CMSIS Cortex-M Core Instruction Access Header File.

+
Version
V3.20
+
Date
05. March 2013
+
Note
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/core__cm_instr_8h__dep__incl.map b/core__cm_instr_8h__dep__incl.map new file mode 100644 index 0000000..7c2d8fa --- /dev/null +++ b/core__cm_instr_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/core__cm_instr_8h__dep__incl.md5 b/core__cm_instr_8h__dep__incl.md5 new file mode 100644 index 0000000..b31a6d5 --- /dev/null +++ b/core__cm_instr_8h__dep__incl.md5 @@ -0,0 +1 @@ +13251e146b95ff9195458e4f7dae1453 \ No newline at end of file diff --git a/core__cm_instr_8h__dep__incl.png b/core__cm_instr_8h__dep__incl.png new file mode 100644 index 0000000..ed85043 Binary files /dev/null and b/core__cm_instr_8h__dep__incl.png differ diff --git a/core__cm_instr_8h_source.html b/core__cm_instr_8h_source.html new file mode 100644 index 0000000..b5327ca --- /dev/null +++ b/core__cm_instr_8h_source.html @@ -0,0 +1,467 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/core_cmInstr.h Source File + + + + + + + + + + +
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core_cmInstr.h
+
+
+Go to the documentation of this file.
1 /**************************************************************************/
+
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
+
11 
+
12  All rights reserved.
+
13  Redistribution and use in source and binary forms, with or without
+
14  modification, are permitted provided that the following conditions are met:
+
15  - Redistributions of source code must retain the above copyright
+
16  notice, this list of conditions and the following disclaimer.
+
17  - Redistributions in binary form must reproduce the above copyright
+
18  notice, this list of conditions and the following disclaimer in the
+
19  documentation and/or other materials provided with the distribution.
+
20  - Neither the name of ARM nor the names of its contributors may be used
+
21  to endorse or promote products derived from this software without
+
22  specific prior written permission.
+
23  *
+
24  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
25  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
26  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+
27  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+
28  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+
29  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+
30  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+
31  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+
32  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+
33  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+
34  POSSIBILITY OF SUCH DAMAGE.
+
35  ---------------------------------------------------------------------------*/
+
36 
+
37 
+
38 #ifndef __CORE_CMINSTR_H
+
39 #define __CORE_CMINSTR_H
+
40 
+
41 
+
42 /* ########################## Core Instruction Access ######################### */
+
48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
49 /* ARM armcc specific functions */
+
50 
+
51 #if (__ARMCC_VERSION < 400677)
+
52  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+
53 #endif
+
54 
+
55 
+
60 #define __NOP __nop
+
61 
+
62 
+
68 #define __WFI __wfi
+
69 
+
70 
+
76 #define __WFE __wfe
+
77 
+
78 
+
83 #define __SEV __sev
+
84 
+
85 
+
92 #define __ISB() __isb(0xF)
+
93 
+
94 
+
100 #define __DSB() __dsb(0xF)
+
101 
+
102 
+
108 #define __DMB() __dmb(0xF)
+
109 
+
110 
+
118 #define __REV __rev
+
119 
+
120 
+
128 #ifndef __NO_EMBEDDED_ASM
+
129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+
130 {
+
131  rev16 r0, r0
+
132  bx lr
+
133 }
+
134 #endif
+
135 
+
143 #ifndef __NO_EMBEDDED_ASM
+
144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+
145 {
+
146  revsh r0, r0
+
147  bx lr
+
148 }
+
149 #endif
+
150 
+
151 
+
160 #define __ROR __ror
+
161 
+
162 
+
171 #define __BKPT(value) __breakpoint(value)
+
172 
+
173 
+
174 #if (__CORTEX_M >= 0x03)
+
175 
+
183 #define __RBIT __rbit
+
184 
+
185 
+
193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
194 
+
195 
+
203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
204 
+
205 
+
213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
214 
+
215 
+
225 #define __STREXB(value, ptr) __strex(value, ptr)
+
226 
+
227 
+
237 #define __STREXH(value, ptr) __strex(value, ptr)
+
238 
+
239 
+
249 #define __STREXW(value, ptr) __strex(value, ptr)
+
250 
+
251 
+
257 #define __CLREX __clrex
+
258 
+
259 
+
268 #define __SSAT __ssat
+
269 
+
270 
+
279 #define __USAT __usat
+
280 
+
281 
+
289 #define __CLZ __clz
+
290 
+
291 #endif /* (__CORTEX_M >= 0x03) */
+
292 
+
293 
+
294 
+
295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+
296 /* IAR iccarm specific functions */
+
297 
+
298 #include <cmsis_iar.h>
+
299 
+
300 
+
301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+
302 /* TI CCS specific functions */
+
303 
+
304 #include <cmsis_ccs.h>
+
305 
+
306 
+
307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+
308 /* GNU gcc specific functions */
+
309 
+
310 /* Define macros for porting to both thumb1 and thumb2.
+
311  * For thumb1, use low register (r0-r7), specified by constrant "l"
+
312  * Otherwise, use general registers, specified by constrant "r" */
+
313 #if defined (__thumb__) && !defined (__thumb2__)
+
314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+
315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
+
316 #else
+
317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+
318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
+
319 #endif
+
320 
+
325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+
326 {
+
327  __ASM volatile ("nop");
+
328 }
+
329 
+
330 
+
336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+
337 {
+
338  __ASM volatile ("wfi");
+
339 }
+
340 
+
341 
+
347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+
348 {
+
349  __ASM volatile ("wfe");
+
350 }
+
351 
+
352 
+
357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+
358 {
+
359  __ASM volatile ("sev");
+
360 }
+
361 
+
362 
+
369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+
370 {
+
371  __ASM volatile ("isb");
+
372 }
+
373 
+
374 
+
380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+
381 {
+
382  __ASM volatile ("dsb");
+
383 }
+
384 
+
385 
+
391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+
392 {
+
393  __ASM volatile ("dmb");
+
394 }
+
395 
+
396 
+
404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+
405 {
+
406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+
407  return __builtin_bswap32(value);
+
408 #else
+
409  uint32_t result;
+
410 
+
411  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+
412  return(result);
+
413 #endif
+
414 }
+
415 
+
416 
+
424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+
425 {
+
426  uint32_t result;
+
427 
+
428  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+
429  return(result);
+
430 }
+
431 
+
432 
+
440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+
441 {
+
442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+
443  return (short)__builtin_bswap16(value);
+
444 #else
+
445  uint32_t result;
+
446 
+
447  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+
448  return(result);
+
449 #endif
+
450 }
+
451 
+
452 
+
461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+
462 {
+
463  return (op1 >> op2) | (op1 << (32 - op2));
+
464 }
+
465 
+
466 
+
475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
+
476 
+
477 
+
478 #if (__CORTEX_M >= 0x03)
+
479 
+
487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+
488 {
+
489  uint32_t result;
+
490 
+
491  __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+
492  return(result);
+
493 }
+
494 
+
495 
+
503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+
504 {
+
505  uint32_t result;
+
506 
+
507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+
508  __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+
509 #else
+
510  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+
511  accepted by assembler. So has to use following less efficient pattern.
+
512  */
+
513  __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+
514 #endif
+
515  return(result);
+
516 }
+
517 
+
518 
+
526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+
527 {
+
528  uint32_t result;
+
529 
+
530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+
531  __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+
532 #else
+
533  /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+
534  accepted by assembler. So has to use following less efficient pattern.
+
535  */
+
536  __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+
537 #endif
+
538  return(result);
+
539 }
+
540 
+
541 
+
549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+
550 {
+
551  uint32_t result;
+
552 
+
553  __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+
554  return(result);
+
555 }
+
556 
+
557 
+
567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+
568 {
+
569  uint32_t result;
+
570 
+
571  __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+
572  return(result);
+
573 }
+
574 
+
575 
+
585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+
586 {
+
587  uint32_t result;
+
588 
+
589  __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+
590  return(result);
+
591 }
+
592 
+
593 
+
603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+
604 {
+
605  uint32_t result;
+
606 
+
607  __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+
608  return(result);
+
609 }
+
610 
+
611 
+
617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+
618 {
+
619  __ASM volatile ("clrex" ::: "memory");
+
620 }
+
621 
+
622 
+
631 #define __SSAT(ARG1,ARG2) \
+
632 ({ \
+
633  uint32_t __RES, __ARG1 = (ARG1); \
+
634  __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+
635  __RES; \
+
636  })
+
637 
+
638 
+
647 #define __USAT(ARG1,ARG2) \
+
648 ({ \
+
649  uint32_t __RES, __ARG1 = (ARG1); \
+
650  __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+
651  __RES; \
+
652  })
+
653 
+
654 
+
662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+
663 {
+
664  uint32_t result;
+
665 
+
666  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+
667  return(result);
+
668 }
+
669 
+
670 #endif /* (__CORTEX_M >= 0x03) */
+
671 
+
672 
+
673 
+
674 
+
675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+
676 /* TASKING carm specific functions */
+
677 
+
678 /*
+
679  * The CMSIS functions have been implemented as intrinsics in the compiler.
+
680  * Please use "carm -?i" to get an up to date list of all intrinsics,
+
681  * Including the CMSIS ones.
+
682  */
+
683 
+
684 #endif
+
685  /* end of group CMSIS_Core_InstructionInterface */
+
687 
+
688 #endif /* __CORE_CMINSTR_H */
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000002.html b/dir_000001_000002.html new file mode 100644 index 0000000..0ae7ac0 --- /dev/null +++ b/dir_000001_000002.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> filesystem Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → filesystem Relation

File in common/appIncludes file in common/filesystem
app.cfilesystem.h
screen_filetest.cfilesystem.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000003.html b/dir_000001_000003.html new file mode 100644 index 0000000..690574b --- /dev/null +++ b/dir_000001_000003.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> gui Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → gui Relation

File in common/appIncludes file in common/gui
screen_filetest.cbutton.h
screen_filetest.hscreen.h
screen_guitest.cbutton.h
screen_guitest.ccheckbox.h
screen_guitest.cnumupdown.h
screen_guitest.hscreen.h
screen_main.cbutton.h
screen_main.hscreen.h
screen_pixytest.cbutton.h
screen_pixytest.hscreen.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000005.html b/dir_000001_000005.html new file mode 100644 index 0000000..e4f6cc0 --- /dev/null +++ b/dir_000001_000005.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> pixy Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → pixy Relation

File in common/appIncludes file in common/pixy
screen_pixytest.cpixy.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000006.html b/dir_000001_000006.html new file mode 100644 index 0000000..871a624 --- /dev/null +++ b/dir_000001_000006.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> system Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → system Relation

File in common/appIncludes file in common/system
app.csystem.h
screen_pixytest.csystem.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000007.html b/dir_000001_000007.html new file mode 100644 index 0000000..1ce25ea --- /dev/null +++ b/dir_000001_000007.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> tft Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → tft Relation

File in common/appIncludes file in common/tft
app.ctft.h
screen_filetest.ctft.h
screen_guitest.ctft.h
screen_main.ctft.h
screen_pixytest.ctft.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000001_000008.html b/dir_000001_000008.html new file mode 100644 index 0000000..ae27bed --- /dev/null +++ b/dir_000001_000008.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/app -> touch Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

app → touch Relation

File in common/appIncludes file in common/touch
app.ctouch.h
screen_pixytest.ctouch.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000002_000004.html b/dir_000002_000004.html new file mode 100644 index 0000000..cb5ba5b --- /dev/null +++ b/dir_000002_000004.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/filesystem -> lowlevel Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

filesystem → lowlevel Relation

File in common/filesystemIncludes file in common/lowlevel
filesystem.cll_filesystem.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000003_000007.html b/dir_000003_000007.html new file mode 100644 index 0000000..214baf0 --- /dev/null +++ b/dir_000003_000007.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/gui -> tft Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

gui → tft Relation

File in common/guiIncludes file in common/tft
button.ctft.h
checkbox.ctft.h
numupdown.ctft.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000003_000008.html b/dir_000003_000008.html new file mode 100644 index 0000000..0c2e769 --- /dev/null +++ b/dir_000003_000008.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/gui -> touch Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

gui → touch Relation

File in common/guiIncludes file in common/touch
button.ctouch.h
button.htouch.h
checkbox.ctouch.h
numupdown.ctouch.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000004_000002.html b/dir_000004_000002.html new file mode 100644 index 0000000..e12268e --- /dev/null +++ b/dir_000004_000002.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/lowlevel -> filesystem Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

lowlevel → filesystem Relation

File in common/lowlevelIncludes file in common/filesystem
ll_filesystem.hfilesystem.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000006_000004.html b/dir_000006_000004.html new file mode 100644 index 0000000..72cb53f --- /dev/null +++ b/dir_000006_000004.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/system -> lowlevel Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

system → lowlevel Relation

File in common/systemIncludes file in common/lowlevel
system.cll_system.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000007_000004.html b/dir_000007_000004.html new file mode 100644 index 0000000..37a191e --- /dev/null +++ b/dir_000007_000004.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/tft -> lowlevel Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

tft → lowlevel Relation

File in common/tftIncludes file in common/lowlevel
tft.cll_tft.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000008_000004.html b/dir_000008_000004.html new file mode 100644 index 0000000..fcc0667 --- /dev/null +++ b/dir_000008_000004.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: common/touch -> lowlevel Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

touch → lowlevel Relation

File in common/touchIncludes file in common/lowlevel
touch.cll_touch.h
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000010_000000.html b/dir_000010_000000.html new file mode 100644 index 0000000..e966004 --- /dev/null +++ b/dir_000010_000000.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: discovery/src -> common Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

src → common Relation

File in discovery/srcIncludes file in common
ll_filesystem.clowlevel / ll_filesystem.h
ll_system.clowlevel / ll_system.h
ll_tft.clowlevel / ll_tft.h
ll_touch.clowlevel / ll_touch.h
main.capp / app.h
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000012_000000.html b/dir_000012_000000.html new file mode 100644 index 0000000..a2c7e1b --- /dev/null +++ b/dir_000012_000000.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: emulator/qt -> common Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

qt → common Relation

File in emulator/qtIncludes file in common
ll_filesystem.cpplowlevel / ll_filesystem.h
ll_system.cpplowlevel / ll_system.h
ll_tft.cpplowlevel / ll_tft.h
ll_touch.cpplowlevel / ll_touch.h
mainwindow.cpptft / tft.h
mainwindow.cpptouch / touch.h
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000019_000018.html b/dir_000019_000018.html new file mode 100644 index 0000000..ec03563 --- /dev/null +++ b/dir_000019_000018.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src -> inc Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

src → inc Relation

File in discovery/libs/StmCoreNPheriph/srcIncludes file in discovery/libs/StmCoreNPheriph/inc
misc.cmisc.h
stm32f4_discovery.cstm32f4_discovery.h
stm32f4_discovery_lis302dl.cstm32f4_discovery_lis302dl.h
stm32f4xx_adc.cstm32f4xx_adc.h
stm32f4xx_adc.cstm32f4xx_rcc.h
stm32f4xx_can.cstm32f4xx_can.h
stm32f4xx_can.cstm32f4xx_rcc.h
stm32f4xx_crc.cstm32f4xx_crc.h
stm32f4xx_cryp.cstm32f4xx_cryp.h
stm32f4xx_cryp.cstm32f4xx_rcc.h
stm32f4xx_cryp_aes.cstm32f4xx_cryp.h
stm32f4xx_cryp_des.cstm32f4xx_cryp.h
stm32f4xx_cryp_tdes.cstm32f4xx_cryp.h
stm32f4xx_dac.cstm32f4xx_dac.h
stm32f4xx_dac.cstm32f4xx_rcc.h
stm32f4xx_dbgmcu.cstm32f4xx_dbgmcu.h
stm32f4xx_dcmi.cstm32f4xx_dcmi.h
stm32f4xx_dcmi.cstm32f4xx_rcc.h
stm32f4xx_dma.cstm32f4xx_dma.h
stm32f4xx_dma.cstm32f4xx_rcc.h
stm32f4xx_dma2d.cstm32f4xx_dma2d.h
stm32f4xx_dma2d.cstm32f4xx_rcc.h
stm32f4xx_exti.cstm32f4xx_exti.h
stm32f4xx_flash.cstm32f4xx_flash.h
stm32f4xx_flash_ramfunc.cstm32f4xx_flash_ramfunc.h
stm32f4xx_fsmc.cstm32f4xx_fsmc.h
stm32f4xx_fsmc.cstm32f4xx_rcc.h
stm32f4xx_gpio.cstm32f4xx_gpio.h
stm32f4xx_gpio.cstm32f4xx_rcc.h
stm32f4xx_hash.cstm32f4xx_hash.h
stm32f4xx_hash.cstm32f4xx_rcc.h
stm32f4xx_hash_md5.cstm32f4xx_hash.h
stm32f4xx_hash_sha1.cstm32f4xx_hash.h
stm32f4xx_i2c.cstm32f4xx_i2c.h
stm32f4xx_i2c.cstm32f4xx_rcc.h
stm32f4xx_iwdg.cstm32f4xx_iwdg.h
stm32f4xx_ltdc.cstm32f4xx_ltdc.h
stm32f4xx_ltdc.cstm32f4xx_rcc.h
stm32f4xx_pwr.cstm32f4xx_pwr.h
stm32f4xx_pwr.cstm32f4xx_rcc.h
stm32f4xx_rcc.cstm32f4xx_rcc.h
stm32f4xx_rng.cstm32f4xx_rcc.h
stm32f4xx_rng.cstm32f4xx_rng.h
stm32f4xx_rtc.cstm32f4xx_rtc.h
stm32f4xx_sai.cstm32f4xx_rcc.h
stm32f4xx_sai.cstm32f4xx_sai.h
stm32f4xx_sdio.cstm32f4xx_rcc.h
stm32f4xx_sdio.cstm32f4xx_sdio.h
stm32f4xx_spi.cstm32f4xx_rcc.h
stm32f4xx_spi.cstm32f4xx_spi.h
stm32f4xx_syscfg.cstm32f4xx_rcc.h
stm32f4xx_syscfg.cstm32f4xx_syscfg.h
stm32f4xx_tim.cstm32f4xx_rcc.h
stm32f4xx_tim.cstm32f4xx_tim.h
stm32f4xx_usart.cstm32f4xx_rcc.h
stm32f4xx_usart.cstm32f4xx_usart.h
stm32f4xx_wwdg.cstm32f4xx_rcc.h
stm32f4xx_wwdg.cstm32f4xx_wwdg.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000020_000017.html b/dir_000020_000017.html new file mode 100644 index 0000000..8426b12 --- /dev/null +++ b/dir_000020_000017.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost -> StmCoreNPheriph Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

StmUsbHost → StmCoreNPheriph Relation

File in discovery/libs/StmUsbHostIncludes file in discovery/libs/StmCoreNPheriph
STM32_USB_OTG_Driver / inc / usb_bsp.hinc / stm32f4_discovery.h
STM32_USB_Device_Specific / usb_conf.hinc / stm32f4xx.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000021_000017.html b/dir_000021_000017.html new file mode 100644 index 0000000..8934973 --- /dev/null +++ b/dir_000021_000017.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_Device_Specific -> StmCoreNPheriph Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

STM32_USB_Device_Specific → StmCoreNPheriph Relation

File in discovery/libs/StmUsbHost/STM32_USB_Device_SpecificIncludes file in discovery/libs/StmCoreNPheriph
usb_conf.hinc / stm32f4xx.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000022_000034.html b/dir_000022_000034.html new file mode 100644 index 0000000..7500070 --- /dev/null +++ b/dir_000022_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+

STM32_USB_HOST_Library → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_LibraryIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
Core / src / usbh_core.cinc / usb_bsp.h
Core / inc / usbh_core.hinc / usb_hcd.h
Class / HID / inc / usbh_hid_core.hinc / usb_bsp.h
Class / MSC / src / usbh_msc_bot.cinc / usb_hcd_int.h
Class / MSC / inc / usbh_msc_core.hinc / usb_bsp.h
Core / inc / usbh_stdreq.hinc / usb_hcd.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000023_000031.html b/dir_000023_000031.html new file mode 100644 index 0000000..f7662dc --- /dev/null +++ b/dir_000023_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class -> Core Relation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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Class → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/ClassIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
HID / inc / usbh_hid_core.hinc / usbh_core.h
HID / inc / usbh_hid_core.hinc / usbh_hcs.h
HID / inc / usbh_hid_core.hinc / usbh_ioreq.h
HID / inc / usbh_hid_core.hinc / usbh_stdreq.h
MSC / src / usbh_msc_bot.cinc / usbh_def.h
MSC / src / usbh_msc_bot.cinc / usbh_ioreq.h
MSC / inc / usbh_msc_bot.hinc / usbh_stdreq.h
MSC / src / usbh_msc_core.cinc / usbh_core.h
MSC / inc / usbh_msc_core.hinc / usbh_core.h
MSC / inc / usbh_msc_core.hinc / usbh_hcs.h
MSC / inc / usbh_msc_core.hinc / usbh_ioreq.h
MSC / inc / usbh_msc_core.hinc / usbh_stdreq.h
MSC / src / usbh_msc_scsi.cinc / usbh_def.h
MSC / src / usbh_msc_scsi.cinc / usbh_ioreq.h
MSC / inc / usbh_msc_scsi.hinc / usbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000023_000034.html b/dir_000023_000034.html new file mode 100644 index 0000000..2aa8bb8 --- /dev/null +++ b/dir_000023_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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Class → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/ClassIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
HID / inc / usbh_hid_core.hinc / usb_bsp.h
MSC / src / usbh_msc_bot.cinc / usb_hcd_int.h
MSC / inc / usbh_msc_core.hinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000024_000031.html b/dir_000024_000031.html new file mode 100644 index 0000000..90f5620 --- /dev/null +++ b/dir_000024_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID -> Core Relation + + + + + + + + + + +
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HID → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HIDIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
inc / usbh_hid_core.hinc / usbh_core.h
inc / usbh_hid_core.hinc / usbh_hcs.h
inc / usbh_hid_core.hinc / usbh_ioreq.h
inc / usbh_hid_core.hinc / usbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000024_000034.html b/dir_000024_000034.html new file mode 100644 index 0000000..8c8668a --- /dev/null +++ b/dir_000024_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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HID → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HIDIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
inc / usbh_hid_core.hinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000025_000031.html b/dir_000025_000031.html new file mode 100644 index 0000000..fccffc3 --- /dev/null +++ b/dir_000025_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc -> Core Relation + + + + + + + + + + +
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inc → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/incIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
usbh_hid_core.hinc / usbh_core.h
usbh_hid_core.hinc / usbh_hcs.h
usbh_hid_core.hinc / usbh_ioreq.h
usbh_hid_core.hinc / usbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000025_000034.html b/dir_000025_000034.html new file mode 100644 index 0000000..cd07780 --- /dev/null +++ b/dir_000025_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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inc → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/incIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
usbh_hid_core.hinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000026_000025.html b/dir_000026_000025.html new file mode 100644 index 0000000..9f6f632 --- /dev/null +++ b/dir_000026_000025.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src -> inc Relation + + + + + + + + + + +
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src → inc Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc
usbh_hid_core.cusbh_hid_core.h
usbh_hid_core.cusbh_hid_keybd.h
usbh_hid_core.cusbh_hid_mouse.h
usbh_hid_keybd.cusbh_hid_keybd.h
usbh_hid_mouse.cusbh_hid_mouse.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000027_000031.html b/dir_000027_000031.html new file mode 100644 index 0000000..ec3a5f1 --- /dev/null +++ b/dir_000027_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC -> Core Relation + + + + + + + + + + +
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MSC → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSCIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
src / usbh_msc_bot.cinc / usbh_def.h
src / usbh_msc_bot.cinc / usbh_ioreq.h
inc / usbh_msc_bot.hinc / usbh_stdreq.h
src / usbh_msc_core.cinc / usbh_core.h
inc / usbh_msc_core.hinc / usbh_core.h
inc / usbh_msc_core.hinc / usbh_hcs.h
inc / usbh_msc_core.hinc / usbh_ioreq.h
inc / usbh_msc_core.hinc / usbh_stdreq.h
src / usbh_msc_scsi.cinc / usbh_def.h
src / usbh_msc_scsi.cinc / usbh_ioreq.h
inc / usbh_msc_scsi.hinc / usbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000027_000034.html b/dir_000027_000034.html new file mode 100644 index 0000000..ce764f5 --- /dev/null +++ b/dir_000027_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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MSC → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSCIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
src / usbh_msc_bot.cinc / usb_hcd_int.h
inc / usbh_msc_core.hinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000028_000031.html b/dir_000028_000031.html new file mode 100644 index 0000000..7e7cdb1 --- /dev/null +++ b/dir_000028_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc -> Core Relation + + + + + + + + + + +
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inc → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/incIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
usbh_msc_bot.hinc / usbh_stdreq.h
usbh_msc_core.hinc / usbh_core.h
usbh_msc_core.hinc / usbh_hcs.h
usbh_msc_core.hinc / usbh_ioreq.h
usbh_msc_core.hinc / usbh_stdreq.h
usbh_msc_scsi.hinc / usbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000028_000034.html b/dir_000028_000034.html new file mode 100644 index 0000000..98dd0a1 --- /dev/null +++ b/dir_000028_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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inc → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/incIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
usbh_msc_core.hinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000029_000010.html b/dir_000029_000010.html new file mode 100644 index 0000000..dc2eec1 --- /dev/null +++ b/dir_000029_000010.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/src -> libs Relation + + + + + + + + + + +
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src → libs Relation

File in discovery/srcIncludes file in discovery/libs
ll_system.cStmCoreNPheriph / inc / stm32f4_discovery.h
ll_system.cStmCoreNPheriph / inc / stm32f4xx.h
ll_system.cStmUsbHost / STM32_USB_OTG_Driver / inc / usb_hcd_int.h
ll_system.cStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_core.h
newlib_stubs.cStmCoreNPheriph / inc / stm32f4xx.h
system_stm32f4xx.cStmCoreNPheriph / inc / stm32f4xx.h
usb_bsp.cStmCoreNPheriph / inc / stm32f4_discovery.h
usb_bsp.cStmUsbHost / STM32_USB_OTG_Driver / inc / usb_bsp.h
usbh_msc_core.cStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_core.h
usbh_msc_core.hStmUsbHost / STM32_USB_OTG_Driver / inc / usb_bsp.h
usbh_msc_core.hStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_core.h
usbh_msc_core.hStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_hcs.h
usbh_msc_core.hStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_ioreq.h
usbh_msc_core.hStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_stdreq.h
usbh_usr.hStmCoreNPheriph / inc / stm32f4_discovery.h
usbh_usr.hStmUsbHost / STM32_USB_HOST_Library / Core / inc / usbh_core.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000030_000028.html b/dir_000030_000028.html new file mode 100644 index 0000000..36a2fc3 --- /dev/null +++ b/dir_000030_000028.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src -> inc Relation + + + + + + + + + + +
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src → inc Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc
usbh_msc_bot.cusbh_msc_bot.h
usbh_msc_bot.cusbh_msc_scsi.h
usbh_msc_core.cusbh_msc_bot.h
usbh_msc_core.cusbh_msc_scsi.h
usbh_msc_scsi.cusbh_msc_bot.h
usbh_msc_scsi.cusbh_msc_scsi.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000030_000031.html b/dir_000030_000031.html new file mode 100644 index 0000000..cba630f --- /dev/null +++ b/dir_000030_000031.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src -> Core Relation + + + + + + + + + + +
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src → Core Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core
usbh_msc_bot.cinc / usbh_def.h
usbh_msc_bot.cinc / usbh_ioreq.h
usbh_msc_core.cinc / usbh_core.h
usbh_msc_scsi.cinc / usbh_def.h
usbh_msc_scsi.cinc / usbh_ioreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000030_000034.html b/dir_000030_000034.html new file mode 100644 index 0000000..7655b3c --- /dev/null +++ b/dir_000030_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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src → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
usbh_msc_bot.cinc / usb_hcd_int.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000031_000034.html b/dir_000031_000034.html new file mode 100644 index 0000000..cc48776 --- /dev/null +++ b/dir_000031_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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Core → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/CoreIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
src / usbh_core.cinc / usb_bsp.h
inc / usbh_core.hinc / usb_hcd.h
inc / usbh_stdreq.hinc / usb_hcd.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000032_000034.html b/dir_000032_000034.html new file mode 100644 index 0000000..5d74e2d --- /dev/null +++ b/dir_000032_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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inc → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/incIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
usbh_core.hinc / usb_hcd.h
usbh_stdreq.hinc / usb_hcd.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000033_000032.html b/dir_000033_000032.html new file mode 100644 index 0000000..31d7f33 --- /dev/null +++ b/dir_000033_000032.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src -> inc Relation + + + + + + + + + + +
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src → inc Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc
usbh_core.cusbh_core.h
usbh_core.cusbh_hcs.h
usbh_core.cusbh_ioreq.h
usbh_core.cusbh_stdreq.h
usbh_hcs.cusbh_hcs.h
usbh_ioreq.cusbh_ioreq.h
usbh_stdreq.cusbh_ioreq.h
usbh_stdreq.cusbh_stdreq.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000033_000034.html b/dir_000033_000034.html new file mode 100644 index 0000000..511cda8 --- /dev/null +++ b/dir_000033_000034.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src -> STM32_USB_OTG_Driver Relation + + + + + + + + + + +
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src → STM32_USB_OTG_Driver Relation

File in discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver
usbh_core.cinc / usb_bsp.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000034_000017.html b/dir_000034_000017.html new file mode 100644 index 0000000..cb9378f --- /dev/null +++ b/dir_000034_000017.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver -> StmCoreNPheriph Relation + + + + + + + + + + +
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STM32_USB_OTG_Driver → StmCoreNPheriph Relation

File in discovery/libs/StmUsbHost/STM32_USB_OTG_DriverIncludes file in discovery/libs/StmCoreNPheriph
inc / usb_bsp.hinc / stm32f4_discovery.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000035_000017.html b/dir_000035_000017.html new file mode 100644 index 0000000..2d82c90 --- /dev/null +++ b/dir_000035_000017.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc -> StmCoreNPheriph Relation + + + + + + + + + + +
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inc → StmCoreNPheriph Relation

File in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/incIncludes file in discovery/libs/StmCoreNPheriph
usb_bsp.hinc / stm32f4_discovery.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_000036_000035.html b/dir_000036_000035.html new file mode 100644 index 0000000..9591b2f --- /dev/null +++ b/dir_000036_000035.html @@ -0,0 +1,91 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src -> inc Relation + + + + + + + + + + +
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src → inc Relation

File in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/srcIncludes file in discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc
usb_core.cusb_bsp.h
usb_core.cusb_core.h
usb_hcd.cusb_bsp.h
usb_hcd.cusb_core.h
usb_hcd.cusb_hcd.h
usb_hcd_int.cusb_core.h
usb_hcd_int.cusb_defines.h
usb_hcd_int.cusb_hcd_int.h
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_017204e842f691777598906361953075.html b/dir_017204e842f691777598906361953075.html new file mode 100644 index 0000000..5385a84 --- /dev/null +++ b/dir_017204e842f691777598906361953075.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: emulator/libs/Pixy Directory Reference + + + + + + + + + + +
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Pixy Directory Reference
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+Directories

directory  src
 
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+Files

file  hello_pixy.cpp
 
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_017204e842f691777598906361953075_dep.map b/dir_017204e842f691777598906361953075_dep.map new file mode 100644 index 0000000..2644431 --- /dev/null +++ b/dir_017204e842f691777598906361953075_dep.map @@ -0,0 +1,5 @@ + + + + + diff --git a/dir_017204e842f691777598906361953075_dep.md5 b/dir_017204e842f691777598906361953075_dep.md5 new file mode 100644 index 0000000..3752c96 --- /dev/null +++ b/dir_017204e842f691777598906361953075_dep.md5 @@ -0,0 +1 @@ +8ff2f7ffada92cd5a35662f8aae3a0d3 \ No newline at end of file diff --git a/dir_017204e842f691777598906361953075_dep.png b/dir_017204e842f691777598906361953075_dep.png new file mode 100644 index 0000000..5e537ba Binary files /dev/null and b/dir_017204e842f691777598906361953075_dep.png differ diff --git a/dir_07523c13f04fd35d8848cb17a371cb5b.html b/dir_07523c13f04fd35d8848cb17a371cb5b.html new file mode 100644 index 0000000..814bb55 --- /dev/null +++ b/dir_07523c13f04fd35d8848cb17a371cb5b.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: discovery/libs Directory Reference + + + + + + + + + + +
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directory  Pixy
 
directory  StmCoreNPheriph
 
directory  StmUsbHost
 
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+ + diff --git a/dir_07523c13f04fd35d8848cb17a371cb5b_dep.map b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.map new file mode 100644 index 0000000..45aa744 --- /dev/null +++ b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/dir_07523c13f04fd35d8848cb17a371cb5b_dep.md5 b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.md5 new file mode 100644 index 0000000..1d42704 --- /dev/null +++ b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.md5 @@ -0,0 +1 @@ +a7720ad27e423995937430d97c361bf9 \ No newline at end of file diff --git a/dir_07523c13f04fd35d8848cb17a371cb5b_dep.png b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.png new file mode 100644 index 0000000..c94c4b9 Binary files /dev/null and b/dir_07523c13f04fd35d8848cb17a371cb5b_dep.png differ diff --git a/dir_0a50ab14f1d261d61cd33403a26c32cc.html b/dir_0a50ab14f1d261d61cd33403a26c32cc.html new file mode 100644 index 0000000..7df79a7 --- /dev/null +++ b/dir_0a50ab14f1d261d61cd33403a26c32cc.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: common/filesystem Directory Reference + + + + + + + + + + +
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filesystem Directory Reference
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+Directory dependency graph for filesystem:
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common/filesystem
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+Files

file  filesystem.c
 
file  filesystem.h [code]
 
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.map b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.map new file mode 100644 index 0000000..7c74882 --- /dev/null +++ b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.md5 b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.md5 new file mode 100644 index 0000000..685f862 --- /dev/null +++ b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.md5 @@ -0,0 +1 @@ +d9e9e0835e9975d68827fb9bc03abdde \ No newline at end of file diff --git a/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.png b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.png new file mode 100644 index 0000000..f3a12de Binary files /dev/null and b/dir_0a50ab14f1d261d61cd33403a26c32cc_dep.png differ diff --git a/dir_0df032ba06b8eb810b5f40e1c65a502c.html b/dir_0df032ba06b8eb810b5f40e1c65a502c.html new file mode 100644 index 0000000..8daa523 --- /dev/null +++ b/dir_0df032ba06b8eb810b5f40e1c65a502c.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class Directory Reference + + + + + + + + + + +
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Class Directory Reference
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+Directory dependency graph for Class:
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discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class
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+Directories

directory  HID
 
directory  MSC
 
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+ + diff --git a/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.map b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.map new file mode 100644 index 0000000..8208d93 --- /dev/null +++ b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.md5 b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.md5 new file mode 100644 index 0000000..da1f170 --- /dev/null +++ b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.md5 @@ -0,0 +1 @@ +3e82b0a48a591c05b5c510085b97573c \ No newline at end of file diff --git a/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.png b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.png new file mode 100644 index 0000000..6ce048d Binary files /dev/null and b/dir_0df032ba06b8eb810b5f40e1c65a502c_dep.png differ diff --git a/dir_1060172239f126d4aafe962033aac0fb.html b/dir_1060172239f126d4aafe962033aac0fb.html new file mode 100644 index 0000000..7dcc658 --- /dev/null +++ b/dir_1060172239f126d4aafe962033aac0fb.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc Directory Reference + + + + + + + + + + +
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inc Directory Reference
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discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc
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+Files

file  usbh_msc_bot.h [code]
 Header file for usbh_msc_bot.c.
 
file  usbh_msc_core.h [code]
 
file  usbh_msc_scsi.h [code]
 Header file for usbh_msc_scsi.c.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_1060172239f126d4aafe962033aac0fb_dep.map b/dir_1060172239f126d4aafe962033aac0fb_dep.map new file mode 100644 index 0000000..9780820 --- /dev/null +++ b/dir_1060172239f126d4aafe962033aac0fb_dep.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/dir_1060172239f126d4aafe962033aac0fb_dep.md5 b/dir_1060172239f126d4aafe962033aac0fb_dep.md5 new file mode 100644 index 0000000..a1a34d0 --- /dev/null +++ b/dir_1060172239f126d4aafe962033aac0fb_dep.md5 @@ -0,0 +1 @@ +9ebf7904e1ddbeed42ac793b1b4cf0d7 \ No newline at end of file diff --git a/dir_1060172239f126d4aafe962033aac0fb_dep.png b/dir_1060172239f126d4aafe962033aac0fb_dep.png new file mode 100644 index 0000000..988d6ee Binary files /dev/null and b/dir_1060172239f126d4aafe962033aac0fb_dep.png differ diff --git a/dir_12f7a99b9d2a0e5955a2ac990af20021.html b/dir_12f7a99b9d2a0e5955a2ac990af20021.html new file mode 100644 index 0000000..5da0a7c --- /dev/null +++ b/dir_12f7a99b9d2a0e5955a2ac990af20021.html @@ -0,0 +1,217 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src Directory Reference + + + + + + + + + + +
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discovery/libs/StmCoreNPheriph/src
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+Files

file  misc.c
 This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).
 
file  stm32f4_discovery.c
 This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics.
 
file  stm32f4_discovery_lis302dl.c
 This file provides a set of functions needed to manage the LIS302DL MEMS accelerometer available on STM32F4-Discovery Kit.
 
file  stm32f4xx_adc.c
 This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral:
 
file  stm32f4xx_can.c
 This file provides firmware functions to manage the following functionalities of the Controller area network (CAN) peripheral:
 
file  stm32f4xx_crc.c
 This file provides all the CRC firmware functions.
 
file  stm32f4xx_cryp.c
 This file provides firmware functions to manage the following functionalities of the Cryptographic processor (CRYP) peripheral:
 
file  stm32f4xx_cryp_aes.c
 This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR/GCM/CCM modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral. AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.
 
file  stm32f4xx_cryp_des.c
 This file provides high level functions to encrypt and decrypt an input message using DES in ECB/CBC modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral.
 
file  stm32f4xx_cryp_tdes.c
 This file provides high level functions to encrypt and decrypt an input message using TDES in ECB/CBC modes . It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral.
 
file  stm32f4xx_dac.c
 This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral:
 
file  stm32f4xx_dbgmcu.c
 This file provides all the DBGMCU firmware functions.
 
file  stm32f4xx_dcmi.c
 This file provides firmware functions to manage the following functionalities of the DCMI peripheral:
 
file  stm32f4xx_dma.c
 This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA):
 
file  stm32f4xx_dma2d.c
 This file provides firmware functions to manage the following functionalities of the DMA2D controller (DMA2D) peripheral:
 
file  stm32f4xx_exti.c
 This file provides firmware functions to manage the following functionalities of the EXTI peripheral:
 
file  stm32f4xx_flash.c
 This file provides firmware functions to manage the following functionalities of the FLASH peripheral:
 
file  stm32f4xx_flash_ramfunc.c
 FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM.
 
file  stm32f4xx_fsmc.c
 This file provides firmware functions to manage the following functionalities of the FSMC peripheral:
 
file  stm32f4xx_gpio.c
 This file provides firmware functions to manage the following functionalities of the GPIO peripheral:
 
file  stm32f4xx_hash.c
 This file provides firmware functions to manage the following functionalities of the HASH / HMAC Processor (HASH) peripheral:
 
file  stm32f4xx_hash_md5.c
 This file provides high level functions to compute the HASH MD5 and HMAC MD5 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral.
 
file  stm32f4xx_hash_sha1.c
 This file provides high level functions to compute the HASH SHA1 and HMAC SHA1 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral.
 
file  stm32f4xx_i2c.c
 This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C)
 
file  stm32f4xx_iwdg.c
 This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral:
 
file  stm32f4xx_ltdc.c
 This file provides firmware functions to manage the following functionalities of the LTDC controller (LTDC) peripheral:
 
file  stm32f4xx_pwr.c
 This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral:
 
file  stm32f4xx_rcc.c
 This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:
 
file  stm32f4xx_rng.c
 This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral:
 
file  stm32f4xx_rtc.c
 This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral:
 
file  stm32f4xx_sai.c
 This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI):
 
file  stm32f4xx_sdio.c
 This file provides firmware functions to manage the following functionalities of the Secure digital input/output interface (SDIO) peripheral:
 
file  stm32f4xx_spi.c
 This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI):
 
file  stm32f4xx_syscfg.c
 This file provides firmware functions to manage the SYSCFG peripheral.
 
file  stm32f4xx_tim.c
 This file provides firmware functions to manage the following functionalities of the TIM peripheral:
 
file  stm32f4xx_usart.c
 This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART):
 
file  stm32f4xx_wwdg.c
 This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral:
 
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.map b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.map new file mode 100644 index 0000000..601895d --- /dev/null +++ b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.md5 b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.md5 new file mode 100644 index 0000000..9df6a40 --- /dev/null +++ b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.md5 @@ -0,0 +1 @@ +1b16a094fa77d8f5978e29a07ccd88b0 \ No newline at end of file diff --git a/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.png b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.png new file mode 100644 index 0000000..20ea22c Binary files /dev/null and b/dir_12f7a99b9d2a0e5955a2ac990af20021_dep.png differ diff --git a/dir_199f00bcd9b0045362f41b6724eab9bb.html b/dir_199f00bcd9b0045362f41b6724eab9bb.html new file mode 100644 index 0000000..db19d92 --- /dev/null +++ b/dir_199f00bcd9b0045362f41b6724eab9bb.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: emulator Directory Reference + + + + + + + + + + +
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discoverpixy +
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emulator Directory Reference
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emulator
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+Directories

directory  qt
 
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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src Directory Reference
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emulator/libs/Pixy/src
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+Files

file  blob.h [code]
 
file  blobs.h [code]
 
file  calc.h [code]
 
file  chirp.cpp
 
file  chirp.hpp [code]
 
file  chirpreceiver.cpp
 
file  chirpreceiver.hpp [code]
 
file  colorlut.h [code]
 
file  debug.h [code]
 
file  debuglog.h [code]
 
file  interpreter.hpp [code]
 
file  link.h [code]
 
file  pixy.cpp
 
file  pixyinterpreter.cpp
 
file  pixyinterpreter.hpp [code]
 
file  pixytypes.h [code]
 
file  qqueue.h [code]
 
file  simplevector.h [code]
 
file  timer.cpp
 
file  timer.hpp [code]
 
file  usblink.cpp
 
file  usblink.h [code]
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_1d6043785e9a6436a0102038a303860d_dep.map b/dir_1d6043785e9a6436a0102038a303860d_dep.map new file mode 100644 index 0000000..e139056 --- /dev/null +++ b/dir_1d6043785e9a6436a0102038a303860d_dep.map @@ -0,0 +1,4 @@ + + + + diff --git a/dir_1d6043785e9a6436a0102038a303860d_dep.md5 b/dir_1d6043785e9a6436a0102038a303860d_dep.md5 new file mode 100644 index 0000000..48e4c65 --- /dev/null +++ b/dir_1d6043785e9a6436a0102038a303860d_dep.md5 @@ -0,0 +1 @@ +2a7464320c6e89cb352df44770e637d3 \ No newline at end of file diff --git a/dir_1d6043785e9a6436a0102038a303860d_dep.png b/dir_1d6043785e9a6436a0102038a303860d_dep.png new file mode 100644 index 0000000..365c26e Binary files /dev/null and b/dir_1d6043785e9a6436a0102038a303860d_dep.png differ diff --git a/dir_1d60ba7d807ff336a2be2f2de640bf2b.html b/dir_1d60ba7d807ff336a2be2f2de640bf2b.html new file mode 100644 index 0000000..3d0576f --- /dev/null +++ b/dir_1d60ba7d807ff336a2be2f2de640bf2b.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph Directory Reference + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+
StmCoreNPheriph Directory Reference
+
+
+
+Directory dependency graph for StmCoreNPheriph:
+
+
discovery/libs/StmCoreNPheriph
+ + +
+ + + + + + +

+Directories

directory  inc
 
directory  src
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.map b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.map new file mode 100644 index 0000000..7a5f9b0 --- /dev/null +++ b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.md5 b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.md5 new file mode 100644 index 0000000..a08d35c --- /dev/null +++ b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.md5 @@ -0,0 +1 @@ +2fd659f4c7bd1efdec60e67b9c80e71b \ No newline at end of file diff --git a/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.png b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.png new file mode 100644 index 0000000..bc90b21 Binary files /dev/null and b/dir_1d60ba7d807ff336a2be2f2de640bf2b_dep.png differ diff --git a/dir_284aa68f6d81a4e6cef9d8d6fca4af3e.html b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e.html new file mode 100644 index 0000000..5f54de2 --- /dev/null +++ b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: common/system Directory Reference + + + + + + + + + + +
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discoverpixy +
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system Directory Reference
+
+
+
+Directory dependency graph for system:
+
+
common/system
+ + +
+ + + + + + +

+Files

file  system.c
 
file  system.h [code]
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.map b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.map new file mode 100644 index 0000000..33c019a --- /dev/null +++ b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.md5 b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.md5 new file mode 100644 index 0000000..6f0bd8f --- /dev/null +++ b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.md5 @@ -0,0 +1 @@ +02538fb42184cb095de6881cf211c77e \ No newline at end of file diff --git a/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.png b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.png new file mode 100644 index 0000000..eb63355 Binary files /dev/null and b/dir_284aa68f6d81a4e6cef9d8d6fca4af3e_dep.png differ diff --git a/dir_332599425fcd5a03c822271582d4e895.html b/dir_332599425fcd5a03c822271582d4e895.html new file mode 100644 index 0000000..d1d9ce9 --- /dev/null +++ b/dir_332599425fcd5a03c822271582d4e895.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
inc Directory Reference
+
+
+
+Directory dependency graph for inc:
+
+
discovery/libs/StmCoreNPheriph/inc
+ + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Files

file  core_cm4.h [code]
 CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
 
file  core_cm4_simd.h [code]
 CMSIS Cortex-M4 SIMD Header File.
 
file  core_cmFunc.h [code]
 CMSIS Cortex-M Core Function Access Header File.
 
file  core_cmInstr.h [code]
 CMSIS Cortex-M Core Instruction Access Header File.
 
file  misc.h [code]
 This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).
 
file  stm32f4_discovery.h [code]
 This file contains definitions for STM32F4-Discovery Kit's Leds and push-button hardware resources.
 
file  stm32f4_discovery_lis302dl.h [code]
 This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c firmware driver.
 
file  stm32f4xx.h [code]
 CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F4xx devices.
 
file  stm32f4xx_adc.h [code]
 This file contains all the functions prototypes for the ADC firmware library.
 
file  stm32f4xx_can.h [code]
 This file contains all the functions prototypes for the CAN firmware library.
 
file  stm32f4xx_conf.h [code]
 
file  stm32f4xx_crc.h [code]
 This file contains all the functions prototypes for the CRC firmware library.
 
file  stm32f4xx_cryp.h [code]
 This file contains all the functions prototypes for the Cryptographic processor(CRYP) firmware library.
 
file  stm32f4xx_dac.h [code]
 This file contains all the functions prototypes for the DAC firmware library.
 
file  stm32f4xx_dbgmcu.h [code]
 This file contains all the functions prototypes for the DBGMCU firmware library.
 
file  stm32f4xx_dcmi.h [code]
 This file contains all the functions prototypes for the DCMI firmware library.
 
file  stm32f4xx_dma.h [code]
 This file contains all the functions prototypes for the DMA firmware library.
 
file  stm32f4xx_dma2d.h [code]
 This file contains all the functions prototypes for the DMA2D firmware library.
 
file  stm32f4xx_exti.h [code]
 This file contains all the functions prototypes for the EXTI firmware library.
 
file  stm32f4xx_flash.h [code]
 This file contains all the functions prototypes for the FLASH firmware library.
 
file  stm32f4xx_flash_ramfunc.h [code]
 Header file of FLASH RAMFUNC driver.
 
file  stm32f4xx_fsmc.h [code]
 This file contains all the functions prototypes for the FSMC firmware library.
 
file  stm32f4xx_gpio.h [code]
 This file contains all the functions prototypes for the GPIO firmware library.
 
file  stm32f4xx_hash.h [code]
 This file contains all the functions prototypes for the HASH firmware library.
 
file  stm32f4xx_i2c.h [code]
 This file contains all the functions prototypes for the I2C firmware library.
 
file  stm32f4xx_iwdg.h [code]
 This file contains all the functions prototypes for the IWDG firmware library.
 
file  stm32f4xx_ltdc.h [code]
 This file contains all the functions prototypes for the LTDC firmware library.
 
file  stm32f4xx_pwr.h [code]
 This file contains all the functions prototypes for the PWR firmware library.
 
file  stm32f4xx_rcc.h [code]
 This file contains all the functions prototypes for the RCC firmware library.
 
file  stm32f4xx_rng.h [code]
 This file contains all the functions prototypes for the Random Number Generator(RNG) firmware library.
 
file  stm32f4xx_rtc.h [code]
 This file contains all the functions prototypes for the RTC firmware library.
 
file  stm32f4xx_sai.h [code]
 This file contains all the functions prototypes for the SAI firmware library.
 
file  stm32f4xx_sdio.h [code]
 This file contains all the functions prototypes for the SDIO firmware library.
 
file  stm32f4xx_spi.h [code]
 This file contains all the functions prototypes for the SPI firmware library.
 
file  stm32f4xx_syscfg.h [code]
 This file contains all the functions prototypes for the SYSCFG firmware library.
 
file  stm32f4xx_tim.h [code]
 This file contains all the functions prototypes for the TIM firmware library.
 
file  stm32f4xx_usart.h [code]
 This file contains all the functions prototypes for the USART firmware library.
 
file  stm32f4xx_wwdg.h [code]
 This file contains all the functions prototypes for the WWDG firmware library.
 
file  system_stm32f4xx.h [code]
 CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_332599425fcd5a03c822271582d4e895_dep.map b/dir_332599425fcd5a03c822271582d4e895_dep.map new file mode 100644 index 0000000..e3e00c2 --- /dev/null +++ b/dir_332599425fcd5a03c822271582d4e895_dep.map @@ -0,0 +1,4 @@ + + + + diff --git a/dir_332599425fcd5a03c822271582d4e895_dep.md5 b/dir_332599425fcd5a03c822271582d4e895_dep.md5 new file mode 100644 index 0000000..d002f4f --- /dev/null +++ b/dir_332599425fcd5a03c822271582d4e895_dep.md5 @@ -0,0 +1 @@ +dc68a62d688db9114b95be4ad854383a \ No newline at end of file diff --git a/dir_332599425fcd5a03c822271582d4e895_dep.png b/dir_332599425fcd5a03c822271582d4e895_dep.png new file mode 100644 index 0000000..c623518 Binary files /dev/null and b/dir_332599425fcd5a03c822271582d4e895_dep.png differ diff --git a/dir_3f62b6de719221ea80424f2e01628f95.html b/dir_3f62b6de719221ea80424f2e01628f95.html new file mode 100644 index 0000000..a715942 --- /dev/null +++ b/dir_3f62b6de719221ea80424f2e01628f95.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
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+
+ + +
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+
+
+
src Directory Reference
+
+
+
+Directory dependency graph for src:
+
+
discovery/libs/Pixy/src
+ + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Files

file  blob.h [code]
 
file  blobs.h [code]
 
file  calc.h [code]
 
file  chirp.cpp
 
file  chirp.hpp [code]
 
file  chirpreceiver.cpp
 
file  chirpreceiver.hpp [code]
 
file  colorlut.h [code]
 
file  debug.h [code]
 
file  debuglog.h [code]
 
file  interpreter.hpp [code]
 
file  link.h [code]
 
file  pixy.cpp
 
file  pixyinterpreter.cpp
 
file  pixyinterpreter.hpp [code]
 
file  pixytypes.h [code]
 
file  qqueue.h [code]
 
file  simplevector.h [code]
 
file  usblink.cpp
 
file  usblink.h [code]
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_3f62b6de719221ea80424f2e01628f95_dep.map b/dir_3f62b6de719221ea80424f2e01628f95_dep.map new file mode 100644 index 0000000..55041a9 --- /dev/null +++ b/dir_3f62b6de719221ea80424f2e01628f95_dep.map @@ -0,0 +1,4 @@ + + + + diff --git a/dir_3f62b6de719221ea80424f2e01628f95_dep.md5 b/dir_3f62b6de719221ea80424f2e01628f95_dep.md5 new file mode 100644 index 0000000..acede5c --- /dev/null +++ b/dir_3f62b6de719221ea80424f2e01628f95_dep.md5 @@ -0,0 +1 @@ +8070ef525ded99d1f3d10fec225168a3 \ No newline at end of file diff --git a/dir_3f62b6de719221ea80424f2e01628f95_dep.png b/dir_3f62b6de719221ea80424f2e01628f95_dep.png new file mode 100644 index 0000000..365c26e Binary files /dev/null and b/dir_3f62b6de719221ea80424f2e01628f95_dep.png differ diff --git a/dir_4126f6c26dc1ae881c4183a59fbd1908.html b/dir_4126f6c26dc1ae881c4183a59fbd1908.html new file mode 100644 index 0000000..2c9a805 --- /dev/null +++ b/dir_4126f6c26dc1ae881c4183a59fbd1908.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: discovery/libs/Pixy Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+
+
Pixy Directory Reference
+
+
+
+Directory dependency graph for Pixy:
+
+
discovery/libs/Pixy
+ + +
+ + + + +

+Directories

directory  src
 
+ + + +

+Files

file  hello_pixy.cpp
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.map b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.map new file mode 100644 index 0000000..8686512 --- /dev/null +++ b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.map @@ -0,0 +1,5 @@ + + + + + diff --git a/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.md5 b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.md5 new file mode 100644 index 0000000..6f859bd --- /dev/null +++ b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.md5 @@ -0,0 +1 @@ +3ff918bde3dfbee3e6a8c17f1ff64a43 \ No newline at end of file diff --git a/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.png b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.png new file mode 100644 index 0000000..5e537ba Binary files /dev/null and b/dir_4126f6c26dc1ae881c4183a59fbd1908_dep.png differ diff --git a/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0.html b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0.html new file mode 100644 index 0000000..ab214cf --- /dev/null +++ b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: common/pixy Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixy Directory Reference
+
+
+
+Directory dependency graph for pixy:
+
+
common/pixy
+ + +
+ + + + + + +

+Files

file  pixy.h [code]
 
file  pixydefs.h [code]
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.map b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.map new file mode 100644 index 0000000..833724d --- /dev/null +++ b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.map @@ -0,0 +1,4 @@ + + + + diff --git a/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.md5 b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.md5 new file mode 100644 index 0000000..5c7183a --- /dev/null +++ b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.md5 @@ -0,0 +1 @@ +b306b4662190255a6f7be8e318644a90 \ No newline at end of file diff --git a/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.png b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.png new file mode 100644 index 0000000..6129e0b Binary files /dev/null and b/dir_4298a0eb495ff7ff4bd3a3a3e6ccf3f0_dep.png differ diff --git a/dir_462dca7257139866f47423804ac1f6c4.html b/dir_462dca7257139866f47423804ac1f6c4.html new file mode 100644 index 0000000..85cbfb0 --- /dev/null +++ b/dir_462dca7257139866f47423804ac1f6c4.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + +
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+
src Directory Reference
+
+
+
+Directory dependency graph for src:
+
+
discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src
+ + +
+ + + + + + + + + + + + +

+Files

file  usbh_msc_bot.c
 This file includes the mass storage related functions.
 
file  usbh_msc_core.c
 
file  usbh_msc_fatfs.c
 
file  usbh_msc_scsi.c
 This file implements the SCSI commands.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_462dca7257139866f47423804ac1f6c4_dep.map b/dir_462dca7257139866f47423804ac1f6c4_dep.map new file mode 100644 index 0000000..b0ee5ca --- /dev/null +++ b/dir_462dca7257139866f47423804ac1f6c4_dep.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/dir_462dca7257139866f47423804ac1f6c4_dep.md5 b/dir_462dca7257139866f47423804ac1f6c4_dep.md5 new file mode 100644 index 0000000..e70f3ce --- /dev/null +++ b/dir_462dca7257139866f47423804ac1f6c4_dep.md5 @@ -0,0 +1 @@ +59b0bd1ef3e8011d1cca94b8e0dc5598 \ No newline at end of file diff --git a/dir_462dca7257139866f47423804ac1f6c4_dep.png b/dir_462dca7257139866f47423804ac1f6c4_dep.png new file mode 100644 index 0000000..48b76da Binary files /dev/null and b/dir_462dca7257139866f47423804ac1f6c4_dep.png differ diff --git a/dir_5668dfef4710d48cd9d7316a574bf987.html b/dir_5668dfef4710d48cd9d7316a574bf987.html new file mode 100644 index 0000000..d06268b --- /dev/null +++ b/dir_5668dfef4710d48cd9d7316a574bf987.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: common/touch Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + + +
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+ + +
+ +
+ + +
+
+
+
touch Directory Reference
+
+
+
+Directory dependency graph for touch:
+
+
common/touch
+ + +
+ + + + + + +

+Files

file  touch.c
 
file  touch.h [code]
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_5668dfef4710d48cd9d7316a574bf987_dep.map b/dir_5668dfef4710d48cd9d7316a574bf987_dep.map new file mode 100644 index 0000000..ece43e4 --- /dev/null +++ b/dir_5668dfef4710d48cd9d7316a574bf987_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_5668dfef4710d48cd9d7316a574bf987_dep.md5 b/dir_5668dfef4710d48cd9d7316a574bf987_dep.md5 new file mode 100644 index 0000000..dfca0e8 --- /dev/null +++ b/dir_5668dfef4710d48cd9d7316a574bf987_dep.md5 @@ -0,0 +1 @@ +ee734dea2430b576d7453dbd5589436b \ No newline at end of file diff --git a/dir_5668dfef4710d48cd9d7316a574bf987_dep.png b/dir_5668dfef4710d48cd9d7316a574bf987_dep.png new file mode 100644 index 0000000..3eca7fc Binary files /dev/null and b/dir_5668dfef4710d48cd9d7316a574bf987_dep.png differ diff --git a/dir_5c16f4dfa412d091e24e9c53f0796f9c.html b/dir_5c16f4dfa412d091e24e9c53f0796f9c.html new file mode 100644 index 0000000..1935d59 --- /dev/null +++ b/dir_5c16f4dfa412d091e24e9c53f0796f9c.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID Directory Reference + + + + + + + + + + +
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discoverpixy +
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HID Directory Reference
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+
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+Directory dependency graph for HID:
+
+
discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID
+ + +
+ + + + + + +

+Directories

directory  inc
 
directory  src
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.map b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.map new file mode 100644 index 0000000..ee6f7c2 --- /dev/null +++ b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.md5 b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.md5 new file mode 100644 index 0000000..361c8af --- /dev/null +++ b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.md5 @@ -0,0 +1 @@ +2624a05aa12628e721021a2153a96f5c \ No newline at end of file diff --git a/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.png b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.png new file mode 100644 index 0000000..c85961c Binary files /dev/null and b/dir_5c16f4dfa412d091e24e9c53f0796f9c_dep.png differ diff --git a/dir_5e67a00a7b81989d115187745c5becbd.html b/dir_5e67a00a7b81989d115187745c5becbd.html new file mode 100644 index 0000000..1dbb716 --- /dev/null +++ b/dir_5e67a00a7b81989d115187745c5becbd.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: emulator/libs Directory Reference + + + + + + + + + + +
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libs Directory Reference
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emulator/libs
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+Directories

directory  Pixy
 
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_5e67a00a7b81989d115187745c5becbd_dep.map b/dir_5e67a00a7b81989d115187745c5becbd_dep.map new file mode 100644 index 0000000..1cb79a8 --- /dev/null +++ b/dir_5e67a00a7b81989d115187745c5becbd_dep.map @@ -0,0 +1,5 @@ + + + + + diff --git a/dir_5e67a00a7b81989d115187745c5becbd_dep.md5 b/dir_5e67a00a7b81989d115187745c5becbd_dep.md5 new file mode 100644 index 0000000..6978f1f --- /dev/null +++ b/dir_5e67a00a7b81989d115187745c5becbd_dep.md5 @@ -0,0 +1 @@ +ef557b51d2638617c1abef6267913f06 \ No newline at end of file diff --git a/dir_5e67a00a7b81989d115187745c5becbd_dep.png b/dir_5e67a00a7b81989d115187745c5becbd_dep.png new file mode 100644 index 0000000..8046e3b Binary files /dev/null and b/dir_5e67a00a7b81989d115187745c5becbd_dep.png differ diff --git a/dir_66bf18220a0388c6a03e6ac34011f996.html b/dir_66bf18220a0388c6a03e6ac34011f996.html new file mode 100644 index 0000000..6a5de18 --- /dev/null +++ b/dir_66bf18220a0388c6a03e6ac34011f996.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc Directory Reference + + + + + + + + + + +
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inc Directory Reference
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+Directory dependency graph for inc:
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discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc
+ + +
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+Files

file  usbh_hid_core.h [code]
 This file contains all the prototypes for the usbh_hid_core.c.
 
file  usbh_hid_keybd.h [code]
 This file contains all the prototypes for the usbh_hid_keybd.c.
 
file  usbh_hid_mouse.h [code]
 This file contains all the prototypes for the usbh_hid_mouse.c.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_66bf18220a0388c6a03e6ac34011f996_dep.map b/dir_66bf18220a0388c6a03e6ac34011f996_dep.map new file mode 100644 index 0000000..78f5bd5 --- /dev/null +++ b/dir_66bf18220a0388c6a03e6ac34011f996_dep.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/dir_66bf18220a0388c6a03e6ac34011f996_dep.md5 b/dir_66bf18220a0388c6a03e6ac34011f996_dep.md5 new file mode 100644 index 0000000..10dd899 --- /dev/null +++ b/dir_66bf18220a0388c6a03e6ac34011f996_dep.md5 @@ -0,0 +1 @@ +e8f6a849ca9449c334925e5ae60eb5aa \ No newline at end of file diff --git a/dir_66bf18220a0388c6a03e6ac34011f996_dep.png b/dir_66bf18220a0388c6a03e6ac34011f996_dep.png new file mode 100644 index 0000000..4fc1d7a Binary files /dev/null and b/dir_66bf18220a0388c6a03e6ac34011f996_dep.png differ diff --git a/dir_670eadf4dd11274b06180e76ece9fdbb.html b/dir_670eadf4dd11274b06180e76ece9fdbb.html new file mode 100644 index 0000000..4216ab5 --- /dev/null +++ b/dir_670eadf4dd11274b06180e76ece9fdbb.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src Directory Reference + + + + + + + + + + +
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src Directory Reference
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+Directory dependency graph for src:
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discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src
+ + +
+ + + + + + + + + + + +

+Files

file  usbh_hid_core.c
 This file is the HID Layer Handlers for USB Host HID class.
 
file  usbh_hid_keybd.c
 This file is the application layer for USB Host HID Keyboard handling QWERTY and AZERTY Keyboard are supported as per the selection in usbh_hid_keybd.h.
 
file  usbh_hid_mouse.c
 This file is the application layer for USB Host HID Mouse Handling.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_670eadf4dd11274b06180e76ece9fdbb_dep.map b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.map new file mode 100644 index 0000000..4ae4013 --- /dev/null +++ b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_670eadf4dd11274b06180e76ece9fdbb_dep.md5 b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.md5 new file mode 100644 index 0000000..7a9aaea --- /dev/null +++ b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.md5 @@ -0,0 +1 @@ +2daad32d6c8190eb50ac7f6292bbacc1 \ No newline at end of file diff --git a/dir_670eadf4dd11274b06180e76ece9fdbb_dep.png b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.png new file mode 100644 index 0000000..cca10fd Binary files /dev/null and b/dir_670eadf4dd11274b06180e76ece9fdbb_dep.png differ diff --git a/dir_73c9649cd1892d880e57f5a32368877e.html b/dir_73c9649cd1892d880e57f5a32368877e.html new file mode 100644 index 0000000..e69c62e --- /dev/null +++ b/dir_73c9649cd1892d880e57f5a32368877e.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: common/lowlevel Directory Reference + + + + + + + + + + +
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discoverpixy +
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lowlevel Directory Reference
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+
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+Directory dependency graph for lowlevel:
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common/lowlevel
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+Files

file  ll_filesystem.h [code]
 
file  ll_system.h [code]
 
file  ll_tft.h [code]
 
file  ll_touch.h [code]
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_73c9649cd1892d880e57f5a32368877e_dep.map b/dir_73c9649cd1892d880e57f5a32368877e_dep.map new file mode 100644 index 0000000..adae756 --- /dev/null +++ b/dir_73c9649cd1892d880e57f5a32368877e_dep.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/dir_73c9649cd1892d880e57f5a32368877e_dep.md5 b/dir_73c9649cd1892d880e57f5a32368877e_dep.md5 new file mode 100644 index 0000000..71c68c4 --- /dev/null +++ b/dir_73c9649cd1892d880e57f5a32368877e_dep.md5 @@ -0,0 +1 @@ +9680eb6ce2160d097a8646fa50be7c82 \ No newline at end of file diff --git a/dir_73c9649cd1892d880e57f5a32368877e_dep.png b/dir_73c9649cd1892d880e57f5a32368877e_dep.png new file mode 100644 index 0000000..11350c1 Binary files /dev/null and b/dir_73c9649cd1892d880e57f5a32368877e_dep.png differ diff --git a/dir_82ac59d6ff70989672cdfd367a0f9fdd.html b/dir_82ac59d6ff70989672cdfd367a0f9fdd.html new file mode 100644 index 0000000..a80c546 --- /dev/null +++ b/dir_82ac59d6ff70989672cdfd367a0f9fdd.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src Directory Reference + + + + + + + + + + +
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src Directory Reference
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+Directory dependency graph for src:
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discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src
+ + +
+ + + + + + + + + + + +

+Files

file  usb_core.c
 USB-OTG Core Layer.
 
file  usb_hcd.c
 Host Interface Layer.
 
file  usb_hcd_int.c
 Host driver interrupt subroutines.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.map b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.map new file mode 100644 index 0000000..ad09de9 --- /dev/null +++ b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.md5 b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.md5 new file mode 100644 index 0000000..73aff5a --- /dev/null +++ b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.md5 @@ -0,0 +1 @@ +b0758634faa765c92554408276db759b \ No newline at end of file diff --git a/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.png b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.png new file mode 100644 index 0000000..3c724a1 Binary files /dev/null and b/dir_82ac59d6ff70989672cdfd367a0f9fdd_dep.png differ diff --git a/dir_84db96586f7d962b526d6d9627d831c2.html b/dir_84db96586f7d962b526d6d9627d831c2.html new file mode 100644 index 0000000..812111e --- /dev/null +++ b/dir_84db96586f7d962b526d6d9627d831c2.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: discovery Directory Reference + + + + + + + + + + +
+
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discoverpixy +
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discovery Directory Reference
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+Directory dependency graph for discovery:
+
+
discovery
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+Directories

directory  src
 
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_84db96586f7d962b526d6d9627d831c2_dep.map b/dir_84db96586f7d962b526d6d9627d831c2_dep.map new file mode 100644 index 0000000..43bf3b4 --- /dev/null +++ b/dir_84db96586f7d962b526d6d9627d831c2_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_84db96586f7d962b526d6d9627d831c2_dep.md5 b/dir_84db96586f7d962b526d6d9627d831c2_dep.md5 new file mode 100644 index 0000000..4bb22e8 --- /dev/null +++ b/dir_84db96586f7d962b526d6d9627d831c2_dep.md5 @@ -0,0 +1 @@ +e4fd4b37d6c2109d42e85e521bd90c30 \ No newline at end of file diff --git a/dir_84db96586f7d962b526d6d9627d831c2_dep.png b/dir_84db96586f7d962b526d6d9627d831c2_dep.png new file mode 100644 index 0000000..663bef4 Binary files /dev/null and b/dir_84db96586f7d962b526d6d9627d831c2_dep.png differ diff --git a/dir_8afe10de55c8b894271ff1b0bd6e1529.html b/dir_8afe10de55c8b894271ff1b0bd6e1529.html new file mode 100644 index 0000000..888fb6e --- /dev/null +++ b/dir_8afe10de55c8b894271ff1b0bd6e1529.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC Directory Reference + + + + + + + + + + +
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discoverpixy +
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MSC Directory Reference
+
+
+
+Directory dependency graph for MSC:
+
+
discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC
+ + +
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+Directories

directory  inc
 
directory  src
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.map b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.map new file mode 100644 index 0000000..b0d0c0e --- /dev/null +++ b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.md5 b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.md5 new file mode 100644 index 0000000..2490321 --- /dev/null +++ b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.md5 @@ -0,0 +1 @@ +ef259fee4f58d35ba0e9e7f422ed6c53 \ No newline at end of file diff --git a/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.png b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.png new file mode 100644 index 0000000..f132aac Binary files /dev/null and b/dir_8afe10de55c8b894271ff1b0bd6e1529_dep.png differ diff --git a/dir_8f72225b67c51b4125f900f2cdfb2cf4.html b/dir_8f72225b67c51b4125f900f2cdfb2cf4.html new file mode 100644 index 0000000..40d0f22 --- /dev/null +++ b/dir_8f72225b67c51b4125f900f2cdfb2cf4.html @@ -0,0 +1,119 @@ + + + + + + +discoverpixy: emulator/qt Directory Reference + + + + + + + + + + +
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discoverpixy +
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qt Directory Reference
+
+
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+Directory dependency graph for qt:
+
+
emulator/qt
+ + +
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+Files

file  ll_filesystem.cpp
 
file  ll_system.cpp
 
file  ll_tft.cpp
 
file  ll_touch.cpp
 
file  main.cpp
 
file  mainwindow.cpp
 
file  mainwindow.h [code]
 
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.map b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.map new file mode 100644 index 0000000..a7ce0f6 --- /dev/null +++ b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.md5 b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.md5 new file mode 100644 index 0000000..2f150f5 --- /dev/null +++ b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.md5 @@ -0,0 +1 @@ +1a87ace57002d586181ef2959ad5c0a7 \ No newline at end of file diff --git a/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.png b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.png new file mode 100644 index 0000000..fdb84d8 Binary files /dev/null and b/dir_8f72225b67c51b4125f900f2cdfb2cf4_dep.png differ diff --git a/dir_99a8943037ff3844556e6a5d529fec0c.html b/dir_99a8943037ff3844556e6a5d529fec0c.html new file mode 100644 index 0000000..0e6a687 --- /dev/null +++ b/dir_99a8943037ff3844556e6a5d529fec0c.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: common/app Directory Reference + + + + + + + + + + +
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discoverpixy +
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app Directory Reference
+
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+Directory dependency graph for app:
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common/app
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+Files

file  app.c
 
file  app.h [code]
 
file  screen_filetest.c
 
file  screen_filetest.h [code]
 
file  screen_guitest.c
 
file  screen_guitest.h [code]
 
file  screen_main.c
 
file  screen_main.h [code]
 
file  screen_pixytest.c
 
file  screen_pixytest.h [code]
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_99a8943037ff3844556e6a5d529fec0c_dep.map b/dir_99a8943037ff3844556e6a5d529fec0c_dep.map new file mode 100644 index 0000000..f229009 --- /dev/null +++ b/dir_99a8943037ff3844556e6a5d529fec0c_dep.map @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/dir_99a8943037ff3844556e6a5d529fec0c_dep.md5 b/dir_99a8943037ff3844556e6a5d529fec0c_dep.md5 new file mode 100644 index 0000000..d33e1c3 --- /dev/null +++ b/dir_99a8943037ff3844556e6a5d529fec0c_dep.md5 @@ -0,0 +1 @@ +17f15595e3eb301e49aa289c55f03154 \ No newline at end of file diff --git a/dir_99a8943037ff3844556e6a5d529fec0c_dep.png b/dir_99a8943037ff3844556e6a5d529fec0c_dep.png new file mode 100644 index 0000000..5d4366d Binary files /dev/null and b/dir_99a8943037ff3844556e6a5d529fec0c_dep.png differ diff --git a/dir_a041ff5c2b284f3abb06af95928aadaf.html b/dir_a041ff5c2b284f3abb06af95928aadaf.html new file mode 100644 index 0000000..0977657 --- /dev/null +++ b/dir_a041ff5c2b284f3abb06af95928aadaf.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost Directory Reference + + + + + + + + + + +
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discoverpixy +
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+
StmUsbHost Directory Reference
+
+
+
+Directory dependency graph for StmUsbHost:
+
+
discovery/libs/StmUsbHost
+ + +
+ + + + + + + + +

+Directories

directory  STM32_USB_Device_Specific
 
directory  STM32_USB_HOST_Library
 
directory  STM32_USB_OTG_Driver
 
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_a041ff5c2b284f3abb06af95928aadaf_dep.map b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.map new file mode 100644 index 0000000..b7b8dc7 --- /dev/null +++ b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dir_a041ff5c2b284f3abb06af95928aadaf_dep.md5 b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.md5 new file mode 100644 index 0000000..09e68e6 --- /dev/null +++ b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.md5 @@ -0,0 +1 @@ +25fddaea3a8246e1c3d65fbce497be00 \ No newline at end of file diff --git a/dir_a041ff5c2b284f3abb06af95928aadaf_dep.png b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.png new file mode 100644 index 0000000..2e3d795 Binary files /dev/null and b/dir_a041ff5c2b284f3abb06af95928aadaf_dep.png differ diff --git a/dir_a923f6237451b7927c5387e7906a14c5.html b/dir_a923f6237451b7927c5387e7906a14c5.html new file mode 100644 index 0000000..acf6549 --- /dev/null +++ b/dir_a923f6237451b7927c5387e7906a14c5.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc Directory Reference + + + + + + + + + + +
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inc Directory Reference
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discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc
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+Files

file  usb_bsp.h [code]
 Specific api's relative to the used hardware platform.
 
file  usb_core.h [code]
 Header of the Core Layer.
 
file  usb_defines.h [code]
 Header of the Core Layer.
 
file  usb_hcd.h [code]
 Host layer Header file.
 
file  usb_hcd_int.h [code]
 Peripheral Device Interface Layer.
 
file  usb_regs.h [code]
 hardware registers
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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file  screen.h [code]
 
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STM32_USB_HOST_Library Directory Reference
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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inc Directory Reference
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discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc
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+Files

file  usbh_conf_template.h [code]
 
file  usbh_core.h [code]
 Header file for usbh_core.c.
 
file  usbh_def.h [code]
 Definitions used in the USB host library.
 
file  usbh_hcs.h [code]
 Header file for usbh_hcs.c.
 
file  usbh_ioreq.h [code]
 Header file for usbh_ioreq.c.
 
file  usbh_stdreq.h [code]
 Header file for usbh_stdreq.c.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_c54195ff74a664fd72168276b9d2230f_dep.map b/dir_c54195ff74a664fd72168276b9d2230f_dep.map new file mode 100644 index 0000000..003655b --- /dev/null +++ b/dir_c54195ff74a664fd72168276b9d2230f_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_c54195ff74a664fd72168276b9d2230f_dep.md5 b/dir_c54195ff74a664fd72168276b9d2230f_dep.md5 new file mode 100644 index 0000000..3662c49 --- /dev/null +++ b/dir_c54195ff74a664fd72168276b9d2230f_dep.md5 @@ -0,0 +1 @@ +51738f7bc6870adec7b6aeb69809341c \ No newline at end of file diff --git a/dir_c54195ff74a664fd72168276b9d2230f_dep.png b/dir_c54195ff74a664fd72168276b9d2230f_dep.png new file mode 100644 index 0000000..caf263b Binary files /dev/null and b/dir_c54195ff74a664fd72168276b9d2230f_dep.png differ diff --git a/dir_c7d50235deb86c44ba1d720cd0b3ba7f.html b/dir_c7d50235deb86c44ba1d720cd0b3ba7f.html new file mode 100644 index 0000000..6948a2e --- /dev/null +++ b/dir_c7d50235deb86c44ba1d720cd0b3ba7f.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_Device_Specific Directory Reference + + + + + + + + + + +
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STM32_USB_Device_Specific Directory Reference
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+Directory dependency graph for STM32_USB_Device_Specific:
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discovery/libs/StmUsbHost/STM32_USB_Device_Specific
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+Files

file  usb_conf.h [code]
 
file  usbh_conf.h [code]
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Files

file  ll_filesystem.c
 
file  ll_system.c
 
file  ll_tft.c
 
file  ll_touch.c
 
file  main.c
 
file  newlib_stubs.c
 
file  usb_bsp.c
 
file  usbh_msc_core.c
 
file  usbh_msc_core.h [code]
 
file  usbh_usr.c
 
file  usbh_usr.h [code]
 
+
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32_USB_OTG_Driver Directory Reference
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file  tft.c
 
file  tft.h [code]
 
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_e222ac1ff707f15b04869ea0388b9123_dep.map b/dir_e222ac1ff707f15b04869ea0388b9123_dep.map new file mode 100644 index 0000000..feac10e --- /dev/null +++ b/dir_e222ac1ff707f15b04869ea0388b9123_dep.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/dir_e222ac1ff707f15b04869ea0388b9123_dep.md5 b/dir_e222ac1ff707f15b04869ea0388b9123_dep.md5 new file mode 100644 index 0000000..26b2c26 --- /dev/null +++ b/dir_e222ac1ff707f15b04869ea0388b9123_dep.md5 @@ -0,0 +1 @@ +53b5c9c3fc0af74739c0f5703c5e1f6c \ No newline at end of file diff --git a/dir_e222ac1ff707f15b04869ea0388b9123_dep.png b/dir_e222ac1ff707f15b04869ea0388b9123_dep.png new file mode 100644 index 0000000..5781d0e Binary files /dev/null and b/dir_e222ac1ff707f15b04869ea0388b9123_dep.png differ diff --git a/dir_e6f5a60ec0646f174eb6ca4de6df9af4.html b/dir_e6f5a60ec0646f174eb6ca4de6df9af4.html new file mode 100644 index 0000000..36e612d --- /dev/null +++ b/dir_e6f5a60ec0646f174eb6ca4de6df9af4.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core Directory Reference + + + + + + + + + + +
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Core Directory Reference
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.map b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.map new file mode 100644 index 0000000..b2fbb8c --- /dev/null +++ b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.md5 b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.md5 new file mode 100644 index 0000000..95dce12 --- /dev/null +++ b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.md5 @@ -0,0 +1 @@ +3522bce4172dd7c68c60a4db6f298920 \ No newline at end of file diff --git a/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.png b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.png new file mode 100644 index 0000000..628fd69 Binary files /dev/null and b/dir_e6f5a60ec0646f174eb6ca4de6df9af4_dep.png differ diff --git a/dir_f48834cc35865346fa45c42d884e2e36.html b/dir_f48834cc35865346fa45c42d884e2e36.html new file mode 100644 index 0000000..d3d58a0 --- /dev/null +++ b/dir_f48834cc35865346fa45c42d884e2e36.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src Directory Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+
+ + +
+ +
+ + +
+
+
+
src Directory Reference
+
+
+
+Directory dependency graph for src:
+
+
discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src
+ + +
+ + + + + + + + + + + + + + +

+Files

file  usbh_core.c
 This file implements the functions for the core state machine process the enumeration and the control transfer process.
 
file  usbh_hcs.c
 This file implements functions for opening and closing host channels.
 
file  usbh_ioreq.c
 This file handles the issuing of the USB transactions.
 
file  usbh_stdreq.c
 This file implements the standard requests for device enumeration.
 
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/dir_f48834cc35865346fa45c42d884e2e36_dep.map b/dir_f48834cc35865346fa45c42d884e2e36_dep.map new file mode 100644 index 0000000..e1a2b1a --- /dev/null +++ b/dir_f48834cc35865346fa45c42d884e2e36_dep.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/dir_f48834cc35865346fa45c42d884e2e36_dep.md5 b/dir_f48834cc35865346fa45c42d884e2e36_dep.md5 new file mode 100644 index 0000000..925cf58 --- /dev/null +++ b/dir_f48834cc35865346fa45c42d884e2e36_dep.md5 @@ -0,0 +1 @@ +112458753e13281d133c8713a4ed54a3 \ No newline at end of file diff --git a/dir_f48834cc35865346fa45c42d884e2e36_dep.png b/dir_f48834cc35865346fa45c42d884e2e36_dep.png new file mode 100644 index 0000000..0bf5dc8 Binary files /dev/null and b/dir_f48834cc35865346fa45c42d884e2e36_dep.png differ diff --git a/discovery_2libs_2_pixy_2src_2blob_8h_source.html b/discovery_2libs_2_pixy_2src_2blob_8h_source.html new file mode 100644 index 0000000..6d7ae23 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2blob_8h_source.html @@ -0,0 +1,464 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/blob.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
blob.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef _BLOB_H
+
16 #define _BLOB_H
+
17 
+
18 // TODO
+
19 //
+
20 // *** Priority 1
+
21 //
+
22 // *** Priority 2:
+
23 //
+
24 // *** Priority 3:
+
25 //
+
26 // *** Priority 4:
+
27 //
+
28 // Think about heap management of CBlobs
+
29 // Think about heap management of SLinkedSegments
+
30 //
+
31 // *** Priority 5 (maybe never do):
+
32 //
+
33 // Try small and large SMoments structure (small for segment)
+
34 // Try more efficient SSegment structure for lastBottom, nextBottom
+
35 //
+
36 // *** DONE
+
37 //
+
38 // DONE Compute elongation, major/minor axes (SMoments::GetStats)
+
39 // DONE Make XRC LUT
+
40 // DONE Use XRC LUT
+
41 // DONE Optimize blob assy
+
42 // DONE Start compiling
+
43 // DONE Conditionally record segments
+
44 // DONE Ask rich about FP, trig
+
45 // Take segmented image in (DONE in imageserver.cc, ARW 10/7/04)
+
46 // Produce colored segmented image out (DONE in imageserver.cc, ARW 10/7/04)
+
47 // Draw blob stats in image out (DONE for centroid, bounding box
+
48 // in imageserver.cc, ARW 10/7/04)
+
49 // Delete segments when deleting blob (DONE, ARW 10/7/04)
+
50 // Check to see if we attach to multiple blobs (DONE, ARW 10/7/04)
+
51 // Sort blobs according to area (DONE, ARW 10/7/04)
+
52 // DONE Sort blobs according to area
+
53 // DONE Clean up code
+
54 
+
55 #include <stdlib.h>
+
56 #include <assert.h>
+
57 //#include <memory.h>
+
58 #include <math.h>
+
59 
+
60 //#define INCLUDE_STATS
+
61 
+
62 // Uncomment this for verbose output for testing
+
63 //#include <iostream.h>
+
64 
+
65 struct SMomentStats {
+
66  int area;
+
67  // X is 0 on the left side of the image and increases to the right
+
68  // Y is 0 on the top of the image and increases to the bottom
+
69  float centroidX, centroidY;
+
70  // angle is 0 to PI, in radians.
+
71  // 0 points to the right (positive X)
+
72  // PI/2 points downward (positive Y)
+
73  float angle;
+
74  float majorDiameter;
+
75  float minorDiameter;
+
76 };
+
77 
+
78 // Image size is 352x278
+
79 // Full-screen blob area is 97856
+
80 // Full-screen centroid is 176,139
+
81 // sumX, sumY is then 17222656, 13601984; well within 32 bits
+
82 struct SMoments {
+
83  // Skip major/minor axis computation when this is false
+
84  static bool computeAxes;
+
85 
+
86  int area; // number of pixels
+
87  void Reset() {
+
88  area = 0;
+
89 #ifdef INCLUDE_STATS
+
90  sumX= sumY= sumXX= sumYY= sumXY= 0;
+
91 #endif
+
92  }
+
93 #ifdef INCLUDE_STATS
+
94  int sumX; // sum of pixel x coords
+
95  int sumY; // sum of pixel y coords
+
96  // XX, XY, YY used for major/minor axis calculation
+
97  long long sumXX; // sum of x^2 for each pixel
+
98  long long sumYY; // sum of y^2 for each pixel
+
99  long long sumXY; // sum of x*y for each pixel
+
100 #endif
+
101  void Add(const SMoments &moments) {
+
102  area += moments.area;
+
103 #ifdef INCLUDE_STATS
+
104  sumX += moments.sumX;
+
105  sumY += moments.sumY;
+
106  if (computeAxes) {
+
107  sumXX += moments.sumXX;
+
108  sumYY += moments.sumYY;
+
109  sumXY += moments.sumXY;
+
110  }
+
111 #endif
+
112  }
+
113 #ifdef INCLUDE_STATS
+
114  void GetStats(SMomentStats &stats) const;
+
115  bool operator==(const SMoments &rhs) const {
+
116  if (area != rhs.area) return 0;
+
117  if (sumX != rhs.sumX) return 0;
+
118  if (sumY != rhs.sumY) return 0;
+
119  if (computeAxes) {
+
120  if (sumXX != rhs.sumXX) return 0;
+
121  if (sumYY != rhs.sumYY) return 0;
+
122  if (sumXY != rhs.sumXY) return 0;
+
123  }
+
124  return 1;
+
125  }
+
126 #endif
+
127 };
+
128 
+
129 struct SSegment {
+
130  unsigned char model : 3 ; // which color channel
+
131  unsigned short row : 9 ;
+
132  unsigned short startCol : 10; // inclusive
+
133  unsigned short endCol : 10; // inclusive
+
134 
+
135  const static short invalid_row= 0x1ff;
+
136 
+
137  // Sum 0^2 + 1^2 + 2^2 + ... + n^2 is (2n^3 + 3n^2 + n) / 6
+
138  // Sum (a+1)^2 + (a+2)^2 ... b^2 is (2(b^3-a^3) + 3(b^2-a^2) + (b-a)) / 6
+
139  //
+
140  // Sum 0+1+2+3+...+n is (n^2 + n)/2
+
141  // Sum (a+1) + (a+2) ... b is (b^2-a^2 + b-a)/2
+
142 
+
143  void GetMoments(SMoments &moments) const {
+
144  int s= startCol - 1;
+
145  int e= endCol;
+
146 
+
147  moments.area = (e-s);
+
148 #ifdef INCLUDE_STATS
+
149  int e2= e*e;
+
150  int y= row;
+
151  int s2= s*s;
+
152  moments.sumX = ( (e2-s2) + (e-s) ) / 2;
+
153  moments.sumY = (e-s) * y;
+
154 
+
155  if (SMoments::computeAxes) {
+
156  int e3= e2*e;
+
157  int s3= s2*s;
+
158  moments.sumXY= moments.sumX*y;
+
159  moments.sumXX= (2*(e3-s3) + 3*(e2-s2) + (e-s)) / 6;
+
160  moments.sumYY= moments.sumY*y;
+
161  }
+
162 #endif
+
163  }
+
164 #ifdef INCLUDE_STATS
+
165  void GetMomentsTest(SMoments &moments) const;
+
166 #endif
+
167 };
+
168 
+
169 struct SLinkedSegment {
+
170  SSegment segment;
+
171  SLinkedSegment *next;
+
172  SLinkedSegment(const SSegment &segmentInit) :
+
173  segment(segmentInit), next(NULL) {}
+
174 };
+
175 
+
176 class CBlob {
+
177  // These are at the beginning for fast inclusion checking
+
178 public:
+
179  static int leakcheck;
+
180  CBlob *next; // next ptr for linked list
+
181 
+
182  // Bottom of blob, which is the surface we'll attach more segments to
+
183  // If bottom of blob contains multiple segments, this is the smallest
+
184  // segment containing the multiple segments
+
185  SSegment lastBottom;
+
186 
+
187  // Next bottom of blob, currently under construction
+
188  SSegment nextBottom;
+
189 
+
190  // Bounding box, inclusive. nextBottom.row contains the "bottom"
+
191  short left, top, right;
+
192 
+
193  void getBBox(short &leftRet, short &topRet,
+
194  short &rightRet, short &bottomRet) {
+
195  leftRet= left;
+
196  topRet= top;
+
197  rightRet= right;
+
198  bottomRet= lastBottom.row;
+
199  }
+
200 
+
201  // Segments which compose the blob
+
202  // Only recorded if CBlob::recordSegments is true
+
203  // firstSegment points to first segment in linked list
+
204  SLinkedSegment *firstSegment;
+
205  // lastSegmentPtr points to the next pointer field _inside_ the
+
206  // last element of the linked list. This is the field you would
+
207  // modify in order to append to the end of the list. Therefore
+
208  // **lastSegmentPtr should always equal to NULL.
+
209  // When the list is empty, lastSegmentPtr actually doesn't point inside
+
210  // a SLinkedSegment structure at all but instead at the firstSegment
+
211  // field above, which in turn is NULL.
+
212  SLinkedSegment **lastSegmentPtr;
+
213 
+
214  SMoments moments;
+
215 
+
216  static bool recordSegments;
+
217  // Set to true for testing code only. Very slow!
+
218  static bool testMoments;
+
219 
+
220  CBlob();
+
221  ~CBlob();
+
222 
+
223  int GetArea() const {
+
224  return(moments.area);
+
225  }
+
226 
+
227  // Clear blob data and free segments, if any
+
228  void Reset();
+
229 
+
230  void NewRow();
+
231 
+
232  void Add(const SSegment &segment);
+
233 
+
234  // This takes futileResister and assimilates it into this blob
+
235  //
+
236  // Takes advantage of the fact that we are always assembling top to
+
237  // bottom, left to right.
+
238  //
+
239  // Be sure to call like so:
+
240  // leftblob.Assimilate(rightblob);
+
241  //
+
242  // This lets us assume two things:
+
243  // 1) The assimilated blob contains no segments on the current row
+
244  // 2) The assimilated blob lastBottom surface is to the right
+
245  // of this blob's lastBottom surface
+
246  void Assimilate(CBlob &futileResister);
+
247 
+
248  // Only updates left, top, and right. bottom is updated
+
249  // by UpdateAttachmentSurface below
+
250  void UpdateBoundingBox(int newLeft, int newTop, int newRight);
+
251 };
+
252 
+
253 // Strategy for using CBlobAssembler:
+
254 //
+
255 // Make one CBlobAssembler for each color channel.
+
256 // CBlobAssembler ignores the model index, so you need to be sure to
+
257 // only pass the correct segments to each CBlobAssembler.
+
258 //
+
259 // At the beginning of a frame, call Reset() on each assembler
+
260 // As segments appear, call Add(segment)
+
261 // At the end of a frame, call EndFrame() on each assembler
+
262 // Get blobs from finishedBlobs. Blobs will remain valid until
+
263 // the next call to Reset(), at which point they will be deleted.
+
264 //
+
265 // To get statistics for a blob, do the following:
+
266 // SMomentStats stats;
+
267 // blob->moments.GetStats(stats);
+
268 // (See imageserver.cc: draw_blob() for an example)
+
269 
+
270 class CBlobAssembler {
+
271  short currentRow;
+
272 
+
273  // Active blobs, in left to right order
+
274  // (Active means we are still potentially adding segments)
+
275  CBlob *activeBlobs;
+
276 
+
277  // Current candidate for adding a segment to. This is a member
+
278  // of activeBlobs, and scans left to right as we search the active blobs.
+
279  CBlob *currentBlob;
+
280 
+
281  // Pointer to pointer to current candidate, which is actually the pointer
+
282  // to the "next" field inside the previous candidate, or a pointer to
+
283  // the activeBlobs field of this object if the current candidate is the
+
284  // first element of the activeBlobs list. Used for inserting and
+
285  // deleting blobs.
+
286  CBlob **previousBlobPtr;
+
287 
+
288 public:
+
289  // Blobs we're no longer adding to
+
290  CBlob *finishedBlobs;
+
291  short maxRowDelta;
+
292  static bool keepFinishedSorted;
+
293 
+
294 public:
+
295  CBlobAssembler();
+
296  ~CBlobAssembler();
+
297 
+
298  // Call prior to starting a frame
+
299  // Deletes any previously created blobs
+
300  void Reset();
+
301 
+
302 
+
303  // Call once for each segment in the color channel
+
304  int Add(const SSegment &segment);
+
305 
+
306  // Call at end of frame
+
307  // Moves all active blobs to finished list
+
308  void EndFrame();
+
309 
+
310  int ListLength(const CBlob *b);
+
311 
+
312  // Split a list of blobs into two halves
+
313  void SplitList(CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf);
+
314 
+
315  // Merge maxelts elements from old1 and old2 into newptr
+
316  void MergeLists(CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts);
+
317 
+
318  // Sorts finishedBlobs in order of descending area using an in-place
+
319  // merge sort (time n log n)
+
320  void SortFinished();
+
321 
+
322  // Assert that finishedBlobs is in fact sorted. For testing only.
+
323  void AssertFinishedSorted();
+
324 
+
325 protected:
+
326  // Manage currentBlob
+
327  //
+
328  // We always want to guarantee that both currentBlob
+
329  // and currentBlob->next have had NewRow() called, and have
+
330  // been validated to remain on the active list. We could just
+
331  // do this for all activeBlobs at the beginning of each row,
+
332  // but it's less work to only do it on demand as segments come in
+
333  // since it might allow us to skip blobs for a given row
+
334  // if there are no segments which might overlap.
+
335 
+
336  // BlobNewRow:
+
337  //
+
338  // Tell blob there is a new row of data, and confirm that the
+
339  // blob should still be on the active list by seeing if too many
+
340  // rows have elapsed since the last segment was added.
+
341  //
+
342  // If blob should no longer be on the active list, remove it and
+
343  // place on the finished list, and skip to the next blob.
+
344  //
+
345  // Call this either zero or one time per blob per row, never more.
+
346  //
+
347  // Pass in the pointer to the "next" field pointing to the blob, so
+
348  // we can delete the blob from the linked list if it's not valid.
+
349 
+
350  void BlobNewRow(CBlob **ptr);
+
351  void RewindCurrent();
+
352  void AdvanceCurrent();
+
353 
+
354  int m_blobCount;
+
355 };
+
356 
+
357 #endif // _BLOB_H
+
CBlobAssembler
Definition: blob.h:270
+
CBlob
Definition: blob.h:176
+
SMoments
Definition: blob.h:82
+
SMomentStats
Definition: blob.h:65
+
SSegment
Definition: blob.h:129
+
SLinkedSegment
Definition: blob.h:169
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2blobs_8h_source.html b/discovery_2libs_2_pixy_2src_2blobs_8h_source.html new file mode 100644 index 0000000..ae227ca --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2blobs_8h_source.html @@ -0,0 +1,217 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/blobs.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
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+
blobs.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef BLOBS_H
+
16 #define BLOBS_H
+
17 
+
18 #include <stdint.h>
+
19 #include "blob.h"
+
20 #include "pixytypes.h"
+
21 #include "colorlut.h"
+
22 #include "qqueue.h"
+
23 
+
24 #define MAX_BLOBS 100
+
25 #define MAX_BLOBS_PER_MODEL 20
+
26 #define MAX_MERGE_DIST 5
+
27 #define MIN_AREA 20
+
28 #define MIN_COLOR_CODE_AREA 10
+
29 #define MAX_CODED_DIST 6
+
30 #define MAX_COLOR_CODE_MODELS 5
+
31 
+
32 #define BL_BEGIN_MARKER 0xaa55
+
33 #define BL_BEGIN_MARKER_CC 0xaa56
+
34 
+
35 enum ColorCodeMode
+
36 {
+
37  DISABLED = 0,
+
38  ENABLED = 1,
+
39  CC_ONLY = 2,
+
40  MIXED = 3 // experimental
+
41 };
+
42 
+
43 class Blobs
+
44 {
+
45 public:
+
46  Blobs(Qqueue *qq, uint8_t *lut);
+
47  ~Blobs();
+
48  int blobify();
+
49  uint16_t getBlock(uint8_t *buf, uint32_t buflen);
+
50  uint16_t getCCBlock(uint8_t *buf, uint32_t buflen);
+
51  BlobA *getMaxBlob(uint16_t signature=0);
+
52  void getBlobs(BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen);
+
53  int setParams(uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode);
+
54  int runlengthAnalysis();
+
55 #ifndef PIXY
+
56  void getRunlengths(uint32_t **qvals, uint32_t *len);
+
57 #endif
+
58 
+
59  ColorLUT m_clut;
+
60  Qqueue *m_qq;
+
61 
+
62 private:
+
63  int handleSegment(uint8_t signature, uint16_t row, uint16_t startCol, uint16_t length);
+
64  void endFrame();
+
65  uint16_t combine(uint16_t *blobs, uint16_t numBlobs);
+
66  uint16_t combine2(uint16_t *blobs, uint16_t numBlobs);
+
67  uint16_t compress(uint16_t *blobs, uint16_t numBlobs);
+
68 
+
69  bool closeby(BlobA *blob0, BlobA *blob1);
+
70  int16_t distance(BlobA *blob0, BlobA *blob1);
+
71  void sort(BlobA *blobs[], uint16_t len, BlobA *firstBlob, bool horiz);
+
72  int16_t angle(BlobA *blob0, BlobA *blob1);
+
73  int16_t distance(BlobA *blob0, BlobA *blob1, bool horiz);
+
74  void processCC();
+
75  void cleanup(BlobA *blobs[], int16_t *numBlobs);
+
76  void cleanup2(BlobA *blobs[], int16_t *numBlobs);
+
77  bool analyzeDistances(BlobA *blobs0[], int16_t numBlobs0, BlobA *blobs[], int16_t numBlobs, BlobA **blobA, BlobA **blobB);
+
78  void mergeClumps(uint16_t scount0, uint16_t scount1);
+
79 
+
80  void printBlobs();
+
81 
+
82  CBlobAssembler m_assembler[CL_NUM_SIGNATURES];
+
83 
+
84  uint16_t *m_blobs;
+
85  uint16_t m_numBlobs;
+
86 
+
87  BlobB *m_ccBlobs;
+
88  uint16_t m_numCCBlobs;
+
89 
+
90  bool m_mutex;
+
91  uint16_t m_maxBlobs;
+
92  uint16_t m_maxBlobsPerModel;
+
93 
+
94  uint16_t m_blobReadIndex;
+
95  uint16_t m_ccBlobReadIndex;
+
96 
+
97  uint32_t m_minArea;
+
98  uint16_t m_mergeDist;
+
99  uint16_t m_maxCodedDist;
+
100  ColorCodeMode m_ccMode;
+
101  BlobA *m_maxBlob;
+
102 
+
103 #ifndef PIXY
+
104  uint32_t m_numQvals;
+
105  uint32_t *m_qvals;
+
106 #endif
+
107 };
+
108 
+
109 
+
110 
+
111 #endif // BLOBS_H
+
CBlobAssembler
Definition: blob.h:270
+
BlobA
Definition: pixytypes.h:133
+
BlobB
Definition: pixytypes.h:156
+
Blobs
Definition: blobs.h:43
+
ColorLUT
Definition: colorlut.h:86
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2calc_8h_source.html b/discovery_2libs_2_pixy_2src_2calc_8h_source.html new file mode 100644 index 0000000..a22255d --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2calc_8h_source.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/calc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
calc.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef CALC_H
+
17 #define CALC_H
+
18 #include <inttypes.h>
+
19 
+
20 #ifdef MAX
+
21 #undef MAX
+
22 #endif
+
23 #ifdef MIN
+
24 #undef MIN
+
25 #endif
+
26 #define MAX(a, b) (a>b ? a : b)
+
27 #define MIN(a, b) (a<b ? a : b)
+
28 
+
29 void hsvc(uint8_t r, uint8_t g, uint8_t b, uint8_t *h, uint8_t *s, uint8_t *v, uint8_t *c);
+
30 uint32_t lighten(uint32_t color, uint8_t factor);
+
31 uint32_t saturate(uint32_t color);
+
32 uint32_t rgbPack(uint32_t r, uint32_t g, uint32_t b);
+
33 void rgbUnpack(uint32_t color, uint32_t *r, uint32_t *g, uint32_t *b);
+
34 
+
35 #endif // CALC_H
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2chirp_8hpp_source.html b/discovery_2libs_2_pixy_2src_2chirp_8hpp_source.html new file mode 100644 index 0000000..63750eb --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2chirp_8hpp_source.html @@ -0,0 +1,398 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/chirp.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
chirp.hpp
+
+
+
1 #ifndef CHIRP_HPP
+
2 #define CHIRP_HPP
+
3 
+
4 #include <stdint.h>
+
5 #include <stdlib.h>
+
6 #include <stdarg.h>
+
7 #include "link.h"
+
8 
+
9 #define ALIGN(v, n) v = v&((n)-1) ? (v&~((n)-1))+(n) : v
+
10 #define FOURCC(a, b, c, d) (((uint32_t)a<<0)|((uint32_t)b<<8)|((uint32_t)c<<16)|((uint32_t)d<<24))
+
11 
+
12 #define CRP_RES_OK 0
+
13 #define CRP_RES_ERROR -1
+
14 #define CRP_RES_ERROR_RECV_TIMEOUT LINK_RESULT_ERROR_RECV_TIMEOUT
+
15 #define CRP_RES_ERROR_SEND_TIMEOUT LINK_RESULT_ERROR_SEND_TIMEOUT
+
16 #define CRP_RES_ERROR_CRC -2
+
17 #define CRP_RES_ERROR_PARSE -3
+
18 #define CRP_RES_ERROR_MAX_NAK -4
+
19 #define CRP_RES_ERROR_MEMORY -5
+
20 #define CRP_RES_ERROR_NOT_CONNECTED -6
+
21 
+
22 #define CRP_MAX_NAK 3
+
23 #define CRP_RETRIES 3
+
24 #define CRP_HEADER_TIMEOUT 1000
+
25 #define CRP_DATA_TIMEOUT 500
+
26 #define CRP_IDLE_TIMEOUT 500
+
27 #define CRP_SEND_TIMEOUT 1000
+
28 #define CRP_MAX_ARGS 10
+
29 #define CRP_BUFSIZE 0x80
+
30 #define CRP_BUFPAD 8
+
31 #define CRP_PROCTABLE_LEN 0x40
+
32 
+
33 #define CRP_START_CODE 0xaaaa5555
+
34 
+
35 #define CRP_CALL 0x80
+
36 #define CRP_RESPONSE 0x40
+
37 #define CRP_INTRINSIC 0x20
+
38 #define CRP_DATA 0x10
+
39 #define CRP_XDATA 0x18 // data not associated with no associated procedure)
+
40 #define CRP_CALL_ENUMERATE (CRP_CALL | CRP_INTRINSIC | 0x00)
+
41 #define CRP_CALL_INIT (CRP_CALL | CRP_INTRINSIC | 0x01)
+
42 #define CRP_CALL_ENUMERATE_INFO (CRP_CALL | CRP_INTRINSIC | 0x02)
+
43 
+
44 #define CRP_ACK 0x59
+
45 #define CRP_NACK 0x95
+
46 #define CRP_MAX_HEADER_LEN 64
+
47 
+
48 #define CRP_ARRAY 0x80 // bit
+
49 #define CRP_FLT 0x10 // bit
+
50 #define CRP_NO_COPY (0x10 | 0x20)
+
51 #define CRP_HINT 0x40 // bit
+
52 #define CRP_NULLTERM_ARRAY (0x20 | CRP_ARRAY) // bits
+
53 #define CRP_INT8 0x01
+
54 #define CRP_UINT8 0x01
+
55 #define CRP_INT16 0x02
+
56 #define CRP_UINT16 0x02
+
57 #define CRP_INT32 0x04
+
58 #define CRP_UINT32 0x04
+
59 #define CRP_FLT32 (CRP_FLT | 0x04)
+
60 #define CRP_FLT64 (CRP_FLT | 0x08)
+
61 #define CRP_STRING (CRP_NULLTERM_ARRAY | CRP_INT8)
+
62 #define CRP_TYPE_HINT 0x64 // type hint identifier
+
63 #define CRP_INTS8 (CRP_INT8 | CRP_ARRAY)
+
64 #define CRP_INTS16 (CRP_INT16 | CRP_ARRAY)
+
65 #define CRP_INTS32 (CRP_INT32 | CRP_ARRAY)
+
66 #define CRP_UINTS8 CRP_INTS8
+
67 #define CRP_UINTS8_NO_COPY (CRP_INTS8 | CRP_NO_COPY)
+
68 #define CRP_UINTS16_NO_COPY (CRP_INTS16 | CRP_NO_COPY)
+
69 #define CRP_UINTS32_NO_COPY (CRP_INTS32 | CRP_NO_COPY)
+
70 #define CRP_UINTS16 CRP_INTS16
+
71 #define CRP_UINTS32 CRP_INTS32
+
72 #define CRP_FLTS32 (CRP_FLT32 | CRP_ARRAY)
+
73 #define CRP_FLTS64 (CRP_FLT64 | CRP_ARRAY)
+
74 #define CRP_HINT8 (CRP_INT8 | CRP_HINT)
+
75 #define CRP_HINT16 (CRP_INT16 | CRP_HINT)
+
76 #define CRP_HINT32 (CRP_INT32 | CRP_HINT)
+
77 #define CRP_HINTS8 (CRP_INT8 | CRP_ARRAY | CRP_HINT)
+
78 #define CRP_HINTS16 (CRP_INT16 | CRP_ARRAY | CRP_HINT)
+
79 #define CRP_HINTS32 (CRP_INT32 | CRP_ARRAY | CRP_HINT)
+
80 #define CRP_HFLTS32 (CRP_FLT32 | CRP_ARRAY | CRP_HINT)
+
81 #define CRP_HFLTS64 (CRP_FLT64 | CRP_ARRAY | CRP_HINT)
+
82 #define CRP_HSTRING (CRP_STRING | CRP_HINT)
+
83 // CRP_HTYPE is for arg lists which are uint8_t arrays
+
84 #define CRP_HTYPE(v) CRP_TYPE_HINT, (uint8_t)(v>>0&0xff), (uint8_t)(v>>8&0xff), (uint8_t)(v>>16&0xff), (uint8_t)(v>>24&0xff)
+
85 
+
86 // regular call args
+
87 #define INT8(v) CRP_INT8, v
+
88 #define UINT8(v) CRP_INT8, v
+
89 #define INT16(v) CRP_INT16, v
+
90 #define UINT16(v) CRP_INT16, v
+
91 #define INT32(v) CRP_INT32, v
+
92 #define UINT32(v) CRP_INT32, v
+
93 #define FLT32(v) CRP_FLT32, v
+
94 #define FLT64(v) CRP_FLT64, v
+
95 #define STRING(s) CRP_STRING, s
+
96 #define INTS8(len, a) CRP_INTS8, len, a
+
97 #define UINTS8(len, a) CRP_INTS8, len, a
+
98 #define UINTS8_NO_COPY(len) CRP_UINTS8_NO_COPY, len
+
99 #define UINTS16_NO_COPY(len) CRP_UINTS16_NO_COPY, len
+
100 #define UINTS32_NO_COPY(len) CRP_UINTS32_NO_COPY, len
+
101 #define INTS16(len, a) CRP_INTS16, len, a
+
102 #define UINTS16(len, a) CRP_INTS16, len, a
+
103 #define INTS32(len, a) CRP_INTS32, len, a
+
104 #define UINTS32(len, a) CRP_INTS32, len, a
+
105 #define FLTS32(len, a) CRP_FLTS32, len, a
+
106 #define FLTS64(len, a) CRP_FLTS64, len, a
+
107 
+
108 // hint call args
+
109 #define HINT8(v) CRP_HINT8, v
+
110 #define UHINT8(v) CRP_HINT8, v
+
111 #define HINT16(v) CRP_HINT16, v
+
112 #define UHINT16(v) CRP_HINT16, v
+
113 #define HINT32(v) CRP_HINT32, v
+
114 #define UHINT32(v) CRP_HINT32, v
+
115 #define HFLT32(v) CRP_HFLT32, v
+
116 #define HFLT64(v) CRP_HFLT64, v
+
117 #define HSTRING(s) CRP_HSTRING, s
+
118 #define HINTS8(len, a) CRP_HINTS8, len, a
+
119 #define UHINTS8(len, a) CRP_HINTS8, len, a
+
120 #define HINTS16(len, a) CRP_HINTS16, len, a
+
121 #define UHINTS16(len, a) CRP_HINTS16, len, a
+
122 #define HINTS32(len, a) CRP_HINTS32, len, a
+
123 #define UHINTS32(len, a) CRP_HINTS32, len, a
+
124 #define HFLTS32(len, a) CRP_HFLTS32, len, a
+
125 #define HFLTS64(len, a) CRP_HFLTS64, len, a
+
126 #define HTYPE(v) CRP_TYPE_HINT, v
+
127 
+
128 #define INT8_IN(v) int8_t & v
+
129 #define UINT8_IN(v) uint8_t & v
+
130 #define INT16_IN(v) int16_t & v
+
131 #define UINT16_IN(v) uint16_t & v
+
132 #define INT32_IN(v) int32_t & v
+
133 #define UINT32_IN(v) uint32_t & v
+
134 #define FLT32_IN(v) float & v
+
135 #define FLT64_IN(v) double & v
+
136 #define STRING_IN(s) const char * s
+
137 #define INTS8_IN(len, a) uint32_t & len, int8_t * a
+
138 #define UINTS8_IN(len, a) uint32_t & len, uint8_t * a
+
139 #define INTS16_IN(len, a) uint32_t & len, int16_t * a
+
140 #define UINTS16_IN(len, a) uint32_t & len, uint16_t * a
+
141 #define INTS32_IN(len, a) uint32_t & len, int32_t * a
+
142 #define UINTS32_IN(len, a) uint32_t & len, uint32_t * a
+
143 #define FLTS32_IN(len, a) uint32_t & len, float * a
+
144 #define FLTS64_IN(len, a) uint32_t & len, double * a
+
145 
+
146 #ifndef END
+
147 #ifdef __x86_64__
+
148 #define END (int64_t)0
+
149 #else
+
150 #define END 0
+
151 #endif
+
152 #endif
+
153 #define END_OUT_ARGS END
+
154 #define END_IN_ARGS END
+
155 
+
156 // service types
+
157 #define SYNC 0
+
158 #define ASYNC 0x01 // bit
+
159 #define RETURN_ARRAY 0x02 // bit
+
160 #define SYNC_RETURN_ARRAY (SYNC | RETURN_ARRAY)
+
161 
+
162 #define CRP_RETURN(chirp, ...) chirp->assemble(0, __VA_ARGS__, END)
+
163 #define CRP_SEND_XDATA(chirp, ...) chirp->assemble(CRP_XDATA, __VA_ARGS__, END)
+
164 #define callSync(...) call(SYNC, __VA_ARGS__, END)
+
165 #define callAsync(...) call(ASYNC, __VA_ARGS__, END)
+
166 #define callSyncArray(...) call(SYNC_RETURN_ARRAY, __VA_ARGS__, END)
+
167 
+
168 class Chirp;
+
169 
+
170 typedef int16_t ChirpProc; // negative values are invalid
+
171 
+
172 typedef uint32_t (*ProcPtr)(Chirp *);
+
173 
+
174 struct ProcModule
+
175 {
+
176  char *procName;
+
177  ProcPtr procPtr;
+
178  uint8_t argTypes[CRP_MAX_ARGS];
+
179  char *procInfo;
+
180 };
+
181 
+
182 struct ProcTableExtension
+
183 {
+
184  uint8_t argTypes[CRP_MAX_ARGS];
+
185  char *procInfo;
+
186 };
+
187 
+
188 struct ProcInfo
+
189 {
+
190  char *procName;
+
191  uint8_t *argTypes;
+
192  char *procInfo;
+
193 };
+
194 
+
195 struct ProcTableEntry
+
196 {
+
197  const char *procName;
+
198  ProcPtr procPtr;
+
199  ChirpProc chirpProc;
+
200  const ProcTableExtension *extension;
+
201 };
+
202 
+
203 class Chirp
+
204 {
+
205 public:
+
206  Chirp(bool hinterested=false, bool client=false, Link *link=NULL);
+
207  ~Chirp();
+
208 
+
209  virtual int init(bool connect);
+
210  int setLink(Link *link);
+
211  ChirpProc getProc(const char *procName, ProcPtr callback=0);
+
212  int setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL);
+
213  int getProcInfo(ChirpProc proc, ProcInfo *info);
+
214  int registerModule(const ProcModule *module);
+
215  void setSendTimeout(uint32_t timeout);
+
216  void setRecvTimeout(uint32_t timeout);
+
217 
+
218  int call(uint8_t service, ChirpProc proc, ...);
+
219  int call(uint8_t service, ChirpProc proc, va_list args);
+
220  static uint8_t getType(const void *arg);
+
221  int service(bool all=true);
+
222  int assemble(uint8_t type, ...);
+
223  bool connected();
+
224 
+
225  // utility methods
+
226  static int serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, ...);
+
227  static int deserialize(uint8_t *buf, uint32_t len, ...);
+
228  static int vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args);
+
229  static int vdeserialize(uint8_t *buf, uint32_t len, va_list *args);
+
230  static int deserializeParse(uint8_t *buf, uint32_t len, void *args[]);
+
231  static int loadArgs(va_list *args, void *recvArgs[]);
+
232  static int getArgList(uint8_t *buf, uint32_t len, uint8_t *argList);
+
233  int useBuffer(uint8_t *buf, uint32_t len);
+
234 
+
235  static uint16_t calcCrc(uint8_t *buf, uint32_t len);
+
236 
+
237 protected:
+
238  int remoteInit(bool connect);
+
239  int recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false); // null pointer terminates
+
240  virtual int handleChirp(uint8_t type, ChirpProc proc, const void *args[]); // null pointer terminates
+
241  virtual void handleXdata(const void *data[]) {(void)data;}
+
242  virtual int sendChirp(uint8_t type, ChirpProc proc);
+
243 
+
244  uint8_t *m_buf;
+
245  uint8_t *m_bufSave;
+
246  uint32_t m_len;
+
247  uint32_t m_offset;
+
248  uint32_t m_bufSize;
+
249  bool m_errorCorrected;
+
250  bool m_sharedMem;
+
251  bool m_hinformer;
+
252  bool m_hinterested;
+
253  bool m_client;
+
254  uint32_t m_headerLen;
+
255  uint16_t m_headerTimeout;
+
256  uint16_t m_dataTimeout;
+
257  uint16_t m_idleTimeout;
+
258  uint16_t m_sendTimeout;
+
259 
+
260 private:
+
261  int sendHeader(uint8_t type, ChirpProc proc);
+
262  int sendFull(uint8_t type, ChirpProc proc);
+
263  int sendData();
+
264  int sendAck(bool ack); // false=nack
+
265  int sendChirpRetry(uint8_t type, ChirpProc proc);
+
266  int recvHeader(uint8_t *type, ChirpProc *proc, bool wait);
+
267  int recvFull(uint8_t *type, ChirpProc *proc, bool wait);
+
268  int recvData();
+
269  int recvAck(bool *ack, uint16_t timeout); // false=nack
+
270  int32_t handleEnumerate(char *procName, ChirpProc *callback);
+
271  int32_t handleInit(uint16_t *blkSize, uint8_t *hintSource);
+
272  int32_t handleEnumerateInfo(ChirpProc *proc);
+
273  int vassemble(va_list *args);
+
274  void restoreBuffer();
+
275 
+
276  ChirpProc updateTable(const char *procName, ProcPtr procPtr);
+
277  ChirpProc lookupTable(const char *procName);
+
278  int realloc(uint32_t min=0);
+
279  int reallocTable();
+
280 
+
281  Link *m_link;
+
282  ProcTableEntry *m_procTable;
+
283  uint16_t m_procTableSize;
+
284  uint16_t m_blkSize;
+
285  uint8_t m_maxNak;
+
286  uint8_t m_retries;
+
287  bool m_call;
+
288  bool m_connected;
+
289 };
+
290 
+
291 #endif // CHIRP_H
+
ProcTableExtension
Definition: chirp.hpp:182
+
ProcTableEntry
Definition: chirp.hpp:195
+
Chirp
Definition: chirp.hpp:203
+
ProcModule
Definition: chirp.hpp:174
+
ProcInfo
Definition: chirp.hpp:188
+ +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html b/discovery_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html new file mode 100644 index 0000000..cb0f811 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html @@ -0,0 +1,142 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/chirpreceiver.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
chirpreceiver.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __CHIRPRECEIVER_HPP__
+
17 #define __CHIRPRECEIVER_HPP__
+
18 
+
19 #include "chirp.hpp"
+
20 #include "usblink.h"
+
21 #include "interpreter.hpp"
+
22 
+
23 class ChirpReceiver : public Chirp
+
24 {
+
25  public:
+
26 
+
27  ChirpReceiver(USBLink * link, Interpreter * interpreter);
+
28  virtual ~ChirpReceiver();
+
29 
+
30  private:
+
31 
+
32  Interpreter * interpreter_;
+
33 
+
40  void handleXdata(const void * data[]);
+
41 };
+
42 
+
43 #endif
+
Chirp
Definition: chirp.hpp:203
+
ChirpReceiver
Definition: chirpreceiver.hpp:23
+ +
Interpreter
Definition: interpreter.hpp:19
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2colorlut_8h_source.html b/discovery_2libs_2_pixy_2src_2colorlut_8h_source.html new file mode 100644 index 0000000..12c6aef --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2colorlut_8h_source.html @@ -0,0 +1,240 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/colorlut.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
colorlut.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef COLORLUT_H
+
16 #define COLORLUT_H
+
17 
+
18 #include <inttypes.h>
+
19 #include "simplevector.h"
+
20 #include "pixytypes.h"
+
21 
+
22 #define CL_NUM_SIGNATURES 7
+
23 #define CL_LUT_COMPONENT_SCALE 6
+
24 #define CL_LUT_SIZE (1<<(CL_LUT_COMPONENT_SCALE*2))
+
25 #define CL_LUT_ENTRY_SCALE 15
+
26 #define CL_GROW_INC 4
+
27 #define CL_MIN_Y_F 0.05 // for when generating signatures, etc
+
28 #define CL_MIN_Y (int32_t)(3*((1<<8)-1)*CL_MIN_Y_F)
+
29 #define CL_MIN_RATIO 0.25f
+
30 #define CL_DEFAULT_MINY 0.1f
+
31 #define CL_DEFAULT_SIG_RANGE 2.5f
+
32 #define CL_MAX_DIST 2000
+
33 #define CL_DEFAULT_TOL 0.9f
+
34 #define CL_DEFAULT_CCGAIN 1.5f
+
35 #define CL_MODEL_TYPE_COLORCODE 1
+
36 
+
37 
+
38 struct ColorSignature
+
39 {
+
40  ColorSignature()
+
41  {
+
42  m_uMin = m_uMax = m_uMean = m_vMin = m_vMax = m_vMean = m_type = 0;
+
43  }
+
44 
+
45  int32_t m_uMin;
+
46  int32_t m_uMax;
+
47  int32_t m_uMean;
+
48  int32_t m_vMin;
+
49  int32_t m_vMax;
+
50  int32_t m_vMean;
+
51  uint32_t m_rgb;
+
52  uint32_t m_type;
+
53 };
+
54 
+
55 struct RuntimeSignature
+
56 {
+
57  int32_t m_uMin;
+
58  int32_t m_uMax;
+
59  int32_t m_vMin;
+
60  int32_t m_vMax;
+
61  uint32_t m_rgbSat;
+
62 };
+
63 
+
64 typedef SimpleVector<Point16> Points;
+
65 
+
66 class IterPixel
+
67 {
+
68 public:
+
69  IterPixel(const Frame8 &frame, const RectA &region);
+
70  IterPixel(const Frame8 &frame, const Points *points);
+
71  bool next(UVPixel *uv, RGBPixel *rgb=NULL);
+
72  bool reset(bool cleari=true);
+
73  uint32_t averageRgb(uint32_t *pixels=NULL);
+
74 
+
75 private:
+
76  bool nextHelper(UVPixel *uv, RGBPixel *rgb);
+
77 
+
78  Frame8 m_frame;
+
79  RectA m_region;
+
80  uint32_t m_x, m_y;
+
81  uint8_t *m_pixels;
+
82  const Points *m_points;
+
83  int m_i;
+
84 };
+
85 
+
86 class ColorLUT
+
87 {
+
88 public:
+
89  ColorLUT(uint8_t *lut);
+
90  ~ColorLUT();
+
91 
+
92  int generateSignature(const Frame8 &frame, const RectA &region, uint8_t signum);
+
93  int generateSignature(const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum);
+
94  ColorSignature *getSignature(uint8_t signum);
+
95  int setSignature(uint8_t signum, const ColorSignature &sig);
+
96 
+
97  int generateLUT();
+
98  void clearLUT(uint8_t signum=0);
+
99  void updateSignature(uint8_t signum);
+
100  void growRegion(const Frame8 &frame, const Point16 &seed, Points *points);
+
101 
+
102  void setSigRange(uint8_t signum, float range);
+
103  void setMinBrightness(float miny);
+
104  void setGrowDist(uint32_t dist);
+
105  void setCCGain(float gain);
+
106  uint32_t getType(uint8_t signum);
+
107 
+
108  // these should be in little access methods, but they're here to speed things up a tad
+
109  ColorSignature m_signatures[CL_NUM_SIGNATURES];
+
110  RuntimeSignature m_runtimeSigs[CL_NUM_SIGNATURES];
+
111  uint32_t m_miny;
+
112 
+
113 private:
+
114  bool growRegion(RectA *region, const Frame8 &frame, uint8_t dir);
+
115  float testRegion(const RectA &region, const Frame8 &frame, UVPixel *mean, Points *points);
+
116 
+
117  void calcRatios(IterPixel *ip, ColorSignature *sig, float ratios[]);
+
118  void iterate(IterPixel *ip, ColorSignature *sig);
+
119  void getMean(const RectA &region ,const Frame8 &frame, UVPixel *mean);
+
120 
+
121  uint8_t *m_lut;
+
122  uint32_t m_maxDist;
+
123  float m_ratio;
+
124  float m_minRatio;
+
125  float m_ccGain;
+
126  float m_sigRanges[CL_NUM_SIGNATURES];
+
127 };
+
128 
+
129 #endif // COLORLUT_H
+
RectA
Definition: pixytypes.h:91
+
Point16
Definition: pixytypes.h:37
+
RGBPixel
Definition: pixytypes.h:233
+
RuntimeSignature
Definition: colorlut.h:55
+
UVPixel
Definition: pixytypes.h:216
+
Frame8
Definition: pixytypes.h:71
+
ColorLUT
Definition: colorlut.h:86
+
ColorSignature
Definition: colorlut.h:38
+
SimpleVector
Definition: simplevector.h:23
+
IterPixel
Definition: colorlut.h:66
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2debug_8h_source.html b/discovery_2libs_2_pixy_2src_2debug_8h_source.html new file mode 100644 index 0000000..35dfb55 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2debug_8h_source.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/debug.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
debug.h
+
+
+
1 #ifndef DEBUG_H
+
2 #define DEBUG_H
+
3 
+
4 #define DBG(...)
+
5 
+
6 #endif // DEBUG_H
+
7 
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2debuglog_8h_source.html b/discovery_2libs_2_pixy_2src_2debuglog_8h_source.html new file mode 100644 index 0000000..a324d26 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2debuglog_8h_source.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/debuglog.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
debuglog.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef __DEBUG_H__
+
16 #define __DEBUG_H__
+
17 
+
18 #include <stdarg.h>
+
19 #include <stdio.h>
+
20 
+
21 static void log(const char *format, ...)
+
22 {
+
23 #ifdef DEBUG
+
24  va_list elements;
+
25 
+
26  // Send debug message to stdout //
+
27  va_start(elements, format);
+
28  vfprintf(stderr,format, elements);
+
29  fflush(stderr);
+
30  va_end(elements);
+
31  #else
+
32  (void)format;
+
33 #endif
+
34 }
+
35 
+
36 #endif
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2interpreter_8hpp_source.html b/discovery_2libs_2_pixy_2src_2interpreter_8hpp_source.html new file mode 100644 index 0000000..4d0e58b --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2interpreter_8hpp_source.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/interpreter.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
interpreter.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __INTERPRETER_HPP__
+
17 #define __INTERPRETER_HPP__
+
18 
+
19 class Interpreter
+
20 {
+
21  public:
+
22 
+
23  virtual void interpret_data(const void *data []) = 0;
+
24 };
+
25 
+
26 #endif
+
Interpreter
Definition: interpreter.hpp:19
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2link_8h_source.html b/discovery_2libs_2_pixy_2src_2link_8h_source.html new file mode 100644 index 0000000..877051c --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2link_8h_source.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/link.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
link.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef LINK_H
+
16 #define LINK_H
+
17 
+
18 #include <stdint.h>
+
19 
+
20 // flags
+
21 #define LINK_FLAG_SHARED_MEM 0x01
+
22 #define LINK_FLAG_ERROR_CORRECTED 0x02
+
23 
+
24 // result codes
+
25 #define LINK_RESULT_OK 0
+
26 #define LINK_RESULT_ERROR -100
+
27 #define LINK_RESULT_ERROR_RECV_TIMEOUT -101
+
28 #define LINK_RESULT_ERROR_SEND_TIMEOUT -102
+
29 
+
30 // link flag index
+
31 #define LINK_FLAG_INDEX_FLAGS 0x00
+
32 #define LINK_FLAG_INDEX_SHARED_MEMORY_LOCATION 0x01
+
33 #define LINK_FLAG_INDEX_SHARED_MEMORY_SIZE 0x02
+
34 
+
35 
+
36 class Link
+
37 {
+
38 public:
+
39  Link()
+
40  {
+
41  m_flags = 0;
+
42  m_blockSize = 0;
+
43  }
+
44  ~Link()
+
45  {
+
46  }
+
47 
+
48  // the timeoutMs is a timeout value in milliseconds. The timeout timer should expire
+
49  // when the data channel has been continuously idle for the specified amount of time
+
50  // not the summation of the idle times.
+
51  virtual int send(const uint8_t *data, uint32_t len, uint16_t timeoutMs) = 0;
+
52  virtual int receive(uint8_t *data, uint32_t len, uint16_t timeoutMs) = 0;
+
53  virtual void setTimer() = 0;
+
54  virtual uint32_t getTimer() = 0; // returns elapsed time in milliseconds since setTimer() was called
+
55  virtual uint32_t getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS)
+
56  {
+
57  if (index==LINK_FLAG_INDEX_FLAGS)
+
58  return m_flags;
+
59  else
+
60  return 0;
+
61  }
+
62  virtual uint32_t blockSize()
+
63  {
+
64  return m_blockSize;
+
65  }
+
66  virtual int getBuffer(uint8_t **, uint32_t *)
+
67  {
+
68  return LINK_RESULT_ERROR;
+
69  }
+
70 
+
71 protected:
+
72  uint32_t m_flags;
+
73  uint32_t m_blockSize;
+
74 };
+
75 
+
76 #endif // LINK_H
+ +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html b/discovery_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html new file mode 100644 index 0000000..4c3dc43 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html @@ -0,0 +1,185 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/pixyinterpreter.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixyinterpreter.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __PIXYINTERPRETER_HPP__
+
17 #define __PIXYINTERPRETER_HPP__
+
18 
+
19 #include <vector>
+
20 #include "pixytypes.h"
+
21 #include "pixy.h"
+
22 #include "pixydefs.h"
+
23 #include "usblink.h"
+
24 #include "interpreter.hpp"
+
25 #include "chirpreceiver.hpp"
+
26 
+
27 #define PIXY_BLOCK_CAPACITY 250
+
28 
+
29 class PixyInterpreter : public Interpreter
+
30 {
+
31  public:
+
32 
+
33  PixyInterpreter();
+
34  ~PixyInterpreter();
+
35 
+
48  int init();
+
49 
+
54  void close();
+
55 
+
62  int blocks_are_new();
+
63 
+
79  int get_blocks(int max_blocks, Block * blocks);
+
80 
+
87  int send_command(const char * name, va_list arguments);
+
88 
+
94  int send_command(const char * name, ...);
+
95 
+
96 
+
97 
+
98  int service();
+
99 
+
100  private:
+
101 
+
102  ChirpReceiver * receiver_;
+
103  USBLink link_;
+
104  std::vector<Block> blocks_;
+
105  bool blocks_are_new_;
+
106  bool init_;
+
107 
+
108 
+
114  void interpret_data(const void * chrip_data[]);
+
115 
+
121  void interpret_CCB1(const void * data[]);
+
122 
+
128  void interpret_CCB2(const void * data[]);
+
129 
+
137  void add_normal_blocks(const BlobA * blocks, uint32_t count);
+
138 
+
146  void add_color_code_blocks(const BlobB * blocks, uint32_t count);
+
147 };
+
148 
+
149 #endif
+
PixyInterpreter::send_command
int send_command(const char *name, va_list arguments)
Sends a command to Pixy.
Definition: pixyinterpreter.cpp:100
+
PixyInterpreter::get_blocks
int get_blocks(int max_blocks, Block *blocks)
Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. ...
Definition: pixyinterpreter.cpp:64
+
PixyInterpreter::close
void close()
Terminates the USB connection to Pixy and the 'iterpreter' thread.
Definition: pixyinterpreter.cpp:54
+
BlobA
Definition: pixytypes.h:133
+
ChirpReceiver
Definition: chirpreceiver.hpp:23
+ +
BlobB
Definition: pixytypes.h:156
+
PixyInterpreter::init
int init()
Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method.
Definition: pixyinterpreter.cpp:31
+
PixyInterpreter
Definition: pixyinterpreter.hpp:29
+
Interpreter
Definition: interpreter.hpp:19
+
PixyInterpreter::blocks_are_new
int blocks_are_new()
Get status of the block data received from Pixy.
Definition: pixyinterpreter.cpp:289
+
Block
Definition: pixy.h:47
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2pixytypes_8h_source.html b/discovery_2libs_2_pixy_2src_2pixytypes_8h_source.html new file mode 100644 index 0000000..4fbf22a --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2pixytypes_8h_source.html @@ -0,0 +1,384 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/pixytypes.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixytypes.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef PIXYTYPES_H
+
17 #define PIXYTYPES_H
+
18 
+
19 #include <stdint.h>
+
20 
+
21 #define RENDER_FLAG_FLUSH 0x01 // add to stack, render immediately
+
22 #define RENDER_FLAG_BLEND 0x02 // blend with a previous images in image stack
+
23 
+
24 #define PRM_FLAG_INTERNAL 0x00000001
+
25 #define PRM_FLAG_ADVANCED 0x00000002
+
26 #define PRM_FLAG_HEX_FORMAT 0x00000010
+
27 #define PRM_FLAG_SIGNED 0x00000080
+
28 
+
29 // render-specific flags
+
30 #define PRM_FLAG_SLIDER 0x00000100
+
31 #define PRM_FLAG_CHECKBOX 0x00000200
+
32 #define PRM_FLAG_PATH 0x00000400
+
33 
+
34 // events
+
35 #define EVT_PARAM_CHANGE 1
+
36 
+
37 struct Point16
+
38 {
+
39  Point16()
+
40  {
+
41  m_x = m_y = 0;
+
42  }
+
43 
+
44  Point16(int16_t x, int16_t y)
+
45  {
+
46  m_x = x;
+
47  m_y = y;
+
48  }
+
49 
+
50  int16_t m_x;
+
51  int16_t m_y;
+
52 };
+
53 
+
54 struct Point32
+
55 {
+
56  Point32()
+
57  {
+
58  m_x = m_y = 0;
+
59  }
+
60 
+
61  Point32(int32_t x, int32_t y)
+
62  {
+
63  m_x = x;
+
64  m_y = y;
+
65  }
+
66 
+
67  int32_t m_x;
+
68  int32_t m_y;
+
69 };
+
70 
+
71 struct Frame8
+
72 {
+
73  Frame8()
+
74  {
+
75  m_pixels = (uint8_t *)NULL;
+
76  m_width = m_height = 0;
+
77  }
+
78 
+
79  Frame8(uint8_t *pixels, uint16_t width, uint16_t height)
+
80  {
+
81  m_pixels = pixels;
+
82  m_width = width;
+
83  m_height = height;
+
84  }
+
85 
+
86  uint8_t *m_pixels;
+
87  int16_t m_width;
+
88  int16_t m_height;
+
89 };
+
90 
+
91 struct RectA
+
92 {
+
93  RectA()
+
94  {
+
95  m_xOffset = m_yOffset = m_width = m_height = 0;
+
96  }
+
97 
+
98  RectA(uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height)
+
99  {
+
100  m_xOffset = xOffset;
+
101  m_yOffset = yOffset;
+
102  m_width = width;
+
103  m_height = height;
+
104  }
+
105 
+
106  uint16_t m_xOffset;
+
107  uint16_t m_yOffset;
+
108  uint16_t m_width;
+
109  uint16_t m_height;
+
110 };
+
111 
+
112 struct RectB
+
113 {
+
114  RectB()
+
115  {
+
116  m_left = m_right = m_top = m_bottom = 0;
+
117  }
+
118 
+
119  RectB(uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
+
120  {
+
121  m_left = left;
+
122  m_right = right;
+
123  m_top = top;
+
124  m_bottom = bottom;
+
125  }
+
126 
+
127  uint16_t m_left;
+
128  uint16_t m_right;
+
129  uint16_t m_top;
+
130  uint16_t m_bottom;
+
131 };
+
132 
+
133 struct BlobA
+
134 {
+
135  BlobA()
+
136  {
+
137  m_model = m_left = m_right = m_top = m_bottom = 0;
+
138  }
+
139 
+
140  BlobA(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
+
141  {
+
142  m_model = model;
+
143  m_left = left;
+
144  m_right = right;
+
145  m_top = top;
+
146  m_bottom = bottom;
+
147  }
+
148 
+
149  uint16_t m_model;
+
150  uint16_t m_left;
+
151  uint16_t m_right;
+
152  uint16_t m_top;
+
153  uint16_t m_bottom;
+
154 };
+
155 
+
156 struct BlobB
+
157 {
+
158  BlobB()
+
159  {
+
160  m_model = m_left = m_right = m_top = m_bottom = m_angle = 0;
+
161  }
+
162 
+
163  BlobB(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle)
+
164  {
+
165  m_model = model;
+
166  m_left = left;
+
167  m_right = right;
+
168  m_top = top;
+
169  m_bottom = bottom;
+
170  m_angle = angle;
+
171  }
+
172 
+
173  uint16_t m_model;
+
174  uint16_t m_left;
+
175  uint16_t m_right;
+
176  uint16_t m_top;
+
177  uint16_t m_bottom;
+
178  int16_t m_angle;
+
179 };
+
180 
+
181 
+
182 struct HuePixel
+
183 {
+
184  HuePixel()
+
185  {
+
186  m_u = m_v = 0;
+
187  }
+
188 
+
189  HuePixel(int8_t u, int8_t v)
+
190  {
+
191  m_u = u;
+
192  m_v = v;
+
193  }
+
194 
+
195  int8_t m_u;
+
196  int8_t m_v;
+
197 };
+
198 
+
199 struct Fpoint
+
200 {
+
201  Fpoint()
+
202  {
+
203  m_x = m_y = 0.0;
+
204  }
+
205 
+
206  Fpoint(float x, float y)
+
207  {
+
208  m_x = x;
+
209  m_y = y;
+
210  }
+
211 
+
212  float m_x;
+
213  float m_y;
+
214 };
+
215 
+
216 struct UVPixel
+
217 {
+
218  UVPixel()
+
219  {
+
220  m_u = m_v = 0;
+
221  }
+
222 
+
223  UVPixel(int32_t u, int32_t v)
+
224  {
+
225  m_u = u;
+
226  m_v = v;
+
227  }
+
228 
+
229  int32_t m_u;
+
230  int32_t m_v;
+
231 };
+
232 
+
233 struct RGBPixel
+
234 {
+
235  RGBPixel()
+
236  {
+
237  m_r = m_g = m_b = 0;
+
238  }
+
239 
+
240  RGBPixel(uint8_t r, uint8_t g, uint8_t b)
+
241  {
+
242  m_r = r;
+
243  m_g = g;
+
244  m_b = b;
+
245  }
+
246 
+
247  uint8_t m_r;
+
248  uint8_t m_g;
+
249  uint8_t m_b;
+
250 };
+
251 
+
252 
+
253 struct Line
+
254 {
+
255  Line()
+
256  {
+
257  m_slope = m_yi = 0.0;
+
258  }
+
259  Line(float slope, float yi)
+
260  {
+
261  m_slope = slope;
+
262  m_yi = yi;
+
263  }
+
264 
+
265  float m_slope;
+
266  float m_yi;
+
267 };
+
268 
+
269 typedef long long longlong;
+
270 
+
271 #endif // PIXYTYPES_H
+
RectA
Definition: pixytypes.h:91
+
BlobA
Definition: pixytypes.h:133
+
Point16
Definition: pixytypes.h:37
+
Fpoint
Definition: pixytypes.h:199
+
RGBPixel
Definition: pixytypes.h:233
+
BlobB
Definition: pixytypes.h:156
+
Point32
Definition: pixytypes.h:54
+
UVPixel
Definition: pixytypes.h:216
+
HuePixel
Definition: pixytypes.h:182
+
Line
Definition: pixytypes.h:253
+
Frame8
Definition: pixytypes.h:71
+
RectB
Definition: pixytypes.h:112
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2qqueue_8h_source.html b/discovery_2libs_2_pixy_2src_2qqueue_8h_source.html new file mode 100644 index 0000000..11cdc82 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2qqueue_8h_source.html @@ -0,0 +1,208 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/qqueue.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
qqueue.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef _QQUEUE_H
+
16 #define _QQUEUE_H
+
17 #include <inttypes.h>
+
18 
+
19 #define QQ_LOC SRAM4_LOC
+
20 #ifdef PIXY
+
21 #define QQ_SIZE 0x3c00
+
22 #else
+
23 #define QQ_SIZE 0x30000
+
24 #endif
+
25 #define QQ_MEM_SIZE ((QQ_SIZE-sizeof(struct QqueueFields)+sizeof(Qval))/sizeof(Qval))
+
26 
+
27 #ifdef __cplusplus
+
28 struct Qval
+
29 #else
+
30 typedef struct
+
31 #endif
+
32 {
+
33 #ifdef __cplusplus
+
34  Qval()
+
35  {
+
36  m_u = m_v = m_y = m_col = 0;
+
37  }
+
38 
+
39  Qval(int16_t u, int16_t v, uint16_t y, uint16_t col)
+
40  {
+
41  m_u = u;
+
42  m_v = v;
+
43  m_y = y;
+
44  m_col = col;
+
45  }
+
46 #endif
+
47 
+
48  uint16_t m_col;
+
49  int16_t m_v;
+
50  int16_t m_u;
+
51  uint16_t m_y;
+
52 
+
53 #ifdef __cplusplus
+
54 };
+
55 #else
+
56 } Qval;
+
57 #endif
+
58 
+
59 
+
60 struct QqueueFields
+
61 {
+
62  uint16_t readIndex;
+
63  uint16_t writeIndex;
+
64 
+
65  uint16_t produced;
+
66  uint16_t consumed;
+
67 
+
68  // (array size below doesn't matter-- we're just going to cast a pointer to this struct)
+
69  Qval data[1]; // data
+
70 };
+
71 
+
72 #ifdef __cplusplus // M4 is C++ and the "consumer" of data
+
73 
+
74 class Qqueue
+
75 {
+
76 public:
+
77  Qqueue();
+
78  ~Qqueue();
+
79 
+
80  uint32_t dequeue(Qval *val);
+
81  uint32_t queued()
+
82  {
+
83  return m_fields->produced - m_fields->consumed;
+
84  }
+
85 #ifndef PIXY
+
86  int enqueue(Qval *val);
+
87 #endif
+
88 
+
89  uint32_t readAll(Qval *mem, uint32_t size);
+
90  void flush();
+
91 
+
92 private:
+
93  QqueueFields *m_fields;
+
94 };
+
95 
+
96 #else // M0 is C and the "producer" of data (Qvals)
+
97 
+
98 uint32_t qq_enqueue(const Qval *val);
+
99 uint16_t qq_free(void);
+
100 
+
101 extern struct QqueueFields *g_qqueue;
+
102 
+
103 #endif
+
104 
+
105 #endif
+
Qval
Definition: qqueue.h:30
+
QqueueFields
Definition: qqueue.h:60
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2simplevector_8h_source.html b/discovery_2libs_2_pixy_2src_2simplevector_8h_source.html new file mode 100644 index 0000000..2300200 --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2simplevector_8h_source.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/simplevector.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
simplevector.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef SIMPLEVECTOR_H
+
17 #define SIMPLEVECTOR_H
+
18 
+
19 #include <new>
+
20 
+
21 #define SPARE_CAPACITY 16
+
22 
+
23 template <typename Object> class SimpleVector
+
24 {
+
25 public:
+
26 
+
27  SimpleVector(int initSize = 0)
+
28  : m_size(0), m_capacity(initSize + SPARE_CAPACITY)
+
29  { m_objects = new Object[m_capacity]; }
+
30 
+
31  ~SimpleVector()
+
32  { delete [] m_objects; }
+
33 
+
34  int resize(int newCapacity)
+
35  {
+
36  if(newCapacity < m_size)
+
37  return 0;
+
38 
+
39  Object *oldArray = m_objects;
+
40 
+
41  m_objects = new (std::nothrow) Object[newCapacity];
+
42  if (m_objects==NULL)
+
43  {
+
44  m_objects = oldArray;
+
45  return -1;
+
46  }
+
47  for(int k = 0; k<m_size; k++)
+
48  m_objects[k] = oldArray[k];
+
49 
+
50  m_capacity = newCapacity;
+
51 
+
52  delete [] oldArray;
+
53  return 0;
+
54  }
+
55 
+
56  Object & operator[](int index)
+
57  { return m_objects[index]; }
+
58 
+
59  const Object& operator[](int index) const
+
60  { return m_objects[index]; }
+
61 
+
62  bool empty() const
+
63  { return size()==0; }
+
64 
+
65  int size() const
+
66  { return m_size; }
+
67 
+
68  int capacity() const
+
69  { return m_capacity; }
+
70 
+
71  const Object *data()
+
72  { return m_objects; }
+
73 
+
74  int push_back(const Object& x)
+
75  {
+
76  if(m_size == m_capacity)
+
77  if (resize(m_capacity + SPARE_CAPACITY)<0)
+
78  return -1;
+
79  m_objects[m_size++] = x;
+
80  return 0;
+
81  }
+
82 
+
83  void pop_back()
+
84  { m_size--; }
+
85 
+
86  void clear()
+
87  { m_size = 0; }
+
88 
+
89 private:
+
90  int m_size;
+
91  int m_capacity;
+
92  Object *m_objects;
+
93 };
+
94 
+
95 #endif // SIMPLEVECTOR_H
+
SimpleVector
Definition: simplevector.h:23
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/discovery_2libs_2_pixy_2src_2usblink_8h_source.html b/discovery_2libs_2_pixy_2src_2usblink_8h_source.html new file mode 100644 index 0000000..0d3defd --- /dev/null +++ b/discovery_2libs_2_pixy_2src_2usblink_8h_source.html @@ -0,0 +1,123 @@ + + + + + + +discoverpixy: discovery/libs/Pixy/src/usblink.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usblink.h
+
+
+
1 #ifndef __USBLINK_H__
+
2 #define __USBLINK_H__
+
3 
+
4 #include "link.h"
+
5 
+
6 class USBLink : public Link
+
7 {
+
8 public:
+
9  USBLink();
+
10  ~USBLink();
+
11 
+
12  int open();
+
13  virtual int send(const uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
14  virtual int receive(uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
15  virtual void setTimer();
+
16  virtual uint32_t getTimer();
+
17 };
+
18 
+
19 #endif
+
20 
+ + +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/doc.png b/doc.png new file mode 100644 index 0000000..17edabf Binary files /dev/null and b/doc.png differ diff --git a/doxygen.css b/doxygen.css new file mode 100644 index 0000000..a000833 --- /dev/null +++ b/doxygen.css @@ -0,0 +1,1449 @@ +/* The standard CSS for doxygen 1.8.9.1 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #879ECB; + color: #354C7B; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +p.starttd { + margin-top: 0px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3D578C; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4665A2; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9CAFD4; + color: #ffffff; + border: 1px double #869DCA; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px 6px; + margin: 4px 8px 4px 2px; + background-color: #FBFCFD; + border: 1px solid #C4CFE5; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah, span.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.classindex ul { + list-style: none; + padding-left: 0; +} + +div.classindex span.ai { + display: inline-block; +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view inside a (index) page */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #9CAFD4; + border-bottom: 1px solid #9CAFD4; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +.arrow { + color: #9CAFD4; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; + cursor: pointer; + font-size: 80%; + display: inline-block; + width: 16px; + height: 22px; +} + +.icon { + font-family: Arial, Helvetica; + font-weight: bold; + font-size: 12px; + height: 14px; + width: 16px; + display: inline-block; + background-color: #728DC1; + color: white; + text-align: center; + border-radius: 4px; + margin-left: 2px; + margin-right: 2px; +} + +.icona { + width: 24px; + height: 22px; + display: inline-block; +} + +.iconfopen { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderopen.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.iconfclosed { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderclosed.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.icondoc { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('doc.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +table.directory { + font: 400 14px Roboto,sans-serif; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #90A5CE; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#334975; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D8DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.s:after, #powerTip.s:before, +#powerTip.w:after, #powerTip.w:before, +#powerTip.e:after, #powerTip.e:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.nw:after, #powerTip.nw:before, +#powerTip.sw:after, #powerTip.sw:before { + border: solid transparent; + content: " "; + height: 0; + width: 0; + position: absolute; +} + +#powerTip.n:after, #powerTip.s:after, +#powerTip.w:after, #powerTip.e:after, +#powerTip.nw:after, #powerTip.ne:after, +#powerTip.sw:after, #powerTip.se:after { + border-color: rgba(255, 255, 255, 0); +} + +#powerTip.n:before, #powerTip.s:before, +#powerTip.w:before, #powerTip.e:before, +#powerTip.nw:before, #powerTip.ne:before, +#powerTip.sw:before, #powerTip.se:before { + border-color: rgba(128, 128, 128, 0); +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.nw:after, #powerTip.nw:before { + top: 100%; +} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/doxygen.png b/doxygen.png new file mode 100644 index 0000000..3ff17d8 Binary files /dev/null and b/doxygen.png differ diff --git a/dynsections.js b/dynsections.js new file mode 100644 index 0000000..85e1836 --- /dev/null +++ b/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} + +function toggleLevel(level) +{ + $('table.directory tr').each(function() { + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + + +discoverpixy: emulator/libs/Pixy/src/blob.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
blob.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef _BLOB_H
+
16 #define _BLOB_H
+
17 
+
18 // TODO
+
19 //
+
20 // *** Priority 1
+
21 //
+
22 // *** Priority 2:
+
23 //
+
24 // *** Priority 3:
+
25 //
+
26 // *** Priority 4:
+
27 //
+
28 // Think about heap management of CBlobs
+
29 // Think about heap management of SLinkedSegments
+
30 //
+
31 // *** Priority 5 (maybe never do):
+
32 //
+
33 // Try small and large SMoments structure (small for segment)
+
34 // Try more efficient SSegment structure for lastBottom, nextBottom
+
35 //
+
36 // *** DONE
+
37 //
+
38 // DONE Compute elongation, major/minor axes (SMoments::GetStats)
+
39 // DONE Make XRC LUT
+
40 // DONE Use XRC LUT
+
41 // DONE Optimize blob assy
+
42 // DONE Start compiling
+
43 // DONE Conditionally record segments
+
44 // DONE Ask rich about FP, trig
+
45 // Take segmented image in (DONE in imageserver.cc, ARW 10/7/04)
+
46 // Produce colored segmented image out (DONE in imageserver.cc, ARW 10/7/04)
+
47 // Draw blob stats in image out (DONE for centroid, bounding box
+
48 // in imageserver.cc, ARW 10/7/04)
+
49 // Delete segments when deleting blob (DONE, ARW 10/7/04)
+
50 // Check to see if we attach to multiple blobs (DONE, ARW 10/7/04)
+
51 // Sort blobs according to area (DONE, ARW 10/7/04)
+
52 // DONE Sort blobs according to area
+
53 // DONE Clean up code
+
54 
+
55 #include <stdlib.h>
+
56 #include <assert.h>
+
57 //#include <memory.h>
+
58 #include <math.h>
+
59 
+
60 //#define INCLUDE_STATS
+
61 
+
62 // Uncomment this for verbose output for testing
+
63 //#include <iostream.h>
+
64 
+
65 struct SMomentStats {
+
66  int area;
+
67  // X is 0 on the left side of the image and increases to the right
+
68  // Y is 0 on the top of the image and increases to the bottom
+
69  float centroidX, centroidY;
+
70  // angle is 0 to PI, in radians.
+
71  // 0 points to the right (positive X)
+
72  // PI/2 points downward (positive Y)
+
73  float angle;
+
74  float majorDiameter;
+
75  float minorDiameter;
+
76 };
+
77 
+
78 // Image size is 352x278
+
79 // Full-screen blob area is 97856
+
80 // Full-screen centroid is 176,139
+
81 // sumX, sumY is then 17222656, 13601984; well within 32 bits
+
82 struct SMoments {
+
83  // Skip major/minor axis computation when this is false
+
84  static bool computeAxes;
+
85 
+
86  int area; // number of pixels
+
87  void Reset() {
+
88  area = 0;
+
89 #ifdef INCLUDE_STATS
+
90  sumX= sumY= sumXX= sumYY= sumXY= 0;
+
91 #endif
+
92  }
+
93 #ifdef INCLUDE_STATS
+
94  int sumX; // sum of pixel x coords
+
95  int sumY; // sum of pixel y coords
+
96  // XX, XY, YY used for major/minor axis calculation
+
97  long long sumXX; // sum of x^2 for each pixel
+
98  long long sumYY; // sum of y^2 for each pixel
+
99  long long sumXY; // sum of x*y for each pixel
+
100 #endif
+
101  void Add(const SMoments &moments) {
+
102  area += moments.area;
+
103 #ifdef INCLUDE_STATS
+
104  sumX += moments.sumX;
+
105  sumY += moments.sumY;
+
106  if (computeAxes) {
+
107  sumXX += moments.sumXX;
+
108  sumYY += moments.sumYY;
+
109  sumXY += moments.sumXY;
+
110  }
+
111 #endif
+
112  }
+
113 #ifdef INCLUDE_STATS
+
114  void GetStats(SMomentStats &stats) const;
+
115  bool operator==(const SMoments &rhs) const {
+
116  if (area != rhs.area) return 0;
+
117  if (sumX != rhs.sumX) return 0;
+
118  if (sumY != rhs.sumY) return 0;
+
119  if (computeAxes) {
+
120  if (sumXX != rhs.sumXX) return 0;
+
121  if (sumYY != rhs.sumYY) return 0;
+
122  if (sumXY != rhs.sumXY) return 0;
+
123  }
+
124  return 1;
+
125  }
+
126 #endif
+
127 };
+
128 
+
129 struct SSegment {
+
130  unsigned char model : 3 ; // which color channel
+
131  unsigned short row : 9 ;
+
132  unsigned short startCol : 10; // inclusive
+
133  unsigned short endCol : 10; // inclusive
+
134 
+
135  const static short invalid_row= 0x1ff;
+
136 
+
137  // Sum 0^2 + 1^2 + 2^2 + ... + n^2 is (2n^3 + 3n^2 + n) / 6
+
138  // Sum (a+1)^2 + (a+2)^2 ... b^2 is (2(b^3-a^3) + 3(b^2-a^2) + (b-a)) / 6
+
139  //
+
140  // Sum 0+1+2+3+...+n is (n^2 + n)/2
+
141  // Sum (a+1) + (a+2) ... b is (b^2-a^2 + b-a)/2
+
142 
+
143  void GetMoments(SMoments &moments) const {
+
144  int s= startCol - 1;
+
145  int e= endCol;
+
146 
+
147  moments.area = (e-s);
+
148 #ifdef INCLUDE_STATS
+
149  int e2= e*e;
+
150  int y= row;
+
151  int s2= s*s;
+
152  moments.sumX = ( (e2-s2) + (e-s) ) / 2;
+
153  moments.sumY = (e-s) * y;
+
154 
+
155  if (SMoments::computeAxes) {
+
156  int e3= e2*e;
+
157  int s3= s2*s;
+
158  moments.sumXY= moments.sumX*y;
+
159  moments.sumXX= (2*(e3-s3) + 3*(e2-s2) + (e-s)) / 6;
+
160  moments.sumYY= moments.sumY*y;
+
161  }
+
162 #endif
+
163  }
+
164 #ifdef INCLUDE_STATS
+
165  void GetMomentsTest(SMoments &moments) const;
+
166 #endif
+
167 };
+
168 
+
169 struct SLinkedSegment {
+
170  SSegment segment;
+
171  SLinkedSegment *next;
+
172  SLinkedSegment(const SSegment &segmentInit) :
+
173  segment(segmentInit), next(NULL) {}
+
174 };
+
175 
+
176 class CBlob {
+
177  // These are at the beginning for fast inclusion checking
+
178 public:
+
179  static int leakcheck;
+
180  CBlob *next; // next ptr for linked list
+
181 
+
182  // Bottom of blob, which is the surface we'll attach more segments to
+
183  // If bottom of blob contains multiple segments, this is the smallest
+
184  // segment containing the multiple segments
+
185  SSegment lastBottom;
+
186 
+
187  // Next bottom of blob, currently under construction
+
188  SSegment nextBottom;
+
189 
+
190  // Bounding box, inclusive. nextBottom.row contains the "bottom"
+
191  short left, top, right;
+
192 
+
193  void getBBox(short &leftRet, short &topRet,
+
194  short &rightRet, short &bottomRet) {
+
195  leftRet= left;
+
196  topRet= top;
+
197  rightRet= right;
+
198  bottomRet= lastBottom.row;
+
199  }
+
200 
+
201  // Segments which compose the blob
+
202  // Only recorded if CBlob::recordSegments is true
+
203  // firstSegment points to first segment in linked list
+
204  SLinkedSegment *firstSegment;
+
205  // lastSegmentPtr points to the next pointer field _inside_ the
+
206  // last element of the linked list. This is the field you would
+
207  // modify in order to append to the end of the list. Therefore
+
208  // **lastSegmentPtr should always equal to NULL.
+
209  // When the list is empty, lastSegmentPtr actually doesn't point inside
+
210  // a SLinkedSegment structure at all but instead at the firstSegment
+
211  // field above, which in turn is NULL.
+
212  SLinkedSegment **lastSegmentPtr;
+
213 
+
214  SMoments moments;
+
215 
+
216  static bool recordSegments;
+
217  // Set to true for testing code only. Very slow!
+
218  static bool testMoments;
+
219 
+
220  CBlob();
+
221  ~CBlob();
+
222 
+
223  int GetArea() const {
+
224  return(moments.area);
+
225  }
+
226 
+
227  // Clear blob data and free segments, if any
+
228  void Reset();
+
229 
+
230  void NewRow();
+
231 
+
232  void Add(const SSegment &segment);
+
233 
+
234  // This takes futileResister and assimilates it into this blob
+
235  //
+
236  // Takes advantage of the fact that we are always assembling top to
+
237  // bottom, left to right.
+
238  //
+
239  // Be sure to call like so:
+
240  // leftblob.Assimilate(rightblob);
+
241  //
+
242  // This lets us assume two things:
+
243  // 1) The assimilated blob contains no segments on the current row
+
244  // 2) The assimilated blob lastBottom surface is to the right
+
245  // of this blob's lastBottom surface
+
246  void Assimilate(CBlob &futileResister);
+
247 
+
248  // Only updates left, top, and right. bottom is updated
+
249  // by UpdateAttachmentSurface below
+
250  void UpdateBoundingBox(int newLeft, int newTop, int newRight);
+
251 };
+
252 
+
253 // Strategy for using CBlobAssembler:
+
254 //
+
255 // Make one CBlobAssembler for each color channel.
+
256 // CBlobAssembler ignores the model index, so you need to be sure to
+
257 // only pass the correct segments to each CBlobAssembler.
+
258 //
+
259 // At the beginning of a frame, call Reset() on each assembler
+
260 // As segments appear, call Add(segment)
+
261 // At the end of a frame, call EndFrame() on each assembler
+
262 // Get blobs from finishedBlobs. Blobs will remain valid until
+
263 // the next call to Reset(), at which point they will be deleted.
+
264 //
+
265 // To get statistics for a blob, do the following:
+
266 // SMomentStats stats;
+
267 // blob->moments.GetStats(stats);
+
268 // (See imageserver.cc: draw_blob() for an example)
+
269 
+
270 class CBlobAssembler {
+
271  short currentRow;
+
272 
+
273  // Active blobs, in left to right order
+
274  // (Active means we are still potentially adding segments)
+
275  CBlob *activeBlobs;
+
276 
+
277  // Current candidate for adding a segment to. This is a member
+
278  // of activeBlobs, and scans left to right as we search the active blobs.
+
279  CBlob *currentBlob;
+
280 
+
281  // Pointer to pointer to current candidate, which is actually the pointer
+
282  // to the "next" field inside the previous candidate, or a pointer to
+
283  // the activeBlobs field of this object if the current candidate is the
+
284  // first element of the activeBlobs list. Used for inserting and
+
285  // deleting blobs.
+
286  CBlob **previousBlobPtr;
+
287 
+
288 public:
+
289  // Blobs we're no longer adding to
+
290  CBlob *finishedBlobs;
+
291  short maxRowDelta;
+
292  static bool keepFinishedSorted;
+
293 
+
294 public:
+
295  CBlobAssembler();
+
296  ~CBlobAssembler();
+
297 
+
298  // Call prior to starting a frame
+
299  // Deletes any previously created blobs
+
300  void Reset();
+
301 
+
302 
+
303  // Call once for each segment in the color channel
+
304  int Add(const SSegment &segment);
+
305 
+
306  // Call at end of frame
+
307  // Moves all active blobs to finished list
+
308  void EndFrame();
+
309 
+
310  int ListLength(const CBlob *b);
+
311 
+
312  // Split a list of blobs into two halves
+
313  void SplitList(CBlob *all, CBlob *&firstHalf, CBlob *&secondHalf);
+
314 
+
315  // Merge maxelts elements from old1 and old2 into newptr
+
316  void MergeLists(CBlob *&old1, CBlob *&old2, CBlob **&newptr, int maxelts);
+
317 
+
318  // Sorts finishedBlobs in order of descending area using an in-place
+
319  // merge sort (time n log n)
+
320  void SortFinished();
+
321 
+
322  // Assert that finishedBlobs is in fact sorted. For testing only.
+
323  void AssertFinishedSorted();
+
324 
+
325 protected:
+
326  // Manage currentBlob
+
327  //
+
328  // We always want to guarantee that both currentBlob
+
329  // and currentBlob->next have had NewRow() called, and have
+
330  // been validated to remain on the active list. We could just
+
331  // do this for all activeBlobs at the beginning of each row,
+
332  // but it's less work to only do it on demand as segments come in
+
333  // since it might allow us to skip blobs for a given row
+
334  // if there are no segments which might overlap.
+
335 
+
336  // BlobNewRow:
+
337  //
+
338  // Tell blob there is a new row of data, and confirm that the
+
339  // blob should still be on the active list by seeing if too many
+
340  // rows have elapsed since the last segment was added.
+
341  //
+
342  // If blob should no longer be on the active list, remove it and
+
343  // place on the finished list, and skip to the next blob.
+
344  //
+
345  // Call this either zero or one time per blob per row, never more.
+
346  //
+
347  // Pass in the pointer to the "next" field pointing to the blob, so
+
348  // we can delete the blob from the linked list if it's not valid.
+
349 
+
350  void BlobNewRow(CBlob **ptr);
+
351  void RewindCurrent();
+
352  void AdvanceCurrent();
+
353 
+
354  int m_blobCount;
+
355 };
+
356 
+
357 #endif // _BLOB_H
+
CBlobAssembler
Definition: blob.h:270
+
CBlob
Definition: blob.h:176
+
SMoments
Definition: blob.h:82
+
SMomentStats
Definition: blob.h:65
+
SSegment
Definition: blob.h:129
+
SLinkedSegment
Definition: blob.h:169
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2blobs_8h_source.html b/emulator_2libs_2_pixy_2src_2blobs_8h_source.html new file mode 100644 index 0000000..ad5b3f1 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2blobs_8h_source.html @@ -0,0 +1,217 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/blobs.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
blobs.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef BLOBS_H
+
16 #define BLOBS_H
+
17 
+
18 #include <stdint.h>
+
19 #include "blob.h"
+
20 #include "pixytypes.h"
+
21 #include "colorlut.h"
+
22 #include "qqueue.h"
+
23 
+
24 #define MAX_BLOBS 100
+
25 #define MAX_BLOBS_PER_MODEL 20
+
26 #define MAX_MERGE_DIST 5
+
27 #define MIN_AREA 20
+
28 #define MIN_COLOR_CODE_AREA 10
+
29 #define MAX_CODED_DIST 6
+
30 #define MAX_COLOR_CODE_MODELS 5
+
31 
+
32 #define BL_BEGIN_MARKER 0xaa55
+
33 #define BL_BEGIN_MARKER_CC 0xaa56
+
34 
+
35 enum ColorCodeMode
+
36 {
+
37  DISABLED = 0,
+
38  ENABLED = 1,
+
39  CC_ONLY = 2,
+
40  MIXED = 3 // experimental
+
41 };
+
42 
+
43 class Blobs
+
44 {
+
45 public:
+
46  Blobs(Qqueue *qq, uint8_t *lut);
+
47  ~Blobs();
+
48  int blobify();
+
49  uint16_t getBlock(uint8_t *buf, uint32_t buflen);
+
50  uint16_t getCCBlock(uint8_t *buf, uint32_t buflen);
+
51  BlobA *getMaxBlob(uint16_t signature=0);
+
52  void getBlobs(BlobA **blobs, uint32_t *len, BlobB **ccBlobs, uint32_t *ccLen);
+
53  int setParams(uint16_t maxBlobs, uint16_t maxBlobsPerModel, uint32_t minArea, ColorCodeMode ccMode);
+
54  int runlengthAnalysis();
+
55 #ifndef PIXY
+
56  void getRunlengths(uint32_t **qvals, uint32_t *len);
+
57 #endif
+
58 
+
59  ColorLUT m_clut;
+
60  Qqueue *m_qq;
+
61 
+
62 private:
+
63  int handleSegment(uint8_t signature, uint16_t row, uint16_t startCol, uint16_t length);
+
64  void endFrame();
+
65  uint16_t combine(uint16_t *blobs, uint16_t numBlobs);
+
66  uint16_t combine2(uint16_t *blobs, uint16_t numBlobs);
+
67  uint16_t compress(uint16_t *blobs, uint16_t numBlobs);
+
68 
+
69  bool closeby(BlobA *blob0, BlobA *blob1);
+
70  int16_t distance(BlobA *blob0, BlobA *blob1);
+
71  void sort(BlobA *blobs[], uint16_t len, BlobA *firstBlob, bool horiz);
+
72  int16_t angle(BlobA *blob0, BlobA *blob1);
+
73  int16_t distance(BlobA *blob0, BlobA *blob1, bool horiz);
+
74  void processCC();
+
75  void cleanup(BlobA *blobs[], int16_t *numBlobs);
+
76  void cleanup2(BlobA *blobs[], int16_t *numBlobs);
+
77  bool analyzeDistances(BlobA *blobs0[], int16_t numBlobs0, BlobA *blobs[], int16_t numBlobs, BlobA **blobA, BlobA **blobB);
+
78  void mergeClumps(uint16_t scount0, uint16_t scount1);
+
79 
+
80  void printBlobs();
+
81 
+
82  CBlobAssembler m_assembler[CL_NUM_SIGNATURES];
+
83 
+
84  uint16_t *m_blobs;
+
85  uint16_t m_numBlobs;
+
86 
+
87  BlobB *m_ccBlobs;
+
88  uint16_t m_numCCBlobs;
+
89 
+
90  bool m_mutex;
+
91  uint16_t m_maxBlobs;
+
92  uint16_t m_maxBlobsPerModel;
+
93 
+
94  uint16_t m_blobReadIndex;
+
95  uint16_t m_ccBlobReadIndex;
+
96 
+
97  uint32_t m_minArea;
+
98  uint16_t m_mergeDist;
+
99  uint16_t m_maxCodedDist;
+
100  ColorCodeMode m_ccMode;
+
101  BlobA *m_maxBlob;
+
102 
+
103 #ifndef PIXY
+
104  uint32_t m_numQvals;
+
105  uint32_t *m_qvals;
+
106 #endif
+
107 };
+
108 
+
109 
+
110 
+
111 #endif // BLOBS_H
+
CBlobAssembler
Definition: blob.h:270
+
BlobA
Definition: pixytypes.h:133
+
BlobB
Definition: pixytypes.h:156
+
Blobs
Definition: blobs.h:43
+
ColorLUT
Definition: colorlut.h:86
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2calc_8h_source.html b/emulator_2libs_2_pixy_2src_2calc_8h_source.html new file mode 100644 index 0000000..85dbfab --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2calc_8h_source.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/calc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
calc.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef CALC_H
+
17 #define CALC_H
+
18 #include <inttypes.h>
+
19 
+
20 #ifdef MAX
+
21 #undef MAX
+
22 #endif
+
23 #ifdef MIN
+
24 #undef MIN
+
25 #endif
+
26 #define MAX(a, b) (a>b ? a : b)
+
27 #define MIN(a, b) (a<b ? a : b)
+
28 
+
29 void hsvc(uint8_t r, uint8_t g, uint8_t b, uint8_t *h, uint8_t *s, uint8_t *v, uint8_t *c);
+
30 uint32_t lighten(uint32_t color, uint8_t factor);
+
31 uint32_t saturate(uint32_t color);
+
32 uint32_t rgbPack(uint32_t r, uint32_t g, uint32_t b);
+
33 void rgbUnpack(uint32_t color, uint32_t *r, uint32_t *g, uint32_t *b);
+
34 
+
35 #endif // CALC_H
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2chirp_8hpp_source.html b/emulator_2libs_2_pixy_2src_2chirp_8hpp_source.html new file mode 100644 index 0000000..e6af177 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2chirp_8hpp_source.html @@ -0,0 +1,398 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/chirp.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
chirp.hpp
+
+
+
1 #ifndef CHIRP_HPP
+
2 #define CHIRP_HPP
+
3 
+
4 #include <stdint.h>
+
5 #include <stdlib.h>
+
6 #include <stdarg.h>
+
7 #include "link.h"
+
8 
+
9 #define ALIGN(v, n) v = v&((n)-1) ? (v&~((n)-1))+(n) : v
+
10 #define FOURCC(a, b, c, d) (((uint32_t)a<<0)|((uint32_t)b<<8)|((uint32_t)c<<16)|((uint32_t)d<<24))
+
11 
+
12 #define CRP_RES_OK 0
+
13 #define CRP_RES_ERROR -1
+
14 #define CRP_RES_ERROR_RECV_TIMEOUT LINK_RESULT_ERROR_RECV_TIMEOUT
+
15 #define CRP_RES_ERROR_SEND_TIMEOUT LINK_RESULT_ERROR_SEND_TIMEOUT
+
16 #define CRP_RES_ERROR_CRC -2
+
17 #define CRP_RES_ERROR_PARSE -3
+
18 #define CRP_RES_ERROR_MAX_NAK -4
+
19 #define CRP_RES_ERROR_MEMORY -5
+
20 #define CRP_RES_ERROR_NOT_CONNECTED -6
+
21 
+
22 #define CRP_MAX_NAK 3
+
23 #define CRP_RETRIES 3
+
24 #define CRP_HEADER_TIMEOUT 1000
+
25 #define CRP_DATA_TIMEOUT 500
+
26 #define CRP_IDLE_TIMEOUT 500
+
27 #define CRP_SEND_TIMEOUT 1000
+
28 #define CRP_MAX_ARGS 10
+
29 #define CRP_BUFSIZE 0x80
+
30 #define CRP_BUFPAD 8
+
31 #define CRP_PROCTABLE_LEN 0x40
+
32 
+
33 #define CRP_START_CODE 0xaaaa5555
+
34 
+
35 #define CRP_CALL 0x80
+
36 #define CRP_RESPONSE 0x40
+
37 #define CRP_INTRINSIC 0x20
+
38 #define CRP_DATA 0x10
+
39 #define CRP_XDATA 0x18 // data not associated with no associated procedure)
+
40 #define CRP_CALL_ENUMERATE (CRP_CALL | CRP_INTRINSIC | 0x00)
+
41 #define CRP_CALL_INIT (CRP_CALL | CRP_INTRINSIC | 0x01)
+
42 #define CRP_CALL_ENUMERATE_INFO (CRP_CALL | CRP_INTRINSIC | 0x02)
+
43 
+
44 #define CRP_ACK 0x59
+
45 #define CRP_NACK 0x95
+
46 #define CRP_MAX_HEADER_LEN 64
+
47 
+
48 #define CRP_ARRAY 0x80 // bit
+
49 #define CRP_FLT 0x10 // bit
+
50 #define CRP_NO_COPY (0x10 | 0x20)
+
51 #define CRP_HINT 0x40 // bit
+
52 #define CRP_NULLTERM_ARRAY (0x20 | CRP_ARRAY) // bits
+
53 #define CRP_INT8 0x01
+
54 #define CRP_UINT8 0x01
+
55 #define CRP_INT16 0x02
+
56 #define CRP_UINT16 0x02
+
57 #define CRP_INT32 0x04
+
58 #define CRP_UINT32 0x04
+
59 #define CRP_FLT32 (CRP_FLT | 0x04)
+
60 #define CRP_FLT64 (CRP_FLT | 0x08)
+
61 #define CRP_STRING (CRP_NULLTERM_ARRAY | CRP_INT8)
+
62 #define CRP_TYPE_HINT 0x64 // type hint identifier
+
63 #define CRP_INTS8 (CRP_INT8 | CRP_ARRAY)
+
64 #define CRP_INTS16 (CRP_INT16 | CRP_ARRAY)
+
65 #define CRP_INTS32 (CRP_INT32 | CRP_ARRAY)
+
66 #define CRP_UINTS8 CRP_INTS8
+
67 #define CRP_UINTS8_NO_COPY (CRP_INTS8 | CRP_NO_COPY)
+
68 #define CRP_UINTS16_NO_COPY (CRP_INTS16 | CRP_NO_COPY)
+
69 #define CRP_UINTS32_NO_COPY (CRP_INTS32 | CRP_NO_COPY)
+
70 #define CRP_UINTS16 CRP_INTS16
+
71 #define CRP_UINTS32 CRP_INTS32
+
72 #define CRP_FLTS32 (CRP_FLT32 | CRP_ARRAY)
+
73 #define CRP_FLTS64 (CRP_FLT64 | CRP_ARRAY)
+
74 #define CRP_HINT8 (CRP_INT8 | CRP_HINT)
+
75 #define CRP_HINT16 (CRP_INT16 | CRP_HINT)
+
76 #define CRP_HINT32 (CRP_INT32 | CRP_HINT)
+
77 #define CRP_HINTS8 (CRP_INT8 | CRP_ARRAY | CRP_HINT)
+
78 #define CRP_HINTS16 (CRP_INT16 | CRP_ARRAY | CRP_HINT)
+
79 #define CRP_HINTS32 (CRP_INT32 | CRP_ARRAY | CRP_HINT)
+
80 #define CRP_HFLTS32 (CRP_FLT32 | CRP_ARRAY | CRP_HINT)
+
81 #define CRP_HFLTS64 (CRP_FLT64 | CRP_ARRAY | CRP_HINT)
+
82 #define CRP_HSTRING (CRP_STRING | CRP_HINT)
+
83 // CRP_HTYPE is for arg lists which are uint8_t arrays
+
84 #define CRP_HTYPE(v) CRP_TYPE_HINT, (uint8_t)(v>>0&0xff), (uint8_t)(v>>8&0xff), (uint8_t)(v>>16&0xff), (uint8_t)(v>>24&0xff)
+
85 
+
86 // regular call args
+
87 #define INT8(v) CRP_INT8, v
+
88 #define UINT8(v) CRP_INT8, v
+
89 #define INT16(v) CRP_INT16, v
+
90 #define UINT16(v) CRP_INT16, v
+
91 #define INT32(v) CRP_INT32, v
+
92 #define UINT32(v) CRP_INT32, v
+
93 #define FLT32(v) CRP_FLT32, v
+
94 #define FLT64(v) CRP_FLT64, v
+
95 #define STRING(s) CRP_STRING, s
+
96 #define INTS8(len, a) CRP_INTS8, len, a
+
97 #define UINTS8(len, a) CRP_INTS8, len, a
+
98 #define UINTS8_NO_COPY(len) CRP_UINTS8_NO_COPY, len
+
99 #define UINTS16_NO_COPY(len) CRP_UINTS16_NO_COPY, len
+
100 #define UINTS32_NO_COPY(len) CRP_UINTS32_NO_COPY, len
+
101 #define INTS16(len, a) CRP_INTS16, len, a
+
102 #define UINTS16(len, a) CRP_INTS16, len, a
+
103 #define INTS32(len, a) CRP_INTS32, len, a
+
104 #define UINTS32(len, a) CRP_INTS32, len, a
+
105 #define FLTS32(len, a) CRP_FLTS32, len, a
+
106 #define FLTS64(len, a) CRP_FLTS64, len, a
+
107 
+
108 // hint call args
+
109 #define HINT8(v) CRP_HINT8, v
+
110 #define UHINT8(v) CRP_HINT8, v
+
111 #define HINT16(v) CRP_HINT16, v
+
112 #define UHINT16(v) CRP_HINT16, v
+
113 #define HINT32(v) CRP_HINT32, v
+
114 #define UHINT32(v) CRP_HINT32, v
+
115 #define HFLT32(v) CRP_HFLT32, v
+
116 #define HFLT64(v) CRP_HFLT64, v
+
117 #define HSTRING(s) CRP_HSTRING, s
+
118 #define HINTS8(len, a) CRP_HINTS8, len, a
+
119 #define UHINTS8(len, a) CRP_HINTS8, len, a
+
120 #define HINTS16(len, a) CRP_HINTS16, len, a
+
121 #define UHINTS16(len, a) CRP_HINTS16, len, a
+
122 #define HINTS32(len, a) CRP_HINTS32, len, a
+
123 #define UHINTS32(len, a) CRP_HINTS32, len, a
+
124 #define HFLTS32(len, a) CRP_HFLTS32, len, a
+
125 #define HFLTS64(len, a) CRP_HFLTS64, len, a
+
126 #define HTYPE(v) CRP_TYPE_HINT, v
+
127 
+
128 #define INT8_IN(v) int8_t & v
+
129 #define UINT8_IN(v) uint8_t & v
+
130 #define INT16_IN(v) int16_t & v
+
131 #define UINT16_IN(v) uint16_t & v
+
132 #define INT32_IN(v) int32_t & v
+
133 #define UINT32_IN(v) uint32_t & v
+
134 #define FLT32_IN(v) float & v
+
135 #define FLT64_IN(v) double & v
+
136 #define STRING_IN(s) const char * s
+
137 #define INTS8_IN(len, a) uint32_t & len, int8_t * a
+
138 #define UINTS8_IN(len, a) uint32_t & len, uint8_t * a
+
139 #define INTS16_IN(len, a) uint32_t & len, int16_t * a
+
140 #define UINTS16_IN(len, a) uint32_t & len, uint16_t * a
+
141 #define INTS32_IN(len, a) uint32_t & len, int32_t * a
+
142 #define UINTS32_IN(len, a) uint32_t & len, uint32_t * a
+
143 #define FLTS32_IN(len, a) uint32_t & len, float * a
+
144 #define FLTS64_IN(len, a) uint32_t & len, double * a
+
145 
+
146 #ifndef END
+
147 #ifdef __x86_64__
+
148 #define END (int64_t)0
+
149 #else
+
150 #define END 0
+
151 #endif
+
152 #endif
+
153 #define END_OUT_ARGS END
+
154 #define END_IN_ARGS END
+
155 
+
156 // service types
+
157 #define SYNC 0
+
158 #define ASYNC 0x01 // bit
+
159 #define RETURN_ARRAY 0x02 // bit
+
160 #define SYNC_RETURN_ARRAY (SYNC | RETURN_ARRAY)
+
161 
+
162 #define CRP_RETURN(chirp, ...) chirp->assemble(0, __VA_ARGS__, END)
+
163 #define CRP_SEND_XDATA(chirp, ...) chirp->assemble(CRP_XDATA, __VA_ARGS__, END)
+
164 #define callSync(...) call(SYNC, __VA_ARGS__, END)
+
165 #define callAsync(...) call(ASYNC, __VA_ARGS__, END)
+
166 #define callSyncArray(...) call(SYNC_RETURN_ARRAY, __VA_ARGS__, END)
+
167 
+
168 class Chirp;
+
169 
+
170 typedef int16_t ChirpProc; // negative values are invalid
+
171 
+
172 typedef uint32_t (*ProcPtr)(Chirp *);
+
173 
+
174 struct ProcModule
+
175 {
+
176  char *procName;
+
177  ProcPtr procPtr;
+
178  uint8_t argTypes[CRP_MAX_ARGS];
+
179  char *procInfo;
+
180 };
+
181 
+
182 struct ProcTableExtension
+
183 {
+
184  uint8_t argTypes[CRP_MAX_ARGS];
+
185  char *procInfo;
+
186 };
+
187 
+
188 struct ProcInfo
+
189 {
+
190  char *procName;
+
191  uint8_t *argTypes;
+
192  char *procInfo;
+
193 };
+
194 
+
195 struct ProcTableEntry
+
196 {
+
197  const char *procName;
+
198  ProcPtr procPtr;
+
199  ChirpProc chirpProc;
+
200  const ProcTableExtension *extension;
+
201 };
+
202 
+
203 class Chirp
+
204 {
+
205 public:
+
206  Chirp(bool hinterested=false, bool client=false, Link *link=NULL);
+
207  ~Chirp();
+
208 
+
209  virtual int init(bool connect);
+
210  int setLink(Link *link);
+
211  ChirpProc getProc(const char *procName, ProcPtr callback=0);
+
212  int setProc(const char *procName, ProcPtr proc, ProcTableExtension *extension=NULL);
+
213  int getProcInfo(ChirpProc proc, ProcInfo *info);
+
214  int registerModule(const ProcModule *module);
+
215  void setSendTimeout(uint32_t timeout);
+
216  void setRecvTimeout(uint32_t timeout);
+
217 
+
218  int call(uint8_t service, ChirpProc proc, ...);
+
219  int call(uint8_t service, ChirpProc proc, va_list args);
+
220  static uint8_t getType(const void *arg);
+
221  int service(bool all=true);
+
222  int assemble(uint8_t type, ...);
+
223  bool connected();
+
224 
+
225  // utility methods
+
226  static int serialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, ...);
+
227  static int deserialize(uint8_t *buf, uint32_t len, ...);
+
228  static int vserialize(Chirp *chirp, uint8_t *buf, uint32_t bufSize, va_list *args);
+
229  static int vdeserialize(uint8_t *buf, uint32_t len, va_list *args);
+
230  static int deserializeParse(uint8_t *buf, uint32_t len, void *args[]);
+
231  static int loadArgs(va_list *args, void *recvArgs[]);
+
232  static int getArgList(uint8_t *buf, uint32_t len, uint8_t *argList);
+
233  int useBuffer(uint8_t *buf, uint32_t len);
+
234 
+
235  static uint16_t calcCrc(uint8_t *buf, uint32_t len);
+
236 
+
237 protected:
+
238  int remoteInit(bool connect);
+
239  int recvChirp(uint8_t *type, ChirpProc *proc, void *args[], bool wait=false); // null pointer terminates
+
240  virtual int handleChirp(uint8_t type, ChirpProc proc, const void *args[]); // null pointer terminates
+
241  virtual void handleXdata(const void *data[]) {(void)data;}
+
242  virtual int sendChirp(uint8_t type, ChirpProc proc);
+
243 
+
244  uint8_t *m_buf;
+
245  uint8_t *m_bufSave;
+
246  uint32_t m_len;
+
247  uint32_t m_offset;
+
248  uint32_t m_bufSize;
+
249  bool m_errorCorrected;
+
250  bool m_sharedMem;
+
251  bool m_hinformer;
+
252  bool m_hinterested;
+
253  bool m_client;
+
254  uint32_t m_headerLen;
+
255  uint16_t m_headerTimeout;
+
256  uint16_t m_dataTimeout;
+
257  uint16_t m_idleTimeout;
+
258  uint16_t m_sendTimeout;
+
259 
+
260 private:
+
261  int sendHeader(uint8_t type, ChirpProc proc);
+
262  int sendFull(uint8_t type, ChirpProc proc);
+
263  int sendData();
+
264  int sendAck(bool ack); // false=nack
+
265  int sendChirpRetry(uint8_t type, ChirpProc proc);
+
266  int recvHeader(uint8_t *type, ChirpProc *proc, bool wait);
+
267  int recvFull(uint8_t *type, ChirpProc *proc, bool wait);
+
268  int recvData();
+
269  int recvAck(bool *ack, uint16_t timeout); // false=nack
+
270  int32_t handleEnumerate(char *procName, ChirpProc *callback);
+
271  int32_t handleInit(uint16_t *blkSize, uint8_t *hintSource);
+
272  int32_t handleEnumerateInfo(ChirpProc *proc);
+
273  int vassemble(va_list *args);
+
274  void restoreBuffer();
+
275 
+
276  ChirpProc updateTable(const char *procName, ProcPtr procPtr);
+
277  ChirpProc lookupTable(const char *procName);
+
278  int realloc(uint32_t min=0);
+
279  int reallocTable();
+
280 
+
281  Link *m_link;
+
282  ProcTableEntry *m_procTable;
+
283  uint16_t m_procTableSize;
+
284  uint16_t m_blkSize;
+
285  uint8_t m_maxNak;
+
286  uint8_t m_retries;
+
287  bool m_call;
+
288  bool m_connected;
+
289 };
+
290 
+
291 #endif // CHIRP_H
+
ProcTableExtension
Definition: chirp.hpp:182
+
ProcTableEntry
Definition: chirp.hpp:195
+
Chirp
Definition: chirp.hpp:203
+
ProcModule
Definition: chirp.hpp:174
+
ProcInfo
Definition: chirp.hpp:188
+ +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html b/emulator_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html new file mode 100644 index 0000000..41285d2 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2chirpreceiver_8hpp_source.html @@ -0,0 +1,142 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/chirpreceiver.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
chirpreceiver.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __CHIRPRECEIVER_HPP__
+
17 #define __CHIRPRECEIVER_HPP__
+
18 
+
19 #include "chirp.hpp"
+
20 #include "usblink.h"
+
21 #include "interpreter.hpp"
+
22 
+
23 class ChirpReceiver : public Chirp
+
24 {
+
25  public:
+
26 
+
27  ChirpReceiver(USBLink * link, Interpreter * interpreter);
+
28  virtual ~ChirpReceiver();
+
29 
+
30  private:
+
31 
+
32  Interpreter * interpreter_;
+
33 
+
40  void handleXdata(const void * data[]);
+
41 };
+
42 
+
43 #endif
+
Chirp
Definition: chirp.hpp:203
+
ChirpReceiver
Definition: chirpreceiver.hpp:23
+ +
Interpreter
Definition: interpreter.hpp:19
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2colorlut_8h_source.html b/emulator_2libs_2_pixy_2src_2colorlut_8h_source.html new file mode 100644 index 0000000..dceaead --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2colorlut_8h_source.html @@ -0,0 +1,240 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/colorlut.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
colorlut.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef COLORLUT_H
+
16 #define COLORLUT_H
+
17 
+
18 #include <inttypes.h>
+
19 #include "simplevector.h"
+
20 #include "pixytypes.h"
+
21 
+
22 #define CL_NUM_SIGNATURES 7
+
23 #define CL_LUT_COMPONENT_SCALE 6
+
24 #define CL_LUT_SIZE (1<<(CL_LUT_COMPONENT_SCALE*2))
+
25 #define CL_LUT_ENTRY_SCALE 15
+
26 #define CL_GROW_INC 4
+
27 #define CL_MIN_Y_F 0.05 // for when generating signatures, etc
+
28 #define CL_MIN_Y (int32_t)(3*((1<<8)-1)*CL_MIN_Y_F)
+
29 #define CL_MIN_RATIO 0.25f
+
30 #define CL_DEFAULT_MINY 0.1f
+
31 #define CL_DEFAULT_SIG_RANGE 2.5f
+
32 #define CL_MAX_DIST 2000
+
33 #define CL_DEFAULT_TOL 0.9f
+
34 #define CL_DEFAULT_CCGAIN 1.5f
+
35 #define CL_MODEL_TYPE_COLORCODE 1
+
36 
+
37 
+
38 struct ColorSignature
+
39 {
+
40  ColorSignature()
+
41  {
+
42  m_uMin = m_uMax = m_uMean = m_vMin = m_vMax = m_vMean = m_type = 0;
+
43  }
+
44 
+
45  int32_t m_uMin;
+
46  int32_t m_uMax;
+
47  int32_t m_uMean;
+
48  int32_t m_vMin;
+
49  int32_t m_vMax;
+
50  int32_t m_vMean;
+
51  uint32_t m_rgb;
+
52  uint32_t m_type;
+
53 };
+
54 
+
55 struct RuntimeSignature
+
56 {
+
57  int32_t m_uMin;
+
58  int32_t m_uMax;
+
59  int32_t m_vMin;
+
60  int32_t m_vMax;
+
61  uint32_t m_rgbSat;
+
62 };
+
63 
+
64 typedef SimpleVector<Point16> Points;
+
65 
+
66 class IterPixel
+
67 {
+
68 public:
+
69  IterPixel(const Frame8 &frame, const RectA &region);
+
70  IterPixel(const Frame8 &frame, const Points *points);
+
71  bool next(UVPixel *uv, RGBPixel *rgb=NULL);
+
72  bool reset(bool cleari=true);
+
73  uint32_t averageRgb(uint32_t *pixels=NULL);
+
74 
+
75 private:
+
76  bool nextHelper(UVPixel *uv, RGBPixel *rgb);
+
77 
+
78  Frame8 m_frame;
+
79  RectA m_region;
+
80  uint32_t m_x, m_y;
+
81  uint8_t *m_pixels;
+
82  const Points *m_points;
+
83  int m_i;
+
84 };
+
85 
+
86 class ColorLUT
+
87 {
+
88 public:
+
89  ColorLUT(uint8_t *lut);
+
90  ~ColorLUT();
+
91 
+
92  int generateSignature(const Frame8 &frame, const RectA &region, uint8_t signum);
+
93  int generateSignature(const Frame8 &frame, const Point16 &point, Points *points, uint8_t signum);
+
94  ColorSignature *getSignature(uint8_t signum);
+
95  int setSignature(uint8_t signum, const ColorSignature &sig);
+
96 
+
97  int generateLUT();
+
98  void clearLUT(uint8_t signum=0);
+
99  void updateSignature(uint8_t signum);
+
100  void growRegion(const Frame8 &frame, const Point16 &seed, Points *points);
+
101 
+
102  void setSigRange(uint8_t signum, float range);
+
103  void setMinBrightness(float miny);
+
104  void setGrowDist(uint32_t dist);
+
105  void setCCGain(float gain);
+
106  uint32_t getType(uint8_t signum);
+
107 
+
108  // these should be in little access methods, but they're here to speed things up a tad
+
109  ColorSignature m_signatures[CL_NUM_SIGNATURES];
+
110  RuntimeSignature m_runtimeSigs[CL_NUM_SIGNATURES];
+
111  uint32_t m_miny;
+
112 
+
113 private:
+
114  bool growRegion(RectA *region, const Frame8 &frame, uint8_t dir);
+
115  float testRegion(const RectA &region, const Frame8 &frame, UVPixel *mean, Points *points);
+
116 
+
117  void calcRatios(IterPixel *ip, ColorSignature *sig, float ratios[]);
+
118  void iterate(IterPixel *ip, ColorSignature *sig);
+
119  void getMean(const RectA &region ,const Frame8 &frame, UVPixel *mean);
+
120 
+
121  uint8_t *m_lut;
+
122  uint32_t m_maxDist;
+
123  float m_ratio;
+
124  float m_minRatio;
+
125  float m_ccGain;
+
126  float m_sigRanges[CL_NUM_SIGNATURES];
+
127 };
+
128 
+
129 #endif // COLORLUT_H
+
RectA
Definition: pixytypes.h:91
+
Point16
Definition: pixytypes.h:37
+
RGBPixel
Definition: pixytypes.h:233
+
RuntimeSignature
Definition: colorlut.h:55
+
UVPixel
Definition: pixytypes.h:216
+
Frame8
Definition: pixytypes.h:71
+
ColorLUT
Definition: colorlut.h:86
+
ColorSignature
Definition: colorlut.h:38
+
SimpleVector
Definition: simplevector.h:23
+
IterPixel
Definition: colorlut.h:66
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2debug_8h_source.html b/emulator_2libs_2_pixy_2src_2debug_8h_source.html new file mode 100644 index 0000000..3637cfe --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2debug_8h_source.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/debug.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
debug.h
+
+
+
1 #ifndef DEBUG_H
+
2 #define DEBUG_H
+
3 
+
4 #define DBG(...)
+
5 
+
6 #endif // DEBUG_H
+
7 
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2debuglog_8h_source.html b/emulator_2libs_2_pixy_2src_2debuglog_8h_source.html new file mode 100644 index 0000000..c899fd4 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2debuglog_8h_source.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/debuglog.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
debuglog.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef __DEBUG_H__
+
16 #define __DEBUG_H__
+
17 
+
18 #include <stdarg.h>
+
19 #include <stdio.h>
+
20 
+
21 static void log(const char *format, ...)
+
22 {
+
23 #ifdef DEBUG
+
24  va_list elements;
+
25 
+
26  // Send debug message to stdout //
+
27  va_start(elements, format);
+
28  vfprintf(stderr,format, elements);
+
29  fflush(stderr);
+
30  va_end(elements);
+
31  #else
+
32  (void)format;
+
33 #endif
+
34 }
+
35 
+
36 #endif
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2interpreter_8hpp_source.html b/emulator_2libs_2_pixy_2src_2interpreter_8hpp_source.html new file mode 100644 index 0000000..775f9c8 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2interpreter_8hpp_source.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/interpreter.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
interpreter.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __INTERPRETER_HPP__
+
17 #define __INTERPRETER_HPP__
+
18 
+
19 class Interpreter
+
20 {
+
21  public:
+
22 
+
23  virtual void interpret_data(const void *data []) = 0;
+
24 };
+
25 
+
26 #endif
+
Interpreter
Definition: interpreter.hpp:19
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2link_8h_source.html b/emulator_2libs_2_pixy_2src_2link_8h_source.html new file mode 100644 index 0000000..507819a --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2link_8h_source.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/link.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
link.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef LINK_H
+
16 #define LINK_H
+
17 
+
18 #include <stdint.h>
+
19 
+
20 // flags
+
21 #define LINK_FLAG_SHARED_MEM 0x01
+
22 #define LINK_FLAG_ERROR_CORRECTED 0x02
+
23 
+
24 // result codes
+
25 #define LINK_RESULT_OK 0
+
26 #define LINK_RESULT_ERROR -100
+
27 #define LINK_RESULT_ERROR_RECV_TIMEOUT -101
+
28 #define LINK_RESULT_ERROR_SEND_TIMEOUT -102
+
29 
+
30 // link flag index
+
31 #define LINK_FLAG_INDEX_FLAGS 0x00
+
32 #define LINK_FLAG_INDEX_SHARED_MEMORY_LOCATION 0x01
+
33 #define LINK_FLAG_INDEX_SHARED_MEMORY_SIZE 0x02
+
34 
+
35 
+
36 class Link
+
37 {
+
38 public:
+
39  Link()
+
40  {
+
41  m_flags = 0;
+
42  m_blockSize = 0;
+
43  }
+
44  ~Link()
+
45  {
+
46  }
+
47 
+
48  // the timeoutMs is a timeout value in milliseconds. The timeout timer should expire
+
49  // when the data channel has been continuously idle for the specified amount of time
+
50  // not the summation of the idle times.
+
51  virtual int send(const uint8_t *data, uint32_t len, uint16_t timeoutMs) = 0;
+
52  virtual int receive(uint8_t *data, uint32_t len, uint16_t timeoutMs) = 0;
+
53  virtual void setTimer() = 0;
+
54  virtual uint32_t getTimer() = 0; // returns elapsed time in milliseconds since setTimer() was called
+
55  virtual uint32_t getFlags(uint8_t index=LINK_FLAG_INDEX_FLAGS)
+
56  {
+
57  if (index==LINK_FLAG_INDEX_FLAGS)
+
58  return m_flags;
+
59  else
+
60  return 0;
+
61  }
+
62  virtual uint32_t blockSize()
+
63  {
+
64  return m_blockSize;
+
65  }
+
66  virtual int getBuffer(uint8_t **, uint32_t *)
+
67  {
+
68  return LINK_RESULT_ERROR;
+
69  }
+
70 
+
71 protected:
+
72  uint32_t m_flags;
+
73  uint32_t m_blockSize;
+
74 };
+
75 
+
76 #endif // LINK_H
+ +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html b/emulator_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html new file mode 100644 index 0000000..c952c9c --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2pixyinterpreter_8hpp_source.html @@ -0,0 +1,185 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/pixyinterpreter.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixyinterpreter.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __PIXYINTERPRETER_HPP__
+
17 #define __PIXYINTERPRETER_HPP__
+
18 
+
19 #include <vector>
+
20 #include "pixytypes.h"
+
21 #include "pixy.h"
+
22 #include "pixydefs.h"
+
23 #include "usblink.h"
+
24 #include "interpreter.hpp"
+
25 #include "chirpreceiver.hpp"
+
26 
+
27 #define PIXY_BLOCK_CAPACITY 250
+
28 
+
29 class PixyInterpreter : public Interpreter
+
30 {
+
31  public:
+
32 
+
33  PixyInterpreter();
+
34  ~PixyInterpreter();
+
35 
+
48  int init();
+
49 
+
54  void close();
+
55 
+
62  int blocks_are_new();
+
63 
+
79  int get_blocks(int max_blocks, Block * blocks);
+
80 
+
87  int send_command(const char * name, va_list arguments);
+
88 
+
94  int send_command(const char * name, ...);
+
95 
+
96 
+
97 
+
98  int service();
+
99 
+
100  private:
+
101 
+
102  ChirpReceiver * receiver_;
+
103  USBLink link_;
+
104  std::vector<Block> blocks_;
+
105  bool blocks_are_new_;
+
106  bool init_;
+
107 
+
108 
+
114  void interpret_data(const void * chrip_data[]);
+
115 
+
121  void interpret_CCB1(const void * data[]);
+
122 
+
128  void interpret_CCB2(const void * data[]);
+
129 
+
137  void add_normal_blocks(const BlobA * blocks, uint32_t count);
+
138 
+
146  void add_color_code_blocks(const BlobB * blocks, uint32_t count);
+
147 };
+
148 
+
149 #endif
+
PixyInterpreter::send_command
int send_command(const char *name, va_list arguments)
Sends a command to Pixy.
Definition: pixyinterpreter.cpp:100
+
PixyInterpreter::get_blocks
int get_blocks(int max_blocks, Block *blocks)
Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. ...
Definition: pixyinterpreter.cpp:64
+
PixyInterpreter::close
void close()
Terminates the USB connection to Pixy and the 'iterpreter' thread.
Definition: pixyinterpreter.cpp:54
+
BlobA
Definition: pixytypes.h:133
+
ChirpReceiver
Definition: chirpreceiver.hpp:23
+ +
BlobB
Definition: pixytypes.h:156
+
PixyInterpreter::init
int init()
Spawns an 'interpreter' thread which attempts to connect to Pixy using the USB interface. On successful connection, this thread will capture and store Pixy 'block' object data which can be retreived using the getBlocks() method.
Definition: pixyinterpreter.cpp:31
+
PixyInterpreter
Definition: pixyinterpreter.hpp:29
+
Interpreter
Definition: interpreter.hpp:19
+
PixyInterpreter::blocks_are_new
int blocks_are_new()
Get status of the block data received from Pixy.
Definition: pixyinterpreter.cpp:289
+
Block
Definition: pixy.h:47
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2pixytypes_8h_source.html b/emulator_2libs_2_pixy_2src_2pixytypes_8h_source.html new file mode 100644 index 0000000..d7114e2 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2pixytypes_8h_source.html @@ -0,0 +1,384 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/pixytypes.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixytypes.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef PIXYTYPES_H
+
17 #define PIXYTYPES_H
+
18 
+
19 #include <stdint.h>
+
20 
+
21 #define RENDER_FLAG_FLUSH 0x01 // add to stack, render immediately
+
22 #define RENDER_FLAG_BLEND 0x02 // blend with a previous images in image stack
+
23 
+
24 #define PRM_FLAG_INTERNAL 0x00000001
+
25 #define PRM_FLAG_ADVANCED 0x00000002
+
26 #define PRM_FLAG_HEX_FORMAT 0x00000010
+
27 #define PRM_FLAG_SIGNED 0x00000080
+
28 
+
29 // render-specific flags
+
30 #define PRM_FLAG_SLIDER 0x00000100
+
31 #define PRM_FLAG_CHECKBOX 0x00000200
+
32 #define PRM_FLAG_PATH 0x00000400
+
33 
+
34 // events
+
35 #define EVT_PARAM_CHANGE 1
+
36 
+
37 struct Point16
+
38 {
+
39  Point16()
+
40  {
+
41  m_x = m_y = 0;
+
42  }
+
43 
+
44  Point16(int16_t x, int16_t y)
+
45  {
+
46  m_x = x;
+
47  m_y = y;
+
48  }
+
49 
+
50  int16_t m_x;
+
51  int16_t m_y;
+
52 };
+
53 
+
54 struct Point32
+
55 {
+
56  Point32()
+
57  {
+
58  m_x = m_y = 0;
+
59  }
+
60 
+
61  Point32(int32_t x, int32_t y)
+
62  {
+
63  m_x = x;
+
64  m_y = y;
+
65  }
+
66 
+
67  int32_t m_x;
+
68  int32_t m_y;
+
69 };
+
70 
+
71 struct Frame8
+
72 {
+
73  Frame8()
+
74  {
+
75  m_pixels = (uint8_t *)NULL;
+
76  m_width = m_height = 0;
+
77  }
+
78 
+
79  Frame8(uint8_t *pixels, uint16_t width, uint16_t height)
+
80  {
+
81  m_pixels = pixels;
+
82  m_width = width;
+
83  m_height = height;
+
84  }
+
85 
+
86  uint8_t *m_pixels;
+
87  int16_t m_width;
+
88  int16_t m_height;
+
89 };
+
90 
+
91 struct RectA
+
92 {
+
93  RectA()
+
94  {
+
95  m_xOffset = m_yOffset = m_width = m_height = 0;
+
96  }
+
97 
+
98  RectA(uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height)
+
99  {
+
100  m_xOffset = xOffset;
+
101  m_yOffset = yOffset;
+
102  m_width = width;
+
103  m_height = height;
+
104  }
+
105 
+
106  uint16_t m_xOffset;
+
107  uint16_t m_yOffset;
+
108  uint16_t m_width;
+
109  uint16_t m_height;
+
110 };
+
111 
+
112 struct RectB
+
113 {
+
114  RectB()
+
115  {
+
116  m_left = m_right = m_top = m_bottom = 0;
+
117  }
+
118 
+
119  RectB(uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
+
120  {
+
121  m_left = left;
+
122  m_right = right;
+
123  m_top = top;
+
124  m_bottom = bottom;
+
125  }
+
126 
+
127  uint16_t m_left;
+
128  uint16_t m_right;
+
129  uint16_t m_top;
+
130  uint16_t m_bottom;
+
131 };
+
132 
+
133 struct BlobA
+
134 {
+
135  BlobA()
+
136  {
+
137  m_model = m_left = m_right = m_top = m_bottom = 0;
+
138  }
+
139 
+
140  BlobA(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
+
141  {
+
142  m_model = model;
+
143  m_left = left;
+
144  m_right = right;
+
145  m_top = top;
+
146  m_bottom = bottom;
+
147  }
+
148 
+
149  uint16_t m_model;
+
150  uint16_t m_left;
+
151  uint16_t m_right;
+
152  uint16_t m_top;
+
153  uint16_t m_bottom;
+
154 };
+
155 
+
156 struct BlobB
+
157 {
+
158  BlobB()
+
159  {
+
160  m_model = m_left = m_right = m_top = m_bottom = m_angle = 0;
+
161  }
+
162 
+
163  BlobB(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle)
+
164  {
+
165  m_model = model;
+
166  m_left = left;
+
167  m_right = right;
+
168  m_top = top;
+
169  m_bottom = bottom;
+
170  m_angle = angle;
+
171  }
+
172 
+
173  uint16_t m_model;
+
174  uint16_t m_left;
+
175  uint16_t m_right;
+
176  uint16_t m_top;
+
177  uint16_t m_bottom;
+
178  int16_t m_angle;
+
179 };
+
180 
+
181 
+
182 struct HuePixel
+
183 {
+
184  HuePixel()
+
185  {
+
186  m_u = m_v = 0;
+
187  }
+
188 
+
189  HuePixel(int8_t u, int8_t v)
+
190  {
+
191  m_u = u;
+
192  m_v = v;
+
193  }
+
194 
+
195  int8_t m_u;
+
196  int8_t m_v;
+
197 };
+
198 
+
199 struct Fpoint
+
200 {
+
201  Fpoint()
+
202  {
+
203  m_x = m_y = 0.0;
+
204  }
+
205 
+
206  Fpoint(float x, float y)
+
207  {
+
208  m_x = x;
+
209  m_y = y;
+
210  }
+
211 
+
212  float m_x;
+
213  float m_y;
+
214 };
+
215 
+
216 struct UVPixel
+
217 {
+
218  UVPixel()
+
219  {
+
220  m_u = m_v = 0;
+
221  }
+
222 
+
223  UVPixel(int32_t u, int32_t v)
+
224  {
+
225  m_u = u;
+
226  m_v = v;
+
227  }
+
228 
+
229  int32_t m_u;
+
230  int32_t m_v;
+
231 };
+
232 
+
233 struct RGBPixel
+
234 {
+
235  RGBPixel()
+
236  {
+
237  m_r = m_g = m_b = 0;
+
238  }
+
239 
+
240  RGBPixel(uint8_t r, uint8_t g, uint8_t b)
+
241  {
+
242  m_r = r;
+
243  m_g = g;
+
244  m_b = b;
+
245  }
+
246 
+
247  uint8_t m_r;
+
248  uint8_t m_g;
+
249  uint8_t m_b;
+
250 };
+
251 
+
252 
+
253 struct Line
+
254 {
+
255  Line()
+
256  {
+
257  m_slope = m_yi = 0.0;
+
258  }
+
259  Line(float slope, float yi)
+
260  {
+
261  m_slope = slope;
+
262  m_yi = yi;
+
263  }
+
264 
+
265  float m_slope;
+
266  float m_yi;
+
267 };
+
268 
+
269 typedef long long longlong;
+
270 
+
271 #endif // PIXYTYPES_H
+
RectA
Definition: pixytypes.h:91
+
BlobA
Definition: pixytypes.h:133
+
Point16
Definition: pixytypes.h:37
+
Fpoint
Definition: pixytypes.h:199
+
RGBPixel
Definition: pixytypes.h:233
+
BlobB
Definition: pixytypes.h:156
+
Point32
Definition: pixytypes.h:54
+
UVPixel
Definition: pixytypes.h:216
+
HuePixel
Definition: pixytypes.h:182
+
Line
Definition: pixytypes.h:253
+
Frame8
Definition: pixytypes.h:71
+
RectB
Definition: pixytypes.h:112
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2qqueue_8h_source.html b/emulator_2libs_2_pixy_2src_2qqueue_8h_source.html new file mode 100644 index 0000000..272499d --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2qqueue_8h_source.html @@ -0,0 +1,208 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/qqueue.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
qqueue.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 #ifndef _QQUEUE_H
+
16 #define _QQUEUE_H
+
17 #include <inttypes.h>
+
18 
+
19 #define QQ_LOC SRAM4_LOC
+
20 #ifdef PIXY
+
21 #define QQ_SIZE 0x3c00
+
22 #else
+
23 #define QQ_SIZE 0x30000
+
24 #endif
+
25 #define QQ_MEM_SIZE ((QQ_SIZE-sizeof(struct QqueueFields)+sizeof(Qval))/sizeof(Qval))
+
26 
+
27 #ifdef __cplusplus
+
28 struct Qval
+
29 #else
+
30 typedef struct
+
31 #endif
+
32 {
+
33 #ifdef __cplusplus
+
34  Qval()
+
35  {
+
36  m_u = m_v = m_y = m_col = 0;
+
37  }
+
38 
+
39  Qval(int16_t u, int16_t v, uint16_t y, uint16_t col)
+
40  {
+
41  m_u = u;
+
42  m_v = v;
+
43  m_y = y;
+
44  m_col = col;
+
45  }
+
46 #endif
+
47 
+
48  uint16_t m_col;
+
49  int16_t m_v;
+
50  int16_t m_u;
+
51  uint16_t m_y;
+
52 
+
53 #ifdef __cplusplus
+
54 };
+
55 #else
+
56 } Qval;
+
57 #endif
+
58 
+
59 
+
60 struct QqueueFields
+
61 {
+
62  uint16_t readIndex;
+
63  uint16_t writeIndex;
+
64 
+
65  uint16_t produced;
+
66  uint16_t consumed;
+
67 
+
68  // (array size below doesn't matter-- we're just going to cast a pointer to this struct)
+
69  Qval data[1]; // data
+
70 };
+
71 
+
72 #ifdef __cplusplus // M4 is C++ and the "consumer" of data
+
73 
+
74 class Qqueue
+
75 {
+
76 public:
+
77  Qqueue();
+
78  ~Qqueue();
+
79 
+
80  uint32_t dequeue(Qval *val);
+
81  uint32_t queued()
+
82  {
+
83  return m_fields->produced - m_fields->consumed;
+
84  }
+
85 #ifndef PIXY
+
86  int enqueue(Qval *val);
+
87 #endif
+
88 
+
89  uint32_t readAll(Qval *mem, uint32_t size);
+
90  void flush();
+
91 
+
92 private:
+
93  QqueueFields *m_fields;
+
94 };
+
95 
+
96 #else // M0 is C and the "producer" of data (Qvals)
+
97 
+
98 uint32_t qq_enqueue(const Qval *val);
+
99 uint16_t qq_free(void);
+
100 
+
101 extern struct QqueueFields *g_qqueue;
+
102 
+
103 #endif
+
104 
+
105 #endif
+
Qval
Definition: qqueue.h:30
+
QqueueFields
Definition: qqueue.h:60
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2simplevector_8h_source.html b/emulator_2libs_2_pixy_2src_2simplevector_8h_source.html new file mode 100644 index 0000000..81c9e6b --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2simplevector_8h_source.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/simplevector.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
simplevector.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef SIMPLEVECTOR_H
+
17 #define SIMPLEVECTOR_H
+
18 
+
19 #include <new>
+
20 
+
21 #define SPARE_CAPACITY 16
+
22 
+
23 template <typename Object> class SimpleVector
+
24 {
+
25 public:
+
26 
+
27  SimpleVector(int initSize = 0)
+
28  : m_size(0), m_capacity(initSize + SPARE_CAPACITY)
+
29  { m_objects = new Object[m_capacity]; }
+
30 
+
31  ~SimpleVector()
+
32  { delete [] m_objects; }
+
33 
+
34  int resize(int newCapacity)
+
35  {
+
36  if(newCapacity < m_size)
+
37  return 0;
+
38 
+
39  Object *oldArray = m_objects;
+
40 
+
41  m_objects = new (std::nothrow) Object[newCapacity];
+
42  if (m_objects==NULL)
+
43  {
+
44  m_objects = oldArray;
+
45  return -1;
+
46  }
+
47  for(int k = 0; k<m_size; k++)
+
48  m_objects[k] = oldArray[k];
+
49 
+
50  m_capacity = newCapacity;
+
51 
+
52  delete [] oldArray;
+
53  return 0;
+
54  }
+
55 
+
56  Object & operator[](int index)
+
57  { return m_objects[index]; }
+
58 
+
59  const Object& operator[](int index) const
+
60  { return m_objects[index]; }
+
61 
+
62  bool empty() const
+
63  { return size()==0; }
+
64 
+
65  int size() const
+
66  { return m_size; }
+
67 
+
68  int capacity() const
+
69  { return m_capacity; }
+
70 
+
71  const Object *data()
+
72  { return m_objects; }
+
73 
+
74  int push_back(const Object& x)
+
75  {
+
76  if(m_size == m_capacity)
+
77  if (resize(m_capacity + SPARE_CAPACITY)<0)
+
78  return -1;
+
79  m_objects[m_size++] = x;
+
80  return 0;
+
81  }
+
82 
+
83  void pop_back()
+
84  { m_size--; }
+
85 
+
86  void clear()
+
87  { m_size = 0; }
+
88 
+
89 private:
+
90  int m_size;
+
91  int m_capacity;
+
92  Object *m_objects;
+
93 };
+
94 
+
95 #endif // SIMPLEVECTOR_H
+
SimpleVector
Definition: simplevector.h:23
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/emulator_2libs_2_pixy_2src_2usblink_8h_source.html b/emulator_2libs_2_pixy_2src_2usblink_8h_source.html new file mode 100644 index 0000000..1701b21 --- /dev/null +++ b/emulator_2libs_2_pixy_2src_2usblink_8h_source.html @@ -0,0 +1,147 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/usblink.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usblink.h
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __USBLINK_H__
+
17 #define __USBLINK_H__
+
18 
+
19 #include "link.h"
+
20 #include "timer.hpp"
+
21 #include <libusb.h>
+
22 
+
23 class USBLink : public Link
+
24 {
+
25 public:
+
26  USBLink();
+
27  ~USBLink();
+
28 
+
29  int open();
+
30  virtual int send(const uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
31  virtual int receive(uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
32  virtual void setTimer();
+
33  virtual uint32_t getTimer();
+
34 
+
35 private:
+
36  libusb_context *m_context;
+
37  libusb_device_handle *m_handle;
+
38 
+
39  util::timer timer_;
+
40 };
+
41 
+
42 #endif
+
43 
+
util::timer
Definition: timer.hpp:25
+ + +
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/files.html b/files.html new file mode 100644 index 0000000..ac5a808 --- /dev/null +++ b/files.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: File List + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + +
+ +
+
+ + +
+ +
+ +
+
+
File List
+
+
+
Here is a list of all files with brief descriptions:
+
[detail level 123]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
 ▼ common
 ▼ app
 app.c
 app.h
 screen_filetest.c
 screen_filetest.h
 screen_guitest.c
 screen_guitest.h
 screen_main.c
 screen_main.h
 screen_pixytest.c
 screen_pixytest.h
 ▼ filesystem
 filesystem.c
 filesystem.h
 ▼ gui
 button.c
 button.h
 checkbox.c
 checkbox.h
 numupdown.c
 numupdown.h
 screen.c
 screen.h
 ▼ lowlevel
 ll_filesystem.h
 ll_system.h
 ll_tft.h
 ll_touch.h
 ▼ pixy
 pixy.h
 pixydefs.h
 ▼ system
 system.c
 system.h
 ▼ tft
 tft.c
 tft.h
 ▼ touch
 touch.c
 touch.h
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/filesystem_8c.html b/filesystem_8c.html new file mode 100644 index 0000000..cbb01bb --- /dev/null +++ b/filesystem_8c.html @@ -0,0 +1,443 @@ + + + + + + +discoverpixy: common/filesystem/filesystem.c File Reference + + + + + + + + + + +
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+Functions
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filesystem.c File Reference
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#include "filesystem.h"
+#include "ll_filesystem.h"
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+Functions

bool filesystem_init ()
 
DIRECTORY_STRUCT * filesystem_dir_open (const char *path)
 
void filesystem_dir_close (DIRECTORY_STRUCT *dir)
 
FILE_HANDLE * filesystem_file_open (const char *filename)
 
void filesystem_file_close (FILE_HANDLE *handle)
 
FILE_STATUS filesystem_file_seek (FILE_HANDLE *handle, uint32_t offset)
 
FILE_STATUS filesystem_file_read (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
FILE_STATUS filesystem_file_write (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
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Function Documentation

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void filesystem_dir_close (DIRECTORY_STRUCT * dir)
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DIRECTORY_STRUCT* filesystem_dir_open (const char * path)
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void filesystem_file_close (FILE_HANDLE * handle)
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FILE_HANDLE* filesystem_file_open (const char * filename)
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FILE_STATUS filesystem_file_read (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
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FILE_STATUS filesystem_file_seek (FILE_HANDLE * handle,
uint32_t offset 
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FILE_STATUS filesystem_file_write (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
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bool filesystem_init ()
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
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+ + +
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+
+Data Structures | +Enumerations | +Functions
+
+
filesystem.h File Reference
+
+
+
#include <stdbool.h>
+#include <stdint.h>
+
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Go to the source code of this file.

+ + + + + + + + + + + + +

+Data Structures

struct  FILE_DATE_STRUCT
 
struct  FILE_TIME_STRUCT
 
struct  FILE_STRUCT
 
struct  DIRECTORY_STRUCT
 
struct  FILE_HANDLE
 
+ + + + + +

+Enumerations

enum  FILE_ATTRIBUTES {
+  F_DIR =1, +F_RDO =2, +F_HID =4, +F_SYS =8, +
+  F_ARC =16 +
+ }
 
enum  FILE_STATUS {
+  F_OK, +F_EOF, +F_EACCESS, +F_INVALIDPARAM, +
+  F_DISKERROR +
+ }
 
+ + + + + + + + + + + + + + + + + +

+Functions

bool filesystem_init ()
 
DIRECTORY_STRUCT * filesystem_dir_open (const char *path)
 
void filesystem_dir_close (DIRECTORY_STRUCT *dir)
 
FILE_HANDLE * filesystem_file_open (const char *filename)
 
void filesystem_file_close (FILE_HANDLE *handle)
 
FILE_STATUS filesystem_file_seek (FILE_HANDLE *handle, uint32_t offset)
 
FILE_STATUS filesystem_file_read (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
FILE_STATUS filesystem_file_write (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum FILE_ATTRIBUTES
+
+ + + + + + +
Enumerator
F_DIR  +
F_RDO  +
F_HID  +
F_SYS  +
F_ARC  +
+ +
+
+ +
+
+ + + + +
enum FILE_STATUS
+
+ + + + + + +
Enumerator
F_OK  +
F_EOF  +
F_EACCESS  +
F_INVALIDPARAM  +
F_DISKERROR  +
+ +
+
+

Function Documentation

+ +
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+ + + + + + + + +
void filesystem_dir_close (DIRECTORY_STRUCT * dir)
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DIRECTORY_STRUCT* filesystem_dir_open (const char * path)
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void filesystem_file_close (FILE_HANDLE * handle)
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FILE_HANDLE* filesystem_file_open (const char * filename)
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FILE_STATUS filesystem_file_read (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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FILE_STATUS filesystem_file_seek (FILE_HANDLE * handle,
uint32_t offset 
)
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FILE_STATUS filesystem_file_write (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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bool filesystem_init ()
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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/dev/null +++ b/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.md5 b/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.md5 new file mode 100644 index 0000000..58509d5 --- /dev/null +++ b/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.md5 @@ -0,0 +1 @@ +29588fc279be29a10cefde38e37399cf \ No newline at end of file diff --git a/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.png b/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.png new file mode 100644 index 0000000..a9453a9 Binary files /dev/null and b/filesystem_8h_ae7124857f3ab32f6032ef129f2a80000_icgraph.png differ diff --git a/filesystem_8h_source.html b/filesystem_8h_source.html new file mode 100644 index 0000000..b6a7b7b --- /dev/null +++ b/filesystem_8h_source.html @@ -0,0 +1,207 @@ + + + + + + +discoverpixy: common/filesystem/filesystem.h Source File + + + + + + + + + + +
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filesystem.h
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+Go to the documentation of this file.
1 #ifndef FILESYSTEM_H
+
2 #define FILESYSTEM_H
+
3 
+
4 #include <stdbool.h>
+
5 #include <stdint.h>
+
6 
+
7 typedef enum {
+
8  F_DIR=1,
+
9  F_RDO=2,
+
10  F_HID=4,
+
11  F_SYS=8,
+
12  F_ARC=16
+
13 } FILE_ATTRIBUTES;
+
14 
+
15 
+
16 typedef struct {
+
17  unsigned year : 7; //year from 1980 (0..127)
+
18  unsigned month: 4; //month (1..12)
+
19  unsigned day: 5; //day (1..31)
+
20 } FILE_DATE_STRUCT;
+
21 
+
22 
+
23 typedef struct {
+
24  unsigned hour : 5; //hour (0..23)
+
25  unsigned min: 6; //minute (0..59
+
26  unsigned sec: 5; //second/2 (0..29)
+
27 } FILE_TIME_STRUCT;
+
28 
+
29 
+
30 typedef struct {
+
31  uint32_t fsize; /* File size */
+
32  FILE_DATE_STRUCT fdate; /* Last modified date */
+
33  FILE_TIME_STRUCT ftime; /* Last modified time */
+
34  uint8_t fattrib; /* Attribute */
+
35  char* fname; /* File name */
+
36 } FILE_STRUCT;
+
37 
+
38 typedef struct {
+
39  const char* path;
+
40  uint16_t num_files;
+
41  FILE_STRUCT* files;
+
42 } DIRECTORY_STRUCT;
+
43 
+
44 typedef struct {
+
45  const char* fname;
+
46  uint32_t fpos;
+
47  uint32_t fsize;
+
48 } FILE_HANDLE;
+
49 
+
50 typedef enum {
+
51  F_OK,
+
52  F_EOF,
+
53  F_EACCESS,
+
54  F_INVALIDPARAM,
+
55  F_DISKERROR
+
56 } FILE_STATUS;
+
57 
+
58 
+
59 bool filesystem_init();
+
60 
+
61 DIRECTORY_STRUCT* filesystem_dir_open(const char* path);
+
62 void filesystem_dir_close(DIRECTORY_STRUCT* dir);
+
63 FILE_HANDLE* filesystem_file_open(const char* filename);
+
64 void filesystem_file_close(FILE_HANDLE* handle);
+
65 FILE_STATUS filesystem_file_seek(FILE_HANDLE* handle, uint32_t offset);
+
66 FILE_STATUS filesystem_file_read(FILE_HANDLE* handle, uint8_t* buf, uint32_t size);
+
67 FILE_STATUS filesystem_file_write(FILE_HANDLE* handle, uint8_t* buf, uint32_t size);
+
68 
+
69 
+
70 #endif /* FILESYSTEM_H */
+
71 
+
F_EOF
Definition: filesystem.h:52
+
F_HID
Definition: filesystem.h:10
+
FILE_HANDLE::fsize
uint32_t fsize
Definition: filesystem.h:47
+
filesystem_file_close
void filesystem_file_close(FILE_HANDLE *handle)
Definition: filesystem.c:20
+
FILE_TIME_STRUCT
Definition: filesystem.h:23
+
FILE_STRUCT::fdate
FILE_DATE_STRUCT fdate
Definition: filesystem.h:32
+
F_ARC
Definition: filesystem.h:12
+
FILE_STRUCT::fattrib
uint8_t fattrib
Definition: filesystem.h:34
+
filesystem_file_seek
FILE_STATUS filesystem_file_seek(FILE_HANDLE *handle, uint32_t offset)
Definition: filesystem.c:24
+
FILE_HANDLE
Definition: filesystem.h:44
+
F_EACCESS
Definition: filesystem.h:53
+
filesystem_dir_close
void filesystem_dir_close(DIRECTORY_STRUCT *dir)
Definition: filesystem.c:12
+
F_INVALIDPARAM
Definition: filesystem.h:54
+
FILE_STATUS
FILE_STATUS
Definition: filesystem.h:50
+
FILE_ATTRIBUTES
FILE_ATTRIBUTES
Definition: filesystem.h:7
+
F_SYS
Definition: filesystem.h:11
+
filesystem_init
bool filesystem_init()
Definition: filesystem.c:4
+
FILE_STRUCT::fname
char * fname
Definition: filesystem.h:35
+
filesystem_dir_open
DIRECTORY_STRUCT * filesystem_dir_open(const char *path)
Definition: filesystem.c:8
+
DIRECTORY_STRUCT::num_files
uint16_t num_files
Definition: filesystem.h:40
+
F_DISKERROR
Definition: filesystem.h:55
+
DIRECTORY_STRUCT
Definition: filesystem.h:38
+
FILE_HANDLE::fpos
uint32_t fpos
Definition: filesystem.h:46
+
F_RDO
Definition: filesystem.h:9
+
DIRECTORY_STRUCT::path
const char * path
Definition: filesystem.h:39
+
DIRECTORY_STRUCT::files
FILE_STRUCT * files
Definition: filesystem.h:41
+
FILE_STRUCT
Definition: filesystem.h:30
+
F_DIR
Definition: filesystem.h:8
+
filesystem_file_read
FILE_STATUS filesystem_file_read(FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
Definition: filesystem.c:28
+
FILE_DATE_STRUCT
Definition: filesystem.h:16
+
filesystem_file_write
FILE_STATUS filesystem_file_write(FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
Definition: filesystem.c:32
+
FILE_HANDLE::fname
const char * fname
Definition: filesystem.h:45
+
filesystem_file_open
FILE_HANDLE * filesystem_file_open(const char *filename)
Definition: filesystem.c:16
+
FILE_STRUCT::ftime
FILE_TIME_STRUCT ftime
Definition: filesystem.h:33
+
FILE_STRUCT::fsize
uint32_t fsize
Definition: filesystem.h:31
+
F_OK
Definition: filesystem.h:51
+
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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Here is a list of all documented class members with links to the class documentation for each member:
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  • pixy_blocks_are_new() +: pixy.h +
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Consider the following example:

1 /*! Invisible class because of truncation */
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2 class Invisible { };
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3 
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4 /*! Truncated class, inheritance relation is hidden */
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5 class Truncated : public Invisible { };
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6 
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7 /* Class not documented with doxygen comments */
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8 class Undocumented { };
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9 
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10 /*! Class that is inherited using public inheritance */
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11 class PublicBase : public Truncated { };
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12 
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13 /*! A template class */
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14 template<class T> class Templ { };
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15 
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16 /*! Class that is inherited using protected inheritance */
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17 class ProtectedBase { };
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18 
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19 /*! Class that is inherited using private inheritance */
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20 class PrivateBase { };
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21 
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22 /*! Class that is used by the Inherited class */
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23 class Used { };
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24 
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25 /*! Super class that inherits a number of other classes */
+
26 class Inherited : public PublicBase,
+
27  protected ProtectedBase,
+
28  private PrivateBase,
+
29  public Undocumented,
+
30  public Templ<int>
+
31 {
+
32  private:
+
33  Used *m_usedClass;
+
34 };
+

This will result in the following graph:

+
+ +
+

The boxes in the above graph have the following meaning:

+
    +
  • +A filled gray box represents the struct or class for which the graph is generated.
    • +
  • +A box with a black border denotes a documented struct or class.
    • +
  • +A box with a grey border denotes an undocumented struct or class.
    • +
  • +A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.
    • +
+

The arrows have the following meaning:

+
    +
  • +A dark blue arrow is used to visualize a public inheritance relation between two classes.
    • +
  • +A dark green arrow is used for protected inheritance.
    • +
  • +A dark red arrow is used for private inheritance.
    • +
  • +A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
    • +
  • +A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.
    • +
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/graph_legend.md5 b/graph_legend.md5 new file mode 100644 index 0000000..a06ed05 --- /dev/null +++ b/graph_legend.md5 @@ -0,0 +1 @@ +387ff8eb65306fa251338d3c9bd7bfff \ No newline at end of file diff --git a/graph_legend.png b/graph_legend.png new file mode 100644 index 0000000..9a7865b Binary files /dev/null and b/graph_legend.png differ diff --git a/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.html b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.html new file mode 100644 index 0000000..016c9c7 --- /dev/null +++ b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.html @@ -0,0 +1,181 @@ + + + + + + +discoverpixy: __DEVICE_DEFINES_ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
__DEVICE_DEFINES_
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for __DEVICE_DEFINES_:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
 
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
 
+#define DSTS_ENUMSPD_LS_PHY_6MHZ   2
 
+#define DSTS_ENUMSPD_FS_PHY_48MHZ   3
 
+#define DCFG_FRAME_INTERVAL_80   0
 
+#define DCFG_FRAME_INTERVAL_85   1
 
+#define DCFG_FRAME_INTERVAL_90   2
 
+#define DCFG_FRAME_INTERVAL_95   3
 
+#define DEP0CTL_MPS_64   0
 
+#define DEP0CTL_MPS_32   1
 
+#define DEP0CTL_MPS_16   2
 
+#define DEP0CTL_MPS_8   3
 
+#define EP_SPEED_LOW   0
 
+#define EP_SPEED_FULL   1
 
+#define EP_SPEED_HIGH   2
 
+#define EP_TYPE_CTRL   0
 
+#define EP_TYPE_ISOC   1
 
+#define EP_TYPE_BULK   2
 
+#define EP_TYPE_INTR   3
 
+#define EP_TYPE_MSK   3
 
+#define STS_GOUT_NAK   1
 
+#define STS_DATA_UPDT   2
 
+#define STS_XFER_COMP   3
 
+#define STS_SETUP_COMP   4
 
+#define STS_SETUP_UPDT   6
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.map b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.map new file mode 100644 index 0000000..394d32b --- /dev/null +++ b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.md5 b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.md5 new file mode 100644 index 0000000..1735378 --- /dev/null +++ b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.md5 @@ -0,0 +1 @@ +3c53bf16f6586c10c1fc46c53fb28aca \ No newline at end of file diff --git a/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.png b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.png new file mode 100644 index 0000000..c9a334a Binary files /dev/null and b/group_______d_e_v_i_c_e___d_e_f_i_n_e_s__.png differ diff --git a/group_______h_o_s_t___d_e_f_i_n_e_s__.html b/group_______h_o_s_t___d_e_f_i_n_e_s__.html new file mode 100644 index 0000000..ff3a0c9 --- /dev/null +++ b/group_______h_o_s_t___d_e_f_i_n_e_s__.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: __HOST_DEFINES_ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
__HOST_DEFINES_
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for __HOST_DEFINES_:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define HC_PID_DATA0   0
 
+#define HC_PID_DATA2   1
 
+#define HC_PID_DATA1   2
 
+#define HC_PID_SETUP   3
 
+#define HPRT0_PRTSPD_HIGH_SPEED   0
 
+#define HPRT0_PRTSPD_FULL_SPEED   1
 
+#define HPRT0_PRTSPD_LOW_SPEED   2
 
+#define HCFG_30_60_MHZ   0
 
+#define HCFG_48_MHZ   1
 
+#define HCFG_6_MHZ   2
 
+#define HCCHAR_CTRL   0
 
+#define HCCHAR_ISOC   1
 
+#define HCCHAR_BULK   2
 
+#define HCCHAR_INTR   3
 
+#define MIN(a, b)   (((a) < (b)) ? (a) : (b))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______h_o_s_t___d_e_f_i_n_e_s__.map b/group_______h_o_s_t___d_e_f_i_n_e_s__.map new file mode 100644 index 0000000..d27121b --- /dev/null +++ b/group_______h_o_s_t___d_e_f_i_n_e_s__.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______h_o_s_t___d_e_f_i_n_e_s__.md5 b/group_______h_o_s_t___d_e_f_i_n_e_s__.md5 new file mode 100644 index 0000000..2465aaf --- /dev/null +++ b/group_______h_o_s_t___d_e_f_i_n_e_s__.md5 @@ -0,0 +1 @@ +e79a0e96f76bcf3f1e2a37c42a46e487 \ No newline at end of file diff --git a/group_______h_o_s_t___d_e_f_i_n_e_s__.png b/group_______h_o_s_t___d_e_f_i_n_e_s__.png new file mode 100644 index 0000000..db89d59 Binary files /dev/null and b/group_______h_o_s_t___d_e_f_i_n_e_s__.png differ diff --git a/group_______host___channel___specific___registers.html b/group_______host___channel___specific___registers.html new file mode 100644 index 0000000..783de0e --- /dev/null +++ b/group_______host___channel___specific___registers.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __Host_Channel_Specific_Registers + + + + + + + + + + +
+
+ + + + + + +
+
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+Classes | +Typedefs
+
+
__Host_Channel_Specific_Registers
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __Host_Channel_Specific_Registers:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_HC_REGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_HC_REGS USB_OTG_HC_REGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______host___channel___specific___registers.map b/group_______host___channel___specific___registers.map new file mode 100644 index 0000000..ee3b89f --- /dev/null +++ b/group_______host___channel___specific___registers.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______host___channel___specific___registers.md5 b/group_______host___channel___specific___registers.md5 new file mode 100644 index 0000000..4b4cd47 --- /dev/null +++ b/group_______host___channel___specific___registers.md5 @@ -0,0 +1 @@ +fe1b1e77732fbde8b54cddba465199bc \ No newline at end of file diff --git a/group_______host___channel___specific___registers.png b/group_______host___channel___specific___registers.png new file mode 100644 index 0000000..de04858 Binary files /dev/null and b/group_______host___channel___specific___registers.png differ diff --git a/group_______host___mode___register___structures.html b/group_______host___mode___register___structures.html new file mode 100644 index 0000000..8c13e93 --- /dev/null +++ b/group_______host___mode___register___structures.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __Host_Mode_Register_Structures + + + + + + + + + + +
+
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+Classes | +Typedefs
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+
__Host_Mode_Register_Structures
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __Host_Mode_Register_Structures:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_HREGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_HREGS USB_OTG_HREGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______host___mode___register___structures.map b/group_______host___mode___register___structures.map new file mode 100644 index 0000000..8603d1d --- /dev/null +++ b/group_______host___mode___register___structures.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______host___mode___register___structures.md5 b/group_______host___mode___register___structures.md5 new file mode 100644 index 0000000..7eaaeb5 --- /dev/null +++ b/group_______host___mode___register___structures.md5 @@ -0,0 +1 @@ +242fdde6eb4f81a688d5c1f4729fc245 \ No newline at end of file diff --git a/group_______host___mode___register___structures.png b/group_______host___mode___register___structures.png new file mode 100644 index 0000000..33bbd48 Binary files /dev/null and b/group_______host___mode___register___structures.png differ diff --git a/group_______i_n___endpoint-_specific___register.html b/group_______i_n___endpoint-_specific___register.html new file mode 100644 index 0000000..6569c8d --- /dev/null +++ b/group_______i_n___endpoint-_specific___register.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __IN_Endpoint-Specific_Register + + + + + + + + + + +
+
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+Classes | +Typedefs
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+
__IN_Endpoint-Specific_Register
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __IN_Endpoint-Specific_Register:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_INEPREGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_INEPREGS USB_OTG_INEPREGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______i_n___endpoint-_specific___register.map b/group_______i_n___endpoint-_specific___register.map new file mode 100644 index 0000000..874babe --- /dev/null +++ b/group_______i_n___endpoint-_specific___register.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______i_n___endpoint-_specific___register.md5 b/group_______i_n___endpoint-_specific___register.md5 new file mode 100644 index 0000000..a6eeea7 --- /dev/null +++ b/group_______i_n___endpoint-_specific___register.md5 @@ -0,0 +1 @@ +231b6e4441d07416d2abe6f0e8768a0d \ No newline at end of file diff --git a/group_______i_n___endpoint-_specific___register.png b/group_______i_n___endpoint-_specific___register.png new file mode 100644 index 0000000..a33f7e8 Binary files /dev/null and b/group_______i_n___endpoint-_specific___register.png differ diff --git a/group_______o_u_t___endpoint-_specific___registers.html b/group_______o_u_t___endpoint-_specific___registers.html new file mode 100644 index 0000000..17248c1 --- /dev/null +++ b/group_______o_u_t___endpoint-_specific___registers.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __OUT_Endpoint-Specific_Registers + + + + + + + + + + +
+
+ + + + + + +
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+ + +
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+Classes | +Typedefs
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+
__OUT_Endpoint-Specific_Registers
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __OUT_Endpoint-Specific_Registers:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_OUTEPREGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_OUTEPREGS USB_OTG_OUTEPREGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______o_u_t___endpoint-_specific___registers.map b/group_______o_u_t___endpoint-_specific___registers.map new file mode 100644 index 0000000..b49f8f6 --- /dev/null +++ b/group_______o_u_t___endpoint-_specific___registers.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______o_u_t___endpoint-_specific___registers.md5 b/group_______o_u_t___endpoint-_specific___registers.md5 new file mode 100644 index 0000000..d9b15b5 --- /dev/null +++ b/group_______o_u_t___endpoint-_specific___registers.md5 @@ -0,0 +1 @@ +7a7b0e0da3920dcfedbbb2bb2122baf7 \ No newline at end of file diff --git a/group_______o_u_t___endpoint-_specific___registers.png b/group_______o_u_t___endpoint-_specific___registers.png new file mode 100644 index 0000000..da86354 Binary files /dev/null and b/group_______o_u_t___endpoint-_specific___registers.png differ diff --git a/group_______u_s_b___o_t_g___core__register.html b/group_______u_s_b___o_t_g___core__register.html new file mode 100644 index 0000000..a38c5db --- /dev/null +++ b/group_______u_s_b___o_t_g___core__register.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __USB_OTG_Core_register + + + + + + + + + + +
+
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+Classes | +Typedefs
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__USB_OTG_Core_register
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __USB_OTG_Core_register:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_GREGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_GREGS USB_OTG_GREGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_______u_s_b___o_t_g___core__register.map b/group_______u_s_b___o_t_g___core__register.map new file mode 100644 index 0000000..da5f1bf --- /dev/null +++ b/group_______u_s_b___o_t_g___core__register.map @@ -0,0 +1,3 @@ + + + diff --git a/group_______u_s_b___o_t_g___core__register.md5 b/group_______u_s_b___o_t_g___core__register.md5 new file mode 100644 index 0000000..4e6c87e --- /dev/null +++ b/group_______u_s_b___o_t_g___core__register.md5 @@ -0,0 +1 @@ +ac730ce490551f923688722ad45add60 \ No newline at end of file diff --git a/group_______u_s_b___o_t_g___core__register.png b/group_______u_s_b___o_t_g___core__register.png new file mode 100644 index 0000000..29778c8 Binary files /dev/null and b/group_______u_s_b___o_t_g___core__register.png differ diff --git a/group______device___registers.html b/group______device___registers.html new file mode 100644 index 0000000..0bc0728 --- /dev/null +++ b/group______device___registers.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: __device_Registers + + + + + + + + + + +
+
+ + + + + + +
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+Classes | +Typedefs
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__device_Registers
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __device_Registers:
+
+
+ + +
+
+ + + + +

+Classes

struct  _USB_OTG_DREGS
 
+ + + +

+Typedefs

+typedef struct _USB_OTG_DREGS USB_OTG_DREGS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group______device___registers.map b/group______device___registers.map new file mode 100644 index 0000000..952c5d3 --- /dev/null +++ b/group______device___registers.map @@ -0,0 +1,3 @@ + + + diff --git a/group______device___registers.md5 b/group______device___registers.md5 new file mode 100644 index 0000000..0bb736a --- /dev/null +++ b/group______device___registers.md5 @@ -0,0 +1 @@ +94d1a525c4d4c1417602a3fbe62686a3 \ No newline at end of file diff --git a/group______device___registers.png b/group______device___registers.png new file mode 100644 index 0000000..0d9208d Binary files /dev/null and b/group______device___registers.png differ diff --git a/group______otg___core__registers.html b/group______otg___core__registers.html new file mode 100644 index 0000000..3193587 --- /dev/null +++ b/group______otg___core__registers.html @@ -0,0 +1,309 @@ + + + + + + +discoverpixy: __otg_Core_registers + + + + + + + + + + +
+
+ + + + + + +
+
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+Classes | +Typedefs
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+
__otg_Core_registers
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for __otg_Core_registers:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Classes

struct  USB_OTG_core_regs
 
union  _USB_OTG_OTGCTL_TypeDef
 
union  _USB_OTG_GOTGINT_TypeDef
 
union  _USB_OTG_GAHBCFG_TypeDef
 
union  _USB_OTG_GUSBCFG_TypeDef
 
union  _USB_OTG_GRSTCTL_TypeDef
 
union  _USB_OTG_GINTMSK_TypeDef
 
union  _USB_OTG_GINTSTS_TypeDef
 
union  _USB_OTG_DRXSTS_TypeDef
 
union  _USB_OTG_GRXSTS_TypeDef
 
union  _USB_OTG_FSIZ_TypeDef
 
union  _USB_OTG_HNPTXSTS_TypeDef
 
union  _USB_OTG_DTXFSTSn_TypeDef
 
union  _USB_OTG_GI2CCTL_TypeDef
 
union  _USB_OTG_GCCFG_TypeDef
 
union  _USB_OTG_DCFG_TypeDef
 
union  _USB_OTG_DCTL_TypeDef
 
union  _USB_OTG_DSTS_TypeDef
 
union  _USB_OTG_DIEPINTn_TypeDef
 
union  _USB_OTG_DOEPINTn_TypeDef
 
union  _USB_OTG_DAINT_TypeDef
 
union  _USB_OTG_DTHRCTL_TypeDef
 
union  _USB_OTG_DEPCTL_TypeDef
 
union  _USB_OTG_DEPXFRSIZ_TypeDef
 
union  _USB_OTG_DEP0XFRSIZ_TypeDef
 
union  _USB_OTG_HCFG_TypeDef
 
union  _USB_OTG_HFRMINTRVL_TypeDef
 
union  _USB_OTG_HFNUM_TypeDef
 
union  _USB_OTG_HPTXSTS_TypeDef
 
union  _USB_OTG_HPRT0_TypeDef
 
union  _USB_OTG_HAINT_TypeDef
 
union  _USB_OTG_HAINTMSK_TypeDef
 
union  _USB_OTG_HCCHAR_TypeDef
 
union  _USB_OTG_HCSPLT_TypeDef
 
union  _USB_OTG_HCINTn_TypeDef
 
union  _USB_OTG_HCTSIZn_TypeDef
 
union  _USB_OTG_HCGINTMSK_TypeDef
 
union  _USB_OTG_PCGCCTL_TypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

+typedef struct USB_OTG_core_regs USB_OTG_CORE_REGS
 
+typedef struct USB_OTG_core_regs * PUSB_OTG_CORE_REGS
 
+typedef union _USB_OTG_OTGCTL_TypeDef USB_OTG_OTGCTL_TypeDef
 
+typedef union _USB_OTG_GOTGINT_TypeDef USB_OTG_GOTGINT_TypeDef
 
+typedef union _USB_OTG_GAHBCFG_TypeDef USB_OTG_GAHBCFG_TypeDef
 
+typedef union _USB_OTG_GUSBCFG_TypeDef USB_OTG_GUSBCFG_TypeDef
 
+typedef union _USB_OTG_GRSTCTL_TypeDef USB_OTG_GRSTCTL_TypeDef
 
+typedef union _USB_OTG_GINTMSK_TypeDef USB_OTG_GINTMSK_TypeDef
 
+typedef union _USB_OTG_GINTSTS_TypeDef USB_OTG_GINTSTS_TypeDef
 
+typedef union _USB_OTG_DRXSTS_TypeDef USB_OTG_DRXSTS_TypeDef
 
+typedef union _USB_OTG_GRXSTS_TypeDef USB_OTG_GRXFSTS_TypeDef
 
+typedef union _USB_OTG_FSIZ_TypeDef USB_OTG_FSIZ_TypeDef
 
+typedef union _USB_OTG_HNPTXSTS_TypeDef USB_OTG_HNPTXSTS_TypeDef
 
+typedef union _USB_OTG_DTXFSTSn_TypeDef USB_OTG_DTXFSTSn_TypeDef
 
+typedef union _USB_OTG_GI2CCTL_TypeDef USB_OTG_GI2CCTL_TypeDef
 
+typedef union _USB_OTG_GCCFG_TypeDef USB_OTG_GCCFG_TypeDef
 
+typedef union _USB_OTG_DCFG_TypeDef USB_OTG_DCFG_TypeDef
 
+typedef union _USB_OTG_DCTL_TypeDef USB_OTG_DCTL_TypeDef
 
+typedef union _USB_OTG_DSTS_TypeDef USB_OTG_DSTS_TypeDef
 
+typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPINTn_TypeDef
 
+typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef
 
+typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPINTn_TypeDef
 
+typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef
 
+typedef union _USB_OTG_DAINT_TypeDef USB_OTG_DAINT_TypeDef
 
+typedef union _USB_OTG_DTHRCTL_TypeDef USB_OTG_DTHRCTL_TypeDef
 
+typedef union _USB_OTG_DEPCTL_TypeDef USB_OTG_DEPCTL_TypeDef
 
+typedef union _USB_OTG_DEPXFRSIZ_TypeDef USB_OTG_DEPXFRSIZ_TypeDef
 
+typedef union _USB_OTG_DEP0XFRSIZ_TypeDef USB_OTG_DEP0XFRSIZ_TypeDef
 
+typedef union _USB_OTG_HCFG_TypeDef USB_OTG_HCFG_TypeDef
 
+typedef union _USB_OTG_HFRMINTRVL_TypeDef USB_OTG_HFRMINTRVL_TypeDef
 
+typedef union _USB_OTG_HFNUM_TypeDef USB_OTG_HFNUM_TypeDef
 
+typedef union _USB_OTG_HPTXSTS_TypeDef USB_OTG_HPTXSTS_TypeDef
 
+typedef union _USB_OTG_HPRT0_TypeDef USB_OTG_HPRT0_TypeDef
 
+typedef union _USB_OTG_HAINT_TypeDef USB_OTG_HAINT_TypeDef
 
+typedef union _USB_OTG_HAINTMSK_TypeDef USB_OTG_HAINTMSK_TypeDef
 
+typedef union _USB_OTG_HCCHAR_TypeDef USB_OTG_HCCHAR_TypeDef
 
+typedef union _USB_OTG_HCSPLT_TypeDef USB_OTG_HCSPLT_TypeDef
 
+typedef union _USB_OTG_HCINTn_TypeDef USB_OTG_HCINTn_TypeDef
 
+typedef union _USB_OTG_HCTSIZn_TypeDef USB_OTG_HCTSIZn_TypeDef
 
+typedef union _USB_OTG_HCGINTMSK_TypeDef USB_OTG_HCGINTMSK_TypeDef
 
+typedef union _USB_OTG_PCGCCTL_TypeDef USB_OTG_PCGCCTL_TypeDef
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group______otg___core__registers.map b/group______otg___core__registers.map new file mode 100644 index 0000000..8032055 --- /dev/null +++ b/group______otg___core__registers.map @@ -0,0 +1,4 @@ + + + + diff --git a/group______otg___core__registers.md5 b/group______otg___core__registers.md5 new file mode 100644 index 0000000..90b3d85 --- /dev/null +++ b/group______otg___core__registers.md5 @@ -0,0 +1 @@ +f6147081ddc83dafb94de723d3fb7140 \ No newline at end of file diff --git a/group______otg___core__registers.png b/group______otg___core__registers.png new file mode 100644 index 0000000..7a89413 Binary files /dev/null and b/group______otg___core__registers.png differ diff --git a/group_____c_o_r_e___d_e_f_i_n_e_s__.html b/group_____c_o_r_e___d_e_f_i_n_e_s__.html new file mode 100644 index 0000000..7ed034a --- /dev/null +++ b/group_____c_o_r_e___d_e_f_i_n_e_s__.html @@ -0,0 +1,130 @@ + + + + + + +discoverpixy: _CORE_DEFINES_ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
_CORE_DEFINES_
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for _CORE_DEFINES_:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define USB_OTG_SPEED_PARAM_HIGH   0
 
+#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL   1
 
+#define USB_OTG_SPEED_PARAM_FULL   3
 
+#define USB_OTG_SPEED_HIGH   0
 
+#define USB_OTG_SPEED_FULL   1
 
+#define USB_OTG_ULPI_PHY   1
 
+#define USB_OTG_EMBEDDED_PHY   2
 
+#define USB_OTG_I2C_PHY   3
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_____c_o_r_e___d_e_f_i_n_e_s__.map b/group_____c_o_r_e___d_e_f_i_n_e_s__.map new file mode 100644 index 0000000..f2a16ba --- /dev/null +++ b/group_____c_o_r_e___d_e_f_i_n_e_s__.map @@ -0,0 +1,3 @@ + + + diff --git a/group_____c_o_r_e___d_e_f_i_n_e_s__.md5 b/group_____c_o_r_e___d_e_f_i_n_e_s__.md5 new file mode 100644 index 0000000..0f50630 --- /dev/null +++ b/group_____c_o_r_e___d_e_f_i_n_e_s__.md5 @@ -0,0 +1 @@ +dc4f3cad30f845a7f5cf2d16e3184853 \ No newline at end of file diff --git a/group_____c_o_r_e___d_e_f_i_n_e_s__.png b/group_____c_o_r_e___d_e_f_i_n_e_s__.png new file mode 100644 index 0000000..b4f1439 Binary files /dev/null and b/group_____c_o_r_e___d_e_f_i_n_e_s__.png differ diff --git a/group_____exported___variables.html b/group_____exported___variables.html new file mode 100644 index 0000000..fdb2aa5 --- /dev/null +++ b/group_____exported___variables.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: _Exported_Variables + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Variables
+
+
_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
+
+
+
+Collaboration diagram for _Exported_Variables:
+
+
+ + +
+
+ + + + +

+Variables

+MassStorageParameter_TypeDef USBH_MSC_Param
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_____exported___variables.map b/group_____exported___variables.map new file mode 100644 index 0000000..55ac933 --- /dev/null +++ b/group_____exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group_____exported___variables.md5 b/group_____exported___variables.md5 new file mode 100644 index 0000000..afe1ced --- /dev/null +++ b/group_____exported___variables.md5 @@ -0,0 +1 @@ +993db366106a56a60287916578fc9439 \ No newline at end of file diff --git a/group_____exported___variables.png b/group_____exported___variables.png new file mode 100644 index 0000000..e66fbca Binary files /dev/null and b/group_____exported___variables.png differ diff --git a/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.html b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.html new file mode 100644 index 0000000..94685d0 --- /dev/null +++ b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: _GLOBAL_DEFINES_ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
_GLOBAL_DEFINES_
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for _GLOBAL_DEFINES_:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define GAHBCFG_TXFEMPTYLVL_EMPTY   1
 
+#define GAHBCFG_TXFEMPTYLVL_EMPTY   1
 
+#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
 
+#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
 
+#define GAHBCFG_GLBINT_ENABLE   1
 
+#define GAHBCFG_INT_DMA_BURST_SINGLE   0
 
+#define GAHBCFG_INT_DMA_BURST_INCR   1
 
+#define GAHBCFG_INT_DMA_BURST_INCR4   3
 
+#define GAHBCFG_INT_DMA_BURST_INCR8   5
 
+#define GAHBCFG_INT_DMA_BURST_INCR16   7
 
+#define GAHBCFG_DMAENABLE   1
 
+#define GRXSTS_PKTSTS_IN   2
 
+#define GRXSTS_PKTSTS_IN_XFER_COMP   3
 
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR   5
 
+#define GRXSTS_PKTSTS_CH_HALTED   7
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.map b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.map new file mode 100644 index 0000000..8eab7e9 --- /dev/null +++ b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.map @@ -0,0 +1,3 @@ + + + diff --git a/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.md5 b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.md5 new file mode 100644 index 0000000..7712010 --- /dev/null +++ b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.md5 @@ -0,0 +1 @@ +7e8752ed4514c6289f600ceb0385068c \ No newline at end of file diff --git a/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.png b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.png new file mode 100644 index 0000000..2e306b1 Binary files /dev/null and b/group_____g_l_o_b_a_l___d_e_f_i_n_e_s__.png differ diff --git a/group_____on_the_go___d_e_f_i_n_e_s__.html b/group_____on_the_go___d_e_f_i_n_e_s__.html new file mode 100644 index 0000000..f295b68 --- /dev/null +++ b/group_____on_the_go___d_e_f_i_n_e_s__.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: _OnTheGo_DEFINES_ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
_OnTheGo_DEFINES_
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for _OnTheGo_DEFINES_:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MODE_HNP_SRP_CAPABLE   0
 
+#define MODE_SRP_ONLY_CAPABLE   1
 
+#define MODE_NO_HNP_SRP_CAPABLE   2
 
+#define MODE_SRP_CAPABLE_DEVICE   3
 
+#define MODE_NO_SRP_CAPABLE_DEVICE   4
 
+#define MODE_SRP_CAPABLE_HOST   5
 
+#define MODE_NO_SRP_CAPABLE_HOST   6
 
+#define A_HOST   1
 
+#define A_SUSPEND   2
 
+#define A_PERIPHERAL   3
 
+#define B_PERIPHERAL   4
 
+#define B_HOST   5
 
+#define DEVICE_MODE   0
 
+#define HOST_MODE   1
 
+#define OTG_MODE   2
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group_____on_the_go___d_e_f_i_n_e_s__.map b/group_____on_the_go___d_e_f_i_n_e_s__.map new file mode 100644 index 0000000..a272db0 --- /dev/null +++ b/group_____on_the_go___d_e_f_i_n_e_s__.map @@ -0,0 +1,3 @@ + + + diff --git a/group_____on_the_go___d_e_f_i_n_e_s__.md5 b/group_____on_the_go___d_e_f_i_n_e_s__.md5 new file mode 100644 index 0000000..5b26f8c --- /dev/null +++ b/group_____on_the_go___d_e_f_i_n_e_s__.md5 @@ -0,0 +1 @@ +e31f67f30668372824f0f3316fe6d231 \ No newline at end of file diff --git a/group_____on_the_go___d_e_f_i_n_e_s__.png b/group_____on_the_go___d_e_f_i_n_e_s__.png new file mode 100644 index 0000000..2244db2 Binary files /dev/null and b/group_____on_the_go___d_e_f_i_n_e_s__.png differ diff --git a/group___a_d_c.html b/group___a_d_c.html new file mode 100644 index 0000000..81123ed --- /dev/null +++ b/group___a_d_c.html @@ -0,0 +1,1949 @@ + + + + + + +discoverpixy: ADC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
ADC
STM32F4xx_StdPeriph_Driver
+
+
+ +

ADC driver modules. +More...

+
+Collaboration diagram for ADC:
+
+
+ + +
+
+ + + + + + +

+Modules

 ADC_Exported_Constants
 
 ADC_Private_Functions
 
+ + + + + + + +

+Classes

struct  ADC_InitTypeDef
 ADC Init structure definition. More...
 
struct  ADC_CommonInitTypeDef
 ADC Common Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define CR1_DISCNUM_RESET   ((uint32_t)0xFFFF1FFF)
 
+#define CR1_AWDCH_RESET   ((uint32_t)0xFFFFFFE0)
 
+#define CR1_AWDMode_RESET   ((uint32_t)0xFF3FFDFF)
 
+#define CR1_CLEAR_MASK   ((uint32_t)0xFCFFFEFF)
 
+#define CR2_EXTEN_RESET   ((uint32_t)0xCFFFFFFF)
 
+#define CR2_JEXTEN_RESET   ((uint32_t)0xFFCFFFFF)
 
+#define CR2_JEXTSEL_RESET   ((uint32_t)0xFFF0FFFF)
 
+#define CR2_CLEAR_MASK   ((uint32_t)0xC0FFF7FD)
 
+#define SQR3_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR2_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR1_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR1_L_RESET   ((uint32_t)0xFF0FFFFF)
 
+#define JSQR_JSQ_SET   ((uint32_t)0x0000001F)
 
+#define JSQR_JL_SET   ((uint32_t)0x00300000)
 
+#define JSQR_JL_RESET   ((uint32_t)0xFFCFFFFF)
 
+#define SMPR1_SMP_SET   ((uint32_t)0x00000007)
 
+#define SMPR2_SMP_SET   ((uint32_t)0x00000007)
 
+#define JDR_OFFSET   ((uint8_t)0x28)
 
+#define CDR_ADDRESS   ((uint32_t)0x40012308)
 
+#define CR_CLEAR_MASK   ((uint32_t)0xFFFC30E0)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_DeInit (void)
 Deinitializes all ADCs peripherals registers to their default reset values. More...
 
void ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
 Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct. More...
 
void ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
 Fills each ADC_InitStruct member with its default value. More...
 
void ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct. More...
 
void ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Fills each ADC_CommonInitStruct member with its default value. More...
 
void ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC peripheral. More...
 
void ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
 Enables or disables the analog watchdog on single/all regular or injected channels. More...
 
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
 Configures the high and low thresholds of the analog watchdog. More...
 
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
 Configures the analog watchdog guarded single channel. More...
 
void ADC_TempSensorVrefintCmd (FunctionalState NewState)
 Enables or disables the temperature sensor and Vrefint channels. More...
 
void ADC_VBATCmd (FunctionalState NewState)
 Enables or disables the VBAT (Voltage Battery) channel. More...
 
void ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the regular channels. More...
 
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start regular conversion Status. More...
 
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the EOC on each regular channel conversion. More...
 
void ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC continuous conversion mode. More...
 
void ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
 Configures the discontinuous mode for the selected ADC regular group channel. More...
 
void ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode on regular group channel for the specified ADC. More...
 
uint16_t ADC_GetConversionValue (ADC_TypeDef *ADCx)
 Returns the last ADCx conversion result data for regular channel. More...
 
uint32_t ADC_GetMultiModeConversionValue (void)
 Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode. More...
 
void ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC DMA request. More...
 
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer (Single-ADC mode) More...
 
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer in multi ADC mode. More...
 
void ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
 Configures the sequencer length for injected channels. More...
 
void ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
 Set the injected channels conversion value offset. More...
 
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
 Configures the ADCx external trigger for injected channels conversion. More...
 
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
 Configures the ADCx external trigger edge for injected channels conversion. More...
 
void ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the injected channels. More...
 
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start injected conversion Status. More...
 
void ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the selected ADC automatic injected group conversion after regular one. More...
 
void ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode for injected group channel for the specified ADC. More...
 
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
 Returns the ADC injected channel conversion result. More...
 
void ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
 Enables or disables the specified ADC interrupts. More...
 
FlagStatus ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Checks whether the specified ADC flag is set or not. More...
 
void ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Clears the ADCx's pending flags. More...
 
ITStatus ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Checks whether the specified ADC interrupt has occurred or not. More...
 
void ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Clears the ADCx's interrupt pending bits. More...
 
+

Detailed Description

+

ADC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogCmd (ADC_TypeDef * ADCx,
uint32_t ADC_AnalogWatchdog 
)
+
+ +

Enables or disables the analog watchdog on single/all regular or injected channels.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_AnalogWatchdogthe ADC analog watchdog configuration. This parameter can be one of the following values:
    +
  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
    • +
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
    • +
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
    • +
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
    • +
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
    • +
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
    • +
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel 
)
+
+ +

Configures the analog watchdog guarded single channel.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure for the analog watchdog. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef * ADCx,
uint16_t HighThreshold,
uint16_t LowThreshold 
)
+
+ +

Configures the high and low thresholds of the analog watchdog.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
HighThresholdthe ADC analog watchdog High threshold value. This parameter must be a 12-bit value.
LowThresholdthe ADC analog watchdog Low threshold value. This parameter must be a 12-bit value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AutoInjectedConvCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected ADC automatic injected group conversion after regular one.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC auto injected conversion This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ClearFlag (ADC_TypeDef * ADCx,
uint8_t ADC_FLAG 
)
+
+ +

Clears the ADCx's pending flags.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • ADC_FLAG_AWD: Analog watchdog flag
    • +
  • ADC_FLAG_EOC: End of conversion flag
    • +
  • ADC_FLAG_JEOC: End of injected group conversion flag
    • +
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
    • +
  • ADC_FLAG_STRT: Start of regular group conversion flag
    • +
  • ADC_FLAG_OVR: Overrun flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ClearITPendingBit (ADC_TypeDef * ADCx,
uint16_t ADC_IT 
)
+
+ +

Clears the ADCx's interrupt pending bits.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_Cmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC peripheral.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_CommonInit (ADC_CommonInitTypeDef * ADC_CommonInitStruct)
+
+ +

Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.

+
Parameters
+ + +
ADC_CommonInitStructpointer to an ADC_CommonInitTypeDef structure that contains the configuration information for All ADCs peripherals.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_CommonStructInit (ADC_CommonInitTypeDef * ADC_CommonInitStruct)
+
+ +

Fills each ADC_CommonInitStruct member with its default value.

+
Parameters
+ + +
ADC_CommonInitStructpointer to an ADC_CommonInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ContinuousModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the ADC continuous conversion mode.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC continuous conversion mode This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_DeInit (void )
+
+ +

Deinitializes all ADCs peripherals registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
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+

+ +
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void ADC_DiscModeChannelCountConfig (ADC_TypeDef * ADCx,
uint8_t Number 
)
+
+ +

Configures the discontinuous mode for the selected ADC regular group channel.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
Numberspecifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DiscModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DMACmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC DMA request.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the ADC DMA request after last transfer (Single-ADC mode)

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC DMA request after last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the EOC on each regular channel conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef * ADCx,
uint32_t ADC_ExternalTrigInjecConv 
)
+
+ +

Configures the ADCx external trigger for injected channels conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConvspecifies the ADC trigger to start injected conversion. This parameter can be one of the following values:
    +
  • ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
    • +
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef * ADCx,
uint32_t ADC_ExternalTrigInjecConvEdge 
)
+
+ +

Configures the ADCx external trigger edge for injected channels conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConvEdgespecifies the ADC external trigger edge to start injected conversion. This parameter can be one of the following values:
    +
  • ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for injected conversion
    • +
  • ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
    • +
  • ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
    • +
  • ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising and falling edge
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t ADC_GetConversionValue (ADC_TypeDef * ADCx)
+
+ +

Returns the last ADCx conversion result data for regular channel.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus ADC_GetFlagStatus (ADC_TypeDef * ADCx,
uint8_t ADC_FLAG 
)
+
+ +

Checks whether the specified ADC flag is set or not.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • ADC_FLAG_AWD: Analog watchdog flag
    • +
  • ADC_FLAG_EOC: End of conversion flag
    • +
  • ADC_FLAG_JEOC: End of injected group conversion flag
    • +
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
    • +
  • ADC_FLAG_STRT: Start of regular group conversion flag
    • +
  • ADC_FLAG_OVR: Overrun flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of ADC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef * ADCx,
uint8_t ADC_InjectedChannel 
)
+
+ +

Returns the ADC injected channel conversion result.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannelthe converted ADC injected channel. This parameter can be one of the following values:
    +
  • ADC_InjectedChannel_1: Injected Channel1 selected
    • +
  • ADC_InjectedChannel_2: Injected Channel2 selected
    • +
  • ADC_InjectedChannel_3: Injected Channel3 selected
    • +
  • ADC_InjectedChannel_4: Injected Channel4 selected
    • +
+
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus ADC_GetITStatus (ADC_TypeDef * ADCx,
uint16_t ADC_IT 
)
+
+ +

Checks whether the specified ADC interrupt has occurred or not.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt source to check. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of ADC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t ADC_GetMultiModeConversionValue (void )
+
+ +

Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+
Note
In dual mode, the value returned by this function is as following Data[15:0] : these bits contain the regular data of ADC1. Data[31:16]: these bits contain the regular data of ADC2.
+
+In triple mode, the value returned by this function is as following Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef * ADCx)
+
+ +

Gets the selected ADC Software start regular conversion Status.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
Thenew state of ADC software start conversion (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef * ADCx)
+
+ +

Gets the selected ADC Software start injected conversion Status.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
Thenew state of ADC software start injected conversion (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_Init (ADC_TypeDef * ADCx,
ADC_InitTypeDef * ADC_InitStruct 
)
+
+ +

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

+
Note
This function is used to configure the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InitStructpointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_InjectedChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel,
uint8_t Rank,
uint8_t ADC_SampleTime 
)
+
+ +

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

+
Parameters
+ + + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
RankThe rank in the injected group sequencer. This parameter must be between 1 to 4.
ADC_SampleTimeThe sample time value to be set for the selected channel. This parameter can be one of the following values:
    +
  • ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
    • +
  • ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
    • +
  • ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
    • +
  • ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
    • +
  • ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
    • +
  • ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
    • +
  • ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
    • +
  • ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_InjectedDiscModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef * ADCx,
uint8_t Length 
)
+
+ +

Configures the sequencer length for injected channels.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
LengthThe sequencer length. This parameter must be a number between 1 to 4.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_ITConfig (ADC_TypeDef * ADCx,
uint16_t ADC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC interrupts.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt enable
    • +
+
NewStatenew state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
+
+ +

Enables or disables the ADC DMA request after last transfer in multi ADC mode.

+
Parameters
+ + +
NewStatenew state of the selected ADC DMA request after last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
if Enabled, DMA requests are issued as long as data are converted and DMA mode for multi ADC mode (selected using ADC_CommonInit() function by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_RegularChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel,
uint8_t Rank,
uint8_t ADC_SampleTime 
)
+
+ +

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

+
Parameters
+ + + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
RankThe rank in the regular group sequencer. This parameter must be between 1 to 16.
ADC_SampleTimeThe sample time value to be set for the selected channel. This parameter can be one of the following values:
    +
  • ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
    • +
  • ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
    • +
  • ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
    • +
  • ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
    • +
  • ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
    • +
  • ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
    • +
  • ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
    • +
  • ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_SetInjectedOffset (ADC_TypeDef * ADCx,
uint8_t ADC_InjectedChannel,
uint16_t Offset 
)
+
+ +

Set the injected channels conversion value offset.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannelthe ADC injected channel to set its offset. This parameter can be one of the following values:
    +
  • ADC_InjectedChannel_1: Injected Channel1 selected
    • +
  • ADC_InjectedChannel_2: Injected Channel2 selected
    • +
  • ADC_InjectedChannel_3: Injected Channel3 selected
    • +
  • ADC_InjectedChannel_4: Injected Channel4 selected
    • +
+
Offsetthe offset value for the selected ADC injected channel This parameter must be a 12bit value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_SoftwareStartConv (ADC_TypeDef * ADCx)
+
+ +

Enables the selected ADC software start conversion of the regular channels.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_SoftwareStartInjectedConv (ADC_TypeDef * ADCx)
+
+ +

Enables the selected ADC software start conversion of the injected channels.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_StructInit (ADC_InitTypeDef * ADC_InitStruct)
+
+ +

Fills each ADC_InitStruct member with its default value.

+
Note
This function is used to initialize the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
+
Parameters
+ + +
ADC_InitStructpointer to an ADC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_TempSensorVrefintCmd (FunctionalState NewState)
+
+ +

Enables or disables the temperature sensor and Vrefint channels.

+
Parameters
+ + +
NewStatenew state of the temperature sensor and Vrefint channels. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_VBATCmd (FunctionalState NewState)
+
+ +

Enables or disables the VBAT (Voltage Battery) channel.

+
Note
the Battery voltage measured is equal to VBAT/2 on STM32F40xx and STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
+
Parameters
+ + +
NewStatenew state of the VBAT channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c.map b/group___a_d_c.map new file mode 100644 index 0000000..4bd73de --- /dev/null +++ b/group___a_d_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___a_d_c.md5 b/group___a_d_c.md5 new file mode 100644 index 0000000..672609a --- /dev/null +++ b/group___a_d_c.md5 @@ -0,0 +1 @@ +23a438dea2e12c8e0dee1621937c1990 \ No newline at end of file diff --git a/group___a_d_c.png b/group___a_d_c.png new file mode 100644 index 0000000..e72c793 Binary files /dev/null and b/group___a_d_c.png differ diff --git a/group___a_d_c___common__mode.html b/group___a_d_c___common__mode.html new file mode 100644 index 0000000..3b19e25 --- /dev/null +++ b/group___a_d_c___common__mode.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: ADC_Common_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_Common_mode
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_Common_mode:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_Mode_Independent   ((uint32_t)0x00000000)
 
+#define ADC_DualMode_RegSimult_InjecSimult   ((uint32_t)0x00000001)
 
+#define ADC_DualMode_RegSimult_AlterTrig   ((uint32_t)0x00000002)
 
+#define ADC_DualMode_InjecSimult   ((uint32_t)0x00000005)
 
+#define ADC_DualMode_RegSimult   ((uint32_t)0x00000006)
 
+#define ADC_DualMode_Interl   ((uint32_t)0x00000007)
 
+#define ADC_DualMode_AlterTrig   ((uint32_t)0x00000009)
 
+#define ADC_TripleMode_RegSimult_InjecSimult   ((uint32_t)0x00000011)
 
+#define ADC_TripleMode_RegSimult_AlterTrig   ((uint32_t)0x00000012)
 
+#define ADC_TripleMode_InjecSimult   ((uint32_t)0x00000015)
 
+#define ADC_TripleMode_RegSimult   ((uint32_t)0x00000016)
 
+#define ADC_TripleMode_Interl   ((uint32_t)0x00000017)
 
+#define ADC_TripleMode_AlterTrig   ((uint32_t)0x00000019)
 
#define IS_ADC_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_MODE( MODE)
+
+Value:
(((MODE) == ADC_Mode_Independent) || \
+
((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+
((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+
((MODE) == ADC_DualMode_InjecSimult) || \
+
((MODE) == ADC_DualMode_RegSimult) || \
+
((MODE) == ADC_DualMode_Interl) || \
+
((MODE) == ADC_DualMode_AlterTrig) || \
+
((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+
((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+
((MODE) == ADC_TripleMode_InjecSimult) || \
+
((MODE) == ADC_TripleMode_RegSimult) || \
+
((MODE) == ADC_TripleMode_Interl) || \
+
((MODE) == ADC_TripleMode_AlterTrig))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___common__mode.map b/group___a_d_c___common__mode.map new file mode 100644 index 0000000..b3fee1d --- /dev/null +++ b/group___a_d_c___common__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___common__mode.md5 b/group___a_d_c___common__mode.md5 new file mode 100644 index 0000000..7bc40d3 --- /dev/null +++ b/group___a_d_c___common__mode.md5 @@ -0,0 +1 @@ +538f2118da1dad0842422b710f3269db \ No newline at end of file diff --git a/group___a_d_c___common__mode.png b/group___a_d_c___common__mode.png new file mode 100644 index 0000000..68933a0 Binary files /dev/null and b/group___a_d_c___common__mode.png differ diff --git a/group___a_d_c___direct__memory__access__mode__for__multi__mode.html b/group___a_d_c___direct__memory__access__mode__for__multi__mode.html new file mode 100644 index 0000000..9cca643 --- /dev/null +++ b/group___a_d_c___direct__memory__access__mode__for__multi__mode.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_Direct_memory_access_mode_for_multi_mode + + + + + + + + + + +
+
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+Macros
+
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ADC_Direct_memory_access_mode_for_multi_mode
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_Direct_memory_access_mode_for_multi_mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_DMAAccessMode_Disabled   ((uint32_t)0x00000000) /* DMA mode disabled */
 
+#define ADC_DMAAccessMode_1   ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
 
+#define ADC_DMAAccessMode_2   ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
 
+#define ADC_DMAAccessMode_3   ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
 
#define IS_ADC_DMA_ACCESS_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_DMA_ACCESS_MODE( MODE)
+
+Value:
(((MODE) == ADC_DMAAccessMode_Disabled) || \
+
((MODE) == ADC_DMAAccessMode_1) || \
+
((MODE) == ADC_DMAAccessMode_2) || \
+
((MODE) == ADC_DMAAccessMode_3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___direct__memory__access__mode__for__multi__mode.map b/group___a_d_c___direct__memory__access__mode__for__multi__mode.map new file mode 100644 index 0000000..dbb800d --- /dev/null +++ b/group___a_d_c___direct__memory__access__mode__for__multi__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___direct__memory__access__mode__for__multi__mode.md5 b/group___a_d_c___direct__memory__access__mode__for__multi__mode.md5 new file mode 100644 index 0000000..e13c345 --- /dev/null +++ b/group___a_d_c___direct__memory__access__mode__for__multi__mode.md5 @@ -0,0 +1 @@ +e3e3cfe363402c92cefe461fc28a9e34 \ No newline at end of file diff --git a/group___a_d_c___direct__memory__access__mode__for__multi__mode.png b/group___a_d_c___direct__memory__access__mode__for__multi__mode.png new file mode 100644 index 0000000..b113ac8 Binary files /dev/null and b/group___a_d_c___direct__memory__access__mode__for__multi__mode.png differ diff --git a/group___a_d_c___exported___constants.html b/group___a_d_c___exported___constants.html new file mode 100644 index 0000000..41c1419 --- /dev/null +++ b/group___a_d_c___exported___constants.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: ADC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
ADC_Exported_Constants
STM32F4xx_StdPeriph_Driver » ADC
+
+
+
+Collaboration diagram for ADC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 ADC_Common_mode
 
 ADC_Prescaler
 
 ADC_Direct_memory_access_mode_for_multi_mode
 
 ADC_delay_between_2_sampling_phases
 
 ADC_resolution
 
 ADC_external_trigger_edge_for_regular_channels_conversion
 
 ADC_extrenal_trigger_sources_for_regular_channels_conversion
 
 ADC_data_align
 
 ADC_channels
 
 ADC_sampling_times
 
 ADC_external_trigger_edge_for_injected_channels_conversion
 
 ADC_extrenal_trigger_sources_for_injected_channels_conversion
 
 ADC_injected_channel_selection
 
 ADC_analog_watchdog_selection
 
 ADC_interrupts_definition
 
 ADC_flags_definition
 
 ADC_thresholds
 
 ADC_injected_offset
 
 ADC_injected_length
 
 ADC_injected_rank
 
 ADC_regular_length
 
 ADC_regular_rank
 
 ADC_regular_discontinuous_mode_number
 
+ + + +

+Macros

#define IS_ADC_ALL_PERIPH(PERIPH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == ADC1) || \
+
((PERIPH) == ADC2) || \
+
((PERIPH) == ADC3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___exported___constants.map b/group___a_d_c___exported___constants.map new file mode 100644 index 0000000..0ccc3c9 --- /dev/null +++ b/group___a_d_c___exported___constants.map @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___a_d_c___exported___constants.md5 b/group___a_d_c___exported___constants.md5 new file mode 100644 index 0000000..17de70a --- /dev/null +++ b/group___a_d_c___exported___constants.md5 @@ -0,0 +1 @@ +72ed94febb1dd704c428bf07b508232c \ No newline at end of file diff --git a/group___a_d_c___exported___constants.png b/group___a_d_c___exported___constants.png new file mode 100644 index 0000000..edc85d7 Binary files /dev/null and b/group___a_d_c___exported___constants.png differ diff --git a/group___a_d_c___group1.html b/group___a_d_c___group1.html new file mode 100644 index 0000000..88bd017 --- /dev/null +++ b/group___a_d_c___group1.html @@ -0,0 +1,359 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_DeInit (void)
 Deinitializes all ADCs peripherals registers to their default reset values. More...
 
void ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
 Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct. More...
 
void ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
 Fills each ADC_InitStruct member with its default value. More...
 
void ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct. More...
 
void ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Fills each ADC_CommonInitStruct member with its default value. More...
 
void ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC peripheral. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC Prescaler
+      (+) ADC Conversion Resolution (12bit..6bit)
+      (+) Scan Conversion Mode (multichannel or one channel) for regular group
+      (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for 
+          regular group
+      (+) External trigger Edge and source of regular group, 
+      (+) Converted data alignment (left or right)
+      (+) The number of ADC conversions that will be done using the sequencer for 
+          regular channel group
+      (+) Multi ADC mode selection
+      (+) Direct memory access mode selection for multi ADC mode  
+      (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
+      (+) Enable or disable the ADC peripheral   
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_Cmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC peripheral.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the ADCx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_CommonInit (ADC_CommonInitTypeDef * ADC_CommonInitStruct)
+
+ +

Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.

+
Parameters
+ + +
ADC_CommonInitStructpointer to an ADC_CommonInitTypeDef structure that contains the configuration information for All ADCs peripherals.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_CommonStructInit (ADC_CommonInitTypeDef * ADC_CommonInitStruct)
+
+ +

Fills each ADC_CommonInitStruct member with its default value.

+
Parameters
+ + +
ADC_CommonInitStructpointer to an ADC_CommonInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_DeInit (void )
+
+ +

Deinitializes all ADCs peripherals registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_Init (ADC_TypeDef * ADCx,
ADC_InitTypeDef * ADC_InitStruct 
)
+
+ +

Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.

+
Note
This function is used to configure the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InitStructpointer to an ADC_InitTypeDef structure that contains the configuration information for the specified ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_StructInit (ADC_InitTypeDef * ADC_InitStruct)
+
+ +

Fills each ADC_InitStruct member with its default value.

+
Note
This function is used to initialize the global features of the ADC ( Resolution and Data Alignment), however, the rest of the configuration parameters are specific to the regular channels group (scan mode activation, continuous mode activation, External trigger source and edge, number of conversion in the regular channels group sequencer).
+
Parameters
+ + +
ADC_InitStructpointer to an ADC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group1.map b/group___a_d_c___group1.map new file mode 100644 index 0000000..967cacd --- /dev/null +++ b/group___a_d_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group1.md5 b/group___a_d_c___group1.md5 new file mode 100644 index 0000000..a94f669 --- /dev/null +++ b/group___a_d_c___group1.md5 @@ -0,0 +1 @@ +b6d1575524b9994faa6b6e463be26a4e \ No newline at end of file diff --git a/group___a_d_c___group1.png b/group___a_d_c___group1.png new file mode 100644 index 0000000..b22b18d Binary files /dev/null and b/group___a_d_c___group1.png differ diff --git a/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map new file mode 100644 index 0000000..63d006d --- /dev/null +++ b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 new file mode 100644 index 0000000..5fb1c4c --- /dev/null +++ b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 @@ -0,0 +1 @@ +d1d3cc26df948442611015cc2613c627 \ No newline at end of file diff --git a/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png new file mode 100644 index 0000000..4d539fd Binary files /dev/null and b/group___a_d_c___group1_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png differ diff --git a/group___a_d_c___group2.html b/group___a_d_c___group2.html new file mode 100644 index 0000000..a978d88 --- /dev/null +++ b/group___a_d_c___group2.html @@ -0,0 +1,293 @@ + + + + + + +discoverpixy: Analog Watchdog configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ +
+
+ + +
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+ +
+
+Functions
+
+
Analog Watchdog configuration functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Analog Watchdog configuration functions. +More...

+
+Collaboration diagram for Analog Watchdog configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
 Enables or disables the analog watchdog on single/all regular or injected channels. More...
 
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
 Configures the high and low thresholds of the analog watchdog. More...
 
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
 Configures the analog watchdog guarded single channel. More...
 
+

Detailed Description

+

Analog Watchdog configuration functions.

+
 ===============================================================================
+             ##### Analog Watchdog configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the Analog Watchdog
+         (AWD) feature in the ADC.
+  
+    [..] A typical configuration Analog Watchdog is done following these steps :
+      (#) the ADC guarded channel(s) is (are) selected using the 
+          ADC_AnalogWatchdogSingleChannelConfig() function.
+      (#) The Analog watchdog lower and higher threshold are configured using the  
+          ADC_AnalogWatchdogThresholdsConfig() function.
+      (#) The Analog watchdog is enabled and configured to enable the check, on one
+          or more channels, using the  ADC_AnalogWatchdogCmd() function.
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogCmd (ADC_TypeDef * ADCx,
uint32_t ADC_AnalogWatchdog 
)
+
+ +

Enables or disables the analog watchdog on single/all regular or injected channels.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_AnalogWatchdogthe ADC analog watchdog configuration. This parameter can be one of the following values:
    +
  • ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
    • +
  • ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
    • +
  • ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
    • +
  • ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
    • +
  • ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
    • +
  • ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
    • +
  • ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel 
)
+
+ +

Configures the analog watchdog guarded single channel.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure for the analog watchdog. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef * ADCx,
uint16_t HighThreshold,
uint16_t LowThreshold 
)
+
+ +

Configures the high and low thresholds of the analog watchdog.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
HighThresholdthe ADC analog watchdog High threshold value. This parameter must be a 12-bit value.
LowThresholdthe ADC analog watchdog Low threshold value. This parameter must be a 12-bit value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group2.map b/group___a_d_c___group2.map new file mode 100644 index 0000000..596ce23 --- /dev/null +++ b/group___a_d_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group2.md5 b/group___a_d_c___group2.md5 new file mode 100644 index 0000000..64026f4 --- /dev/null +++ b/group___a_d_c___group2.md5 @@ -0,0 +1 @@ +4b6c5a96be8d135c20984990ad28011b \ No newline at end of file diff --git a/group___a_d_c___group2.png b/group___a_d_c___group2.png new file mode 100644 index 0000000..dfa792f Binary files /dev/null and b/group___a_d_c___group2.png differ diff --git a/group___a_d_c___group3.html b/group___a_d_c___group3.html new file mode 100644 index 0000000..9038110 --- /dev/null +++ b/group___a_d_c___group3.html @@ -0,0 +1,201 @@ + + + + + + +discoverpixy: Temperature Sensor, Vrefint (Voltage Reference internal) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Temperature Sensor, Vrefint (Voltage Reference internal)
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Temperature Sensor, Vrefint and VBAT management functions. +More...

+
+Collaboration diagram for Temperature Sensor, Vrefint (Voltage Reference internal):
+
+
+ + +
+
+ + + + + + + + +

+Functions

void ADC_TempSensorVrefintCmd (FunctionalState NewState)
 Enables or disables the temperature sensor and Vrefint channels. More...
 
void ADC_VBATCmd (FunctionalState NewState)
 Enables or disables the VBAT (Voltage Battery) channel. More...
 
+

Detailed Description

+

Temperature Sensor, Vrefint and VBAT management functions.

+

and VBAT (Voltage BATtery) management functions 

 ===============================================================================
+      ##### Temperature Sensor, Vrefint and VBAT management functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to enable/ disable the internal 
+         connections between the ADC and the Temperature Sensor, the Vrefint and 
+         the Vbat sources.
+     
+    [..] A typical configuration to get the Temperature sensor and Vrefint channels 
+         voltages is done following these steps :
+      (#) Enable the internal connection of Temperature sensor and Vrefint sources 
+          with the ADC channels using ADC_TempSensorVrefintCmd() function. 
+      (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using 
+          ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions 
+      (#) Get the voltage values, using ADC_GetConversionValue() or  
+          ADC_GetInjectedConversionValue().
+
+    [..] A typical configuration to get the VBAT channel voltage is done following 
+         these steps :
+      (#) Enable the internal connection of VBAT source with the ADC channel using 
+          ADC_VBATCmd() function. 
+      (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or  
+          ADC_InjectedChannelConfig() functions 
+      (#) Get the voltage value, using ADC_GetConversionValue() or  
+          ADC_GetInjectedConversionValue().

Function Documentation

+ +
+
+ + + + + + + + +
void ADC_TempSensorVrefintCmd (FunctionalState NewState)
+
+ +

Enables or disables the temperature sensor and Vrefint channels.

+
Parameters
+ + +
NewStatenew state of the temperature sensor and Vrefint channels. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_VBATCmd (FunctionalState NewState)
+
+ +

Enables or disables the VBAT (Voltage Battery) channel.

+
Note
the Battery voltage measured is equal to VBAT/2 on STM32F40xx and STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
+
Parameters
+ + +
NewStatenew state of the VBAT channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group3.map b/group___a_d_c___group3.map new file mode 100644 index 0000000..b59e877 --- /dev/null +++ b/group___a_d_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group3.md5 b/group___a_d_c___group3.md5 new file mode 100644 index 0000000..91dea91 --- /dev/null +++ b/group___a_d_c___group3.md5 @@ -0,0 +1 @@ +b25e6af0018b9a449123dcf8f3c51208 \ No newline at end of file diff --git a/group___a_d_c___group3.png b/group___a_d_c___group3.png new file mode 100644 index 0000000..6976f07 Binary files /dev/null and b/group___a_d_c___group3.png differ diff --git a/group___a_d_c___group4.html b/group___a_d_c___group4.html new file mode 100644 index 0000000..0c4e6a6 --- /dev/null +++ b/group___a_d_c___group4.html @@ -0,0 +1,543 @@ + + + + + + +discoverpixy: Regular Channels Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Regular Channels Configuration functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Regular Channels Configuration functions. +More...

+
+Collaboration diagram for Regular Channels Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the regular channels. More...
 
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start regular conversion Status. More...
 
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the EOC on each regular channel conversion. More...
 
void ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC continuous conversion mode. More...
 
void ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
 Configures the discontinuous mode for the selected ADC regular group channel. More...
 
void ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode on regular group channel for the specified ADC. More...
 
uint16_t ADC_GetConversionValue (ADC_TypeDef *ADCx)
 Returns the last ADCx conversion result data for regular channel. More...
 
uint32_t ADC_GetMultiModeConversionValue (void)
 Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode. More...
 
+

Detailed Description

+

Regular Channels Configuration functions.

+
 ===============================================================================
+             ##### Regular Channels Configuration functions #####
+ ===============================================================================  
+
+    [..] This section provides functions allowing to manage the ADC's regular channels,
+         it is composed of 2 sub sections : 
+  
+      (#) Configuration and management functions for regular channels: This subsection 
+          provides functions allowing to configure the ADC regular channels :    
+         (++) Configure the rank in the regular group sequencer for each channel
+         (++) Configure the sampling time for each channel
+         (++) select the conversion Trigger for regular channels
+         (++) select the desired EOC event behavior configuration
+         (++) Activate the continuous Mode  (*)
+         (++) Activate the Discontinuous Mode 
+         -@@- Please Note that the following features for regular channels 
+             are configurated using the ADC_Init() function : 
+           (+@@) scan mode activation 
+           (+@@) continuous mode activation (**) 
+           (+@@) External trigger source  
+           (+@@) External trigger edge 
+           (+@@) number of conversion in the regular channels group sequencer.
+     
+         -@@- (*) and (**) are performing the same configuration
+     
+      (#) Get the conversion data: This subsection provides an important function in 
+          the ADC peripheral since it returns the converted data of the current 
+          regular channel. When the Conversion value is read, the EOC Flag is 
+          automatically cleared.
+     
+          -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions 
+              results data (in the selected multi mode) can be returned in the same 
+              time using ADC_GetMultiModeConversionValue() function.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ContinuousModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the ADC continuous conversion mode.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC continuous conversion mode This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DiscModeChannelCountConfig (ADC_TypeDef * ADCx,
uint8_t Number 
)
+
+ +

Configures the discontinuous mode for the selected ADC regular group channel.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
Numberspecifies the discontinuous mode regular channel count value. This number must be between 1 and 8.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DiscModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the discontinuous mode on regular group channel for the specified ADC.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC discontinuous mode on regular group channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the EOC on each regular channel conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC EOC flag rising This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t ADC_GetConversionValue (ADC_TypeDef * ADCx)
+
+ +

Returns the last ADCx conversion result data for regular channel.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t ADC_GetMultiModeConversionValue (void )
+
+ +

Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+
Note
In dual mode, the value returned by this function is as following Data[15:0] : these bits contain the regular data of ADC1. Data[31:16]: these bits contain the regular data of ADC2.
+
+In triple mode, the value returned by this function is as following Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef * ADCx)
+
+ +

Gets the selected ADC Software start regular conversion Status.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
Thenew state of ADC software start conversion (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_RegularChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel,
uint8_t Rank,
uint8_t ADC_SampleTime 
)
+
+ +

Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.

+
Parameters
+ + + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
RankThe rank in the regular group sequencer. This parameter must be between 1 to 16.
ADC_SampleTimeThe sample time value to be set for the selected channel. This parameter can be one of the following values:
    +
  • ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
    • +
  • ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
    • +
  • ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
    • +
  • ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
    • +
  • ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
    • +
  • ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
    • +
  • ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
    • +
  • ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_SoftwareStartConv (ADC_TypeDef * ADCx)
+
+ +

Enables the selected ADC software start conversion of the regular channels.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group4.map b/group___a_d_c___group4.map new file mode 100644 index 0000000..5981bec --- /dev/null +++ b/group___a_d_c___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group4.md5 b/group___a_d_c___group4.md5 new file mode 100644 index 0000000..7580f14 --- /dev/null +++ b/group___a_d_c___group4.md5 @@ -0,0 +1 @@ +4f4553dd376327f79f5aad2669fab48b \ No newline at end of file diff --git a/group___a_d_c___group4.png b/group___a_d_c___group4.png new file mode 100644 index 0000000..3d40716 Binary files /dev/null and b/group___a_d_c___group4.png differ diff --git a/group___a_d_c___group5.html b/group___a_d_c___group5.html new file mode 100644 index 0000000..f515990 --- /dev/null +++ b/group___a_d_c___group5.html @@ -0,0 +1,253 @@ + + + + + + +discoverpixy: Regular Channels DMA Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Functions
+
+
Regular Channels DMA Configuration functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Regular Channels DMA Configuration functions. +More...

+
+Collaboration diagram for Regular Channels DMA Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC DMA request. More...
 
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer (Single-ADC mode) More...
 
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer in multi ADC mode. More...
 
+

Detailed Description

+

Regular Channels DMA Configuration functions.

+
 ===============================================================================
+            ##### Regular Channels DMA Configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to configure the DMA for ADC 
+         regular channels.
+         Since converted regular channel values are stored into a unique data 
+         register, it is useful to use DMA for conversion of more than one regular 
+         channel. This avoids the loss of the data already stored in the ADC 
+         Data register.   
+         When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+         conversion of a regular channel, a DMA request is generated.
+    [..] Depending on the "DMA disable selection for Independent ADC mode" 
+         configuration (using the ADC_DMARequestAfterLastTransferCmd() function), 
+         at the end of the last DMA transfer, two possibilities are allowed:
+      (+) No new DMA request is issued to the DMA controller (feature DISABLED) 
+      (+) Requests can continue to be generated (feature ENABLED).  
+    [..] Depending on the "DMA disable selection for multi ADC mode" configuration 
+         (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), 
+         at the end of the last DMA transfer, two possibilities are allowed:
+        (+) No new DMA request is issued to the DMA controller (feature DISABLED) 
+        (+) Requests can continue to be generated (feature ENABLED).

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DMACmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC DMA request.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC DMA transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the ADC DMA request after last transfer (Single-ADC mode)

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC DMA request after last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
+
+ +

Enables or disables the ADC DMA request after last transfer in multi ADC mode.

+
Parameters
+ + +
NewStatenew state of the selected ADC DMA request after last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
if Enabled, DMA requests are issued as long as data are converted and DMA mode for multi ADC mode (selected using ADC_CommonInit() function by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group5.map b/group___a_d_c___group5.map new file mode 100644 index 0000000..0e291eb --- /dev/null +++ b/group___a_d_c___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group5.md5 b/group___a_d_c___group5.md5 new file mode 100644 index 0000000..cffe35e --- /dev/null +++ b/group___a_d_c___group5.md5 @@ -0,0 +1 @@ +df2551ee1ea50eeea70f2e50cc577300 \ No newline at end of file diff --git a/group___a_d_c___group5.png b/group___a_d_c___group5.png new file mode 100644 index 0000000..976c531 Binary files /dev/null and b/group___a_d_c___group5.png differ diff --git a/group___a_d_c___group6.html b/group___a_d_c___group6.html new file mode 100644 index 0000000..a14aac9 --- /dev/null +++ b/group___a_d_c___group6.html @@ -0,0 +1,637 @@ + + + + + + +discoverpixy: Injected channels Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Injected channels Configuration functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Injected channels Configuration functions. +More...

+
+Collaboration diagram for Injected channels Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
 Configures the sequencer length for injected channels. More...
 
void ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
 Set the injected channels conversion value offset. More...
 
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
 Configures the ADCx external trigger for injected channels conversion. More...
 
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
 Configures the ADCx external trigger edge for injected channels conversion. More...
 
void ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the injected channels. More...
 
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start injected conversion Status. More...
 
void ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the selected ADC automatic injected group conversion after regular one. More...
 
void ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode for injected group channel for the specified ADC. More...
 
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
 Returns the ADC injected channel conversion result. More...
 
+

Detailed Description

+

Injected channels Configuration functions.

+
 ===============================================================================
+              ##### Injected channels Configuration functions #####
+ ===============================================================================  
+
+    [..] This section provide functions allowing to configure the ADC Injected channels,
+         it is composed of 2 sub sections : 
+    
+      (#) Configuration functions for Injected channels: This subsection provides 
+          functions allowing to configure the ADC injected channels :    
+        (++) Configure the rank in the injected group sequencer for each channel
+        (++) Configure the sampling time for each channel    
+        (++) Activate the Auto injected Mode  
+        (++) Activate the Discontinuous Mode 
+        (++) scan mode activation  
+        (++) External/software trigger source   
+        (++) External trigger edge 
+        (++) injected channels sequencer.
+    
+      (#) Get the Specified Injected channel conversion data: This subsection 
+          provides an important function in the ADC peripheral since it returns the 
+          converted data of the specific injected channel.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_AutoInjectedConvCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected ADC automatic injected group conversion after regular one.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC auto injected conversion This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef * ADCx,
uint32_t ADC_ExternalTrigInjecConv 
)
+
+ +

Configures the ADCx external trigger for injected channels conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConvspecifies the ADC trigger to start injected conversion. This parameter can be one of the following values:
    +
  • ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
    • +
  • ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
    • +
  • ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected
    • +
  • ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected
    • +
  • ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef * ADCx,
uint32_t ADC_ExternalTrigInjecConvEdge 
)
+
+ +

Configures the ADCx external trigger edge for injected channels conversion.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ExternalTrigInjecConvEdgespecifies the ADC external trigger edge to start injected conversion. This parameter can be one of the following values:
    +
  • ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for injected conversion
    • +
  • ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
    • +
  • ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
    • +
  • ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising and falling edge
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef * ADCx,
uint8_t ADC_InjectedChannel 
)
+
+ +

Returns the ADC injected channel conversion result.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannelthe converted ADC injected channel. This parameter can be one of the following values:
    +
  • ADC_InjectedChannel_1: Injected Channel1 selected
    • +
  • ADC_InjectedChannel_2: Injected Channel2 selected
    • +
  • ADC_InjectedChannel_3: Injected Channel3 selected
    • +
  • ADC_InjectedChannel_4: Injected Channel4 selected
    • +
+
+
+
+
Return values
+ + +
TheData conversion value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef * ADCx)
+
+ +

Gets the selected ADC Software start injected conversion Status.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
Thenew state of ADC software start injected conversion (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_InjectedChannelConfig (ADC_TypeDef * ADCx,
uint8_t ADC_Channel,
uint8_t Rank,
uint8_t ADC_SampleTime 
)
+
+ +

Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time.

+
Parameters
+ + + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_Channelthe ADC channel to configure. This parameter can be one of the following values:
    +
  • ADC_Channel_0: ADC Channel0 selected
    • +
  • ADC_Channel_1: ADC Channel1 selected
    • +
  • ADC_Channel_2: ADC Channel2 selected
    • +
  • ADC_Channel_3: ADC Channel3 selected
    • +
  • ADC_Channel_4: ADC Channel4 selected
    • +
  • ADC_Channel_5: ADC Channel5 selected
    • +
  • ADC_Channel_6: ADC Channel6 selected
    • +
  • ADC_Channel_7: ADC Channel7 selected
    • +
  • ADC_Channel_8: ADC Channel8 selected
    • +
  • ADC_Channel_9: ADC Channel9 selected
    • +
  • ADC_Channel_10: ADC Channel10 selected
    • +
  • ADC_Channel_11: ADC Channel11 selected
    • +
  • ADC_Channel_12: ADC Channel12 selected
    • +
  • ADC_Channel_13: ADC Channel13 selected
    • +
  • ADC_Channel_14: ADC Channel14 selected
    • +
  • ADC_Channel_15: ADC Channel15 selected
    • +
  • ADC_Channel_16: ADC Channel16 selected
    • +
  • ADC_Channel_17: ADC Channel17 selected
    • +
  • ADC_Channel_18: ADC Channel18 selected
    • +
+
RankThe rank in the injected group sequencer. This parameter must be between 1 to 4.
ADC_SampleTimeThe sample time value to be set for the selected channel. This parameter can be one of the following values:
    +
  • ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
    • +
  • ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
    • +
  • ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
    • +
  • ADC_SampleTime_56Cycles: Sample time equal to 56 cycles
    • +
  • ADC_SampleTime_84Cycles: Sample time equal to 84 cycles
    • +
  • ADC_SampleTime_112Cycles: Sample time equal to 112 cycles
    • +
  • ADC_SampleTime_144Cycles: Sample time equal to 144 cycles
    • +
  • ADC_SampleTime_480Cycles: Sample time equal to 480 cycles
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_InjectedDiscModeCmd (ADC_TypeDef * ADCx,
FunctionalState NewState 
)
+
+ +

Enables or disables the discontinuous mode for injected group channel for the specified ADC.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
NewStatenew state of the selected ADC discontinuous mode on injected group channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef * ADCx,
uint8_t Length 
)
+
+ +

Configures the sequencer length for injected channels.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
LengthThe sequencer length. This parameter must be a number between 1 to 4.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_SetInjectedOffset (ADC_TypeDef * ADCx,
uint8_t ADC_InjectedChannel,
uint16_t Offset 
)
+
+ +

Set the injected channels conversion value offset.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_InjectedChannelthe ADC injected channel to set its offset. This parameter can be one of the following values:
    +
  • ADC_InjectedChannel_1: Injected Channel1 selected
    • +
  • ADC_InjectedChannel_2: Injected Channel2 selected
    • +
  • ADC_InjectedChannel_3: Injected Channel3 selected
    • +
  • ADC_InjectedChannel_4: Injected Channel4 selected
    • +
+
Offsetthe offset value for the selected ADC injected channel This parameter must be a 12bit value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void ADC_SoftwareStartInjectedConv (ADC_TypeDef * ADCx)
+
+ +

Enables the selected ADC software start conversion of the injected channels.

+
Parameters
+ + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group6.map b/group___a_d_c___group6.map new file mode 100644 index 0000000..e4fe87c --- /dev/null +++ b/group___a_d_c___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group6.md5 b/group___a_d_c___group6.md5 new file mode 100644 index 0000000..eed83de --- /dev/null +++ b/group___a_d_c___group6.md5 @@ -0,0 +1 @@ +efe05edb30d0d708fe423633acacc163 \ No newline at end of file diff --git a/group___a_d_c___group6.png b/group___a_d_c___group6.png new file mode 100644 index 0000000..fe7cebd Binary files /dev/null and b/group___a_d_c___group6.png differ diff --git a/group___a_d_c___group7.html b/group___a_d_c___group7.html new file mode 100644 index 0000000..ed8b513 --- /dev/null +++ b/group___a_d_c___group7.html @@ -0,0 +1,441 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » ADC » ADC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
 Enables or disables the specified ADC interrupts. More...
 
FlagStatus ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Checks whether the specified ADC flag is set or not. More...
 
void ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Clears the ADCx's pending flags. More...
 
ITStatus ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Checks whether the specified ADC interrupt has occurred or not. More...
 
void ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Clears the ADCx's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+    [..] This section provides functions allowing to configure the ADC Interrupts 
+         and to get the status and clear flags and Interrupts pending bits.
+  
+    [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
+        into 3 groups:
+  
+  *** Flags and Interrupts for ADC regular channels ***
+  =====================================================
+    [..]
+      (+) Flags :
+        (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost
+
+        (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate 
+             (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
+             the end of:
+             (+++) a regular CHANNEL conversion 
+             (+++) sequence of regular GROUP conversions .
+
+        (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular 
+             CHANNEL conversion starts.
+    [..]
+      (+) Interrupts :
+        (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection 
+             event.  
+        (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end
+             of conversion event.
+  
+  
+  *** Flags and Interrupts for ADC Injected channels ***
+  ======================================================
+    [..]
+      (+) Flags :
+        (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate 
+             at the end of injected GROUP conversion  
+              
+        (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when 
+             injected GROUP conversion starts.
+    [..]
+      (+) Interrupts :
+        (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel 
+             end of conversion event.     
+
+  *** General Flags and Interrupts for the ADC ***
+  ================================================ 
+    [..]
+      (+)Flags :
+        (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage 
+             crosses the programmed thresholds values.
+    [..]          
+      (+) Interrupts :
+        (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. 
+
+  
+    [..] The user should identify which mode will be used in his application to 
+         manage the ADC controller events: Polling mode or Interrupt mode.
+  
+    [..] In the Polling Mode it is advised to use the following functions:
+      (+) ADC_GetFlagStatus() : to check if flags events occur. 
+      (+) ADC_ClearFlag()     : to clear the flags events.
+      
+    [..] In the Interrupt Mode it is advised to use the following functions:
+      (+) ADC_ITConfig()          : to enable or disable the interrupt source.
+      (+) ADC_GetITStatus()       : to check if Interrupt occurs.
+      (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                   (corresponding Flag). 
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ClearFlag (ADC_TypeDef * ADCx,
uint8_t ADC_FLAG 
)
+
+ +

Clears the ADCx's pending flags.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • ADC_FLAG_AWD: Analog watchdog flag
    • +
  • ADC_FLAG_EOC: End of conversion flag
    • +
  • ADC_FLAG_JEOC: End of injected group conversion flag
    • +
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
    • +
  • ADC_FLAG_STRT: Start of regular group conversion flag
    • +
  • ADC_FLAG_OVR: Overrun flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void ADC_ClearITPendingBit (ADC_TypeDef * ADCx,
uint16_t ADC_IT 
)
+
+ +

Clears the ADCx's interrupt pending bits.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus ADC_GetFlagStatus (ADC_TypeDef * ADCx,
uint8_t ADC_FLAG 
)
+
+ +

Checks whether the specified ADC flag is set or not.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • ADC_FLAG_AWD: Analog watchdog flag
    • +
  • ADC_FLAG_EOC: End of conversion flag
    • +
  • ADC_FLAG_JEOC: End of injected group conversion flag
    • +
  • ADC_FLAG_JSTRT: Start of injected group conversion flag
    • +
  • ADC_FLAG_STRT: Start of regular group conversion flag
    • +
  • ADC_FLAG_OVR: Overrun flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of ADC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus ADC_GetITStatus (ADC_TypeDef * ADCx,
uint16_t ADC_IT 
)
+
+ +

Checks whether the specified ADC interrupt has occurred or not.

+
Parameters
+ + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt source to check. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of ADC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void ADC_ITConfig (ADC_TypeDef * ADCx,
uint16_t ADC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified ADC interrupts.

+
Parameters
+ + + + +
ADCxwhere x can be 1, 2 or 3 to select the ADC peripheral.
ADC_ITspecifies the ADC interrupt sources to be enabled or disabled. This parameter can be one of the following values:
    +
  • ADC_IT_EOC: End of conversion interrupt mask
    • +
  • ADC_IT_AWD: Analog watchdog interrupt mask
    • +
  • ADC_IT_JEOC: End of injected conversion interrupt mask
    • +
  • ADC_IT_OVR: Overrun interrupt enable
    • +
+
NewStatenew state of the specified ADC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___group7.map b/group___a_d_c___group7.map new file mode 100644 index 0000000..94f67e0 --- /dev/null +++ b/group___a_d_c___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___group7.md5 b/group___a_d_c___group7.md5 new file mode 100644 index 0000000..4879b89 --- /dev/null +++ b/group___a_d_c___group7.md5 @@ -0,0 +1 @@ +f3ad0de64de795e1fc11dbdf9e87a589 \ No newline at end of file diff --git a/group___a_d_c___group7.png b/group___a_d_c___group7.png new file mode 100644 index 0000000..1ca8ff6 Binary files /dev/null and b/group___a_d_c___group7.png differ diff --git a/group___a_d_c___prescaler.html b/group___a_d_c___prescaler.html new file mode 100644 index 0000000..f25d73f --- /dev/null +++ b/group___a_d_c___prescaler.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_Prescaler
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_Prescaler_Div2   ((uint32_t)0x00000000)
 
+#define ADC_Prescaler_Div4   ((uint32_t)0x00010000)
 
+#define ADC_Prescaler_Div6   ((uint32_t)0x00020000)
 
+#define ADC_Prescaler_Div8   ((uint32_t)0x00030000)
 
#define IS_ADC_PRESCALER(PRESCALER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == ADC_Prescaler_Div2) || \
+
((PRESCALER) == ADC_Prescaler_Div4) || \
+
((PRESCALER) == ADC_Prescaler_Div6) || \
+
((PRESCALER) == ADC_Prescaler_Div8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___prescaler.map b/group___a_d_c___prescaler.map new file mode 100644 index 0000000..a7fd123 --- /dev/null +++ b/group___a_d_c___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c___prescaler.md5 b/group___a_d_c___prescaler.md5 new file mode 100644 index 0000000..8576710 --- /dev/null +++ b/group___a_d_c___prescaler.md5 @@ -0,0 +1 @@ +b7539eb54baeb2d3648cad77af9c5f04 \ No newline at end of file diff --git a/group___a_d_c___prescaler.png b/group___a_d_c___prescaler.png new file mode 100644 index 0000000..d47cf3d Binary files /dev/null and b/group___a_d_c___prescaler.png differ diff --git a/group___a_d_c___private___functions.html b/group___a_d_c___private___functions.html new file mode 100644 index 0000000..19b6b34 --- /dev/null +++ b/group___a_d_c___private___functions.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: ADC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
ADC_Private_Functions
STM32F4xx_StdPeriph_Driver » ADC
+
+
+
+Collaboration diagram for ADC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Analog Watchdog configuration functions
 Analog Watchdog configuration functions.
 
 Temperature Sensor, Vrefint (Voltage Reference internal)
 Temperature Sensor, Vrefint and VBAT management functions.
 
 Regular Channels Configuration functions
 Regular Channels Configuration functions.
 
 Regular Channels DMA Configuration functions
 Regular Channels DMA Configuration functions.
 
 Injected channels Configuration functions
 Injected channels Configuration functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c___private___functions.map b/group___a_d_c___private___functions.map new file mode 100644 index 0000000..cc05f55 --- /dev/null +++ b/group___a_d_c___private___functions.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___a_d_c___private___functions.md5 b/group___a_d_c___private___functions.md5 new file mode 100644 index 0000000..3b12dab --- /dev/null +++ b/group___a_d_c___private___functions.md5 @@ -0,0 +1 @@ +2fe3349be9335467da17ee4753c47f80 \ No newline at end of file diff --git a/group___a_d_c___private___functions.png b/group___a_d_c___private___functions.png new file mode 100644 index 0000000..35c0ff0 Binary files /dev/null and b/group___a_d_c___private___functions.png differ diff --git a/group___a_d_c__analog__watchdog__selection.html b/group___a_d_c__analog__watchdog__selection.html new file mode 100644 index 0000000..bad5246 --- /dev/null +++ b/group___a_d_c__analog__watchdog__selection.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: ADC_analog_watchdog_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_analog_watchdog_selection
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_analog_watchdog_selection:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_AnalogWatchdog_SingleRegEnable   ((uint32_t)0x00800200)
 
+#define ADC_AnalogWatchdog_SingleInjecEnable   ((uint32_t)0x00400200)
 
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable   ((uint32_t)0x00C00200)
 
+#define ADC_AnalogWatchdog_AllRegEnable   ((uint32_t)0x00800000)
 
+#define ADC_AnalogWatchdog_AllInjecEnable   ((uint32_t)0x00400000)
 
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable   ((uint32_t)0x00C00000)
 
+#define ADC_AnalogWatchdog_None   ((uint32_t)0x00000000)
 
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_ANALOG_WATCHDOG( WATCHDOG)
+
+Value:
(((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+
((WATCHDOG) == ADC_AnalogWatchdog_None))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__analog__watchdog__selection.map b/group___a_d_c__analog__watchdog__selection.map new file mode 100644 index 0000000..11a9453 --- /dev/null +++ b/group___a_d_c__analog__watchdog__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__analog__watchdog__selection.md5 b/group___a_d_c__analog__watchdog__selection.md5 new file mode 100644 index 0000000..d2bea14 --- /dev/null +++ b/group___a_d_c__analog__watchdog__selection.md5 @@ -0,0 +1 @@ +11b1dd210db64542ef8ab1a9c696d8b3 \ No newline at end of file diff --git a/group___a_d_c__analog__watchdog__selection.png b/group___a_d_c__analog__watchdog__selection.png new file mode 100644 index 0000000..32b8561 Binary files /dev/null and b/group___a_d_c__analog__watchdog__selection.png differ diff --git a/group___a_d_c__channels.html b/group___a_d_c__channels.html new file mode 100644 index 0000000..4a96f63 --- /dev/null +++ b/group___a_d_c__channels.html @@ -0,0 +1,210 @@ + + + + + + +discoverpixy: ADC_channels + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_channels
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_channels:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_Channel_0   ((uint8_t)0x00)
 
+#define ADC_Channel_1   ((uint8_t)0x01)
 
+#define ADC_Channel_2   ((uint8_t)0x02)
 
+#define ADC_Channel_3   ((uint8_t)0x03)
 
+#define ADC_Channel_4   ((uint8_t)0x04)
 
+#define ADC_Channel_5   ((uint8_t)0x05)
 
+#define ADC_Channel_6   ((uint8_t)0x06)
 
+#define ADC_Channel_7   ((uint8_t)0x07)
 
+#define ADC_Channel_8   ((uint8_t)0x08)
 
+#define ADC_Channel_9   ((uint8_t)0x09)
 
+#define ADC_Channel_10   ((uint8_t)0x0A)
 
+#define ADC_Channel_11   ((uint8_t)0x0B)
 
+#define ADC_Channel_12   ((uint8_t)0x0C)
 
+#define ADC_Channel_13   ((uint8_t)0x0D)
 
+#define ADC_Channel_14   ((uint8_t)0x0E)
 
+#define ADC_Channel_15   ((uint8_t)0x0F)
 
+#define ADC_Channel_16   ((uint8_t)0x10)
 
+#define ADC_Channel_17   ((uint8_t)0x11)
 
+#define ADC_Channel_18   ((uint8_t)0x12)
 
+#define ADC_Channel_TempSensor   ((uint8_t)ADC_Channel_16)
 
+#define ADC_Channel_Vrefint   ((uint8_t)ADC_Channel_17)
 
+#define ADC_Channel_Vbat   ((uint8_t)ADC_Channel_18)
 
#define IS_ADC_CHANNEL(CHANNEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == ADC_Channel_0) || \
+
((CHANNEL) == ADC_Channel_1) || \
+
((CHANNEL) == ADC_Channel_2) || \
+
((CHANNEL) == ADC_Channel_3) || \
+
((CHANNEL) == ADC_Channel_4) || \
+
((CHANNEL) == ADC_Channel_5) || \
+
((CHANNEL) == ADC_Channel_6) || \
+
((CHANNEL) == ADC_Channel_7) || \
+
((CHANNEL) == ADC_Channel_8) || \
+
((CHANNEL) == ADC_Channel_9) || \
+
((CHANNEL) == ADC_Channel_10) || \
+
((CHANNEL) == ADC_Channel_11) || \
+
((CHANNEL) == ADC_Channel_12) || \
+
((CHANNEL) == ADC_Channel_13) || \
+
((CHANNEL) == ADC_Channel_14) || \
+
((CHANNEL) == ADC_Channel_15) || \
+
((CHANNEL) == ADC_Channel_16) || \
+
((CHANNEL) == ADC_Channel_17) || \
+
((CHANNEL) == ADC_Channel_18))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__channels.map b/group___a_d_c__channels.map new file mode 100644 index 0000000..63fc6f7 --- /dev/null +++ b/group___a_d_c__channels.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__channels.md5 b/group___a_d_c__channels.md5 new file mode 100644 index 0000000..6a3a231 --- /dev/null +++ b/group___a_d_c__channels.md5 @@ -0,0 +1 @@ +61672095c0fd01063f9db1f1618a9853 \ No newline at end of file diff --git a/group___a_d_c__channels.png b/group___a_d_c__channels.png new file mode 100644 index 0000000..2666478 Binary files /dev/null and b/group___a_d_c__channels.png differ diff --git a/group___a_d_c__data__align.html b/group___a_d_c__data__align.html new file mode 100644 index 0000000..a12e0b7 --- /dev/null +++ b/group___a_d_c__data__align.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: ADC_data_align + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_data_align
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_data_align:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define ADC_DataAlign_Right   ((uint32_t)0x00000000)
 
+#define ADC_DataAlign_Left   ((uint32_t)0x00000800)
 
#define IS_ADC_DATA_ALIGN(ALIGN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_DATA_ALIGN( ALIGN)
+
+Value:
(((ALIGN) == ADC_DataAlign_Right) || \
+
((ALIGN) == ADC_DataAlign_Left))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__data__align.map b/group___a_d_c__data__align.map new file mode 100644 index 0000000..ecf52bd --- /dev/null +++ b/group___a_d_c__data__align.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__data__align.md5 b/group___a_d_c__data__align.md5 new file mode 100644 index 0000000..d875661 --- /dev/null +++ b/group___a_d_c__data__align.md5 @@ -0,0 +1 @@ +d49765525ab3a2c860e3d17716fc755b \ No newline at end of file diff --git a/group___a_d_c__data__align.png b/group___a_d_c__data__align.png new file mode 100644 index 0000000..0666e7a Binary files /dev/null and b/group___a_d_c__data__align.png differ diff --git a/group___a_d_c__delay__between__2__sampling__phases.html b/group___a_d_c__delay__between__2__sampling__phases.html new file mode 100644 index 0000000..4f66fec --- /dev/null +++ b/group___a_d_c__delay__between__2__sampling__phases.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: ADC_delay_between_2_sampling_phases + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_delay_between_2_sampling_phases
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_delay_between_2_sampling_phases:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_TwoSamplingDelay_5Cycles   ((uint32_t)0x00000000)
 
+#define ADC_TwoSamplingDelay_6Cycles   ((uint32_t)0x00000100)
 
+#define ADC_TwoSamplingDelay_7Cycles   ((uint32_t)0x00000200)
 
+#define ADC_TwoSamplingDelay_8Cycles   ((uint32_t)0x00000300)
 
+#define ADC_TwoSamplingDelay_9Cycles   ((uint32_t)0x00000400)
 
+#define ADC_TwoSamplingDelay_10Cycles   ((uint32_t)0x00000500)
 
+#define ADC_TwoSamplingDelay_11Cycles   ((uint32_t)0x00000600)
 
+#define ADC_TwoSamplingDelay_12Cycles   ((uint32_t)0x00000700)
 
+#define ADC_TwoSamplingDelay_13Cycles   ((uint32_t)0x00000800)
 
+#define ADC_TwoSamplingDelay_14Cycles   ((uint32_t)0x00000900)
 
+#define ADC_TwoSamplingDelay_15Cycles   ((uint32_t)0x00000A00)
 
+#define ADC_TwoSamplingDelay_16Cycles   ((uint32_t)0x00000B00)
 
+#define ADC_TwoSamplingDelay_17Cycles   ((uint32_t)0x00000C00)
 
+#define ADC_TwoSamplingDelay_18Cycles   ((uint32_t)0x00000D00)
 
+#define ADC_TwoSamplingDelay_19Cycles   ((uint32_t)0x00000E00)
 
+#define ADC_TwoSamplingDelay_20Cycles   ((uint32_t)0x00000F00)
 
#define IS_ADC_SAMPLING_DELAY(DELAY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_SAMPLING_DELAY( DELAY)
+
+Value:
(((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+
((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__delay__between__2__sampling__phases.map b/group___a_d_c__delay__between__2__sampling__phases.map new file mode 100644 index 0000000..0c76298 --- /dev/null +++ b/group___a_d_c__delay__between__2__sampling__phases.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__delay__between__2__sampling__phases.md5 b/group___a_d_c__delay__between__2__sampling__phases.md5 new file mode 100644 index 0000000..1f170eb --- /dev/null +++ b/group___a_d_c__delay__between__2__sampling__phases.md5 @@ -0,0 +1 @@ +3d08b3c791fcdee8420300d7d3172aa0 \ No newline at end of file diff --git a/group___a_d_c__delay__between__2__sampling__phases.png b/group___a_d_c__delay__between__2__sampling__phases.png new file mode 100644 index 0000000..63dc171 Binary files /dev/null and b/group___a_d_c__delay__between__2__sampling__phases.png differ diff --git a/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.html b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.html new file mode 100644 index 0000000..a2138ae --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_external_trigger_edge_for_injected_channels_conversion + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_external_trigger_edge_for_injected_channels_conversion
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_external_trigger_edge_for_injected_channels_conversion:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_ExternalTrigInjecConvEdge_None   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConvEdge_Rising   ((uint32_t)0x00100000)
 
+#define ADC_ExternalTrigInjecConvEdge_Falling   ((uint32_t)0x00200000)
 
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling   ((uint32_t)0x00300000)
 
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_EXT_INJEC_TRIG_EDGE( EDGE)
+
+Value:
(((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.map b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.map new file mode 100644 index 0000000..194bc51 --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.md5 b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.md5 new file mode 100644 index 0000000..ed510b8 --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.md5 @@ -0,0 +1 @@ +65cfdb2a1c6b5c0009b39b7af927d09b \ No newline at end of file diff --git a/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.png b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.png new file mode 100644 index 0000000..14e127b Binary files /dev/null and b/group___a_d_c__external__trigger__edge__for__injected__channels__conversion.png differ diff --git a/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.html b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.html new file mode 100644 index 0000000..1639e3e --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_external_trigger_edge_for_regular_channels_conversion + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_external_trigger_edge_for_regular_channels_conversion
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_external_trigger_edge_for_regular_channels_conversion:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_ExternalTrigConvEdge_None   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConvEdge_Rising   ((uint32_t)0x10000000)
 
+#define ADC_ExternalTrigConvEdge_Falling   ((uint32_t)0x20000000)
 
+#define ADC_ExternalTrigConvEdge_RisingFalling   ((uint32_t)0x30000000)
 
#define IS_ADC_EXT_TRIG_EDGE(EDGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_EXT_TRIG_EDGE( EDGE)
+
+Value:
(((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.map b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.map new file mode 100644 index 0000000..632c305 --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.md5 b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.md5 new file mode 100644 index 0000000..d37b377 --- /dev/null +++ b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.md5 @@ -0,0 +1 @@ +feb6c641fc1f9d0fd6a16e8d97a47077 \ No newline at end of file diff --git a/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.png b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.png new file mode 100644 index 0000000..a0c0b4e Binary files /dev/null and b/group___a_d_c__external__trigger__edge__for__regular__channels__conversion.png differ diff --git a/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.html b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.html new file mode 100644 index 0000000..0e322b2 --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: ADC_extrenal_trigger_sources_for_injected_channels_conversion + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_extrenal_trigger_sources_for_injected_channels_conversion
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_extrenal_trigger_sources_for_injected_channels_conversion:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_ExternalTrigInjecConv_T1_CC4   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConv_T1_TRGO   ((uint32_t)0x00010000)
 
+#define ADC_ExternalTrigInjecConv_T2_CC1   ((uint32_t)0x00020000)
 
+#define ADC_ExternalTrigInjecConv_T2_TRGO   ((uint32_t)0x00030000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC2   ((uint32_t)0x00040000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC4   ((uint32_t)0x00050000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC1   ((uint32_t)0x00060000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC2   ((uint32_t)0x00070000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC3   ((uint32_t)0x00080000)
 
+#define ADC_ExternalTrigInjecConv_T4_TRGO   ((uint32_t)0x00090000)
 
+#define ADC_ExternalTrigInjecConv_T5_CC4   ((uint32_t)0x000A0000)
 
+#define ADC_ExternalTrigInjecConv_T5_TRGO   ((uint32_t)0x000B0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC2   ((uint32_t)0x000C0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC3   ((uint32_t)0x000D0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC4   ((uint32_t)0x000E0000)
 
+#define ADC_ExternalTrigInjecConv_Ext_IT15   ((uint32_t)0x000F0000)
 
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_EXT_INJEC_TRIG( INJTRIG)
+
+Value:
(((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.map b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.map new file mode 100644 index 0000000..2a24460 --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.md5 b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.md5 new file mode 100644 index 0000000..239c0ac --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.md5 @@ -0,0 +1 @@ +980bb35a513b91a24f2b96c768f03e3b \ No newline at end of file diff --git a/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.png b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.png new file mode 100644 index 0000000..3ecef5c Binary files /dev/null and b/group___a_d_c__extrenal__trigger__sources__for__injected__channels__conversion.png differ diff --git a/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.html b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.html new file mode 100644 index 0000000..1bf390a --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: ADC_extrenal_trigger_sources_for_regular_channels_conversion + + + + + + + + + + +
+
+ + + + + + +
+
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+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_extrenal_trigger_sources_for_regular_channels_conversion
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_extrenal_trigger_sources_for_regular_channels_conversion:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_ExternalTrigConv_T1_CC1   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConv_T1_CC2   ((uint32_t)0x01000000)
 
+#define ADC_ExternalTrigConv_T1_CC3   ((uint32_t)0x02000000)
 
+#define ADC_ExternalTrigConv_T2_CC2   ((uint32_t)0x03000000)
 
+#define ADC_ExternalTrigConv_T2_CC3   ((uint32_t)0x04000000)
 
+#define ADC_ExternalTrigConv_T2_CC4   ((uint32_t)0x05000000)
 
+#define ADC_ExternalTrigConv_T2_TRGO   ((uint32_t)0x06000000)
 
+#define ADC_ExternalTrigConv_T3_CC1   ((uint32_t)0x07000000)
 
+#define ADC_ExternalTrigConv_T3_TRGO   ((uint32_t)0x08000000)
 
+#define ADC_ExternalTrigConv_T4_CC4   ((uint32_t)0x09000000)
 
+#define ADC_ExternalTrigConv_T5_CC1   ((uint32_t)0x0A000000)
 
+#define ADC_ExternalTrigConv_T5_CC2   ((uint32_t)0x0B000000)
 
+#define ADC_ExternalTrigConv_T5_CC3   ((uint32_t)0x0C000000)
 
+#define ADC_ExternalTrigConv_T8_CC1   ((uint32_t)0x0D000000)
 
+#define ADC_ExternalTrigConv_T8_TRGO   ((uint32_t)0x0E000000)
 
+#define ADC_ExternalTrigConv_Ext_IT11   ((uint32_t)0x0F000000)
 
#define IS_ADC_EXT_TRIG(REGTRIG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_EXT_TRIG( REGTRIG)
+
+Value:
(((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.map b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.map new file mode 100644 index 0000000..8caa773 --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.md5 b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.md5 new file mode 100644 index 0000000..d798f82 --- /dev/null +++ b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.md5 @@ -0,0 +1 @@ +bdae4e246470aeaf9ea870a11cfa88c8 \ No newline at end of file diff --git a/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.png b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.png new file mode 100644 index 0000000..47ba39e Binary files /dev/null and b/group___a_d_c__extrenal__trigger__sources__for__regular__channels__conversion.png differ diff --git a/group___a_d_c__flags__definition.html b/group___a_d_c__flags__definition.html new file mode 100644 index 0000000..2c5c985 --- /dev/null +++ b/group___a_d_c__flags__definition.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: ADC_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_flags_definition
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_flags_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_FLAG_AWD   ((uint8_t)0x01)
 
+#define ADC_FLAG_EOC   ((uint8_t)0x02)
 
+#define ADC_FLAG_JEOC   ((uint8_t)0x04)
 
+#define ADC_FLAG_JSTRT   ((uint8_t)0x08)
 
+#define ADC_FLAG_STRT   ((uint8_t)0x10)
 
+#define ADC_FLAG_OVR   ((uint8_t)0x20)
 
+#define IS_ADC_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
 
#define IS_ADC_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == ADC_FLAG_AWD) || \
+
((FLAG) == ADC_FLAG_EOC) || \
+
((FLAG) == ADC_FLAG_JEOC) || \
+
((FLAG)== ADC_FLAG_JSTRT) || \
+
((FLAG) == ADC_FLAG_STRT) || \
+
((FLAG)== ADC_FLAG_OVR))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__flags__definition.map b/group___a_d_c__flags__definition.map new file mode 100644 index 0000000..2eb3b22 --- /dev/null +++ b/group___a_d_c__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__flags__definition.md5 b/group___a_d_c__flags__definition.md5 new file mode 100644 index 0000000..3595ac3 --- /dev/null +++ b/group___a_d_c__flags__definition.md5 @@ -0,0 +1 @@ +e2df9da7811c8cfd15d65a68e8625954 \ No newline at end of file diff --git a/group___a_d_c__flags__definition.png b/group___a_d_c__flags__definition.png new file mode 100644 index 0000000..3eec002 Binary files /dev/null and b/group___a_d_c__flags__definition.png differ diff --git a/group___a_d_c__injected__channel__selection.html b/group___a_d_c__injected__channel__selection.html new file mode 100644 index 0000000..4cd424b --- /dev/null +++ b/group___a_d_c__injected__channel__selection.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_injected_channel_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
ADC_injected_channel_selection
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_injected_channel_selection:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_InjectedChannel_1   ((uint8_t)0x14)
 
+#define ADC_InjectedChannel_2   ((uint8_t)0x18)
 
+#define ADC_InjectedChannel_3   ((uint8_t)0x1C)
 
+#define ADC_InjectedChannel_4   ((uint8_t)0x20)
 
#define IS_ADC_INJECTED_CHANNEL(CHANNEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_INJECTED_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == ADC_InjectedChannel_1) || \
+
((CHANNEL) == ADC_InjectedChannel_2) || \
+
((CHANNEL) == ADC_InjectedChannel_3) || \
+
((CHANNEL) == ADC_InjectedChannel_4))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__injected__channel__selection.map b/group___a_d_c__injected__channel__selection.map new file mode 100644 index 0000000..d59acf0 --- /dev/null +++ b/group___a_d_c__injected__channel__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__injected__channel__selection.md5 b/group___a_d_c__injected__channel__selection.md5 new file mode 100644 index 0000000..4607aef --- /dev/null +++ b/group___a_d_c__injected__channel__selection.md5 @@ -0,0 +1 @@ +1b568c8cd809c45b48c5347b711c7700 \ No newline at end of file diff --git a/group___a_d_c__injected__channel__selection.png b/group___a_d_c__injected__channel__selection.png new file mode 100644 index 0000000..4d3b32f Binary files /dev/null and b/group___a_d_c__injected__channel__selection.png differ diff --git a/group___a_d_c__injected__length.html b/group___a_d_c__injected__length.html new file mode 100644 index 0000000..f964396 --- /dev/null +++ b/group___a_d_c__injected__length.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_injected_length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_injected_length
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_injected_length:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_INJECTED_LENGTH(LENGTH)   (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__injected__length.map b/group___a_d_c__injected__length.map new file mode 100644 index 0000000..3ccde1b --- /dev/null +++ b/group___a_d_c__injected__length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__injected__length.md5 b/group___a_d_c__injected__length.md5 new file mode 100644 index 0000000..c15e37d --- /dev/null +++ b/group___a_d_c__injected__length.md5 @@ -0,0 +1 @@ +82c43eb72320026872f9fc834dd2d1c2 \ No newline at end of file diff --git a/group___a_d_c__injected__length.png b/group___a_d_c__injected__length.png new file mode 100644 index 0000000..b87c255 Binary files /dev/null and b/group___a_d_c__injected__length.png differ diff --git a/group___a_d_c__injected__offset.html b/group___a_d_c__injected__offset.html new file mode 100644 index 0000000..b45a76b --- /dev/null +++ b/group___a_d_c__injected__offset.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_injected_offset + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_injected_offset
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_injected_offset:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_OFFSET(OFFSET)   ((OFFSET) <= 0xFFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__injected__offset.map b/group___a_d_c__injected__offset.map new file mode 100644 index 0000000..174007e --- /dev/null +++ b/group___a_d_c__injected__offset.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__injected__offset.md5 b/group___a_d_c__injected__offset.md5 new file mode 100644 index 0000000..011ab8b --- /dev/null +++ b/group___a_d_c__injected__offset.md5 @@ -0,0 +1 @@ +0d8495941c7449d46b3c3916df2793ed \ No newline at end of file diff --git a/group___a_d_c__injected__offset.png b/group___a_d_c__injected__offset.png new file mode 100644 index 0000000..793130e Binary files /dev/null and b/group___a_d_c__injected__offset.png differ diff --git a/group___a_d_c__injected__rank.html b/group___a_d_c__injected__rank.html new file mode 100644 index 0000000..fcd6ffd --- /dev/null +++ b/group___a_d_c__injected__rank.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_injected_rank + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
ADC_injected_rank
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_injected_rank:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_INJECTED_RANK(RANK)   (((RANK) >= 0x1) && ((RANK) <= 0x4))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__injected__rank.map b/group___a_d_c__injected__rank.map new file mode 100644 index 0000000..daec33a --- /dev/null +++ b/group___a_d_c__injected__rank.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__injected__rank.md5 b/group___a_d_c__injected__rank.md5 new file mode 100644 index 0000000..fbbeb94 --- /dev/null +++ b/group___a_d_c__injected__rank.md5 @@ -0,0 +1 @@ +92699b20bf5037f49675b7eab5205e29 \ No newline at end of file diff --git a/group___a_d_c__injected__rank.png b/group___a_d_c__injected__rank.png new file mode 100644 index 0000000..b6955d5 Binary files /dev/null and b/group___a_d_c__injected__rank.png differ diff --git a/group___a_d_c__interrupts__definition.html b/group___a_d_c__interrupts__definition.html new file mode 100644 index 0000000..ff5a24b --- /dev/null +++ b/group___a_d_c__interrupts__definition.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: ADC_interrupts_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
ADC_interrupts_definition
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_interrupts_definition:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_IT_EOC   ((uint16_t)0x0205)
 
+#define ADC_IT_AWD   ((uint16_t)0x0106)
 
+#define ADC_IT_JEOC   ((uint16_t)0x0407)
 
+#define ADC_IT_OVR   ((uint16_t)0x201A)
 
#define IS_ADC_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_IT( IT)
+
+Value:
(((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__interrupts__definition.map b/group___a_d_c__interrupts__definition.map new file mode 100644 index 0000000..39e9af2 --- /dev/null +++ b/group___a_d_c__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__interrupts__definition.md5 b/group___a_d_c__interrupts__definition.md5 new file mode 100644 index 0000000..d363d8f --- /dev/null +++ b/group___a_d_c__interrupts__definition.md5 @@ -0,0 +1 @@ +9b85b717fddc42c4a18963d0665a60cd \ No newline at end of file diff --git a/group___a_d_c__interrupts__definition.png b/group___a_d_c__interrupts__definition.png new file mode 100644 index 0000000..ba35d7b Binary files /dev/null and b/group___a_d_c__interrupts__definition.png differ diff --git a/group___a_d_c__regular__discontinuous__mode__number.html b/group___a_d_c__regular__discontinuous__mode__number.html new file mode 100644 index 0000000..752906f --- /dev/null +++ b/group___a_d_c__regular__discontinuous__mode__number.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_regular_discontinuous_mode_number + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
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+ +
+
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+ +
+ +
+
+Macros
+
+
ADC_regular_discontinuous_mode_number
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_regular_discontinuous_mode_number:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)   (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__regular__discontinuous__mode__number.map b/group___a_d_c__regular__discontinuous__mode__number.map new file mode 100644 index 0000000..27ead47 --- /dev/null +++ b/group___a_d_c__regular__discontinuous__mode__number.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__regular__discontinuous__mode__number.md5 b/group___a_d_c__regular__discontinuous__mode__number.md5 new file mode 100644 index 0000000..f8209eb --- /dev/null +++ b/group___a_d_c__regular__discontinuous__mode__number.md5 @@ -0,0 +1 @@ +708b622f47b051623bf708f5b04c4b3e \ No newline at end of file diff --git a/group___a_d_c__regular__discontinuous__mode__number.png b/group___a_d_c__regular__discontinuous__mode__number.png new file mode 100644 index 0000000..9be7c9c Binary files /dev/null and b/group___a_d_c__regular__discontinuous__mode__number.png differ diff --git a/group___a_d_c__regular__length.html b/group___a_d_c__regular__length.html new file mode 100644 index 0000000..4e54435 --- /dev/null +++ b/group___a_d_c__regular__length.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_regular_length + + + + + + + + + + +
+
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+
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+ +
+
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+ +
+ +
+
+Macros
+
+
ADC_regular_length
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_regular_length:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_REGULAR_LENGTH(LENGTH)   (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__regular__length.map b/group___a_d_c__regular__length.map new file mode 100644 index 0000000..5a54afb --- /dev/null +++ b/group___a_d_c__regular__length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__regular__length.md5 b/group___a_d_c__regular__length.md5 new file mode 100644 index 0000000..e6224a3 --- /dev/null +++ b/group___a_d_c__regular__length.md5 @@ -0,0 +1 @@ +1914db18b35b14f37a3651ed3257c9da \ No newline at end of file diff --git a/group___a_d_c__regular__length.png b/group___a_d_c__regular__length.png new file mode 100644 index 0000000..38e9f0f Binary files /dev/null and b/group___a_d_c__regular__length.png differ diff --git a/group___a_d_c__regular__rank.html b/group___a_d_c__regular__rank.html new file mode 100644 index 0000000..6568777 --- /dev/null +++ b/group___a_d_c__regular__rank.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_regular_rank + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + +
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+
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+ +
+
+Macros
+
+
ADC_regular_rank
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_regular_rank:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_REGULAR_RANK(RANK)   (((RANK) >= 0x1) && ((RANK) <= 0x10))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__regular__rank.map b/group___a_d_c__regular__rank.map new file mode 100644 index 0000000..6c0bc9b --- /dev/null +++ b/group___a_d_c__regular__rank.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__regular__rank.md5 b/group___a_d_c__regular__rank.md5 new file mode 100644 index 0000000..3afd7c7 --- /dev/null +++ b/group___a_d_c__regular__rank.md5 @@ -0,0 +1 @@ +086c51856c40d11218289704a9f30fb3 \ No newline at end of file diff --git a/group___a_d_c__regular__rank.png b/group___a_d_c__regular__rank.png new file mode 100644 index 0000000..08bf39c Binary files /dev/null and b/group___a_d_c__regular__rank.png differ diff --git a/group___a_d_c__resolution.html b/group___a_d_c__resolution.html new file mode 100644 index 0000000..889d390 --- /dev/null +++ b/group___a_d_c__resolution.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: ADC_resolution + + + + + + + + + + +
+
+ + + + + + +
+
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+
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+ +
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+Macros
+
+
ADC_resolution
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_resolution:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define ADC_Resolution_12b   ((uint32_t)0x00000000)
 
+#define ADC_Resolution_10b   ((uint32_t)0x01000000)
 
+#define ADC_Resolution_8b   ((uint32_t)0x02000000)
 
+#define ADC_Resolution_6b   ((uint32_t)0x03000000)
 
#define IS_ADC_RESOLUTION(RESOLUTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_RESOLUTION( RESOLUTION)
+
+Value:
(((RESOLUTION) == ADC_Resolution_12b) || \
+
((RESOLUTION) == ADC_Resolution_10b) || \
+
((RESOLUTION) == ADC_Resolution_8b) || \
+
((RESOLUTION) == ADC_Resolution_6b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__resolution.map b/group___a_d_c__resolution.map new file mode 100644 index 0000000..cba3bdb --- /dev/null +++ b/group___a_d_c__resolution.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__resolution.md5 b/group___a_d_c__resolution.md5 new file mode 100644 index 0000000..8624b36 --- /dev/null +++ b/group___a_d_c__resolution.md5 @@ -0,0 +1 @@ +d818583c0907b2989336aa52cbbb18f1 \ No newline at end of file diff --git a/group___a_d_c__resolution.png b/group___a_d_c__resolution.png new file mode 100644 index 0000000..8d8c502 Binary files /dev/null and b/group___a_d_c__resolution.png differ diff --git a/group___a_d_c__sampling__times.html b/group___a_d_c__sampling__times.html new file mode 100644 index 0000000..19dd672 --- /dev/null +++ b/group___a_d_c__sampling__times.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: ADC_sampling_times + + + + + + + + + + +
+
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+
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+ +
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+Macros
+
+
ADC_sampling_times
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_sampling_times:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define ADC_SampleTime_3Cycles   ((uint8_t)0x00)
 
+#define ADC_SampleTime_15Cycles   ((uint8_t)0x01)
 
+#define ADC_SampleTime_28Cycles   ((uint8_t)0x02)
 
+#define ADC_SampleTime_56Cycles   ((uint8_t)0x03)
 
+#define ADC_SampleTime_84Cycles   ((uint8_t)0x04)
 
+#define ADC_SampleTime_112Cycles   ((uint8_t)0x05)
 
+#define ADC_SampleTime_144Cycles   ((uint8_t)0x06)
 
+#define ADC_SampleTime_480Cycles   ((uint8_t)0x07)
 
#define IS_ADC_SAMPLE_TIME(TIME)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_ADC_SAMPLE_TIME( TIME)
+
+Value:
(((TIME) == ADC_SampleTime_3Cycles) || \
+
((TIME) == ADC_SampleTime_15Cycles) || \
+
((TIME) == ADC_SampleTime_28Cycles) || \
+
((TIME) == ADC_SampleTime_56Cycles) || \
+
((TIME) == ADC_SampleTime_84Cycles) || \
+
((TIME) == ADC_SampleTime_112Cycles) || \
+
((TIME) == ADC_SampleTime_144Cycles) || \
+
((TIME) == ADC_SampleTime_480Cycles))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__sampling__times.map b/group___a_d_c__sampling__times.map new file mode 100644 index 0000000..47d07db --- /dev/null +++ b/group___a_d_c__sampling__times.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__sampling__times.md5 b/group___a_d_c__sampling__times.md5 new file mode 100644 index 0000000..63d7538 --- /dev/null +++ b/group___a_d_c__sampling__times.md5 @@ -0,0 +1 @@ +3306b8c36fd3e56f66406b51a5454563 \ No newline at end of file diff --git a/group___a_d_c__sampling__times.png b/group___a_d_c__sampling__times.png new file mode 100644 index 0000000..97bafbc Binary files /dev/null and b/group___a_d_c__sampling__times.png differ diff --git a/group___a_d_c__thresholds.html b/group___a_d_c__thresholds.html new file mode 100644 index 0000000..64b5110 --- /dev/null +++ b/group___a_d_c__thresholds.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: ADC_thresholds + + + + + + + + + + +
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+Macros
+
+
ADC_thresholds
STM32F4xx_StdPeriph_Driver » ADC » ADC_Exported_Constants
+
+
+
+Collaboration diagram for ADC_thresholds:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_ADC_THRESHOLD(THRESHOLD)   ((THRESHOLD) <= 0xFFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___a_d_c__thresholds.map b/group___a_d_c__thresholds.map new file mode 100644 index 0000000..852cbac --- /dev/null +++ b/group___a_d_c__thresholds.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c__thresholds.md5 b/group___a_d_c__thresholds.md5 new file mode 100644 index 0000000..9672c3a --- /dev/null +++ b/group___a_d_c__thresholds.md5 @@ -0,0 +1 @@ +a0408103631569887b231da42bcab1ba \ No newline at end of file diff --git a/group___a_d_c__thresholds.png b/group___a_d_c__thresholds.png new file mode 100644 index 0000000..d3d1ba0 Binary files /dev/null and b/group___a_d_c__thresholds.png differ diff --git a/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map new file mode 100644 index 0000000..63d006d --- /dev/null +++ b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 new file mode 100644 index 0000000..5fb1c4c --- /dev/null +++ b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.md5 @@ -0,0 +1 @@ +d1d3cc26df948442611015cc2613c627 \ No newline at end of file diff --git a/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png new file mode 100644 index 0000000..4d539fd Binary files /dev/null and b/group___a_d_c_ga1962afdd9eebe5c896bbba2e4f26fe09_cgraph.png differ diff --git a/group___boot___mode__selection.html b/group___boot___mode__selection.html new file mode 100644 index 0000000..c8ee40c --- /dev/null +++ b/group___boot___mode__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Boot_Mode_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
Boot_Mode_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Boot_Mode_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_BOOT_NORMALMODE   ((uint8_t)0x00)
 
+#define LIS302DL_BOOT_REBOOTMEMORY   ((uint8_t)0x40)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___boot___mode__selection.map b/group___boot___mode__selection.map new file mode 100644 index 0000000..250bc72 --- /dev/null +++ b/group___boot___mode__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___boot___mode__selection.md5 b/group___boot___mode__selection.md5 new file mode 100644 index 0000000..5dc3a9b --- /dev/null +++ b/group___boot___mode__selection.md5 @@ -0,0 +1 @@ +eef8d782e39c0857a3bce14d97ef924f \ No newline at end of file diff --git a/group___boot___mode__selection.png b/group___boot___mode__selection.png new file mode 100644 index 0000000..f5d6b8f Binary files /dev/null and b/group___boot___mode__selection.png differ diff --git a/group___c_a_n.html b/group___c_a_n.html new file mode 100644 index 0000000..6165405 --- /dev/null +++ b/group___c_a_n.html @@ -0,0 +1,1272 @@ + + + + + + +discoverpixy: CAN + + + + + + + + + + +
+
+ + + + + + +
+
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+ + +
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+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
CAN
STM32F4xx_StdPeriph_Driver
+
+
+ +

CAN driver modules. +More...

+
+Collaboration diagram for CAN:
+
+
+ + +
+
+ + + + + + +

+Modules

 CAN_Exported_Constants
 
 CAN_Private_Functions
 
+ + + + + + + + + + + + + +

+Classes

struct  CAN_InitTypeDef
 CAN init structure definition. More...
 
struct  CAN_FilterInitTypeDef
 CAN filter init structure definition. More...
 
struct  CanTxMsg
 CAN Tx message structure definition. More...
 
struct  CanRxMsg
 CAN Rx message structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_CAN_ALL_PERIPH(PERIPH)
 
+#define MCR_DBF   ((uint32_t)0x00010000) /* software master reset */
 
+#define TMIDxR_TXRQ   ((uint32_t)0x00000001) /* Transmit mailbox request */
 
+#define FMR_FINIT   ((uint32_t)0x00000001) /* Filter init mode */
 
+#define INAK_TIMEOUT   ((uint32_t)0x0000FFFF)
 
+#define SLAK_TIMEOUT   ((uint32_t)0x0000FFFF)
 
+#define CAN_FLAGS_TSR   ((uint32_t)0x08000000)
 
+#define CAN_FLAGS_RF1R   ((uint32_t)0x04000000)
 
+#define CAN_FLAGS_RF0R   ((uint32_t)0x02000000)
 
+#define CAN_FLAGS_MSR   ((uint32_t)0x01000000)
 
+#define CAN_FLAGS_ESR   ((uint32_t)0x00F00000)
 
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
 
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
 
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
 
+#define CAN_MODE_MASK   ((uint32_t) 0x00000003)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CAN_DeInit (CAN_TypeDef *CANx)
 Deinitializes the CAN peripheral registers to their default reset values. More...
 
uint8_t CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
 Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct. More...
 
void CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
 Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct. More...
 
void CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
 Fills each CAN_InitStruct member with its default value. More...
 
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
 Select the start bank filter for slave CAN. More...
 
void CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the DBG Freeze for CAN. More...
 
void CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the CAN Time TriggerOperation communication mode. More...
 
uint8_t CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
 Initiates and transmits a CAN frame message. More...
 
uint8_t CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
 Checks the transmission status of a CAN Frame. More...
 
void CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
 Cancels a transmit request. More...
 
void CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
 Receives a correct CAN frame. More...
 
void CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Releases the specified receive FIFO. More...
 
uint8_t CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Returns the number of pending received messages. More...
 
uint8_t CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
 Selects the CAN Operation mode. More...
 
uint8_t CAN_Sleep (CAN_TypeDef *CANx)
 Enters the Sleep (low power) mode. More...
 
uint8_t CAN_WakeUp (CAN_TypeDef *CANx)
 Wakes up the CAN peripheral from sleep mode . More...
 
uint8_t CAN_GetLastErrorCode (CAN_TypeDef *CANx)
 Returns the CANx's last error code (LEC). More...
 
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
 Returns the CANx Receive Error Counter (REC). More...
 
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
 Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). More...
 
void CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
 Enables or disables the specified CANx interrupts. More...
 
FlagStatus CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Checks whether the specified CAN flag is set or not. More...
 
void CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Clears the CAN's pending flags. More...
 
ITStatus CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Checks whether the specified CANx interrupt has occurred or not. More...
 
void CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Clears the CANx's interrupt pending bits. More...
 
+

Detailed Description

+

CAN driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_CAN_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == CAN1) || \
+
((PERIPH) == CAN2))
+
+
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_CancelTransmit (CAN_TypeDef * CANx,
uint8_t Mailbox 
)
+
+ +

Cancels a transmit request.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
MailboxMailbox number.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_ClearFlag (CAN_TypeDef * CANx,
uint32_t CAN_FLAG 
)
+
+ +

Clears the CAN's pending flags.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAGspecifies the flag to clear. This parameter can be one of the following values:
    +
  • CAN_FLAG_RQCP0: Request MailBox0 Flag
    • +
  • CAN_FLAG_RQCP1: Request MailBox1 Flag
    • +
  • CAN_FLAG_RQCP2: Request MailBox2 Flag
    • +
  • CAN_FLAG_FF0: FIFO 0 Full Flag
    • +
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
    • +
  • CAN_FLAG_FF1: FIFO 1 Full Flag
    • +
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
    • +
  • CAN_FLAG_WKU: Wake up Flag
    • +
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
    • +
  • CAN_FLAG_LEC: Last error code Flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_ClearITPendingBit (CAN_TypeDef * CANx,
uint32_t CAN_IT 
)
+
+ +

Clears the CANx's interrupt pending bits.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_DBGFreeze (CAN_TypeDef * CANx,
FunctionalState NewState 
)
+
+ +

Enables or disables the DBG Freeze for CAN.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
NewStatenew state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFOs can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_DeInit (CAN_TypeDef * CANx)
+
+ +

Deinitializes the CAN peripheral registers to their default reset values.

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
None.
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_FIFORelease (CAN_TypeDef * CANx,
uint8_t FIFONumber 
)
+
+ +

Releases the specified receive FIFO.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_FilterInit (CAN_FilterInitTypeDef * CAN_FilterInitStruct)
+
+ +

Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

+
Parameters
+ + +
CAN_FilterInitStructpointer to a CAN_FilterInitTypeDef structure that contains the configuration information.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus CAN_GetFlagStatus (CAN_TypeDef * CANx,
uint32_t CAN_FLAG 
)
+
+ +

Checks whether the specified CAN flag is set or not.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • CAN_FLAG_RQCP0: Request MailBox0 Flag
    • +
  • CAN_FLAG_RQCP1: Request MailBox1 Flag
    • +
  • CAN_FLAG_RQCP2: Request MailBox2 Flag
    • +
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
    • +
  • CAN_FLAG_FF0: FIFO 0 Full Flag
    • +
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
    • +
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
    • +
  • CAN_FLAG_FF1: FIFO 1 Full Flag
    • +
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
    • +
  • CAN_FLAG_WKU: Wake up Flag
    • +
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
    • +
  • CAN_FLAG_EWG: Error Warning Flag
    • +
  • CAN_FLAG_EPV: Error Passive Flag
    • +
  • CAN_FLAG_BOF: Bus-Off Flag
    • +
  • CAN_FLAG_LEC: Last error code Flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of CAN_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus CAN_GetITStatus (CAN_TypeDef * CANx,
uint32_t CAN_IT 
)
+
+ +

Checks whether the specified CANx interrupt has occurred or not.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the CAN interrupt source to check. This parameter can be one of the following values:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FMP0: FIFO 0 message pending Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FMP1: FIFO 1 message pending Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
+
+
+
Return values
+ + +
Thecurrent state of CAN_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_GetLastErrorCode (CAN_TypeDef * CANx)
+
+ +

Returns the CANx's last error code (LEC).

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
Errorcode:
    +
  • CAN_ERRORCODE_NoErr: No Error
    • +
  • CAN_ERRORCODE_StuffErr: Stuff Error
    • +
  • CAN_ERRORCODE_FormErr: Form Error
    • +
  • CAN_ERRORCODE_ACKErr : Acknowledgment Error
    • +
  • CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
    • +
  • CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
    • +
  • CAN_ERRORCODE_CRCErr: CRC Error
    • +
  • CAN_ERRORCODE_SoftwareSetErr: Software Set Error
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef * CANx)
+
+ +

Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
+
+
+
Return values
+ + +
LSBof the 9-bit CAN Transmit Error Counter.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef * CANx)
+
+ +

Returns the CANx Receive Error Counter (REC).

+
Note
In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception, the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state.
+
Parameters
+ + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
+
+
+
Return values
+ + +
CANReceive Error Counter.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_Init (CAN_TypeDef * CANx,
CAN_InitTypeDef * CAN_InitStruct 
)
+
+ +

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
CAN_InitStructpointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral.
+
+
+
Return values
+ + +
Constantindicates initialization succeed which will be CAN_InitStatus_Failed or CAN_InitStatus_Success.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CAN_ITConfig (CAN_TypeDef * CANx,
uint32_t CAN_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified CANx interrupts.

+
Parameters
+ + + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the CAN interrupt sources to be enabled or disabled. This parameter can be:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FMP0: FIFO 0 message pending Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FMP1: FIFO 1 message pending Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
NewStatenew state of the CAN interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_MessagePending (CAN_TypeDef * CANx,
uint8_t FIFONumber 
)
+
+ +

Returns the number of pending received messages.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberReceive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+
+
+
Return values
+ + +
NbMessage: which is the number of pending message.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_OperatingModeRequest (CAN_TypeDef * CANx,
uint8_t CAN_OperatingMode 
)
+
+ +

Selects the CAN Operation mode.

+
Parameters
+ + +
CAN_OperatingModeCAN Operating Mode. This parameter can be one of CAN_OperatingMode_TypeDef enumeration.
+
+
+
Return values
+ + +
statusof the requested mode which can be
    +
  • CAN_ModeStatus_Failed: CAN failed entering the specific mode
    • +
  • CAN_ModeStatus_Success: CAN Succeed entering the specific mode
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CAN_Receive (CAN_TypeDef * CANx,
uint8_t FIFONumber,
CanRxMsg * RxMessage 
)
+
+ +

Receives a correct CAN frame.

+
Parameters
+ + + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberReceive FIFO number, CAN_FIFO0 or CAN_FIFO1.
RxMessagepointer to a structure receive frame which contains CAN Id, CAN DLC, CAN data and FMI number.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
+
+ +

Select the start bank filter for slave CAN.

+
Parameters
+ + +
CAN_BankNumberSelect the start slave bank filter from 1..27.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_Sleep (CAN_TypeDef * CANx)
+
+ +

Enters the Sleep (low power) mode.

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
CAN_Sleep_Okif sleep entered, CAN_Sleep_Failed otherwise.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_StructInit (CAN_InitTypeDef * CAN_InitStruct)
+
+ +

Fills each CAN_InitStruct member with its default value.

+
Parameters
+ + +
CAN_InitStructpointer to a CAN_InitTypeDef structure which ill be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_Transmit (CAN_TypeDef * CANx,
CanTxMsg * TxMessage 
)
+
+ +

Initiates and transmits a CAN frame message.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
TxMessagepointer to a structure which contains CAN Id, CAN DLC and CAN data.
+
+
+
Return values
+ + +
Thenumber of the mailbox that is used for transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_TransmitStatus (CAN_TypeDef * CANx,
uint8_t TransmitMailbox 
)
+
+ +

Checks the transmission status of a CAN Frame.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
TransmitMailboxthe number of the mailbox that is used for transmission.
+
+
+
Return values
+ + +
CAN_TxStatus_Okif the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_TTComModeCmd (CAN_TypeDef * CANx,
FunctionalState NewState 
)
+
+ +

Enables or disables the CAN Time TriggerOperation communication mode.

+
Note
DLC must be programmed as 8 in order Time Stamp (2 bytes) to be sent over the CAN bus.
+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
NewStateMode new state. This parameter can be: ENABLE or DISABLE. When enabled, Time stamp (TIME[15:0]) value is sent in the last two data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] in data byte 7.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_WakeUp (CAN_TypeDef * CANx)
+
+ +

Wakes up the CAN peripheral from sleep mode .

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
CAN_WakeUp_Okif sleep mode left, CAN_WakeUp_Failed otherwise.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n.map b/group___c_a_n.map new file mode 100644 index 0000000..a586d94 --- /dev/null +++ b/group___c_a_n.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___c_a_n.md5 b/group___c_a_n.md5 new file mode 100644 index 0000000..0e1de55 --- /dev/null +++ b/group___c_a_n.md5 @@ -0,0 +1 @@ +bd84bfbc6f73279dedaf1dff92d979cc \ No newline at end of file diff --git a/group___c_a_n.png b/group___c_a_n.png new file mode 100644 index 0000000..7933d48 Binary files /dev/null and b/group___c_a_n.png differ diff --git a/group___c_a_n___error___code__constants.html b/group___c_a_n___error___code__constants.html new file mode 100644 index 0000000..f8e36d3 --- /dev/null +++ b/group___c_a_n___error___code__constants.html @@ -0,0 +1,227 @@ + + + + + + +discoverpixy: CAN_Error_Code_constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_Error_Code_constants
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_Error_Code_constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_ErrorCode_NoErr   ((uint8_t)0x00)
 
#define CAN_ErrorCode_StuffErr   ((uint8_t)0x10)
 
#define CAN_ErrorCode_FormErr   ((uint8_t)0x20)
 
#define CAN_ErrorCode_ACKErr   ((uint8_t)0x30)
 
#define CAN_ErrorCode_BitRecessiveErr   ((uint8_t)0x40)
 
#define CAN_ErrorCode_BitDominantErr   ((uint8_t)0x50)
 
#define CAN_ErrorCode_CRCErr   ((uint8_t)0x60)
 
#define CAN_ErrorCode_SoftwareSetErr   ((uint8_t)0x70)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_ErrorCode_ACKErr   ((uint8_t)0x30)
+
+

Acknowledgment Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_BitDominantErr   ((uint8_t)0x50)
+
+

Bit Dominant Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_BitRecessiveErr   ((uint8_t)0x40)
+
+

Bit Recessive Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_CRCErr   ((uint8_t)0x60)
+
+

CRC Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_FormErr   ((uint8_t)0x20)
+
+

Form Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_NoErr   ((uint8_t)0x00)
+
+

No Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_SoftwareSetErr   ((uint8_t)0x70)
+
+

Software Set Error

+ +
+
+ +
+
+ + + + +
#define CAN_ErrorCode_StuffErr   ((uint8_t)0x10)
+
+

Stuff Error

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___error___code__constants.map b/group___c_a_n___error___code__constants.map new file mode 100644 index 0000000..566e5b4 --- /dev/null +++ b/group___c_a_n___error___code__constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___error___code__constants.md5 b/group___c_a_n___error___code__constants.md5 new file mode 100644 index 0000000..ad479ee --- /dev/null +++ b/group___c_a_n___error___code__constants.md5 @@ -0,0 +1 @@ +de766add8a791abc27fe9772bf9428c1 \ No newline at end of file diff --git a/group___c_a_n___error___code__constants.png b/group___c_a_n___error___code__constants.png new file mode 100644 index 0000000..f5b99bb Binary files /dev/null and b/group___c_a_n___error___code__constants.png differ diff --git a/group___c_a_n___exported___constants.html b/group___c_a_n___exported___constants.html new file mode 100644 index 0000000..31c1c6f --- /dev/null +++ b/group___c_a_n___exported___constants.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: CAN_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
CAN_Exported_Constants
STM32F4xx_StdPeriph_Driver » CAN
+
+
+
+Collaboration diagram for CAN_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 CAN_InitStatus
 
 CAN_operating_mode
 
 CAN_operating_mode_status
 
 CAN_synchronisation_jump_width
 
 CAN_time_quantum_in_bit_segment_1
 
 CAN_time_quantum_in_bit_segment_2
 
 CAN_clock_prescaler
 
 CAN_filter_number
 
 CAN_filter_mode
 
 CAN_filter_scale
 
 CAN_filter_FIFO
 
 CAN_Start_bank_filter_for_slave_CAN
 
 CAN_Tx
 
 CAN_identifier_type
 
 CAN_remote_transmission_request
 
 CAN_transmit_constants
 
 CAN_receive_FIFO_number_constants
 
 CAN_sleep_constants
 
 CAN_wake_up_constants
 
 CAN_Error_Code_constants
 
 CAN_flags
 
 CAN_interrupts
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___exported___constants.map b/group___c_a_n___exported___constants.map new file mode 100644 index 0000000..adeee04 --- /dev/null +++ b/group___c_a_n___exported___constants.map @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___c_a_n___exported___constants.md5 b/group___c_a_n___exported___constants.md5 new file mode 100644 index 0000000..7ac7be7 --- /dev/null +++ b/group___c_a_n___exported___constants.md5 @@ -0,0 +1 @@ +5d01c572598c78d88b9738be3c022b5c \ No newline at end of file diff --git a/group___c_a_n___exported___constants.png b/group___c_a_n___exported___constants.png new file mode 100644 index 0000000..f7a1f65 Binary files /dev/null and b/group___c_a_n___exported___constants.png differ diff --git a/group___c_a_n___group1.html b/group___c_a_n___group1.html new file mode 100644 index 0000000..d183da4 --- /dev/null +++ b/group___c_a_n___group1.html @@ -0,0 +1,396 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CAN_DeInit (CAN_TypeDef *CANx)
 Deinitializes the CAN peripheral registers to their default reset values. More...
 
uint8_t CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
 Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct. More...
 
void CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
 Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct. More...
 
void CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
 Fills each CAN_InitStruct member with its default value. More...
 
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
 Select the start bank filter for slave CAN. More...
 
void CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the DBG Freeze for CAN. More...
 
void CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the CAN Time TriggerOperation communication mode. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+      (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum 
+          number of time quanta to perform resynchronization, the number of time 
+          quanta in Bit Segment 1 and 2 and many other modes. 
+          Refer to  @ref CAN_InitTypeDef  for more details.
+      (+) Configures the CAN reception filter.                                      
+      (+) Select the start bank filter for slave CAN.
+      (+) Enables or disables the Debug Freeze mode for CAN
+      (+)Enables or disables the CAN Time Trigger Operation communication mode

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_DBGFreeze (CAN_TypeDef * CANx,
FunctionalState NewState 
)
+
+ +

Enables or disables the DBG Freeze for CAN.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
NewStatenew state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFOs can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_DeInit (CAN_TypeDef * CANx)
+
+ +

Deinitializes the CAN peripheral registers to their default reset values.

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
None.
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void CAN_FilterInit (CAN_FilterInitTypeDef * CAN_FilterInitStruct)
+
+ +

Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

+
Parameters
+ + +
CAN_FilterInitStructpointer to a CAN_FilterInitTypeDef structure that contains the configuration information.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_Init (CAN_TypeDef * CANx,
CAN_InitTypeDef * CAN_InitStruct 
)
+
+ +

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
CAN_InitStructpointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral.
+
+
+
Return values
+ + +
Constantindicates initialization succeed which will be CAN_InitStatus_Failed or CAN_InitStatus_Success.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
+
+ +

Select the start bank filter for slave CAN.

+
Parameters
+ + +
CAN_BankNumberSelect the start slave bank filter from 1..27.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CAN_StructInit (CAN_InitTypeDef * CAN_InitStruct)
+
+ +

Fills each CAN_InitStruct member with its default value.

+
Parameters
+ + +
CAN_InitStructpointer to a CAN_InitTypeDef structure which ill be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_TTComModeCmd (CAN_TypeDef * CANx,
FunctionalState NewState 
)
+
+ +

Enables or disables the CAN Time TriggerOperation communication mode.

+
Note
DLC must be programmed as 8 in order Time Stamp (2 bytes) to be sent over the CAN bus.
+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
NewStateMode new state. This parameter can be: ENABLE or DISABLE. When enabled, Time stamp (TIME[15:0]) value is sent in the last two data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] in data byte 7.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group1.map b/group___c_a_n___group1.map new file mode 100644 index 0000000..a241b57 --- /dev/null +++ b/group___c_a_n___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group1.md5 b/group___c_a_n___group1.md5 new file mode 100644 index 0000000..767d6b1 --- /dev/null +++ b/group___c_a_n___group1.md5 @@ -0,0 +1 @@ +63a4b27cb16eba465ee1cada9530d11c \ No newline at end of file diff --git a/group___c_a_n___group1.png b/group___c_a_n___group1.png new file mode 100644 index 0000000..3d8f45c Binary files /dev/null and b/group___c_a_n___group1.png differ diff --git a/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.map b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.map new file mode 100644 index 0000000..48a5b18 --- /dev/null +++ b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 new file mode 100644 index 0000000..c070298 --- /dev/null +++ b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 @@ -0,0 +1 @@ +158f2dd1050c18711f6807efb25f733f \ No newline at end of file diff --git a/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.png b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.png new file mode 100644 index 0000000..cb4dea8 Binary files /dev/null and b/group___c_a_n___group1_ga002b74cd69574a14b17ad445090245cd_cgraph.png differ diff --git a/group___c_a_n___group2.html b/group___c_a_n___group2.html new file mode 100644 index 0000000..379d9b9 --- /dev/null +++ b/group___c_a_n___group2.html @@ -0,0 +1,249 @@ + + + + + + +discoverpixy: CAN Frames Transmission functions + + + + + + + + + + +
+
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+
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+ +
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+Functions
+
+
CAN Frames Transmission functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

CAN Frames Transmission functions. +More...

+
+Collaboration diagram for CAN Frames Transmission functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

uint8_t CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
 Initiates and transmits a CAN frame message. More...
 
uint8_t CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
 Checks the transmission status of a CAN Frame. More...
 
void CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
 Cancels a transmit request. More...
 
+

Detailed Description

+

CAN Frames Transmission functions.

+
 ===============================================================================
+                ##### CAN Frames Transmission functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+      (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
+      (+) Check the transmission status of a CAN Frame
+      (+) Cancel a transmit request

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_CancelTransmit (CAN_TypeDef * CANx,
uint8_t Mailbox 
)
+
+ +

Cancels a transmit request.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
MailboxMailbox number.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_Transmit (CAN_TypeDef * CANx,
CanTxMsg * TxMessage 
)
+
+ +

Initiates and transmits a CAN frame message.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
TxMessagepointer to a structure which contains CAN Id, CAN DLC and CAN data.
+
+
+
Return values
+ + +
Thenumber of the mailbox that is used for transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_TransmitStatus (CAN_TypeDef * CANx,
uint8_t TransmitMailbox 
)
+
+ +

Checks the transmission status of a CAN Frame.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
TransmitMailboxthe number of the mailbox that is used for transmission.
+
+
+
Return values
+ + +
CAN_TxStatus_Okif the CAN driver transmits the message, CAN_TxStatus_Failed in an other case.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group2.map b/group___c_a_n___group2.map new file mode 100644 index 0000000..7721362 --- /dev/null +++ b/group___c_a_n___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group2.md5 b/group___c_a_n___group2.md5 new file mode 100644 index 0000000..69e5167 --- /dev/null +++ b/group___c_a_n___group2.md5 @@ -0,0 +1 @@ +d1ff22bf6432c8e338152ad65de94e5c \ No newline at end of file diff --git a/group___c_a_n___group2.png b/group___c_a_n___group2.png new file mode 100644 index 0000000..b3538c0 Binary files /dev/null and b/group___c_a_n___group2.png differ diff --git a/group___c_a_n___group3.html b/group___c_a_n___group3.html new file mode 100644 index 0000000..a78c703 --- /dev/null +++ b/group___c_a_n___group3.html @@ -0,0 +1,256 @@ + + + + + + +discoverpixy: CAN Frames Reception functions + + + + + + + + + + +
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+Functions
+
+
CAN Frames Reception functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

CAN Frames Reception functions. +More...

+
+Collaboration diagram for CAN Frames Reception functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
 Receives a correct CAN frame. More...
 
void CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Releases the specified receive FIFO. More...
 
uint8_t CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Returns the number of pending received messages. More...
 
+

Detailed Description

+

CAN Frames Reception functions.

+
 ===============================================================================
+                ##### CAN Frames Reception functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+      (+) Receive a correct CAN frame
+      (+) Release a specified receive FIFO (2 FIFOs are available)
+      (+) Return the number of the pending received CAN frames

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_FIFORelease (CAN_TypeDef * CANx,
uint8_t FIFONumber 
)
+
+ +

Releases the specified receive FIFO.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberFIFO to release, CAN_FIFO0 or CAN_FIFO1.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_MessagePending (CAN_TypeDef * CANx,
uint8_t FIFONumber 
)
+
+ +

Returns the number of pending received messages.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberReceive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+
+
+
Return values
+ + +
NbMessage: which is the number of pending message.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CAN_Receive (CAN_TypeDef * CANx,
uint8_t FIFONumber,
CanRxMsg * RxMessage 
)
+
+ +

Receives a correct CAN frame.

+
Parameters
+ + + + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
FIFONumberReceive FIFO number, CAN_FIFO0 or CAN_FIFO1.
RxMessagepointer to a structure receive frame which contains CAN Id, CAN DLC, CAN data and FMI number.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group3.map b/group___c_a_n___group3.map new file mode 100644 index 0000000..d9785b0 --- /dev/null +++ b/group___c_a_n___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group3.md5 b/group___c_a_n___group3.md5 new file mode 100644 index 0000000..e75c841 --- /dev/null +++ b/group___c_a_n___group3.md5 @@ -0,0 +1 @@ +e6a6ec0c4d2e259039b39714f46fa957 \ No newline at end of file diff --git a/group___c_a_n___group3.png b/group___c_a_n___group3.png new file mode 100644 index 0000000..d68ce52 Binary files /dev/null and b/group___c_a_n___group3.png differ diff --git a/group___c_a_n___group4.html b/group___c_a_n___group4.html new file mode 100644 index 0000000..58638c7 --- /dev/null +++ b/group___c_a_n___group4.html @@ -0,0 +1,230 @@ + + + + + + +discoverpixy: CAN Operation modes functions + + + + + + + + + + +
+
+ + + + + + +
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+Functions
+
+
CAN Operation modes functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

CAN Operation modes functions. +More...

+
+Collaboration diagram for CAN Operation modes functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

uint8_t CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
 Selects the CAN Operation mode. More...
 
uint8_t CAN_Sleep (CAN_TypeDef *CANx)
 Enters the Sleep (low power) mode. More...
 
uint8_t CAN_WakeUp (CAN_TypeDef *CANx)
 Wakes up the CAN peripheral from sleep mode . More...
 
+

Detailed Description

+

CAN Operation modes functions.

+
 ===============================================================================
+                    ##### CAN Operation modes functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to select the CAN Operation modes
+      (+) sleep mode
+      (+) normal mode 
+      (+) initialization mode

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t CAN_OperatingModeRequest (CAN_TypeDef * CANx,
uint8_t CAN_OperatingMode 
)
+
+ +

Selects the CAN Operation mode.

+
Parameters
+ + +
CAN_OperatingModeCAN Operating Mode. This parameter can be one of CAN_OperatingMode_TypeDef enumeration.
+
+
+
Return values
+ + +
statusof the requested mode which can be
    +
  • CAN_ModeStatus_Failed: CAN failed entering the specific mode
    • +
  • CAN_ModeStatus_Success: CAN Succeed entering the specific mode
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_Sleep (CAN_TypeDef * CANx)
+
+ +

Enters the Sleep (low power) mode.

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
CAN_Sleep_Okif sleep entered, CAN_Sleep_Failed otherwise.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_WakeUp (CAN_TypeDef * CANx)
+
+ +

Wakes up the CAN peripheral from sleep mode .

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
CAN_WakeUp_Okif sleep mode left, CAN_WakeUp_Failed otherwise.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group4.map b/group___c_a_n___group4.map new file mode 100644 index 0000000..5bba106 --- /dev/null +++ b/group___c_a_n___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group4.md5 b/group___c_a_n___group4.md5 new file mode 100644 index 0000000..5fb9512 --- /dev/null +++ b/group___c_a_n___group4.md5 @@ -0,0 +1 @@ +bffb0778792f32f6071f308991485e36 \ No newline at end of file diff --git a/group___c_a_n___group4.png b/group___c_a_n___group4.png new file mode 100644 index 0000000..24093d5 Binary files /dev/null and b/group___c_a_n___group4.png differ diff --git a/group___c_a_n___group5.html b/group___c_a_n___group5.html new file mode 100644 index 0000000..485b9ec --- /dev/null +++ b/group___c_a_n___group5.html @@ -0,0 +1,231 @@ + + + + + + +discoverpixy: CAN Bus Error management functions + + + + + + + + + + +
+
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+Functions
+
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CAN Bus Error management functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

CAN Bus Error management functions. +More...

+
+Collaboration diagram for CAN Bus Error management functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

uint8_t CAN_GetLastErrorCode (CAN_TypeDef *CANx)
 Returns the CANx's last error code (LEC). More...
 
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
 Returns the CANx Receive Error Counter (REC). More...
 
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
 Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). More...
 
+

Detailed Description

+

CAN Bus Error management functions.

+
 ===============================================================================
+                ##### CAN Bus Error management functions #####
+ ===============================================================================  
+    [..] This section provides functions allowing to 
+      (+) Return the CANx's last error code (LEC)
+      (+) Return the CANx Receive Error Counter (REC)
+      (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+   
+      -@- If TEC is greater than 255, The CAN is in bus-off state.
+      -@- if REC or TEC are greater than 96, an Error warning flag occurs.
+      -@- if REC or TEC are greater than 127, an Error Passive Flag occurs.

Function Documentation

+ +
+
+ + + + + + + + +
uint8_t CAN_GetLastErrorCode (CAN_TypeDef * CANx)
+
+ +

Returns the CANx's last error code (LEC).

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to select the CAN peripheral.
+
+
+
Return values
+ + +
Errorcode:
    +
  • CAN_ERRORCODE_NoErr: No Error
    • +
  • CAN_ERRORCODE_StuffErr: Stuff Error
    • +
  • CAN_ERRORCODE_FormErr: Form Error
    • +
  • CAN_ERRORCODE_ACKErr : Acknowledgment Error
    • +
  • CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
    • +
  • CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
    • +
  • CAN_ERRORCODE_CRCErr: CRC Error
    • +
  • CAN_ERRORCODE_SoftwareSetErr: Software Set Error
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef * CANx)
+
+ +

Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).

+
Parameters
+ + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
+
+
+
Return values
+ + +
LSBof the 9-bit CAN Transmit Error Counter.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef * CANx)
+
+ +

Returns the CANx Receive Error Counter (REC).

+
Note
In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception, the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state.
+
Parameters
+ + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
+
+
+
Return values
+ + +
CANReceive Error Counter.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group5.map b/group___c_a_n___group5.map new file mode 100644 index 0000000..3428e30 --- /dev/null +++ b/group___c_a_n___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group5.md5 b/group___c_a_n___group5.md5 new file mode 100644 index 0000000..f9c8e5f --- /dev/null +++ b/group___c_a_n___group5.md5 @@ -0,0 +1 @@ +afcf90fa5f4d9976a9fbdd939472c22c \ No newline at end of file diff --git a/group___c_a_n___group5.png b/group___c_a_n___group5.png new file mode 100644 index 0000000..6c45cb1 Binary files /dev/null and b/group___c_a_n___group5.png differ diff --git a/group___c_a_n___group6.html b/group___c_a_n___group6.html new file mode 100644 index 0000000..0167deb --- /dev/null +++ b/group___c_a_n___group6.html @@ -0,0 +1,569 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
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+Functions
+
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Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » CAN » CAN_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
 Enables or disables the specified CANx interrupts. More...
 
FlagStatus CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Checks whether the specified CAN flag is set or not. More...
 
void CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Clears the CAN's pending flags. More...
 
ITStatus CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Checks whether the specified CANx interrupt has occurred or not. More...
 
void CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Clears the CANx's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+     [..] This section provides functions allowing to configure the CAN Interrupts 
+          and to get the status and clear flags and Interrupts pending bits.
+  
+          The CAN provides 14 Interrupts sources and 15 Flags:
+
+   
+  *** Flags ***
+  =============
+    [..] The 15 flags can be divided on 4 groups: 
+
+      (+) Transmit Flags
+        (++) CAN_FLAG_RQCP0, 
+        (++) CAN_FLAG_RQCP1, 
+        (++) CAN_FLAG_RQCP2  : Request completed MailBoxes 0, 1 and 2  Flags
+                               Set when when the last request (transmit or abort)
+                               has been performed. 
+
+      (+) Receive Flags
+
+
+        (++) CAN_FLAG_FMP0,
+        (++) CAN_FLAG_FMP1   : FIFO 0 and 1 Message Pending Flags 
+                               set to signal that messages are pending in the receive 
+                               FIFO.
+                               These Flags are cleared only by hardware. 
+
+        (++) CAN_FLAG_FF0,
+        (++) CAN_FLAG_FF1    : FIFO 0 and 1 Full Flags
+                               set when three messages are stored in the selected 
+                               FIFO.                        
+
+        (++) CAN_FLAG_FOV0              
+        (++) CAN_FLAG_FOV1   : FIFO 0 and 1 Overrun Flags
+                               set when a new message has been received and passed 
+                               the filter while the FIFO was full.         
+
+      (+) Operating Mode Flags
+
+        (++) CAN_FLAG_WKU    : Wake up Flag
+                               set to signal that a SOF bit has been detected while 
+                               the CAN hardware was in Sleep mode. 
+        
+        (++) CAN_FLAG_SLAK   : Sleep acknowledge Flag
+                               Set to signal that the CAN has entered Sleep Mode. 
+    
+      (+) Error Flags
+
+        (++) CAN_FLAG_EWG    : Error Warning Flag
+                               Set when the warning limit has been reached (Receive 
+                               Error Counter or Transmit Error Counter greater than 96). 
+                               This Flag is cleared only by hardware.
+                            
+        (++) CAN_FLAG_EPV    : Error Passive Flag
+                               Set when the Error Passive limit has been reached 
+                               (Receive Error Counter or Transmit Error Counter 
+                               greater than 127).
+                               This Flag is cleared only by hardware.
+                             
+        (++) CAN_FLAG_BOF    : Bus-Off Flag
+                               set when CAN enters the bus-off state. The bus-off 
+                               state is entered on TEC overflow, greater than 255.
+                               This Flag is cleared only by hardware.
+                                   
+        (++) CAN_FLAG_LEC    : Last error code Flag
+                               set If a message has been transferred (reception or
+                               transmission) with error, and the error code is hold.              
+                           
+  *** Interrupts ***
+  ==================
+    [..] The 14 interrupts can be divided on 4 groups: 
+  
+      (+) Transmit interrupt
+  
+        (++) CAN_IT_TME   :  Transmit mailbox empty Interrupt
+                             if enabled, this interrupt source is pending when 
+                             no transmit request are pending for Tx mailboxes.      
+
+      (+) Receive Interrupts
+         
+        (++) CAN_IT_FMP0,
+        (++) CAN_IT_FMP1    :  FIFO 0 and FIFO1 message pending Interrupts
+                               if enabled, these interrupt sources are pending 
+                               when messages are pending in the receive FIFO.
+                               The corresponding interrupt pending bits are cleared 
+                               only by hardware.
+                
+        (++) CAN_IT_FF0,              
+        (++) CAN_IT_FF1     :  FIFO 0 and FIFO1 full Interrupts
+                               if enabled, these interrupt sources are pending 
+                               when three messages are stored in the selected FIFO.
+        
+        (++) CAN_IT_FOV0,        
+        (++) CAN_IT_FOV1    :  FIFO 0 and FIFO1 overrun Interrupts        
+                               if enabled, these interrupt sources are pending 
+                               when a new message has been received and passed 
+                               the filter while the FIFO was full.
+
+      (+) Operating Mode Interrupts
+         
+        (++) CAN_IT_WKU     :  Wake-up Interrupt
+                               if enabled, this interrupt source is pending when 
+                               a SOF bit has been detected while the CAN hardware 
+                               was in Sleep mode.
+                                  
+        (++) CAN_IT_SLK     :  Sleep acknowledge Interrupt
+                               if enabled, this interrupt source is pending when 
+                               the CAN has entered Sleep Mode.       
+
+      (+) Error Interrupts 
+        
+        (++) CAN_IT_EWG     :  Error warning Interrupt 
+                               if enabled, this interrupt source is pending when
+                               the warning limit has been reached (Receive Error 
+                               Counter or Transmit Error Counter=96). 
+                               
+        (++) CAN_IT_EPV     :  Error passive Interrupt        
+                               if enabled, this interrupt source is pending when
+                               the Error Passive limit has been reached (Receive 
+                               Error Counter or Transmit Error Counter>127).
+                          
+        (++) CAN_IT_BOF     :  Bus-off Interrupt
+                               if enabled, this interrupt source is pending when
+                               CAN enters the bus-off state. The bus-off state is 
+                               entered on TEC overflow, greater than 255.
+                               This Flag is cleared only by hardware.
+                                  
+        (++) CAN_IT_LEC     :  Last error code Interrupt        
+                               if enabled, this interrupt source is pending  when
+                               a message has been transferred (reception or
+                               transmission) with error, and the error code is hold.
+                          
+        (++) CAN_IT_ERR     :  Error Interrupt
+                               if enabled, this interrupt source is pending when 
+                               an error condition is pending.      
+                      
+    [..] Managing the CAN controller events :
+ 
+         The user should identify which mode will be used in his application to 
+         manage the CAN controller events: Polling mode or Interrupt mode.
+  
+      (#) In the Polling Mode it is advised to use the following functions:
+        (++) CAN_GetFlagStatus() : to check if flags events occur. 
+        (++) CAN_ClearFlag()     : to clear the flags events.
+  
+
+  
+      (#) In the Interrupt Mode it is advised to use the following functions:
+        (++) CAN_ITConfig()       : to enable or disable the interrupt source.
+        (++) CAN_GetITStatus()    : to check if Interrupt occurs.
+        (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit 
+            (corresponding Flag).
+        -@@-  This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts 
+             pending bits since there are cleared only by hardware.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_ClearFlag (CAN_TypeDef * CANx,
uint32_t CAN_FLAG 
)
+
+ +

Clears the CAN's pending flags.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAGspecifies the flag to clear. This parameter can be one of the following values:
    +
  • CAN_FLAG_RQCP0: Request MailBox0 Flag
    • +
  • CAN_FLAG_RQCP1: Request MailBox1 Flag
    • +
  • CAN_FLAG_RQCP2: Request MailBox2 Flag
    • +
  • CAN_FLAG_FF0: FIFO 0 Full Flag
    • +
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
    • +
  • CAN_FLAG_FF1: FIFO 1 Full Flag
    • +
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
    • +
  • CAN_FLAG_WKU: Wake up Flag
    • +
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
    • +
  • CAN_FLAG_LEC: Last error code Flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CAN_ClearITPendingBit (CAN_TypeDef * CANx,
uint32_t CAN_IT 
)
+
+ +

Clears the CANx's interrupt pending bits.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus CAN_GetFlagStatus (CAN_TypeDef * CANx,
uint32_t CAN_FLAG 
)
+
+ +

Checks whether the specified CAN flag is set or not.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • CAN_FLAG_RQCP0: Request MailBox0 Flag
    • +
  • CAN_FLAG_RQCP1: Request MailBox1 Flag
    • +
  • CAN_FLAG_RQCP2: Request MailBox2 Flag
    • +
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
    • +
  • CAN_FLAG_FF0: FIFO 0 Full Flag
    • +
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
    • +
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
    • +
  • CAN_FLAG_FF1: FIFO 1 Full Flag
    • +
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
    • +
  • CAN_FLAG_WKU: Wake up Flag
    • +
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
    • +
  • CAN_FLAG_EWG: Error Warning Flag
    • +
  • CAN_FLAG_EPV: Error Passive Flag
    • +
  • CAN_FLAG_BOF: Bus-Off Flag
    • +
  • CAN_FLAG_LEC: Last error code Flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of CAN_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus CAN_GetITStatus (CAN_TypeDef * CANx,
uint32_t CAN_IT 
)
+
+ +

Checks whether the specified CANx interrupt has occurred or not.

+
Parameters
+ + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the CAN interrupt source to check. This parameter can be one of the following values:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FMP0: FIFO 0 message pending Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FMP1: FIFO 1 message pending Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
+
+
+
Return values
+ + +
Thecurrent state of CAN_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void CAN_ITConfig (CAN_TypeDef * CANx,
uint32_t CAN_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified CANx interrupts.

+
Parameters
+ + + + +
CANxwhere x can be 1 or 2 to to select the CAN peripheral.
CAN_ITspecifies the CAN interrupt sources to be enabled or disabled. This parameter can be:
    +
  • CAN_IT_TME: Transmit mailbox empty Interrupt
    • +
  • CAN_IT_FMP0: FIFO 0 message pending Interrupt
    • +
  • CAN_IT_FF0: FIFO 0 full Interrupt
    • +
  • CAN_IT_FOV0: FIFO 0 overrun Interrupt
    • +
  • CAN_IT_FMP1: FIFO 1 message pending Interrupt
    • +
  • CAN_IT_FF1: FIFO 1 full Interrupt
    • +
  • CAN_IT_FOV1: FIFO 1 overrun Interrupt
    • +
  • CAN_IT_WKU: Wake-up Interrupt
    • +
  • CAN_IT_SLK: Sleep acknowledge Interrupt
    • +
  • CAN_IT_EWG: Error warning Interrupt
    • +
  • CAN_IT_EPV: Error passive Interrupt
    • +
  • CAN_IT_BOF: Bus-off Interrupt
    • +
  • CAN_IT_LEC: Last error code Interrupt
    • +
  • CAN_IT_ERR: Error Interrupt
    • +
+
NewStatenew state of the CAN interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___group6.map b/group___c_a_n___group6.map new file mode 100644 index 0000000..2060352 --- /dev/null +++ b/group___c_a_n___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___group6.md5 b/group___c_a_n___group6.md5 new file mode 100644 index 0000000..80a7ade --- /dev/null +++ b/group___c_a_n___group6.md5 @@ -0,0 +1 @@ +42c4b86e787ba8a80b3b8d226405d965 \ No newline at end of file diff --git a/group___c_a_n___group6.png b/group___c_a_n___group6.png new file mode 100644 index 0000000..37bd8a1 Binary files /dev/null and b/group___c_a_n___group6.png differ diff --git a/group___c_a_n___init_status.html b/group___c_a_n___init_status.html new file mode 100644 index 0000000..cf9f48f --- /dev/null +++ b/group___c_a_n___init_status.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: CAN_InitStatus + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ +
+
+ + +
+ +
+ +
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+Macros
+
+
CAN_InitStatus
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_InitStatus:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define CAN_InitStatus_Failed   ((uint8_t)0x00)
 
#define CAN_InitStatus_Success   ((uint8_t)0x01)
 
+#define CANINITFAILED   CAN_InitStatus_Failed
 
+#define CANINITOK   CAN_InitStatus_Success
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_InitStatus_Failed   ((uint8_t)0x00)
+
+

CAN initialization failed

+ +
+
+ +
+
+ + + + +
#define CAN_InitStatus_Success   ((uint8_t)0x01)
+
+

CAN initialization OK

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___init_status.map b/group___c_a_n___init_status.map new file mode 100644 index 0000000..ec4c15e --- /dev/null +++ b/group___c_a_n___init_status.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___init_status.md5 b/group___c_a_n___init_status.md5 new file mode 100644 index 0000000..08d1270 --- /dev/null +++ b/group___c_a_n___init_status.md5 @@ -0,0 +1 @@ +37595789ce2584fd6a8ca3a43f188c4e \ No newline at end of file diff --git a/group___c_a_n___init_status.png b/group___c_a_n___init_status.png new file mode 100644 index 0000000..6bc9993 Binary files /dev/null and b/group___c_a_n___init_status.png differ diff --git a/group___c_a_n___private___functions.html b/group___c_a_n___private___functions.html new file mode 100644 index 0000000..4662243 --- /dev/null +++ b/group___c_a_n___private___functions.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: CAN_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
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+Modules
+
+
CAN_Private_Functions
STM32F4xx_StdPeriph_Driver » CAN
+
+
+
+Collaboration diagram for CAN_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 CAN Frames Transmission functions
 CAN Frames Transmission functions.
 
 CAN Frames Reception functions
 CAN Frames Reception functions.
 
 CAN Operation modes functions
 CAN Operation modes functions.
 
 CAN Bus Error management functions
 CAN Bus Error management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___private___functions.map b/group___c_a_n___private___functions.map new file mode 100644 index 0000000..fedfffe --- /dev/null +++ b/group___c_a_n___private___functions.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/group___c_a_n___private___functions.md5 b/group___c_a_n___private___functions.md5 new file mode 100644 index 0000000..8eca6b7 --- /dev/null +++ b/group___c_a_n___private___functions.md5 @@ -0,0 +1 @@ +bed008f7075d9a5f1f7252466ee96ea7 \ No newline at end of file diff --git a/group___c_a_n___private___functions.png b/group___c_a_n___private___functions.png new file mode 100644 index 0000000..9062f4e Binary files /dev/null and b/group___c_a_n___private___functions.png differ diff --git a/group___c_a_n___start__bank__filter__for__slave___c_a_n.html b/group___c_a_n___start__bank__filter__for__slave___c_a_n.html new file mode 100644 index 0000000..79788ea --- /dev/null +++ b/group___c_a_n___start__bank__filter__for__slave___c_a_n.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: CAN_Start_bank_filter_for_slave_CAN + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
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+Macros
+
+
CAN_Start_bank_filter_for_slave_CAN
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_Start_bank_filter_for_slave_CAN:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_CAN_BANKNUMBER(BANKNUMBER)   (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___start__bank__filter__for__slave___c_a_n.map b/group___c_a_n___start__bank__filter__for__slave___c_a_n.map new file mode 100644 index 0000000..1c282a8 --- /dev/null +++ b/group___c_a_n___start__bank__filter__for__slave___c_a_n.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___start__bank__filter__for__slave___c_a_n.md5 b/group___c_a_n___start__bank__filter__for__slave___c_a_n.md5 new file mode 100644 index 0000000..c4ddb96 --- /dev/null +++ b/group___c_a_n___start__bank__filter__for__slave___c_a_n.md5 @@ -0,0 +1 @@ +9c78ef4b4797d4c70ca2cff0ee4ee8b1 \ No newline at end of file diff --git a/group___c_a_n___start__bank__filter__for__slave___c_a_n.png b/group___c_a_n___start__bank__filter__for__slave___c_a_n.png new file mode 100644 index 0000000..e6bd91e Binary files /dev/null and b/group___c_a_n___start__bank__filter__for__slave___c_a_n.png differ diff --git a/group___c_a_n___tx.html b/group___c_a_n___tx.html new file mode 100644 index 0000000..c370125 --- /dev/null +++ b/group___c_a_n___tx.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: CAN_Tx + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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+ + +
+ +
+ +
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+Macros
+
+
CAN_Tx
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_Tx:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)   ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
 
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
 
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
 
+#define IS_CAN_DLC(DLC)   ((DLC) <= ((uint8_t)0x08))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n___tx.map b/group___c_a_n___tx.map new file mode 100644 index 0000000..1b1362e --- /dev/null +++ b/group___c_a_n___tx.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n___tx.md5 b/group___c_a_n___tx.md5 new file mode 100644 index 0000000..b2e46e7 --- /dev/null +++ b/group___c_a_n___tx.md5 @@ -0,0 +1 @@ +1c8c06bf6601d3b1214ec9b896cc5352 \ No newline at end of file diff --git a/group___c_a_n___tx.png b/group___c_a_n___tx.png new file mode 100644 index 0000000..f2fdc96 Binary files /dev/null and b/group___c_a_n___tx.png differ diff --git a/group___c_a_n__clock__prescaler.html b/group___c_a_n__clock__prescaler.html new file mode 100644 index 0000000..ab08d67 --- /dev/null +++ b/group___c_a_n__clock__prescaler.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: CAN_clock_prescaler + + + + + + + + + + +
+
+ + + + + + +
+
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+ + + + +
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+ +
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+Macros
+
+
CAN_clock_prescaler
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_clock_prescaler:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_CAN_PRESCALER(PRESCALER)   (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__clock__prescaler.map b/group___c_a_n__clock__prescaler.map new file mode 100644 index 0000000..340550f --- /dev/null +++ b/group___c_a_n__clock__prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__clock__prescaler.md5 b/group___c_a_n__clock__prescaler.md5 new file mode 100644 index 0000000..4b5272e --- /dev/null +++ b/group___c_a_n__clock__prescaler.md5 @@ -0,0 +1 @@ +3fcd2269445a88886833955f571c290e \ No newline at end of file diff --git a/group___c_a_n__clock__prescaler.png b/group___c_a_n__clock__prescaler.png new file mode 100644 index 0000000..a9ab78a Binary files /dev/null and b/group___c_a_n__clock__prescaler.png differ diff --git a/group___c_a_n__filter___f_i_f_o.html b/group___c_a_n__filter___f_i_f_o.html new file mode 100644 index 0000000..4c93d71 --- /dev/null +++ b/group___c_a_n__filter___f_i_f_o.html @@ -0,0 +1,163 @@ + + + + + + +discoverpixy: CAN_filter_FIFO + + + + + + + + + + +
+
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+ + +
+ +
+ +
+
+Macros
+
+
CAN_filter_FIFO
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_filter_FIFO:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define CAN_Filter_FIFO0   ((uint8_t)0x00)
 
#define CAN_Filter_FIFO1   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_FIFO(FIFO)
 
+#define CAN_FilterFIFO0   CAN_Filter_FIFO0
 
+#define CAN_FilterFIFO1   CAN_Filter_FIFO1
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_Filter_FIFO0   ((uint8_t)0x00)
+
+

Filter FIFO 0 assignment for filter x

+ +
+
+ +
+
+ + + + +
#define CAN_Filter_FIFO1   ((uint8_t)0x01)
+
+

Filter FIFO 1 assignment for filter x

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_FILTER_FIFO( FIFO)
+
+Value:
(((FIFO) == CAN_FilterFIFO0) || \
+
((FIFO) == CAN_FilterFIFO1))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__filter___f_i_f_o.map b/group___c_a_n__filter___f_i_f_o.map new file mode 100644 index 0000000..2a08e62 --- /dev/null +++ b/group___c_a_n__filter___f_i_f_o.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__filter___f_i_f_o.md5 b/group___c_a_n__filter___f_i_f_o.md5 new file mode 100644 index 0000000..0fc7557 --- /dev/null +++ b/group___c_a_n__filter___f_i_f_o.md5 @@ -0,0 +1 @@ +61789c7006bbd939a6eaf08740472bca \ No newline at end of file diff --git a/group___c_a_n__filter___f_i_f_o.png b/group___c_a_n__filter___f_i_f_o.png new file mode 100644 index 0000000..41cb9b4 Binary files /dev/null and b/group___c_a_n__filter___f_i_f_o.png differ diff --git a/group___c_a_n__filter__mode.html b/group___c_a_n__filter__mode.html new file mode 100644 index 0000000..8d0d13a --- /dev/null +++ b/group___c_a_n__filter__mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: CAN_filter_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_filter_mode
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_filter_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define CAN_FilterMode_IdMask   ((uint8_t)0x00)
 
#define CAN_FilterMode_IdList   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_FilterMode_IdList   ((uint8_t)0x01)
+
+

identifier list mode

+ +
+
+ +
+
+ + + + +
#define CAN_FilterMode_IdMask   ((uint8_t)0x00)
+
+

identifier/mask mode

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_FILTER_MODE( MODE)
+
+Value:
(((MODE) == CAN_FilterMode_IdMask) || \
+
((MODE) == CAN_FilterMode_IdList))
+
CAN_FilterMode_IdList
#define CAN_FilterMode_IdList
Definition: stm32f4xx_can.h:332
+
CAN_FilterMode_IdMask
#define CAN_FilterMode_IdMask
Definition: stm32f4xx_can.h:331
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__filter__mode.map b/group___c_a_n__filter__mode.map new file mode 100644 index 0000000..23e8905 --- /dev/null +++ b/group___c_a_n__filter__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__filter__mode.md5 b/group___c_a_n__filter__mode.md5 new file mode 100644 index 0000000..230aaf7 --- /dev/null +++ b/group___c_a_n__filter__mode.md5 @@ -0,0 +1 @@ +5dd3ea08931ffe5d84bd1b2b52bc31a4 \ No newline at end of file diff --git a/group___c_a_n__filter__mode.png b/group___c_a_n__filter__mode.png new file mode 100644 index 0000000..72f07b6 Binary files /dev/null and b/group___c_a_n__filter__mode.png differ diff --git a/group___c_a_n__filter__number.html b/group___c_a_n__filter__number.html new file mode 100644 index 0000000..f4c5173 --- /dev/null +++ b/group___c_a_n__filter__number.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: CAN_filter_number + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_filter_number
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_filter_number:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_CAN_FILTER_NUMBER(NUMBER)   ((NUMBER) <= 27)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__filter__number.map b/group___c_a_n__filter__number.map new file mode 100644 index 0000000..ed99cee --- /dev/null +++ b/group___c_a_n__filter__number.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__filter__number.md5 b/group___c_a_n__filter__number.md5 new file mode 100644 index 0000000..3e75bd3 --- /dev/null +++ b/group___c_a_n__filter__number.md5 @@ -0,0 +1 @@ +391aabf09b5ab13d4d67dbbfc94d6992 \ No newline at end of file diff --git a/group___c_a_n__filter__number.png b/group___c_a_n__filter__number.png new file mode 100644 index 0000000..415ed50 Binary files /dev/null and b/group___c_a_n__filter__number.png differ diff --git a/group___c_a_n__filter__scale.html b/group___c_a_n__filter__scale.html new file mode 100644 index 0000000..1a18fe4 --- /dev/null +++ b/group___c_a_n__filter__scale.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: CAN_filter_scale + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_filter_scale
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_filter_scale:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define CAN_FilterScale_16bit   ((uint8_t)0x00)
 
#define CAN_FilterScale_32bit   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_SCALE(SCALE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_FilterScale_16bit   ((uint8_t)0x00)
+
+

Two 16-bit filters

+ +
+
+ +
+
+ + + + +
#define CAN_FilterScale_32bit   ((uint8_t)0x01)
+
+

One 32-bit filter

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_FILTER_SCALE( SCALE)
+
+Value:
(((SCALE) == CAN_FilterScale_16bit) || \
+
((SCALE) == CAN_FilterScale_32bit))
+
CAN_FilterScale_32bit
#define CAN_FilterScale_32bit
Definition: stm32f4xx_can.h:344
+
CAN_FilterScale_16bit
#define CAN_FilterScale_16bit
Definition: stm32f4xx_can.h:343
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__filter__scale.map b/group___c_a_n__filter__scale.map new file mode 100644 index 0000000..e1fa387 --- /dev/null +++ b/group___c_a_n__filter__scale.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__filter__scale.md5 b/group___c_a_n__filter__scale.md5 new file mode 100644 index 0000000..eff7402 --- /dev/null +++ b/group___c_a_n__filter__scale.md5 @@ -0,0 +1 @@ +759c520d0dde40c1d83d7359fe9e846c \ No newline at end of file diff --git a/group___c_a_n__filter__scale.png b/group___c_a_n__filter__scale.png new file mode 100644 index 0000000..0434894 Binary files /dev/null and b/group___c_a_n__filter__scale.png differ diff --git a/group___c_a_n__flags.html b/group___c_a_n__flags.html new file mode 100644 index 0000000..76085e2 --- /dev/null +++ b/group___c_a_n__flags.html @@ -0,0 +1,406 @@ + + + + + + +discoverpixy: CAN_flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_flags
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_FLAG_RQCP0   ((uint32_t)0x38000001)
 
#define CAN_FLAG_RQCP1   ((uint32_t)0x38000100)
 
#define CAN_FLAG_RQCP2   ((uint32_t)0x38010000)
 
#define CAN_FLAG_FMP0   ((uint32_t)0x12000003)
 
#define CAN_FLAG_FF0   ((uint32_t)0x32000008)
 
#define CAN_FLAG_FOV0   ((uint32_t)0x32000010)
 
#define CAN_FLAG_FMP1   ((uint32_t)0x14000003)
 
#define CAN_FLAG_FF1   ((uint32_t)0x34000008)
 
#define CAN_FLAG_FOV1   ((uint32_t)0x34000010)
 
#define CAN_FLAG_WKU   ((uint32_t)0x31000008)
 
#define CAN_FLAG_SLAK   ((uint32_t)0x31000012)
 
#define CAN_FLAG_EWG   ((uint32_t)0x10F00001)
 
#define CAN_FLAG_EPV   ((uint32_t)0x10F00002)
 
#define CAN_FLAG_BOF   ((uint32_t)0x10F00004)
 
#define CAN_FLAG_LEC   ((uint32_t)0x30F00070)
 
#define IS_CAN_GET_FLAG(FLAG)
 
#define IS_CAN_CLEAR_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_FLAG_BOF   ((uint32_t)0x10F00004)
+
+

Bus-Off Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_EPV   ((uint32_t)0x10F00002)
+
+

Error Passive Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_EWG   ((uint32_t)0x10F00001)
+
+

Error Warning Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FF0   ((uint32_t)0x32000008)
+
+

FIFO 0 Full Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FF1   ((uint32_t)0x34000008)
+
+

FIFO 1 Full Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FMP0   ((uint32_t)0x12000003)
+
+

FIFO 0 Message Pending Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FMP1   ((uint32_t)0x14000003)
+
+

FIFO 1 Message Pending Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FOV0   ((uint32_t)0x32000010)
+
+

FIFO 0 Overrun Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_FOV1   ((uint32_t)0x34000010)
+
+

FIFO 1 Overrun Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_LEC   ((uint32_t)0x30F00070)
+
+

Last error code Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_RQCP0   ((uint32_t)0x38000001)
+
+

Request MailBox0 Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_RQCP1   ((uint32_t)0x38000100)
+
+

Request MailBox1 Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_RQCP2   ((uint32_t)0x38010000)
+
+

Request MailBox2 Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_SLAK   ((uint32_t)0x31000012)
+
+

Sleep acknowledge Flag

+ +
+
+ +
+
+ + + + +
#define CAN_FLAG_WKU   ((uint32_t)0x31000008)
+
+

Wake up Flag

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_CLEAR_FLAG( FLAG)
+
+Value:
(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+
CAN_FLAG_WKU
#define CAN_FLAG_WKU
Definition: stm32f4xx_can.h:508
+
CAN_FLAG_FOV0
#define CAN_FLAG_FOV0
Definition: stm32f4xx_can.h:502
+
CAN_FLAG_LEC
#define CAN_FLAG_LEC
Definition: stm32f4xx_can.h:517
+
CAN_FLAG_SLAK
#define CAN_FLAG_SLAK
Definition: stm32f4xx_can.h:509
+
CAN_FLAG_FF0
#define CAN_FLAG_FF0
Definition: stm32f4xx_can.h:501
+
CAN_FLAG_FOV1
#define CAN_FLAG_FOV1
Definition: stm32f4xx_can.h:505
+
CAN_FLAG_FF1
#define CAN_FLAG_FF1
Definition: stm32f4xx_can.h:504
+
CAN_FLAG_RQCP2
#define CAN_FLAG_RQCP2
Definition: stm32f4xx_can.h:497
+
CAN_FLAG_RQCP1
#define CAN_FLAG_RQCP1
Definition: stm32f4xx_can.h:496
+
CAN_FLAG_RQCP0
#define CAN_FLAG_RQCP0
Definition: stm32f4xx_can.h:495
+
+
+
+ +
+
+ + + + + + + + +
#define IS_CAN_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+
((FLAG) == CAN_FLAG_SLAK ))
+
CAN_FLAG_FMP0
#define CAN_FLAG_FMP0
Definition: stm32f4xx_can.h:500
+
CAN_FLAG_WKU
#define CAN_FLAG_WKU
Definition: stm32f4xx_can.h:508
+
CAN_FLAG_FOV0
#define CAN_FLAG_FOV0
Definition: stm32f4xx_can.h:502
+
CAN_FLAG_FMP1
#define CAN_FLAG_FMP1
Definition: stm32f4xx_can.h:503
+
CAN_FLAG_EWG
#define CAN_FLAG_EWG
Definition: stm32f4xx_can.h:514
+
CAN_FLAG_EPV
#define CAN_FLAG_EPV
Definition: stm32f4xx_can.h:515
+
CAN_FLAG_LEC
#define CAN_FLAG_LEC
Definition: stm32f4xx_can.h:517
+
CAN_FLAG_BOF
#define CAN_FLAG_BOF
Definition: stm32f4xx_can.h:516
+
CAN_FLAG_SLAK
#define CAN_FLAG_SLAK
Definition: stm32f4xx_can.h:509
+
CAN_FLAG_FF0
#define CAN_FLAG_FF0
Definition: stm32f4xx_can.h:501
+
CAN_FLAG_FOV1
#define CAN_FLAG_FOV1
Definition: stm32f4xx_can.h:505
+
CAN_FLAG_FF1
#define CAN_FLAG_FF1
Definition: stm32f4xx_can.h:504
+
CAN_FLAG_RQCP2
#define CAN_FLAG_RQCP2
Definition: stm32f4xx_can.h:497
+
CAN_FLAG_RQCP1
#define CAN_FLAG_RQCP1
Definition: stm32f4xx_can.h:496
+
CAN_FLAG_RQCP0
#define CAN_FLAG_RQCP0
Definition: stm32f4xx_can.h:495
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__flags.map b/group___c_a_n__flags.map new file mode 100644 index 0000000..2439311 --- /dev/null +++ b/group___c_a_n__flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__flags.md5 b/group___c_a_n__flags.md5 new file mode 100644 index 0000000..747ff19 --- /dev/null +++ b/group___c_a_n__flags.md5 @@ -0,0 +1 @@ +2eec674830b03205a6b2d058d58ed095 \ No newline at end of file diff --git a/group___c_a_n__flags.png b/group___c_a_n__flags.png new file mode 100644 index 0000000..8c90e0e Binary files /dev/null and b/group___c_a_n__flags.png differ diff --git a/group___c_a_n__identifier__type.html b/group___c_a_n__identifier__type.html new file mode 100644 index 0000000..5e86091 --- /dev/null +++ b/group___c_a_n__identifier__type.html @@ -0,0 +1,165 @@ + + + + + + +discoverpixy: CAN_identifier_type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_identifier_type
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_identifier_type:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define CAN_Id_Standard   ((uint32_t)0x00000000)
 
#define CAN_Id_Extended   ((uint32_t)0x00000004)
 
#define IS_CAN_IDTYPE(IDTYPE)
 
+#define CAN_ID_STD   CAN_Id_Standard
 
+#define CAN_ID_EXT   CAN_Id_Extended
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_Id_Extended   ((uint32_t)0x00000004)
+
+

Extended Id

+ +
+
+ +
+
+ + + + +
#define CAN_Id_Standard   ((uint32_t)0x00000000)
+
+

Standard Id

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_IDTYPE( IDTYPE)
+
+Value:
(((IDTYPE) == CAN_Id_Standard) || \
+
((IDTYPE) == CAN_Id_Extended))
+
CAN_Id_Standard
#define CAN_Id_Standard
Definition: stm32f4xx_can.h:389
+
CAN_Id_Extended
#define CAN_Id_Extended
Definition: stm32f4xx_can.h:390
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__identifier__type.map b/group___c_a_n__identifier__type.map new file mode 100644 index 0000000..5891e72 --- /dev/null +++ b/group___c_a_n__identifier__type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__identifier__type.md5 b/group___c_a_n__identifier__type.md5 new file mode 100644 index 0000000..02e8a8a --- /dev/null +++ b/group___c_a_n__identifier__type.md5 @@ -0,0 +1 @@ +e0cb64fb4fa04b2cc3748d762e86f280 \ No newline at end of file diff --git a/group___c_a_n__identifier__type.png b/group___c_a_n__identifier__type.png new file mode 100644 index 0000000..9dedc28 Binary files /dev/null and b/group___c_a_n__identifier__type.png differ diff --git a/group___c_a_n__interrupts.html b/group___c_a_n__interrupts.html new file mode 100644 index 0000000..bc39ca2 --- /dev/null +++ b/group___c_a_n__interrupts.html @@ -0,0 +1,401 @@ + + + + + + +discoverpixy: CAN_interrupts + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_interrupts
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_interrupts:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_IT_TME   ((uint32_t)0x00000001)
 
#define CAN_IT_FMP0   ((uint32_t)0x00000002)
 
#define CAN_IT_FF0   ((uint32_t)0x00000004)
 
#define CAN_IT_FOV0   ((uint32_t)0x00000008)
 
#define CAN_IT_FMP1   ((uint32_t)0x00000010)
 
#define CAN_IT_FF1   ((uint32_t)0x00000020)
 
#define CAN_IT_FOV1   ((uint32_t)0x00000040)
 
#define CAN_IT_WKU   ((uint32_t)0x00010000)
 
#define CAN_IT_SLK   ((uint32_t)0x00020000)
 
#define CAN_IT_EWG   ((uint32_t)0x00000100)
 
#define CAN_IT_EPV   ((uint32_t)0x00000200)
 
#define CAN_IT_BOF   ((uint32_t)0x00000400)
 
#define CAN_IT_LEC   ((uint32_t)0x00000800)
 
#define CAN_IT_ERR   ((uint32_t)0x00008000)
 
+#define CAN_IT_RQCP0   CAN_IT_TME
 
+#define CAN_IT_RQCP1   CAN_IT_TME
 
+#define CAN_IT_RQCP2   CAN_IT_TME
 
#define IS_CAN_IT(IT)
 
#define IS_CAN_CLEAR_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_IT_BOF   ((uint32_t)0x00000400)
+
+

Bus-off Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_EPV   ((uint32_t)0x00000200)
+
+

Error passive Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_ERR   ((uint32_t)0x00008000)
+
+

Error Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_EWG   ((uint32_t)0x00000100)
+
+

Error warning Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FF0   ((uint32_t)0x00000004)
+
+

FIFO 0 full Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FF1   ((uint32_t)0x00000020)
+
+

FIFO 1 full Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FMP0   ((uint32_t)0x00000002)
+
+

FIFO 0 message pending Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FMP1   ((uint32_t)0x00000010)
+
+

FIFO 1 message pending Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FOV0   ((uint32_t)0x00000008)
+
+

FIFO 0 overrun Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_FOV1   ((uint32_t)0x00000040)
+
+

FIFO 1 overrun Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_LEC   ((uint32_t)0x00000800)
+
+

Last error code Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_SLK   ((uint32_t)0x00020000)
+
+

Sleep acknowledge Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_TME   ((uint32_t)0x00000001)
+
+

Transmit mailbox empty Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_IT_WKU   ((uint32_t)0x00010000)
+
+

Wake-up Interrupt

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_CLEAR_IT( IT)
+
+Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
CAN_IT_EWG
#define CAN_IT_EWG
Definition: stm32f4xx_can.h:556
+
CAN_IT_ERR
#define CAN_IT_ERR
Definition: stm32f4xx_can.h:560
+
CAN_IT_FOV0
#define CAN_IT_FOV0
Definition: stm32f4xx_can.h:546
+
CAN_IT_SLK
#define CAN_IT_SLK
Definition: stm32f4xx_can.h:553
+
CAN_IT_TME
#define CAN_IT_TME
Definition: stm32f4xx_can.h:541
+
CAN_IT_BOF
#define CAN_IT_BOF
Definition: stm32f4xx_can.h:558
+
CAN_IT_WKU
#define CAN_IT_WKU
Definition: stm32f4xx_can.h:552
+
CAN_IT_LEC
#define CAN_IT_LEC
Definition: stm32f4xx_can.h:559
+
CAN_IT_FF1
#define CAN_IT_FF1
Definition: stm32f4xx_can.h:548
+
CAN_IT_EPV
#define CAN_IT_EPV
Definition: stm32f4xx_can.h:557
+
CAN_IT_FF0
#define CAN_IT_FF0
Definition: stm32f4xx_can.h:545
+
CAN_IT_FOV1
#define CAN_IT_FOV1
Definition: stm32f4xx_can.h:549
+
+
+
+ +
+
+ + + + + + + + +
#define IS_CAN_IT( IT)
+
+Value:
(((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
CAN_IT_EWG
#define CAN_IT_EWG
Definition: stm32f4xx_can.h:556
+
CAN_IT_ERR
#define CAN_IT_ERR
Definition: stm32f4xx_can.h:560
+
CAN_IT_FOV0
#define CAN_IT_FOV0
Definition: stm32f4xx_can.h:546
+
CAN_IT_SLK
#define CAN_IT_SLK
Definition: stm32f4xx_can.h:553
+
CAN_IT_TME
#define CAN_IT_TME
Definition: stm32f4xx_can.h:541
+
CAN_IT_BOF
#define CAN_IT_BOF
Definition: stm32f4xx_can.h:558
+
CAN_IT_WKU
#define CAN_IT_WKU
Definition: stm32f4xx_can.h:552
+
CAN_IT_LEC
#define CAN_IT_LEC
Definition: stm32f4xx_can.h:559
+
CAN_IT_FF1
#define CAN_IT_FF1
Definition: stm32f4xx_can.h:548
+
CAN_IT_EPV
#define CAN_IT_EPV
Definition: stm32f4xx_can.h:557
+
CAN_IT_FF0
#define CAN_IT_FF0
Definition: stm32f4xx_can.h:545
+
CAN_IT_FMP0
#define CAN_IT_FMP0
Definition: stm32f4xx_can.h:544
+
CAN_IT_FMP1
#define CAN_IT_FMP1
Definition: stm32f4xx_can.h:547
+
CAN_IT_FOV1
#define CAN_IT_FOV1
Definition: stm32f4xx_can.h:549
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__interrupts.map b/group___c_a_n__interrupts.map new file mode 100644 index 0000000..ab899b6 --- /dev/null +++ b/group___c_a_n__interrupts.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__interrupts.md5 b/group___c_a_n__interrupts.md5 new file mode 100644 index 0000000..445d5c8 --- /dev/null +++ b/group___c_a_n__interrupts.md5 @@ -0,0 +1 @@ +4dbe2afac5474d2dcb8666a523579d66 \ No newline at end of file diff --git a/group___c_a_n__interrupts.png b/group___c_a_n__interrupts.png new file mode 100644 index 0000000..851c52e Binary files /dev/null and b/group___c_a_n__interrupts.png differ diff --git a/group___c_a_n__operating__mode.html b/group___c_a_n__operating__mode.html new file mode 100644 index 0000000..8892e5f --- /dev/null +++ b/group___c_a_n__operating__mode.html @@ -0,0 +1,262 @@ + + + + + + +discoverpixy: CAN_operating_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_operating_mode
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_operating_mode:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_Mode_Normal   ((uint8_t)0x00)
 
#define CAN_Mode_LoopBack   ((uint8_t)0x01)
 
#define CAN_Mode_Silent   ((uint8_t)0x02)
 
#define CAN_Mode_Silent_LoopBack   ((uint8_t)0x03)
 
#define IS_CAN_MODE(MODE)
 
#define CAN_OperatingMode_Initialization   ((uint8_t)0x00)
 
#define CAN_OperatingMode_Normal   ((uint8_t)0x01)
 
#define CAN_OperatingMode_Sleep   ((uint8_t)0x02)
 
#define IS_CAN_OPERATING_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_Mode_LoopBack   ((uint8_t)0x01)
+
+

loopback mode

+ +
+
+ +
+
+ + + + +
#define CAN_Mode_Normal   ((uint8_t)0x00)
+
+

normal mode

+ +
+
+ +
+
+ + + + +
#define CAN_Mode_Silent   ((uint8_t)0x02)
+
+

silent mode

+ +
+
+ +
+
+ + + + +
#define CAN_Mode_Silent_LoopBack   ((uint8_t)0x03)
+
+

loopback combined with silent mode

+ +
+
+ +
+
+ + + + +
#define CAN_OperatingMode_Initialization   ((uint8_t)0x00)
+
+

Initialization mode

+ +
+
+ +
+
+ + + + +
#define CAN_OperatingMode_Normal   ((uint8_t)0x01)
+
+

Normal mode

+ +
+
+ +
+
+ + + + +
#define CAN_OperatingMode_Sleep   ((uint8_t)0x02)
+
+

sleep mode

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_MODE( MODE)
+
+Value:
(((MODE) == CAN_Mode_Normal) || \
+
((MODE) == CAN_Mode_LoopBack)|| \
+
((MODE) == CAN_Mode_Silent) || \
+
((MODE) == CAN_Mode_Silent_LoopBack))
+
CAN_Mode_Silent
#define CAN_Mode_Silent
Definition: stm32f4xx_can.h:217
+
CAN_Mode_Silent_LoopBack
#define CAN_Mode_Silent_LoopBack
Definition: stm32f4xx_can.h:218
+
CAN_Mode_Normal
#define CAN_Mode_Normal
Definition: stm32f4xx_can.h:215
+
CAN_Mode_LoopBack
#define CAN_Mode_LoopBack
Definition: stm32f4xx_can.h:216
+
+
+
+ +
+
+ + + + + + + + +
#define IS_CAN_OPERATING_MODE( MODE)
+
+Value:
(((MODE) == CAN_OperatingMode_Initialization) ||\
+
((MODE) == CAN_OperatingMode_Normal)|| \
+
((MODE) == CAN_OperatingMode_Sleep))
+
CAN_OperatingMode_Initialization
#define CAN_OperatingMode_Initialization
Definition: stm32f4xx_can.h:233
+
CAN_OperatingMode_Normal
#define CAN_OperatingMode_Normal
Definition: stm32f4xx_can.h:234
+
CAN_OperatingMode_Sleep
#define CAN_OperatingMode_Sleep
Definition: stm32f4xx_can.h:235
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__operating__mode.map b/group___c_a_n__operating__mode.map new file mode 100644 index 0000000..90eb452 --- /dev/null +++ b/group___c_a_n__operating__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__operating__mode.md5 b/group___c_a_n__operating__mode.md5 new file mode 100644 index 0000000..f88a719 --- /dev/null +++ b/group___c_a_n__operating__mode.md5 @@ -0,0 +1 @@ +9b3725947e7a82207dc9ddc9051102b2 \ No newline at end of file diff --git a/group___c_a_n__operating__mode.png b/group___c_a_n__operating__mode.png new file mode 100644 index 0000000..6f97c89 Binary files /dev/null and b/group___c_a_n__operating__mode.png differ diff --git a/group___c_a_n__operating__mode__status.html b/group___c_a_n__operating__mode__status.html new file mode 100644 index 0000000..85a420a --- /dev/null +++ b/group___c_a_n__operating__mode__status.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: CAN_operating_mode_status + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_operating_mode_status
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_operating_mode_status:
+
+
+ + +
+
+ + + + + + +

+Macros

#define CAN_ModeStatus_Failed   ((uint8_t)0x00)
 
#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_ModeStatus_Failed   ((uint8_t)0x00)
+
+

CAN entering the specific mode failed

+ +
+
+ +
+
+ + + + +
#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)
+
+

CAN entering the specific mode Succeed

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__operating__mode__status.map b/group___c_a_n__operating__mode__status.map new file mode 100644 index 0000000..8dab7eb --- /dev/null +++ b/group___c_a_n__operating__mode__status.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__operating__mode__status.md5 b/group___c_a_n__operating__mode__status.md5 new file mode 100644 index 0000000..5ca9b91 --- /dev/null +++ b/group___c_a_n__operating__mode__status.md5 @@ -0,0 +1 @@ +59a8f20c004759ea7da2fe7e5aae039c \ No newline at end of file diff --git a/group___c_a_n__operating__mode__status.png b/group___c_a_n__operating__mode__status.png new file mode 100644 index 0000000..f65237b Binary files /dev/null and b/group___c_a_n__operating__mode__status.png differ diff --git a/group___c_a_n__receive___f_i_f_o__number__constants.html b/group___c_a_n__receive___f_i_f_o__number__constants.html new file mode 100644 index 0000000..c8f78f1 --- /dev/null +++ b/group___c_a_n__receive___f_i_f_o__number__constants.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: CAN_receive_FIFO_number_constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_receive_FIFO_number_constants
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_receive_FIFO_number_constants:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define CAN_FIFO0   ((uint8_t)0x00)
 
#define CAN_FIFO1   ((uint8_t)0x01)
 
+#define IS_CAN_FIFO(FIFO)   (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_FIFO0   ((uint8_t)0x00)
+
+

CAN FIFO 0 used to receive

+ +
+
+ +
+
+ + + + +
#define CAN_FIFO1   ((uint8_t)0x01)
+
+

CAN FIFO 1 used to receive

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__receive___f_i_f_o__number__constants.map b/group___c_a_n__receive___f_i_f_o__number__constants.map new file mode 100644 index 0000000..a146c98 --- /dev/null +++ b/group___c_a_n__receive___f_i_f_o__number__constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__receive___f_i_f_o__number__constants.md5 b/group___c_a_n__receive___f_i_f_o__number__constants.md5 new file mode 100644 index 0000000..6680a58 --- /dev/null +++ b/group___c_a_n__receive___f_i_f_o__number__constants.md5 @@ -0,0 +1 @@ +2578e2e2a70b008c549f7b2088fef4c1 \ No newline at end of file diff --git a/group___c_a_n__receive___f_i_f_o__number__constants.png b/group___c_a_n__receive___f_i_f_o__number__constants.png new file mode 100644 index 0000000..609a138 Binary files /dev/null and b/group___c_a_n__receive___f_i_f_o__number__constants.png differ diff --git a/group___c_a_n__remote__transmission__request.html b/group___c_a_n__remote__transmission__request.html new file mode 100644 index 0000000..1ca995d --- /dev/null +++ b/group___c_a_n__remote__transmission__request.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: CAN_remote_transmission_request + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_remote_transmission_request
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_remote_transmission_request:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define CAN_RTR_Data   ((uint32_t)0x00000000)
 
#define CAN_RTR_Remote   ((uint32_t)0x00000002)
 
+#define IS_CAN_RTR(RTR)   (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
 
+#define CAN_RTR_DATA   CAN_RTR_Data
 
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_RTR_Data   ((uint32_t)0x00000000)
+
+

Data frame

+ +
+
+ +
+
+ + + + +
#define CAN_RTR_Remote   ((uint32_t)0x00000002)
+
+

Remote frame

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__remote__transmission__request.map b/group___c_a_n__remote__transmission__request.map new file mode 100644 index 0000000..0d86e4d --- /dev/null +++ b/group___c_a_n__remote__transmission__request.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__remote__transmission__request.md5 b/group___c_a_n__remote__transmission__request.md5 new file mode 100644 index 0000000..8ccd4a6 --- /dev/null +++ b/group___c_a_n__remote__transmission__request.md5 @@ -0,0 +1 @@ +e2004a396f1e78d902e6b6fb90ee7bd1 \ No newline at end of file diff --git a/group___c_a_n__remote__transmission__request.png b/group___c_a_n__remote__transmission__request.png new file mode 100644 index 0000000..c57a910 Binary files /dev/null and b/group___c_a_n__remote__transmission__request.png differ diff --git a/group___c_a_n__sleep__constants.html b/group___c_a_n__sleep__constants.html new file mode 100644 index 0000000..fb06724 --- /dev/null +++ b/group___c_a_n__sleep__constants.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: CAN_sleep_constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_sleep_constants
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_sleep_constants:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define CAN_Sleep_Failed   ((uint8_t)0x00)
 
#define CAN_Sleep_Ok   ((uint8_t)0x01)
 
+#define CANSLEEPFAILED   CAN_Sleep_Failed
 
+#define CANSLEEPOK   CAN_Sleep_Ok
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_Sleep_Failed   ((uint8_t)0x00)
+
+

CAN did not enter the sleep mode

+ +
+
+ +
+
+ + + + +
#define CAN_Sleep_Ok   ((uint8_t)0x01)
+
+

CAN entered the sleep mode

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__sleep__constants.map b/group___c_a_n__sleep__constants.map new file mode 100644 index 0000000..9d4b62b --- /dev/null +++ b/group___c_a_n__sleep__constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__sleep__constants.md5 b/group___c_a_n__sleep__constants.md5 new file mode 100644 index 0000000..8192887 --- /dev/null +++ b/group___c_a_n__sleep__constants.md5 @@ -0,0 +1 @@ +36d0503173ae0ad86a908ef8c6899a4d \ No newline at end of file diff --git a/group___c_a_n__sleep__constants.png b/group___c_a_n__sleep__constants.png new file mode 100644 index 0000000..85fac70 Binary files /dev/null and b/group___c_a_n__sleep__constants.png differ diff --git a/group___c_a_n__synchronisation__jump__width.html b/group___c_a_n__synchronisation__jump__width.html new file mode 100644 index 0000000..9bee74d --- /dev/null +++ b/group___c_a_n__synchronisation__jump__width.html @@ -0,0 +1,191 @@ + + + + + + +discoverpixy: CAN_synchronisation_jump_width + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_synchronisation_jump_width
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_synchronisation_jump_width:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define CAN_SJW_1tq   ((uint8_t)0x00)
 
#define CAN_SJW_2tq   ((uint8_t)0x01)
 
#define CAN_SJW_3tq   ((uint8_t)0x02)
 
#define CAN_SJW_4tq   ((uint8_t)0x03)
 
#define IS_CAN_SJW(SJW)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_SJW_1tq   ((uint8_t)0x00)
+
+

1 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_SJW_2tq   ((uint8_t)0x01)
+
+

2 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_SJW_3tq   ((uint8_t)0x02)
+
+

3 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_SJW_4tq   ((uint8_t)0x03)
+
+

4 time quantum

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CAN_SJW( SJW)
+
+Value:
(((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+
CAN_SJW_4tq
#define CAN_SJW_4tq
Definition: stm32f4xx_can.h:262
+
CAN_SJW_1tq
#define CAN_SJW_1tq
Definition: stm32f4xx_can.h:259
+
CAN_SJW_2tq
#define CAN_SJW_2tq
Definition: stm32f4xx_can.h:260
+
CAN_SJW_3tq
#define CAN_SJW_3tq
Definition: stm32f4xx_can.h:261
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__synchronisation__jump__width.map b/group___c_a_n__synchronisation__jump__width.map new file mode 100644 index 0000000..581560d --- /dev/null +++ b/group___c_a_n__synchronisation__jump__width.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__synchronisation__jump__width.md5 b/group___c_a_n__synchronisation__jump__width.md5 new file mode 100644 index 0000000..12f9458 --- /dev/null +++ b/group___c_a_n__synchronisation__jump__width.md5 @@ -0,0 +1 @@ +fb58d30bfc3353d011dda27d40cd40ef \ No newline at end of file diff --git a/group___c_a_n__synchronisation__jump__width.png b/group___c_a_n__synchronisation__jump__width.png new file mode 100644 index 0000000..b44d866 Binary files /dev/null and b/group___c_a_n__synchronisation__jump__width.png differ diff --git a/group___c_a_n__time__quantum__in__bit__segment__1.html b/group___c_a_n__time__quantum__in__bit__segment__1.html new file mode 100644 index 0000000..1547303 --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__1.html @@ -0,0 +1,350 @@ + + + + + + +discoverpixy: CAN_time_quantum_in_bit_segment_1 + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CAN_time_quantum_in_bit_segment_1
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_time_quantum_in_bit_segment_1:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_BS1_1tq   ((uint8_t)0x00)
 
#define CAN_BS1_2tq   ((uint8_t)0x01)
 
#define CAN_BS1_3tq   ((uint8_t)0x02)
 
#define CAN_BS1_4tq   ((uint8_t)0x03)
 
#define CAN_BS1_5tq   ((uint8_t)0x04)
 
#define CAN_BS1_6tq   ((uint8_t)0x05)
 
#define CAN_BS1_7tq   ((uint8_t)0x06)
 
#define CAN_BS1_8tq   ((uint8_t)0x07)
 
#define CAN_BS1_9tq   ((uint8_t)0x08)
 
#define CAN_BS1_10tq   ((uint8_t)0x09)
 
#define CAN_BS1_11tq   ((uint8_t)0x0A)
 
#define CAN_BS1_12tq   ((uint8_t)0x0B)
 
#define CAN_BS1_13tq   ((uint8_t)0x0C)
 
#define CAN_BS1_14tq   ((uint8_t)0x0D)
 
#define CAN_BS1_15tq   ((uint8_t)0x0E)
 
#define CAN_BS1_16tq   ((uint8_t)0x0F)
 
+#define IS_CAN_BS1(BS1)   ((BS1) <= CAN_BS1_16tq)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_BS1_10tq   ((uint8_t)0x09)
+
+

10 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_11tq   ((uint8_t)0x0A)
+
+

11 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_12tq   ((uint8_t)0x0B)
+
+

12 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_13tq   ((uint8_t)0x0C)
+
+

13 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_14tq   ((uint8_t)0x0D)
+
+

14 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_15tq   ((uint8_t)0x0E)
+
+

15 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_16tq   ((uint8_t)0x0F)
+
+

16 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_1tq   ((uint8_t)0x00)
+
+

1 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_2tq   ((uint8_t)0x01)
+
+

2 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_3tq   ((uint8_t)0x02)
+
+

3 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_4tq   ((uint8_t)0x03)
+
+

4 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_5tq   ((uint8_t)0x04)
+
+

5 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_6tq   ((uint8_t)0x05)
+
+

6 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_7tq   ((uint8_t)0x06)
+
+

7 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_8tq   ((uint8_t)0x07)
+
+

8 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS1_9tq   ((uint8_t)0x08)
+
+

9 time quantum

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__time__quantum__in__bit__segment__1.map b/group___c_a_n__time__quantum__in__bit__segment__1.map new file mode 100644 index 0000000..0a83c22 --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__time__quantum__in__bit__segment__1.md5 b/group___c_a_n__time__quantum__in__bit__segment__1.md5 new file mode 100644 index 0000000..45d624d --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__1.md5 @@ -0,0 +1 @@ +a03952826a43212488bd4ef72e79e09b \ No newline at end of file diff --git a/group___c_a_n__time__quantum__in__bit__segment__1.png b/group___c_a_n__time__quantum__in__bit__segment__1.png new file mode 100644 index 0000000..be6e7cb Binary files /dev/null and b/group___c_a_n__time__quantum__in__bit__segment__1.png differ diff --git a/group___c_a_n__time__quantum__in__bit__segment__2.html b/group___c_a_n__time__quantum__in__bit__segment__2.html new file mode 100644 index 0000000..3eb2169 --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__2.html @@ -0,0 +1,230 @@ + + + + + + +discoverpixy: CAN_time_quantum_in_bit_segment_2 + + + + + + + + + + +
+
+ + + + + + +
+
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+
+
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+Macros
+
+
CAN_time_quantum_in_bit_segment_2
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_time_quantum_in_bit_segment_2:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_BS2_1tq   ((uint8_t)0x00)
 
#define CAN_BS2_2tq   ((uint8_t)0x01)
 
#define CAN_BS2_3tq   ((uint8_t)0x02)
 
#define CAN_BS2_4tq   ((uint8_t)0x03)
 
#define CAN_BS2_5tq   ((uint8_t)0x04)
 
#define CAN_BS2_6tq   ((uint8_t)0x05)
 
#define CAN_BS2_7tq   ((uint8_t)0x06)
 
#define CAN_BS2_8tq   ((uint8_t)0x07)
 
+#define IS_CAN_BS2(BS2)   ((BS2) <= CAN_BS2_8tq)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_BS2_1tq   ((uint8_t)0x00)
+
+

1 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_2tq   ((uint8_t)0x01)
+
+

2 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_3tq   ((uint8_t)0x02)
+
+

3 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_4tq   ((uint8_t)0x03)
+
+

4 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_5tq   ((uint8_t)0x04)
+
+

5 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_6tq   ((uint8_t)0x05)
+
+

6 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_7tq   ((uint8_t)0x06)
+
+

7 time quantum

+ +
+
+ +
+
+ + + + +
#define CAN_BS2_8tq   ((uint8_t)0x07)
+
+

8 time quantum

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__time__quantum__in__bit__segment__2.map b/group___c_a_n__time__quantum__in__bit__segment__2.map new file mode 100644 index 0000000..9274c4b --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__time__quantum__in__bit__segment__2.md5 b/group___c_a_n__time__quantum__in__bit__segment__2.md5 new file mode 100644 index 0000000..0eea292 --- /dev/null +++ b/group___c_a_n__time__quantum__in__bit__segment__2.md5 @@ -0,0 +1 @@ +fbb38cb0d34379f752731a218c532d44 \ No newline at end of file diff --git a/group___c_a_n__time__quantum__in__bit__segment__2.png b/group___c_a_n__time__quantum__in__bit__segment__2.png new file mode 100644 index 0000000..bcb683a Binary files /dev/null and b/group___c_a_n__time__quantum__in__bit__segment__2.png differ diff --git a/group___c_a_n__transmit__constants.html b/group___c_a_n__transmit__constants.html new file mode 100644 index 0000000..6b9e93a --- /dev/null +++ b/group___c_a_n__transmit__constants.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: CAN_transmit_constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
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+Macros
+
+
CAN_transmit_constants
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_transmit_constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

#define CAN_TxStatus_Failed   ((uint8_t)0x00)
 
#define CAN_TxStatus_Ok   ((uint8_t)0x01)
 
#define CAN_TxStatus_Pending   ((uint8_t)0x02)
 
#define CAN_TxStatus_NoMailBox   ((uint8_t)0x04)
 
+#define CANTXFAILED   CAN_TxStatus_Failed
 
+#define CANTXOK   CAN_TxStatus_Ok
 
+#define CANTXPENDING   CAN_TxStatus_Pending
 
+#define CAN_NO_MB   CAN_TxStatus_NoMailBox
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_TxStatus_Failed   ((uint8_t)0x00)
+
+

CAN transmission failed

+ +
+
+ +
+
+ + + + +
#define CAN_TxStatus_NoMailBox   ((uint8_t)0x04)
+
+

CAN cell did not provide an empty mailbox

+ +
+
+ +
+
+ + + + +
#define CAN_TxStatus_Ok   ((uint8_t)0x01)
+
+

CAN transmission succeeded

+ +
+
+ +
+
+ + + + +
#define CAN_TxStatus_Pending   ((uint8_t)0x02)
+
+

CAN transmission pending

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__transmit__constants.map b/group___c_a_n__transmit__constants.map new file mode 100644 index 0000000..230120e --- /dev/null +++ b/group___c_a_n__transmit__constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__transmit__constants.md5 b/group___c_a_n__transmit__constants.md5 new file mode 100644 index 0000000..08fd48f --- /dev/null +++ b/group___c_a_n__transmit__constants.md5 @@ -0,0 +1 @@ +0b44033b30dfcebe1d1d51a0f058af44 \ No newline at end of file diff --git a/group___c_a_n__transmit__constants.png b/group___c_a_n__transmit__constants.png new file mode 100644 index 0000000..b19c6bd Binary files /dev/null and b/group___c_a_n__transmit__constants.png differ diff --git a/group___c_a_n__wake__up__constants.html b/group___c_a_n__wake__up__constants.html new file mode 100644 index 0000000..2decdfc --- /dev/null +++ b/group___c_a_n__wake__up__constants.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: CAN_wake_up_constants + + + + + + + + + + +
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CAN_wake_up_constants
STM32F4xx_StdPeriph_Driver » CAN » CAN_Exported_Constants
+
+
+
+Collaboration diagram for CAN_wake_up_constants:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define CAN_WakeUp_Failed   ((uint8_t)0x00)
 
#define CAN_WakeUp_Ok   ((uint8_t)0x01)
 
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed
 
+#define CANWAKEUPOK   CAN_WakeUp_Ok
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CAN_WakeUp_Failed   ((uint8_t)0x00)
+
+

CAN did not leave the sleep mode

+ +
+
+ +
+
+ + + + +
#define CAN_WakeUp_Ok   ((uint8_t)0x01)
+
+

CAN leaved the sleep mode

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_a_n__wake__up__constants.map b/group___c_a_n__wake__up__constants.map new file mode 100644 index 0000000..d14fa3f --- /dev/null +++ b/group___c_a_n__wake__up__constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n__wake__up__constants.md5 b/group___c_a_n__wake__up__constants.md5 new file mode 100644 index 0000000..7a7a8c6 --- /dev/null +++ b/group___c_a_n__wake__up__constants.md5 @@ -0,0 +1 @@ +40f64af35bc499ed4dcc42515cda277d \ No newline at end of file diff --git a/group___c_a_n__wake__up__constants.png b/group___c_a_n__wake__up__constants.png new file mode 100644 index 0000000..52eb00d Binary files /dev/null and b/group___c_a_n__wake__up__constants.png differ diff --git a/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.map b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.map new file mode 100644 index 0000000..48a5b18 --- /dev/null +++ b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 new file mode 100644 index 0000000..c070298 --- /dev/null +++ b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.md5 @@ -0,0 +1 @@ +158f2dd1050c18711f6807efb25f733f \ No newline at end of file diff --git a/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.png b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.png new file mode 100644 index 0000000..cb4dea8 Binary files /dev/null and b/group___c_a_n_ga002b74cd69574a14b17ad445090245cd_cgraph.png differ diff --git a/group___c_m_s_i_s.html b/group___c_m_s_i_s.html new file mode 100644 index 0000000..9ead540 --- /dev/null +++ b/group___c_m_s_i_s.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: CMSIS + + + + + + + + + + +
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 Stm32f4xx_system
 
+

Detailed Description

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+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s.map b/group___c_m_s_i_s.map new file mode 100644 index 0000000..c510b76 --- /dev/null +++ b/group___c_m_s_i_s.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s.md5 b/group___c_m_s_i_s.md5 new file mode 100644 index 0000000..d9a7812 --- /dev/null +++ b/group___c_m_s_i_s.md5 @@ -0,0 +1 @@ +0a911c9e84f2b02b5ef52130d8a5204c \ No newline at end of file diff --git a/group___c_m_s_i_s.png b/group___c_m_s_i_s.png new file mode 100644 index 0000000..b5f6e3e Binary files /dev/null and b/group___c_m_s_i_s.png differ diff --git a/group___c_m_s_i_s___c_o_r_e.html b/group___c_m_s_i_s___c_o_r_e.html new file mode 100644 index 0000000..606c850 --- /dev/null +++ b/group___c_m_s_i_s___c_o_r_e.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: Status and Control Registers + + + + + + + + + + +
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Status and Control Registers
Defines and Type Definitions
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+ +

Core Register type definitions. +More...

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+Collaboration diagram for Status and Control Registers:
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+Classes

union  APSR_Type
 Union type to access the Application Program Status Register (APSR). More...
 
union  IPSR_Type
 Union type to access the Interrupt Program Status Register (IPSR). More...
 
union  xPSR_Type
 Union type to access the Special-Purpose Program Status Registers (xPSR). More...
 
union  CONTROL_Type
 Union type to access the Control Registers (CONTROL). More...
 
+

Detailed Description

+

Core Register type definitions.

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___c_o_r_e.map b/group___c_m_s_i_s___c_o_r_e.map new file mode 100644 index 0000000..03c97d0 --- /dev/null +++ b/group___c_m_s_i_s___c_o_r_e.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___c_o_r_e.md5 b/group___c_m_s_i_s___c_o_r_e.md5 new file mode 100644 index 0000000..b7144d9 --- /dev/null +++ b/group___c_m_s_i_s___c_o_r_e.md5 @@ -0,0 +1 @@ +cbffcd37b6a97549ccf57a46ea461307 \ No newline at end of file diff --git a/group___c_m_s_i_s___c_o_r_e.png b/group___c_m_s_i_s___c_o_r_e.png new file mode 100644 index 0000000..b0f1727 Binary files /dev/null and b/group___c_m_s_i_s___c_o_r_e.png differ diff --git a/group___c_m_s_i_s___core___function_interface.html b/group___c_m_s_i_s___core___function_interface.html new file mode 100644 index 0000000..1e4e6af --- /dev/null +++ b/group___c_m_s_i_s___core___function_interface.html @@ -0,0 +1,117 @@ + + + + + + +discoverpixy: Functions and Instructions Reference + + + + + + + + + + +
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+
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+Modules

 NVIC Functions
 Functions that manage interrupts and exceptions via the NVIC.
 
 SysTick Functions
 Functions that configure the System.
 
 ITM Functions
 Functions that access the ITM debug interface.
 
 CMSIS Core Register Access Functions
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___core___function_interface.map b/group___c_m_s_i_s___core___function_interface.map new file mode 100644 index 0000000..e5e56e0 --- /dev/null +++ b/group___c_m_s_i_s___core___function_interface.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___c_m_s_i_s___core___function_interface.md5 b/group___c_m_s_i_s___core___function_interface.md5 new file mode 100644 index 0000000..27bf2fc --- /dev/null +++ b/group___c_m_s_i_s___core___function_interface.md5 @@ -0,0 +1 @@ +60bc21d3dad900f10d79abc3e3572984 \ No newline at end of file diff --git a/group___c_m_s_i_s___core___function_interface.png b/group___c_m_s_i_s___core___function_interface.png new file mode 100644 index 0000000..b4c9f7a Binary files /dev/null and b/group___c_m_s_i_s___core___function_interface.png differ diff --git a/group___c_m_s_i_s___core___instruction_interface.html b/group___c_m_s_i_s___core___instruction_interface.html new file mode 100644 index 0000000..b58dde8 --- /dev/null +++ b/group___c_m_s_i_s___core___instruction_interface.html @@ -0,0 +1,92 @@ + + + + + + +discoverpixy: CMSIS Core Instruction Interface + + + + + + + + + + +
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CMSIS Core Instruction Interface
+
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+

Access to dedicated instructions

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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___core___n_v_i_c_functions.html b/group___c_m_s_i_s___core___n_v_i_c_functions.html new file mode 100644 index 0000000..b4ca5e2 --- /dev/null +++ b/group___c_m_s_i_s___core___n_v_i_c_functions.html @@ -0,0 +1,536 @@ + + + + + + +discoverpixy: NVIC Functions + + + + + + + + + + +
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+Functions
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NVIC Functions
Functions and Instructions Reference
+
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+ +

Functions that manage interrupts and exceptions via the NVIC. +More...

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+Collaboration diagram for NVIC Functions:
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+Functions

__STATIC_INLINE void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set Priority Grouping. More...
 
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping (void)
 Get Priority Grouping. More...
 
__STATIC_INLINE void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable External Interrupt. More...
 
__STATIC_INLINE void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable External Interrupt. More...
 
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get Pending Interrupt. More...
 
__STATIC_INLINE void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set Pending Interrupt. More...
 
__STATIC_INLINE void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear Pending Interrupt. More...
 
__STATIC_INLINE uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get Active Interrupt. More...
 
__STATIC_INLINE void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set Interrupt Priority. More...
 
__STATIC_INLINE uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get Interrupt Priority. More...
 
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encode Priority. More...
 
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode Priority. More...
 
__STATIC_INLINE void NVIC_SystemReset (void)
 System Reset. More...
 
+

Detailed Description

+

Functions that manage interrupts and exceptions via the NVIC.

+

Function Documentation

+ +
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__STATIC_INLINE void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+ +

Clear Pending Interrupt.

+

The function clears the pending bit of an external interrupt.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
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__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority,
uint32_t PriorityGroup,
uint32_t * pPreemptPriority,
uint32_t * pSubPriority 
)
+
+ +

Decode Priority.

+

The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.

+
Parameters
+ + + + + +
[in]PriorityPriority value, which can be retrieved with the function NVIC_GetPriority().
[in]PriorityGroupUsed priority group.
[out]pPreemptPriorityPreemptive priority value (starting from 0).
[out]pSubPrioritySubpriority value (starting from 0).
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__STATIC_INLINE void NVIC_DisableIRQ (IRQn_Type IRQn)
+
+ +

Disable External Interrupt.

+

The function disables a device-specific interrupt in the NVIC interrupt controller.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
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__STATIC_INLINE void NVIC_EnableIRQ (IRQn_Type IRQn)
+
+ +

Enable External Interrupt.

+

The function enables a device-specific interrupt in the NVIC interrupt controller.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
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__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
uint32_t PreemptPriority,
uint32_t SubPriority 
)
+
+ +

Encode Priority.

+

The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.

+
Parameters
+ + + + +
[in]PriorityGroupUsed priority group.
[in]PreemptPriorityPreemptive priority value (starting from 0).
[in]SubPrioritySubpriority value (starting from 0).
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Returns
Encoded priority. Value can be used in the function NVIC_SetPriority().
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__STATIC_INLINE uint32_t NVIC_GetActive (IRQn_Type IRQn)
+
+ +

Get Active Interrupt.

+

The function reads the active register in NVIC and returns the active bit.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
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Returns
0 Interrupt status is not active.
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+1 Interrupt status is active.
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__STATIC_INLINE uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
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Get Pending Interrupt.

+

The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt.

+
Parameters
+ + +
[in]IRQnInterrupt number.
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Returns
0 Interrupt status is not pending.
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+1 Interrupt status is pending.
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__STATIC_INLINE uint32_t NVIC_GetPriority (IRQn_Type IRQn)
+
+ +

Get Interrupt Priority.

+

The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
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Returns
Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
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__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping (void )
+
+ +

Get Priority Grouping.

+

The function reads the priority grouping field from the NVIC Interrupt Controller.

+
Returns
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
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__STATIC_INLINE void NVIC_SetPendingIRQ (IRQn_Type IRQn)
+
+ +

Set Pending Interrupt.

+

The function sets the pending bit of an external interrupt.

+
Parameters
+ + +
[in]IRQnInterrupt number. Value cannot be negative.
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__STATIC_INLINE void NVIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
+
+ +

Set Interrupt Priority.

+

The function sets the priority of an interrupt.

+
Note
The priority cannot be set for every core interrupt.
+
Parameters
+ + + +
[in]IRQnInterrupt number.
[in]priorityPriority to set.
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__STATIC_INLINE void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
+
+ +

Set Priority Grouping.

+

The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

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Parameters
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[in]PriorityGroupPriority grouping field.
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__STATIC_INLINE void NVIC_SystemReset (void )
+
+ +

System Reset.

+

The function initiates a system reset request to reset the MCU.

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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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CMSIS Core Register Access Functions
Functions and Instructions Reference
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+Collaboration diagram for CMSIS Core Register Access Functions:
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___core___reg_acc_functions.map b/group___c_m_s_i_s___core___reg_acc_functions.map new file mode 100644 index 0000000..c9ca656 --- /dev/null +++ b/group___c_m_s_i_s___core___reg_acc_functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___core___reg_acc_functions.md5 b/group___c_m_s_i_s___core___reg_acc_functions.md5 new file mode 100644 index 0000000..ca777d9 --- /dev/null +++ b/group___c_m_s_i_s___core___reg_acc_functions.md5 @@ -0,0 +1 @@ +adae4cc23d79c773ec04d1561bb4a3d2 \ No newline at end of file diff --git a/group___c_m_s_i_s___core___reg_acc_functions.png b/group___c_m_s_i_s___core___reg_acc_functions.png new file mode 100644 index 0000000..0c9a921 Binary files /dev/null and b/group___c_m_s_i_s___core___reg_acc_functions.png differ diff --git a/group___c_m_s_i_s___core___sys_tick_functions.html b/group___c_m_s_i_s___core___sys_tick_functions.html new file mode 100644 index 0000000..c893a65 --- /dev/null +++ b/group___c_m_s_i_s___core___sys_tick_functions.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: SysTick Functions + + + + + + + + + + +
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+Functions
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SysTick Functions
Functions and Instructions Reference
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Functions that configure the System. +More...

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+Collaboration diagram for SysTick Functions:
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+Functions

__STATIC_INLINE uint32_t SysTick_Config (uint32_t ticks)
 System Tick Configuration. More...
 
+

Detailed Description

+

Functions that configure the System.

+

Function Documentation

+ +
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+ + + + + + + + +
__STATIC_INLINE uint32_t SysTick_Config (uint32_t ticks)
+
+ +

System Tick Configuration.

+

The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts.

+
Parameters
+ + +
[in]ticksNumber of ticks between two interrupts.
+
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Returns
0 Function succeeded.
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+1 Function failed.
+
Note
When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function.
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Classes | +Macros
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Core Debug Registers (CoreDebug)
Defines and Type Definitions
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Type definitions for the Core Debug Registers. +More...

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struct  CoreDebug_Type
 Structure type to access the Core Debug Register (CoreDebug). More...
 
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+Macros

#define CoreDebug_DHCSR_DBGKEY_Pos   16
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
 
+

Detailed Description

+

Type definitions for the Core Debug Registers.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
+
+

CoreDebug DCRSR: REGSEL Mask

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+ + + + +
#define CoreDebug_DCRSR_REGSEL_Pos   0
+
+

CoreDebug DCRSR: REGSEL Position

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#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
+
+

CoreDebug DCRSR: REGWnR Mask

+ +
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+ +
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+ + + + +
#define CoreDebug_DCRSR_REGWnR_Pos   16
+
+

CoreDebug DCRSR: REGWnR Position

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#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
+
+

CoreDebug DEMCR: MON_EN Mask

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#define CoreDebug_DEMCR_MON_EN_Pos   16
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CoreDebug DEMCR: MON_EN Position

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#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
+
+

CoreDebug DEMCR: MON_PEND Mask

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+ + + + +
#define CoreDebug_DEMCR_MON_PEND_Pos   17
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CoreDebug DEMCR: MON_PEND Position

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#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
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CoreDebug DEMCR: MON_REQ Mask

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#define CoreDebug_DEMCR_MON_REQ_Pos   19
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CoreDebug DEMCR: MON_REQ Position

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#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
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CoreDebug DEMCR: MON_STEP Mask

+ +
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#define CoreDebug_DEMCR_MON_STEP_Pos   18
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CoreDebug DEMCR: MON_STEP Position

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#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
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CoreDebug DEMCR: TRCENA Mask

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#define CoreDebug_DEMCR_TRCENA_Pos   24
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CoreDebug DEMCR: TRCENA Position

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#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
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CoreDebug DEMCR: VC_BUSERR Mask

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#define CoreDebug_DEMCR_VC_BUSERR_Pos   8
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CoreDebug DEMCR: VC_BUSERR Position

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#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
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CoreDebug DEMCR: VC_CHKERR Mask

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#define CoreDebug_DEMCR_VC_CHKERR_Pos   6
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CoreDebug DEMCR: VC_CHKERR Position

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#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
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+

CoreDebug DEMCR: VC_CORERESET Mask

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#define CoreDebug_DEMCR_VC_CORERESET_Pos   0
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CoreDebug DEMCR: VC_CORERESET Position

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#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
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CoreDebug DEMCR: VC_HARDERR Mask

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#define CoreDebug_DEMCR_VC_HARDERR_Pos   10
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CoreDebug DEMCR: VC_HARDERR Position

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#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
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CoreDebug DEMCR: VC_INTERR Mask

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#define CoreDebug_DEMCR_VC_INTERR_Pos   9
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CoreDebug DEMCR: VC_INTERR Position

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#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
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CoreDebug DEMCR: VC_MMERR Mask

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#define CoreDebug_DEMCR_VC_MMERR_Pos   4
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CoreDebug DEMCR: VC_MMERR Position

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#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
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+

CoreDebug DEMCR: VC_NOCPERR Mask

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#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5
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CoreDebug DEMCR: VC_NOCPERR Position

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#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
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CoreDebug DEMCR: VC_STATERR Mask

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#define CoreDebug_DEMCR_VC_STATERR_Pos   7
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CoreDebug DEMCR: VC_STATERR Position

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#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
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CoreDebug DHCSR: C_DEBUGEN Mask

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#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0
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CoreDebug DHCSR: C_DEBUGEN Position

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#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
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CoreDebug DHCSR: C_HALT Mask

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#define CoreDebug_DHCSR_C_HALT_Pos   1
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CoreDebug DHCSR: C_HALT Position

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#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
+
+

CoreDebug DHCSR: C_MASKINTS Mask

+ +
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#define CoreDebug_DHCSR_C_MASKINTS_Pos   3
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CoreDebug DHCSR: C_MASKINTS Position

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#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
+
+

CoreDebug DHCSR: C_SNAPSTALL Mask

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#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5
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+

CoreDebug DHCSR: C_SNAPSTALL Position

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#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
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CoreDebug DHCSR: C_STEP Mask

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#define CoreDebug_DHCSR_C_STEP_Pos   2
+
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CoreDebug DHCSR: C_STEP Position

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#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
+
+

CoreDebug DHCSR: DBGKEY Mask

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#define CoreDebug_DHCSR_DBGKEY_Pos   16
+
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CoreDebug DHCSR: DBGKEY Position

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#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
+
+

CoreDebug DHCSR: S_HALT Mask

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#define CoreDebug_DHCSR_S_HALT_Pos   17
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CoreDebug DHCSR: S_HALT Position

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#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
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CoreDebug DHCSR: S_LOCKUP Mask

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#define CoreDebug_DHCSR_S_LOCKUP_Pos   19
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CoreDebug DHCSR: S_LOCKUP Position

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#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
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CoreDebug DHCSR: S_REGRDY Mask

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#define CoreDebug_DHCSR_S_REGRDY_Pos   16
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CoreDebug DHCSR: S_REGRDY Position

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#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
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CoreDebug DHCSR: S_RESET_ST Mask

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#define CoreDebug_DHCSR_S_RESET_ST_Pos   25
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CoreDebug DHCSR: S_RESET_ST Position

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#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
+
+

CoreDebug DHCSR: S_RETIRE_ST Mask

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+ +
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#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24
+
+

CoreDebug DHCSR: S_RETIRE_ST Position

+ +
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+ +
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#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
+
+

CoreDebug DHCSR: S_SLEEP Mask

+ +
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+ +
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+ + + + +
#define CoreDebug_DHCSR_S_SLEEP_Pos   18
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+

CoreDebug DHCSR: S_SLEEP Position

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+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___core_debug.map b/group___c_m_s_i_s___core_debug.map new file mode 100644 index 0000000..7a377b8 --- /dev/null +++ b/group___c_m_s_i_s___core_debug.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___core_debug.md5 b/group___c_m_s_i_s___core_debug.md5 new file mode 100644 index 0000000..e4ae63e --- /dev/null +++ b/group___c_m_s_i_s___core_debug.md5 @@ -0,0 +1 @@ +ef0130f40178f75dd0a22b9c5458d851 \ No newline at end of file diff --git a/group___c_m_s_i_s___core_debug.png b/group___c_m_s_i_s___core_debug.png new file mode 100644 index 0000000..d6c781c Binary files /dev/null and b/group___c_m_s_i_s___core_debug.png differ diff --git a/group___c_m_s_i_s___d_w_t.html b/group___c_m_s_i_s___d_w_t.html new file mode 100644 index 0000000..58f1e2d --- /dev/null +++ b/group___c_m_s_i_s___d_w_t.html @@ -0,0 +1,1108 @@ + + + + + + +discoverpixy: Data Watchpoint and Trace (DWT) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Classes | +Macros
+
+
Data Watchpoint and Trace (DWT)
Defines and Type Definitions
+
+
+ +

Type definitions for the Data Watchpoint and Trace (DWT) +More...

+
+Collaboration diagram for Data Watchpoint and Trace (DWT):
+
+
+ + +
+
+ + + + + +

+Classes

struct  DWT_Type
 Structure type to access the Data Watchpoint and Trace Register (DWT). More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DWT_CTRL_NUMCOMP_Pos   28
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
 
#define DWT_CPICNT_CPICNT_Pos   0
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL << DWT_CPICNT_CPICNT_Pos)
 
#define DWT_EXCCNT_EXCCNT_Pos   0
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
 
#define DWT_LSUCNT_LSUCNT_Pos   0
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
 
#define DWT_MASK_MASK_Pos   0
 
#define DWT_MASK_MASK_Msk   (0x1FUL << DWT_MASK_MASK_Pos)
 
#define DWT_FUNCTION_MATCHED_Pos   24
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
 
+

Detailed Description

+

Type definitions for the Data Watchpoint and Trace (DWT)

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL << DWT_CPICNT_CPICNT_Pos)
+
+

DWT CPICNT: CPICNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CPICNT_CPICNT_Pos   0
+
+

DWT CPICNT: CPICNT Position

+ +
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+ +
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+ + + + +
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
+
+

DWT CTRL: CPIEVTENA Mask

+ +
+
+ +
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+ + + + +
#define DWT_CTRL_CPIEVTENA_Pos   17
+
+

DWT CTRL: CPIEVTENA Position

+ +
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+ +
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#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
+
+

DWT CTRL: CYCCNTENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_CYCCNTENA_Pos   0
+
+

DWT CTRL: CYCCNTENA Position

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#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
+
+

DWT CTRL: CYCEVTENA Mask

+ +
+
+ +
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+ + + + +
#define DWT_CTRL_CYCEVTENA_Pos   22
+
+

DWT CTRL: CYCEVTENA Position

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#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
+
+

DWT CTRL: CYCTAP Mask

+ +
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+ + + + +
#define DWT_CTRL_CYCTAP_Pos   9
+
+

DWT CTRL: CYCTAP Position

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+ + + + +
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
+
+

DWT CTRL: EXCEVTENA Mask

+ +
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#define DWT_CTRL_EXCEVTENA_Pos   18
+
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DWT CTRL: EXCEVTENA Position

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#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
+
+

DWT CTRL: EXCTRCENA Mask

+ +
+
+ +
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+ + + + +
#define DWT_CTRL_EXCTRCENA_Pos   16
+
+

DWT CTRL: EXCTRCENA Position

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#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
+
+

DWT CTRL: FOLDEVTENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_FOLDEVTENA_Pos   21
+
+

DWT CTRL: FOLDEVTENA Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
+
+

DWT CTRL: LSUEVTENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_LSUEVTENA_Pos   20
+
+

DWT CTRL: LSUEVTENA Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
+
+

DWT CTRL: NOCYCCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOCYCCNT_Pos   25
+
+

DWT CTRL: NOCYCCNT Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
+
+

DWT CTRL: NOEXTTRIG Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOEXTTRIG_Pos   26
+
+

DWT CTRL: NOEXTTRIG Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
+
+

DWT CTRL: NOPRFCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOPRFCNT_Pos   24
+
+

DWT CTRL: NOPRFCNT Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
+
+

DWT CTRL: NOTRCPKT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NOTRCPKT_Pos   27
+
+

DWT CTRL: NOTRCPKT Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
+
+

DWT CTRL: NUMCOMP Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_NUMCOMP_Pos   28
+
+

DWT CTRL: NUMCOMP Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
+
+

DWT CTRL: PCSAMPLENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_PCSAMPLENA_Pos   12
+
+

DWT CTRL: PCSAMPLENA Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
+
+

DWT CTRL: POSTINIT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_POSTINIT_Pos   5
+
+

DWT CTRL: POSTINIT Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
+
+

DWT CTRL: POSTPRESET Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_POSTPRESET_Pos   1
+
+

DWT CTRL: POSTPRESET Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
+
+

DWT CTRL: SLEEPEVTENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_SLEEPEVTENA_Pos   19
+
+

DWT CTRL: SLEEPEVTENA Position

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
+
+

DWT CTRL: SYNCTAP Mask

+ +
+
+ +
+
+ + + + +
#define DWT_CTRL_SYNCTAP_Pos   10
+
+

DWT CTRL: SYNCTAP Position

+ +
+
+ +
+
+ + + + +
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
+
+

DWT EXCCNT: EXCCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_EXCCNT_EXCCNT_Pos   0
+
+

DWT EXCCNT: EXCCNT Position

+ +
+
+ +
+
+ + + + +
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
+
+

DWT FOLDCNT: FOLDCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FOLDCNT_FOLDCNT_Pos   0
+
+

DWT FOLDCNT: FOLDCNT Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
+
+

DWT FUNCTION: CYCMATCH Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_CYCMATCH_Pos   7
+
+

DWT FUNCTION: CYCMATCH Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
+
+

DWT FUNCTION: DATAVADDR0 Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVADDR0_Pos   12
+
+

DWT FUNCTION: DATAVADDR0 Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
+
+

DWT FUNCTION: DATAVADDR1 Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVADDR1_Pos   16
+
+

DWT FUNCTION: DATAVADDR1 Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
+
+

DWT FUNCTION: DATAVMATCH Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVMATCH_Pos   8
+
+

DWT FUNCTION: DATAVMATCH Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
+
+

DWT FUNCTION: DATAVSIZE Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_DATAVSIZE_Pos   10
+
+

DWT FUNCTION: DATAVSIZE Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
+
+

DWT FUNCTION: EMITRANGE Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_EMITRANGE_Pos   5
+
+

DWT FUNCTION: EMITRANGE Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
+
+

DWT FUNCTION: FUNCTION Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_FUNCTION_Pos   0
+
+

DWT FUNCTION: FUNCTION Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
+
+

DWT FUNCTION: LNK1ENA Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_LNK1ENA_Pos   9
+
+

DWT FUNCTION: LNK1ENA Position

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
+
+

DWT FUNCTION: MATCHED Mask

+ +
+
+ +
+
+ + + + +
#define DWT_FUNCTION_MATCHED_Pos   24
+
+

DWT FUNCTION: MATCHED Position

+ +
+
+ +
+
+ + + + +
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
+
+

DWT LSUCNT: LSUCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_LSUCNT_LSUCNT_Pos   0
+
+

DWT LSUCNT: LSUCNT Position

+ +
+
+ +
+
+ + + + +
#define DWT_MASK_MASK_Msk   (0x1FUL << DWT_MASK_MASK_Pos)
+
+

DWT MASK: MASK Mask

+ +
+
+ +
+
+ + + + +
#define DWT_MASK_MASK_Pos   0
+
+

DWT MASK: MASK Position

+ +
+
+ +
+
+ + + + +
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
+
+

DWT SLEEPCNT: SLEEPCNT Mask

+ +
+
+ +
+
+ + + + +
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0
+
+

DWT SLEEPCNT: SLEEPCNT Position

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___d_w_t.map b/group___c_m_s_i_s___d_w_t.map new file mode 100644 index 0000000..1068377 --- /dev/null +++ b/group___c_m_s_i_s___d_w_t.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___d_w_t.md5 b/group___c_m_s_i_s___d_w_t.md5 new file mode 100644 index 0000000..cca0722 --- /dev/null +++ b/group___c_m_s_i_s___d_w_t.md5 @@ -0,0 +1 @@ +9e6f5af32e7f6e814e876890a396265a \ No newline at end of file diff --git a/group___c_m_s_i_s___d_w_t.png b/group___c_m_s_i_s___d_w_t.png new file mode 100644 index 0000000..b64833d Binary files /dev/null and b/group___c_m_s_i_s___d_w_t.png differ diff --git a/group___c_m_s_i_s___i_t_m.html b/group___c_m_s_i_s___i_t_m.html new file mode 100644 index 0000000..9ace03c --- /dev/null +++ b/group___c_m_s_i_s___i_t_m.html @@ -0,0 +1,598 @@ + + + + + + +discoverpixy: Instrumentation Trace Macrocell (ITM) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Classes | +Macros
+
+
Instrumentation Trace Macrocell (ITM)
Defines and Type Definitions
+
+
+ +

Type definitions for the Instrumentation Trace Macrocell (ITM) +More...

+
+Collaboration diagram for Instrumentation Trace Macrocell (ITM):
+
+
+ + +
+
+ + + + + +

+Classes

struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define ITM_TPR_PRIVMASK_Pos   0
 
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
 
#define ITM_TCR_BUSY_Pos   23
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0
 
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
 
#define ITM_IWR_ATVALIDM_Pos   0
 
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
 
#define ITM_IRR_ATREADYM_Pos   0
 
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
 
#define ITM_IMCR_INTEGRATION_Pos   0
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
 
#define ITM_LSR_ByteAcc_Pos   2
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0
 
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
 
+

Detailed Description

+

Type definitions for the Instrumentation Trace Macrocell (ITM)

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ITM_IMCR_INTEGRATION_Msk   (1UL << ITM_IMCR_INTEGRATION_Pos)
+
+

ITM IMCR: INTEGRATION Mask

+ +
+
+ +
+
+ + + + +
#define ITM_IMCR_INTEGRATION_Pos   0
+
+

ITM IMCR: INTEGRATION Position

+ +
+
+ +
+
+ + + + +
#define ITM_IRR_ATREADYM_Msk   (1UL << ITM_IRR_ATREADYM_Pos)
+
+

ITM IRR: ATREADYM Mask

+ +
+
+ +
+
+ + + + +
#define ITM_IRR_ATREADYM_Pos   0
+
+

ITM IRR: ATREADYM Position

+ +
+
+ +
+
+ + + + +
#define ITM_IWR_ATVALIDM_Msk   (1UL << ITM_IWR_ATVALIDM_Pos)
+
+

ITM IWR: ATVALIDM Mask

+ +
+
+ +
+
+ + + + +
#define ITM_IWR_ATVALIDM_Pos   0
+
+

ITM IWR: ATVALIDM Position

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
+
+

ITM LSR: Access Mask

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_Access_Pos   1
+
+

ITM LSR: Access Position

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
+
+

ITM LSR: ByteAcc Mask

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_ByteAcc_Pos   2
+
+

ITM LSR: ByteAcc Position

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_Present_Msk   (1UL << ITM_LSR_Present_Pos)
+
+

ITM LSR: Present Mask

+ +
+
+ +
+
+ + + + +
#define ITM_LSR_Present_Pos   0
+
+

ITM LSR: Present Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
+
+

ITM TCR: BUSY Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_BUSY_Pos   23
+
+

ITM TCR: BUSY Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
+
+

ITM TCR: DWTENA Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_DWTENA_Pos   3
+
+

ITM TCR: DWTENA Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
+
+

ITM TCR: Global timestamp frequency Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_GTSFREQ_Pos   10
+
+

ITM TCR: Global timestamp frequency Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_ITMENA_Msk   (1UL << ITM_TCR_ITMENA_Pos)
+
+

ITM TCR: ITM Enable bit Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_ITMENA_Pos   0
+
+

ITM TCR: ITM Enable bit Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
+
+

ITM TCR: SWOENA Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_SWOENA_Pos   4
+
+

ITM TCR: SWOENA Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
+
+

ITM TCR: SYNCENA Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_SYNCENA_Pos   2
+
+

ITM TCR: SYNCENA Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
+
+

ITM TCR: ATBID Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TraceBusID_Pos   16
+
+

ITM TCR: ATBID Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
+
+

ITM TCR: TSENA Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TSENA_Pos   1
+
+

ITM TCR: TSENA Position

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
+
+

ITM TCR: TSPrescale Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TCR_TSPrescale_Pos   8
+
+

ITM TCR: TSPrescale Position

+ +
+
+ +
+
+ + + + +
#define ITM_TPR_PRIVMASK_Msk   (0xFUL << ITM_TPR_PRIVMASK_Pos)
+
+

ITM TPR: PRIVMASK Mask

+ +
+
+ +
+
+ + + + +
#define ITM_TPR_PRIVMASK_Pos   0
+
+

ITM TPR: PRIVMASK Position

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___i_t_m.map b/group___c_m_s_i_s___i_t_m.map new file mode 100644 index 0000000..fd26d40 --- /dev/null +++ b/group___c_m_s_i_s___i_t_m.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___i_t_m.md5 b/group___c_m_s_i_s___i_t_m.md5 new file mode 100644 index 0000000..abeabf1 --- /dev/null +++ b/group___c_m_s_i_s___i_t_m.md5 @@ -0,0 +1 @@ +cab3d787adb84090c1d1c80bcd58c16e \ No newline at end of file diff --git a/group___c_m_s_i_s___i_t_m.png b/group___c_m_s_i_s___i_t_m.png new file mode 100644 index 0000000..ded7bdc Binary files /dev/null and b/group___c_m_s_i_s___i_t_m.png differ diff --git a/group___c_m_s_i_s___n_v_i_c.html b/group___c_m_s_i_s___n_v_i_c.html new file mode 100644 index 0000000..87f0384 --- /dev/null +++ b/group___c_m_s_i_s___n_v_i_c.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: Nested Vectored Interrupt Controller (NVIC) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Classes | +Macros
+
+
Nested Vectored Interrupt Controller (NVIC)
Defines and Type Definitions
+
+
+ +

Type definitions for the NVIC Registers. +More...

+
+Collaboration diagram for Nested Vectored Interrupt Controller (NVIC):
+
+
+ + +
+
+ + + + + +

+Classes

struct  NVIC_Type
 Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
 
+ + + + + +

+Macros

#define NVIC_STIR_INTID_Pos   0
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL << NVIC_STIR_INTID_Pos)
 
+

Detailed Description

+

Type definitions for the NVIC Registers.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define NVIC_STIR_INTID_Msk   (0x1FFUL << NVIC_STIR_INTID_Pos)
+
+

STIR: INTLINESNUM Mask

+ +
+
+ +
+
+ + + + +
#define NVIC_STIR_INTID_Pos   0
+
+

STIR: INTLINESNUM Position

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___n_v_i_c.map b/group___c_m_s_i_s___n_v_i_c.map new file mode 100644 index 0000000..2cfe685 --- /dev/null +++ b/group___c_m_s_i_s___n_v_i_c.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___n_v_i_c.md5 b/group___c_m_s_i_s___n_v_i_c.md5 new file mode 100644 index 0000000..cec392d --- /dev/null +++ b/group___c_m_s_i_s___n_v_i_c.md5 @@ -0,0 +1 @@ +361e2c628e13d61625de02ae8e805575 \ No newline at end of file diff --git a/group___c_m_s_i_s___n_v_i_c.png b/group___c_m_s_i_s___n_v_i_c.png new file mode 100644 index 0000000..72ac3b3 Binary files /dev/null and b/group___c_m_s_i_s___n_v_i_c.png differ diff --git a/group___c_m_s_i_s___s_c_b.html b/group___c_m_s_i_s___s_c_b.html new file mode 100644 index 0000000..e526969 --- /dev/null +++ b/group___c_m_s_i_s___s_c_b.html @@ -0,0 +1,1828 @@ + + + + + + +discoverpixy: System Control Block (SCB) + + + + + + + + + + +
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discoverpixy +
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+Classes | +Macros
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+
System Control Block (SCB)
Defines and Type Definitions
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+ +

Type definitions for the System Control Block Registers. +More...

+
+Collaboration diagram for System Control Block (SCB):
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+ + + + + +

+Classes

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
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+Macros

#define SCB_CPUID_IMPLEMENTER_Pos   24
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0
 
#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   31
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define SCB_VTOR_TBLOFF_Pos   7
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 
#define SCB_CFSR_USGFAULTSR_Pos   16
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0
 
#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
 
+

Detailed Description

+

Type definitions for the System Control Block Registers.

+

Macro Definition Documentation

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#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
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SCB AIRCR: ENDIANESS Mask

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#define SCB_AIRCR_ENDIANESS_Pos   15
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SCB AIRCR: ENDIANESS Position

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#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
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SCB AIRCR: PRIGROUP Mask

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#define SCB_AIRCR_PRIGROUP_Pos   8
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SCB AIRCR: PRIGROUP Position

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#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
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SCB AIRCR: SYSRESETREQ Mask

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#define SCB_AIRCR_SYSRESETREQ_Pos   2
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SCB AIRCR: SYSRESETREQ Position

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#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
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SCB AIRCR: VECTCLRACTIVE Mask

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#define SCB_AIRCR_VECTCLRACTIVE_Pos   1
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SCB AIRCR: VECTCLRACTIVE Position

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#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
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SCB AIRCR: VECTKEY Mask

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#define SCB_AIRCR_VECTKEY_Pos   16
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SCB AIRCR: VECTKEY Position

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#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
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SCB AIRCR: VECTKEYSTAT Mask

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#define SCB_AIRCR_VECTKEYSTAT_Pos   16
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SCB AIRCR: VECTKEYSTAT Position

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#define SCB_AIRCR_VECTRESET_Msk   (1UL << SCB_AIRCR_VECTRESET_Pos)
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SCB AIRCR: VECTRESET Mask

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#define SCB_AIRCR_VECTRESET_Pos   0
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SCB AIRCR: VECTRESET Position

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#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
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SCB CCR: BFHFNMIGN Mask

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#define SCB_CCR_BFHFNMIGN_Pos   8
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SCB CCR: BFHFNMIGN Position

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#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
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SCB CCR: DIV_0_TRP Mask

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#define SCB_CCR_DIV_0_TRP_Pos   4
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SCB CCR: DIV_0_TRP Position

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#define SCB_CCR_NONBASETHRDENA_Msk   (1UL << SCB_CCR_NONBASETHRDENA_Pos)
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SCB CCR: NONBASETHRDENA Mask

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#define SCB_CCR_NONBASETHRDENA_Pos   0
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SCB CCR: NONBASETHRDENA Position

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#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
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SCB CCR: STKALIGN Mask

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#define SCB_CCR_STKALIGN_Pos   9
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SCB CCR: STKALIGN Position

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#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
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SCB CCR: UNALIGN_TRP Mask

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#define SCB_CCR_UNALIGN_TRP_Pos   3
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SCB CCR: UNALIGN_TRP Position

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#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
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SCB CCR: USERSETMPEND Mask

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#define SCB_CCR_USERSETMPEND_Pos   1
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SCB CCR: USERSETMPEND Position

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#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
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SCB CFSR: Bus Fault Status Register Mask

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#define SCB_CFSR_BUSFAULTSR_Pos   8
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SCB CFSR: Bus Fault Status Register Position

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#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
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SCB CFSR: Memory Manage Fault Status Register Mask

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#define SCB_CFSR_MEMFAULTSR_Pos   0
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SCB CFSR: Memory Manage Fault Status Register Position

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#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
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SCB CFSR: Usage Fault Status Register Mask

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#define SCB_CFSR_USGFAULTSR_Pos   16
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SCB CFSR: Usage Fault Status Register Position

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#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
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SCB CPUID: ARCHITECTURE Mask

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#define SCB_CPUID_ARCHITECTURE_Pos   16
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SCB CPUID: ARCHITECTURE Position

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#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
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SCB CPUID: IMPLEMENTER Mask

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#define SCB_CPUID_IMPLEMENTER_Pos   24
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SCB CPUID: IMPLEMENTER Position

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#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
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SCB CPUID: PARTNO Mask

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#define SCB_CPUID_PARTNO_Pos   4
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SCB CPUID: PARTNO Position

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#define SCB_CPUID_REVISION_Msk   (0xFUL << SCB_CPUID_REVISION_Pos)
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SCB CPUID: REVISION Mask

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#define SCB_CPUID_REVISION_Pos   0
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SCB CPUID: REVISION Position

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#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
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SCB CPUID: VARIANT Mask

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#define SCB_CPUID_VARIANT_Pos   20
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SCB CPUID: VARIANT Position

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#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
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SCB DFSR: BKPT Mask

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#define SCB_DFSR_BKPT_Pos   1
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SCB DFSR: BKPT Position

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#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
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SCB DFSR: DWTTRAP Mask

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#define SCB_DFSR_DWTTRAP_Pos   2
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SCB DFSR: DWTTRAP Position

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#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
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SCB DFSR: EXTERNAL Mask

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#define SCB_DFSR_EXTERNAL_Pos   4
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SCB DFSR: EXTERNAL Position

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#define SCB_DFSR_HALTED_Msk   (1UL << SCB_DFSR_HALTED_Pos)
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SCB DFSR: HALTED Mask

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#define SCB_DFSR_HALTED_Pos   0
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SCB DFSR: HALTED Position

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#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
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SCB DFSR: VCATCH Mask

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#define SCB_DFSR_VCATCH_Pos   3
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SCB DFSR: VCATCH Position

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#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
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SCB HFSR: DEBUGEVT Mask

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#define SCB_HFSR_DEBUGEVT_Pos   31
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SCB HFSR: DEBUGEVT Position

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#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
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SCB HFSR: FORCED Mask

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#define SCB_HFSR_FORCED_Pos   30
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+

SCB HFSR: FORCED Position

+ +
+
+ +
+
+ + + + +
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
+
+

SCB HFSR: VECTTBL Mask

+ +
+
+ +
+
+ + + + +
#define SCB_HFSR_VECTTBL_Pos   1
+
+

SCB HFSR: VECTTBL Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
+
+

SCB ICSR: ISRPENDING Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_ISRPENDING_Pos   22
+
+

SCB ICSR: ISRPENDING Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
+
+

SCB ICSR: ISRPREEMPT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_ISRPREEMPT_Pos   23
+
+

SCB ICSR: ISRPREEMPT Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
+
+

SCB ICSR: NMIPENDSET Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_NMIPENDSET_Pos   31
+
+

SCB ICSR: NMIPENDSET Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
+
+

SCB ICSR: PENDSTCLR Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSTCLR_Pos   25
+
+

SCB ICSR: PENDSTCLR Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
+
+

SCB ICSR: PENDSTSET Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSTSET_Pos   26
+
+

SCB ICSR: PENDSTSET Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
+
+

SCB ICSR: PENDSVCLR Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSVCLR_Pos   27
+
+

SCB ICSR: PENDSVCLR Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
+
+

SCB ICSR: PENDSVSET Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_PENDSVSET_Pos   28
+
+

SCB ICSR: PENDSVSET Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
+
+

SCB ICSR: RETTOBASE Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_RETTOBASE_Pos   11
+
+

SCB ICSR: RETTOBASE Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
+
+

SCB ICSR: VECTACTIVE Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_VECTACTIVE_Pos   0
+
+

SCB ICSR: VECTACTIVE Position

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
+
+

SCB ICSR: VECTPENDING Mask

+ +
+
+ +
+
+ + + + +
#define SCB_ICSR_VECTPENDING_Pos   12
+
+

SCB ICSR: VECTPENDING Position

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
+
+

SCB SCR: SEVONPEND Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SEVONPEND_Pos   4
+
+

SCB SCR: SEVONPEND Position

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
+
+

SCB SCR: SLEEPDEEP Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SLEEPDEEP_Pos   2
+
+

SCB SCR: SLEEPDEEP Position

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
+
+

SCB SCR: SLEEPONEXIT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SCR_SLEEPONEXIT_Pos   1
+
+

SCB SCR: SLEEPONEXIT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
+
+

SCB SHCSR: BUSFAULTACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTACT_Pos   1
+
+

SCB SHCSR: BUSFAULTACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
+
+

SCB SHCSR: BUSFAULTENA Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTENA_Pos   17
+
+

SCB SHCSR: BUSFAULTENA Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
+
+

SCB SHCSR: BUSFAULTPENDED Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14
+
+

SCB SHCSR: BUSFAULTPENDED Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
+
+

SCB SHCSR: MEMFAULTACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTACT_Pos   0
+
+

SCB SHCSR: MEMFAULTACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
+
+

SCB SHCSR: MEMFAULTENA Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTENA_Pos   16
+
+

SCB SHCSR: MEMFAULTENA Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
+
+

SCB SHCSR: MEMFAULTPENDED Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13
+
+

SCB SHCSR: MEMFAULTPENDED Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
+
+

SCB SHCSR: MONITORACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_MONITORACT_Pos   8
+
+

SCB SHCSR: MONITORACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
+
+

SCB SHCSR: PENDSVACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_PENDSVACT_Pos   10
+
+

SCB SHCSR: PENDSVACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
+
+

SCB SHCSR: SVCALLACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SVCALLACT_Pos   7
+
+

SCB SHCSR: SVCALLACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
+
+

SCB SHCSR: SVCALLPENDED Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SVCALLPENDED_Pos   15
+
+

SCB SHCSR: SVCALLPENDED Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
+
+

SCB SHCSR: SYSTICKACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_SYSTICKACT_Pos   11
+
+

SCB SHCSR: SYSTICKACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
+
+

SCB SHCSR: USGFAULTACT Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTACT_Pos   3
+
+

SCB SHCSR: USGFAULTACT Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
+
+

SCB SHCSR: USGFAULTENA Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTENA_Pos   18
+
+

SCB SHCSR: USGFAULTENA Position

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
+
+

SCB SHCSR: USGFAULTPENDED Mask

+ +
+
+ +
+
+ + + + +
#define SCB_SHCSR_USGFAULTPENDED_Pos   12
+
+

SCB SHCSR: USGFAULTPENDED Position

+ +
+
+ +
+
+ + + + +
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
+
+

SCB VTOR: TBLOFF Mask

+ +
+
+ +
+
+ + + + +
#define SCB_VTOR_TBLOFF_Pos   7
+
+

SCB VTOR: TBLOFF Position

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___s_c_b.map b/group___c_m_s_i_s___s_c_b.map new file mode 100644 index 0000000..989a15d --- /dev/null +++ b/group___c_m_s_i_s___s_c_b.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___s_c_b.md5 b/group___c_m_s_i_s___s_c_b.md5 new file mode 100644 index 0000000..41108e2 --- /dev/null +++ b/group___c_m_s_i_s___s_c_b.md5 @@ -0,0 +1 @@ +1e2abb23c019110036cdbadee6367666 \ No newline at end of file diff --git a/group___c_m_s_i_s___s_c_b.png b/group___c_m_s_i_s___s_c_b.png new file mode 100644 index 0000000..24f474a Binary files /dev/null and b/group___c_m_s_i_s___s_c_b.png differ diff --git a/group___c_m_s_i_s___s_cn_s_c_b.html b/group___c_m_s_i_s___s_cn_s_c_b.html new file mode 100644 index 0000000..150de73 --- /dev/null +++ b/group___c_m_s_i_s___s_cn_s_c_b.html @@ -0,0 +1,298 @@ + + + + + + +discoverpixy: System Controls not in SCB (SCnSCB) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Classes | +Macros
+
+
System Controls not in SCB (SCnSCB)
Defines and Type Definitions
+
+
+ +

Type definitions for the System Control and ID Register not in the SCB. +More...

+
+Collaboration diagram for System Controls not in SCB (SCnSCB):
+
+
+ + +
+
+ + + + + +

+Classes

struct  SCnSCB_Type
 Structure type to access the System Control and ID Register not in the SCB. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define SCnSCB_ICTR_INTLINESNUM_Pos   0
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
 
#define SCnSCB_ACTLR_DISOOFP_Pos   9
 
#define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
 
#define SCnSCB_ACTLR_DISFPCA_Pos   8
 
#define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
 
#define SCnSCB_ACTLR_DISFOLD_Pos   2
 
#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
 
#define SCnSCB_ACTLR_DISDEFWBUF_Pos   1
 
#define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
 
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0
 
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
 
+

Detailed Description

+

Type definitions for the System Control and ID Register not in the SCB.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
+
+

ACTLR: DISDEFWBUF Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISDEFWBUF_Pos   1
+
+

ACTLR: DISDEFWBUF Position

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
+
+

ACTLR: DISFOLD Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISFOLD_Pos   2
+
+

ACTLR: DISFOLD Position

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
+
+

ACTLR: DISFPCA Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISFPCA_Pos   8
+
+

ACTLR: DISFPCA Position

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
+
+

ACTLR: DISMCYCINT Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0
+
+

ACTLR: DISMCYCINT Position

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
+
+

ACTLR: DISOOFP Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ACTLR_DISOOFP_Pos   9
+
+

ACTLR: DISOOFP Position

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
+
+

ICTR: INTLINESNUM Mask

+ +
+
+ +
+
+ + + + +
#define SCnSCB_ICTR_INTLINESNUM_Pos   0
+
+

ICTR: INTLINESNUM Position

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___s_cn_s_c_b.map b/group___c_m_s_i_s___s_cn_s_c_b.map new file mode 100644 index 0000000..4d40564 --- /dev/null +++ b/group___c_m_s_i_s___s_cn_s_c_b.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___s_cn_s_c_b.md5 b/group___c_m_s_i_s___s_cn_s_c_b.md5 new file mode 100644 index 0000000..26d6ed2 --- /dev/null +++ b/group___c_m_s_i_s___s_cn_s_c_b.md5 @@ -0,0 +1 @@ +d574e1d5d67853173230741dc14792fe \ No newline at end of file diff --git a/group___c_m_s_i_s___s_cn_s_c_b.png b/group___c_m_s_i_s___s_cn_s_c_b.png new file mode 100644 index 0000000..332155a Binary files /dev/null and b/group___c_m_s_i_s___s_cn_s_c_b.png differ diff --git a/group___c_m_s_i_s___s_i_m_d__intrinsics.html b/group___c_m_s_i_s___s_i_m_d__intrinsics.html new file mode 100644 index 0000000..d9010e9 --- /dev/null +++ b/group___c_m_s_i_s___s_i_m_d__intrinsics.html @@ -0,0 +1,92 @@ + + + + + + +discoverpixy: CMSIS SIMD Intrinsics + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+
CMSIS SIMD Intrinsics
+
+
+

Access to dedicated SIMD instructions

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___sys_tick.html b/group___c_m_s_i_s___sys_tick.html new file mode 100644 index 0000000..4c7d5e4 --- /dev/null +++ b/group___c_m_s_i_s___sys_tick.html @@ -0,0 +1,388 @@ + + + + + + +discoverpixy: System Tick Timer (SysTick) + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Classes | +Macros
+
+
System Tick Timer (SysTick)
Defines and Type Definitions
+
+
+ +

Type definitions for the System Timer Registers. +More...

+
+Collaboration diagram for System Tick Timer (SysTick):
+
+
+ + +
+
+ + + + + +

+Classes

struct  SysTick_Type
 Structure type to access the System Timer (SysTick). More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define SysTick_CTRL_COUNTFLAG_Pos   16
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0
 
#define SysTick_CTRL_ENABLE_Msk   (1UL << SysTick_CTRL_ENABLE_Pos)
 
#define SysTick_LOAD_RELOAD_Pos   0
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
 
#define SysTick_VAL_CURRENT_Pos   0
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
 
#define SysTick_CALIB_NOREF_Pos   31
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
 
+

Detailed Description

+

Type definitions for the System Timer Registers.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
+
+

SysTick CALIB: NOREF Mask

+ +
+
+ +
+
+ + + + +
#define SysTick_CALIB_NOREF_Pos   31
+
+

SysTick CALIB: NOREF Position

+ +
+
+ +
+
+ + + + +
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
+
+

SysTick CALIB: SKEW Mask

+ +
+
+ +
+
+ + + + +
#define SysTick_CALIB_SKEW_Pos   30
+
+

SysTick CALIB: SKEW Position

+ +
+
+ +
+
+ + + + +
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
+
+

SysTick CALIB: TENMS Mask

+ +
+
+ +
+
+ + + + +
#define SysTick_CALIB_TENMS_Pos   0
+
+

SysTick CALIB: TENMS Position

+ +
+
+ +
+
+ + + + +
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
+
+

SysTick CTRL: CLKSOURCE Mask

+ +
+
+ +
+
+ + + + +
#define SysTick_CTRL_CLKSOURCE_Pos   2
+
+

SysTick CTRL: CLKSOURCE Position

+ +
+
+ +
+
+ + + + +
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
+
+

SysTick CTRL: COUNTFLAG Mask

+ +
+
+ +
+
+ + + + +
#define SysTick_CTRL_COUNTFLAG_Pos   16
+
+

SysTick CTRL: COUNTFLAG Position

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#define SysTick_CTRL_ENABLE_Msk   (1UL << SysTick_CTRL_ENABLE_Pos)
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SysTick CTRL: ENABLE Mask

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#define SysTick_CTRL_ENABLE_Pos   0
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SysTick CTRL: ENABLE Position

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#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
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SysTick CTRL: TICKINT Mask

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#define SysTick_CTRL_TICKINT_Pos   1
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SysTick CTRL: TICKINT Position

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#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
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SysTick LOAD: RELOAD Mask

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#define SysTick_LOAD_RELOAD_Pos   0
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SysTick LOAD: RELOAD Position

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#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
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SysTick VAL: CURRENT Mask

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#define SysTick_VAL_CURRENT_Pos   0
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SysTick VAL: CURRENT Position

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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___sys_tick.map b/group___c_m_s_i_s___sys_tick.map new file mode 100644 index 0000000..b86780b --- /dev/null +++ b/group___c_m_s_i_s___sys_tick.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___sys_tick.md5 b/group___c_m_s_i_s___sys_tick.md5 new file mode 100644 index 0000000..f1def44 --- /dev/null +++ b/group___c_m_s_i_s___sys_tick.md5 @@ -0,0 +1 @@ +cd66807b384a4f416433e340813d2773 \ No newline at end of file diff --git a/group___c_m_s_i_s___sys_tick.png b/group___c_m_s_i_s___sys_tick.png new file mode 100644 index 0000000..c62bdbb Binary files /dev/null and b/group___c_m_s_i_s___sys_tick.png differ diff --git a/group___c_m_s_i_s___t_p_i.html b/group___c_m_s_i_s___t_p_i.html new file mode 100644 index 0000000..01937b8 --- /dev/null +++ b/group___c_m_s_i_s___t_p_i.html @@ -0,0 +1,1138 @@ + + + + + + +discoverpixy: Trace Port Interface (TPI) + + + + + + + + + + +
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discoverpixy +
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+Classes | +Macros
+
+
Trace Port Interface (TPI)
Defines and Type Definitions
+
+
+ +

Type definitions for the Trace Port Interface (TPI) +More...

+
+Collaboration diagram for Trace Port Interface (TPI):
+
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+ + +
+
+ + + + + +

+Classes

struct  TPI_Type
 Structure type to access the Trace Port Interface Register (TPI). More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define TPI_ACPR_PRESCALER_Pos   0
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
 
#define TPI_SPPR_TXMODE_Pos   0
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL << TPI_SPPR_TXMODE_Pos)
 
#define TPI_FFSR_FtNonStop_Pos   3
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL << TPI_FFSR_FlInProg_Pos)
 
#define TPI_FFCR_TrigIn_Pos   8
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL << TPI_FIFO0_ETM0_Pos)
 
#define TPI_ITATBCTR2_ATREADY_Pos   0
 
#define TPI_ITATBCTR2_ATREADY_Msk   (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL << TPI_FIFO1_ITM0_Pos)
 
#define TPI_ITATBCTR0_ATREADY_Pos   0
 
#define TPI_ITATBCTR0_ATREADY_Msk   (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
 
#define TPI_ITCTRL_Mode_Pos   0
 
#define TPI_ITCTRL_Mode_Msk   (0x1UL << TPI_ITCTRL_Mode_Pos)
 
#define TPI_DEVID_NRZVALID_Pos   11
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
 
#define TPI_DEVTYPE_SubType_Pos   0
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL << TPI_DEVTYPE_SubType_Pos)
 
#define TPI_DEVTYPE_MajorType_Pos   4
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
+

Detailed Description

+

Type definitions for the Trace Port Interface (TPI)

+

Macro Definition Documentation

+ +
+
+ + + + +
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
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+

TPI ACPR: PRESCALER Mask

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#define TPI_ACPR_PRESCALER_Pos   0
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TPI ACPR: PRESCALER Position

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#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
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+

TPI DEVID: AsynClkIn Mask

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#define TPI_DEVID_AsynClkIn_Pos   5
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TPI DEVID: AsynClkIn Position

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#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
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TPI DEVID: MANCVALID Mask

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#define TPI_DEVID_MANCVALID_Pos   10
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TPI DEVID: MANCVALID Position

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#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
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TPI DEVID: MinBufSz Mask

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#define TPI_DEVID_MinBufSz_Pos   6
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TPI DEVID: MinBufSz Position

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#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
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TPI DEVID: NrTraceInput Mask

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#define TPI_DEVID_NrTraceInput_Pos   0
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TPI DEVID: NrTraceInput Position

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#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
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TPI DEVID: NRZVALID Mask

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#define TPI_DEVID_NRZVALID_Pos   11
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TPI DEVID: NRZVALID Position

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#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
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TPI DEVID: PTINVALID Mask

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#define TPI_DEVID_PTINVALID_Pos   9
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TPI DEVID: PTINVALID Position

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#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
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TPI DEVTYPE: MajorType Mask

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#define TPI_DEVTYPE_MajorType_Pos   4
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TPI DEVTYPE: MajorType Position

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#define TPI_DEVTYPE_SubType_Msk   (0xFUL << TPI_DEVTYPE_SubType_Pos)
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TPI DEVTYPE: SubType Mask

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#define TPI_DEVTYPE_SubType_Pos   0
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TPI DEVTYPE: SubType Position

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#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
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TPI FFCR: EnFCont Mask

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#define TPI_FFCR_EnFCont_Pos   1
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TPI FFCR: EnFCont Position

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#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
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TPI FFCR: TrigIn Mask

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#define TPI_FFCR_TrigIn_Pos   8
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TPI FFCR: TrigIn Position

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#define TPI_FFSR_FlInProg_Msk   (0x1UL << TPI_FFSR_FlInProg_Pos)
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TPI FFSR: FlInProg Mask

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#define TPI_FFSR_FlInProg_Pos   0
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TPI FFSR: FlInProg Position

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#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
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TPI FFSR: FtNonStop Mask

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#define TPI_FFSR_FtNonStop_Pos   3
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TPI FFSR: FtNonStop Position

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#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
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TPI FFSR: FtStopped Mask

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#define TPI_FFSR_FtStopped_Pos   1
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TPI FFSR: FtStopped Position

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#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
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TPI FFSR: TCPresent Mask

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#define TPI_FFSR_TCPresent_Pos   2
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TPI FFSR: TCPresent Position

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#define TPI_FIFO0_ETM0_Msk   (0xFFUL << TPI_FIFO0_ETM0_Pos)
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TPI FIFO0: ETM0 Mask

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#define TPI_FIFO0_ETM0_Pos   0
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TPI FIFO0: ETM0 Position

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#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
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TPI FIFO0: ETM1 Mask

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#define TPI_FIFO0_ETM1_Pos   8
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TPI FIFO0: ETM1 Position

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#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
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TPI FIFO0: ETM2 Mask

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#define TPI_FIFO0_ETM2_Pos   16
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TPI FIFO0: ETM2 Position

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#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
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TPI FIFO0: ETM_ATVALID Mask

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#define TPI_FIFO0_ETM_ATVALID_Pos   26
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TPI FIFO0: ETM_ATVALID Position

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#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
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TPI FIFO0: ETM_bytecount Mask

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#define TPI_FIFO0_ETM_bytecount_Pos   24
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TPI FIFO0: ETM_bytecount Position

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#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
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TPI FIFO0: ITM_ATVALID Mask

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#define TPI_FIFO0_ITM_ATVALID_Pos   29
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TPI FIFO0: ITM_ATVALID Position

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#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
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TPI FIFO0: ITM_bytecount Mask

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#define TPI_FIFO0_ITM_bytecount_Pos   27
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TPI FIFO0: ITM_bytecount Position

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#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
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TPI FIFO1: ETM_ATVALID Mask

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#define TPI_FIFO1_ETM_ATVALID_Pos   26
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TPI FIFO1: ETM_ATVALID Position

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#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
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TPI FIFO1: ETM_bytecount Mask

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#define TPI_FIFO1_ETM_bytecount_Pos   24
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TPI FIFO1: ETM_bytecount Position

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#define TPI_FIFO1_ITM0_Msk   (0xFFUL << TPI_FIFO1_ITM0_Pos)
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TPI FIFO1: ITM0 Mask

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#define TPI_FIFO1_ITM0_Pos   0
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TPI FIFO1: ITM0 Position

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#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
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TPI FIFO1: ITM1 Mask

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#define TPI_FIFO1_ITM1_Pos   8
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TPI FIFO1: ITM1 Position

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#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
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TPI FIFO1: ITM2 Mask

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#define TPI_FIFO1_ITM2_Pos   16
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TPI FIFO1: ITM2 Position

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#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
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TPI FIFO1: ITM_ATVALID Mask

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#define TPI_FIFO1_ITM_ATVALID_Pos   29
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TPI FIFO1: ITM_ATVALID Position

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#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
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TPI FIFO1: ITM_bytecount Mask

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#define TPI_FIFO1_ITM_bytecount_Pos   27
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TPI FIFO1: ITM_bytecount Position

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#define TPI_ITATBCTR0_ATREADY_Msk   (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
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TPI ITATBCTR0: ATREADY Mask

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#define TPI_ITATBCTR0_ATREADY_Pos   0
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TPI ITATBCTR0: ATREADY Position

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#define TPI_ITATBCTR2_ATREADY_Msk   (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
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TPI ITATBCTR2: ATREADY Mask

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#define TPI_ITATBCTR2_ATREADY_Pos   0
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TPI ITATBCTR2: ATREADY Position

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#define TPI_ITCTRL_Mode_Msk   (0x1UL << TPI_ITCTRL_Mode_Pos)
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TPI ITCTRL: Mode Mask

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#define TPI_ITCTRL_Mode_Pos   0
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TPI ITCTRL: Mode Position

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#define TPI_SPPR_TXMODE_Msk   (0x3UL << TPI_SPPR_TXMODE_Pos)
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TPI SPPR: TXMODE Mask

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#define TPI_SPPR_TXMODE_Pos   0
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TPI SPPR: TXMODE Position

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#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
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TPI TRIGGER: TRIGGER Mask

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#define TPI_TRIGGER_TRIGGER_Pos   0
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TPI TRIGGER: TRIGGER Position

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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s___t_p_i.map b/group___c_m_s_i_s___t_p_i.map new file mode 100644 index 0000000..b69686f --- /dev/null +++ b/group___c_m_s_i_s___t_p_i.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s___t_p_i.md5 b/group___c_m_s_i_s___t_p_i.md5 new file mode 100644 index 0000000..4f16a14 --- /dev/null +++ b/group___c_m_s_i_s___t_p_i.md5 @@ -0,0 +1 @@ +9a17c2c684a48916420ef79bb5ce8128 \ No newline at end of file diff --git a/group___c_m_s_i_s___t_p_i.png b/group___c_m_s_i_s___t_p_i.png new file mode 100644 index 0000000..cff4365 Binary files /dev/null and b/group___c_m_s_i_s___t_p_i.png differ diff --git a/group___c_m_s_i_s__core___debug_functions.html b/group___c_m_s_i_s__core___debug_functions.html new file mode 100644 index 0000000..d45d83b --- /dev/null +++ b/group___c_m_s_i_s__core___debug_functions.html @@ -0,0 +1,233 @@ + + + + + + +discoverpixy: ITM Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions | +Variables
+
+
ITM Functions
Functions and Instructions Reference
+
+
+ +

Functions that access the ITM debug interface. +More...

+
+Collaboration diagram for ITM Functions:
+
+
+ + +
+
+ + + + +

+Macros

#define ITM_RXBUFFER_EMPTY   0x5AA55AA5
 
+ + + + + + + + + + +

+Functions

__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 ITM Send Character. More...
 
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
 ITM Receive Character. More...
 
__STATIC_INLINE int32_t ITM_CheckChar (void)
 ITM Check Character. More...
 
+ + + +

+Variables

volatile int32_t ITM_RxBuffer
 
+

Detailed Description

+

Functions that access the ITM debug interface.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ITM_RXBUFFER_EMPTY   0x5AA55AA5
+
+

Value identifying ITM_RxBuffer is ready for next character.

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE int32_t ITM_CheckChar (void )
+
+ +

ITM Check Character.

+

The function checks whether a character is pending for reading in the variable ITM_RxBuffer.

+
Returns
0 No character available.
+
+1 Character available.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE int32_t ITM_ReceiveChar (void )
+
+ +

ITM Receive Character.

+

The function inputs a character via the external variable ITM_RxBuffer.

+
Returns
Received character.
+
+-1 No character pending.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+
+ +

ITM Send Character.

+

The function transmits a character via the ITM channel 0, and

    +
  • Just returns when no debugger is connected that has booked the output.
    • +
  • Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
    • +
+
Parameters
+ + +
[in]chCharacter to transmit.
+
+
+
Returns
Character to transmit.
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
volatile int32_t ITM_RxBuffer
+
+

External variable to receive characters.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s__core___debug_functions.map b/group___c_m_s_i_s__core___debug_functions.map new file mode 100644 index 0000000..9a6eac3 --- /dev/null +++ b/group___c_m_s_i_s__core___debug_functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s__core___debug_functions.md5 b/group___c_m_s_i_s__core___debug_functions.md5 new file mode 100644 index 0000000..5415032 --- /dev/null +++ b/group___c_m_s_i_s__core___debug_functions.md5 @@ -0,0 +1 @@ +17f3964819985bf3854f34ca7ea57f54 \ No newline at end of file diff --git a/group___c_m_s_i_s__core___debug_functions.png b/group___c_m_s_i_s__core___debug_functions.png new file mode 100644 index 0000000..530147e Binary files /dev/null and b/group___c_m_s_i_s__core___debug_functions.png differ diff --git a/group___c_m_s_i_s__core__base.html b/group___c_m_s_i_s__core__base.html new file mode 100644 index 0000000..af68c21 --- /dev/null +++ b/group___c_m_s_i_s__core__base.html @@ -0,0 +1,351 @@ + + + + + + +discoverpixy: Core Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Core Definitions
Defines and Type Definitions
+
+
+ +

Definitions for base addresses, unions, and structures. +More...

+
+Collaboration diagram for Core Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define SCS_BASE   (0xE000E000UL)
 
#define ITM_BASE   (0xE0000000UL)
 
#define DWT_BASE   (0xE0001000UL)
 
#define TPI_BASE   (0xE0040000UL)
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
+

Detailed Description

+

Definitions for base addresses, unions, and structures.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
+
+

Core Debug configuration struct

+ +
+
+ +
+
+ + + + +
#define CoreDebug_BASE   (0xE000EDF0UL)
+
+

Core Debug Base Address

+ +
+
+ +
+
+ + + + +
#define DWT   ((DWT_Type *) DWT_BASE )
+
+

DWT configuration struct

+ +
+
+ +
+
+ + + + +
#define DWT_BASE   (0xE0001000UL)
+
+

DWT Base Address

+ +
+
+ +
+
+ + + + +
#define ITM   ((ITM_Type *) ITM_BASE )
+
+

ITM configuration struct

+ +
+
+ +
+
+ + + + +
#define ITM_BASE   (0xE0000000UL)
+
+

ITM Base Address

+ +
+
+ +
+
+ + + + +
#define NVIC   ((NVIC_Type *) NVIC_BASE )
+
+

NVIC configuration struct

+ +
+
+ +
+
+ + + + +
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
+
+

NVIC Base Address

+ +
+
+ +
+
+ + + + +
#define SCB   ((SCB_Type *) SCB_BASE )
+
+

SCB configuration struct

+ +
+
+ +
+
+ + + + +
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
+
+

System Control Block Base Address

+ +
+
+ +
+
+ + + + +
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
+
+

System control Register not in SCB

+ +
+
+ +
+
+ + + + +
#define SCS_BASE   (0xE000E000UL)
+
+

System Control Space Base Address

+ +
+
+ +
+
+ + + + +
#define SysTick   ((SysTick_Type *) SysTick_BASE )
+
+

SysTick configuration struct

+ +
+
+ +
+
+ + + + +
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
+
+

SysTick Base Address

+ +
+
+ +
+
+ + + + +
#define TPI   ((TPI_Type *) TPI_BASE )
+
+

TPI configuration struct

+ +
+
+ +
+
+ + + + +
#define TPI_BASE   (0xE0040000UL)
+
+

TPI Base Address

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s__core__base.map b/group___c_m_s_i_s__core__base.map new file mode 100644 index 0000000..24765e4 --- /dev/null +++ b/group___c_m_s_i_s__core__base.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_m_s_i_s__core__base.md5 b/group___c_m_s_i_s__core__base.md5 new file mode 100644 index 0000000..2d5b058 --- /dev/null +++ b/group___c_m_s_i_s__core__base.md5 @@ -0,0 +1 @@ +9296ef9949005164e8f84316aa0060a7 \ No newline at end of file diff --git a/group___c_m_s_i_s__core__base.png b/group___c_m_s_i_s__core__base.png new file mode 100644 index 0000000..38b2dcb Binary files /dev/null and b/group___c_m_s_i_s__core__base.png differ diff --git a/group___c_m_s_i_s__core__register.html b/group___c_m_s_i_s__core__register.html new file mode 100644 index 0000000..a540c49 --- /dev/null +++ b/group___c_m_s_i_s__core__register.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: Defines and Type Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Defines and Type Definitions
+
+
+ +

Type definitions and defines for Cortex-M processor based devices. +More...

+
+Collaboration diagram for Defines and Type Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Status and Control Registers
 Core Register type definitions.
 
 Nested Vectored Interrupt Controller (NVIC)
 Type definitions for the NVIC Registers.
 
 System Control Block (SCB)
 Type definitions for the System Control Block Registers.
 
 System Controls not in SCB (SCnSCB)
 Type definitions for the System Control and ID Register not in the SCB.
 
 System Tick Timer (SysTick)
 Type definitions for the System Timer Registers.
 
 Instrumentation Trace Macrocell (ITM)
 Type definitions for the Instrumentation Trace Macrocell (ITM)
 
 Data Watchpoint and Trace (DWT)
 Type definitions for the Data Watchpoint and Trace (DWT)
 
 Trace Port Interface (TPI)
 Type definitions for the Trace Port Interface (TPI)
 
 Core Debug Registers (CoreDebug)
 Type definitions for the Core Debug Registers.
 
 Core Definitions
 Definitions for base addresses, unions, and structures.
 
+

Detailed Description

+

Type definitions and defines for Cortex-M processor based devices.

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_m_s_i_s__core__register.map b/group___c_m_s_i_s__core__register.map new file mode 100644 index 0000000..860f538 --- /dev/null +++ b/group___c_m_s_i_s__core__register.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___c_m_s_i_s__core__register.md5 b/group___c_m_s_i_s__core__register.md5 new file mode 100644 index 0000000..54e59a3 --- /dev/null +++ b/group___c_m_s_i_s__core__register.md5 @@ -0,0 +1 @@ +9d52c61287c806d098508af79fa15d64 \ No newline at end of file diff --git a/group___c_m_s_i_s__core__register.png b/group___c_m_s_i_s__core__register.png new file mode 100644 index 0000000..4d15dd9 Binary files /dev/null and b/group___c_m_s_i_s__core__register.png differ diff --git a/group___c_m_s_i_s__glob__defs.html b/group___c_m_s_i_s__glob__defs.html new file mode 100644 index 0000000..ff84fb2 --- /dev/null +++ b/group___c_m_s_i_s__glob__defs.html @@ -0,0 +1,95 @@ + + + + + + +discoverpixy: CMSIS Global Defines + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+
CMSIS Global Defines
+
+
+

IO Type Qualifiers are used

    +
  • to specify the access to peripheral variables.
    • +
  • for automatic generation of peripheral register debug information.
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_c.html b/group___c_r_c.html new file mode 100644 index 0000000..1038cb7 --- /dev/null +++ b/group___c_r_c.html @@ -0,0 +1,328 @@ + + + + + + +discoverpixy: CRC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Functions
+
+
CRC
STM32F4xx_StdPeriph_Driver
+
+
+ +

CRC driver modules. +More...

+
+Collaboration diagram for CRC:
+
+
+ + +
+
+ + + + + + +

+Modules

 CRC_Exported_Constants
 
 CRC_Private_Functions
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

void CRC_ResetDR (void)
 Resets the CRC Data register (DR). More...
 
uint32_t CRC_CalcCRC (uint32_t Data)
 Computes the 32-bit CRC of a given data word(32-bit). More...
 
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
 Computes the 32-bit CRC of a given buffer of data word(32-bit). More...
 
uint32_t CRC_GetCRC (void)
 Returns the current CRC value. More...
 
void CRC_SetIDRegister (uint8_t IDValue)
 Stores a 8-bit data in the Independent Data(ID) register. More...
 
uint8_t CRC_GetIDRegister (void)
 Returns the 8-bit data stored in the Independent Data(ID) register. More...
 
+

Detailed Description

+

CRC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[],
uint32_t BufferLength 
)
+
+ +

Computes the 32-bit CRC of a given buffer of data word(32-bit).

+
Parameters
+ + + +
pBufferpointer to the buffer containing the data to be computed
BufferLengthlength of the buffer to be computed
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CRC_CalcCRC (uint32_t Data)
+
+ +

Computes the 32-bit CRC of a given data word(32-bit).

+
Parameters
+ + +
Datadata word(32-bit) to compute its CRC
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CRC_GetCRC (void )
+
+ +

Returns the current CRC value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CRC_GetIDRegister (void )
+
+ +

Returns the 8-bit data stored in the Independent Data(ID) register.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
8-bitvalue of the ID register
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CRC_ResetDR (void )
+
+ +

Resets the CRC Data register (DR).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CRC_SetIDRegister (uint8_t IDValue)
+
+ +

Stores a 8-bit data in the Independent Data(ID) register.

+
Parameters
+ + +
IDValue8-bit value to be stored in the ID register
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_c.map b/group___c_r_c.map new file mode 100644 index 0000000..5d472ac --- /dev/null +++ b/group___c_r_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___c_r_c.md5 b/group___c_r_c.md5 new file mode 100644 index 0000000..f3a9066 --- /dev/null +++ b/group___c_r_c.md5 @@ -0,0 +1 @@ +848eb1671b84d6215c1a1838103a6dab \ No newline at end of file diff --git a/group___c_r_c.png b/group___c_r_c.png new file mode 100644 index 0000000..0273e1f Binary files /dev/null and b/group___c_r_c.png differ diff --git a/group___c_r_c___exported___constants.html b/group___c_r_c___exported___constants.html new file mode 100644 index 0000000..8b3b2bf --- /dev/null +++ b/group___c_r_c___exported___constants.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: CRC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+
CRC_Exported_Constants
STM32F4xx_StdPeriph_Driver » CRC
+
+
+
+Collaboration diagram for CRC_Exported_Constants:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_c___exported___constants.map b/group___c_r_c___exported___constants.map new file mode 100644 index 0000000..ae06eff --- /dev/null +++ b/group___c_r_c___exported___constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_c___exported___constants.md5 b/group___c_r_c___exported___constants.md5 new file mode 100644 index 0000000..6c67a25 --- /dev/null +++ b/group___c_r_c___exported___constants.md5 @@ -0,0 +1 @@ +9072da8f0b605aac6005d07e84a7170c \ No newline at end of file diff --git a/group___c_r_c___exported___constants.png b/group___c_r_c___exported___constants.png new file mode 100644 index 0000000..be060da Binary files /dev/null and b/group___c_r_c___exported___constants.png differ diff --git a/group___c_r_c___private___functions.html b/group___c_r_c___private___functions.html new file mode 100644 index 0000000..ab6eb59 --- /dev/null +++ b/group___c_r_c___private___functions.html @@ -0,0 +1,316 @@ + + + + + + +discoverpixy: CRC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
CRC_Private_Functions
STM32F4xx_StdPeriph_Driver » CRC
+
+
+
+Collaboration diagram for CRC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void CRC_ResetDR (void)
 Resets the CRC Data register (DR). More...
 
uint32_t CRC_CalcCRC (uint32_t Data)
 Computes the 32-bit CRC of a given data word(32-bit). More...
 
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
 Computes the 32-bit CRC of a given buffer of data word(32-bit). More...
 
uint32_t CRC_GetCRC (void)
 Returns the current CRC value. More...
 
void CRC_SetIDRegister (uint8_t IDValue)
 Stores a 8-bit data in the Independent Data(ID) register. More...
 
uint8_t CRC_GetIDRegister (void)
 Returns the 8-bit data stored in the Independent Data(ID) register. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[],
uint32_t BufferLength 
)
+
+ +

Computes the 32-bit CRC of a given buffer of data word(32-bit).

+
Parameters
+ + + +
pBufferpointer to the buffer containing the data to be computed
BufferLengthlength of the buffer to be computed
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CRC_CalcCRC (uint32_t Data)
+
+ +

Computes the 32-bit CRC of a given data word(32-bit).

+
Parameters
+ + +
Datadata word(32-bit) to compute its CRC
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t CRC_GetCRC (void )
+
+ +

Returns the current CRC value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
32-bitCRC
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t CRC_GetIDRegister (void )
+
+ +

Returns the 8-bit data stored in the Independent Data(ID) register.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
8-bitvalue of the ID register
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CRC_ResetDR (void )
+
+ +

Resets the CRC Data register (DR).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CRC_SetIDRegister (uint8_t IDValue)
+
+ +

Stores a 8-bit data in the Independent Data(ID) register.

+
Parameters
+ + +
IDValue8-bit value to be stored in the ID register
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_c___private___functions.map b/group___c_r_c___private___functions.map new file mode 100644 index 0000000..9ad5a75 --- /dev/null +++ b/group___c_r_c___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_c___private___functions.md5 b/group___c_r_c___private___functions.md5 new file mode 100644 index 0000000..ce506fe --- /dev/null +++ b/group___c_r_c___private___functions.md5 @@ -0,0 +1 @@ +53eb29e60660520bfcc61d5f1fd7a371 \ No newline at end of file diff --git a/group___c_r_c___private___functions.png b/group___c_r_c___private___functions.png new file mode 100644 index 0000000..7d64270 Binary files /dev/null and b/group___c_r_c___private___functions.png differ diff --git a/group___c_r_y_p.html b/group___c_r_y_p.html new file mode 100644 index 0000000..b5910d1 --- /dev/null +++ b/group___c_r_y_p.html @@ -0,0 +1,1833 @@ + + + + + + +discoverpixy: CRYP + + + + + + + + + + +
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+Modules | +Classes | +Macros | +Functions
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+
CRYP
STM32F4xx_StdPeriph_Driver
+
+
+ +

CRYP driver modules. +More...

+
+Collaboration diagram for CRYP:
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+ + + + + + +

+Modules

 CRYP_Exported_Constants
 
 CRYP_Private_Functions
 
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+Classes

struct  CRYP_InitTypeDef
 CRYP Init structure definition. More...
 
struct  CRYP_KeyInitTypeDef
 CRYP Key(s) structure definition. More...
 
struct  CRYP_IVInitTypeDef
 CRYP Initialization Vectors (IV) structure definition. More...
 
struct  CRYP_Context
 CRYP context swapping structure definition. More...
 
+ + + + + + + + + + + +

+Macros

+#define FLAG_MASK   ((uint8_t)0x20)
 
+#define MAX_TIMEOUT   ((uint16_t)0xFFFF)
 
+#define AESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+#define DESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+#define TDESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
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+Functions

void CRYP_DeInit (void)
 Deinitializes the CRYP peripheral registers to their default reset values. More...
 
void CRYP_Init (CRYP_InitTypeDef *CRYP_InitStruct)
 Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct. More...
 
void CRYP_StructInit (CRYP_InitTypeDef *CRYP_InitStruct)
 Fills each CRYP_InitStruct member with its default value. More...
 
void CRYP_KeyInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct. More...
 
void CRYP_KeyStructInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Fills each CRYP_KeyInitStruct member with its default value. More...
 
void CRYP_IVInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct. More...
 
void CRYP_IVStructInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Fills each CRYP_IVInitStruct member with its default value. More...
 
void CRYP_Cmd (FunctionalState NewState)
 Enables or disables the CRYP peripheral. More...
 
void CRYP_PhaseConfig (uint32_t CRYP_Phase)
 Configures the AES-CCM and AES-GCM phases. More...
 
void CRYP_FIFOFlush (void)
 Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset) More...
 
void CRYP_DataIn (uint32_t Data)
 Writes data in the Data Input register (DIN). More...
 
uint32_t CRYP_DataOut (void)
 Returns the last data entered into the output FIFO. More...
 
ErrorStatus CRYP_SaveContext (CRYP_Context *CRYP_ContextSave, CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Saves the CRYP peripheral Context. More...
 
void CRYP_RestoreContext (CRYP_Context *CRYP_ContextRestore)
 Restores the CRYP peripheral Context. More...
 
void CRYP_DMACmd (uint8_t CRYP_DMAReq, FunctionalState NewState)
 Enables or disables the CRYP DMA interface. More...
 
void CRYP_ITConfig (uint8_t CRYP_IT, FunctionalState NewState)
 Enables or disables the specified CRYP interrupts. More...
 
ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
 Checks whether the specified CRYP interrupt has occurred or not. More...
 
FunctionalState CRYP_GetCmdStatus (void)
 Returns whether CRYP peripheral is enabled or disabled. More...
 
FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
 Checks whether the specified CRYP flag is set or not. More...
 
ErrorStatus CRYP_AES_ECB (uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in ECB Mode. More...
 
ErrorStatus CRYP_AES_CBC (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CBC Mode. More...
 
ErrorStatus CRYP_AES_CTR (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CTR Mode. More...
 
ErrorStatus CRYP_AES_GCM (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG)
 Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_AES_CCM (uint8_t Mode, uint8_t *Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize)
 Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_TDES_ECB (uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in ECB Mode. More...
 
ErrorStatus CRYP_TDES_CBC (uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in CBC Mode. More...
 
ErrorStatus CRYP_DES_ECB (uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in ECB Mode. More...
 
ErrorStatus CRYP_DES_CBC (uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in CBC Mode. More...
 
+

Detailed Description

+

CRYP driver modules.

+

Function Documentation

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ErrorStatus CRYP_AES_CBC (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in CBC Mode.

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Parameters
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Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
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Return values
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AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
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ErrorStatus CRYP_AES_CCM (uint8_t Mode,
uint8_t * Nonce,
uint32_t NonceSize,
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t ILength,
uint8_t * Header,
uint32_t HLength,
uint8_t * HBuffer,
uint8_t * Output,
uint8_t * AuthTAG,
uint32_t TAGSize 
)
+
+ +

Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices.

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Parameters
+ + + + + + + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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Noncethe nounce used for AES algorithm. It shall be unique for each processing.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer in bytes, must be a multiple of 16.
Headerpointer to the header buffer.
Hlengthlength of the header buffer in bytes.
HBufferpointer to temporary buffer used to append the header HBuffer size must be equal to Hlength + 21
Outputpointer to the returned buffer.
AuthTAGpointer to the authentication TAG buffer.
TAGSizethe size of the TAG (called also MAC).
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Return values
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AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
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  • ERROR: Operation failed
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ErrorStatus CRYP_AES_CTR (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in CTR Mode.

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Parameters
+ + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
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Return values
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AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
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  • ERROR: Operation failed
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ErrorStatus CRYP_AES_ECB (uint8_t Mode,
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in ECB Mode.

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Parameters
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Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
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Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
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  • ERROR: Operation failed
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ErrorStatus CRYP_AES_GCM (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t ILength,
uint8_t * Header,
uint32_t HLength,
uint8_t * Output,
uint8_t * AuthTAG 
)
+
+ +

Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices.

+
Parameters
+ + + + + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer in bytes, must be a multiple of 16.
Headerpointer to the header buffer.
Hlengthlength of the header buffer in bytes, must be a multiple of 16.
Outputpointer to the returned buffer.
AuthTAGpointer to the authentication TAG buffer.
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Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
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  • ERROR: Operation failed
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void CRYP_Cmd (FunctionalState NewState)
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Enables or disables the CRYP peripheral.

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Parameters
+ + +
NewStatenew state of the CRYP peripheral. This parameter can be: ENABLE or DISABLE.
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Return values
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None
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void CRYP_DataIn (uint32_t Data)
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Writes data in the Data Input register (DIN).

+
Note
After the DIN register has been read once or several times, the FIFO must be flushed (using CRYP_FIFOFlush() function).
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Parameters
+ + +
Datadata to write in Data Input register
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Return values
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None
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uint32_t CRYP_DataOut (void )
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Returns the last data entered into the output FIFO.

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Parameters
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None
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Return values
+ + +
Lastdata entered into the output FIFO.
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void CRYP_DeInit (void )
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Deinitializes the CRYP peripheral registers to their default reset values.

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Parameters
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None
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None
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ErrorStatus CRYP_DES_CBC (uint8_t Mode,
uint8_t Key[8],
uint8_t InitVectors[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using DES in CBC Mode.

+
Parameters
+ + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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KeyKey used for DES algorithm.
InitVectorsInitialisation Vectors used for DES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
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Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
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  • ERROR: Operation failed
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ErrorStatus CRYP_DES_ECB (uint8_t Mode,
uint8_t Key[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using DES in ECB Mode.

+
Parameters
+ + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
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KeyKey used for DES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
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Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
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void CRYP_DMACmd (uint8_t CRYP_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the CRYP DMA interface.

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Parameters
+ + + +
CRYP_DMAReqspecifies the CRYP DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
    • +
  • CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
    • +
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NewStatenew state of the selected CRYP DMA transfer request. This parameter can be: ENABLE or DISABLE.
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Return values
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None
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void CRYP_FIFOFlush (void )
+
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Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset)

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Note
The FIFOs must be flushed only when BUSY flag is reset.
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Parameters
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None
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None
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FunctionalState CRYP_GetCmdStatus (void )
+
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Returns whether CRYP peripheral is enabled or disabled.

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Parameters
+ + +
none.
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Return values
+ + +
Currentstate of the CRYP peripheral (ENABLE or DISABLE).
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FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
+
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Checks whether the specified CRYP flag is set or not.

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Parameters
+ + +
CRYP_FLAGspecifies the CRYP flag to check. This parameter can be one of the following values:
    +
  • CRYP_FLAG_IFEM: Input FIFO Empty flag.
    • +
  • CRYP_FLAG_IFNF: Input FIFO Not Full flag.
    • +
  • CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
    • +
  • CRYP_FLAG_OFFU: Output FIFO Full flag.
    • +
  • CRYP_FLAG_BUSY: Busy flag.
    • +
  • CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
    • +
  • CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
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Thenew state of CRYP_FLAG (SET or RESET).
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ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
+
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Checks whether the specified CRYP interrupt has occurred or not.

+
Note
This function checks the status of the masked interrupt (i.e the interrupt should be previously enabled).
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Parameters
+ + +
CRYP_ITspecifies the CRYP (masked) interrupt source to check. This parameter can be one of the following values:
    +
  • CRYP_IT_INI: Input FIFO interrupt
    • +
  • CRYP_IT_OUTI: Output FIFO interrupt
    • +
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Return values
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Thenew state of CRYP_IT (SET or RESET).
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void CRYP_Init (CRYP_InitTypeDef * CRYP_InitStruct)
+
+ +

Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct.

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Parameters
+ + +
CRYP_InitStructpointer to a CRYP_InitTypeDef structure that contains the configuration information for the CRYP peripheral.
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Return values
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None
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void CRYP_ITConfig (uint8_t CRYP_IT,
FunctionalState NewState 
)
+
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Enables or disables the specified CRYP interrupts.

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Parameters
+ + + +
CRYP_ITspecifies the CRYP interrupt source to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • CRYP_IT_INI: Input FIFO interrupt
    • +
  • CRYP_IT_OUTI: Output FIFO interrupt
    • +
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NewStatenew state of the specified CRYP interrupt. This parameter can be: ENABLE or DISABLE.
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Return values
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None
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void CRYP_IVInit (CRYP_IVInitTypeDef * CRYP_IVInitStruct)
+
+ +

Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct.

+
Parameters
+ + +
CRYP_IVInitStructpointer to a CRYP_IVInitTypeDef structure that contains the configuration information for the CRYP Initialization Vectors(IV).
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Return values
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None
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void CRYP_IVStructInit (CRYP_IVInitTypeDef * CRYP_IVInitStruct)
+
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Fills each CRYP_IVInitStruct member with its default value.

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Parameters
+ + +
CRYP_IVInitStructpointer to a CRYP_IVInitTypeDef Initialization Vectors(IV) structure which will be initialized.
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None
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void CRYP_KeyInit (CRYP_KeyInitTypeDef * CRYP_KeyInitStruct)
+
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Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct.

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Parameters
+ + +
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure that contains the configuration information for the CRYP Keys.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void CRYP_KeyStructInit (CRYP_KeyInitTypeDef * CRYP_KeyInitStruct)
+
+ +

Fills each CRYP_KeyInitStruct member with its default value.

+
Parameters
+ + +
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void CRYP_PhaseConfig (uint32_t CRYP_Phase)
+
+ +

Configures the AES-CCM and AES-GCM phases.

+
Note
This function is used only with AES-CCM or AES-GCM Algorithms
+
Parameters
+ + +
CRYP_Phasespecifies the CRYP AES-CCM and AES-GCM phase to be configured. This parameter can be one of the following values:
    +
  • CRYP_Phase_Init: Initialization phase
    • +
  • CRYP_Phase_Header: Header phase
    • +
  • CRYP_Phase_Payload: Payload phase
    • +
  • CRYP_Phase_Final: Final phase
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
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+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void CRYP_RestoreContext (CRYP_Context * CRYP_ContextRestore)
+
+ +

Restores the CRYP peripheral Context.

+
Note
Since teh DMA transfer is stopped in CRYP_SaveContext() function, after restoring the context, you have to enable the DMA again (if the DMA was previously used).
+
Parameters
+ + +
CRYP_ContextRestorepointer to a CRYP_Context structure that contains the repository for saved context.
+
+
+
Note
The data that were saved during context saving must be rewrited into the IN FIFO.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_SaveContext (CRYP_Context * CRYP_ContextSave,
CRYP_KeyInitTypeDef * CRYP_KeyInitStruct 
)
+
+ +

Saves the CRYP peripheral Context.

+
Note
This function stops DMA transfer before to save the context. After restoring the context, you have to enable the DMA again (if the DMA was previously used).
+
Parameters
+ + + +
CRYP_ContextSavepointer to a CRYP_Context structure that contains the repository for current context.
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure that contains the configuration information for the CRYP Keys.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void CRYP_StructInit (CRYP_InitTypeDef * CRYP_InitStruct)
+
+ +

Fills each CRYP_InitStruct member with its default value.

+
Parameters
+ + +
CRYP_InitStructpointer to a CRYP_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_TDES_CBC (uint8_t Mode,
uint8_t Key[24],
uint8_t InitVectors[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using TDES in CBC Mode.

+
Parameters
+ + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for TDES algorithm.
InitVectorsInitialisation Vectors used for TDES algorithm.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 8.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

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+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_TDES_ECB (uint8_t Mode,
uint8_t Key[24],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using TDES in ECB Mode.

+
Parameters
+ + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for TDES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p.map b/group___c_r_y_p.map new file mode 100644 index 0000000..8bfc2bb --- /dev/null +++ b/group___c_r_y_p.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___c_r_y_p.md5 b/group___c_r_y_p.md5 new file mode 100644 index 0000000..479ad4b --- /dev/null +++ b/group___c_r_y_p.md5 @@ -0,0 +1 @@ +dd24c5917867be69f52016e34c47f535 \ No newline at end of file diff --git a/group___c_r_y_p.png b/group___c_r_y_p.png new file mode 100644 index 0000000..3cabdb4 Binary files /dev/null and b/group___c_r_y_p.png differ diff --git a/group___c_r_y_p___algorithm___direction.html b/group___c_r_y_p___algorithm___direction.html new file mode 100644 index 0000000..84c0e64 --- /dev/null +++ b/group___c_r_y_p___algorithm___direction.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: CRYP_Algorithm_Direction + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CRYP_Algorithm_Direction
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Algorithm_Direction:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define CRYP_AlgoDir_Encrypt   ((uint16_t)0x0000)
 
+#define CRYP_AlgoDir_Decrypt   ((uint16_t)0x0004)
 
#define IS_CRYP_ALGODIR(ALGODIR)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_CRYP_ALGODIR( ALGODIR)
+
+Value:
(((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
+
((ALGODIR) == CRYP_AlgoDir_Decrypt))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___algorithm___direction.map b/group___c_r_y_p___algorithm___direction.map new file mode 100644 index 0000000..2680e57 --- /dev/null +++ b/group___c_r_y_p___algorithm___direction.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___algorithm___direction.md5 b/group___c_r_y_p___algorithm___direction.md5 new file mode 100644 index 0000000..a37f6ce --- /dev/null +++ b/group___c_r_y_p___algorithm___direction.md5 @@ -0,0 +1 @@ +9cec016eb6c6196c0548966cb7df61c7 \ No newline at end of file diff --git a/group___c_r_y_p___algorithm___direction.png b/group___c_r_y_p___algorithm___direction.png new file mode 100644 index 0000000..752eaee Binary files /dev/null and b/group___c_r_y_p___algorithm___direction.png differ diff --git a/group___c_r_y_p___algorithm___mode.html b/group___c_r_y_p___algorithm___mode.html new file mode 100644 index 0000000..f290151 --- /dev/null +++ b/group___c_r_y_p___algorithm___mode.html @@ -0,0 +1,204 @@ + + + + + + +discoverpixy: CRYP_Algorithm_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CRYP_Algorithm_Mode
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Algorithm_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CRYP_AlgoMode_TDES_ECB   ((uint32_t)0x00000000)
 
#define CRYP_AlgoMode_TDES_CBC   ((uint32_t)0x00000008)
 
+#define CRYP_AlgoMode_DES_ECB   ((uint32_t)0x00000010)
 
#define CRYP_AlgoMode_DES_CBC   ((uint32_t)0x00000018)
 
+#define CRYP_AlgoMode_AES_ECB   ((uint32_t)0x00000020)
 
+#define CRYP_AlgoMode_AES_CBC   ((uint32_t)0x00000028)
 
+#define CRYP_AlgoMode_AES_CTR   ((uint32_t)0x00000030)
 
+#define CRYP_AlgoMode_AES_Key   ((uint32_t)0x00000038)
 
+#define CRYP_AlgoMode_AES_GCM   ((uint32_t)0x00080000)
 
+#define CRYP_AlgoMode_AES_CCM   ((uint32_t)0x00080008)
 
#define IS_CRYP_ALGOMODE(ALGOMODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CRYP_AlgoMode_DES_CBC   ((uint32_t)0x00000018)
+
+

AES Modes

+ +
+
+ +
+
+ + + + +
#define CRYP_AlgoMode_TDES_CBC   ((uint32_t)0x00000008)
+
+

DES Modes

+ +
+
+ +
+
+ + + + +
#define CRYP_AlgoMode_TDES_ECB   ((uint32_t)0x00000000)
+
+

< TDES Modes

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CRYP_ALGOMODE( ALGOMODE)
+
+Value:
(((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
+
((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
+
((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
+
((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
+
((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
+
CRYP_AlgoMode_DES_CBC
#define CRYP_AlgoMode_DES_CBC
Definition: stm32f4xx_cryp.h:146
+
CRYP_AlgoMode_TDES_ECB
#define CRYP_AlgoMode_TDES_ECB
Definition: stm32f4xx_cryp.h:141
+
CRYP_AlgoMode_TDES_CBC
#define CRYP_AlgoMode_TDES_CBC
Definition: stm32f4xx_cryp.h:142
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___algorithm___mode.map b/group___c_r_y_p___algorithm___mode.map new file mode 100644 index 0000000..15c013c --- /dev/null +++ b/group___c_r_y_p___algorithm___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___algorithm___mode.md5 b/group___c_r_y_p___algorithm___mode.md5 new file mode 100644 index 0000000..788ed06 --- /dev/null +++ b/group___c_r_y_p___algorithm___mode.md5 @@ -0,0 +1 @@ +da06884ddf7e7ad1e7c86b30e9c708b8 \ No newline at end of file diff --git a/group___c_r_y_p___algorithm___mode.png b/group___c_r_y_p___algorithm___mode.png new file mode 100644 index 0000000..e76e9ca Binary files /dev/null and b/group___c_r_y_p___algorithm___mode.png differ diff --git a/group___c_r_y_p___d_m_a__transfer__requests.html b/group___c_r_y_p___d_m_a__transfer__requests.html new file mode 100644 index 0000000..e464ce6 --- /dev/null +++ b/group___c_r_y_p___d_m_a__transfer__requests.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: CRYP_DMA_transfer_requests + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CRYP_DMA_transfer_requests
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_DMA_transfer_requests:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define CRYP_DMAReq_DataIN   ((uint8_t)0x01)
 
+#define CRYP_DMAReq_DataOUT   ((uint8_t)0x02)
 
+#define IS_CRYP_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___d_m_a__transfer__requests.map b/group___c_r_y_p___d_m_a__transfer__requests.map new file mode 100644 index 0000000..9a2deae --- /dev/null +++ b/group___c_r_y_p___d_m_a__transfer__requests.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___d_m_a__transfer__requests.md5 b/group___c_r_y_p___d_m_a__transfer__requests.md5 new file mode 100644 index 0000000..4a7ac5a --- /dev/null +++ b/group___c_r_y_p___d_m_a__transfer__requests.md5 @@ -0,0 +1 @@ +a9ccf23b868a43b749c3f6ecf62fd3ef \ No newline at end of file diff --git a/group___c_r_y_p___d_m_a__transfer__requests.png b/group___c_r_y_p___d_m_a__transfer__requests.png new file mode 100644 index 0000000..2f1e27a Binary files /dev/null and b/group___c_r_y_p___d_m_a__transfer__requests.png differ diff --git a/group___c_r_y_p___data___type.html b/group___c_r_y_p___data___type.html new file mode 100644 index 0000000..b2e6b4e --- /dev/null +++ b/group___c_r_y_p___data___type.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: CRYP_Data_Type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
CRYP_Data_Type
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Data_Type:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define CRYP_DataType_32b   ((uint16_t)0x0000)
 
+#define CRYP_DataType_16b   ((uint16_t)0x0040)
 
+#define CRYP_DataType_8b   ((uint16_t)0x0080)
 
+#define CRYP_DataType_1b   ((uint16_t)0x00C0)
 
#define IS_CRYP_DATATYPE(DATATYPE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_CRYP_DATATYPE( DATATYPE)
+
+Value:
(((DATATYPE) == CRYP_DataType_32b) || \
+
((DATATYPE) == CRYP_DataType_16b)|| \
+
((DATATYPE) == CRYP_DataType_8b)|| \
+
((DATATYPE) == CRYP_DataType_1b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___data___type.map b/group___c_r_y_p___data___type.map new file mode 100644 index 0000000..e54f2db --- /dev/null +++ b/group___c_r_y_p___data___type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___data___type.md5 b/group___c_r_y_p___data___type.md5 new file mode 100644 index 0000000..88fbeff --- /dev/null +++ b/group___c_r_y_p___data___type.md5 @@ -0,0 +1 @@ +fee07f2585686255eafe6fa771b92792 \ No newline at end of file diff --git a/group___c_r_y_p___data___type.png b/group___c_r_y_p___data___type.png new file mode 100644 index 0000000..c92066e Binary files /dev/null and b/group___c_r_y_p___data___type.png differ diff --git a/group___c_r_y_p___encryption___decryption__modes__definition.html b/group___c_r_y_p___encryption___decryption__modes__definition.html new file mode 100644 index 0000000..a05fff1 --- /dev/null +++ b/group___c_r_y_p___encryption___decryption__modes__definition.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: CRYP_Encryption_Decryption_modes_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
CRYP_Encryption_Decryption_modes_definition
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Encryption_Decryption_modes_definition:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define MODE_ENCRYPT   ((uint8_t)0x01)
 
+#define MODE_DECRYPT   ((uint8_t)0x00)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___encryption___decryption__modes__definition.map b/group___c_r_y_p___encryption___decryption__modes__definition.map new file mode 100644 index 0000000..f271b48 --- /dev/null +++ b/group___c_r_y_p___encryption___decryption__modes__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___encryption___decryption__modes__definition.md5 b/group___c_r_y_p___encryption___decryption__modes__definition.md5 new file mode 100644 index 0000000..4c8bc8a --- /dev/null +++ b/group___c_r_y_p___encryption___decryption__modes__definition.md5 @@ -0,0 +1 @@ +679b6a653b16f0659dbee3c8d8cd2da2 \ No newline at end of file diff --git a/group___c_r_y_p___encryption___decryption__modes__definition.png b/group___c_r_y_p___encryption___decryption__modes__definition.png new file mode 100644 index 0000000..5537ff4 Binary files /dev/null and b/group___c_r_y_p___encryption___decryption__modes__definition.png differ diff --git a/group___c_r_y_p___exported___constants.html b/group___c_r_y_p___exported___constants.html new file mode 100644 index 0000000..cfb64ff --- /dev/null +++ b/group___c_r_y_p___exported___constants.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: CRYP_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
CRYP_Exported_Constants
STM32F4xx_StdPeriph_Driver » CRYP
+
+
+
+Collaboration diagram for CRYP_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Modules

 CRYP_Algorithm_Direction
 
 CRYP_Algorithm_Mode
 
 CRYP_Phase
 
 CRYP_Data_Type
 
 CRYP_Key_Size_for_AES_only
 
 CRYP_flags_definition
 
 CRYP_interrupts_definition
 
 CRYP_Encryption_Decryption_modes_definition
 
 CRYP_DMA_transfer_requests
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___exported___constants.map b/group___c_r_y_p___exported___constants.map new file mode 100644 index 0000000..1609d88 --- /dev/null +++ b/group___c_r_y_p___exported___constants.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___c_r_y_p___exported___constants.md5 b/group___c_r_y_p___exported___constants.md5 new file mode 100644 index 0000000..32163d2 --- /dev/null +++ b/group___c_r_y_p___exported___constants.md5 @@ -0,0 +1 @@ +e1703dea1a09c2ed3ed3c93908e31bbd \ No newline at end of file diff --git a/group___c_r_y_p___exported___constants.png b/group___c_r_y_p___exported___constants.png new file mode 100644 index 0000000..b0a7eca Binary files /dev/null and b/group___c_r_y_p___exported___constants.png differ diff --git a/group___c_r_y_p___group1.html b/group___c_r_y_p___group1.html new file mode 100644 index 0000000..4ef0e81 --- /dev/null +++ b/group___c_r_y_p___group1.html @@ -0,0 +1,536 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CRYP_DeInit (void)
 Deinitializes the CRYP peripheral registers to their default reset values. More...
 
void CRYP_Init (CRYP_InitTypeDef *CRYP_InitStruct)
 Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct. More...
 
void CRYP_StructInit (CRYP_InitTypeDef *CRYP_InitStruct)
 Fills each CRYP_InitStruct member with its default value. More...
 
void CRYP_KeyInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct. More...
 
void CRYP_KeyStructInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Fills each CRYP_KeyInitStruct member with its default value. More...
 
void CRYP_IVInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct. More...
 
void CRYP_IVStructInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Fills each CRYP_IVInitStruct member with its default value. More...
 
void CRYP_PhaseConfig (uint32_t CRYP_Phase)
 Configures the AES-CCM and AES-GCM phases. More...
 
void CRYP_FIFOFlush (void)
 Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset) More...
 
void CRYP_Cmd (FunctionalState NewState)
 Enables or disables the CRYP peripheral. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the cryptographic Processor using CRYP_Init() function 
+       (++)  Encrypt or Decrypt 
+       (++)  mode : TDES-ECB, TDES-CBC, 
+                    DES-ECB, DES-CBC, 
+                    AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM 
+       (++) DataType :  32-bit data, 16-bit data, bit data or bit-string
+       (++) Key Size (only in AES modes)
+   (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function 
+   (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using 
+       CRYP_IVInit() function.  
+   (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.                         
+   (+) Enable or disable the CRYP Processor using CRYP_Cmd() function

Function Documentation

+ +
+
+ + + + + + + + +
void CRYP_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the CRYP peripheral.

+
Parameters
+ + +
NewStatenew state of the CRYP peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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void CRYP_DeInit (void )
+
+ +

Deinitializes the CRYP peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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void CRYP_FIFOFlush (void )
+
+ +

Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset)

+
Note
The FIFOs must be flushed only when BUSY flag is reset.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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void CRYP_Init (CRYP_InitTypeDef * CRYP_InitStruct)
+
+ +

Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct.

+
Parameters
+ + +
CRYP_InitStructpointer to a CRYP_InitTypeDef structure that contains the configuration information for the CRYP peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

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void CRYP_IVInit (CRYP_IVInitTypeDef * CRYP_IVInitStruct)
+
+ +

Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct.

+
Parameters
+ + +
CRYP_IVInitStructpointer to a CRYP_IVInitTypeDef structure that contains the configuration information for the CRYP Initialization Vectors(IV).
+
+
+
Return values
+ + +
None
+
+
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void CRYP_IVStructInit (CRYP_IVInitTypeDef * CRYP_IVInitStruct)
+
+ +

Fills each CRYP_IVInitStruct member with its default value.

+
Parameters
+ + +
CRYP_IVInitStructpointer to a CRYP_IVInitTypeDef Initialization Vectors(IV) structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
void CRYP_KeyInit (CRYP_KeyInitTypeDef * CRYP_KeyInitStruct)
+
+ +

Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct.

+
Parameters
+ + +
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure that contains the configuration information for the CRYP Keys.
+
+
+
Return values
+ + +
None
+
+
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void CRYP_KeyStructInit (CRYP_KeyInitTypeDef * CRYP_KeyInitStruct)
+
+ +

Fills each CRYP_KeyInitStruct member with its default value.

+
Parameters
+ + +
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
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void CRYP_PhaseConfig (uint32_t CRYP_Phase)
+
+ +

Configures the AES-CCM and AES-GCM phases.

+
Note
This function is used only with AES-CCM or AES-GCM Algorithms
+
Parameters
+ + +
CRYP_Phasespecifies the CRYP AES-CCM and AES-GCM phase to be configured. This parameter can be one of the following values:
    +
  • CRYP_Phase_Init: Initialization phase
    • +
  • CRYP_Phase_Header: Header phase
    • +
  • CRYP_Phase_Payload: Payload phase
    • +
  • CRYP_Phase_Final: Final phase
    • +
+
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+
Return values
+ + +
None
+
+
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void CRYP_StructInit (CRYP_InitTypeDef * CRYP_InitStruct)
+
+ +

Fills each CRYP_InitStruct member with its default value.

+
Parameters
+ + +
CRYP_InitStructpointer to a CRYP_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+ + + + +discoverpixy: CRYP Data processing functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Functions
+
+
CRYP Data processing functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

CRYP Data processing functions. +More...

+
+Collaboration diagram for CRYP Data processing functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void CRYP_DataIn (uint32_t Data)
 Writes data in the Data Input register (DIN). More...
 
uint32_t CRYP_DataOut (void)
 Returns the last data entered into the output FIFO. More...
 
+

Detailed Description

+

CRYP Data processing functions.

+
 ===============================================================================
+                    ##### CRYP Data processing functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing the encryption and decryption 
+      operations: 
+   (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
+   (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.

Function Documentation

+ +
+
+ + + + + + + + +
void CRYP_DataIn (uint32_t Data)
+
+ +

Writes data in the Data Input register (DIN).

+
Note
After the DIN register has been read once or several times, the FIFO must be flushed (using CRYP_FIFOFlush() function).
+
Parameters
+ + +
Datadata to write in Data Input register
+
+
+
Return values
+ + +
None
+
+
+ +

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uint32_t CRYP_DataOut (void )
+
+ +

Returns the last data entered into the output FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Lastdata entered into the output FIFO.
+
+
+ +

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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group2.map b/group___c_r_y_p___group2.map new file mode 100644 index 0000000..0bd31e6 --- /dev/null +++ b/group___c_r_y_p___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group2.md5 b/group___c_r_y_p___group2.md5 new file mode 100644 index 0000000..8b01a04 --- /dev/null +++ b/group___c_r_y_p___group2.md5 @@ -0,0 +1 @@ +9aa2e503a3989ce8d3a912df28260af1 \ No newline at end of file diff --git a/group___c_r_y_p___group2.png b/group___c_r_y_p___group2.png new file mode 100644 index 0000000..750b1cf Binary files /dev/null and b/group___c_r_y_p___group2.png differ diff --git a/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.map b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.map new file mode 100644 index 0000000..3513386 --- /dev/null +++ b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.md5 b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.md5 new file mode 100644 index 0000000..acd5b3e --- /dev/null +++ b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.md5 @@ -0,0 +1 @@ +fd2c6dc24637c74fb8b3b05d3edb5cb3 \ No newline at end of file diff --git a/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.png b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.png new file mode 100644 index 0000000..1cb415a Binary files /dev/null and b/group___c_r_y_p___group2_ga16dc76244318d464357ee6ff208bf9a4_icgraph.png differ diff --git a/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.map b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.map new file mode 100644 index 0000000..e47cb99 --- /dev/null +++ b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.md5 b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.md5 new file mode 100644 index 0000000..ae28bd5 --- /dev/null +++ b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.md5 @@ -0,0 +1 @@ +e1efdc7603de16ee8b3b955b2cef4d4f \ No newline at end of file diff --git a/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.png b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.png new file mode 100644 index 0000000..aad21f1 Binary files /dev/null and b/group___c_r_y_p___group2_gacbe5fcf4c7e4919192376fa615588b54_icgraph.png differ diff --git a/group___c_r_y_p___group3.html b/group___c_r_y_p___group3.html new file mode 100644 index 0000000..64914c4 --- /dev/null +++ b/group___c_r_y_p___group3.html @@ -0,0 +1,203 @@ + + + + + + +discoverpixy: Context swapping functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Context swapping functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

Context swapping functions. +More...

+
+Collaboration diagram for Context swapping functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

ErrorStatus CRYP_SaveContext (CRYP_Context *CRYP_ContextSave, CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Saves the CRYP peripheral Context. More...
 
void CRYP_RestoreContext (CRYP_Context *CRYP_ContextRestore)
 Restores the CRYP peripheral Context. More...
 
+

Detailed Description

+

Context swapping functions.

+
 ===============================================================================
+                      ##### Context swapping functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to save and store CRYP Context
+
+ [..] It is possible to interrupt an encryption/ decryption/ key generation process 
+      to perform another processing with a higher priority, and to complete the 
+      interrupted process later on, when the higher-priority task is complete. To do 
+      so, the context of the interrupted task must be saved from the CRYP registers 
+      to memory, and then be restored from memory to the CRYP registers.
+   
+   (#) To save the current context, use CRYP_SaveContext() function
+   (#) To restore the saved context, use CRYP_RestoreContext() function

Function Documentation

+ +
+
+ + + + + + + + +
void CRYP_RestoreContext (CRYP_Context * CRYP_ContextRestore)
+
+ +

Restores the CRYP peripheral Context.

+
Note
Since teh DMA transfer is stopped in CRYP_SaveContext() function, after restoring the context, you have to enable the DMA again (if the DMA was previously used).
+
Parameters
+ + +
CRYP_ContextRestorepointer to a CRYP_Context structure that contains the repository for saved context.
+
+
+
Note
The data that were saved during context saving must be rewrited into the IN FIFO.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_SaveContext (CRYP_Context * CRYP_ContextSave,
CRYP_KeyInitTypeDef * CRYP_KeyInitStruct 
)
+
+ +

Saves the CRYP peripheral Context.

+
Note
This function stops DMA transfer before to save the context. After restoring the context, you have to enable the DMA again (if the DMA was previously used).
+
Parameters
+ + + +
CRYP_ContextSavepointer to a CRYP_Context structure that contains the repository for current context.
CRYP_KeyInitStructpointer to a CRYP_KeyInitTypeDef structure that contains the configuration information for the CRYP Keys.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group3.map b/group___c_r_y_p___group3.map new file mode 100644 index 0000000..86d7637 --- /dev/null +++ b/group___c_r_y_p___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group3.md5 b/group___c_r_y_p___group3.md5 new file mode 100644 index 0000000..c5b4863 --- /dev/null +++ b/group___c_r_y_p___group3.md5 @@ -0,0 +1 @@ +e5142b66bd375bc7e80542621e72ca3b \ No newline at end of file diff --git a/group___c_r_y_p___group3.png b/group___c_r_y_p___group3.png new file mode 100644 index 0000000..3ece498 Binary files /dev/null and b/group___c_r_y_p___group3.png differ diff --git a/group___c_r_y_p___group4.html b/group___c_r_y_p___group4.html new file mode 100644 index 0000000..7048c3a --- /dev/null +++ b/group___c_r_y_p___group4.html @@ -0,0 +1,170 @@ + + + + + + +discoverpixy: CRYP's DMA interface Configuration function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
CRYP's DMA interface Configuration function
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

CRYP's DMA interface Configuration function. +More...

+
+Collaboration diagram for CRYP's DMA interface Configuration function:
+
+
+ + +
+
+ + + + + +

+Functions

void CRYP_DMACmd (uint8_t CRYP_DMAReq, FunctionalState NewState)
 Enables or disables the CRYP DMA interface. More...
 
+

Detailed Description

+

CRYP's DMA interface Configuration function.

+
 ===============================================================================
+             ##### CRYP's DMA interface Configuration function #####
+ ===============================================================================  
+ [..] This section provides functions allowing to configure the DMA interface for 
+      CRYP data input and output transfer.
+   
+ [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be 
+      transferred:
+   (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling 
+       the CRYP_DMAReq_DataIN request.
+   (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling 
+       the CRYP_DMAReq_DataOUT request.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void CRYP_DMACmd (uint8_t CRYP_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the CRYP DMA interface.

+
Parameters
+ + + +
CRYP_DMAReqspecifies the CRYP DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
    • +
  • CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
    • +
+
NewStatenew state of the selected CRYP DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group4.map b/group___c_r_y_p___group4.map new file mode 100644 index 0000000..51e7d20 --- /dev/null +++ b/group___c_r_y_p___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group4.md5 b/group___c_r_y_p___group4.md5 new file mode 100644 index 0000000..a97deb0 --- /dev/null +++ b/group___c_r_y_p___group4.md5 @@ -0,0 +1 @@ +b85fb73db28156c086b2946f7db53aaa \ No newline at end of file diff --git a/group___c_r_y_p___group4.png b/group___c_r_y_p___group4.png new file mode 100644 index 0000000..bb86778 Binary files /dev/null and b/group___c_r_y_p___group4.png differ diff --git a/group___c_r_y_p___group5.html b/group___c_r_y_p___group5.html new file mode 100644 index 0000000..80b1a78 --- /dev/null +++ b/group___c_r_y_p___group5.html @@ -0,0 +1,367 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void CRYP_ITConfig (uint8_t CRYP_IT, FunctionalState NewState)
 Enables or disables the specified CRYP interrupts. More...
 
ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
 Checks whether the specified CRYP interrupt has occurred or not. More...
 
FunctionalState CRYP_GetCmdStatus (void)
 Returns whether CRYP peripheral is enabled or disabled. More...
 
FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
 Checks whether the specified CRYP flag is set or not. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to configure the CRYP Interrupts and 
+      to get the status and Interrupts pending bits.
+
+ [..] The CRYP provides 2 Interrupts sources and 7 Flags:
+
+ *** Flags : ***
+ ===============
+ [..] 
+   (#) CRYP_FLAG_IFEM :  Set when Input FIFO is empty. This Flag is cleared only
+       by hardware.
+      
+   (#) CRYP_FLAG_IFNF :  Set when Input FIFO is not full. This Flag is cleared 
+       only by hardware.
+
+
+   (#) CRYP_FLAG_INRIS  : Set when Input FIFO Raw interrupt is pending it gives 
+       the raw interrupt state prior to masking of the input FIFO service interrupt.
+       This Flag is cleared only by hardware.
+     
+   (#) CRYP_FLAG_OFNE   : Set when Output FIFO not empty. This Flag is cleared 
+       only by hardware.
+        
+   (#) CRYP_FLAG_OFFU   : Set when Output FIFO is full. This Flag is cleared only 
+       by hardware.
+                           
+   (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives 
+       the raw interrupt state prior to masking of the output FIFO service interrupt.
+       This Flag is cleared only by hardware.
+                               
+   (#) CRYP_FLAG_BUSY   : Set when the CRYP core is currently processing a block 
+       of data or a key preparation (for AES decryption). This Flag is cleared 
+       only by hardware. To clear it, the CRYP core must be disabled and the last
+       processing has completed. 
+
+ *** Interrupts : ***
+ ====================
+ [..]
+   (#) CRYP_IT_INI   : The input FIFO service interrupt is asserted when there 
+      are less than 4 words in the input FIFO. This interrupt is associated to 
+      CRYP_FLAG_INRIS flag.
+
+      -@- This interrupt is cleared by performing write operations to the input FIFO 
+          until it holds 4 or more words. The input FIFO service interrupt INMIS is 
+          enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the 
+          INMIS signal is low even if the input FIFO is empty.
+
+
+
+   (#) CRYP_IT_OUTI  : The output FIFO service interrupt is asserted when there 
+       is one or more (32-bit word) data items in the output FIFO. This interrupt 
+       is associated to CRYP_FLAG_OUTRIS flag.
+
+       -@- This interrupt is cleared by reading data from the output FIFO until there 
+           is no valid (32-bit) word left (that is, the interrupt follows the state 
+           of the OFNE (output FIFO not empty) flag).
+
+ *** Managing the CRYP controller events : ***
+ =============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the CRYP controller events: Polling mode or Interrupt mode.
+
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) CRYP_GetFlagStatus() : to check if flags events occur. 
+
+       -@@- The CRYPT flags do not need to be cleared since they are cleared as 
+            soon as the associated event are reset.   
+
+
+   (#) In the Interrupt Mode it is advised to use the following functions:
+       (++) CRYP_ITConfig()       : to enable or disable the interrupt source.
+       (++) CRYP_GetITStatus()    : to check if Interrupt occurs.
+
+       -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as 
+             soon as the associated event is reset.

Function Documentation

+ +
+
+ + + + + + + + +
FunctionalState CRYP_GetCmdStatus (void )
+
+ +

Returns whether CRYP peripheral is enabled or disabled.

+
Parameters
+ + +
none.
+
+
+
Return values
+ + +
Currentstate of the CRYP peripheral (ENABLE or DISABLE).
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
+
+ +

Checks whether the specified CRYP flag is set or not.

+
Parameters
+ + +
CRYP_FLAGspecifies the CRYP flag to check. This parameter can be one of the following values:
    +
  • CRYP_FLAG_IFEM: Input FIFO Empty flag.
    • +
  • CRYP_FLAG_IFNF: Input FIFO Not Full flag.
    • +
  • CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
    • +
  • CRYP_FLAG_OFFU: Output FIFO Full flag.
    • +
  • CRYP_FLAG_BUSY: Busy flag.
    • +
  • CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
    • +
  • CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of CRYP_FLAG (SET or RESET).
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
+
+ +

Checks whether the specified CRYP interrupt has occurred or not.

+
Note
This function checks the status of the masked interrupt (i.e the interrupt should be previously enabled).
+
Parameters
+ + +
CRYP_ITspecifies the CRYP (masked) interrupt source to check. This parameter can be one of the following values:
    +
  • CRYP_IT_INI: Input FIFO interrupt
    • +
  • CRYP_IT_OUTI: Output FIFO interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of CRYP_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void CRYP_ITConfig (uint8_t CRYP_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified CRYP interrupts.

+
Parameters
+ + + +
CRYP_ITspecifies the CRYP interrupt source to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • CRYP_IT_INI: Input FIFO interrupt
    • +
  • CRYP_IT_OUTI: Output FIFO interrupt
    • +
+
NewStatenew state of the specified CRYP interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group5.map b/group___c_r_y_p___group5.map new file mode 100644 index 0000000..d277312 --- /dev/null +++ b/group___c_r_y_p___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group5.md5 b/group___c_r_y_p___group5.md5 new file mode 100644 index 0000000..4e4047c --- /dev/null +++ b/group___c_r_y_p___group5.md5 @@ -0,0 +1 @@ +e6ee6463064ef4987530c4ae71879072 \ No newline at end of file diff --git a/group___c_r_y_p___group5.png b/group___c_r_y_p___group5.png new file mode 100644 index 0000000..e28c961 Binary files /dev/null and b/group___c_r_y_p___group5.png differ diff --git a/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.map b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.map new file mode 100644 index 0000000..a91fbf4 --- /dev/null +++ b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.md5 b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.md5 new file mode 100644 index 0000000..19dd103 --- /dev/null +++ b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.md5 @@ -0,0 +1 @@ +723ca8db33e03ed5f8e127cc7e3ebd66 \ No newline at end of file diff --git a/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.png b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.png new file mode 100644 index 0000000..ae7f422 Binary files /dev/null and b/group___c_r_y_p___group5_ga993d568b626a74b2973d4a6848a681f6_icgraph.png differ diff --git a/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.map b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.map new file mode 100644 index 0000000..ddc1e7c --- /dev/null +++ b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.md5 b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.md5 new file mode 100644 index 0000000..1eb6772 --- /dev/null +++ b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.md5 @@ -0,0 +1 @@ +4e2b262f47672bd38fa1a7588040a529 \ No newline at end of file diff --git a/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.png b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.png new file mode 100644 index 0000000..1ad98e9 Binary files /dev/null and b/group___c_r_y_p___group5_gabe26186adf64660a4a573bd6a4368fee_icgraph.png differ diff --git a/group___c_r_y_p___group6.html b/group___c_r_y_p___group6.html new file mode 100644 index 0000000..b9e2101 --- /dev/null +++ b/group___c_r_y_p___group6.html @@ -0,0 +1,648 @@ + + + + + + +discoverpixy: High Level AES functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
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+Functions
+
+
High Level AES functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

High Level AES functions. +More...

+
+Collaboration diagram for High Level AES functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus CRYP_AES_ECB (uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in ECB Mode. More...
 
ErrorStatus CRYP_AES_CBC (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CBC Mode. More...
 
ErrorStatus CRYP_AES_CTR (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CTR Mode. More...
 
ErrorStatus CRYP_AES_GCM (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG)
 Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_AES_CCM (uint8_t Mode, uint8_t *Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize)
 Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
+

Detailed Description

+

High Level AES functions.

+
 ===============================================================================
+                       ##### High Level AES functions #####
+ ===============================================================================

Function Documentation

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ErrorStatus CRYP_AES_CBC (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in CBC Mode.

+
Parameters
+ + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
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ErrorStatus CRYP_AES_CCM (uint8_t Mode,
uint8_t * Nonce,
uint32_t NonceSize,
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t ILength,
uint8_t * Header,
uint32_t HLength,
uint8_t * HBuffer,
uint8_t * Output,
uint8_t * AuthTAG,
uint32_t TAGSize 
)
+
+ +

Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices.

+
Parameters
+ + + + + + + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
Noncethe nounce used for AES algorithm. It shall be unique for each processing.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer in bytes, must be a multiple of 16.
Headerpointer to the header buffer.
Hlengthlength of the header buffer in bytes.
HBufferpointer to temporary buffer used to append the header HBuffer size must be equal to Hlength + 21
Outputpointer to the returned buffer.
AuthTAGpointer to the authentication TAG buffer.
TAGSizethe size of the TAG (called also MAC).
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+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
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ErrorStatus CRYP_AES_CTR (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in CTR Mode.

+
Parameters
+ + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
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ErrorStatus CRYP_AES_ECB (uint8_t Mode,
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using AES in ECB Mode.

+
Parameters
+ + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 16.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
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ErrorStatus CRYP_AES_GCM (uint8_t Mode,
uint8_t InitVectors[16],
uint8_t * Key,
uint16_t Keysize,
uint8_t * Input,
uint32_t ILength,
uint8_t * Header,
uint32_t HLength,
uint8_t * Output,
uint8_t * AuthTAG 
)
+
+ +

Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices.

+
Parameters
+ + + + + + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
InitVectorsInitialisation Vectors used for AES algorithm.
KeyKey used for AES algorithm.
Keysizelength of the Key, must be a 128, 192 or 256.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer in bytes, must be a multiple of 16.
Headerpointer to the header buffer.
Hlengthlength of the header buffer in bytes, must be a multiple of 16.
Outputpointer to the returned buffer.
AuthTAGpointer to the authentication TAG buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group6.map b/group___c_r_y_p___group6.map new file mode 100644 index 0000000..f267ca4 --- /dev/null +++ b/group___c_r_y_p___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group6.md5 b/group___c_r_y_p___group6.md5 new file mode 100644 index 0000000..e90c739 --- /dev/null +++ b/group___c_r_y_p___group6.md5 @@ -0,0 +1 @@ +a5dd11d06ce12c33c3ab7d7f7d3177c1 \ No newline at end of file diff --git a/group___c_r_y_p___group6.png b/group___c_r_y_p___group6.png new file mode 100644 index 0000000..a074000 Binary files /dev/null and b/group___c_r_y_p___group6.png differ diff --git a/group___c_r_y_p___group6_ga2f36aea6e94452e5e5e938547fb89d4c_cgraph.map b/group___c_r_y_p___group6_ga2f36aea6e94452e5e5e938547fb89d4c_cgraph.map new file mode 100644 index 0000000..77f032b --- /dev/null +++ b/group___c_r_y_p___group6_ga2f36aea6e94452e5e5e938547fb89d4c_cgraph.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git 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diff --git a/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.md5 b/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.md5 new file mode 100644 index 0000000..fd9f832 --- /dev/null +++ b/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.md5 @@ -0,0 +1 @@ +38f187f20fb84b1593d1791290f794ad \ No newline at end of file diff --git a/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.png b/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.png new file mode 100644 index 0000000..9e8a4ef Binary files /dev/null and b/group___c_r_y_p___group6_ga74b48d820c5c360eb303fc2fb78af055_cgraph.png differ diff --git a/group___c_r_y_p___group6_ga79ff82ece0e9620dc86d6e57abe639e1_cgraph.map b/group___c_r_y_p___group6_ga79ff82ece0e9620dc86d6e57abe639e1_cgraph.map new file mode 100644 index 0000000..68c6417 --- /dev/null +++ b/group___c_r_y_p___group6_ga79ff82ece0e9620dc86d6e57abe639e1_cgraph.map @@ -0,0 +1,11 @@ + + + + + + + + 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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
High Level TDES functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

High Level TDES functions. +More...

+
+Collaboration diagram for High Level TDES functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

ErrorStatus CRYP_TDES_ECB (uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in ECB Mode. More...
 
ErrorStatus CRYP_TDES_CBC (uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in CBC Mode. More...
 
+

Detailed Description

+

High Level TDES functions.

+
 ===============================================================================
+                      ##### High Level TDES functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_TDES_CBC (uint8_t Mode,
uint8_t Key[24],
uint8_t InitVectors[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using TDES in CBC Mode.

+
Parameters
+ + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for TDES algorithm.
InitVectorsInitialisation Vectors used for TDES algorithm.
Inputpointer to the Input buffer.
Ilengthlength of the Input buffer, must be a multiple of 8.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
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+

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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus CRYP_TDES_ECB (uint8_t Mode,
uint8_t Key[24],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using TDES in ECB Mode.

+
Parameters
+ + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for TDES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group7.map b/group___c_r_y_p___group7.map new file mode 100644 index 0000000..5383a3d --- /dev/null +++ b/group___c_r_y_p___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group7.md5 b/group___c_r_y_p___group7.md5 new file mode 100644 index 0000000..f57037b --- /dev/null +++ b/group___c_r_y_p___group7.md5 @@ -0,0 +1 @@ +b327918392797e856749631e86d2f34e \ No newline at end of file diff --git a/group___c_r_y_p___group7.png b/group___c_r_y_p___group7.png new file mode 100644 index 0000000..b195c18 Binary files /dev/null and b/group___c_r_y_p___group7.png differ diff --git a/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.map b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.map new file mode 100644 index 0000000..70308b0 --- /dev/null +++ b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.md5 b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.md5 new file mode 100644 index 0000000..6e5142c --- /dev/null +++ b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.md5 @@ -0,0 +1 @@ +abd6141eb6352cb9d1ac633065c375a3 \ No newline at end of file diff --git a/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.png b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.png new file mode 100644 index 0000000..8d888f3 Binary files /dev/null and b/group___c_r_y_p___group7_ga17c03ab4f0566fcbc3dd8c052e6f9886_cgraph.png differ diff --git a/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.map b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.map new file mode 100644 index 0000000..d3e4ab5 --- /dev/null +++ b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.md5 b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.md5 new file mode 100644 index 0000000..11ac1d8 --- /dev/null +++ b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.md5 @@ -0,0 +1 @@ +8adbb8aa17b553ca1e92e85cae15f033 \ No newline at end of file diff --git a/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.png b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.png new file mode 100644 index 0000000..04b315d Binary files /dev/null and b/group___c_r_y_p___group7_gabe52a368c4882450c1e82f16bc1eb686_cgraph.png differ diff --git a/group___c_r_y_p___group8.html b/group___c_r_y_p___group8.html new file mode 100644 index 0000000..bc32d78 --- /dev/null +++ b/group___c_r_y_p___group8.html @@ -0,0 +1,285 @@ + + + + + + +discoverpixy: High Level DES functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
High Level DES functions
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Private_Functions
+
+
+ +

High Level DES functions. +More...

+
+Collaboration diagram for High Level DES functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

ErrorStatus CRYP_DES_ECB (uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in ECB Mode. More...
 
ErrorStatus CRYP_DES_CBC (uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in CBC Mode. More...
 
+

Detailed Description

+

High Level DES functions.

+
 ===============================================================================
+                       ##### High Level DES functions #####
+ ===============================================================================
+

Function Documentation

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ErrorStatus CRYP_DES_CBC (uint8_t Mode,
uint8_t Key[8],
uint8_t InitVectors[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using DES in CBC Mode.

+
Parameters
+ + + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for DES algorithm.
InitVectorsInitialisation Vectors used for DES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

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ErrorStatus CRYP_DES_ECB (uint8_t Mode,
uint8_t Key[8],
uint8_t * Input,
uint32_t Ilength,
uint8_t * Output 
)
+
+ +

Encrypt and decrypt using DES in ECB Mode.

+
Parameters
+ + + + + + +
Modeencryption or decryption Mode. This parameter can be one of the following values:
    +
  • MODE_ENCRYPT: Encryption
    • +
  • MODE_DECRYPT: Decryption
    • +
+
KeyKey used for DES algorithm.
Ilengthlength of the Input buffer, must be a multiple of 8.
Inputpointer to the Input buffer.
Outputpointer to the returned buffer.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Operation done
    • +
  • ERROR: Operation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
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+
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+

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+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___group8.map b/group___c_r_y_p___group8.map new file mode 100644 index 0000000..a6109de --- /dev/null +++ b/group___c_r_y_p___group8.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___group8.md5 b/group___c_r_y_p___group8.md5 new file mode 100644 index 0000000..f73a500 --- /dev/null +++ b/group___c_r_y_p___group8.md5 @@ -0,0 +1 @@ +0122783f294331b9ff2fe275776f700a \ No newline at end of file diff --git a/group___c_r_y_p___group8.png b/group___c_r_y_p___group8.png new file mode 100644 index 0000000..4359997 Binary files /dev/null and b/group___c_r_y_p___group8.png differ diff --git a/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.map b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.map new file mode 100644 index 0000000..698bc78 --- /dev/null +++ b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.md5 b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.md5 new file mode 100644 index 0000000..15fcb64 --- /dev/null +++ b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.md5 @@ -0,0 +1 @@ +bb006bfc8b861b9fd4c7cf5b68051520 \ No newline at end of file diff --git a/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.png b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.png new file mode 100644 index 0000000..7dae0ab Binary files /dev/null and b/group___c_r_y_p___group8_ga3b96b7608b39197209abed5f5845f590_cgraph.png differ diff --git a/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.map b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.map new file mode 100644 index 0000000..3a401a1 --- /dev/null +++ b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.md5 b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.md5 new file mode 100644 index 0000000..cacf884 --- /dev/null +++ b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.md5 @@ -0,0 +1 @@ +f080b6f1b0134df95d181f91e98d5732 \ No newline at end of file diff --git a/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.png b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.png new file mode 100644 index 0000000..0df3556 Binary files /dev/null and b/group___c_r_y_p___group8_ga75724391a8560c557e1152b805f5cad1_cgraph.png differ diff --git a/group___c_r_y_p___key___size__for___a_e_s__only.html b/group___c_r_y_p___key___size__for___a_e_s__only.html new file mode 100644 index 0000000..1c684ca --- /dev/null +++ b/group___c_r_y_p___key___size__for___a_e_s__only.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: CRYP_Key_Size_for_AES_only + + + + + + + + + + +
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+
discoverpixy +
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+ +
+ +
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+Macros
+
+
CRYP_Key_Size_for_AES_only
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Key_Size_for_AES_only:
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+ + + + + + + + + + +

+Macros

+#define CRYP_KeySize_128b   ((uint16_t)0x0000)
 
+#define CRYP_KeySize_192b   ((uint16_t)0x0100)
 
+#define CRYP_KeySize_256b   ((uint16_t)0x0200)
 
#define IS_CRYP_KEYSIZE(KEYSIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_CRYP_KEYSIZE( KEYSIZE)
+
+Value:
(((KEYSIZE) == CRYP_KeySize_128b)|| \
+
((KEYSIZE) == CRYP_KeySize_192b)|| \
+
((KEYSIZE) == CRYP_KeySize_256b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___key___size__for___a_e_s__only.map b/group___c_r_y_p___key___size__for___a_e_s__only.map new file mode 100644 index 0000000..bacaf94 --- /dev/null +++ b/group___c_r_y_p___key___size__for___a_e_s__only.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___key___size__for___a_e_s__only.md5 b/group___c_r_y_p___key___size__for___a_e_s__only.md5 new file mode 100644 index 0000000..678ebb7 --- /dev/null +++ b/group___c_r_y_p___key___size__for___a_e_s__only.md5 @@ -0,0 +1 @@ +012dd23bb8833599fc1eca91d53661e0 \ No newline at end of file diff --git a/group___c_r_y_p___key___size__for___a_e_s__only.png b/group___c_r_y_p___key___size__for___a_e_s__only.png new file mode 100644 index 0000000..1b54a4d Binary files /dev/null and b/group___c_r_y_p___key___size__for___a_e_s__only.png differ diff --git a/group___c_r_y_p___phase.html b/group___c_r_y_p___phase.html new file mode 100644 index 0000000..55d0386 --- /dev/null +++ b/group___c_r_y_p___phase.html @@ -0,0 +1,154 @@ + + + + + + +discoverpixy: CRYP_Phase + + + + + + + + + + +
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discoverpixy +
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+Macros
+
+
CRYP_Phase
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
+
+
+Collaboration diagram for CRYP_Phase:
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+
+ + +
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+ + + + + + + + + + + + +

+Macros

#define CRYP_Phase_Init   ((uint32_t)0x00000000)
 
+#define CRYP_Phase_Header   CRYP_CR_GCM_CCMPH_0
 
+#define CRYP_Phase_Payload   CRYP_CR_GCM_CCMPH_1
 
+#define CRYP_Phase_Final   CRYP_CR_GCM_CCMPH
 
#define IS_CRYP_PHASE(PHASE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CRYP_Phase_Init   ((uint32_t)0x00000000)
+
+

< The phases are valid only for AES-GCM and AES-CCM modes

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CRYP_PHASE( PHASE)
+
+Value:
(((PHASE) == CRYP_Phase_Init) || \
+
((PHASE) == CRYP_Phase_Header) || \
+
((PHASE) == CRYP_Phase_Payload) || \
+
((PHASE) == CRYP_Phase_Final))
+
CRYP_Phase_Init
#define CRYP_Phase_Init
Definition: stm32f4xx_cryp.h:175
+
+
+
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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___phase.map b/group___c_r_y_p___phase.map new file mode 100644 index 0000000..99b2058 --- /dev/null +++ b/group___c_r_y_p___phase.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p___phase.md5 b/group___c_r_y_p___phase.md5 new file mode 100644 index 0000000..3132de6 --- /dev/null +++ b/group___c_r_y_p___phase.md5 @@ -0,0 +1 @@ +af5b6f463c52425efd976cdf76f2247e \ No newline at end of file diff --git a/group___c_r_y_p___phase.png b/group___c_r_y_p___phase.png new file mode 100644 index 0000000..e51d9ee Binary files /dev/null and b/group___c_r_y_p___phase.png differ diff --git a/group___c_r_y_p___private___functions.html b/group___c_r_y_p___private___functions.html new file mode 100644 index 0000000..16aa6d6 --- /dev/null +++ b/group___c_r_y_p___private___functions.html @@ -0,0 +1,130 @@ + + + + + + +discoverpixy: CRYP_Private_Functions + + + + + + + + + + +
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discoverpixy +
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+Modules
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+
CRYP_Private_Functions
STM32F4xx_StdPeriph_Driver » CRYP
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+
+
+Collaboration diagram for CRYP_Private_Functions:
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+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 CRYP Data processing functions
 CRYP Data processing functions.
 
 Context swapping functions
 Context swapping functions.
 
 CRYP's DMA interface Configuration function
 CRYP's DMA interface Configuration function.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
 High Level AES functions
 High Level AES functions.
 
 High Level DES functions
 High Level DES functions.
 
 High Level TDES functions
 High Level TDES functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p___private___functions.map b/group___c_r_y_p___private___functions.map new file mode 100644 index 0000000..39e236a --- /dev/null +++ b/group___c_r_y_p___private___functions.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___c_r_y_p___private___functions.md5 b/group___c_r_y_p___private___functions.md5 new file mode 100644 index 0000000..e35f062 --- /dev/null +++ b/group___c_r_y_p___private___functions.md5 @@ -0,0 +1 @@ +b0ca70284a6cdb8ab680071e4e511a4d \ No newline at end of file diff --git a/group___c_r_y_p___private___functions.png b/group___c_r_y_p___private___functions.png new file mode 100644 index 0000000..74edc25 Binary files /dev/null and b/group___c_r_y_p___private___functions.png differ diff --git a/group___c_r_y_p__flags__definition.html b/group___c_r_y_p__flags__definition.html new file mode 100644 index 0000000..0731c18 --- /dev/null +++ b/group___c_r_y_p__flags__definition.html @@ -0,0 +1,244 @@ + + + + + + +discoverpixy: CRYP_flags_definition + + + + + + + + + + +
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discoverpixy +
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+Macros
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CRYP_flags_definition
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
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+
+
+Collaboration diagram for CRYP_flags_definition:
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+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

#define CRYP_FLAG_BUSY   ((uint8_t)0x10)
 
#define CRYP_FLAG_IFEM   ((uint8_t)0x01)
 
#define CRYP_FLAG_IFNF   ((uint8_t)0x02)
 
#define CRYP_FLAG_INRIS   ((uint8_t)0x22)
 
#define CRYP_FLAG_OFNE   ((uint8_t)0x04)
 
#define CRYP_FLAG_OFFU   ((uint8_t)0x08)
 
#define CRYP_FLAG_OUTRIS   ((uint8_t)0x21)
 
#define IS_CRYP_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CRYP_FLAG_BUSY   ((uint8_t)0x10)
+
+

The CRYP core is currently processing a block of data or a key preparation (for AES decryption).

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_IFEM   ((uint8_t)0x01)
+
+

Input Fifo Empty

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_IFNF   ((uint8_t)0x02)
+
+

Input Fifo is Not Full

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_INRIS   ((uint8_t)0x22)
+
+

Raw interrupt pending

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_OFFU   ((uint8_t)0x08)
+
+

Output Fifo is Full

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_OFNE   ((uint8_t)0x04)
+
+

Input Fifo service raw interrupt status

+ +
+
+ +
+
+ + + + +
#define CRYP_FLAG_OUTRIS   ((uint8_t)0x21)
+
+

Output Fifo service raw interrupt status

+ +
+
+ +
+
+ + + + + + + + +
#define IS_CRYP_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == CRYP_FLAG_IFEM) || \
+
((FLAG) == CRYP_FLAG_IFNF) || \
+
((FLAG) == CRYP_FLAG_OFNE) || \
+
((FLAG) == CRYP_FLAG_OFFU) || \
+
((FLAG) == CRYP_FLAG_BUSY) || \
+
((FLAG) == CRYP_FLAG_OUTRIS)|| \
+
((FLAG) == CRYP_FLAG_INRIS))
+
CRYP_FLAG_OFFU
#define CRYP_FLAG_OFFU
Definition: stm32f4xx_cryp.h:233
+
CRYP_FLAG_BUSY
#define CRYP_FLAG_BUSY
Definition: stm32f4xx_cryp.h:220
+
CRYP_FLAG_IFEM
#define CRYP_FLAG_IFEM
Definition: stm32f4xx_cryp.h:227
+
CRYP_FLAG_IFNF
#define CRYP_FLAG_IFNF
Definition: stm32f4xx_cryp.h:228
+
CRYP_FLAG_OFNE
#define CRYP_FLAG_OFNE
Definition: stm32f4xx_cryp.h:230
+
CRYP_FLAG_OUTRIS
#define CRYP_FLAG_OUTRIS
Definition: stm32f4xx_cryp.h:234
+
CRYP_FLAG_INRIS
#define CRYP_FLAG_INRIS
Definition: stm32f4xx_cryp.h:229
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___c_r_y_p__flags__definition.map b/group___c_r_y_p__flags__definition.map new file mode 100644 index 0000000..09eed7f --- /dev/null +++ b/group___c_r_y_p__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___c_r_y_p__flags__definition.md5 b/group___c_r_y_p__flags__definition.md5 new file mode 100644 index 0000000..208ad1e --- /dev/null +++ b/group___c_r_y_p__flags__definition.md5 @@ -0,0 +1 @@ +1a0b640bde99706250865b380a9dbccb \ No newline at end of file diff --git a/group___c_r_y_p__flags__definition.png b/group___c_r_y_p__flags__definition.png new file mode 100644 index 0000000..12edce3 Binary files /dev/null and b/group___c_r_y_p__flags__definition.png differ diff --git a/group___c_r_y_p__interrupts__definition.html b/group___c_r_y_p__interrupts__definition.html new file mode 100644 index 0000000..5d53cd4 --- /dev/null +++ b/group___c_r_y_p__interrupts__definition.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: CRYP_interrupts_definition + + + + + + + + + + +
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+Macros
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CRYP_interrupts_definition
STM32F4xx_StdPeriph_Driver » CRYP » CRYP_Exported_Constants
+
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+Collaboration diagram for CRYP_interrupts_definition:
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+ + + + + + + + + + +

+Macros

#define CRYP_IT_INI   ((uint8_t)0x01)
 
#define CRYP_IT_OUTI   ((uint8_t)0x02)
 
+#define IS_CRYP_CONFIG_IT(IT)   ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
 
+#define IS_CRYP_GET_IT(IT)   (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CRYP_IT_INI   ((uint8_t)0x01)
+
+

IN Fifo Interrupt

+ +
+
+ +
+
+ + + + +
#define CRYP_IT_OUTI   ((uint8_t)0x02)
+
+

OUT Fifo Interrupt

+ +
+
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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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file mode 100644 index 0000000..cb25c0c --- /dev/null +++ b/group___c_r_y_p_gaeecd86b00d0d0137d97b06108789bcb2_icgraph.md5 @@ -0,0 +1 @@ +6d4bff35f262f5aa1c1c78d0e67fb79c \ No newline at end of file diff --git a/group___c_r_y_p_gaeecd86b00d0d0137d97b06108789bcb2_icgraph.png b/group___c_r_y_p_gaeecd86b00d0d0137d97b06108789bcb2_icgraph.png new file mode 100644 index 0000000..0b50f91 Binary files /dev/null and b/group___c_r_y_p_gaeecd86b00d0d0137d97b06108789bcb2_icgraph.png differ diff --git a/group___click___interrupt___x_y_z__selection.html b/group___click___interrupt___x_y_z__selection.html new file mode 100644 index 0000000..67fc6f2 --- /dev/null +++ b/group___click___interrupt___x_y_z__selection.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: Click_Interrupt_XYZ_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Click_Interrupt_XYZ_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Click_Interrupt_XYZ_selection:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE   ((uint8_t)0x00)
 
+#define LIS302DL_CLICKINTERRUPT_X_ENABLE   ((uint8_t)0x01)
 
+#define LIS302DL_CLICKINTERRUPT_Y_ENABLE   ((uint8_t)0x04)
 
+#define LIS302DL_CLICKINTERRUPT_Z_ENABLE   ((uint8_t)0x10)
 
+#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE   ((uint8_t)0x15)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___click___interrupt___x_y_z__selection.map b/group___click___interrupt___x_y_z__selection.map new file mode 100644 index 0000000..5a60d00 --- /dev/null +++ b/group___click___interrupt___x_y_z__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___click___interrupt___x_y_z__selection.md5 b/group___click___interrupt___x_y_z__selection.md5 new file mode 100644 index 0000000..8fa6680 --- /dev/null +++ b/group___click___interrupt___x_y_z__selection.md5 @@ -0,0 +1 @@ +3a8a780673aa189643617a11f5198fa8 \ No newline at end of file diff --git a/group___click___interrupt___x_y_z__selection.png b/group___click___interrupt___x_y_z__selection.png new file mode 100644 index 0000000..e529262 Binary files /dev/null and b/group___click___interrupt___x_y_z__selection.png differ diff --git a/group___configuration__section__for___c_m_s_i_s.html b/group___configuration__section__for___c_m_s_i_s.html new file mode 100644 index 0000000..e3ea0b2 --- /dev/null +++ b/group___configuration__section__for___c_m_s_i_s.html @@ -0,0 +1,601 @@ + + + + + + +discoverpixy: Configuration_section_for_CMSIS + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Typedefs | +Enumerations
+
+
Configuration_section_for_CMSIS
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Configuration_section_for_CMSIS:
+
+
+ + +
+
+ + + + + + + + + + + + + +

+Macros

#define __CM4_REV   0x0001
 Configuration of the Cortex-M4 Processor and Core Peripherals. More...
 
#define __MPU_PRESENT   1
 
#define __NVIC_PRIO_BITS   4
 
#define __Vendor_SysTickConfig   0
 
#define __FPU_PRESENT   1
 
+ + + + +

+Typedefs

+typedef enum IRQn IRQn_Type
 STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section.
 
+ + + + +

+Enumerations

enum  IRQn {
+  NonMaskableInt_IRQn = -14, +MemoryManagement_IRQn = -12, +BusFault_IRQn = -11, +UsageFault_IRQn = -10, +
+  SVCall_IRQn = -5, +DebugMonitor_IRQn = -4, +PendSV_IRQn = -2, +SysTick_IRQn = -1, +
+  WWDG_IRQn = 0, +PVD_IRQn = 1, +TAMP_STAMP_IRQn = 2, +RTC_WKUP_IRQn = 3, +
+  FLASH_IRQn = 4, +RCC_IRQn = 5, +EXTI0_IRQn = 6, +EXTI1_IRQn = 7, +
+  EXTI2_IRQn = 8, +EXTI3_IRQn = 9, +EXTI4_IRQn = 10, +DMA1_Stream0_IRQn = 11, +
+  DMA1_Stream1_IRQn = 12, +DMA1_Stream2_IRQn = 13, +DMA1_Stream3_IRQn = 14, +DMA1_Stream4_IRQn = 15, +
+  DMA1_Stream5_IRQn = 16, +DMA1_Stream6_IRQn = 17, +ADC_IRQn = 18, +CAN1_TX_IRQn = 19, +
+  CAN1_RX0_IRQn = 20, +CAN1_RX1_IRQn = 21, +CAN1_SCE_IRQn = 22, +EXTI9_5_IRQn = 23, +
+  TIM1_BRK_TIM9_IRQn = 24, +TIM1_UP_TIM10_IRQn = 25, +TIM1_TRG_COM_TIM11_IRQn = 26, +TIM1_CC_IRQn = 27, +
+  TIM2_IRQn = 28, +TIM3_IRQn = 29, +TIM4_IRQn = 30, +I2C1_EV_IRQn = 31, +
+  I2C1_ER_IRQn = 32, +I2C2_EV_IRQn = 33, +I2C2_ER_IRQn = 34, +SPI1_IRQn = 35, +
+  SPI2_IRQn = 36, +USART1_IRQn = 37, +USART2_IRQn = 38, +USART3_IRQn = 39, +
+  EXTI15_10_IRQn = 40, +RTC_Alarm_IRQn = 41, +OTG_FS_WKUP_IRQn = 42, +TIM8_BRK_TIM12_IRQn = 43, +
+  TIM8_UP_TIM13_IRQn = 44, +TIM8_TRG_COM_TIM14_IRQn = 45, +TIM8_CC_IRQn = 46, +DMA1_Stream7_IRQn = 47, +
+  FSMC_IRQn = 48, +SDIO_IRQn = 49, +TIM5_IRQn = 50, +SPI3_IRQn = 51, +
+  UART4_IRQn = 52, +UART5_IRQn = 53, +TIM6_DAC_IRQn = 54, +TIM7_IRQn = 55, +
+  DMA2_Stream0_IRQn = 56, +DMA2_Stream1_IRQn = 57, +DMA2_Stream2_IRQn = 58, +DMA2_Stream3_IRQn = 59, +
+  DMA2_Stream4_IRQn = 60, +ETH_IRQn = 61, +ETH_WKUP_IRQn = 62, +CAN2_TX_IRQn = 63, +
+  CAN2_RX0_IRQn = 64, +CAN2_RX1_IRQn = 65, +CAN2_SCE_IRQn = 66, +OTG_FS_IRQn = 67, +
+  DMA2_Stream5_IRQn = 68, +DMA2_Stream6_IRQn = 69, +DMA2_Stream7_IRQn = 70, +USART6_IRQn = 71, +
+  I2C3_EV_IRQn = 72, +I2C3_ER_IRQn = 73, +OTG_HS_EP1_OUT_IRQn = 74, +OTG_HS_EP1_IN_IRQn = 75, +
+  OTG_HS_WKUP_IRQn = 76, +OTG_HS_IRQn = 77, +DCMI_IRQn = 78, +CRYP_IRQn = 79, +
+  HASH_RNG_IRQn = 80, +FPU_IRQn = 81 +
+ }
 STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CM4_REV   0x0001
+
+ +

Configuration of the Cortex-M4 Processor and Core Peripherals.

+

Core revision r0p1

+ +
+
+ +
+
+ + + + +
#define __FPU_PRESENT   1
+
+

FPU present

+ +
+
+ +
+
+ + + + +
#define __MPU_PRESENT   1
+
+

STM32F4XX provides an MPU

+ +
+
+ +
+
+ + + + +
#define __NVIC_PRIO_BITS   4
+
+

STM32F4XX uses 4 Bits for the Priority Levels

+ +
+
+ +
+
+ + + + +
#define __Vendor_SysTickConfig   0
+
+

Set to 1 if different SysTick Config is used

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn
+
+ +

STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
NonMaskableInt_IRQn  +

2 Non Maskable Interrupt

+
MemoryManagement_IRQn  +

4 Cortex-M4 Memory Management Interrupt

+
BusFault_IRQn  +

5 Cortex-M4 Bus Fault Interrupt

+
UsageFault_IRQn  +

6 Cortex-M4 Usage Fault Interrupt

+
SVCall_IRQn  +

11 Cortex-M4 SV Call Interrupt

+
DebugMonitor_IRQn  +

12 Cortex-M4 Debug Monitor Interrupt

+
PendSV_IRQn  +

14 Cortex-M4 Pend SV Interrupt

+
SysTick_IRQn  +

15 Cortex-M4 System Tick Interrupt

+
WWDG_IRQn  +

Window WatchDog Interrupt

+
PVD_IRQn  +

PVD through EXTI Line detection Interrupt

+
TAMP_STAMP_IRQn  +

Tamper and TimeStamp interrupts through the EXTI line

+
RTC_WKUP_IRQn  +

RTC Wakeup interrupt through the EXTI line

+
FLASH_IRQn  +

FLASH global Interrupt

+
RCC_IRQn  +

RCC global Interrupt

+
EXTI0_IRQn  +

EXTI Line0 Interrupt

+
EXTI1_IRQn  +

EXTI Line1 Interrupt

+
EXTI2_IRQn  +

EXTI Line2 Interrupt

+
EXTI3_IRQn  +

EXTI Line3 Interrupt

+
EXTI4_IRQn  +

EXTI Line4 Interrupt

+
DMA1_Stream0_IRQn  +

DMA1 Stream 0 global Interrupt

+
DMA1_Stream1_IRQn  +

DMA1 Stream 1 global Interrupt

+
DMA1_Stream2_IRQn  +

DMA1 Stream 2 global Interrupt

+
DMA1_Stream3_IRQn  +

DMA1 Stream 3 global Interrupt

+
DMA1_Stream4_IRQn  +

DMA1 Stream 4 global Interrupt

+
DMA1_Stream5_IRQn  +

DMA1 Stream 5 global Interrupt

+
DMA1_Stream6_IRQn  +

DMA1 Stream 6 global Interrupt

+
ADC_IRQn  +

ADC1, ADC2 and ADC3 global Interrupts

+
CAN1_TX_IRQn  +

CAN1 TX Interrupt

+
CAN1_RX0_IRQn  +

CAN1 RX0 Interrupt

+
CAN1_RX1_IRQn  +

CAN1 RX1 Interrupt

+
CAN1_SCE_IRQn  +

CAN1 SCE Interrupt

+
EXTI9_5_IRQn  +

External Line[9:5] Interrupts

+
TIM1_BRK_TIM9_IRQn  +

TIM1 Break interrupt and TIM9 global interrupt

+
TIM1_UP_TIM10_IRQn  +

TIM1 Update Interrupt and TIM10 global interrupt

+
TIM1_TRG_COM_TIM11_IRQn  +

TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt

+
TIM1_CC_IRQn  +

TIM1 Capture Compare Interrupt

+
TIM2_IRQn  +

TIM2 global Interrupt

+
TIM3_IRQn  +

TIM3 global Interrupt

+
TIM4_IRQn  +

TIM4 global Interrupt

+
I2C1_EV_IRQn  +

I2C1 Event Interrupt

+
I2C1_ER_IRQn  +

I2C1 Error Interrupt

+
I2C2_EV_IRQn  +

I2C2 Event Interrupt

+
I2C2_ER_IRQn  +

I2C2 Error Interrupt

+
SPI1_IRQn  +

SPI1 global Interrupt

+
SPI2_IRQn  +

SPI2 global Interrupt

+
USART1_IRQn  +

USART1 global Interrupt

+
USART2_IRQn  +

USART2 global Interrupt

+
USART3_IRQn  +

USART3 global Interrupt

+
EXTI15_10_IRQn  +

External Line[15:10] Interrupts

+
RTC_Alarm_IRQn  +

RTC Alarm (A and B) through EXTI Line Interrupt

+
OTG_FS_WKUP_IRQn  +

USB OTG FS Wakeup through EXTI line interrupt

+
TIM8_BRK_TIM12_IRQn  +

TIM8 Break Interrupt and TIM12 global interrupt

+
TIM8_UP_TIM13_IRQn  +

TIM8 Update Interrupt and TIM13 global interrupt

+
TIM8_TRG_COM_TIM14_IRQn  +

TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt

+
TIM8_CC_IRQn  +

TIM8 Capture Compare Interrupt

+
DMA1_Stream7_IRQn  +

DMA1 Stream7 Interrupt

+
FSMC_IRQn  +

FSMC global Interrupt

+
SDIO_IRQn  +

SDIO global Interrupt

+
TIM5_IRQn  +

TIM5 global Interrupt

+
SPI3_IRQn  +

SPI3 global Interrupt

+
UART4_IRQn  +

UART4 global Interrupt

+
UART5_IRQn  +

UART5 global Interrupt

+
TIM6_DAC_IRQn  +

TIM6 global and DAC1&2 underrun error interrupts

+
TIM7_IRQn  +

TIM7 global interrupt

+
DMA2_Stream0_IRQn  +

DMA2 Stream 0 global Interrupt

+
DMA2_Stream1_IRQn  +

DMA2 Stream 1 global Interrupt

+
DMA2_Stream2_IRQn  +

DMA2 Stream 2 global Interrupt

+
DMA2_Stream3_IRQn  +

DMA2 Stream 3 global Interrupt

+
DMA2_Stream4_IRQn  +

DMA2 Stream 4 global Interrupt

+
ETH_IRQn  +

Ethernet global Interrupt

+
ETH_WKUP_IRQn  +

Ethernet Wakeup through EXTI line Interrupt

+
CAN2_TX_IRQn  +

CAN2 TX Interrupt

+
CAN2_RX0_IRQn  +

CAN2 RX0 Interrupt

+
CAN2_RX1_IRQn  +

CAN2 RX1 Interrupt

+
CAN2_SCE_IRQn  +

CAN2 SCE Interrupt

+
OTG_FS_IRQn  +

USB OTG FS global Interrupt

+
DMA2_Stream5_IRQn  +

DMA2 Stream 5 global interrupt

+
DMA2_Stream6_IRQn  +

DMA2 Stream 6 global interrupt

+
DMA2_Stream7_IRQn  +

DMA2 Stream 7 global interrupt

+
USART6_IRQn  +

USART6 global interrupt

+
I2C3_EV_IRQn  +

I2C3 event interrupt

+
I2C3_ER_IRQn  +

I2C3 error interrupt

+
OTG_HS_EP1_OUT_IRQn  +

USB OTG HS End Point 1 Out global interrupt

+
OTG_HS_EP1_IN_IRQn  +

USB OTG HS End Point 1 In global interrupt

+
OTG_HS_WKUP_IRQn  +

USB OTG HS Wakeup through EXTI interrupt

+
OTG_HS_IRQn  +

USB OTG HS global interrupt

+
DCMI_IRQn  +

DCMI global interrupt

+
CRYP_IRQn  +

CRYP crypto global interrupt

+
HASH_RNG_IRQn  +

Hash and Rng global interrupt

+
FPU_IRQn  +

FPU global interrupt

+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___configuration__section__for___c_m_s_i_s.map b/group___configuration__section__for___c_m_s_i_s.map new file mode 100644 index 0000000..ef68811 --- /dev/null +++ b/group___configuration__section__for___c_m_s_i_s.map @@ -0,0 +1,3 @@ + + + diff --git a/group___configuration__section__for___c_m_s_i_s.md5 b/group___configuration__section__for___c_m_s_i_s.md5 new file mode 100644 index 0000000..8bc6fd4 --- /dev/null +++ b/group___configuration__section__for___c_m_s_i_s.md5 @@ -0,0 +1 @@ +45628593d75f673adeb3569559e0e60e \ No newline at end of file diff --git a/group___configuration__section__for___c_m_s_i_s.png b/group___configuration__section__for___c_m_s_i_s.png new file mode 100644 index 0000000..df66e45 Binary files /dev/null and b/group___configuration__section__for___c_m_s_i_s.png differ diff --git a/group___d_a_c.html b/group___d_a_c.html new file mode 100644 index 0000000..015ac8b --- /dev/null +++ b/group___d_a_c.html @@ -0,0 +1,979 @@ + + + + + + +discoverpixy: DAC + + + + + + + + + + +
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discoverpixy +
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+Modules | +Classes | +Macros | +Functions
+
+
DAC
STM32F4xx_StdPeriph_Driver
+
+
+ +

DAC driver modules. +More...

+
+Collaboration diagram for DAC:
+
+
+ + +
+
+ + + + + + +

+Modules

 DAC_Exported_Constants
 
 DAC_Private_Functions
 
+ + + + +

+Classes

struct  DAC_InitTypeDef
 DAC Init structure definition. More...
 
+ + + + + + + + + + + + + + + +

+Macros

+#define CR_CLEAR_MASK   ((uint32_t)0x00000FFE)
 
+#define DUAL_SWTRIG_SET   ((uint32_t)0x00000003)
 
+#define DUAL_SWTRIG_RESET   ((uint32_t)0xFFFFFFFC)
 
+#define DHR12R1_OFFSET   ((uint32_t)0x00000008)
 
+#define DHR12R2_OFFSET   ((uint32_t)0x00000014)
 
+#define DHR12RD_OFFSET   ((uint32_t)0x00000020)
 
+#define DOR_OFFSET   ((uint32_t)0x0000002C)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DAC_DeInit (void)
 Deinitializes the DAC peripheral registers to their default reset values. More...
 
void DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
 Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. More...
 
void DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
 Fills each DAC_InitStruct member with its default value. More...
 
void DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel. More...
 
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the selected DAC channel software trigger. More...
 
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
 Enables or disables simultaneously the two DAC channels software triggers. More...
 
void DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
 Enables or disables the selected DAC channel wave generation. More...
 
void DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel1. More...
 
void DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel2. More...
 
void DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
 Set the specified data holding register value for dual channel DAC. More...
 
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
 Returns the last data output value of the selected DAC channel. More...
 
void DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel DMA request. More...
 
void DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
 Enables or disables the specified DAC interrupts. More...
 
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Checks whether the specified DAC flag is set or not. More...
 
void DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Clears the DAC channel's pending flags. More...
 
ITStatus DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
 Checks whether the specified DAC interrupt has occurred or not. More...
 
void DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
 Clears the DAC channel's interrupt pending bits. More...
 
+

Detailed Description

+

DAC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_ClearFlag (uint32_t DAC_Channel,
uint32_t DAC_FLAG 
)
+
+ +

Clears the DAC channel's pending flags.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_FLAGspecifies the flag to clear. This parameter can be of the following value:
    +
  • DAC_FLAG_DMAUDR: DMA underrun flag
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_ClearITPendingBit (uint32_t DAC_Channel,
uint32_t DAC_IT 
)
+
+ +

Clears the DAC channel's interrupt pending bits.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt pending bit to clear. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_Cmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC channel.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the DAC channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the DAC channel is enabled the trigger source can no more be modified.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DAC_DeInit (void )
+
+ +

Deinitializes the DAC peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
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+ +
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void DAC_DMACmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC channel DMA request.

+
Note
When enabled DMA1 is generated when an external trigger (EXTI Line9, TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be already configured.
+
+The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be already configured.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
+
+ +

Enables or disables simultaneously the two DAC channels software triggers.

+
Parameters
+ + +
NewStatenew state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
+
+ +

Returns the last data output value of the selected DAC channel.

+
Parameters
+ + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
+
+
+
Return values
+ + +
Theselected DAC channel data output value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel,
uint32_t DAC_FLAG 
)
+
+ +

Checks whether the specified DAC flag is set or not.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_FLAGspecifies the flag to check. This parameter can be only of the following value:
    +
  • DAC_FLAG_DMAUDR: DMA underrun flag
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
Thenew state of DAC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus DAC_GetITStatus (uint32_t DAC_Channel,
uint32_t DAC_IT 
)
+
+ +

Checks whether the specified DAC interrupt has occurred or not.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt source to check. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
Thenew state of DAC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_Init (uint32_t DAC_Channel,
DAC_InitTypeDef * DAC_InitStruct 
)
+
+ +

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

+
Parameters
+ + + +
DAC_Channelthe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_InitStructpointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_ITConfig (uint32_t DAC_Channel,
uint32_t DAC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC interrupts.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt sources to be enabled or disabled. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Parameters
+ + +
NewStatenew state of the specified DAC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SetChannel1Data (uint32_t DAC_Align,
uint16_t Data 
)
+
+ +

Set the specified data holding register value for DAC channel1.

+
Parameters
+ + + +
DAC_AlignSpecifies the data alignment for DAC channel1. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
DataData to be loaded in the selected data holding register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SetChannel2Data (uint32_t DAC_Align,
uint16_t Data 
)
+
+ +

Set the specified data holding register value for DAC channel2.

+
Parameters
+ + + +
DAC_AlignSpecifies the data alignment for DAC channel2. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
DataData to be loaded in the selected data holding register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_SetDualChannelData (uint32_t DAC_Align,
uint16_t Data2,
uint16_t Data1 
)
+
+ +

Set the specified data holding register value for dual channel DAC.

+
Parameters
+ + + + +
DAC_AlignSpecifies the data alignment for dual channel DAC. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
Data2Data for DAC Channel2 to be loaded in the selected data holding register.
Data1Data for DAC Channel1 to be loaded in the selected data holding register.
+
+
+
Note
In dual mode, a unique register access is required to write in both DAC channels at the same time.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected DAC channel software trigger.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DAC_StructInit (DAC_InitTypeDef * DAC_InitStruct)
+
+ +

Fills each DAC_InitStruct member with its default value.

+
Parameters
+ + +
DAC_InitStructpointer to a DAC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_WaveGenerationCmd (uint32_t DAC_Channel,
uint32_t DAC_Wave,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected DAC channel wave generation.

+
Parameters
+ + + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_Wavespecifies the wave type to enable or disable. This parameter can be one of the following values:
    +
  • DAC_Wave_Noise: noise wave generation
    • +
  • DAC_Wave_Triangle: triangle wave generation
    • +
+
NewStatenew state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c.map b/group___d_a_c.map new file mode 100644 index 0000000..cf0f071 --- /dev/null +++ b/group___d_a_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_a_c.md5 b/group___d_a_c.md5 new file mode 100644 index 0000000..363a7d0 --- /dev/null +++ b/group___d_a_c.md5 @@ -0,0 +1 @@ +918183be913b7d32199f5f7e118968b4 \ No newline at end of file diff --git a/group___d_a_c.png b/group___d_a_c.png new file mode 100644 index 0000000..85f09a1 Binary files /dev/null and b/group___d_a_c.png differ diff --git a/group___d_a_c___channel__selection.html b/group___d_a_c___channel__selection.html new file mode 100644 index 0000000..fda63c0 --- /dev/null +++ b/group___d_a_c___channel__selection.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DAC_Channel_selection + + + + + + + + + + +
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+Macros
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+
DAC_Channel_selection
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_Channel_selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DAC_Channel_1   ((uint32_t)0x00000000)
 
+#define DAC_Channel_2   ((uint32_t)0x00000010)
 
#define IS_DAC_CHANNEL(CHANNEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DAC_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == DAC_Channel_1) || \
+
((CHANNEL) == DAC_Channel_2))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___channel__selection.map b/group___d_a_c___channel__selection.map new file mode 100644 index 0000000..82c3285 --- /dev/null +++ b/group___d_a_c___channel__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c___channel__selection.md5 b/group___d_a_c___channel__selection.md5 new file mode 100644 index 0000000..18bffdd --- /dev/null +++ b/group___d_a_c___channel__selection.md5 @@ -0,0 +1 @@ +15fd805aa87030c4fd881dae6361b1fd \ No newline at end of file diff --git a/group___d_a_c___channel__selection.png b/group___d_a_c___channel__selection.png new file mode 100644 index 0000000..a9bd013 Binary files /dev/null and b/group___d_a_c___channel__selection.png differ diff --git a/group___d_a_c___exported___constants.html b/group___d_a_c___exported___constants.html new file mode 100644 index 0000000..731e84a --- /dev/null +++ b/group___d_a_c___exported___constants.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: DAC_Exported_Constants + + + + + + + + + + +
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discoverpixy +
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+Modules
+
+
DAC_Exported_Constants
STM32F4xx_StdPeriph_Driver » DAC
+
+
+
+Collaboration diagram for DAC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Modules

 DAC_trigger_selection
 
 DAC_wave_generation
 
 DAC_lfsrunmask_triangleamplitude
 
 DAC_output_buffer
 
 DAC_Channel_selection
 
 DAC_data_alignement
 
 DAC_data
 
 DAC_interrupts_definition
 
 DAC_flags_definition
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___exported___constants.map b/group___d_a_c___exported___constants.map new file mode 100644 index 0000000..235c9f4 --- /dev/null +++ b/group___d_a_c___exported___constants.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___d_a_c___exported___constants.md5 b/group___d_a_c___exported___constants.md5 new file mode 100644 index 0000000..0784049 --- /dev/null +++ b/group___d_a_c___exported___constants.md5 @@ -0,0 +1 @@ +bd301b0865e2bfc50fbb039d636d0ccd \ No newline at end of file diff --git a/group___d_a_c___exported___constants.png b/group___d_a_c___exported___constants.png new file mode 100644 index 0000000..f732527 Binary files /dev/null and b/group___d_a_c___exported___constants.png differ diff --git a/group___d_a_c___group1.html b/group___d_a_c___group1.html new file mode 100644 index 0000000..b4f10bf --- /dev/null +++ b/group___d_a_c___group1.html @@ -0,0 +1,617 @@ + + + + + + +discoverpixy: DAC channels configuration + + + + + + + + + + +
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discoverpixy +
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+ +
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+ + +
+ +
+ +
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+Functions
+
+
DAC channels configuration
STM32F4xx_StdPeriph_Driver » DAC » DAC_Private_Functions
+
+
+ +

DAC channels configuration: trigger, output buffer, data format. +More...

+
+Collaboration diagram for DAC channels configuration:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DAC_DeInit (void)
 Deinitializes the DAC peripheral registers to their default reset values. More...
 
void DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
 Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. More...
 
void DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
 Fills each DAC_InitStruct member with its default value. More...
 
void DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel. More...
 
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the selected DAC channel software trigger. More...
 
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
 Enables or disables simultaneously the two DAC channels software triggers. More...
 
void DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
 Enables or disables the selected DAC channel wave generation. More...
 
void DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel1. More...
 
void DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel2. More...
 
void DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
 Set the specified data holding register value for dual channel DAC. More...
 
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
 Returns the last data output value of the selected DAC channel. More...
 
+

Detailed Description

+

DAC channels configuration: trigger, output buffer, data format.

+
 ===============================================================================
+   ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_Cmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC channel.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the DAC channel. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the DAC channel is enabled the trigger source can no more be modified.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DAC_DeInit (void )
+
+ +

Deinitializes the DAC peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
+
+ +

Enables or disables simultaneously the two DAC channels software triggers.

+
Parameters
+ + +
NewStatenew state of the DAC channels software triggers. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
+
+ +

Returns the last data output value of the selected DAC channel.

+
Parameters
+ + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
+
+
+
Return values
+ + +
Theselected DAC channel data output value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_Init (uint32_t DAC_Channel,
DAC_InitTypeDef * DAC_InitStruct 
)
+
+ +

Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.

+
Parameters
+ + + +
DAC_Channelthe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_InitStructpointer to a DAC_InitTypeDef structure that contains the configuration information for the specified DAC channel.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SetChannel1Data (uint32_t DAC_Align,
uint16_t Data 
)
+
+ +

Set the specified data holding register value for DAC channel1.

+
Parameters
+ + + +
DAC_AlignSpecifies the data alignment for DAC channel1. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
DataData to be loaded in the selected data holding register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SetChannel2Data (uint32_t DAC_Align,
uint16_t Data 
)
+
+ +

Set the specified data holding register value for DAC channel2.

+
Parameters
+ + + +
DAC_AlignSpecifies the data alignment for DAC channel2. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
DataData to be loaded in the selected data holding register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_SetDualChannelData (uint32_t DAC_Align,
uint16_t Data2,
uint16_t Data1 
)
+
+ +

Set the specified data holding register value for dual channel DAC.

+
Parameters
+ + + + +
DAC_AlignSpecifies the data alignment for dual channel DAC. This parameter can be one of the following values:
    +
  • DAC_Align_8b_R: 8bit right data alignment selected
    • +
  • DAC_Align_12b_L: 12bit left data alignment selected
    • +
  • DAC_Align_12b_R: 12bit right data alignment selected
    • +
+
Data2Data for DAC Channel2 to be loaded in the selected data holding register.
Data1Data for DAC Channel1 to be loaded in the selected data holding register.
+
+
+
Note
In dual mode, a unique register access is required to write in both DAC channels at the same time.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected DAC channel software trigger.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the selected DAC channel software trigger. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DAC_StructInit (DAC_InitTypeDef * DAC_InitStruct)
+
+ +

Fills each DAC_InitStruct member with its default value.

+
Parameters
+ + +
DAC_InitStructpointer to a DAC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_WaveGenerationCmd (uint32_t DAC_Channel,
uint32_t DAC_Wave,
FunctionalState NewState 
)
+
+ +

Enables or disables the selected DAC channel wave generation.

+
Parameters
+ + + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_Wavespecifies the wave type to enable or disable. This parameter can be one of the following values:
    +
  • DAC_Wave_Noise: noise wave generation
    • +
  • DAC_Wave_Triangle: triangle wave generation
    • +
+
NewStatenew state of the selected DAC channel wave generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___group1.map b/group___d_a_c___group1.map new file mode 100644 index 0000000..0f31a0e --- /dev/null +++ b/group___d_a_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c___group1.md5 b/group___d_a_c___group1.md5 new file mode 100644 index 0000000..0f0cb5d --- /dev/null +++ b/group___d_a_c___group1.md5 @@ -0,0 +1 @@ +2472b87f069d19937da3d89556eddd6c \ No newline at end of file diff --git a/group___d_a_c___group1.png b/group___d_a_c___group1.png new file mode 100644 index 0000000..470b474 Binary files /dev/null and b/group___d_a_c___group1.png differ diff --git a/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map new file mode 100644 index 0000000..e849f0f --- /dev/null +++ b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 new file mode 100644 index 0000000..931bfa0 --- /dev/null +++ b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 @@ -0,0 +1 @@ +04ec67b258886c02ac84d96a741e392e \ No newline at end of file diff --git a/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png new file mode 100644 index 0000000..40e12d1 Binary files /dev/null and b/group___d_a_c___group1_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png differ diff --git a/group___d_a_c___group2.html b/group___d_a_c___group2.html new file mode 100644 index 0000000..ac64531 --- /dev/null +++ b/group___d_a_c___group2.html @@ -0,0 +1,165 @@ + + + + + + +discoverpixy: DMA management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DMA management functions
STM32F4xx_StdPeriph_Driver » DAC » DAC_Private_Functions
+
+
+ +

DMA management functions. +More...

+
+Collaboration diagram for DMA management functions:
+
+
+ + +
+
+ + + + + +

+Functions

void DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel DMA request. More...
 
+

Detailed Description

+

DMA management functions.

+
 ===============================================================================
+                       ##### DMA management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_DMACmd (uint32_t DAC_Channel,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC channel DMA request.

+
Note
When enabled DMA1 is generated when an external trigger (EXTI Line9, TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs.
+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
NewStatenew state of the selected DAC channel DMA request. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be already configured.
+
+The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be already configured.
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___group2.map b/group___d_a_c___group2.map new file mode 100644 index 0000000..84d5782 --- /dev/null +++ b/group___d_a_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c___group2.md5 b/group___d_a_c___group2.md5 new file mode 100644 index 0000000..ad06b77 --- /dev/null +++ b/group___d_a_c___group2.md5 @@ -0,0 +1 @@ +1795531841e30fe6ce19f81c9a55ad76 \ No newline at end of file diff --git a/group___d_a_c___group2.png b/group___d_a_c___group2.png new file mode 100644 index 0000000..81557a8 Binary files /dev/null and b/group___d_a_c___group2.png differ diff --git a/group___d_a_c___group3.html b/group___d_a_c___group3.html new file mode 100644 index 0000000..6d42dd6 --- /dev/null +++ b/group___d_a_c___group3.html @@ -0,0 +1,385 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » DAC » DAC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
 Enables or disables the specified DAC interrupts. More...
 
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Checks whether the specified DAC flag is set or not. More...
 
void DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Clears the DAC channel's pending flags. More...
 
ITStatus DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
 Checks whether the specified DAC interrupt has occurred or not. More...
 
void DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
 Clears the DAC channel's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_ClearFlag (uint32_t DAC_Channel,
uint32_t DAC_FLAG 
)
+
+ +

Clears the DAC channel's pending flags.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_FLAGspecifies the flag to clear. This parameter can be of the following value:
    +
  • DAC_FLAG_DMAUDR: DMA underrun flag
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DAC_ClearITPendingBit (uint32_t DAC_Channel,
uint32_t DAC_IT 
)
+
+ +

Clears the DAC channel's interrupt pending bits.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt pending bit to clear. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel,
uint32_t DAC_FLAG 
)
+
+ +

Checks whether the specified DAC flag is set or not.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_FLAGspecifies the flag to check. This parameter can be only of the following value:
    +
  • DAC_FLAG_DMAUDR: DMA underrun flag
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
Thenew state of DAC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus DAC_GetITStatus (uint32_t DAC_Channel,
uint32_t DAC_IT 
)
+
+ +

Checks whether the specified DAC interrupt has occurred or not.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt source to check. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Return values
+ + +
Thenew state of DAC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DAC_ITConfig (uint32_t DAC_Channel,
uint32_t DAC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DAC interrupts.

+
Parameters
+ + + +
DAC_ChannelThe selected DAC channel. This parameter can be one of the following values:
    +
  • DAC_Channel_1: DAC Channel1 selected
    • +
  • DAC_Channel_2: DAC Channel2 selected
    • +
+
DAC_ITspecifies the DAC interrupt sources to be enabled or disabled. This parameter can be the following values:
    +
  • DAC_IT_DMAUDR: DMA underrun interrupt mask
    • +
+
+
+
+
Note
The DMA underrun occurs when a second external trigger arrives before the acknowledgement for the first external trigger is received (first request).
+
Parameters
+ + +
NewStatenew state of the specified DAC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___group3.map b/group___d_a_c___group3.map new file mode 100644 index 0000000..5a95312 --- /dev/null +++ b/group___d_a_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c___group3.md5 b/group___d_a_c___group3.md5 new file mode 100644 index 0000000..9dfe7fe --- /dev/null +++ b/group___d_a_c___group3.md5 @@ -0,0 +1 @@ +cc0ba37eb13dfc3e8fb181f4cabcf55d \ No newline at end of file diff --git a/group___d_a_c___group3.png b/group___d_a_c___group3.png new file mode 100644 index 0000000..c5f4574 Binary files /dev/null and b/group___d_a_c___group3.png differ diff --git a/group___d_a_c___private___functions.html b/group___d_a_c___private___functions.html new file mode 100644 index 0000000..3436b3c --- /dev/null +++ b/group___d_a_c___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: DAC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DAC_Private_Functions
STM32F4xx_StdPeriph_Driver » DAC
+
+
+
+Collaboration diagram for DAC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 DAC channels configuration
 DAC channels configuration: trigger, output buffer, data format.
 
 DMA management functions
 DMA management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c___private___functions.map b/group___d_a_c___private___functions.map new file mode 100644 index 0000000..80ab69f --- /dev/null +++ b/group___d_a_c___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___d_a_c___private___functions.md5 b/group___d_a_c___private___functions.md5 new file mode 100644 index 0000000..44b57f0 --- /dev/null +++ b/group___d_a_c___private___functions.md5 @@ -0,0 +1 @@ +8431ced0e1278a20bb43d7abfec3f3c3 \ No newline at end of file diff --git a/group___d_a_c___private___functions.png b/group___d_a_c___private___functions.png new file mode 100644 index 0000000..a0f8929 Binary files /dev/null and b/group___d_a_c___private___functions.png differ diff --git a/group___d_a_c__data.html b/group___d_a_c__data.html new file mode 100644 index 0000000..9acca91 --- /dev/null +++ b/group___d_a_c__data.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: DAC_data + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_data
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_data:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_DAC_DATA(DATA)   ((DATA) <= 0xFFF0)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__data.map b/group___d_a_c__data.map new file mode 100644 index 0000000..b5fe53a --- /dev/null +++ b/group___d_a_c__data.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__data.md5 b/group___d_a_c__data.md5 new file mode 100644 index 0000000..0b0db32 --- /dev/null +++ b/group___d_a_c__data.md5 @@ -0,0 +1 @@ +b57100d8a6d7e3e4c3c0b6190b5792ef \ No newline at end of file diff --git a/group___d_a_c__data.png b/group___d_a_c__data.png new file mode 100644 index 0000000..d89ed65 Binary files /dev/null and b/group___d_a_c__data.png differ diff --git a/group___d_a_c__data__alignement.html b/group___d_a_c__data__alignement.html new file mode 100644 index 0000000..b914f82 --- /dev/null +++ b/group___d_a_c__data__alignement.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: DAC_data_alignement + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_data_alignement
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_data_alignement:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DAC_Align_12b_R   ((uint32_t)0x00000000)
 
+#define DAC_Align_12b_L   ((uint32_t)0x00000004)
 
+#define DAC_Align_8b_R   ((uint32_t)0x00000008)
 
#define IS_DAC_ALIGN(ALIGN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DAC_ALIGN( ALIGN)
+
+Value:
(((ALIGN) == DAC_Align_12b_R) || \
+
((ALIGN) == DAC_Align_12b_L) || \
+
((ALIGN) == DAC_Align_8b_R))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__data__alignement.map b/group___d_a_c__data__alignement.map new file mode 100644 index 0000000..33cd8d6 --- /dev/null +++ b/group___d_a_c__data__alignement.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__data__alignement.md5 b/group___d_a_c__data__alignement.md5 new file mode 100644 index 0000000..56f42a4 --- /dev/null +++ b/group___d_a_c__data__alignement.md5 @@ -0,0 +1 @@ +2e0715d39ec976cb1d138feb08401b09 \ No newline at end of file diff --git a/group___d_a_c__data__alignement.png b/group___d_a_c__data__alignement.png new file mode 100644 index 0000000..671e7fa Binary files /dev/null and b/group___d_a_c__data__alignement.png differ diff --git a/group___d_a_c__flags__definition.html b/group___d_a_c__flags__definition.html new file mode 100644 index 0000000..c7ca424 --- /dev/null +++ b/group___d_a_c__flags__definition.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: DAC_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_flags_definition
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_flags_definition:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define DAC_FLAG_DMAUDR   ((uint32_t)0x00002000)
 
+#define IS_DAC_FLAG(FLAG)   (((FLAG) == DAC_FLAG_DMAUDR))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__flags__definition.map b/group___d_a_c__flags__definition.map new file mode 100644 index 0000000..a377d40 --- /dev/null +++ b/group___d_a_c__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__flags__definition.md5 b/group___d_a_c__flags__definition.md5 new file mode 100644 index 0000000..ad57940 --- /dev/null +++ b/group___d_a_c__flags__definition.md5 @@ -0,0 +1 @@ +45790572de60cfa4d43336d17664dccd \ No newline at end of file diff --git a/group___d_a_c__flags__definition.png b/group___d_a_c__flags__definition.png new file mode 100644 index 0000000..556bb86 Binary files /dev/null and b/group___d_a_c__flags__definition.png differ diff --git a/group___d_a_c__interrupts__definition.html b/group___d_a_c__interrupts__definition.html new file mode 100644 index 0000000..7123610 --- /dev/null +++ b/group___d_a_c__interrupts__definition.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: DAC_interrupts_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_interrupts_definition
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_interrupts_definition:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define DAC_IT_DMAUDR   ((uint32_t)0x00002000)
 
+#define IS_DAC_IT(IT)   (((IT) == DAC_IT_DMAUDR))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__interrupts__definition.map b/group___d_a_c__interrupts__definition.map new file mode 100644 index 0000000..e06e429 --- /dev/null +++ b/group___d_a_c__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__interrupts__definition.md5 b/group___d_a_c__interrupts__definition.md5 new file mode 100644 index 0000000..f5ba3f9 --- /dev/null +++ b/group___d_a_c__interrupts__definition.md5 @@ -0,0 +1 @@ +652a8ef08e0bd48a7aa4e67954167475 \ No newline at end of file diff --git a/group___d_a_c__interrupts__definition.png b/group___d_a_c__interrupts__definition.png new file mode 100644 index 0000000..c7513af Binary files /dev/null and b/group___d_a_c__interrupts__definition.png differ diff --git a/group___d_a_c__lfsrunmask__triangleamplitude.html b/group___d_a_c__lfsrunmask__triangleamplitude.html new file mode 100644 index 0000000..e742e10 --- /dev/null +++ b/group___d_a_c__lfsrunmask__triangleamplitude.html @@ -0,0 +1,533 @@ + + + + + + +discoverpixy: DAC_lfsrunmask_triangleamplitude + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_lfsrunmask_triangleamplitude
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_lfsrunmask_triangleamplitude:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DAC_LFSRUnmask_Bit0   ((uint32_t)0x00000000)
 
#define DAC_LFSRUnmask_Bits1_0   ((uint32_t)0x00000100)
 
#define DAC_LFSRUnmask_Bits2_0   ((uint32_t)0x00000200)
 
#define DAC_LFSRUnmask_Bits3_0   ((uint32_t)0x00000300)
 
#define DAC_LFSRUnmask_Bits4_0   ((uint32_t)0x00000400)
 
#define DAC_LFSRUnmask_Bits5_0   ((uint32_t)0x00000500)
 
#define DAC_LFSRUnmask_Bits6_0   ((uint32_t)0x00000600)
 
#define DAC_LFSRUnmask_Bits7_0   ((uint32_t)0x00000700)
 
#define DAC_LFSRUnmask_Bits8_0   ((uint32_t)0x00000800)
 
#define DAC_LFSRUnmask_Bits9_0   ((uint32_t)0x00000900)
 
#define DAC_LFSRUnmask_Bits10_0   ((uint32_t)0x00000A00)
 
#define DAC_LFSRUnmask_Bits11_0   ((uint32_t)0x00000B00)
 
#define DAC_TriangleAmplitude_1   ((uint32_t)0x00000000)
 
#define DAC_TriangleAmplitude_3   ((uint32_t)0x00000100)
 
#define DAC_TriangleAmplitude_7   ((uint32_t)0x00000200)
 
#define DAC_TriangleAmplitude_15   ((uint32_t)0x00000300)
 
#define DAC_TriangleAmplitude_31   ((uint32_t)0x00000400)
 
#define DAC_TriangleAmplitude_63   ((uint32_t)0x00000500)
 
#define DAC_TriangleAmplitude_127   ((uint32_t)0x00000600)
 
#define DAC_TriangleAmplitude_255   ((uint32_t)0x00000700)
 
#define DAC_TriangleAmplitude_511   ((uint32_t)0x00000800)
 
#define DAC_TriangleAmplitude_1023   ((uint32_t)0x00000900)
 
#define DAC_TriangleAmplitude_2047   ((uint32_t)0x00000A00)
 
#define DAC_TriangleAmplitude_4095   ((uint32_t)0x00000B00)
 
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bit0   ((uint32_t)0x00000000)
+
+

Unmask DAC channel LFSR bit0 for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits10_0   ((uint32_t)0x00000A00)
+
+

Unmask DAC channel LFSR bit[10:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits11_0   ((uint32_t)0x00000B00)
+
+

Unmask DAC channel LFSR bit[11:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits1_0   ((uint32_t)0x00000100)
+
+

Unmask DAC channel LFSR bit[1:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits2_0   ((uint32_t)0x00000200)
+
+

Unmask DAC channel LFSR bit[2:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits3_0   ((uint32_t)0x00000300)
+
+

Unmask DAC channel LFSR bit[3:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits4_0   ((uint32_t)0x00000400)
+
+

Unmask DAC channel LFSR bit[4:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits5_0   ((uint32_t)0x00000500)
+
+

Unmask DAC channel LFSR bit[5:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits6_0   ((uint32_t)0x00000600)
+
+

Unmask DAC channel LFSR bit[6:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits7_0   ((uint32_t)0x00000700)
+
+

Unmask DAC channel LFSR bit[7:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits8_0   ((uint32_t)0x00000800)
+
+

Unmask DAC channel LFSR bit[8:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_LFSRUnmask_Bits9_0   ((uint32_t)0x00000900)
+
+

Unmask DAC channel LFSR bit[9:0] for noise wave generation

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_1   ((uint32_t)0x00000000)
+
+

Select max triangle amplitude of 1

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_1023   ((uint32_t)0x00000900)
+
+

Select max triangle amplitude of 1023

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_127   ((uint32_t)0x00000600)
+
+

Select max triangle amplitude of 127

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_15   ((uint32_t)0x00000300)
+
+

Select max triangle amplitude of 15

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_2047   ((uint32_t)0x00000A00)
+
+

Select max triangle amplitude of 2047

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_255   ((uint32_t)0x00000700)
+
+

Select max triangle amplitude of 255

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_3   ((uint32_t)0x00000100)
+
+

Select max triangle amplitude of 3

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_31   ((uint32_t)0x00000400)
+
+

Select max triangle amplitude of 31

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_4095   ((uint32_t)0x00000B00)
+
+

Select max triangle amplitude of 4095

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_511   ((uint32_t)0x00000800)
+
+

Select max triangle amplitude of 511

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_63   ((uint32_t)0x00000500)
+
+

Select max triangle amplitude of 63

+ +
+
+ +
+
+ + + + +
#define DAC_TriangleAmplitude_7   ((uint32_t)0x00000200)
+
+

Select max triangle amplitude of 7

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE( VALUE)
+
+Value:
(((VALUE) == DAC_LFSRUnmask_Bit0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+
((VALUE) == DAC_TriangleAmplitude_1) || \
+
((VALUE) == DAC_TriangleAmplitude_3) || \
+
((VALUE) == DAC_TriangleAmplitude_7) || \
+
((VALUE) == DAC_TriangleAmplitude_15) || \
+
((VALUE) == DAC_TriangleAmplitude_31) || \
+
((VALUE) == DAC_TriangleAmplitude_63) || \
+
((VALUE) == DAC_TriangleAmplitude_127) || \
+
((VALUE) == DAC_TriangleAmplitude_255) || \
+
((VALUE) == DAC_TriangleAmplitude_511) || \
+
((VALUE) == DAC_TriangleAmplitude_1023) || \
+
((VALUE) == DAC_TriangleAmplitude_2047) || \
+
((VALUE) == DAC_TriangleAmplitude_4095))
+
DAC_LFSRUnmask_Bits10_0
#define DAC_LFSRUnmask_Bits10_0
Definition: stm32f4xx_dac.h:136
+
DAC_LFSRUnmask_Bits2_0
#define DAC_LFSRUnmask_Bits2_0
Definition: stm32f4xx_dac.h:128
+
DAC_LFSRUnmask_Bits6_0
#define DAC_LFSRUnmask_Bits6_0
Definition: stm32f4xx_dac.h:132
+
DAC_LFSRUnmask_Bits4_0
#define DAC_LFSRUnmask_Bits4_0
Definition: stm32f4xx_dac.h:130
+
DAC_LFSRUnmask_Bits8_0
#define DAC_LFSRUnmask_Bits8_0
Definition: stm32f4xx_dac.h:134
+
DAC_TriangleAmplitude_1
#define DAC_TriangleAmplitude_1
Definition: stm32f4xx_dac.h:138
+
DAC_LFSRUnmask_Bit0
#define DAC_LFSRUnmask_Bit0
Definition: stm32f4xx_dac.h:126
+
DAC_LFSRUnmask_Bits1_0
#define DAC_LFSRUnmask_Bits1_0
Definition: stm32f4xx_dac.h:127
+
DAC_TriangleAmplitude_255
#define DAC_TriangleAmplitude_255
Definition: stm32f4xx_dac.h:145
+
DAC_LFSRUnmask_Bits5_0
#define DAC_LFSRUnmask_Bits5_0
Definition: stm32f4xx_dac.h:131
+
DAC_TriangleAmplitude_7
#define DAC_TriangleAmplitude_7
Definition: stm32f4xx_dac.h:140
+
DAC_LFSRUnmask_Bits9_0
#define DAC_LFSRUnmask_Bits9_0
Definition: stm32f4xx_dac.h:135
+
DAC_LFSRUnmask_Bits7_0
#define DAC_LFSRUnmask_Bits7_0
Definition: stm32f4xx_dac.h:133
+
DAC_TriangleAmplitude_3
#define DAC_TriangleAmplitude_3
Definition: stm32f4xx_dac.h:139
+
DAC_LFSRUnmask_Bits3_0
#define DAC_LFSRUnmask_Bits3_0
Definition: stm32f4xx_dac.h:129
+
DAC_TriangleAmplitude_31
#define DAC_TriangleAmplitude_31
Definition: stm32f4xx_dac.h:142
+
DAC_TriangleAmplitude_2047
#define DAC_TriangleAmplitude_2047
Definition: stm32f4xx_dac.h:148
+
DAC_TriangleAmplitude_1023
#define DAC_TriangleAmplitude_1023
Definition: stm32f4xx_dac.h:147
+
DAC_TriangleAmplitude_4095
#define DAC_TriangleAmplitude_4095
Definition: stm32f4xx_dac.h:149
+
DAC_TriangleAmplitude_127
#define DAC_TriangleAmplitude_127
Definition: stm32f4xx_dac.h:144
+
DAC_TriangleAmplitude_15
#define DAC_TriangleAmplitude_15
Definition: stm32f4xx_dac.h:141
+
DAC_TriangleAmplitude_511
#define DAC_TriangleAmplitude_511
Definition: stm32f4xx_dac.h:146
+
DAC_TriangleAmplitude_63
#define DAC_TriangleAmplitude_63
Definition: stm32f4xx_dac.h:143
+
DAC_LFSRUnmask_Bits11_0
#define DAC_LFSRUnmask_Bits11_0
Definition: stm32f4xx_dac.h:137
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__lfsrunmask__triangleamplitude.map b/group___d_a_c__lfsrunmask__triangleamplitude.map new file mode 100644 index 0000000..4a60d5d --- /dev/null +++ b/group___d_a_c__lfsrunmask__triangleamplitude.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__lfsrunmask__triangleamplitude.md5 b/group___d_a_c__lfsrunmask__triangleamplitude.md5 new file mode 100644 index 0000000..3b4a607 --- /dev/null +++ b/group___d_a_c__lfsrunmask__triangleamplitude.md5 @@ -0,0 +1 @@ +9e5a50585c8b2461b50d713769698459 \ No newline at end of file diff --git a/group___d_a_c__lfsrunmask__triangleamplitude.png b/group___d_a_c__lfsrunmask__triangleamplitude.png new file mode 100644 index 0000000..6527a6f Binary files /dev/null and b/group___d_a_c__lfsrunmask__triangleamplitude.png differ diff --git a/group___d_a_c__output__buffer.html b/group___d_a_c__output__buffer.html new file mode 100644 index 0000000..3a18023 --- /dev/null +++ b/group___d_a_c__output__buffer.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DAC_output_buffer + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
DAC_output_buffer
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_output_buffer:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DAC_OutputBuffer_Enable   ((uint32_t)0x00000000)
 
+#define DAC_OutputBuffer_Disable   ((uint32_t)0x00000002)
 
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DAC_OUTPUT_BUFFER_STATE( STATE)
+
+Value:
(((STATE) == DAC_OutputBuffer_Enable) || \
+
((STATE) == DAC_OutputBuffer_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__output__buffer.map b/group___d_a_c__output__buffer.map new file mode 100644 index 0000000..4a13df4 --- /dev/null +++ b/group___d_a_c__output__buffer.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__output__buffer.md5 b/group___d_a_c__output__buffer.md5 new file mode 100644 index 0000000..04c95a1 --- /dev/null +++ b/group___d_a_c__output__buffer.md5 @@ -0,0 +1 @@ +8513603de4e304836001d2b3d000efe9 \ No newline at end of file diff --git a/group___d_a_c__output__buffer.png b/group___d_a_c__output__buffer.png new file mode 100644 index 0000000..3e2b935 Binary files /dev/null and b/group___d_a_c__output__buffer.png differ diff --git a/group___d_a_c__trigger__selection.html b/group___d_a_c__trigger__selection.html new file mode 100644 index 0000000..66e207b --- /dev/null +++ b/group___d_a_c__trigger__selection.html @@ -0,0 +1,278 @@ + + + + + + +discoverpixy: DAC_trigger_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DAC_trigger_selection
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_trigger_selection:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DAC_Trigger_None   ((uint32_t)0x00000000)
 
#define DAC_Trigger_T2_TRGO   ((uint32_t)0x00000024)
 
#define DAC_Trigger_T4_TRGO   ((uint32_t)0x0000002C)
 
#define DAC_Trigger_T5_TRGO   ((uint32_t)0x0000001C)
 
#define DAC_Trigger_T6_TRGO   ((uint32_t)0x00000004)
 
#define DAC_Trigger_T7_TRGO   ((uint32_t)0x00000014)
 
#define DAC_Trigger_T8_TRGO   ((uint32_t)0x0000000C)
 
#define DAC_Trigger_Ext_IT9   ((uint32_t)0x00000034)
 
#define DAC_Trigger_Software   ((uint32_t)0x0000003C)
 
#define IS_DAC_TRIGGER(TRIGGER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DAC_Trigger_Ext_IT9   ((uint32_t)0x00000034)
+
+

EXTI Line9 event selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_None   ((uint32_t)0x00000000)
+
+

Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_Software   ((uint32_t)0x0000003C)
+
+

Conversion started by software trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T2_TRGO   ((uint32_t)0x00000024)
+
+

TIM2 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T4_TRGO   ((uint32_t)0x0000002C)
+
+

TIM4 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T5_TRGO   ((uint32_t)0x0000001C)
+
+

TIM5 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T6_TRGO   ((uint32_t)0x00000004)
+
+

TIM6 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T7_TRGO   ((uint32_t)0x00000014)
+
+

TIM7 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + +
#define DAC_Trigger_T8_TRGO   ((uint32_t)0x0000000C)
+
+

TIM8 TRGO selected as external conversion trigger for DAC channel

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DAC_TRIGGER( TRIGGER)
+
+Value:
(((TRIGGER) == DAC_Trigger_None) || \
+
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+
((TRIGGER) == DAC_Trigger_Software))
+
DAC_Trigger_T6_TRGO
#define DAC_Trigger_T6_TRGO
Definition: stm32f4xx_dac.h:87
+
DAC_Trigger_T8_TRGO
#define DAC_Trigger_T8_TRGO
Definition: stm32f4xx_dac.h:89
+
DAC_Trigger_T4_TRGO
#define DAC_Trigger_T4_TRGO
Definition: stm32f4xx_dac.h:85
+
DAC_Trigger_Ext_IT9
#define DAC_Trigger_Ext_IT9
Definition: stm32f4xx_dac.h:91
+
DAC_Trigger_None
#define DAC_Trigger_None
Definition: stm32f4xx_dac.h:81
+
DAC_Trigger_Software
#define DAC_Trigger_Software
Definition: stm32f4xx_dac.h:92
+
DAC_Trigger_T2_TRGO
#define DAC_Trigger_T2_TRGO
Definition: stm32f4xx_dac.h:84
+
DAC_Trigger_T7_TRGO
#define DAC_Trigger_T7_TRGO
Definition: stm32f4xx_dac.h:88
+
DAC_Trigger_T5_TRGO
#define DAC_Trigger_T5_TRGO
Definition: stm32f4xx_dac.h:86
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__trigger__selection.map b/group___d_a_c__trigger__selection.map new file mode 100644 index 0000000..0b4d035 --- /dev/null +++ b/group___d_a_c__trigger__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__trigger__selection.md5 b/group___d_a_c__trigger__selection.md5 new file mode 100644 index 0000000..b287801 --- /dev/null +++ b/group___d_a_c__trigger__selection.md5 @@ -0,0 +1 @@ +e99655ea9132a92c944860dbbdd4fc4b \ No newline at end of file diff --git a/group___d_a_c__trigger__selection.png b/group___d_a_c__trigger__selection.png new file mode 100644 index 0000000..09c26c5 Binary files /dev/null and b/group___d_a_c__trigger__selection.png differ diff --git a/group___d_a_c__wave__generation.html b/group___d_a_c__wave__generation.html new file mode 100644 index 0000000..12e8349 --- /dev/null +++ b/group___d_a_c__wave__generation.html @@ -0,0 +1,163 @@ + + + + + + +discoverpixy: DAC_wave_generation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+Macros
+
+
DAC_wave_generation
STM32F4xx_StdPeriph_Driver » DAC » DAC_Exported_Constants
+
+
+
+Collaboration diagram for DAC_wave_generation:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define DAC_WaveGeneration_None   ((uint32_t)0x00000000)
 
+#define DAC_WaveGeneration_Noise   ((uint32_t)0x00000040)
 
+#define DAC_WaveGeneration_Triangle   ((uint32_t)0x00000080)
 
#define IS_DAC_GENERATE_WAVE(WAVE)
 
+#define DAC_Wave_Noise   ((uint32_t)0x00000040)
 
+#define DAC_Wave_Triangle   ((uint32_t)0x00000080)
 
#define IS_DAC_WAVE(WAVE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DAC_GENERATE_WAVE( WAVE)
+
+Value:
(((WAVE) == DAC_WaveGeneration_None) || \
+
((WAVE) == DAC_WaveGeneration_Noise) || \
+
((WAVE) == DAC_WaveGeneration_Triangle))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DAC_WAVE( WAVE)
+
+Value:
(((WAVE) == DAC_Wave_Noise) || \
+
((WAVE) == DAC_Wave_Triangle))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_a_c__wave__generation.map b/group___d_a_c__wave__generation.map new file mode 100644 index 0000000..7aa1dee --- /dev/null +++ b/group___d_a_c__wave__generation.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c__wave__generation.md5 b/group___d_a_c__wave__generation.md5 new file mode 100644 index 0000000..138cec8 --- /dev/null +++ b/group___d_a_c__wave__generation.md5 @@ -0,0 +1 @@ +f53855b3c5cbd2744dced9103a69603f \ No newline at end of file diff --git a/group___d_a_c__wave__generation.png b/group___d_a_c__wave__generation.png new file mode 100644 index 0000000..1883881 Binary files /dev/null and b/group___d_a_c__wave__generation.png differ diff --git a/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map new file mode 100644 index 0000000..e849f0f --- /dev/null +++ b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 new file mode 100644 index 0000000..931bfa0 --- /dev/null +++ b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.md5 @@ -0,0 +1 @@ +04ec67b258886c02ac84d96a741e392e \ No newline at end of file diff --git a/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png new file mode 100644 index 0000000..40e12d1 Binary files /dev/null and b/group___d_a_c_ga1fae225204e1e049d6795319e99ba8bc_cgraph.png differ diff --git a/group___d_b_g_m_c_u.html b/group___d_b_g_m_c_u.html new file mode 100644 index 0000000..e09d9f0 --- /dev/null +++ b/group___d_b_g_m_c_u.html @@ -0,0 +1,354 @@ + + + + + + +discoverpixy: DBGMCU + + + + + + + + + + +
+
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+
+ + +
+ +
+ +
+
+Modules | +Macros | +Functions
+
+
DBGMCU
STM32F4xx_StdPeriph_Driver
+
+
+ +

DBGMCU driver modules. +More...

+
+Collaboration diagram for DBGMCU:
+
+
+ + +
+
+ + + + + + +

+Modules

 DBGMCU_Exported_Constants
 
 DBGMCU_Private_Functions
 
+ + + +

+Macros

+#define IDCODE_DEVID_MASK   ((uint32_t)0x00000FFF)
 
+ + + + + + + + + + + + + + + + +

+Functions

uint32_t DBGMCU_GetREVID (void)
 Returns the device revision identifier. More...
 
uint32_t DBGMCU_GetDEVID (void)
 Returns the device identifier. More...
 
void DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures low power mode behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB1 peripheral behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB2 peripheral behavior when the MCU is in Debug mode. More...
 
+

Detailed Description

+

DBGMCU driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures APB1 peripheral behavior when the MCU is in Debug mode.

+
Parameters
+ + +
DBGMCU_Periphspecifies the APB1 peripheral. This parameter can be any combination of the following values:
    +
  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
    • +
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
    • +
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
    • +
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
    • +
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
    • +
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
    • +
  • DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
    • +
  • DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
    • +
  • DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
    • +
  • DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
    • +
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
    • +
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
    • +
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
    • +
  • DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted This parameter can be: ENABLE or DISABLE.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures APB2 peripheral behavior when the MCU is in Debug mode.

+
Parameters
+ + + +
DBGMCU_Periphspecifies the APB2 peripheral. This parameter can be any combination of the following values:
    +
  • DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
    • +
  • DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
    • +
  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
    • +
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
    • +
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
    • +
+
NewStatenew state of the specified peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_Config (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures low power mode behavior when the MCU is in Debug mode.

+
Parameters
+ + + +
DBGMCU_Periphspecifies the low power mode. This parameter can be any combination of the following values:
    +
  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
    • +
  • DBGMCU_STOP: Keep debugger connection during STOP mode
    • +
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
    • +
+
NewStatenew state of the specified low power mode in Debug mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DBGMCU_GetDEVID (void )
+
+ +

Returns the device identifier.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Deviceidentifier
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DBGMCU_GetREVID (void )
+
+ +

Returns the device revision identifier.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Devicerevision identifier
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_b_g_m_c_u.map b/group___d_b_g_m_c_u.map new file mode 100644 index 0000000..23df2fa --- /dev/null +++ b/group___d_b_g_m_c_u.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_b_g_m_c_u.md5 b/group___d_b_g_m_c_u.md5 new file mode 100644 index 0000000..461d31e --- /dev/null +++ b/group___d_b_g_m_c_u.md5 @@ -0,0 +1 @@ +2518c39846ed58e8209f062d02921e71 \ No newline at end of file diff --git a/group___d_b_g_m_c_u.png b/group___d_b_g_m_c_u.png new file mode 100644 index 0000000..bb777c5 Binary files /dev/null and b/group___d_b_g_m_c_u.png differ diff --git a/group___d_b_g_m_c_u___exported___constants.html b/group___d_b_g_m_c_u___exported___constants.html new file mode 100644 index 0000000..bf9ee45 --- /dev/null +++ b/group___d_b_g_m_c_u___exported___constants.html @@ -0,0 +1,190 @@ + + + + + + +discoverpixy: DBGMCU_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DBGMCU_Exported_Constants
STM32F4xx_StdPeriph_Driver » DBGMCU
+
+
+
+Collaboration diagram for DBGMCU_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DBGMCU_SLEEP   ((uint32_t)0x00000001)
 
+#define DBGMCU_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_STANDBY   ((uint32_t)0x00000004)
 
+#define IS_DBGMCU_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
 
+#define DBGMCU_TIM2_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM3_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM4_STOP   ((uint32_t)0x00000004)
 
+#define DBGMCU_TIM5_STOP   ((uint32_t)0x00000008)
 
+#define DBGMCU_TIM6_STOP   ((uint32_t)0x00000010)
 
+#define DBGMCU_TIM7_STOP   ((uint32_t)0x00000020)
 
+#define DBGMCU_TIM12_STOP   ((uint32_t)0x00000040)
 
+#define DBGMCU_TIM13_STOP   ((uint32_t)0x00000080)
 
+#define DBGMCU_TIM14_STOP   ((uint32_t)0x00000100)
 
+#define DBGMCU_RTC_STOP   ((uint32_t)0x00000400)
 
+#define DBGMCU_WWDG_STOP   ((uint32_t)0x00000800)
 
+#define DBGMCU_IWDG_STOP   ((uint32_t)0x00001000)
 
+#define DBGMCU_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
 
+#define DBGMCU_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
 
+#define DBGMCU_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
 
+#define DBGMCU_CAN1_STOP   ((uint32_t)0x02000000)
 
+#define DBGMCU_CAN2_STOP   ((uint32_t)0x04000000)
 
+#define IS_DBGMCU_APB1PERIPH(PERIPH)   ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
 
+#define DBGMCU_TIM1_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM8_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM9_STOP   ((uint32_t)0x00010000)
 
+#define DBGMCU_TIM10_STOP   ((uint32_t)0x00020000)
 
+#define DBGMCU_TIM11_STOP   ((uint32_t)0x00040000)
 
+#define IS_DBGMCU_APB2PERIPH(PERIPH)   ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_b_g_m_c_u___exported___constants.map b/group___d_b_g_m_c_u___exported___constants.map new file mode 100644 index 0000000..2c56de3 --- /dev/null +++ b/group___d_b_g_m_c_u___exported___constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_b_g_m_c_u___exported___constants.md5 b/group___d_b_g_m_c_u___exported___constants.md5 new file mode 100644 index 0000000..b72d40d --- /dev/null +++ b/group___d_b_g_m_c_u___exported___constants.md5 @@ -0,0 +1 @@ +0e6ddd66d3632cdee7ff3c531c685391 \ No newline at end of file diff --git a/group___d_b_g_m_c_u___exported___constants.png b/group___d_b_g_m_c_u___exported___constants.png new file mode 100644 index 0000000..91bce31 Binary files /dev/null and b/group___d_b_g_m_c_u___exported___constants.png differ diff --git a/group___d_b_g_m_c_u___private___functions.html b/group___d_b_g_m_c_u___private___functions.html new file mode 100644 index 0000000..004a6f8 --- /dev/null +++ b/group___d_b_g_m_c_u___private___functions.html @@ -0,0 +1,335 @@ + + + + + + +discoverpixy: DBGMCU_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DBGMCU_Private_Functions
STM32F4xx_StdPeriph_Driver » DBGMCU
+
+
+
+Collaboration diagram for DBGMCU_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

uint32_t DBGMCU_GetREVID (void)
 Returns the device revision identifier. More...
 
uint32_t DBGMCU_GetDEVID (void)
 Returns the device identifier. More...
 
void DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures low power mode behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB1 peripheral behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB2 peripheral behavior when the MCU is in Debug mode. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures APB1 peripheral behavior when the MCU is in Debug mode.

+
Parameters
+ + +
DBGMCU_Periphspecifies the APB1 peripheral. This parameter can be any combination of the following values:
    +
  • DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
    • +
  • DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
    • +
  • DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
    • +
  • DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
    • +
  • DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
    • +
  • DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
    • +
  • DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
    • +
  • DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
    • +
  • DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
    • +
  • DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
    • +
  • DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
    • +
  • DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
    • +
  • DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
    • +
  • DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
    • +
  • DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted This parameter can be: ENABLE or DISABLE.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures APB2 peripheral behavior when the MCU is in Debug mode.

+
Parameters
+ + + +
DBGMCU_Periphspecifies the APB2 peripheral. This parameter can be any combination of the following values:
    +
  • DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
    • +
  • DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
    • +
  • DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
    • +
  • DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
    • +
  • DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
    • +
+
NewStatenew state of the specified peripheral in Debug mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DBGMCU_Config (uint32_t DBGMCU_Periph,
FunctionalState NewState 
)
+
+ +

Configures low power mode behavior when the MCU is in Debug mode.

+
Parameters
+ + + +
DBGMCU_Periphspecifies the low power mode. This parameter can be any combination of the following values:
    +
  • DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
    • +
  • DBGMCU_STOP: Keep debugger connection during STOP mode
    • +
  • DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
    • +
+
NewStatenew state of the specified low power mode in Debug mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DBGMCU_GetDEVID (void )
+
+ +

Returns the device identifier.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Deviceidentifier
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DBGMCU_GetREVID (void )
+
+ +

Returns the device revision identifier.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Devicerevision identifier
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_b_g_m_c_u___private___functions.map b/group___d_b_g_m_c_u___private___functions.map new file mode 100644 index 0000000..c94baa4 --- /dev/null +++ b/group___d_b_g_m_c_u___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_b_g_m_c_u___private___functions.md5 b/group___d_b_g_m_c_u___private___functions.md5 new file mode 100644 index 0000000..58fed28 --- /dev/null +++ b/group___d_b_g_m_c_u___private___functions.md5 @@ -0,0 +1 @@ +eb552061b5f08f1dedbc043bc5cf8374 \ No newline at end of file diff --git a/group___d_b_g_m_c_u___private___functions.png b/group___d_b_g_m_c_u___private___functions.png new file mode 100644 index 0000000..d1f18b0 Binary files /dev/null and b/group___d_b_g_m_c_u___private___functions.png differ diff --git a/group___d_c_m_i.html b/group___d_c_m_i.html new file mode 100644 index 0000000..4799873 --- /dev/null +++ b/group___d_c_m_i.html @@ -0,0 +1,684 @@ + + + + + + +discoverpixy: DCMI + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Functions
+
+
DCMI
STM32F4xx_StdPeriph_Driver
+
+
+ +

DCMI driver modules. +More...

+
+Collaboration diagram for DCMI:
+
+
+ + +
+
+ + + + + + +

+Modules

 DCMI_Exported_Constants
 
 DCMI_Private_Functions
 
+ + + + + + + + + + +

+Classes

struct  DCMI_InitTypeDef
 DCMI Init structure definition. More...
 
struct  DCMI_CROPInitTypeDef
 DCMI CROP Init structure definition. More...
 
struct  DCMI_CodesInitTypeDef
 DCMI Embedded Synchronisation CODE Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DCMI_DeInit (void)
 Deinitializes the DCMI registers to their default reset values. More...
 
void DCMI_Init (DCMI_InitTypeDef *DCMI_InitStruct)
 Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. More...
 
void DCMI_StructInit (DCMI_InitTypeDef *DCMI_InitStruct)
 Fills each DCMI_InitStruct member with its default value. More...
 
void DCMI_CROPConfig (DCMI_CROPInitTypeDef *DCMI_CROPInitStruct)
 Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct. More...
 
void DCMI_CROPCmd (FunctionalState NewState)
 Enables or disables the DCMI Crop feature. More...
 
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef *DCMI_CodesInitStruct)
 Sets the embedded synchronization codes. More...
 
void DCMI_JPEGCmd (FunctionalState NewState)
 Enables or disables the DCMI JPEG format. More...
 
void DCMI_Cmd (FunctionalState NewState)
 Enables or disables the DCMI interface. More...
 
void DCMI_CaptureCmd (FunctionalState NewState)
 Enables or disables the DCMI Capture. More...
 
uint32_t DCMI_ReadData (void)
 Reads the data stored in the DR register. More...
 
void DCMI_ITConfig (uint16_t DCMI_IT, FunctionalState NewState)
 Enables or disables the DCMI interface interrupts. More...
 
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
 Checks whether the DCMI interface flag is set or not. More...
 
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
 Clears the DCMI's pending flags. More...
 
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
 Checks whether the DCMI interrupt has occurred or not. More...
 
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
 Clears the DCMI's interrupt pending bits. More...
 
+

Detailed Description

+

DCMI driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void DCMI_CaptureCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI Capture.

+
Parameters
+ + +
NewStatenew state of the DCMI capture. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
+
+ +

Clears the DCMI's pending flags.

+
Parameters
+ + +
DCMI_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
    • +
  • DCMI_FLAG_OVFRI: Overflow Raw flag mask
    • +
  • DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
    • +
  • DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
    • +
  • DCMI_FLAG_LINERI: Line Raw flag mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
+
+ +

Clears the DCMI's interrupt pending bits.

+
Parameters
+ + +
DCMI_ITspecifies the DCMI interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI interface.

+
Parameters
+ + +
NewStatenew state of the DCMI interface. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_CROPCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI Crop feature.

+
Note
This function should be called before to enable and start the DCMI interface.
+
Parameters
+ + +
NewStatenew state of the DCMI Crop feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_CROPConfig (DCMI_CROPInitTypeDef * DCMI_CROPInitStruct)
+
+ +

Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct.

+
Note
This function should be called before to enable and start the DCMI interface.
+
Parameters
+ + +
DCMI_CROPInitStructpointer to a DCMI_CROPInitTypeDef structure that contains the configuration information for the DCMI peripheral CROP mode.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_DeInit (void )
+
+ +

Deinitializes the DCMI registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
+
+ +

Checks whether the DCMI interface flag is set or not.

+
Parameters
+ + +
DCMI_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
    • +
  • DCMI_FLAG_OVFRI: Overflow Raw flag mask
    • +
  • DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
    • +
  • DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
    • +
  • DCMI_FLAG_LINERI: Line Raw flag mask
    • +
  • DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
    • +
  • DCMI_FLAG_OVFMI: Overflow Masked flag mask
    • +
  • DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
    • +
  • DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
    • +
  • DCMI_FLAG_LINEMI: Line Masked flag mask
    • +
  • DCMI_FLAG_HSYNC: HSYNC flag mask
    • +
  • DCMI_FLAG_VSYNC: VSYNC flag mask
    • +
  • DCMI_FLAG_FNE: Fifo not empty flag mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of DCMI_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
+
+ +

Checks whether the DCMI interrupt has occurred or not.

+
Parameters
+ + +
DCMI_ITspecifies the DCMI interrupt source to check. This parameter can be one of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of DCMI_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_Init (DCMI_InitTypeDef * DCMI_InitStruct)
+
+ +

Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.

+
Parameters
+ + +
DCMI_InitStructpointer to a DCMI_InitTypeDef structure that contains the configuration information for the DCMI.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DCMI_ITConfig (uint16_t DCMI_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the DCMI interface interrupts.

+
Parameters
+ + + +
DCMI_ITspecifies the DCMI interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
NewStatenew state of the specified DCMI interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_JPEGCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI JPEG format.

+
Note
The Crop and Embedded Synchronization features cannot be used in this mode.
+
Parameters
+ + +
NewStatenew state of the DCMI JPEG format. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DCMI_ReadData (void )
+
+ +

Reads the data stored in the DR register.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Dataregister value
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef * DCMI_CodesInitStruct)
+
+ +

Sets the embedded synchronization codes.

+
Parameters
+ + +
DCMI_CodesInitTypeDefpointer to a DCMI_CodesInitTypeDef structure that contains the embedded synchronization codes for the DCMI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_StructInit (DCMI_InitTypeDef * DCMI_InitStruct)
+
+ +

Fills each DCMI_InitStruct member with its default value.

+
Parameters
+ + +
DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i.map b/group___d_c_m_i.map new file mode 100644 index 0000000..1f90824 --- /dev/null +++ b/group___d_c_m_i.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_c_m_i.md5 b/group___d_c_m_i.md5 new file mode 100644 index 0000000..18bc54e --- /dev/null +++ b/group___d_c_m_i.md5 @@ -0,0 +1 @@ +21edd48cf72e910f19bfc6d190ab0d9e \ No newline at end of file diff --git a/group___d_c_m_i.png b/group___d_c_m_i.png new file mode 100644 index 0000000..26c7728 Binary files /dev/null and b/group___d_c_m_i.png differ diff --git a/group___d_c_m_i___capture___mode.html b/group___d_c_m_i___capture___mode.html new file mode 100644 index 0000000..7109499 --- /dev/null +++ b/group___d_c_m_i___capture___mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: DCMI_Capture_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_Capture_Mode
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_Capture_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define DCMI_CaptureMode_Continuous   ((uint16_t)0x0000)
 
#define DCMI_CaptureMode_SnapShot   ((uint16_t)0x0002)
 
#define IS_DCMI_CAPTURE_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_CaptureMode_Continuous   ((uint16_t)0x0000)
+
+

The received data are transferred continuously into the destination memory through the DMA

+ +
+
+ +
+
+ + + + +
#define DCMI_CaptureMode_SnapShot   ((uint16_t)0x0002)
+
+

Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_CAPTURE_MODE( MODE)
+
+Value:
(((MODE) == DCMI_CaptureMode_Continuous) || \
+
((MODE) == DCMI_CaptureMode_SnapShot))
+
DCMI_CaptureMode_SnapShot
#define DCMI_CaptureMode_SnapShot
Definition: stm32f4xx_dcmi.h:117
+
DCMI_CaptureMode_Continuous
#define DCMI_CaptureMode_Continuous
Definition: stm32f4xx_dcmi.h:114
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___capture___mode.map b/group___d_c_m_i___capture___mode.map new file mode 100644 index 0000000..d68f0ae --- /dev/null +++ b/group___d_c_m_i___capture___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___capture___mode.md5 b/group___d_c_m_i___capture___mode.md5 new file mode 100644 index 0000000..c1b8741 --- /dev/null +++ b/group___d_c_m_i___capture___mode.md5 @@ -0,0 +1 @@ +25c1167eac8e433f2bc4e56fb7f3e970 \ No newline at end of file diff --git a/group___d_c_m_i___capture___mode.png b/group___d_c_m_i___capture___mode.png new file mode 100644 index 0000000..081a894 Binary files /dev/null and b/group___d_c_m_i___capture___mode.png differ diff --git a/group___d_c_m_i___capture___rate.html b/group___d_c_m_i___capture___rate.html new file mode 100644 index 0000000..e00d01e --- /dev/null +++ b/group___d_c_m_i___capture___rate.html @@ -0,0 +1,176 @@ + + + + + + +discoverpixy: DCMI_Capture_Rate + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_Capture_Rate
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_Capture_Rate:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define DCMI_CaptureRate_All_Frame   ((uint16_t)0x0000)
 
#define DCMI_CaptureRate_1of2_Frame   ((uint16_t)0x0100)
 
#define DCMI_CaptureRate_1of4_Frame   ((uint16_t)0x0200)
 
#define IS_DCMI_CAPTURE_RATE(RATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_CaptureRate_1of2_Frame   ((uint16_t)0x0100)
+
+

Every alternate frame captured

+ +
+
+ +
+
+ + + + +
#define DCMI_CaptureRate_1of4_Frame   ((uint16_t)0x0200)
+
+

One frame in 4 frames captured

+ +
+
+ +
+
+ + + + +
#define DCMI_CaptureRate_All_Frame   ((uint16_t)0x0000)
+
+

All frames are captured

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_CAPTURE_RATE( RATE)
+
+Value:
(((RATE) == DCMI_CaptureRate_All_Frame) || \
+
((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
+
((RATE) == DCMI_CaptureRate_1of4_Frame))
+
DCMI_CaptureRate_1of4_Frame
#define DCMI_CaptureRate_1of4_Frame
Definition: stm32f4xx_dcmi.h:184
+
DCMI_CaptureRate_All_Frame
#define DCMI_CaptureRate_All_Frame
Definition: stm32f4xx_dcmi.h:182
+
DCMI_CaptureRate_1of2_Frame
#define DCMI_CaptureRate_1of2_Frame
Definition: stm32f4xx_dcmi.h:183
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___capture___rate.map b/group___d_c_m_i___capture___rate.map new file mode 100644 index 0000000..956270d --- /dev/null +++ b/group___d_c_m_i___capture___rate.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___capture___rate.md5 b/group___d_c_m_i___capture___rate.md5 new file mode 100644 index 0000000..40df150 --- /dev/null +++ b/group___d_c_m_i___capture___rate.md5 @@ -0,0 +1 @@ +5e7ddf98d33d8bfeab12f83ce5871b13 \ No newline at end of file diff --git a/group___d_c_m_i___capture___rate.png b/group___d_c_m_i___capture___rate.png new file mode 100644 index 0000000..047c0aa Binary files /dev/null and b/group___d_c_m_i___capture___rate.png differ diff --git a/group___d_c_m_i___exported___constants.html b/group___d_c_m_i___exported___constants.html new file mode 100644 index 0000000..efdda5b --- /dev/null +++ b/group___d_c_m_i___exported___constants.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: DCMI_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DCMI_Exported_Constants
STM32F4xx_StdPeriph_Driver » DCMI
+
+
+
+Collaboration diagram for DCMI_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Modules

 DCMI_Capture_Mode
 
 DCMI_Synchronization_Mode
 
 DCMI_PIXCK_Polarity
 
 DCMI_VSYNC_Polarity
 
 DCMI_HSYNC_Polarity
 
 DCMI_Capture_Rate
 
 DCMI_Extended_Data_Mode
 
 DCMI_interrupt_sources
 
 DCMI_Flags
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___exported___constants.map b/group___d_c_m_i___exported___constants.map new file mode 100644 index 0000000..11d10a5 --- /dev/null +++ b/group___d_c_m_i___exported___constants.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___d_c_m_i___exported___constants.md5 b/group___d_c_m_i___exported___constants.md5 new file mode 100644 index 0000000..bd0fcd1 --- /dev/null +++ b/group___d_c_m_i___exported___constants.md5 @@ -0,0 +1 @@ +a3b88097a91e92f1baf9acd67e9e8058 \ No newline at end of file diff --git a/group___d_c_m_i___exported___constants.png b/group___d_c_m_i___exported___constants.png new file mode 100644 index 0000000..d67fe8b Binary files /dev/null and b/group___d_c_m_i___exported___constants.png differ diff --git a/group___d_c_m_i___extended___data___mode.html b/group___d_c_m_i___extended___data___mode.html new file mode 100644 index 0000000..17ab1b4 --- /dev/null +++ b/group___d_c_m_i___extended___data___mode.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: DCMI_Extended_Data_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_Extended_Data_Mode
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_Extended_Data_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define DCMI_ExtendedDataMode_8b   ((uint16_t)0x0000)
 
#define DCMI_ExtendedDataMode_10b   ((uint16_t)0x0400)
 
#define DCMI_ExtendedDataMode_12b   ((uint16_t)0x0800)
 
#define DCMI_ExtendedDataMode_14b   ((uint16_t)0x0C00)
 
#define IS_DCMI_EXTENDED_DATA(DATA)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_ExtendedDataMode_10b   ((uint16_t)0x0400)
+
+

Interface captures 10-bit data on every pixel clock

+ +
+
+ +
+
+ + + + +
#define DCMI_ExtendedDataMode_12b   ((uint16_t)0x0800)
+
+

Interface captures 12-bit data on every pixel clock

+ +
+
+ +
+
+ + + + +
#define DCMI_ExtendedDataMode_14b   ((uint16_t)0x0C00)
+
+

Interface captures 14-bit data on every pixel clock

+ +
+
+ +
+
+ + + + +
#define DCMI_ExtendedDataMode_8b   ((uint16_t)0x0000)
+
+

Interface captures 8-bit data on every pixel clock

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_EXTENDED_DATA( DATA)
+
+Value:
(((DATA) == DCMI_ExtendedDataMode_8b) || \
+
((DATA) == DCMI_ExtendedDataMode_10b) ||\
+
((DATA) == DCMI_ExtendedDataMode_12b) ||\
+
((DATA) == DCMI_ExtendedDataMode_14b))
+
DCMI_ExtendedDataMode_8b
#define DCMI_ExtendedDataMode_8b
Definition: stm32f4xx_dcmi.h:196
+
DCMI_ExtendedDataMode_12b
#define DCMI_ExtendedDataMode_12b
Definition: stm32f4xx_dcmi.h:198
+
DCMI_ExtendedDataMode_10b
#define DCMI_ExtendedDataMode_10b
Definition: stm32f4xx_dcmi.h:197
+
DCMI_ExtendedDataMode_14b
#define DCMI_ExtendedDataMode_14b
Definition: stm32f4xx_dcmi.h:199
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___extended___data___mode.map b/group___d_c_m_i___extended___data___mode.map new file mode 100644 index 0000000..c691e32 --- /dev/null +++ b/group___d_c_m_i___extended___data___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___extended___data___mode.md5 b/group___d_c_m_i___extended___data___mode.md5 new file mode 100644 index 0000000..359e5a5 --- /dev/null +++ b/group___d_c_m_i___extended___data___mode.md5 @@ -0,0 +1 @@ +c4da8969006e24cde69165c5ed505774 \ No newline at end of file diff --git a/group___d_c_m_i___extended___data___mode.png b/group___d_c_m_i___extended___data___mode.png new file mode 100644 index 0000000..c9407e8 Binary files /dev/null and b/group___d_c_m_i___extended___data___mode.png differ diff --git a/group___d_c_m_i___flags.html b/group___d_c_m_i___flags.html new file mode 100644 index 0000000..8794c19 --- /dev/null +++ b/group___d_c_m_i___flags.html @@ -0,0 +1,186 @@ + + + + + + +discoverpixy: DCMI_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_Flags
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DCMI_FLAG_HSYNC   ((uint16_t)0x2001)
 DCMI SR register.
 
+#define DCMI_FLAG_VSYNC   ((uint16_t)0x2002)
 
+#define DCMI_FLAG_FNE   ((uint16_t)0x2004)
 
+#define DCMI_FLAG_FRAMERI   ((uint16_t)0x0001)
 DCMI RISR register.
 
+#define DCMI_FLAG_OVFRI   ((uint16_t)0x0002)
 
+#define DCMI_FLAG_ERRRI   ((uint16_t)0x0004)
 
+#define DCMI_FLAG_VSYNCRI   ((uint16_t)0x0008)
 
+#define DCMI_FLAG_LINERI   ((uint16_t)0x0010)
 
+#define DCMI_FLAG_FRAMEMI   ((uint16_t)0x1001)
 DCMI MISR register.
 
+#define DCMI_FLAG_OVFMI   ((uint16_t)0x1002)
 
+#define DCMI_FLAG_ERRMI   ((uint16_t)0x1004)
 
+#define DCMI_FLAG_VSYNCMI   ((uint16_t)0x1008)
 
+#define DCMI_FLAG_LINEMI   ((uint16_t)0x1010)
 
#define IS_DCMI_GET_FLAG(FLAG)
 
+#define IS_DCMI_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DCMI_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == DCMI_FLAG_HSYNC) || \
+
((FLAG) == DCMI_FLAG_VSYNC) || \
+
((FLAG) == DCMI_FLAG_FNE) || \
+
((FLAG) == DCMI_FLAG_FRAMERI) || \
+
((FLAG) == DCMI_FLAG_OVFRI) || \
+
((FLAG) == DCMI_FLAG_ERRRI) || \
+
((FLAG) == DCMI_FLAG_VSYNCRI) || \
+
((FLAG) == DCMI_FLAG_LINERI) || \
+
((FLAG) == DCMI_FLAG_FRAMEMI) || \
+
((FLAG) == DCMI_FLAG_OVFMI) || \
+
((FLAG) == DCMI_FLAG_ERRMI) || \
+
((FLAG) == DCMI_FLAG_VSYNCMI) || \
+
((FLAG) == DCMI_FLAG_LINEMI))
+
DCMI_FLAG_FRAMERI
#define DCMI_FLAG_FRAMERI
DCMI RISR register.
Definition: stm32f4xx_dcmi.h:240
+
DCMI_FLAG_FRAMEMI
#define DCMI_FLAG_FRAMEMI
DCMI MISR register.
Definition: stm32f4xx_dcmi.h:248
+
DCMI_FLAG_HSYNC
#define DCMI_FLAG_HSYNC
DCMI SR register.
Definition: stm32f4xx_dcmi.h:234
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___flags.map b/group___d_c_m_i___flags.map new file mode 100644 index 0000000..4f6b9a4 --- /dev/null +++ b/group___d_c_m_i___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___flags.md5 b/group___d_c_m_i___flags.md5 new file mode 100644 index 0000000..bf3df69 --- /dev/null +++ b/group___d_c_m_i___flags.md5 @@ -0,0 +1 @@ +c646c06ea965361ee305987ef48a8415 \ No newline at end of file diff --git a/group___d_c_m_i___flags.png b/group___d_c_m_i___flags.png new file mode 100644 index 0000000..365e794 Binary files /dev/null and b/group___d_c_m_i___flags.png differ diff --git a/group___d_c_m_i___group1.html b/group___d_c_m_i___group1.html new file mode 100644 index 0000000..67aa7b2 --- /dev/null +++ b/group___d_c_m_i___group1.html @@ -0,0 +1,347 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DCMI_DeInit (void)
 Deinitializes the DCMI registers to their default reset values. More...
 
void DCMI_Init (DCMI_InitTypeDef *DCMI_InitStruct)
 Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. More...
 
void DCMI_StructInit (DCMI_InitTypeDef *DCMI_InitStruct)
 Fills each DCMI_InitStruct member with its default value. More...
 
void DCMI_CROPConfig (DCMI_CROPInitTypeDef *DCMI_CROPInitStruct)
 Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct. More...
 
void DCMI_CROPCmd (FunctionalState NewState)
 Enables or disables the DCMI Crop feature. More...
 
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef *DCMI_CodesInitStruct)
 Sets the embedded synchronization codes. More...
 
void DCMI_JPEGCmd (FunctionalState NewState)
 Enables or disables the DCMI JPEG format. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void DCMI_CROPCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI Crop feature.

+
Note
This function should be called before to enable and start the DCMI interface.
+
Parameters
+ + +
NewStatenew state of the DCMI Crop feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_CROPConfig (DCMI_CROPInitTypeDef * DCMI_CROPInitStruct)
+
+ +

Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct.

+
Note
This function should be called before to enable and start the DCMI interface.
+
Parameters
+ + +
DCMI_CROPInitStructpointer to a DCMI_CROPInitTypeDef structure that contains the configuration information for the DCMI peripheral CROP mode.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_DeInit (void )
+
+ +

Deinitializes the DCMI registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_Init (DCMI_InitTypeDef * DCMI_InitStruct)
+
+ +

Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.

+
Parameters
+ + +
DCMI_InitStructpointer to a DCMI_InitTypeDef structure that contains the configuration information for the DCMI.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_JPEGCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI JPEG format.

+
Note
The Crop and Embedded Synchronization features cannot be used in this mode.
+
Parameters
+ + +
NewStatenew state of the DCMI JPEG format. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef * DCMI_CodesInitStruct)
+
+ +

Sets the embedded synchronization codes.

+
Parameters
+ + +
DCMI_CodesInitTypeDefpointer to a DCMI_CodesInitTypeDef structure that contains the embedded synchronization codes for the DCMI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_StructInit (DCMI_InitTypeDef * DCMI_InitStruct)
+
+ +

Fills each DCMI_InitStruct member with its default value.

+
Parameters
+ + +
DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___group1.map b/group___d_c_m_i___group1.map new file mode 100644 index 0000000..b1783b0 --- /dev/null +++ b/group___d_c_m_i___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___group1.md5 b/group___d_c_m_i___group1.md5 new file mode 100644 index 0000000..6f939f7 --- /dev/null +++ b/group___d_c_m_i___group1.md5 @@ -0,0 +1 @@ +8e793b003d9794f6cfa31b00ddbad917 \ No newline at end of file diff --git a/group___d_c_m_i___group1.png b/group___d_c_m_i___group1.png new file mode 100644 index 0000000..0926732 Binary files /dev/null and b/group___d_c_m_i___group1.png differ diff --git a/group___d_c_m_i___group2.html b/group___d_c_m_i___group2.html new file mode 100644 index 0000000..ecd0d00 --- /dev/null +++ b/group___d_c_m_i___group2.html @@ -0,0 +1,212 @@ + + + + + + +discoverpixy: Image capture functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Image capture functions
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Private_Functions
+
+
+ +

Image capture functions. +More...

+
+Collaboration diagram for Image capture functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void DCMI_Cmd (FunctionalState NewState)
 Enables or disables the DCMI interface. More...
 
void DCMI_CaptureCmd (FunctionalState NewState)
 Enables or disables the DCMI Capture. More...
 
uint32_t DCMI_ReadData (void)
 Reads the data stored in the DR register. More...
 
+

Detailed Description

+

Image capture functions.

+
 ===============================================================================
+                    ##### Image capture functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void DCMI_CaptureCmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI Capture.

+
Parameters
+ + +
NewStatenew state of the DCMI capture. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the DCMI interface.

+
Parameters
+ + +
NewStatenew state of the DCMI interface. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DCMI_ReadData (void )
+
+ +

Reads the data stored in the DR register.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Dataregister value
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___group2.map b/group___d_c_m_i___group2.map new file mode 100644 index 0000000..b80a7e4 --- /dev/null +++ b/group___d_c_m_i___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___group2.md5 b/group___d_c_m_i___group2.md5 new file mode 100644 index 0000000..10b1ef0 --- /dev/null +++ b/group___d_c_m_i___group2.md5 @@ -0,0 +1 @@ +2ff6a2a2351ddce4714b5aaa2f0e3f52 \ No newline at end of file diff --git a/group___d_c_m_i___group2.png b/group___d_c_m_i___group2.png new file mode 100644 index 0000000..ed58836 Binary files /dev/null and b/group___d_c_m_i___group2.png differ diff --git a/group___d_c_m_i___group3.html b/group___d_c_m_i___group3.html new file mode 100644 index 0000000..1714f0e --- /dev/null +++ b/group___d_c_m_i___group3.html @@ -0,0 +1,332 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void DCMI_ITConfig (uint16_t DCMI_IT, FunctionalState NewState)
 Enables or disables the DCMI interface interrupts. More...
 
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
 Checks whether the DCMI interface flag is set or not. More...
 
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
 Clears the DCMI's pending flags. More...
 
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
 Checks whether the DCMI interrupt has occurred or not. More...
 
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
 Clears the DCMI's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
+
+ +

Clears the DCMI's pending flags.

+
Parameters
+ + +
DCMI_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
    • +
  • DCMI_FLAG_OVFRI: Overflow Raw flag mask
    • +
  • DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
    • +
  • DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
    • +
  • DCMI_FLAG_LINERI: Line Raw flag mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
+
+ +

Clears the DCMI's interrupt pending bits.

+
Parameters
+ + +
DCMI_ITspecifies the DCMI interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
+
+ +

Checks whether the DCMI interface flag is set or not.

+
Parameters
+ + +
DCMI_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
    • +
  • DCMI_FLAG_OVFRI: Overflow Raw flag mask
    • +
  • DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
    • +
  • DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
    • +
  • DCMI_FLAG_LINERI: Line Raw flag mask
    • +
  • DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
    • +
  • DCMI_FLAG_OVFMI: Overflow Masked flag mask
    • +
  • DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
    • +
  • DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
    • +
  • DCMI_FLAG_LINEMI: Line Masked flag mask
    • +
  • DCMI_FLAG_HSYNC: HSYNC flag mask
    • +
  • DCMI_FLAG_VSYNC: VSYNC flag mask
    • +
  • DCMI_FLAG_FNE: Fifo not empty flag mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of DCMI_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
+
+ +

Checks whether the DCMI interrupt has occurred or not.

+
Parameters
+ + +
DCMI_ITspecifies the DCMI interrupt source to check. This parameter can be one of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
+
+
+
Return values
+ + +
Thenew state of DCMI_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DCMI_ITConfig (uint16_t DCMI_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the DCMI interface interrupts.

+
Parameters
+ + + +
DCMI_ITspecifies the DCMI interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DCMI_IT_FRAME: Frame capture complete interrupt mask
    • +
  • DCMI_IT_OVF: Overflow interrupt mask
    • +
  • DCMI_IT_ERR: Synchronization error interrupt mask
    • +
  • DCMI_IT_VSYNC: VSYNC interrupt mask
    • +
  • DCMI_IT_LINE: Line interrupt mask
    • +
+
NewStatenew state of the specified DCMI interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___group3.map b/group___d_c_m_i___group3.map new file mode 100644 index 0000000..86c6567 --- /dev/null +++ b/group___d_c_m_i___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___group3.md5 b/group___d_c_m_i___group3.md5 new file mode 100644 index 0000000..2fc88dc --- /dev/null +++ b/group___d_c_m_i___group3.md5 @@ -0,0 +1 @@ +9cac0d40a25e7ce72a431919275d2abb \ No newline at end of file diff --git a/group___d_c_m_i___group3.png b/group___d_c_m_i___group3.png new file mode 100644 index 0000000..a9ddd5c Binary files /dev/null and b/group___d_c_m_i___group3.png differ diff --git a/group___d_c_m_i___h_s_y_n_c___polarity.html b/group___d_c_m_i___h_s_y_n_c___polarity.html new file mode 100644 index 0000000..aa59c65 --- /dev/null +++ b/group___d_c_m_i___h_s_y_n_c___polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: DCMI_HSYNC_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_HSYNC_Polarity
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_HSYNC_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define DCMI_HSPolarity_Low   ((uint16_t)0x0000)
 
#define DCMI_HSPolarity_High   ((uint16_t)0x0040)
 
#define IS_DCMI_HSPOLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_HSPolarity_High   ((uint16_t)0x0040)
+
+

Horizontal synchronization active High

+ +
+
+ +
+
+ + + + +
#define DCMI_HSPolarity_Low   ((uint16_t)0x0000)
+
+

Horizontal synchronization active Low

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_HSPOLARITY( POLARITY)
+
+Value:
(((POLARITY) == DCMI_HSPolarity_Low) || \
+
((POLARITY) == DCMI_HSPolarity_High))
+
DCMI_HSPolarity_Low
#define DCMI_HSPolarity_Low
Definition: stm32f4xx_dcmi.h:170
+
DCMI_HSPolarity_High
#define DCMI_HSPolarity_High
Definition: stm32f4xx_dcmi.h:171
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___h_s_y_n_c___polarity.map b/group___d_c_m_i___h_s_y_n_c___polarity.map new file mode 100644 index 0000000..e6dd332 --- /dev/null +++ b/group___d_c_m_i___h_s_y_n_c___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___h_s_y_n_c___polarity.md5 b/group___d_c_m_i___h_s_y_n_c___polarity.md5 new file mode 100644 index 0000000..53922d5 --- /dev/null +++ b/group___d_c_m_i___h_s_y_n_c___polarity.md5 @@ -0,0 +1 @@ +6e8f4d81f32f6d99165b27fac05723b2 \ No newline at end of file diff --git a/group___d_c_m_i___h_s_y_n_c___polarity.png b/group___d_c_m_i___h_s_y_n_c___polarity.png new file mode 100644 index 0000000..4420dda Binary files /dev/null and b/group___d_c_m_i___h_s_y_n_c___polarity.png differ diff --git a/group___d_c_m_i___p_i_x_c_k___polarity.html b/group___d_c_m_i___p_i_x_c_k___polarity.html new file mode 100644 index 0000000..8012362 --- /dev/null +++ b/group___d_c_m_i___p_i_x_c_k___polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: DCMI_PIXCK_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_PIXCK_Polarity
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_PIXCK_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define DCMI_PCKPolarity_Falling   ((uint16_t)0x0000)
 
#define DCMI_PCKPolarity_Rising   ((uint16_t)0x0020)
 
#define IS_DCMI_PCKPOLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_PCKPolarity_Falling   ((uint16_t)0x0000)
+
+

Pixel clock active on Falling edge

+ +
+
+ +
+
+ + + + +
#define DCMI_PCKPolarity_Rising   ((uint16_t)0x0020)
+
+

Pixel clock active on Rising edge

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_PCKPOLARITY( POLARITY)
+
+Value:
(((POLARITY) == DCMI_PCKPolarity_Falling) || \
+
((POLARITY) == DCMI_PCKPolarity_Rising))
+
DCMI_PCKPolarity_Falling
#define DCMI_PCKPolarity_Falling
Definition: stm32f4xx_dcmi.h:146
+
DCMI_PCKPolarity_Rising
#define DCMI_PCKPolarity_Rising
Definition: stm32f4xx_dcmi.h:147
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___p_i_x_c_k___polarity.map b/group___d_c_m_i___p_i_x_c_k___polarity.map new file mode 100644 index 0000000..c68f399 --- /dev/null +++ b/group___d_c_m_i___p_i_x_c_k___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___p_i_x_c_k___polarity.md5 b/group___d_c_m_i___p_i_x_c_k___polarity.md5 new file mode 100644 index 0000000..c3fd27d --- /dev/null +++ b/group___d_c_m_i___p_i_x_c_k___polarity.md5 @@ -0,0 +1 @@ +b3b9f3cf79db9a80c73f74bb9bf1a432 \ No newline at end of file diff --git a/group___d_c_m_i___p_i_x_c_k___polarity.png b/group___d_c_m_i___p_i_x_c_k___polarity.png new file mode 100644 index 0000000..2a2d0a7 Binary files /dev/null and b/group___d_c_m_i___p_i_x_c_k___polarity.png differ diff --git a/group___d_c_m_i___private___functions.html b/group___d_c_m_i___private___functions.html new file mode 100644 index 0000000..df9b8af --- /dev/null +++ b/group___d_c_m_i___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: DCMI_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DCMI_Private_Functions
STM32F4xx_StdPeriph_Driver » DCMI
+
+
+
+Collaboration diagram for DCMI_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Image capture functions
 Image capture functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___private___functions.map b/group___d_c_m_i___private___functions.map new file mode 100644 index 0000000..9d9e8ba --- /dev/null +++ b/group___d_c_m_i___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___d_c_m_i___private___functions.md5 b/group___d_c_m_i___private___functions.md5 new file mode 100644 index 0000000..e8d579d --- /dev/null +++ b/group___d_c_m_i___private___functions.md5 @@ -0,0 +1 @@ +bd2fbd27e2d8902bf96ffb1dd939a9ba \ No newline at end of file diff --git a/group___d_c_m_i___private___functions.png b/group___d_c_m_i___private___functions.png new file mode 100644 index 0000000..0192197 Binary files /dev/null and b/group___d_c_m_i___private___functions.png differ diff --git a/group___d_c_m_i___synchronization___mode.html b/group___d_c_m_i___synchronization___mode.html new file mode 100644 index 0000000..c06214c --- /dev/null +++ b/group___d_c_m_i___synchronization___mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: DCMI_Synchronization_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_Synchronization_Mode
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_Synchronization_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define DCMI_SynchroMode_Hardware   ((uint16_t)0x0000)
 
#define DCMI_SynchroMode_Embedded   ((uint16_t)0x0010)
 
#define IS_DCMI_SYNCHRO(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_SynchroMode_Embedded   ((uint16_t)0x0010)
+
+

Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow

+ +
+
+ +
+
+ + + + +
#define DCMI_SynchroMode_Hardware   ((uint16_t)0x0000)
+
+

Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_SYNCHRO( MODE)
+
+Value:
(((MODE) == DCMI_SynchroMode_Hardware) || \
+
((MODE) == DCMI_SynchroMode_Embedded))
+
DCMI_SynchroMode_Embedded
#define DCMI_SynchroMode_Embedded
Definition: stm32f4xx_dcmi.h:133
+
DCMI_SynchroMode_Hardware
#define DCMI_SynchroMode_Hardware
Definition: stm32f4xx_dcmi.h:130
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___synchronization___mode.map b/group___d_c_m_i___synchronization___mode.map new file mode 100644 index 0000000..97e11ec --- /dev/null +++ b/group___d_c_m_i___synchronization___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___synchronization___mode.md5 b/group___d_c_m_i___synchronization___mode.md5 new file mode 100644 index 0000000..9f5b474 --- /dev/null +++ b/group___d_c_m_i___synchronization___mode.md5 @@ -0,0 +1 @@ +54b4e3a0aa65b51dd88bca437f8d6199 \ No newline at end of file diff --git a/group___d_c_m_i___synchronization___mode.png b/group___d_c_m_i___synchronization___mode.png new file mode 100644 index 0000000..89108e0 Binary files /dev/null and b/group___d_c_m_i___synchronization___mode.png differ diff --git a/group___d_c_m_i___v_s_y_n_c___polarity.html b/group___d_c_m_i___v_s_y_n_c___polarity.html new file mode 100644 index 0000000..bbb1dc7 --- /dev/null +++ b/group___d_c_m_i___v_s_y_n_c___polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: DCMI_VSYNC_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_VSYNC_Polarity
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_VSYNC_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define DCMI_VSPolarity_Low   ((uint16_t)0x0000)
 
#define DCMI_VSPolarity_High   ((uint16_t)0x0080)
 
#define IS_DCMI_VSPOLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DCMI_VSPolarity_High   ((uint16_t)0x0080)
+
+

Vertical synchronization active High

+ +
+
+ +
+
+ + + + +
#define DCMI_VSPolarity_Low   ((uint16_t)0x0000)
+
+

Vertical synchronization active Low

+ +
+
+ +
+
+ + + + + + + + +
#define IS_DCMI_VSPOLARITY( POLARITY)
+
+Value:
(((POLARITY) == DCMI_VSPolarity_Low) || \
+
((POLARITY) == DCMI_VSPolarity_High))
+
DCMI_VSPolarity_High
#define DCMI_VSPolarity_High
Definition: stm32f4xx_dcmi.h:159
+
DCMI_VSPolarity_Low
#define DCMI_VSPolarity_Low
Definition: stm32f4xx_dcmi.h:158
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i___v_s_y_n_c___polarity.map b/group___d_c_m_i___v_s_y_n_c___polarity.map new file mode 100644 index 0000000..e7e2c95 --- /dev/null +++ b/group___d_c_m_i___v_s_y_n_c___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i___v_s_y_n_c___polarity.md5 b/group___d_c_m_i___v_s_y_n_c___polarity.md5 new file mode 100644 index 0000000..8cc9fc4 --- /dev/null +++ b/group___d_c_m_i___v_s_y_n_c___polarity.md5 @@ -0,0 +1 @@ +d11ce0d4759b0e3bf9319c769931c70f \ No newline at end of file diff --git a/group___d_c_m_i___v_s_y_n_c___polarity.png b/group___d_c_m_i___v_s_y_n_c___polarity.png new file mode 100644 index 0000000..40b933f Binary files /dev/null and b/group___d_c_m_i___v_s_y_n_c___polarity.png differ diff --git a/group___d_c_m_i__interrupt__sources.html b/group___d_c_m_i__interrupt__sources.html new file mode 100644 index 0000000..e0c98cd --- /dev/null +++ b/group___d_c_m_i__interrupt__sources.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: DCMI_interrupt_sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DCMI_interrupt_sources
STM32F4xx_StdPeriph_Driver » DCMI » DCMI_Exported_Constants
+
+
+
+Collaboration diagram for DCMI_interrupt_sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define DCMI_IT_FRAME   ((uint16_t)0x0001)
 
+#define DCMI_IT_OVF   ((uint16_t)0x0002)
 
+#define DCMI_IT_ERR   ((uint16_t)0x0004)
 
+#define DCMI_IT_VSYNC   ((uint16_t)0x0008)
 
+#define DCMI_IT_LINE   ((uint16_t)0x0010)
 
+#define IS_DCMI_CONFIG_IT(IT)   ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
 
#define IS_DCMI_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DCMI_GET_IT( IT)
+
+Value:
(((IT) == DCMI_IT_FRAME) || \
+
((IT) == DCMI_IT_OVF) || \
+
((IT) == DCMI_IT_ERR) || \
+
((IT) == DCMI_IT_VSYNC) || \
+
((IT) == DCMI_IT_LINE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_c_m_i__interrupt__sources.map b/group___d_c_m_i__interrupt__sources.map new file mode 100644 index 0000000..ec3a5ed --- /dev/null +++ b/group___d_c_m_i__interrupt__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_c_m_i__interrupt__sources.md5 b/group___d_c_m_i__interrupt__sources.md5 new file mode 100644 index 0000000..b9ebbd5 --- /dev/null +++ b/group___d_c_m_i__interrupt__sources.md5 @@ -0,0 +1 @@ +5cb759354ba82ffbcafb7e43d7ed2ea6 \ No newline at end of file diff --git a/group___d_c_m_i__interrupt__sources.png b/group___d_c_m_i__interrupt__sources.png new file mode 100644 index 0000000..68b2f21 Binary files /dev/null and b/group___d_c_m_i__interrupt__sources.png differ diff --git a/group___d_m_a.html b/group___d_m_a.html new file mode 100644 index 0000000..3f31fbf --- /dev/null +++ b/group___d_m_a.html @@ -0,0 +1,1060 @@ + + + + + + +discoverpixy: DMA + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
DMA
STM32F4xx_StdPeriph_Driver
+
+
+ +

DMA driver modules. +More...

+
+Collaboration diagram for DMA:
+
+
+ + +
+
+ + + + + + +

+Modules

 DMA_Exported_Constants
 
 DMA_Private_Functions
 
+ + + + +

+Classes

struct  DMA_InitTypeDef
 DMA Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define TRANSFER_IT_ENABLE_MASK
 
#define DMA_Stream0_IT_MASK
 
+#define DMA_Stream1_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 6)
 
+#define DMA_Stream2_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 16)
 
+#define DMA_Stream3_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 22)
 
+#define DMA_Stream4_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream5_IT_MASK   (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream6_IT_MASK   (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream7_IT_MASK   (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
 
+#define TRANSFER_IT_MASK   (uint32_t)0x0F3C0F3C
 
+#define HIGH_ISR_MASK   (uint32_t)0x20000000
 
+#define RESERVED_MASK   (uint32_t)0x0F7D0F7D
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA_DeInit (DMA_Stream_TypeDef *DMAy_Streamx)
 Deinitialize the DMAy Streamx registers to their default reset values. More...
 
void DMA_Init (DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
 Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure. More...
 
void DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
 Fills each DMA_InitStruct member with its default value. More...
 
void DMA_Cmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx. More...
 
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
 Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses). More...
 
void DMA_FlowControllerConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
 Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory). More...
 
void DMA_SetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
 Writes the number of data units to be transferred on the DMAy Streamx. More...
 
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the number of remaining data units in the current DMAy Streamx transfer. More...
 
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
 Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target. More...
 
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the double buffer mode for the selected DMA stream. More...
 
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
 Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing. More...
 
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current memory target used by double buffer transfer. More...
 
FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the status of EN bit for the specified DMAy Streamx. More...
 
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current DMAy Streamx FIFO filled level. More...
 
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Checks whether the specified DMAy Streamx flag is set or not. More...
 
void DMA_ClearFlag (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Clears the DMAy Streamx's pending flags. More...
 
void DMA_ITConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx interrupts. More...
 
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Checks whether the specified DMAy Streamx interrupt has occurred or not. More...
 
void DMA_ClearITPendingBit (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Clears the DMAy Streamx's interrupt pending bits. More...
 
+

Detailed Description

+

DMA driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DMA_Stream0_IT_MASK
+
+Value:
(uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
+
DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
+
DMA_LISR_TCIF0)
+
+
+
+ +
+
+ + + + +
#define TRANSFER_IT_ENABLE_MASK
+
+Value:
(uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
+
DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
+
+
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_ClearFlag (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FLAG 
)
+
+ +

Clears the DMAy Streamx's pending flags.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DMA_FLAG_TCIFx: Streamx transfer complete flag
    • +
  • DMA_FLAG_HTIFx: Streamx half transfer complete flag
    • +
  • DMA_FLAG_TEIFx: Streamx transfer error flag
    • +
  • DMA_FLAG_DMEIFx: Streamx direct mode error flag
    • +
  • DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_ClearITPendingBit (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT 
)
+
+ +

Clears the DMAy Streamx's interrupt pending bits.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DMA_IT_TCIFx: Streamx transfer complete interrupt
    • +
  • DMA_IT_HTIFx: Streamx half transfer complete interrupt
    • +
  • DMA_IT_TEIFx: Streamx transfer error interrupt
    • +
  • DMA_IT_DMEIFx: Streamx direct mode error interrupt
    • +
  • DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_Cmd (DMA_Stream_TypeDef * DMAy_Streamx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMAy Streamx.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
NewStatenew state of the DMAy Streamx. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
This function may be used to perform Pause-Resume operation. When a transfer is ongoing, calling this function to disable the Stream will cause the transfer to be paused. All configuration registers and the number of remaining data will be preserved. When calling again this function to re-enable the Stream, the transfer will be resumed from the point where it was paused.
+
+After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA_DeInit (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Deinitialize the DMAy Streamx registers to their default reset values.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef * DMAy_Streamx,
FunctionalState NewState 
)
+
+ +

Enables or disables the double buffer mode for the selected DMA stream.

+
Note
This function can be called only when the DMA Stream is disabled.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
NewStatenew state of the DMAy Streamx double buffer mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t Memory1BaseAddr,
uint32_t DMA_CurrentMemory 
)
+
+ +

Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
Memory1BaseAddrthe base address of the second buffer (Memory 1)
DMA_CurrentMemoryspecifies which memory will be first buffer for the transactions when the Stream will be enabled. This parameter can be one of the following values:
    +
  • DMA_Memory_0: Memory 0 is the current buffer.
    • +
  • DMA_Memory_1: Memory 1 is the current buffer.
    • +
+
+
+
+
Note
Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_FlowControllerConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FlowCtrl 
)
+
+ +

Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory).

+
Note
Before enabling this feature, check if the used peripheral supports the Flow Controller mode or not.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FlowCtrlspecifies the DMA flow controller. This parameter can be one of the following values:
    +
  • DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is the DMA controller.
    • +
  • DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller is the peripheral.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the status of EN bit for the specified DMAy Streamx.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Note
After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
+
Return values
+ + +
Currentstate of the DMAy Streamx (ENABLE or DISABLE).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the number of remaining data units in the current DMAy Streamx transfer.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
Thenumber of remaining data units in the current DMAy Streamx transfer.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the current memory target used by double buffer transfer.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
Thememory target number: 0 for Memory0 or 1 for Memory1.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the current DMAy Streamx FIFO filled level.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
TheFIFO filling state.
    +
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
    • +
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
    • +
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
    • +
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
    • +
  • DMA_FIFOStatus_Empty: when FIFO is empty
    • +
  • DMA_FIFOStatus_Full: when FIFO is full
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FLAG 
)
+
+ +

Checks whether the specified DMAy Streamx flag is set or not.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DMA_FLAG_TCIFx: Streamx transfer complete flag
    • +
  • DMA_FLAG_HTIFx: Streamx half transfer complete flag
    • +
  • DMA_FLAG_TEIFx: Streamx transfer error flag
    • +
  • DMA_FLAG_DMEIFx: Streamx direct mode error flag
    • +
  • DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT 
)
+
+ +

Checks whether the specified DMAy Streamx interrupt has occurred or not.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt source to check. This parameter can be one of the following values:
    +
  • DMA_IT_TCIFx: Streamx transfer complete interrupt
    • +
  • DMA_IT_HTIFx: Streamx half transfer complete interrupt
    • +
  • DMA_IT_TEIFx: Streamx transfer error interrupt
    • +
  • DMA_IT_DMEIFx: Streamx direct mode error interrupt
    • +
  • DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_Init (DMA_Stream_TypeDef * DMAy_Streamx,
DMA_InitTypeDef * DMA_InitStruct 
)
+
+ +

Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure.

+
Note
Before calling this function, it is recommended to check that the Stream is actually disabled using the function DMA_GetCmdStatus().
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_InitStructpointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Stream.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_ITConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMAy Streamx interrupts.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DMA_IT_TC: Transfer complete interrupt mask
    • +
  • DMA_IT_HT: Half transfer complete interrupt mask
    • +
  • DMA_IT_TE: Transfer error interrupt mask
    • +
  • DMA_IT_FE: FIFO error interrupt mask
    • +
+
NewStatenew state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t MemoryBaseAddr,
uint32_t DMA_MemoryTarget 
)
+
+ +

Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
MemoryBaseAddrThe base address of the target memory buffer
DMA_MemoryTargetNext memory target to be used. This parameter can be one of the following values:
    +
  • DMA_Memory_0: To use the memory address 0
    • +
  • DMA_Memory_1: To use the memory address 1
    • +
+
+
+
+
Note
It is not allowed to modify the Base Address of a target Memory when this target is involved in the current transfer. ie. If the DMA Stream is currently transferring to/from Memory 1, then it not possible to modify Base address of Memory 1, but it is possible to modify Base address of Memory 0. To know which Memory is currently used, you can use the function DMA_GetCurrentMemoryTarget().
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_Pincos 
)
+
+ +

Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses).

+
Note
This function has no effect if the Peripheral Increment mode is disabled.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_Pincosspecifies the Peripheral increment offset size. This parameter can be one of the following values:
    +
  • DMA_PINCOS_Psize: Peripheral address increment is done accordingly to PSIZE parameter.
    • +
  • DMA_PINCOS_WordAligned: Peripheral address increment offset is fixed to 4 (32-bit aligned addresses).
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_SetCurrDataCounter (DMA_Stream_TypeDef * DMAy_Streamx,
uint16_t Counter 
)
+
+ +

Writes the number of data units to be transferred on the DMAy Streamx.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
CounterNumber of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
+
+
+
Note
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
+
+If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
+
+If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
+
+In Memory-to-Memory transfer mode, the memory buffer pointed by DMAy_SxPAR register is considered as Peripheral.
+
Return values
+ + +
Thenumber of remaining data units in the current DMAy Streamx transfer.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA_StructInit (DMA_InitTypeDef * DMA_InitStruct)
+
+ +

Fills each DMA_InitStruct member with its default value.

+
Parameters
+ + +
DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a.map b/group___d_m_a.map new file mode 100644 index 0000000..744dac6 --- /dev/null +++ b/group___d_m_a.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_m_a.md5 b/group___d_m_a.md5 new file mode 100644 index 0000000..b90652f --- /dev/null +++ b/group___d_m_a.md5 @@ -0,0 +1 @@ +d9b21d6c063a3f4dc1587b9e10ddb6e5 \ No newline at end of file diff --git a/group___d_m_a.png b/group___d_m_a.png new file mode 100644 index 0000000..f38c22c Binary files /dev/null and b/group___d_m_a.png differ diff --git a/group___d_m_a2_d.html b/group___d_m_a2_d.html new file mode 100644 index 0000000..2ca74c8 --- /dev/null +++ b/group___d_m_a2_d.html @@ -0,0 +1,835 @@ + + + + + + +discoverpixy: DMA2D + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
DMA2D
STM32F4xx_StdPeriph_Driver
+
+
+ +

DMA2D driver modules. +More...

+
+Collaboration diagram for DMA2D:
+
+
+ + +
+
+ + + + + + +

+Modules

 DMA2D_Exported_Constants
 
 DMA2D_Private_Functions
 
+ + + + + + + + +

+Classes

struct  DMA2D_InitTypeDef
 DMA2D Init structure definition. More...
 
struct  DMA2D_FG_InitTypeDef
 
struct  DMA2D_BG_InitTypeDef
 
+ + + + + + + +

+Macros

+#define CR_MASK   ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */
 
+#define PFCCR_MASK   ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */
 
+#define DEAD_MASK   ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA2D_DeInit (void)
 Deinitializes the DMA2D peripheral registers to their default reset values. More...
 
void DMA2D_Init (DMA2D_InitTypeDef *DMA2D_InitStruct)
 Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct. More...
 
+void DMA2D_StructInit (DMA2D_InitTypeDef *DMA2D_InitStruct)
 
void DMA2D_StartTransfer (void)
 Start the DMA2D transfer. More...
 
void DMA2D_AbortTransfer (void)
 Aboart the DMA2D transfer. More...
 
void DMA2D_Suspend (FunctionalState NewState)
 Stop or continue the DMA2D transfer. More...
 
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Configures the Foreground according to the specified parameters in the DMA2D_FGStruct. More...
 
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Fills each DMA2D_FGStruct member with its default value. More...
 
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Configures the Background according to the specified parameters in the DMA2D_BGStruct. More...
 
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Fills each DMA2D_BGStruct member with its default value. More...
 
void DMA2D_FGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_BGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime, FunctionalState NewState)
 Configures the DMA2D dead time. More...
 
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
 Define the configuration of the line watermark . More...
 
void DMA2D_ITConfig (uint32_t DMA2D_IT, FunctionalState NewState)
 Enables or disables the specified DMA2D's interrupts. More...
 
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
 Checks whether the specified DMA2D's flag is set or not. More...
 
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
 Clears the DMA2D's pending flags. More...
 
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
 Checks whether the specified DMA2D's interrupt has occurred or not. More...
 
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
 Clears the DMA2D's interrupt pending bits. More...
 
+

Detailed Description

+

DMA2D driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void DMA2D_AbortTransfer (void )
+
+ +

Aboart the DMA2D transfer.

+
Parameters
+ + +
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef * DMA2D_BG_InitStruct)
+
+ +

Fills each DMA2D_BGStruct member with its default value.

+
Parameters
+ + +
DMA2D_BGStructpointer to a DMA2D_BGTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the DMA2D background memory address

+

< Initialize the DMA2D background offset

+

< Initialize the DMA2D background color mode

+

< Initialize the DMA2D background CLUT color mode

+

< Initialize the DMA2D background CLUT size

+

< Initialize the DMA2D background alpha mode

+

< Initialize the DMA2D background alpha value

+

< Initialize the DMA2D background blue value

+

< Initialize the DMA2D background green value

+

< Initialize the DMA2D background red value

+

< Initialize the DMA2D background CLUT memory address

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef * DMA2D_BG_InitStruct)
+
+ +

Configures the Background according to the specified parameters in the DMA2D_BGStruct.

+
Note
This function can be used only when the transfer is disabled.
+
Parameters
+ + +
DMA2D_BGStructpointer to a DMA2D_BGTypeDef structure that contains the configuration information for the specified Background.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BGStart (FunctionalState NewState)
+
+ +

Start the automatic loading of the CLUT or abort the transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
+
+ +

Clears the DMA2D's pending flags.

+
Parameters
+ + +
DMA2D_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DMA2D_FLAG_CE: Configuration Error Interrupt flag.
    • +
  • DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
    • +
  • DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
    • +
  • DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
    • +
  • DMA2D_FLAG_TC: Transfer Complete interrupt flag.
    • +
  • DMA2D_FLAG_TE: Transfer Error interrupt flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
+
+ +

Clears the DMA2D's interrupt pending bits.

+
Parameters
+ + +
DMA2D_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime,
FunctionalState NewState 
)
+
+ +

Configures the DMA2D dead time.

+
Parameters
+ + +
DMA2D_DeadTimespecifies the DMA2D dead time. This parameter can be one of the following values:
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_DeInit (void )
+
+ +

Deinitializes the DMA2D peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef * DMA2D_FG_InitStruct)
+
+ +

Fills each DMA2D_FGStruct member with its default value.

+
Parameters
+ + +
DMA2D_FGStructpointer to a DMA2D_FGTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the DMA2D foreground memory address

+

< Initialize the DMA2D foreground offset

+

< Initialize the DMA2D foreground color mode

+

< Initialize the DMA2D foreground CLUT color mode

+

< Initialize the DMA2D foreground CLUT size

+

< Initialize the DMA2D foreground alpha mode

+

< Initialize the DMA2D foreground alpha value

+

< Initialize the DMA2D foreground blue value

+

< Initialize the DMA2D foreground green value

+

< Initialize the DMA2D foreground red value

+

< Initialize the DMA2D foreground CLUT memory address

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef * DMA2D_FG_InitStruct)
+
+ +

Configures the Foreground according to the specified parameters in the DMA2D_FGStruct.

+
Note
This function can be used only when the transfer is disabled.
+
Parameters
+ + +
DMA2D_FGStructpointer to a DMA2D_FGTypeDef structure that contains the configuration information for the specified Background.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FGStart (FunctionalState NewState)
+
+ +

Start the automatic loading of the CLUT or abort the transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
+
+ +

Checks whether the specified DMA2D's flag is set or not.

+
Parameters
+ + +
DMA2D_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DMA2D_FLAG_CE: Configuration Error Interrupt flag.
    • +
  • DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
    • +
  • DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
    • +
  • DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
    • +
  • DMA2D_FLAG_TC: Transfer Complete interrupt flag.
    • +
  • DMA2D_FLAG_TE: Transfer Error interrupt flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA2D_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
+
+ +

Checks whether the specified DMA2D's interrupt has occurred or not.

+
Parameters
+ + +
DMA2D_ITspecifies the DMA2D interrupts sources to check. This parameter can be one of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt Enable.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt enable.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt enable.
    • +
+
+
+
+
Return values
+ + +
Thenew state of the DMA2D_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_Init (DMA2D_InitTypeDef * DMA2D_InitStruct)
+
+ +

Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct.

+
Note
This function can be used only when the DMA2D is disabled.
+
Parameters
+ + +
DMA2D_InitStructpointer to a DMA2D_InitTypeDef structure that contains the configuration information for the specified DMA2D peripheral.
+
+
+
Return values
+ + +
None
+
+
+

Fills each DMA2D_InitStruct member with its default value.

Parameters
+ + +
DMA2D_InitStructpointer to a DMA2D_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA2D_ITConfig (uint32_t DMA2D_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMA2D's interrupts.

+
Parameters
+ + + +
DMA2D_ITspecifies the DMA2D interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt Enable.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt enable.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt enable.
    • +
+
NewStatenew state of the specified DMA2D interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
+
+ +

Define the configuration of the line watermark .

+
Parameters
+ + +
DMA2D_LWatermarkConfigLine Watermark configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_StartTransfer (void )
+
+ +

Start the DMA2D transfer.

+
Parameters
+ + +
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_Suspend (FunctionalState NewState)
+
+ +

Stop or continue the DMA2D transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d.map b/group___d_m_a2_d.map new file mode 100644 index 0000000..31bd96b --- /dev/null +++ b/group___d_m_a2_d.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_m_a2_d.md5 b/group___d_m_a2_d.md5 new file mode 100644 index 0000000..0e0c0fc --- /dev/null +++ b/group___d_m_a2_d.md5 @@ -0,0 +1 @@ +87c47ca59449ed877ceee549207b3ab6 \ No newline at end of file diff --git a/group___d_m_a2_d.png b/group___d_m_a2_d.png new file mode 100644 index 0000000..79a9658 Binary files /dev/null and b/group___d_m_a2_d.png differ diff --git a/group___d_m_a2_d___c_m_o_d_e.html b/group___d_m_a2_d___c_m_o_d_e.html new file mode 100644 index 0000000..a6abe0c --- /dev/null +++ b/group___d_m_a2_d___c_m_o_d_e.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: DMA2D_CMODE + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_CMODE
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_CMODE:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define DMA2D_ARGB8888   ((uint32_t)0x00000000)
 
+#define DMA2D_RGB888   ((uint32_t)0x00000001)
 
+#define DMA2D_RGB565   ((uint32_t)0x00000002)
 
+#define DMA2D_ARGB1555   ((uint32_t)0x00000003)
 
+#define DMA2D_ARGB4444   ((uint32_t)0x00000004)
 
#define IS_DMA2D_CMODE(MODE_ARGB)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_CMODE( MODE_ARGB)
+
+Value:
(((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+
((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+
((MODE_ARGB) == DMA2D_ARGB4444))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___c_m_o_d_e.map b/group___d_m_a2_d___c_m_o_d_e.map new file mode 100644 index 0000000..fdb2f9e --- /dev/null +++ b/group___d_m_a2_d___c_m_o_d_e.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___c_m_o_d_e.md5 b/group___d_m_a2_d___c_m_o_d_e.md5 new file mode 100644 index 0000000..57b48b1 --- /dev/null +++ b/group___d_m_a2_d___c_m_o_d_e.md5 @@ -0,0 +1 @@ +1dc450e1d589d90c022c5628476f3790 \ No newline at end of file diff --git a/group___d_m_a2_d___c_m_o_d_e.png b/group___d_m_a2_d___c_m_o_d_e.png new file mode 100644 index 0000000..7047d94 Binary files /dev/null and b/group___d_m_a2_d___c_m_o_d_e.png differ diff --git a/group___d_m_a2_d___dead_time.html b/group___d_m_a2_d___dead_time.html new file mode 100644 index 0000000..6ead257 --- /dev/null +++ b/group___d_m_a2_d___dead_time.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: DMA2D_DeadTime + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_DeadTime
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_DeadTime:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DEADTIME   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_DEAD_TIME(DEAD_TIME)   ((DEAD_TIME) <= DEADTIME)
 
+#define LINE_WATERMARK   DMA2D_LWR_LW
 
+#define IS_DMA2D_LineWatermark(LineWatermark)   ((LineWatermark) <= LINE_WATERMARK)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___dead_time.map b/group___d_m_a2_d___dead_time.map new file mode 100644 index 0000000..8f76525 --- /dev/null +++ b/group___d_m_a2_d___dead_time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___dead_time.md5 b/group___d_m_a2_d___dead_time.md5 new file mode 100644 index 0000000..e202048 --- /dev/null +++ b/group___d_m_a2_d___dead_time.md5 @@ -0,0 +1 @@ +92ed34990e068afd3c0c3b326bbc88a0 \ No newline at end of file diff --git a/group___d_m_a2_d___dead_time.png b/group___d_m_a2_d___dead_time.png new file mode 100644 index 0000000..0cf5d07 Binary files /dev/null and b/group___d_m_a2_d___dead_time.png differ diff --git a/group___d_m_a2_d___exported___constants.html b/group___d_m_a2_d___exported___constants.html new file mode 100644 index 0000000..bca5149 --- /dev/null +++ b/group___d_m_a2_d___exported___constants.html @@ -0,0 +1,196 @@ + + + + + + +discoverpixy: DMA2D_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DMA2D_Exported_Constants
STM32F4xx_StdPeriph_Driver » DMA2D
+
+
+
+Collaboration diagram for DMA2D_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 DMA2D_MODE
 
 DMA2D_CMODE
 
 DMA2D_OUTPUT_COLOR
 
 DMA2D_OUTPUT_OFFSET
 
 DMA2D_SIZE
 
 DMA2D_OFFSET
 
 DMA2D_FGCM
 
 DMA2D_FG_CLUT_CM
 
 DMA2D_FG_COLOR_VALUE
 
 DMA2D_Interrupts
 
 DMA2D_Flag
 
 DMA2D_DeadTime
 
#define NO_MODIF_ALPHA_VALUE   ((uint32_t)0x00000000)
 
+#define REPLACE_ALPHA_VALUE   ((uint32_t)0x00000001)
 
+#define COMBINE_ALPHA_VALUE   ((uint32_t)0x00000002)
 
#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE)
 
#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_BG_ALPHA_MODE( BG_ALPHA_MODE)
+
+Value:
(((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
+
((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+
((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
NO_MODIF_ALPHA_VALUE
#define NO_MODIF_ALPHA_VALUE
Definition: stm32f4xx_dma2d.h:356
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DMA2D_FG_ALPHA_MODE( FG_ALPHA_MODE)
+
+Value:
(((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
+
((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+
((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
NO_MODIF_ALPHA_VALUE
#define NO_MODIF_ALPHA_VALUE
Definition: stm32f4xx_dma2d.h:356
+
+
+
+ +
+
+ + + + +
#define NO_MODIF_ALPHA_VALUE   ((uint32_t)0x00000000)
+
+

DMA2D_FGPFC_ALPHA_MODE

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___exported___constants.map b/group___d_m_a2_d___exported___constants.map new file mode 100644 index 0000000..f7d3880 --- /dev/null +++ b/group___d_m_a2_d___exported___constants.map @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/group___d_m_a2_d___exported___constants.md5 b/group___d_m_a2_d___exported___constants.md5 new file mode 100644 index 0000000..1b3fb2b --- /dev/null +++ b/group___d_m_a2_d___exported___constants.md5 @@ -0,0 +1 @@ +60fe4cca89f6bc88dd76518027ed43bf \ No newline at end of file diff --git a/group___d_m_a2_d___exported___constants.png b/group___d_m_a2_d___exported___constants.png new file mode 100644 index 0000000..5f573e7 Binary files /dev/null and b/group___d_m_a2_d___exported___constants.png differ diff --git a/group___d_m_a2_d___f_g___c_l_u_t___c_m.html b/group___d_m_a2_d___f_g___c_l_u_t___c_m.html new file mode 100644 index 0000000..d120c23 --- /dev/null +++ b/group___d_m_a2_d___f_g___c_l_u_t___c_m.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: DMA2D_FG_CLUT_CM + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_FG_CLUT_CM
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_FG_CLUT_CM:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define CLUT_CM_ARGB8888   ((uint32_t)0x00000000)
 
+#define CLUT_CM_RGB888   ((uint32_t)0x00000001)
 
+#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM)   (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
 
+#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM)   (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___f_g___c_l_u_t___c_m.map b/group___d_m_a2_d___f_g___c_l_u_t___c_m.map new file mode 100644 index 0000000..9349d69 --- /dev/null +++ b/group___d_m_a2_d___f_g___c_l_u_t___c_m.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___f_g___c_l_u_t___c_m.md5 b/group___d_m_a2_d___f_g___c_l_u_t___c_m.md5 new file mode 100644 index 0000000..7d49c7e --- /dev/null +++ b/group___d_m_a2_d___f_g___c_l_u_t___c_m.md5 @@ -0,0 +1 @@ +93e2f0a0050a751e5554e3c52c9aed02 \ No newline at end of file diff --git a/group___d_m_a2_d___f_g___c_l_u_t___c_m.png b/group___d_m_a2_d___f_g___c_l_u_t___c_m.png new file mode 100644 index 0000000..e4c3dd0 Binary files /dev/null and b/group___d_m_a2_d___f_g___c_l_u_t___c_m.png differ diff --git a/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.html b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.html new file mode 100644 index 0000000..ec4c8b2 --- /dev/null +++ b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: DMA2D_FG_COLOR_VALUE + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_FG_COLOR_VALUE
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_FG_COLOR_VALUE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define COLOR_VALUE   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE)   ((FG_CLUT_SIZE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE)   ((FG_ALPHA_VALUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_BLUE(FGC_BLUE)   ((FGC_BLUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_GREEN(FGC_GREEN)   ((FGC_GREEN) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_RED(FGC_RED)   ((FGC_RED) <= COLOR_VALUE)
 
+#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE)   ((BG_CLUT_SIZE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE)   ((BG_ALPHA_VALUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_BLUE(BGC_BLUE)   ((BGC_BLUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_GREEN(BGC_GREEN)   ((BGC_GREEN) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_RED(BGC_RED)   ((BGC_RED) <= COLOR_VALUE)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.map b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.map new file mode 100644 index 0000000..28b8c20 --- /dev/null +++ b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.md5 b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.md5 new file mode 100644 index 0000000..b94e303 --- /dev/null +++ b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.md5 @@ -0,0 +1 @@ +e7a12dff28aec01fc616d89a8879de1a \ No newline at end of file diff --git a/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.png b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.png new file mode 100644 index 0000000..dd1d0c9 Binary files /dev/null and b/group___d_m_a2_d___f_g___c_o_l_o_r___v_a_l_u_e.png differ diff --git a/group___d_m_a2_d___f_g_c_m.html b/group___d_m_a2_d___f_g_c_m.html new file mode 100644 index 0000000..64fa5ab --- /dev/null +++ b/group___d_m_a2_d___f_g_c_m.html @@ -0,0 +1,188 @@ + + + + + + +discoverpixy: DMA2D_FGCM + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_FGCM
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_FGCM:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define CM_ARGB8888   ((uint32_t)0x00000000)
 
+#define CM_RGB888   ((uint32_t)0x00000001)
 
+#define CM_RGB565   ((uint32_t)0x00000002)
 
+#define CM_ARGB1555   ((uint32_t)0x00000003)
 
+#define CM_ARGB4444   ((uint32_t)0x00000004)
 
+#define CM_L8   ((uint32_t)0x00000005)
 
+#define CM_AL44   ((uint32_t)0x00000006)
 
+#define CM_AL88   ((uint32_t)0x00000007)
 
+#define CM_L4   ((uint32_t)0x00000008)
 
+#define CM_A8   ((uint32_t)0x00000009)
 
+#define CM_A4   ((uint32_t)0x0000000A)
 
#define IS_DMA2D_FGCM(FGCM)
 
#define IS_DMA2D_BGCM(BGCM)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_BGCM( BGCM)
+
+Value:
(((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
+
((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
+
((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
+
((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
+
((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
+
((BGCM) == CM_A4))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DMA2D_FGCM( FGCM)
+
+Value:
(((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
+
((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
+
((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
+
((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
+
((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
+
((FGCM) == CM_A4))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___f_g_c_m.map b/group___d_m_a2_d___f_g_c_m.map new file mode 100644 index 0000000..c1164a8 --- /dev/null +++ b/group___d_m_a2_d___f_g_c_m.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___f_g_c_m.md5 b/group___d_m_a2_d___f_g_c_m.md5 new file mode 100644 index 0000000..e8a9fa8 --- /dev/null +++ b/group___d_m_a2_d___f_g_c_m.md5 @@ -0,0 +1 @@ +8cf00a1c4e752bd13f5c61de8c075917 \ No newline at end of file diff --git a/group___d_m_a2_d___f_g_c_m.png b/group___d_m_a2_d___f_g_c_m.png new file mode 100644 index 0000000..0384012 Binary files /dev/null and b/group___d_m_a2_d___f_g_c_m.png differ diff --git a/group___d_m_a2_d___flag.html b/group___d_m_a2_d___flag.html new file mode 100644 index 0000000..7eb977a --- /dev/null +++ b/group___d_m_a2_d___flag.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: DMA2D_Flag + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_Flag
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_Flag:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define DMA2D_FLAG_CE   DMA2D_ISR_CEIF
 
+#define DMA2D_FLAG_CTC   DMA2D_ISR_CTCIF
 
+#define DMA2D_FLAG_CAE   DMA2D_ISR_CAEIF
 
+#define DMA2D_FLAG_TW   DMA2D_ISR_TWIF
 
+#define DMA2D_FLAG_TC   DMA2D_ISR_TCIF
 
+#define DMA2D_FLAG_TE   DMA2D_ISR_TEIF
 
#define IS_DMA2D_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___flag.map b/group___d_m_a2_d___flag.map new file mode 100644 index 0000000..5724ee5 --- /dev/null +++ b/group___d_m_a2_d___flag.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___flag.md5 b/group___d_m_a2_d___flag.md5 new file mode 100644 index 0000000..d39515f --- /dev/null +++ b/group___d_m_a2_d___flag.md5 @@ -0,0 +1 @@ +59f3fa765c86922c1c8ab5f0a1dfcd21 \ No newline at end of file diff --git a/group___d_m_a2_d___flag.png b/group___d_m_a2_d___flag.png new file mode 100644 index 0000000..ca3b00e Binary files /dev/null and b/group___d_m_a2_d___flag.png differ diff --git a/group___d_m_a2_d___group1.html b/group___d_m_a2_d___group1.html new file mode 100644 index 0000000..5dfec30 --- /dev/null +++ b/group___d_m_a2_d___group1.html @@ -0,0 +1,595 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA2D_DeInit (void)
 Deinitializes the DMA2D peripheral registers to their default reset values. More...
 
void DMA2D_Init (DMA2D_InitTypeDef *DMA2D_InitStruct)
 Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct. More...
 
+void DMA2D_StructInit (DMA2D_InitTypeDef *DMA2D_InitStruct)
 
void DMA2D_StartTransfer (void)
 Start the DMA2D transfer. More...
 
void DMA2D_AbortTransfer (void)
 Aboart the DMA2D transfer. More...
 
void DMA2D_Suspend (FunctionalState NewState)
 Stop or continue the DMA2D transfer. More...
 
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Configures the Foreground according to the specified parameters in the DMA2D_FGStruct. More...
 
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Fills each DMA2D_FGStruct member with its default value. More...
 
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Configures the Background according to the specified parameters in the DMA2D_BGStruct. More...
 
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Fills each DMA2D_BGStruct member with its default value. More...
 
void DMA2D_FGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_BGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime, FunctionalState NewState)
 Configures the DMA2D dead time. More...
 
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
 Define the configuration of the line watermark . More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DMA2D
+      (+) Start/Abort/Suspend Transfer
+      (+) Initialize, configure and set Foreground and background
+      (+) configure and enable DeadTime
+      (+) configure lineWatermark

Function Documentation

+ +
+
+ + + + + + + + +
void DMA2D_AbortTransfer (void )
+
+ +

Aboart the DMA2D transfer.

+
Parameters
+ + +
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef * DMA2D_BG_InitStruct)
+
+ +

Fills each DMA2D_BGStruct member with its default value.

+
Parameters
+ + +
DMA2D_BGStructpointer to a DMA2D_BGTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the DMA2D background memory address

+

< Initialize the DMA2D background offset

+

< Initialize the DMA2D background color mode

+

< Initialize the DMA2D background CLUT color mode

+

< Initialize the DMA2D background CLUT size

+

< Initialize the DMA2D background alpha mode

+

< Initialize the DMA2D background alpha value

+

< Initialize the DMA2D background blue value

+

< Initialize the DMA2D background green value

+

< Initialize the DMA2D background red value

+

< Initialize the DMA2D background CLUT memory address

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef * DMA2D_BG_InitStruct)
+
+ +

Configures the Background according to the specified parameters in the DMA2D_BGStruct.

+
Note
This function can be used only when the transfer is disabled.
+
Parameters
+ + +
DMA2D_BGStructpointer to a DMA2D_BGTypeDef structure that contains the configuration information for the specified Background.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_BGStart (FunctionalState NewState)
+
+ +

Start the automatic loading of the CLUT or abort the transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime,
FunctionalState NewState 
)
+
+ +

Configures the DMA2D dead time.

+
Parameters
+ + +
DMA2D_DeadTimespecifies the DMA2D dead time. This parameter can be one of the following values:
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_DeInit (void )
+
+ +

Deinitializes the DMA2D peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef * DMA2D_FG_InitStruct)
+
+ +

Fills each DMA2D_FGStruct member with its default value.

+
Parameters
+ + +
DMA2D_FGStructpointer to a DMA2D_FGTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the DMA2D foreground memory address

+

< Initialize the DMA2D foreground offset

+

< Initialize the DMA2D foreground color mode

+

< Initialize the DMA2D foreground CLUT color mode

+

< Initialize the DMA2D foreground CLUT size

+

< Initialize the DMA2D foreground alpha mode

+

< Initialize the DMA2D foreground alpha value

+

< Initialize the DMA2D foreground blue value

+

< Initialize the DMA2D foreground green value

+

< Initialize the DMA2D foreground red value

+

< Initialize the DMA2D foreground CLUT memory address

+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef * DMA2D_FG_InitStruct)
+
+ +

Configures the Foreground according to the specified parameters in the DMA2D_FGStruct.

+
Note
This function can be used only when the transfer is disabled.
+
Parameters
+ + +
DMA2D_FGStructpointer to a DMA2D_FGTypeDef structure that contains the configuration information for the specified Background.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_FGStart (FunctionalState NewState)
+
+ +

Start the automatic loading of the CLUT or abort the transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_Init (DMA2D_InitTypeDef * DMA2D_InitStruct)
+
+ +

Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct.

+
Note
This function can be used only when the DMA2D is disabled.
+
Parameters
+ + +
DMA2D_InitStructpointer to a DMA2D_InitTypeDef structure that contains the configuration information for the specified DMA2D peripheral.
+
+
+
Return values
+ + +
None
+
+
+

Fills each DMA2D_InitStruct member with its default value.

Parameters
+ + +
DMA2D_InitStructpointer to a DMA2D_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
+
+ +

Define the configuration of the line watermark .

+
Parameters
+ + +
DMA2D_LWatermarkConfigLine Watermark configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_StartTransfer (void )
+
+ +

Start the DMA2D transfer.

+
Parameters
+ + +
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_Suspend (FunctionalState NewState)
+
+ +

Stop or continue the DMA2D transfer.

+
Parameters
+ + +
NewStatenew state of the DMA2D peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___group1.map b/group___d_m_a2_d___group1.map new file mode 100644 index 0000000..345a6e4 --- /dev/null +++ b/group___d_m_a2_d___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___group1.md5 b/group___d_m_a2_d___group1.md5 new file mode 100644 index 0000000..6b5180a --- /dev/null +++ b/group___d_m_a2_d___group1.md5 @@ -0,0 +1 @@ +621ded2770bf23e2b26dafda52e7d224 \ No newline at end of file diff --git a/group___d_m_a2_d___group1.png b/group___d_m_a2_d___group1.png new file mode 100644 index 0000000..211f220 Binary files /dev/null and b/group___d_m_a2_d___group1.png differ diff --git a/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map new file mode 100644 index 0000000..1cef2e3 --- /dev/null +++ b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 new file mode 100644 index 0000000..2aa64bc --- /dev/null +++ b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 @@ -0,0 +1 @@ +bbae5dbed5c98408e4f7c563ea7dcb43 \ No newline at end of file diff --git a/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png new file mode 100644 index 0000000..117d71a Binary files /dev/null and b/group___d_m_a2_d___group1_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png differ diff --git a/group___d_m_a2_d___group2.html b/group___d_m_a2_d___group2.html new file mode 100644 index 0000000..4d02011 --- /dev/null +++ b/group___d_m_a2_d___group2.html @@ -0,0 +1,359 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void DMA2D_ITConfig (uint32_t DMA2D_IT, FunctionalState NewState)
 Enables or disables the specified DMA2D's interrupts. More...
 
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
 Checks whether the specified DMA2D's flag is set or not. More...
 
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
 Clears the DMA2D's pending flags. More...
 
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
 Checks whether the specified DMA2D's interrupt has occurred or not. More...
 
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
 Clears the DMA2D's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+    [..] This section provides functions allowing to configure the DMA2D 
+         Interrupts and to get the status and clear flags and Interrupts 
+         pending bits.
+    [..] The DMA2D provides 6 Interrupts sources and 6 Flags
+    
+    *** Flags ***
+    =============
+    [..]
+      (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag
+      (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag
+      (+) DMA2D_FLAG_TW:  Transfer Watermark Interrupt flag
+      (+) DMA2D_FLAG_TC:  Transfer Complete interrupt flag
+      (+) DMA2D_FLAG_TE:  Transfer Error interrupt flag
+      (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag
+      
+    *** Interrupts ***
+    ==================
+    [..]
+      (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong 
+                       configuration is detected
+      (+) DMA2D_IT_CAE: CLUT Access Error Interrupt
+      (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when 
+                       the programmed watermark is reached 
+      (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying 
+                       to access the CLUT while a CLUT loading or a DMA2D1 transfer 
+                       is on going       
+      (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt 
+      (+) DMA2D_IT_TC: Transfer Complete interrupt         
+

Function Documentation

+ +
+
+ + + + + + + + +
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
+
+ +

Clears the DMA2D's pending flags.

+
Parameters
+ + +
DMA2D_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DMA2D_FLAG_CE: Configuration Error Interrupt flag.
    • +
  • DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
    • +
  • DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
    • +
  • DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
    • +
  • DMA2D_FLAG_TC: Transfer Complete interrupt flag.
    • +
  • DMA2D_FLAG_TE: Transfer Error interrupt flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
+
+ +

Clears the DMA2D's interrupt pending bits.

+
Parameters
+ + +
DMA2D_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
+
+ +

Checks whether the specified DMA2D's flag is set or not.

+
Parameters
+ + +
DMA2D_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DMA2D_FLAG_CE: Configuration Error Interrupt flag.
    • +
  • DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
    • +
  • DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
    • +
  • DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
    • +
  • DMA2D_FLAG_TC: Transfer Complete interrupt flag.
    • +
  • DMA2D_FLAG_TE: Transfer Error interrupt flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA2D_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
+
+ +

Checks whether the specified DMA2D's interrupt has occurred or not.

+
Parameters
+ + +
DMA2D_ITspecifies the DMA2D interrupts sources to check. This parameter can be one of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt Enable.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt enable.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt enable.
    • +
+
+
+
+
Return values
+ + +
Thenew state of the DMA2D_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA2D_ITConfig (uint32_t DMA2D_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMA2D's interrupts.

+
Parameters
+ + + +
DMA2D_ITspecifies the DMA2D interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DMA2D_IT_CE: Configuration Error Interrupt Enable.
    • +
  • DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
    • +
  • DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
    • +
  • DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
    • +
  • DMA2D_IT_TC: Transfer Complete interrupt enable.
    • +
  • DMA2D_IT_TE: Transfer Error interrupt enable.
    • +
+
NewStatenew state of the specified DMA2D interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___group2.map b/group___d_m_a2_d___group2.map new file mode 100644 index 0000000..4d03ee0 --- /dev/null +++ b/group___d_m_a2_d___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___group2.md5 b/group___d_m_a2_d___group2.md5 new file mode 100644 index 0000000..474bd36 --- /dev/null +++ b/group___d_m_a2_d___group2.md5 @@ -0,0 +1 @@ +1ba829aad40fc4d39f412fe7e156c0a5 \ No newline at end of file diff --git a/group___d_m_a2_d___group2.png b/group___d_m_a2_d___group2.png new file mode 100644 index 0000000..2fe5c31 Binary files /dev/null and b/group___d_m_a2_d___group2.png differ diff --git a/group___d_m_a2_d___interrupts.html b/group___d_m_a2_d___interrupts.html new file mode 100644 index 0000000..f7bfc1e --- /dev/null +++ b/group___d_m_a2_d___interrupts.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: DMA2D_Interrupts + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_Interrupts
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_Interrupts:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define DMA2D_IT_CE   DMA2D_CR_CEIE
 
+#define DMA2D_IT_CTC   DMA2D_CR_CTCIE
 
+#define DMA2D_IT_CAE   DMA2D_CR_CAEIE
 
+#define DMA2D_IT_TW   DMA2D_CR_TWIE
 
+#define DMA2D_IT_TC   DMA2D_CR_TCIE
 
+#define DMA2D_IT_TE   DMA2D_CR_TEIE
 
#define IS_DMA2D_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_IT( IT)
+
+Value:
(((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___interrupts.map b/group___d_m_a2_d___interrupts.map new file mode 100644 index 0000000..8b2bd28 --- /dev/null +++ b/group___d_m_a2_d___interrupts.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___interrupts.md5 b/group___d_m_a2_d___interrupts.md5 new file mode 100644 index 0000000..e257a96 --- /dev/null +++ b/group___d_m_a2_d___interrupts.md5 @@ -0,0 +1 @@ +cf8b28e76a8fcbdbd60a83389ce00b8b \ No newline at end of file diff --git a/group___d_m_a2_d___interrupts.png b/group___d_m_a2_d___interrupts.png new file mode 100644 index 0000000..3361817 Binary files /dev/null and b/group___d_m_a2_d___interrupts.png differ diff --git a/group___d_m_a2_d___m_o_d_e.html b/group___d_m_a2_d___m_o_d_e.html new file mode 100644 index 0000000..859ab4f --- /dev/null +++ b/group___d_m_a2_d___m_o_d_e.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: DMA2D_MODE + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_MODE
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_MODE:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA2D_M2M   ((uint32_t)0x00000000)
 
+#define DMA2D_M2M_PFC   ((uint32_t)0x00010000)
 
+#define DMA2D_M2M_BLEND   ((uint32_t)0x00020000)
 
+#define DMA2D_R2M   ((uint32_t)0x00030000)
 
#define IS_DMA2D_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA2D_MODE( MODE)
+
+Value:
(((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___m_o_d_e.map b/group___d_m_a2_d___m_o_d_e.map new file mode 100644 index 0000000..7e784c2 --- /dev/null +++ b/group___d_m_a2_d___m_o_d_e.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___m_o_d_e.md5 b/group___d_m_a2_d___m_o_d_e.md5 new file mode 100644 index 0000000..5b8fa53 --- /dev/null +++ b/group___d_m_a2_d___m_o_d_e.md5 @@ -0,0 +1 @@ +1be12e9ef357f371762ee9a615743e91 \ No newline at end of file diff --git a/group___d_m_a2_d___m_o_d_e.png b/group___d_m_a2_d___m_o_d_e.png new file mode 100644 index 0000000..c4caacf Binary files /dev/null and b/group___d_m_a2_d___m_o_d_e.png differ diff --git a/group___d_m_a2_d___o_f_f_s_e_t.html b/group___d_m_a2_d___o_f_f_s_e_t.html new file mode 100644 index 0000000..c8a0191 --- /dev/null +++ b/group___d_m_a2_d___o_f_f_s_e_t.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: DMA2D_OFFSET + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_OFFSET
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_OFFSET:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define OFFSET   ((uint32_t)0x00003FFF)
 
+#define IS_DMA2D_FGO(FGO)   ((FGO) <= OFFSET)
 
+#define IS_DMA2D_BGO(BGO)   ((BGO) <= OFFSET)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___o_f_f_s_e_t.map b/group___d_m_a2_d___o_f_f_s_e_t.map new file mode 100644 index 0000000..b47e792 --- /dev/null +++ b/group___d_m_a2_d___o_f_f_s_e_t.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___o_f_f_s_e_t.md5 b/group___d_m_a2_d___o_f_f_s_e_t.md5 new file mode 100644 index 0000000..fc862c5 --- /dev/null +++ b/group___d_m_a2_d___o_f_f_s_e_t.md5 @@ -0,0 +1 @@ +48db923ec6b731dc0708932eb347c7f1 \ No newline at end of file diff --git a/group___d_m_a2_d___o_f_f_s_e_t.png b/group___d_m_a2_d___o_f_f_s_e_t.png new file mode 100644 index 0000000..f763316 Binary files /dev/null and b/group___d_m_a2_d___o_f_f_s_e_t.png differ diff --git a/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.html b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.html new file mode 100644 index 0000000..0176772 --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: DMA2D_OUTPUT_COLOR + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_OUTPUT_COLOR
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_OUTPUT_COLOR:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA2D_Output_Color   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_OGREEN(OGREEN)   ((OGREEN) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_ORED(ORED)   ((ORED) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_OBLUE(OBLUE)   ((OBLUE) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_OALPHA(OALPHA)   ((OALPHA) <= DMA2D_Output_Color)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.map b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.map new file mode 100644 index 0000000..d8d4b5d --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.md5 b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.md5 new file mode 100644 index 0000000..5ef9440 --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.md5 @@ -0,0 +1 @@ +4b08c807fbf2c2e9ee16e64c7edbc103 \ No newline at end of file diff --git a/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.png b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.png new file mode 100644 index 0000000..fe5c803 Binary files /dev/null and b/group___d_m_a2_d___o_u_t_p_u_t___c_o_l_o_r.png differ diff --git a/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.html b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.html new file mode 100644 index 0000000..3fb2c4c --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: DMA2D_OUTPUT_OFFSET + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_OUTPUT_OFFSET
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_OUTPUT_OFFSET:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define DMA2D_OUTPUT_OFFSET   ((uint32_t)0x00003FFF)
 
+#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET)   ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.map b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.map new file mode 100644 index 0000000..9b5e1f8 --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.md5 b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.md5 new file mode 100644 index 0000000..46c7ba4 --- /dev/null +++ b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.md5 @@ -0,0 +1 @@ +842e71c797018543c8bfba83ca064ad8 \ No newline at end of file diff --git a/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.png b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.png new file mode 100644 index 0000000..ae5a72f Binary files /dev/null and b/group___d_m_a2_d___o_u_t_p_u_t___o_f_f_s_e_t.png differ diff --git a/group___d_m_a2_d___private___functions.html b/group___d_m_a2_d___private___functions.html new file mode 100644 index 0000000..91069ed --- /dev/null +++ b/group___d_m_a2_d___private___functions.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: DMA2D_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DMA2D_Private_Functions
STM32F4xx_StdPeriph_Driver » DMA2D
+
+
+
+Collaboration diagram for DMA2D_Private_Functions:
+
+
+ + +
+
+ + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___private___functions.map b/group___d_m_a2_d___private___functions.map new file mode 100644 index 0000000..9e360d3 --- /dev/null +++ b/group___d_m_a2_d___private___functions.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___d_m_a2_d___private___functions.md5 b/group___d_m_a2_d___private___functions.md5 new file mode 100644 index 0000000..3a90958 --- /dev/null +++ b/group___d_m_a2_d___private___functions.md5 @@ -0,0 +1 @@ +f7b62e0ec1522ac13e7f2d43c784be34 \ No newline at end of file diff --git a/group___d_m_a2_d___private___functions.png b/group___d_m_a2_d___private___functions.png new file mode 100644 index 0000000..67f350b Binary files /dev/null and b/group___d_m_a2_d___private___functions.png differ diff --git a/group___d_m_a2_d___s_i_z_e.html b/group___d_m_a2_d___s_i_z_e.html new file mode 100644 index 0000000..c53c138 --- /dev/null +++ b/group___d_m_a2_d___s_i_z_e.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: DMA2D_SIZE + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA2D_SIZE
STM32F4xx_StdPeriph_Driver » DMA2D » DMA2D_Exported_Constants
+
+
+
+Collaboration diagram for DMA2D_SIZE:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DMA2D_pixel   ((uint32_t)0x00003FFF)
 
+#define DMA2D_Line   ((uint32_t)0x0000FFFF)
 
+#define IS_DMA2D_LINE(LINE)   ((LINE) <= DMA2D_Line)
 
+#define IS_DMA2D_PIXEL(PIXEL)   ((PIXEL) <= DMA2D_pixel)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a2_d___s_i_z_e.map b/group___d_m_a2_d___s_i_z_e.map new file mode 100644 index 0000000..5f8d61d --- /dev/null +++ b/group___d_m_a2_d___s_i_z_e.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d___s_i_z_e.md5 b/group___d_m_a2_d___s_i_z_e.md5 new file mode 100644 index 0000000..15a50af --- /dev/null +++ b/group___d_m_a2_d___s_i_z_e.md5 @@ -0,0 +1 @@ +de752d054ab746b92d3b912854f14a3b \ No newline at end of file diff --git a/group___d_m_a2_d___s_i_z_e.png b/group___d_m_a2_d___s_i_z_e.png new file mode 100644 index 0000000..6976d07 Binary files /dev/null and b/group___d_m_a2_d___s_i_z_e.png differ diff --git a/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map new file mode 100644 index 0000000..1cef2e3 --- /dev/null +++ b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 new file mode 100644 index 0000000..2aa64bc --- /dev/null +++ b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.md5 @@ -0,0 +1 @@ +bbae5dbed5c98408e4f7c563ea7dcb43 \ No newline at end of file diff --git a/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png new file mode 100644 index 0000000..117d71a Binary files /dev/null and b/group___d_m_a2_d_gaccfa4814f6cec9d5e4e47d8b92f0de3a_cgraph.png differ diff --git a/group___d_m_a___exported___constants.html b/group___d_m_a___exported___constants.html new file mode 100644 index 0000000..3f6d7f2 --- /dev/null +++ b/group___d_m_a___exported___constants.html @@ -0,0 +1,205 @@ + + + + + + +discoverpixy: DMA_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
DMA_Exported_Constants
STM32F4xx_StdPeriph_Driver » DMA
+
+
+
+Collaboration diagram for DMA_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 DMA_channel
 
 DMA_data_transfer_direction
 
 DMA_data_buffer_size
 
 DMA_peripheral_incremented_mode
 
 DMA_memory_incremented_mode
 
 DMA_peripheral_data_size
 
 DMA_memory_data_size
 
 DMA_circular_normal_mode
 
 DMA_priority_level
 
 DMA_fifo_direct_mode
 
 DMA_fifo_threshold_level
 
 DMA_memory_burst
 
 DMA_peripheral_burst
 
 DMA_fifo_status_level
 
 DMA_flags_definition
 
 DMA_interrupt_enable_definitions
 
 DMA_interrupts_definitions
 
 DMA_peripheral_increment_offset
 
 DMA_flow_controller_definitions
 
 DMA_memory_targets_definitions
 
+ + + + + +

+Macros

#define IS_DMA_ALL_PERIPH(PERIPH)
 
#define IS_DMA_ALL_CONTROLLER(CONTROLLER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_ALL_CONTROLLER( CONTROLLER)
+
+Value:
(((CONTROLLER) == DMA1) || \
+
((CONTROLLER) == DMA2))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DMA_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == DMA1_Stream0) || \
+
((PERIPH) == DMA1_Stream1) || \
+
((PERIPH) == DMA1_Stream2) || \
+
((PERIPH) == DMA1_Stream3) || \
+
((PERIPH) == DMA1_Stream4) || \
+
((PERIPH) == DMA1_Stream5) || \
+
((PERIPH) == DMA1_Stream6) || \
+
((PERIPH) == DMA1_Stream7) || \
+
((PERIPH) == DMA2_Stream0) || \
+
((PERIPH) == DMA2_Stream1) || \
+
((PERIPH) == DMA2_Stream2) || \
+
((PERIPH) == DMA2_Stream3) || \
+
((PERIPH) == DMA2_Stream4) || \
+
((PERIPH) == DMA2_Stream5) || \
+
((PERIPH) == DMA2_Stream6) || \
+
((PERIPH) == DMA2_Stream7))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___exported___constants.map b/group___d_m_a___exported___constants.map new file mode 100644 index 0000000..6b180e0 --- /dev/null +++ b/group___d_m_a___exported___constants.map @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___d_m_a___exported___constants.md5 b/group___d_m_a___exported___constants.md5 new file mode 100644 index 0000000..515ae8a --- /dev/null +++ b/group___d_m_a___exported___constants.md5 @@ -0,0 +1 @@ +371ee490ae76153c25d5fd5d6647eba8 \ No newline at end of file diff --git a/group___d_m_a___exported___constants.png b/group___d_m_a___exported___constants.png new file mode 100644 index 0000000..7225a83 Binary files /dev/null and b/group___d_m_a___exported___constants.png differ diff --git a/group___d_m_a___group1.html b/group___d_m_a___group1.html new file mode 100644 index 0000000..6510043 --- /dev/null +++ b/group___d_m_a___group1.html @@ -0,0 +1,379 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA_DeInit (DMA_Stream_TypeDef *DMAy_Streamx)
 Deinitialize the DMAy Streamx registers to their default reset values. More...
 
void DMA_Init (DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
 Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure. More...
 
void DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
 Fills each DMA_InitStruct member with its default value. More...
 
void DMA_Cmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx. More...
 
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
 Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses). More...
 
void DMA_FlowControllerConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
 Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory). More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+                ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to initialize the DMA Stream source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    buffer size, circular/normal mode selection, memory-to-memory mode selection 
+    and Stream priority value.
+    [..]
+    The DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual (RM0090) except the first point: waiting on EN bit to be reset.
+    This condition should be checked by user application using the function DMA_GetCmdStatus()
+    before calling the DMA_Init() function.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_Cmd (DMA_Stream_TypeDef * DMAy_Streamx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMAy Streamx.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
NewStatenew state of the DMAy Streamx. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
This function may be used to perform Pause-Resume operation. When a transfer is ongoing, calling this function to disable the Stream will cause the transfer to be paused. All configuration registers and the number of remaining data will be preserved. When calling again this function to re-enable the Stream, the transfer will be resumed from the point where it was paused.
+
+After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA_DeInit (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Deinitialize the DMAy Streamx registers to their default reset values.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_FlowControllerConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FlowCtrl 
)
+
+ +

Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory).

+
Note
Before enabling this feature, check if the used peripheral supports the Flow Controller mode or not.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FlowCtrlspecifies the DMA flow controller. This parameter can be one of the following values:
    +
  • DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is the DMA controller.
    • +
  • DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller is the peripheral.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_Init (DMA_Stream_TypeDef * DMAy_Streamx,
DMA_InitTypeDef * DMA_InitStruct 
)
+
+ +

Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure.

+
Note
Before calling this function, it is recommended to check that the Stream is actually disabled using the function DMA_GetCmdStatus().
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_InitStructpointer to a DMA_InitTypeDef structure that contains the configuration information for the specified DMA Stream.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_Pincos 
)
+
+ +

Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses).

+
Note
This function has no effect if the Peripheral Increment mode is disabled.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_Pincosspecifies the Peripheral increment offset size. This parameter can be one of the following values:
    +
  • DMA_PINCOS_Psize: Peripheral address increment is done accordingly to PSIZE parameter.
    • +
  • DMA_PINCOS_WordAligned: Peripheral address increment offset is fixed to 4 (32-bit aligned addresses).
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void DMA_StructInit (DMA_InitTypeDef * DMA_InitStruct)
+
+ +

Fills each DMA_InitStruct member with its default value.

+
Parameters
+ + +
DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___group1.map b/group___d_m_a___group1.map new file mode 100644 index 0000000..8aca7b4 --- /dev/null +++ b/group___d_m_a___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a___group1.md5 b/group___d_m_a___group1.md5 new file mode 100644 index 0000000..1b9b0d2 --- /dev/null +++ b/group___d_m_a___group1.md5 @@ -0,0 +1 @@ +0d9c7b31eb39dc5a6dd54f90c4b298a8 \ No newline at end of file diff --git a/group___d_m_a___group1.png b/group___d_m_a___group1.png new file mode 100644 index 0000000..98d3161 Binary files /dev/null and b/group___d_m_a___group1.png differ diff --git a/group___d_m_a___group2.html b/group___d_m_a___group2.html new file mode 100644 index 0000000..df63594 --- /dev/null +++ b/group___d_m_a___group2.html @@ -0,0 +1,224 @@ + + + + + + +discoverpixy: Data Counter functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Data Counter functions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Private_Functions
+
+
+ +

Data Counter functions. +More...

+
+Collaboration diagram for Data Counter functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void DMA_SetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
 Writes the number of data units to be transferred on the DMAy Streamx. More...
 
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the number of remaining data units in the current DMAy Streamx transfer. More...
 
+

Detailed Description

+

Data Counter functions.

+
 ===============================================================================
+                      ##### Data Counter functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides function allowing to configure and read the buffer size
+    (number of data to be transferred). 
+    [..]
+    The DMA data counter can be written only when the DMA Stream is disabled 
+    (ie. after transfer complete event).
+    [..]
+    The following function can be used to write the Stream data counter value:
+      (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+      -@- It is advised to use this function rather than DMA_Init() in situations 
+          where only the Data buffer needs to be reloaded.
+      -@- If the Source and Destination Data Sizes are different, then the value 
+          written in data counter, expressing the number of transfers, is relative 
+          to the number of transfers from the Peripheral point of view.
+          ie. If Memory data size is Word, Peripheral data size is Half-Words, 
+          then the value to be configured in the data counter is the number 
+          of Half-Words to be transferred from/to the peripheral.
+    [..]
+    The DMA data counter can be read to indicate the number of remaining transfers for
+    the relative DMA Stream. This counter is decremented at the end of each data 
+    transfer and when the transfer is complete: 
+      (+) If Normal mode is selected: the counter is set to 0.
+      (+) If Circular mode is selected: the counter is reloaded with the initial value
+          (configured before enabling the DMA Stream)
+     [..]
+     The following function can be used to read the Stream data counter value:
+       (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the number of remaining data units in the current DMAy Streamx transfer.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
Thenumber of remaining data units in the current DMAy Streamx transfer.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_SetCurrDataCounter (DMA_Stream_TypeDef * DMAy_Streamx,
uint16_t Counter 
)
+
+ +

Writes the number of data units to be transferred on the DMAy Streamx.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
CounterNumber of data units to be transferred (from 0 to 65535) Number of data items depends only on the Peripheral data format.
+
+
+
Note
If Peripheral data format is Bytes: number of data units is equal to total number of bytes to be transferred.
+
+If Peripheral data format is Half-Word: number of data units is equal to total number of bytes to be transferred / 2.
+
+If Peripheral data format is Word: number of data units is equal to total number of bytes to be transferred / 4.
+
+In Memory-to-Memory transfer mode, the memory buffer pointed by DMAy_SxPAR register is considered as Peripheral.
+
Return values
+ + +
Thenumber of remaining data units in the current DMAy Streamx transfer.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___group2.map b/group___d_m_a___group2.map new file mode 100644 index 0000000..01fddeb --- /dev/null +++ b/group___d_m_a___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a___group2.md5 b/group___d_m_a___group2.md5 new file mode 100644 index 0000000..28cb1bf --- /dev/null +++ b/group___d_m_a___group2.md5 @@ -0,0 +1 @@ +d10eaa97495a09da5b7d00a983949585 \ No newline at end of file diff --git a/group___d_m_a___group2.png b/group___d_m_a___group2.png new file mode 100644 index 0000000..abb31c0 Binary files /dev/null and b/group___d_m_a___group2.png differ diff --git a/group___d_m_a___group3.html b/group___d_m_a___group3.html new file mode 100644 index 0000000..fcc3f53 --- /dev/null +++ b/group___d_m_a___group3.html @@ -0,0 +1,346 @@ + + + + + + +discoverpixy: Double Buffer mode functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Double Buffer mode functions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Private_Functions
+
+
+ +

Double Buffer mode functions. +More...

+
+Collaboration diagram for Double Buffer mode functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
 Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target. More...
 
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the double buffer mode for the selected DMA stream. More...
 
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
 Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing. More...
 
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current memory target used by double buffer transfer. More...
 
+

Detailed Description

+

Double Buffer mode functions.

+
 ===============================================================================
+                    ##### Double Buffer mode functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides function allowing to configure and control the double 
+    buffer mode parameters.
+    
+    [..]
+    The Double Buffer mode can be used only when Circular mode is enabled.
+    The Double Buffer mode cannot be used when transferring data from Memory to Memory.
+    
+    [..]
+    The Double Buffer mode allows to set two different Memory addresses from/to which
+    the DMA controller will access alternatively (after completing transfer to/from 
+    target memory 0, it will start transfer to/from target memory 1).
+    This allows to reduce software overhead for double buffering and reduce the CPU
+    access time.
+    
+    [..]
+    Two functions must be called before calling the DMA_Init() function:
+      (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, 
+          uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
+      (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+      
+    [..]
+    DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address 
+    and the first Memory target from/to which the transfer will start after 
+    enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called 
+    to enable the Double Buffer mode (or disable it when it should not be used).
+  
+    [..]
+    Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is 
+    stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
+    used:
+      (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, 
+                uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
+      (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+      
+    [..]
+    DMA_MemoryTargetConfig() can be called to modify the base address of one of 
+    the two target Memories.
+    The Memory of which the base address will be modified must not be currently 
+    be used by the DMA Stream (ie. if the DMA Stream is currently transferring 
+    from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
+    To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
+    returns the index of the Memory target currently in use by the DMA Stream.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef * DMAy_Streamx,
FunctionalState NewState 
)
+
+ +

Enables or disables the double buffer mode for the selected DMA stream.

+
Note
This function can be called only when the DMA Stream is disabled.
+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
NewStatenew state of the DMAy Streamx double buffer mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t Memory1BaseAddr,
uint32_t DMA_CurrentMemory 
)
+
+ +

Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
Memory1BaseAddrthe base address of the second buffer (Memory 1)
DMA_CurrentMemoryspecifies which memory will be first buffer for the transactions when the Stream will be enabled. This parameter can be one of the following values:
    +
  • DMA_Memory_0: Memory 0 is the current buffer.
    • +
  • DMA_Memory_1: Memory 1 is the current buffer.
    • +
+
+
+
+
Note
Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the current memory target used by double buffer transfer.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
Thememory target number: 0 for Memory0 or 1 for Memory1.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t MemoryBaseAddr,
uint32_t DMA_MemoryTarget 
)
+
+ +

Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
MemoryBaseAddrThe base address of the target memory buffer
DMA_MemoryTargetNext memory target to be used. This parameter can be one of the following values:
    +
  • DMA_Memory_0: To use the memory address 0
    • +
  • DMA_Memory_1: To use the memory address 1
    • +
+
+
+
+
Note
It is not allowed to modify the Base Address of a target Memory when this target is involved in the current transfer. ie. If the DMA Stream is currently transferring to/from Memory 1, then it not possible to modify Base address of Memory 1, but it is possible to modify Base address of Memory 0. To know which Memory is currently used, you can use the function DMA_GetCurrentMemoryTarget().
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___group3.map b/group___d_m_a___group3.map new file mode 100644 index 0000000..4173567 --- /dev/null +++ b/group___d_m_a___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a___group3.md5 b/group___d_m_a___group3.md5 new file mode 100644 index 0000000..0b1622a --- /dev/null +++ b/group___d_m_a___group3.md5 @@ -0,0 +1 @@ +505350af0682250eb7e4ad22ae6b70ff \ No newline at end of file diff --git a/group___d_m_a___group3.png b/group___d_m_a___group3.png new file mode 100644 index 0000000..8149db9 Binary files /dev/null and b/group___d_m_a___group3.png differ diff --git a/group___d_m_a___group4.html b/group___d_m_a___group4.html new file mode 100644 index 0000000..2430fdd --- /dev/null +++ b/group___d_m_a___group4.html @@ -0,0 +1,511 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the status of EN bit for the specified DMAy Streamx. More...
 
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current DMAy Streamx FIFO filled level. More...
 
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Checks whether the specified DMAy Streamx flag is set or not. More...
 
void DMA_ClearFlag (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Clears the DMAy Streamx's pending flags. More...
 
void DMA_ITConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx interrupts. More...
 
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Checks whether the specified DMAy Streamx interrupt has occurred or not. More...
 
void DMA_ClearITPendingBit (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Clears the DMAy Streamx's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA enable status
+      (+) Check the FIFO status 
+      (+) Configure the DMA Interrupts sources and check or clear the flags or 
+          pending bits status.  
+           
+    [..]
+      (#) DMA Enable status:
+          After configuring the DMA Stream (DMA_Init() function) and enabling 
+          the stream, it is recommended to check (or wait until) the DMA Stream 
+          is effectively enabled. A Stream may remain disabled if a configuration 
+          parameter is wrong. After disabling a DMA Stream, it is also recommended 
+          to check (or wait until) the DMA Stream is effectively disabled. 
+          If a Stream is disabled while a data transfer is ongoing, the current 
+          data will be transferred and the Stream will be effectively disabled 
+          only after this data transfer completion.
+          To monitor this state it is possible to use the following function:
+        (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+      (#) FIFO Status:
+          It is possible to monitor the FIFO status when a transfer is ongoing 
+          using the following function:
+        (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+      (#) DMA Interrupts and Flags:
+          The user should identify which mode will be used in his application 
+          to manage the DMA controller events: Polling mode or Interrupt mode. 
+    
+    *** Polling Mode ***
+    ====================
+    [..]
+    Each DMA stream can be managed through 4 event Flags:
+    (x : DMA Stream number )
+      (#) DMA_FLAG_FEIFx  : to indicate that a FIFO Mode Transfer Error event occurred.
+      (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
+      (#) DMA_FLAG_TEIFx  : to indicate that a Transfer Error event occurred.
+      (#) DMA_FLAG_HTIFx  : to indicate that a Half-Transfer Complete event occurred.
+      (#) DMA_FLAG_TCIFx  : to indicate that a Transfer Complete event occurred .       
+    [..]
+    In this Mode it is advised to use the following functions:
+      (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+      (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+
+    *** Interrupt Mode ***
+    ======================
+    [..]
+    Each DMA Stream can be managed through 4 Interrupts:
+
+    *** Interrupt Source ***
+    ========================
+    [..]
+      (#) DMA_IT_FEIFx  : specifies the interrupt source for the  FIFO Mode Transfer Error event.
+      (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
+      (#) DMA_IT_TEIFx  : specifies the interrupt source for the Transfer Error event.
+      (#) DMA_IT_HTIFx  : specifies the interrupt source for the Half-Transfer Complete event.
+      (#) DMA_IT_TCIFx  : specifies the interrupt source for the a Transfer Complete event. 
+    [..]
+    In this Mode it is advised to use the following functions:
+      (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+      (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+      (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_ClearFlag (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FLAG 
)
+
+ +

Clears the DMAy Streamx's pending flags.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • DMA_FLAG_TCIFx: Streamx transfer complete flag
    • +
  • DMA_FLAG_HTIFx: Streamx half transfer complete flag
    • +
  • DMA_FLAG_TEIFx: Streamx transfer error flag
    • +
  • DMA_FLAG_DMEIFx: Streamx direct mode error flag
    • +
  • DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void DMA_ClearITPendingBit (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT 
)
+
+ +

Clears the DMAy Streamx's interrupt pending bits.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • DMA_IT_TCIFx: Streamx transfer complete interrupt
    • +
  • DMA_IT_HTIFx: Streamx half transfer complete interrupt
    • +
  • DMA_IT_TEIFx: Streamx transfer error interrupt
    • +
  • DMA_IT_DMEIFx: Streamx direct mode error interrupt
    • +
  • DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the status of EN bit for the specified DMAy Streamx.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Note
After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.
+
Return values
+ + +
Currentstate of the DMAy Streamx (ENABLE or DISABLE).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef * DMAy_Streamx)
+
+ +

Returns the current DMAy Streamx FIFO filled level.

+
Parameters
+ + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
+
+
+
Return values
+ + +
TheFIFO filling state.
    +
  • DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
    • +
  • DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
    • +
  • DMA_FIFOStatus_HalfFull: if more than 1 half-full.
    • +
  • DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
    • +
  • DMA_FIFOStatus_Empty: when FIFO is empty
    • +
  • DMA_FIFOStatus_Full: when FIFO is full
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_FLAG 
)
+
+ +

Checks whether the specified DMAy Streamx flag is set or not.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • DMA_FLAG_TCIFx: Streamx transfer complete flag
    • +
  • DMA_FLAG_HTIFx: Streamx half transfer complete flag
    • +
  • DMA_FLAG_TEIFx: Streamx transfer error flag
    • +
  • DMA_FLAG_DMEIFx: Streamx direct mode error flag
    • +
  • DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT 
)
+
+ +

Checks whether the specified DMAy Streamx interrupt has occurred or not.

+
Parameters
+ + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt source to check. This parameter can be one of the following values:
    +
  • DMA_IT_TCIFx: Streamx transfer complete interrupt
    • +
  • DMA_IT_HTIFx: Streamx half transfer complete interrupt
    • +
  • DMA_IT_TEIFx: Streamx transfer error interrupt
    • +
  • DMA_IT_DMEIFx: Streamx direct mode error interrupt
    • +
  • DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream.
    • +
+
+
+
+
Return values
+ + +
Thenew state of DMA_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void DMA_ITConfig (DMA_Stream_TypeDef * DMAy_Streamx,
uint32_t DMA_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified DMAy Streamx interrupts.

+
Parameters
+ + + + +
DMAy_Streamxwhere y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.
DMA_ITspecifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • DMA_IT_TC: Transfer complete interrupt mask
    • +
  • DMA_IT_HT: Half transfer complete interrupt mask
    • +
  • DMA_IT_TE: Transfer error interrupt mask
    • +
  • DMA_IT_FE: FIFO error interrupt mask
    • +
+
NewStatenew state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___group4.map b/group___d_m_a___group4.map new file mode 100644 index 0000000..866907e --- /dev/null +++ b/group___d_m_a___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a___group4.md5 b/group___d_m_a___group4.md5 new file mode 100644 index 0000000..9c6dcbf --- /dev/null +++ b/group___d_m_a___group4.md5 @@ -0,0 +1 @@ +3ab587ec31b62839f225ee21c49dbcaa \ No newline at end of file diff --git a/group___d_m_a___group4.png b/group___d_m_a___group4.png new file mode 100644 index 0000000..ed33542 Binary files /dev/null and b/group___d_m_a___group4.png differ diff --git a/group___d_m_a___private___functions.html b/group___d_m_a___private___functions.html new file mode 100644 index 0000000..ce82b60 --- /dev/null +++ b/group___d_m_a___private___functions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: DMA_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
DMA_Private_Functions
STM32F4xx_StdPeriph_Driver » DMA
+
+
+
+Collaboration diagram for DMA_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Data Counter functions
 Data Counter functions.
 
 Double Buffer mode functions
 Double Buffer mode functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a___private___functions.map b/group___d_m_a___private___functions.map new file mode 100644 index 0000000..0cec791 --- /dev/null +++ b/group___d_m_a___private___functions.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___d_m_a___private___functions.md5 b/group___d_m_a___private___functions.md5 new file mode 100644 index 0000000..849c748 --- /dev/null +++ b/group___d_m_a___private___functions.md5 @@ -0,0 +1 @@ +687915afeaa4dbda8bac7e4f0178ed69 \ No newline at end of file diff --git a/group___d_m_a___private___functions.png b/group___d_m_a___private___functions.png new file mode 100644 index 0000000..a27c7b5 Binary files /dev/null and b/group___d_m_a___private___functions.png differ diff --git a/group___d_m_a__channel.html b/group___d_m_a__channel.html new file mode 100644 index 0000000..a16ea13 --- /dev/null +++ b/group___d_m_a__channel.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: DMA_channel + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_channel
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_channel:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DMA_Channel_0   ((uint32_t)0x00000000)
 
+#define DMA_Channel_1   ((uint32_t)0x02000000)
 
+#define DMA_Channel_2   ((uint32_t)0x04000000)
 
+#define DMA_Channel_3   ((uint32_t)0x06000000)
 
+#define DMA_Channel_4   ((uint32_t)0x08000000)
 
+#define DMA_Channel_5   ((uint32_t)0x0A000000)
 
+#define DMA_Channel_6   ((uint32_t)0x0C000000)
 
+#define DMA_Channel_7   ((uint32_t)0x0E000000)
 
#define IS_DMA_CHANNEL(CHANNEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == DMA_Channel_0) || \
+
((CHANNEL) == DMA_Channel_1) || \
+
((CHANNEL) == DMA_Channel_2) || \
+
((CHANNEL) == DMA_Channel_3) || \
+
((CHANNEL) == DMA_Channel_4) || \
+
((CHANNEL) == DMA_Channel_5) || \
+
((CHANNEL) == DMA_Channel_6) || \
+
((CHANNEL) == DMA_Channel_7))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__channel.map b/group___d_m_a__channel.map new file mode 100644 index 0000000..3e51803 --- /dev/null +++ b/group___d_m_a__channel.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__channel.md5 b/group___d_m_a__channel.md5 new file mode 100644 index 0000000..00fa180 --- /dev/null +++ b/group___d_m_a__channel.md5 @@ -0,0 +1 @@ +3e7f4d059fd25f5d814d1bec9c27e83c \ No newline at end of file diff --git a/group___d_m_a__channel.png b/group___d_m_a__channel.png new file mode 100644 index 0000000..02e6dff Binary files /dev/null and b/group___d_m_a__channel.png differ diff --git a/group___d_m_a__circular__normal__mode.html b/group___d_m_a__circular__normal__mode.html new file mode 100644 index 0000000..dd8720c --- /dev/null +++ b/group___d_m_a__circular__normal__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_circular_normal_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_circular_normal_mode
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_circular_normal_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_Mode_Normal   ((uint32_t)0x00000000)
 
+#define DMA_Mode_Circular   ((uint32_t)0x00000100)
 
#define IS_DMA_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_MODE( MODE)
+
+Value:
(((MODE) == DMA_Mode_Normal ) || \
+
((MODE) == DMA_Mode_Circular))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__circular__normal__mode.map b/group___d_m_a__circular__normal__mode.map new file mode 100644 index 0000000..8b9dacb --- /dev/null +++ b/group___d_m_a__circular__normal__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__circular__normal__mode.md5 b/group___d_m_a__circular__normal__mode.md5 new file mode 100644 index 0000000..ae6ed97 --- /dev/null +++ b/group___d_m_a__circular__normal__mode.md5 @@ -0,0 +1 @@ +40f62278a970af07c9cea92294644c81 \ No newline at end of file diff --git a/group___d_m_a__circular__normal__mode.png b/group___d_m_a__circular__normal__mode.png new file mode 100644 index 0000000..69b02e5 Binary files /dev/null and b/group___d_m_a__circular__normal__mode.png differ diff --git a/group___d_m_a__data__buffer__size.html b/group___d_m_a__data__buffer__size.html new file mode 100644 index 0000000..e3d86bc --- /dev/null +++ b/group___d_m_a__data__buffer__size.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: DMA_data_buffer_size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_data_buffer_size
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_data_buffer_size:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_DMA_BUFFER_SIZE(SIZE)   (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__data__buffer__size.map b/group___d_m_a__data__buffer__size.map new file mode 100644 index 0000000..63733ea --- /dev/null +++ b/group___d_m_a__data__buffer__size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__data__buffer__size.md5 b/group___d_m_a__data__buffer__size.md5 new file mode 100644 index 0000000..117b525 --- /dev/null +++ b/group___d_m_a__data__buffer__size.md5 @@ -0,0 +1 @@ +1590d7e83f12d71f110d8150b1a87aad \ No newline at end of file diff --git a/group___d_m_a__data__buffer__size.png b/group___d_m_a__data__buffer__size.png new file mode 100644 index 0000000..1c9cacf Binary files /dev/null and b/group___d_m_a__data__buffer__size.png differ diff --git a/group___d_m_a__data__transfer__direction.html b/group___d_m_a__data__transfer__direction.html new file mode 100644 index 0000000..02dd9f4 --- /dev/null +++ b/group___d_m_a__data__transfer__direction.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: DMA_data_transfer_direction + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_data_transfer_direction
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_data_transfer_direction:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DMA_DIR_PeripheralToMemory   ((uint32_t)0x00000000)
 
+#define DMA_DIR_MemoryToPeripheral   ((uint32_t)0x00000040)
 
+#define DMA_DIR_MemoryToMemory   ((uint32_t)0x00000080)
 
#define IS_DMA_DIRECTION(DIRECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_DIRECTION( DIRECTION)
+
+Value:
(((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+
((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
+
((DIRECTION) == DMA_DIR_MemoryToMemory))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__data__transfer__direction.map b/group___d_m_a__data__transfer__direction.map new file mode 100644 index 0000000..495ea37 --- /dev/null +++ b/group___d_m_a__data__transfer__direction.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__data__transfer__direction.md5 b/group___d_m_a__data__transfer__direction.md5 new file mode 100644 index 0000000..8f7dedb --- /dev/null +++ b/group___d_m_a__data__transfer__direction.md5 @@ -0,0 +1 @@ +3a60cd75b98e769c75dca869ba5d2d5b \ No newline at end of file diff --git a/group___d_m_a__data__transfer__direction.png b/group___d_m_a__data__transfer__direction.png new file mode 100644 index 0000000..2f9aa81 Binary files /dev/null and b/group___d_m_a__data__transfer__direction.png differ diff --git a/group___d_m_a__fifo__direct__mode.html b/group___d_m_a__fifo__direct__mode.html new file mode 100644 index 0000000..2f182ee --- /dev/null +++ b/group___d_m_a__fifo__direct__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_fifo_direct_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_fifo_direct_mode
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_fifo_direct_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_FIFOMode_Disable   ((uint32_t)0x00000000)
 
+#define DMA_FIFOMode_Enable   ((uint32_t)0x00000004)
 
#define IS_DMA_FIFO_MODE_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_FIFO_MODE_STATE( STATE)
+
+Value:
(((STATE) == DMA_FIFOMode_Disable ) || \
+
((STATE) == DMA_FIFOMode_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__fifo__direct__mode.map b/group___d_m_a__fifo__direct__mode.map new file mode 100644 index 0000000..7c39cf4 --- /dev/null +++ b/group___d_m_a__fifo__direct__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__fifo__direct__mode.md5 b/group___d_m_a__fifo__direct__mode.md5 new file mode 100644 index 0000000..27e301c --- /dev/null +++ b/group___d_m_a__fifo__direct__mode.md5 @@ -0,0 +1 @@ +8cbc0573d4af71556193fcdd34ca0329 \ No newline at end of file diff --git a/group___d_m_a__fifo__direct__mode.png b/group___d_m_a__fifo__direct__mode.png new file mode 100644 index 0000000..9b0547a Binary files /dev/null and b/group___d_m_a__fifo__direct__mode.png differ diff --git a/group___d_m_a__fifo__status__level.html b/group___d_m_a__fifo__status__level.html new file mode 100644 index 0000000..e5f3100 --- /dev/null +++ b/group___d_m_a__fifo__status__level.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: DMA_fifo_status_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_fifo_status_level
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_fifo_status_level:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
 
+#define DMA_FIFOStatus_1QuarterFull   ((uint32_t)0x00000001 << 3)
 
+#define DMA_FIFOStatus_HalfFull   ((uint32_t)0x00000002 << 3)
 
+#define DMA_FIFOStatus_3QuartersFull   ((uint32_t)0x00000003 << 3)
 
+#define DMA_FIFOStatus_Empty   ((uint32_t)0x00000004 << 3)
 
+#define DMA_FIFOStatus_Full   ((uint32_t)0x00000005 << 3)
 
#define IS_DMA_FIFO_STATUS(STATUS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_FIFO_STATUS( STATUS)
+
+Value:
(((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+
((STATUS) == DMA_FIFOStatus_HalfFull) || \
+
((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
+
((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
+
((STATUS) == DMA_FIFOStatus_Full) || \
+
((STATUS) == DMA_FIFOStatus_Empty))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__fifo__status__level.map b/group___d_m_a__fifo__status__level.map new file mode 100644 index 0000000..ab44c98 --- /dev/null +++ b/group___d_m_a__fifo__status__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__fifo__status__level.md5 b/group___d_m_a__fifo__status__level.md5 new file mode 100644 index 0000000..fe2fca2 --- /dev/null +++ b/group___d_m_a__fifo__status__level.md5 @@ -0,0 +1 @@ +75ea5337c21f830960cb6d26e3f7b4b4 \ No newline at end of file diff --git a/group___d_m_a__fifo__status__level.png b/group___d_m_a__fifo__status__level.png new file mode 100644 index 0000000..4ae94c2 Binary files /dev/null and b/group___d_m_a__fifo__status__level.png differ diff --git a/group___d_m_a__fifo__threshold__level.html b/group___d_m_a__fifo__threshold__level.html new file mode 100644 index 0000000..cfc1efb --- /dev/null +++ b/group___d_m_a__fifo__threshold__level.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: DMA_fifo_threshold_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_fifo_threshold_level
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_fifo_threshold_level:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA_FIFOThreshold_1QuarterFull   ((uint32_t)0x00000000)
 
+#define DMA_FIFOThreshold_HalfFull   ((uint32_t)0x00000001)
 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
 
+#define DMA_FIFOThreshold_Full   ((uint32_t)0x00000003)
 
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_FIFO_THRESHOLD( THRESHOLD)
+
+Value:
(((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+
((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
+
((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+
((THRESHOLD) == DMA_FIFOThreshold_Full))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__fifo__threshold__level.map b/group___d_m_a__fifo__threshold__level.map new file mode 100644 index 0000000..f85cb99 --- /dev/null +++ b/group___d_m_a__fifo__threshold__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__fifo__threshold__level.md5 b/group___d_m_a__fifo__threshold__level.md5 new file mode 100644 index 0000000..e6ac203 --- /dev/null +++ b/group___d_m_a__fifo__threshold__level.md5 @@ -0,0 +1 @@ +fec5011b67c697712d2b799d98cb99ca \ No newline at end of file diff --git a/group___d_m_a__fifo__threshold__level.png b/group___d_m_a__fifo__threshold__level.png new file mode 100644 index 0000000..4372e94 Binary files /dev/null and b/group___d_m_a__fifo__threshold__level.png differ diff --git a/group___d_m_a__flags__definition.html b/group___d_m_a__flags__definition.html new file mode 100644 index 0000000..fcfcb7f --- /dev/null +++ b/group___d_m_a__flags__definition.html @@ -0,0 +1,285 @@ + + + + + + +discoverpixy: DMA_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_flags_definition
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_flags_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DMA_FLAG_FEIF0   ((uint32_t)0x10800001)
 
+#define DMA_FLAG_DMEIF0   ((uint32_t)0x10800004)
 
+#define DMA_FLAG_TEIF0   ((uint32_t)0x10000008)
 
+#define DMA_FLAG_HTIF0   ((uint32_t)0x10000010)
 
+#define DMA_FLAG_TCIF0   ((uint32_t)0x10000020)
 
+#define DMA_FLAG_FEIF1   ((uint32_t)0x10000040)
 
+#define DMA_FLAG_DMEIF1   ((uint32_t)0x10000100)
 
+#define DMA_FLAG_TEIF1   ((uint32_t)0x10000200)
 
+#define DMA_FLAG_HTIF1   ((uint32_t)0x10000400)
 
+#define DMA_FLAG_TCIF1   ((uint32_t)0x10000800)
 
+#define DMA_FLAG_FEIF2   ((uint32_t)0x10010000)
 
+#define DMA_FLAG_DMEIF2   ((uint32_t)0x10040000)
 
+#define DMA_FLAG_TEIF2   ((uint32_t)0x10080000)
 
+#define DMA_FLAG_HTIF2   ((uint32_t)0x10100000)
 
+#define DMA_FLAG_TCIF2   ((uint32_t)0x10200000)
 
+#define DMA_FLAG_FEIF3   ((uint32_t)0x10400000)
 
+#define DMA_FLAG_DMEIF3   ((uint32_t)0x11000000)
 
+#define DMA_FLAG_TEIF3   ((uint32_t)0x12000000)
 
+#define DMA_FLAG_HTIF3   ((uint32_t)0x14000000)
 
+#define DMA_FLAG_TCIF3   ((uint32_t)0x18000000)
 
+#define DMA_FLAG_FEIF4   ((uint32_t)0x20000001)
 
+#define DMA_FLAG_DMEIF4   ((uint32_t)0x20000004)
 
+#define DMA_FLAG_TEIF4   ((uint32_t)0x20000008)
 
+#define DMA_FLAG_HTIF4   ((uint32_t)0x20000010)
 
+#define DMA_FLAG_TCIF4   ((uint32_t)0x20000020)
 
+#define DMA_FLAG_FEIF5   ((uint32_t)0x20000040)
 
+#define DMA_FLAG_DMEIF5   ((uint32_t)0x20000100)
 
+#define DMA_FLAG_TEIF5   ((uint32_t)0x20000200)
 
+#define DMA_FLAG_HTIF5   ((uint32_t)0x20000400)
 
+#define DMA_FLAG_TCIF5   ((uint32_t)0x20000800)
 
+#define DMA_FLAG_FEIF6   ((uint32_t)0x20010000)
 
+#define DMA_FLAG_DMEIF6   ((uint32_t)0x20040000)
 
+#define DMA_FLAG_TEIF6   ((uint32_t)0x20080000)
 
+#define DMA_FLAG_HTIF6   ((uint32_t)0x20100000)
 
+#define DMA_FLAG_TCIF6   ((uint32_t)0x20200000)
 
+#define DMA_FLAG_FEIF7   ((uint32_t)0x20400000)
 
+#define DMA_FLAG_DMEIF7   ((uint32_t)0x21000000)
 
+#define DMA_FLAG_TEIF7   ((uint32_t)0x22000000)
 
+#define DMA_FLAG_HTIF7   ((uint32_t)0x24000000)
 
+#define DMA_FLAG_TCIF7   ((uint32_t)0x28000000)
 
#define IS_DMA_CLEAR_FLAG(FLAG)
 
#define IS_DMA_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_CLEAR_FLAG( FLAG)
+
+Value:
((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+
(((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DMA_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
+
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
+
((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
+
((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
+
((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
+
((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
+
((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
+
((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
+
((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
+
((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
+
((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
+
((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
+
((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
+
((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
+
((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
+
((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
+
((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
+
((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
+
((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
+
((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__flags__definition.map b/group___d_m_a__flags__definition.map new file mode 100644 index 0000000..6182ce3 --- /dev/null +++ b/group___d_m_a__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__flags__definition.md5 b/group___d_m_a__flags__definition.md5 new file mode 100644 index 0000000..f1b1e8a --- /dev/null +++ b/group___d_m_a__flags__definition.md5 @@ -0,0 +1 @@ +29308bc1ea03a3761fae674484d6ad8e \ No newline at end of file diff --git a/group___d_m_a__flags__definition.png b/group___d_m_a__flags__definition.png new file mode 100644 index 0000000..e90cee8 Binary files /dev/null and b/group___d_m_a__flags__definition.png differ diff --git a/group___d_m_a__flow__controller__definitions.html b/group___d_m_a__flow__controller__definitions.html new file mode 100644 index 0000000..09f5b1e --- /dev/null +++ b/group___d_m_a__flow__controller__definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_flow_controller_definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_flow_controller_definitions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_flow_controller_definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_FlowCtrl_Memory   ((uint32_t)0x00000000)
 
+#define DMA_FlowCtrl_Peripheral   ((uint32_t)0x00000020)
 
#define IS_DMA_FLOW_CTRL(CTRL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_FLOW_CTRL( CTRL)
+
+Value:
(((CTRL) == DMA_FlowCtrl_Memory) || \
+
((CTRL) == DMA_FlowCtrl_Peripheral))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__flow__controller__definitions.map b/group___d_m_a__flow__controller__definitions.map new file mode 100644 index 0000000..95cd3e4 --- /dev/null +++ b/group___d_m_a__flow__controller__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__flow__controller__definitions.md5 b/group___d_m_a__flow__controller__definitions.md5 new file mode 100644 index 0000000..dbb326c --- /dev/null +++ b/group___d_m_a__flow__controller__definitions.md5 @@ -0,0 +1 @@ +6603847ac4e1f6f53f45bc2fb86ca34b \ No newline at end of file diff --git a/group___d_m_a__flow__controller__definitions.png b/group___d_m_a__flow__controller__definitions.png new file mode 100644 index 0000000..ba38686 Binary files /dev/null and b/group___d_m_a__flow__controller__definitions.png differ diff --git a/group___d_m_a__interrupt__enable__definitions.html b/group___d_m_a__interrupt__enable__definitions.html new file mode 100644 index 0000000..6eba066 --- /dev/null +++ b/group___d_m_a__interrupt__enable__definitions.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: DMA_interrupt_enable_definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_interrupt_enable_definitions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_interrupt_enable_definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define DMA_IT_TC   ((uint32_t)0x00000010)
 
+#define DMA_IT_HT   ((uint32_t)0x00000008)
 
+#define DMA_IT_TE   ((uint32_t)0x00000004)
 
+#define DMA_IT_DME   ((uint32_t)0x00000002)
 
+#define DMA_IT_FE   ((uint32_t)0x00000080)
 
+#define IS_DMA_CONFIG_IT(IT)   ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__interrupt__enable__definitions.map b/group___d_m_a__interrupt__enable__definitions.map new file mode 100644 index 0000000..2561c49 --- /dev/null +++ b/group___d_m_a__interrupt__enable__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__interrupt__enable__definitions.md5 b/group___d_m_a__interrupt__enable__definitions.md5 new file mode 100644 index 0000000..e79e200 --- /dev/null +++ b/group___d_m_a__interrupt__enable__definitions.md5 @@ -0,0 +1 @@ +65a9ba01e818fa9b1159e05fcb2e4547 \ No newline at end of file diff --git a/group___d_m_a__interrupt__enable__definitions.png b/group___d_m_a__interrupt__enable__definitions.png new file mode 100644 index 0000000..b539431 Binary files /dev/null and b/group___d_m_a__interrupt__enable__definitions.png differ diff --git a/group___d_m_a__interrupts__definitions.html b/group___d_m_a__interrupts__definitions.html new file mode 100644 index 0000000..e6eacf7 --- /dev/null +++ b/group___d_m_a__interrupts__definitions.html @@ -0,0 +1,286 @@ + + + + + + +discoverpixy: DMA_interrupts_definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_interrupts_definitions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_interrupts_definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DMA_IT_FEIF0   ((uint32_t)0x90000001)
 
+#define DMA_IT_DMEIF0   ((uint32_t)0x10001004)
 
+#define DMA_IT_TEIF0   ((uint32_t)0x10002008)
 
+#define DMA_IT_HTIF0   ((uint32_t)0x10004010)
 
+#define DMA_IT_TCIF0   ((uint32_t)0x10008020)
 
+#define DMA_IT_FEIF1   ((uint32_t)0x90000040)
 
+#define DMA_IT_DMEIF1   ((uint32_t)0x10001100)
 
+#define DMA_IT_TEIF1   ((uint32_t)0x10002200)
 
+#define DMA_IT_HTIF1   ((uint32_t)0x10004400)
 
+#define DMA_IT_TCIF1   ((uint32_t)0x10008800)
 
+#define DMA_IT_FEIF2   ((uint32_t)0x90010000)
 
+#define DMA_IT_DMEIF2   ((uint32_t)0x10041000)
 
+#define DMA_IT_TEIF2   ((uint32_t)0x10082000)
 
+#define DMA_IT_HTIF2   ((uint32_t)0x10104000)
 
+#define DMA_IT_TCIF2   ((uint32_t)0x10208000)
 
+#define DMA_IT_FEIF3   ((uint32_t)0x90400000)
 
+#define DMA_IT_DMEIF3   ((uint32_t)0x11001000)
 
+#define DMA_IT_TEIF3   ((uint32_t)0x12002000)
 
+#define DMA_IT_HTIF3   ((uint32_t)0x14004000)
 
+#define DMA_IT_TCIF3   ((uint32_t)0x18008000)
 
+#define DMA_IT_FEIF4   ((uint32_t)0xA0000001)
 
+#define DMA_IT_DMEIF4   ((uint32_t)0x20001004)
 
+#define DMA_IT_TEIF4   ((uint32_t)0x20002008)
 
+#define DMA_IT_HTIF4   ((uint32_t)0x20004010)
 
+#define DMA_IT_TCIF4   ((uint32_t)0x20008020)
 
+#define DMA_IT_FEIF5   ((uint32_t)0xA0000040)
 
+#define DMA_IT_DMEIF5   ((uint32_t)0x20001100)
 
+#define DMA_IT_TEIF5   ((uint32_t)0x20002200)
 
+#define DMA_IT_HTIF5   ((uint32_t)0x20004400)
 
+#define DMA_IT_TCIF5   ((uint32_t)0x20008800)
 
+#define DMA_IT_FEIF6   ((uint32_t)0xA0010000)
 
+#define DMA_IT_DMEIF6   ((uint32_t)0x20041000)
 
+#define DMA_IT_TEIF6   ((uint32_t)0x20082000)
 
+#define DMA_IT_HTIF6   ((uint32_t)0x20104000)
 
+#define DMA_IT_TCIF6   ((uint32_t)0x20208000)
 
+#define DMA_IT_FEIF7   ((uint32_t)0xA0400000)
 
+#define DMA_IT_DMEIF7   ((uint32_t)0x21001000)
 
+#define DMA_IT_TEIF7   ((uint32_t)0x22002000)
 
+#define DMA_IT_HTIF7   ((uint32_t)0x24004000)
 
+#define DMA_IT_TCIF7   ((uint32_t)0x28008000)
 
#define IS_DMA_CLEAR_IT(IT)
 
#define IS_DMA_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_CLEAR_IT( IT)
+
+Value:
((((IT) & 0x30000000) != 0x30000000) && \
+
(((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+
(((IT) & 0x40820082) == 0x00))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_DMA_GET_IT( IT)
+
+Value:
(((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
+
((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+
((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
+
((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
+
((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
+
((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
+
((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+
((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
+
((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
+
((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
+
((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
+
((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+
((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
+
((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
+
((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
+
((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
+
((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+
((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
+
((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
+
((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__interrupts__definitions.map b/group___d_m_a__interrupts__definitions.map new file mode 100644 index 0000000..98ac9f5 --- /dev/null +++ b/group___d_m_a__interrupts__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__interrupts__definitions.md5 b/group___d_m_a__interrupts__definitions.md5 new file mode 100644 index 0000000..2cfc528 --- /dev/null +++ b/group___d_m_a__interrupts__definitions.md5 @@ -0,0 +1 @@ +7db56438d72d61df365a4dfdc52f6f32 \ No newline at end of file diff --git a/group___d_m_a__interrupts__definitions.png b/group___d_m_a__interrupts__definitions.png new file mode 100644 index 0000000..c28c5b2 Binary files /dev/null and b/group___d_m_a__interrupts__definitions.png differ diff --git a/group___d_m_a__memory__burst.html b/group___d_m_a__memory__burst.html new file mode 100644 index 0000000..6498ac1 --- /dev/null +++ b/group___d_m_a__memory__burst.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: DMA_memory_burst + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_memory_burst
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_memory_burst:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA_MemoryBurst_Single   ((uint32_t)0x00000000)
 
+#define DMA_MemoryBurst_INC4   ((uint32_t)0x00800000)
 
+#define DMA_MemoryBurst_INC8   ((uint32_t)0x01000000)
 
+#define DMA_MemoryBurst_INC16   ((uint32_t)0x01800000)
 
#define IS_DMA_MEMORY_BURST(BURST)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_MEMORY_BURST( BURST)
+
+Value:
(((BURST) == DMA_MemoryBurst_Single) || \
+
((BURST) == DMA_MemoryBurst_INC4) || \
+
((BURST) == DMA_MemoryBurst_INC8) || \
+
((BURST) == DMA_MemoryBurst_INC16))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__memory__burst.map b/group___d_m_a__memory__burst.map new file mode 100644 index 0000000..1a614b6 --- /dev/null +++ b/group___d_m_a__memory__burst.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__memory__burst.md5 b/group___d_m_a__memory__burst.md5 new file mode 100644 index 0000000..81089f1 --- /dev/null +++ b/group___d_m_a__memory__burst.md5 @@ -0,0 +1 @@ +8c5fe24932d8f389bc3df85f6bb32cba \ No newline at end of file diff --git a/group___d_m_a__memory__burst.png b/group___d_m_a__memory__burst.png new file mode 100644 index 0000000..a731b1d Binary files /dev/null and b/group___d_m_a__memory__burst.png differ diff --git a/group___d_m_a__memory__data__size.html b/group___d_m_a__memory__data__size.html new file mode 100644 index 0000000..8373758 --- /dev/null +++ b/group___d_m_a__memory__data__size.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: DMA_memory_data_size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_memory_data_size
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_memory_data_size:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DMA_MemoryDataSize_Byte   ((uint32_t)0x00000000)
 
+#define DMA_MemoryDataSize_HalfWord   ((uint32_t)0x00002000)
 
+#define DMA_MemoryDataSize_Word   ((uint32_t)0x00004000)
 
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_MEMORY_DATA_SIZE( SIZE)
+
+Value:
(((SIZE) == DMA_MemoryDataSize_Byte) || \
+
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+
((SIZE) == DMA_MemoryDataSize_Word ))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__memory__data__size.map b/group___d_m_a__memory__data__size.map new file mode 100644 index 0000000..2e5fb55 --- /dev/null +++ b/group___d_m_a__memory__data__size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__memory__data__size.md5 b/group___d_m_a__memory__data__size.md5 new file mode 100644 index 0000000..90e9bc6 --- /dev/null +++ b/group___d_m_a__memory__data__size.md5 @@ -0,0 +1 @@ +f85bbbbd03c474801b27231e4d2711b6 \ No newline at end of file diff --git a/group___d_m_a__memory__data__size.png b/group___d_m_a__memory__data__size.png new file mode 100644 index 0000000..cbb61d9 Binary files /dev/null and b/group___d_m_a__memory__data__size.png differ diff --git a/group___d_m_a__memory__incremented__mode.html b/group___d_m_a__memory__incremented__mode.html new file mode 100644 index 0000000..f7bcc11 --- /dev/null +++ b/group___d_m_a__memory__incremented__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_memory_incremented_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_memory_incremented_mode
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_memory_incremented_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_MemoryInc_Enable   ((uint32_t)0x00000400)
 
+#define DMA_MemoryInc_Disable   ((uint32_t)0x00000000)
 
#define IS_DMA_MEMORY_INC_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_MEMORY_INC_STATE( STATE)
+
+Value:
(((STATE) == DMA_MemoryInc_Enable) || \
+
((STATE) == DMA_MemoryInc_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__memory__incremented__mode.map b/group___d_m_a__memory__incremented__mode.map new file mode 100644 index 0000000..91eb5a6 --- /dev/null +++ b/group___d_m_a__memory__incremented__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__memory__incremented__mode.md5 b/group___d_m_a__memory__incremented__mode.md5 new file mode 100644 index 0000000..eb0b919 --- /dev/null +++ b/group___d_m_a__memory__incremented__mode.md5 @@ -0,0 +1 @@ +833622351a902249fa10aa76a2d5c9ca \ No newline at end of file diff --git a/group___d_m_a__memory__incremented__mode.png b/group___d_m_a__memory__incremented__mode.png new file mode 100644 index 0000000..89f130f Binary files /dev/null and b/group___d_m_a__memory__incremented__mode.png differ diff --git a/group___d_m_a__memory__targets__definitions.html b/group___d_m_a__memory__targets__definitions.html new file mode 100644 index 0000000..a18208d --- /dev/null +++ b/group___d_m_a__memory__targets__definitions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: DMA_memory_targets_definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_memory_targets_definitions
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_memory_targets_definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_Memory_0   ((uint32_t)0x00000000)
 
+#define DMA_Memory_1   ((uint32_t)0x00080000)
 
+#define IS_DMA_CURRENT_MEM(MEM)   (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__memory__targets__definitions.map b/group___d_m_a__memory__targets__definitions.map new file mode 100644 index 0000000..a066960 --- /dev/null +++ b/group___d_m_a__memory__targets__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__memory__targets__definitions.md5 b/group___d_m_a__memory__targets__definitions.md5 new file mode 100644 index 0000000..e224b42 --- /dev/null +++ b/group___d_m_a__memory__targets__definitions.md5 @@ -0,0 +1 @@ +5d15ec7c788edbae153d7178130d825c \ No newline at end of file diff --git a/group___d_m_a__memory__targets__definitions.png b/group___d_m_a__memory__targets__definitions.png new file mode 100644 index 0000000..0ac012c Binary files /dev/null and b/group___d_m_a__memory__targets__definitions.png differ diff --git a/group___d_m_a__peripheral__burst.html b/group___d_m_a__peripheral__burst.html new file mode 100644 index 0000000..18f490b --- /dev/null +++ b/group___d_m_a__peripheral__burst.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: DMA_peripheral_burst + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_peripheral_burst
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_peripheral_burst:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA_PeripheralBurst_Single   ((uint32_t)0x00000000)
 
+#define DMA_PeripheralBurst_INC4   ((uint32_t)0x00200000)
 
+#define DMA_PeripheralBurst_INC8   ((uint32_t)0x00400000)
 
+#define DMA_PeripheralBurst_INC16   ((uint32_t)0x00600000)
 
#define IS_DMA_PERIPHERAL_BURST(BURST)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_PERIPHERAL_BURST( BURST)
+
+Value:
(((BURST) == DMA_PeripheralBurst_Single) || \
+
((BURST) == DMA_PeripheralBurst_INC4) || \
+
((BURST) == DMA_PeripheralBurst_INC8) || \
+
((BURST) == DMA_PeripheralBurst_INC16))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__peripheral__burst.map b/group___d_m_a__peripheral__burst.map new file mode 100644 index 0000000..888847c --- /dev/null +++ b/group___d_m_a__peripheral__burst.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__peripheral__burst.md5 b/group___d_m_a__peripheral__burst.md5 new file mode 100644 index 0000000..8fdbbde --- /dev/null +++ b/group___d_m_a__peripheral__burst.md5 @@ -0,0 +1 @@ +5f0b3944cd272dbd93d8235f6a44d80d \ No newline at end of file diff --git a/group___d_m_a__peripheral__burst.png b/group___d_m_a__peripheral__burst.png new file mode 100644 index 0000000..d7a08f8 Binary files /dev/null and b/group___d_m_a__peripheral__burst.png differ diff --git a/group___d_m_a__peripheral__data__size.html b/group___d_m_a__peripheral__data__size.html new file mode 100644 index 0000000..149290b --- /dev/null +++ b/group___d_m_a__peripheral__data__size.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: DMA_peripheral_data_size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_peripheral_data_size
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_peripheral_data_size:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define DMA_PeripheralDataSize_Byte   ((uint32_t)0x00000000)
 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800)
 
+#define DMA_PeripheralDataSize_Word   ((uint32_t)0x00001000)
 
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_PERIPHERAL_DATA_SIZE( SIZE)
+
+Value:
(((SIZE) == DMA_PeripheralDataSize_Byte) || \
+
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+
((SIZE) == DMA_PeripheralDataSize_Word))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__peripheral__data__size.map b/group___d_m_a__peripheral__data__size.map new file mode 100644 index 0000000..d098919 --- /dev/null +++ b/group___d_m_a__peripheral__data__size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__peripheral__data__size.md5 b/group___d_m_a__peripheral__data__size.md5 new file mode 100644 index 0000000..84505e3 --- /dev/null +++ b/group___d_m_a__peripheral__data__size.md5 @@ -0,0 +1 @@ +03f93240d234f6b0e2dd3feb17a796e5 \ No newline at end of file diff --git a/group___d_m_a__peripheral__data__size.png b/group___d_m_a__peripheral__data__size.png new file mode 100644 index 0000000..b07f5b6 Binary files /dev/null and b/group___d_m_a__peripheral__data__size.png differ diff --git a/group___d_m_a__peripheral__increment__offset.html b/group___d_m_a__peripheral__increment__offset.html new file mode 100644 index 0000000..82c85ba --- /dev/null +++ b/group___d_m_a__peripheral__increment__offset.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_peripheral_increment_offset + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_peripheral_increment_offset
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_peripheral_increment_offset:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_PINCOS_Psize   ((uint32_t)0x00000000)
 
+#define DMA_PINCOS_WordAligned   ((uint32_t)0x00008000)
 
#define IS_DMA_PINCOS_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_PINCOS_SIZE( SIZE)
+
+Value:
(((SIZE) == DMA_PINCOS_Psize) || \
+
((SIZE) == DMA_PINCOS_WordAligned))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__peripheral__increment__offset.map b/group___d_m_a__peripheral__increment__offset.map new file mode 100644 index 0000000..5c69a33 --- /dev/null +++ b/group___d_m_a__peripheral__increment__offset.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__peripheral__increment__offset.md5 b/group___d_m_a__peripheral__increment__offset.md5 new file mode 100644 index 0000000..35088b1 --- /dev/null +++ b/group___d_m_a__peripheral__increment__offset.md5 @@ -0,0 +1 @@ +90190f40129635a963c8ea8f0c8a3b77 \ No newline at end of file diff --git a/group___d_m_a__peripheral__increment__offset.png b/group___d_m_a__peripheral__increment__offset.png new file mode 100644 index 0000000..e688d68 Binary files /dev/null and b/group___d_m_a__peripheral__increment__offset.png differ diff --git a/group___d_m_a__peripheral__incremented__mode.html b/group___d_m_a__peripheral__incremented__mode.html new file mode 100644 index 0000000..c4c4746 --- /dev/null +++ b/group___d_m_a__peripheral__incremented__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: DMA_peripheral_incremented_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_peripheral_incremented_mode
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_peripheral_incremented_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define DMA_PeripheralInc_Enable   ((uint32_t)0x00000200)
 
+#define DMA_PeripheralInc_Disable   ((uint32_t)0x00000000)
 
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_PERIPHERAL_INC_STATE( STATE)
+
+Value:
(((STATE) == DMA_PeripheralInc_Enable) || \
+
((STATE) == DMA_PeripheralInc_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__peripheral__incremented__mode.map b/group___d_m_a__peripheral__incremented__mode.map new file mode 100644 index 0000000..cffda0f --- /dev/null +++ b/group___d_m_a__peripheral__incremented__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__peripheral__incremented__mode.md5 b/group___d_m_a__peripheral__incremented__mode.md5 new file mode 100644 index 0000000..4d571c1 --- /dev/null +++ b/group___d_m_a__peripheral__incremented__mode.md5 @@ -0,0 +1 @@ +dfe334a267e252159f86e170a3880dfe \ No newline at end of file diff --git a/group___d_m_a__peripheral__incremented__mode.png b/group___d_m_a__peripheral__incremented__mode.png new file mode 100644 index 0000000..23670ba Binary files /dev/null and b/group___d_m_a__peripheral__incremented__mode.png differ diff --git a/group___d_m_a__priority__level.html b/group___d_m_a__priority__level.html new file mode 100644 index 0000000..1c114a5 --- /dev/null +++ b/group___d_m_a__priority__level.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: DMA_priority_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
DMA_priority_level
STM32F4xx_StdPeriph_Driver » DMA » DMA_Exported_Constants
+
+
+
+Collaboration diagram for DMA_priority_level:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define DMA_Priority_Low   ((uint32_t)0x00000000)
 
+#define DMA_Priority_Medium   ((uint32_t)0x00010000)
 
+#define DMA_Priority_High   ((uint32_t)0x00020000)
 
+#define DMA_Priority_VeryHigh   ((uint32_t)0x00030000)
 
#define IS_DMA_PRIORITY(PRIORITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_DMA_PRIORITY( PRIORITY)
+
+Value:
(((PRIORITY) == DMA_Priority_Low ) || \
+
((PRIORITY) == DMA_Priority_Medium) || \
+
((PRIORITY) == DMA_Priority_High) || \
+
((PRIORITY) == DMA_Priority_VeryHigh))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___d_m_a__priority__level.map b/group___d_m_a__priority__level.map new file mode 100644 index 0000000..a7991c3 --- /dev/null +++ b/group___d_m_a__priority__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___d_m_a__priority__level.md5 b/group___d_m_a__priority__level.md5 new file mode 100644 index 0000000..720bbd3 --- /dev/null +++ b/group___d_m_a__priority__level.md5 @@ -0,0 +1 @@ +18113e37e0e5a0d70cb18b6b87ead0d2 \ No newline at end of file diff --git a/group___d_m_a__priority__level.png b/group___d_m_a__priority__level.png new file mode 100644 index 0000000..ffe6fcd Binary files /dev/null and b/group___d_m_a__priority__level.png differ diff --git a/group___data___rate__selection.html b/group___data___rate__selection.html new file mode 100644 index 0000000..0a5a45c --- /dev/null +++ b/group___data___rate__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Data_Rate_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Data_Rate_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Data_Rate_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_DATARATE_100   ((uint8_t)0x00)
 
+#define LIS302DL_DATARATE_400   ((uint8_t)0x80)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___data___rate__selection.map b/group___data___rate__selection.map new file mode 100644 index 0000000..add4c75 --- /dev/null +++ b/group___data___rate__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___data___rate__selection.md5 b/group___data___rate__selection.md5 new file mode 100644 index 0000000..2ec08ad --- /dev/null +++ b/group___data___rate__selection.md5 @@ -0,0 +1 @@ +ebf3210a4051407f59e7ce74e075a0d0 \ No newline at end of file diff --git a/group___data___rate__selection.png b/group___data___rate__selection.png new file mode 100644 index 0000000..4b26026 Binary files /dev/null and b/group___data___rate__selection.png differ diff --git a/group___direction___x_y_z__selection.html b/group___direction___x_y_z__selection.html new file mode 100644 index 0000000..7e63b40 --- /dev/null +++ b/group___direction___x_y_z__selection.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: Direction_XYZ_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
Direction_XYZ_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Direction_XYZ_selection:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define LIS302DL_X_ENABLE   ((uint8_t)0x01)
 
+#define LIS302DL_Y_ENABLE   ((uint8_t)0x02)
 
+#define LIS302DL_Z_ENABLE   ((uint8_t)0x04)
 
+#define LIS302DL_XYZ_ENABLE   ((uint8_t)0x07)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___direction___x_y_z__selection.map b/group___direction___x_y_z__selection.map new file mode 100644 index 0000000..2ea454a --- /dev/null +++ b/group___direction___x_y_z__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___direction___x_y_z__selection.md5 b/group___direction___x_y_z__selection.md5 new file mode 100644 index 0000000..4867059 --- /dev/null +++ b/group___direction___x_y_z__selection.md5 @@ -0,0 +1 @@ +3ba4aaffae147c562a11185f420ff902 \ No newline at end of file diff --git a/group___direction___x_y_z__selection.png b/group___direction___x_y_z__selection.png new file mode 100644 index 0000000..d0f278a Binary files /dev/null and b/group___direction___x_y_z__selection.png differ diff --git a/group___double___click___interrupt___x_y_z__selection.html b/group___double___click___interrupt___x_y_z__selection.html new file mode 100644 index 0000000..41f8012 --- /dev/null +++ b/group___double___click___interrupt___x_y_z__selection.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: Double_Click_Interrupt_XYZ_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
Double_Click_Interrupt_XYZ_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Double_Click_Interrupt_XYZ_selection:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE   ((uint8_t)0x00)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE   ((uint8_t)0x02)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE   ((uint8_t)0x08)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE   ((uint8_t)0x20)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE   ((uint8_t)0x2A)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___double___click___interrupt___x_y_z__selection.map b/group___double___click___interrupt___x_y_z__selection.map new file mode 100644 index 0000000..e98935a --- /dev/null +++ b/group___double___click___interrupt___x_y_z__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___double___click___interrupt___x_y_z__selection.md5 b/group___double___click___interrupt___x_y_z__selection.md5 new file mode 100644 index 0000000..16b3cfb --- /dev/null +++ b/group___double___click___interrupt___x_y_z__selection.md5 @@ -0,0 +1 @@ +7ee56e57f8217d9b967db727ead385fb \ No newline at end of file diff --git a/group___double___click___interrupt___x_y_z__selection.png b/group___double___click___interrupt___x_y_z__selection.png new file mode 100644 index 0000000..882f39d Binary files /dev/null and b/group___double___click___interrupt___x_y_z__selection.png differ diff --git a/group___e_x_t_i.html b/group___e_x_t_i.html new file mode 100644 index 0000000..df18dcb --- /dev/null +++ b/group___e_x_t_i.html @@ -0,0 +1,446 @@ + + + + + + +discoverpixy: EXTI + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Enumerations | +Functions
+
+
EXTI
STM32F4xx_StdPeriph_Driver
+
+
+ +

EXTI driver modules. +More...

+
+Collaboration diagram for EXTI:
+
+
+ + +
+
+ + + + + + +

+Modules

 EXTI_Exported_Constants
 
 EXTI_Private_Functions
 
+ + + + +

+Classes

struct  EXTI_InitTypeDef
 EXTI Init Structure definition. More...
 
+ + + + + + + +

+Macros

+#define IS_EXTI_MODE(MODE)   (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
 
#define IS_EXTI_TRIGGER(TRIGGER)
 
+#define EXTI_LINENONE   ((uint32_t)0x00000) /* No interrupt selected */
 
+ + + + + + + +

+Enumerations

enum  EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, +EXTI_Mode_Event = 0x04 + }
 EXTI mode enumeration.
 
enum  EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, +EXTI_Trigger_Falling = 0x0C, +EXTI_Trigger_Rising_Falling = 0x10 + }
 EXTI Trigger enumeration.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void EXTI_DeInit (void)
 Deinitializes the EXTI peripheral registers to their default reset values. More...
 
void EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
 Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct. More...
 
void EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
 Fills each EXTI_InitStruct member with its reset value. More...
 
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
 Generates a Software interrupt on selected EXTI line. More...
 
FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line flag is set or not. More...
 
void EXTI_ClearFlag (uint32_t EXTI_Line)
 Clears the EXTI's line pending flags. More...
 
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line is asserted or not. More...
 
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
 Clears the EXTI's line pending bits. More...
 
+

Detailed Description

+

EXTI driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_EXTI_TRIGGER( TRIGGER)
+
+Value:
(((TRIGGER) == EXTI_Trigger_Rising) || \
+
((TRIGGER) == EXTI_Trigger_Falling) || \
+
((TRIGGER) == EXTI_Trigger_Rising_Falling))
+
+
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void EXTI_ClearFlag (uint32_t EXTI_Line)
+
+ +

Clears the EXTI's line pending flags.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
+
+ +

Clears the EXTI's line pending bits.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_DeInit (void )
+
+ +

Deinitializes the EXTI peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
+
+ +

Generates a Software interrupt on selected EXTI line.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line on which the software interrupt will be generated. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
+
+ +

Checks whether the specified EXTI line flag is set or not.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line flag to check. This parameter can be EXTI_Linex where x can be(0..22)
+
+
+
Return values
+ + +
Thenew state of EXTI_Line (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
+
+ +

Checks whether the specified EXTI line is asserted or not.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line to check. This parameter can be EXTI_Linex where x can be(0..22)
+
+
+
Return values
+ + +
Thenew state of EXTI_Line (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_Init (EXTI_InitTypeDef * EXTI_InitStruct)
+
+ +

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

+
Parameters
+ + +
EXTI_InitStructpointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void EXTI_StructInit (EXTI_InitTypeDef * EXTI_InitStruct)
+
+ +

Fills each EXTI_InitStruct member with its reset value.

+
Parameters
+ + +
EXTI_InitStructpointer to a EXTI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i.map b/group___e_x_t_i.map new file mode 100644 index 0000000..263a2a8 --- /dev/null +++ b/group___e_x_t_i.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___e_x_t_i.md5 b/group___e_x_t_i.md5 new file mode 100644 index 0000000..267500e --- /dev/null +++ b/group___e_x_t_i.md5 @@ -0,0 +1 @@ +1ce04b88c977a2ff754496abd84f7397 \ No newline at end of file diff --git a/group___e_x_t_i.png b/group___e_x_t_i.png new file mode 100644 index 0000000..3dbdb70 Binary files /dev/null and b/group___e_x_t_i.png differ diff --git a/group___e_x_t_i___exported___constants.html b/group___e_x_t_i___exported___constants.html new file mode 100644 index 0000000..bcc3767 --- /dev/null +++ b/group___e_x_t_i___exported___constants.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: EXTI_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
EXTI_Exported_Constants
STM32F4xx_StdPeriph_Driver » EXTI
+
+
+
+Collaboration diagram for EXTI_Exported_Constants:
+
+
+ + +
+
+ + + + +

+Modules

 EXTI_Lines
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i___exported___constants.map b/group___e_x_t_i___exported___constants.map new file mode 100644 index 0000000..7b8e8af --- /dev/null +++ b/group___e_x_t_i___exported___constants.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___e_x_t_i___exported___constants.md5 b/group___e_x_t_i___exported___constants.md5 new file mode 100644 index 0000000..550e74d --- /dev/null +++ b/group___e_x_t_i___exported___constants.md5 @@ -0,0 +1 @@ +991957fe8fc77991494494162bab6ff0 \ No newline at end of file diff --git a/group___e_x_t_i___exported___constants.png b/group___e_x_t_i___exported___constants.png new file mode 100644 index 0000000..3333c71 Binary files /dev/null and b/group___e_x_t_i___exported___constants.png differ diff --git a/group___e_x_t_i___group1.html b/group___e_x_t_i___group1.html new file mode 100644 index 0000000..708adf4 --- /dev/null +++ b/group___e_x_t_i___group1.html @@ -0,0 +1,254 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » EXTI » EXTI_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void EXTI_DeInit (void)
 Deinitializes the EXTI peripheral registers to their default reset values. More...
 
void EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
 Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct. More...
 
void EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
 Fills each EXTI_InitStruct member with its reset value. More...
 
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
 Generates a Software interrupt on selected EXTI line. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void EXTI_DeInit (void )
+
+ +

Deinitializes the EXTI peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
+
+ +

Generates a Software interrupt on selected EXTI line.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line on which the software interrupt will be generated. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_Init (EXTI_InitTypeDef * EXTI_InitStruct)
+
+ +

Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.

+
Parameters
+ + +
EXTI_InitStructpointer to a EXTI_InitTypeDef structure that contains the configuration information for the EXTI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void EXTI_StructInit (EXTI_InitTypeDef * EXTI_InitStruct)
+
+ +

Fills each EXTI_InitStruct member with its reset value.

+
Parameters
+ + +
EXTI_InitStructpointer to a EXTI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i___group1.map b/group___e_x_t_i___group1.map new file mode 100644 index 0000000..2f81dfa --- /dev/null +++ b/group___e_x_t_i___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___e_x_t_i___group1.md5 b/group___e_x_t_i___group1.md5 new file mode 100644 index 0000000..32d3f30 --- /dev/null +++ b/group___e_x_t_i___group1.md5 @@ -0,0 +1 @@ +39e7f8b4dc9ed9f339e566ce087b167c \ No newline at end of file diff --git a/group___e_x_t_i___group1.png b/group___e_x_t_i___group1.png new file mode 100644 index 0000000..fca63f2 Binary files /dev/null and b/group___e_x_t_i___group1.png differ diff --git a/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map new file mode 100644 index 0000000..d779761 --- /dev/null +++ b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 new file mode 100644 index 0000000..a2b14bb --- /dev/null +++ b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 @@ -0,0 +1 @@ +f7f76d764fe9f09dcad23d388720d684 \ No newline at end of file diff --git a/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png new file mode 100644 index 0000000..0dd8f14 Binary files /dev/null and b/group___e_x_t_i___group1_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png differ diff --git a/group___e_x_t_i___group2.html b/group___e_x_t_i___group2.html new file mode 100644 index 0000000..79d86d7 --- /dev/null +++ b/group___e_x_t_i___group2.html @@ -0,0 +1,245 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » EXTI » EXTI_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line flag is set or not. More...
 
void EXTI_ClearFlag (uint32_t EXTI_Line)
 Clears the EXTI's line pending flags. More...
 
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line is asserted or not. More...
 
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
 Clears the EXTI's line pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void EXTI_ClearFlag (uint32_t EXTI_Line)
+
+ +

Clears the EXTI's line pending flags.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI lines flags to clear. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
+
+ +

Clears the EXTI's line pending bits.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI lines to clear. This parameter can be any combination of EXTI_Linex where x can be (0..22)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
+
+ +

Checks whether the specified EXTI line flag is set or not.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line flag to check. This parameter can be EXTI_Linex where x can be(0..22)
+
+
+
Return values
+ + +
Thenew state of EXTI_Line (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
+
+ +

Checks whether the specified EXTI line is asserted or not.

+
Parameters
+ + +
EXTI_Linespecifies the EXTI line to check. This parameter can be EXTI_Linex where x can be(0..22)
+
+
+
Return values
+ + +
Thenew state of EXTI_Line (SET or RESET).
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i___group2.map b/group___e_x_t_i___group2.map new file mode 100644 index 0000000..1c1c385 --- /dev/null +++ b/group___e_x_t_i___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___e_x_t_i___group2.md5 b/group___e_x_t_i___group2.md5 new file mode 100644 index 0000000..2cfe35b --- /dev/null +++ b/group___e_x_t_i___group2.md5 @@ -0,0 +1 @@ +47d2a4d70ff30c885d9dc3d1fd7d89fe \ No newline at end of file diff --git a/group___e_x_t_i___group2.png b/group___e_x_t_i___group2.png new file mode 100644 index 0000000..dde7ec3 Binary files /dev/null and b/group___e_x_t_i___group2.png differ diff --git a/group___e_x_t_i___lines.html b/group___e_x_t_i___lines.html new file mode 100644 index 0000000..def7955 --- /dev/null +++ b/group___e_x_t_i___lines.html @@ -0,0 +1,508 @@ + + + + + + +discoverpixy: EXTI_Lines + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
EXTI_Lines
STM32F4xx_StdPeriph_Driver » EXTI » EXTI_Exported_Constants
+
+
+
+Collaboration diagram for EXTI_Lines:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define EXTI_Line0   ((uint32_t)0x00001)
 
#define EXTI_Line1   ((uint32_t)0x00002)
 
#define EXTI_Line2   ((uint32_t)0x00004)
 
#define EXTI_Line3   ((uint32_t)0x00008)
 
#define EXTI_Line4   ((uint32_t)0x00010)
 
#define EXTI_Line5   ((uint32_t)0x00020)
 
#define EXTI_Line6   ((uint32_t)0x00040)
 
#define EXTI_Line7   ((uint32_t)0x00080)
 
#define EXTI_Line8   ((uint32_t)0x00100)
 
#define EXTI_Line9   ((uint32_t)0x00200)
 
#define EXTI_Line10   ((uint32_t)0x00400)
 
#define EXTI_Line11   ((uint32_t)0x00800)
 
#define EXTI_Line12   ((uint32_t)0x01000)
 
#define EXTI_Line13   ((uint32_t)0x02000)
 
#define EXTI_Line14   ((uint32_t)0x04000)
 
#define EXTI_Line15   ((uint32_t)0x08000)
 
#define EXTI_Line16   ((uint32_t)0x10000)
 
#define EXTI_Line17   ((uint32_t)0x20000)
 
#define EXTI_Line18   ((uint32_t)0x40000)
 
#define EXTI_Line19   ((uint32_t)0x80000)
 
#define EXTI_Line20   ((uint32_t)0x00100000)
 
#define EXTI_Line21   ((uint32_t)0x00200000)
 
#define EXTI_Line22   ((uint32_t)0x00400000)
 
+#define IS_EXTI_LINE(LINE)   ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
 
#define IS_GET_EXTI_LINE(LINE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define EXTI_Line0   ((uint32_t)0x00001)
+
+

External interrupt line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_Line1   ((uint32_t)0x00002)
+
+

External interrupt line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_Line10   ((uint32_t)0x00400)
+
+

External interrupt line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_Line11   ((uint32_t)0x00800)
+
+

External interrupt line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_Line12   ((uint32_t)0x01000)
+
+

External interrupt line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_Line13   ((uint32_t)0x02000)
+
+

External interrupt line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_Line14   ((uint32_t)0x04000)
+
+

External interrupt line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_Line15   ((uint32_t)0x08000)
+
+

External interrupt line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_Line16   ((uint32_t)0x10000)
+
+

External interrupt line 16 Connected to the PVD Output

+ +
+
+ +
+
+ + + + +
#define EXTI_Line17   ((uint32_t)0x20000)
+
+

External interrupt line 17 Connected to the RTC Alarm event

+ +
+
+ +
+
+ + + + +
#define EXTI_Line18   ((uint32_t)0x40000)
+
+

External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event

+ +
+
+ +
+
+ + + + +
#define EXTI_Line19   ((uint32_t)0x80000)
+
+

External interrupt line 19 Connected to the Ethernet Wakeup event

+ +
+
+ +
+
+ + + + +
#define EXTI_Line2   ((uint32_t)0x00004)
+
+

External interrupt line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_Line20   ((uint32_t)0x00100000)
+
+

External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event

+ +
+
+ +
+
+ + + + +
#define EXTI_Line21   ((uint32_t)0x00200000)
+
+

External interrupt line 21 Connected to the RTC Tamper and Time Stamp events

+ +
+
+ +
+
+ + + + +
#define EXTI_Line22   ((uint32_t)0x00400000)
+
+

External interrupt line 22 Connected to the RTC Wakeup event

+ +
+
+ +
+
+ + + + +
#define EXTI_Line3   ((uint32_t)0x00008)
+
+

External interrupt line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_Line4   ((uint32_t)0x00010)
+
+

External interrupt line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_Line5   ((uint32_t)0x00020)
+
+

External interrupt line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_Line6   ((uint32_t)0x00040)
+
+

External interrupt line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_Line7   ((uint32_t)0x00080)
+
+

External interrupt line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_Line8   ((uint32_t)0x00100)
+
+

External interrupt line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_Line9   ((uint32_t)0x00200)
+
+

External interrupt line 9

+ +
+
+ +
+
+ + + + + + + + +
#define IS_GET_EXTI_LINE( LINE)
+
+Value:
(((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
+
((LINE) == EXTI_Line22))
+
EXTI_Line1
#define EXTI_Line1
Definition: stm32f4xx_exti.h:106
+
EXTI_Line13
#define EXTI_Line13
Definition: stm32f4xx_exti.h:118
+
EXTI_Line17
#define EXTI_Line17
Definition: stm32f4xx_exti.h:122
+
EXTI_Line2
#define EXTI_Line2
Definition: stm32f4xx_exti.h:107
+
EXTI_Line16
#define EXTI_Line16
Definition: stm32f4xx_exti.h:121
+
EXTI_Line19
#define EXTI_Line19
Definition: stm32f4xx_exti.h:124
+
EXTI_Line10
#define EXTI_Line10
Definition: stm32f4xx_exti.h:115
+
EXTI_Line11
#define EXTI_Line11
Definition: stm32f4xx_exti.h:116
+
EXTI_Line14
#define EXTI_Line14
Definition: stm32f4xx_exti.h:119
+
EXTI_Line12
#define EXTI_Line12
Definition: stm32f4xx_exti.h:117
+
EXTI_Line7
#define EXTI_Line7
Definition: stm32f4xx_exti.h:112
+
EXTI_Line18
#define EXTI_Line18
Definition: stm32f4xx_exti.h:123
+
EXTI_Line20
#define EXTI_Line20
Definition: stm32f4xx_exti.h:125
+
EXTI_Line5
#define EXTI_Line5
Definition: stm32f4xx_exti.h:110
+
EXTI_Line21
#define EXTI_Line21
Definition: stm32f4xx_exti.h:126
+
EXTI_Line0
#define EXTI_Line0
Definition: stm32f4xx_exti.h:105
+
EXTI_Line15
#define EXTI_Line15
Definition: stm32f4xx_exti.h:120
+
EXTI_Line3
#define EXTI_Line3
Definition: stm32f4xx_exti.h:108
+
EXTI_Line9
#define EXTI_Line9
Definition: stm32f4xx_exti.h:114
+
EXTI_Line6
#define EXTI_Line6
Definition: stm32f4xx_exti.h:111
+
EXTI_Line4
#define EXTI_Line4
Definition: stm32f4xx_exti.h:109
+
EXTI_Line8
#define EXTI_Line8
Definition: stm32f4xx_exti.h:113
+
EXTI_Line22
#define EXTI_Line22
Definition: stm32f4xx_exti.h:127
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i___lines.map b/group___e_x_t_i___lines.map new file mode 100644 index 0000000..44d07e2 --- /dev/null +++ b/group___e_x_t_i___lines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___e_x_t_i___lines.md5 b/group___e_x_t_i___lines.md5 new file mode 100644 index 0000000..497827a --- /dev/null +++ b/group___e_x_t_i___lines.md5 @@ -0,0 +1 @@ +7d26c7ab768e396d6a55c35187cf42b2 \ No newline at end of file diff --git a/group___e_x_t_i___lines.png b/group___e_x_t_i___lines.png new file mode 100644 index 0000000..b27de3e Binary files /dev/null and b/group___e_x_t_i___lines.png differ diff --git a/group___e_x_t_i___private___functions.html b/group___e_x_t_i___private___functions.html new file mode 100644 index 0000000..1b1704d --- /dev/null +++ b/group___e_x_t_i___private___functions.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: EXTI_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
EXTI_Private_Functions
STM32F4xx_StdPeriph_Driver » EXTI
+
+
+
+Collaboration diagram for EXTI_Private_Functions:
+
+
+ + +
+
+ + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___e_x_t_i___private___functions.map b/group___e_x_t_i___private___functions.map new file mode 100644 index 0000000..f8456f0 --- /dev/null +++ b/group___e_x_t_i___private___functions.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___e_x_t_i___private___functions.md5 b/group___e_x_t_i___private___functions.md5 new file mode 100644 index 0000000..8cda65f --- /dev/null +++ b/group___e_x_t_i___private___functions.md5 @@ -0,0 +1 @@ +178f4d39c7fa88b1a67d96c88e1c0cfe \ No newline at end of file diff --git a/group___e_x_t_i___private___functions.png b/group___e_x_t_i___private___functions.png new file mode 100644 index 0000000..423ade7 Binary files /dev/null and b/group___e_x_t_i___private___functions.png differ diff --git a/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map new file mode 100644 index 0000000..d779761 --- /dev/null +++ b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 new file mode 100644 index 0000000..a2b14bb --- /dev/null +++ b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.md5 @@ -0,0 +1 @@ +f7f76d764fe9f09dcad23d388720d684 \ No newline at end of file diff --git a/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png new file mode 100644 index 0000000..0dd8f14 Binary files /dev/null and b/group___e_x_t_i_ga8c9ce6352a3a2dfc8fc9287cb24c6501_icgraph.png differ diff --git a/group___exported__constants.html b/group___exported__constants.html new file mode 100644 index 0000000..c8f7d57 --- /dev/null +++ b/group___exported__constants.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Exported_constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
Exported_constants
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Exported_constants:
+
+
+ + +
+
+ + + + + + +

+Modules

 Peripheral_Registers_Bits_Definition
 
 Exported_macro
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___exported__constants.map b/group___exported__constants.map new file mode 100644 index 0000000..924cf50 --- /dev/null +++ b/group___exported__constants.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___exported__constants.md5 b/group___exported__constants.md5 new file mode 100644 index 0000000..1648b25 --- /dev/null +++ b/group___exported__constants.md5 @@ -0,0 +1 @@ +cd32c3255f9863cc98a445d3c9d1636f \ No newline at end of file diff --git a/group___exported__constants.png b/group___exported__constants.png new file mode 100644 index 0000000..e51286e Binary files /dev/null and b/group___exported__constants.png differ diff --git a/group___exported__macro.html b/group___exported__macro.html new file mode 100644 index 0000000..102b4a0 --- /dev/null +++ b/group___exported__macro.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: Exported_macro + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Exported_macro
CMSIS » Stm32f4xx » Exported_constants
+
+
+
+Collaboration diagram for Exported_macro:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define SET_BIT(REG, BIT)   ((REG) |= (BIT))
 
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
 
+#define READ_BIT(REG, BIT)   ((REG) & (BIT))
 
+#define CLEAR_REG(REG)   ((REG) = (0x0))
 
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
 
+#define READ_REG(REG)   ((REG))
 
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)   WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___exported__macro.map b/group___exported__macro.map new file mode 100644 index 0000000..ef755bc --- /dev/null +++ b/group___exported__macro.map @@ -0,0 +1,3 @@ + + + diff --git a/group___exported__macro.md5 b/group___exported__macro.md5 new file mode 100644 index 0000000..c25b0be --- /dev/null +++ b/group___exported__macro.md5 @@ -0,0 +1 @@ +367f72e997d7079fa21cde863d47e93c \ No newline at end of file diff --git a/group___exported__macro.png b/group___exported__macro.png new file mode 100644 index 0000000..dd5fcf2 Binary files /dev/null and b/group___exported__macro.png differ diff --git a/group___exported__types.html b/group___exported__types.html new file mode 100644 index 0000000..11be33c --- /dev/null +++ b/group___exported__types.html @@ -0,0 +1,361 @@ + + + + + + +discoverpixy: Exported_types + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Typedefs | +Enumerations
+
+
Exported_types
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Exported_types:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FUNCTIONAL_STATE(STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

typedef int32_t s32
 
+typedef int16_t s16
 
+typedef int8_t s8
 
typedef const int32_t sc32
 
typedef const int16_t sc16
 
typedef const int8_t sc8
 
+typedef __IO int32_t vs32
 
+typedef __IO int16_t vs16
 
+typedef __IO int8_t vs8
 
typedef __I int32_t vsc32
 
typedef __I int16_t vsc16
 
typedef __I int8_t vsc8
 
+typedef uint32_t u32
 
+typedef uint16_t u16
 
+typedef uint8_t u8
 
typedef const uint32_t uc32
 
typedef const uint16_t uc16
 
typedef const uint8_t uc8
 
+typedef __IO uint32_t vu32
 
+typedef __IO uint16_t vu16
 
+typedef __IO uint8_t vu8
 
typedef __I uint32_t vuc32
 
typedef __I uint16_t vuc16
 
typedef __I uint8_t vuc8
 
+typedef enum FlagStatus ITStatus
 
+ + + + + + + +

+Enumerations

enum  FlagStatus { RESET = 0, +SET = !RESET + }
 
enum  FunctionalState { DISABLE = 0, +ENABLE = !DISABLE + }
 
enum  ErrorStatus { ERROR = 0, +SUCCESS = !ERROR + }
 
+

Detailed Description

+

Typedef Documentation

+ +
+
+ + + + +
typedef int32_t s32
+
+

< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose)

+ +
+
+ +
+
+ + + + +
typedef const int16_t sc16
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef const int32_t sc32
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef const int8_t sc8
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef const uint16_t uc16
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef const uint32_t uc32
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef const uint8_t uc8
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I int16_t vsc16
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I int32_t vsc32
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I int8_t vsc8
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I uint16_t vuc16
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I uint32_t vuc32
+
+

Read Only

+ +
+
+ +
+
+ + + + +
typedef __I uint8_t vuc8
+
+

Read Only

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___exported__types.map b/group___exported__types.map new file mode 100644 index 0000000..faa1192 --- /dev/null +++ b/group___exported__types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___exported__types.md5 b/group___exported__types.md5 new file mode 100644 index 0000000..9414796 --- /dev/null +++ b/group___exported__types.md5 @@ -0,0 +1 @@ +89974f87b30d53ee4dc18ab2eb25610d \ No newline at end of file diff --git a/group___exported__types.png b/group___exported__types.png new file mode 100644 index 0000000..6434afc Binary files /dev/null and b/group___exported__types.png differ diff --git a/group___f_l_a_s_h.html b/group___f_l_a_s_h.html new file mode 100644 index 0000000..a4103ca --- /dev/null +++ b/group___f_l_a_s_h.html @@ -0,0 +1,2015 @@ + + + + + + +discoverpixy: RAMFUNC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
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+
+ + +
+ +
+ +
+
+Modules | +Macros | +Enumerations | +Functions
+
+
RAMFUNC
STM32F4xx_StdPeriph_Driver
+
+
+ +

FLASH driver modules. +More...

+
+Collaboration diagram for RAMFUNC:
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+
+ + + + + + + + +

+Modules

 FLASH_Exported_Constants
 
 FLASH_Private_Functions
 
 FLASH_RAMFUNC_Private_Functions
 
+ + + +

+Macros

+#define SECTOR_MASK   ((uint32_t)0xFFFFFF07)
 
+ + + + +

+Enumerations

enum  FLASH_Status {
+  FLASH_BUSY = 1, +FLASH_ERROR_RD, +FLASH_ERROR_PGS, +FLASH_ERROR_PGP, +
+  FLASH_ERROR_PGA, +FLASH_ERROR_WRP, +FLASH_ERROR_PROGRAM, +FLASH_ERROR_OPERATION, +
+  FLASH_COMPLETE +
+ }
 FLASH Status.
 
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+Functions

void FLASH_SetLatency (uint32_t FLASH_Latency)
 Sets the code latency value. More...
 
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
 Enables or disables the Prefetch Buffer. More...
 
void FLASH_InstructionCacheCmd (FunctionalState NewState)
 Enables or disables the Instruction Cache feature. More...
 
void FLASH_DataCacheCmd (FunctionalState NewState)
 Enables or disables the Data Cache feature. More...
 
void FLASH_InstructionCacheReset (void)
 Resets the Instruction Cache. More...
 
void FLASH_DataCacheReset (void)
 Resets the Data Cache. More...
 
void FLASH_Unlock (void)
 Unlocks the FLASH control register access. More...
 
void FLASH_Lock (void)
 Locks the FLASH control register access. More...
 
FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector, uint8_t VoltageRange)
 Erases a specified FLASH Sector. More...
 
FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
 Erases all FLASH Sectors. More...
 
FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 1. More...
 
FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 2. More...
 
FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address, uint64_t Data)
 Programs a double word (64-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramWord (uint32_t Address, uint32_t Data)
 Programs a word (32-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
 Programs a half word (16-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramByte (uint32_t Address, uint8_t Data)
 Programs a byte (8-bit) at a specified address. More...
 
void FLASH_OB_Unlock (void)
 Unlocks the FLASH Option Control Registers access. More...
 
void FLASH_OB_Lock (void)
 Locks the FLASH Option Control Registers access. More...
 
void FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash. More...
 
void FLASH_OB_WRP1Config (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash. More...
 
void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
 Select the Protection Mode (SPRMOD). More...
 
void FLASH_OB_PCROPConfig (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash. More...
 
void FLASH_OB_PCROP1Config (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors. More...
 
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
 Sets the read protection level. More...
 
void FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. More...
 
void FLASH_OB_BORConfig (uint8_t OB_BOR)
 Sets the BOR Level. More...
 
void FLASH_OB_BootConfig (uint8_t OB_BOOT)
 Configure the Dual Bank Boot. More...
 
FLASH_Status FLASH_OB_Launch (void)
 Launch the option byte loading. More...
 
uint8_t FLASH_OB_GetUser (void)
 Returns the FLASH User Option Bytes values. More...
 
uint16_t FLASH_OB_GetWRP (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetWRP1 (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP1 (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
FlagStatus FLASH_OB_GetRDP (void)
 Returns the FLASH Read Protection level. More...
 
uint8_t FLASH_OB_GetBOR (void)
 Returns the FLASH BOR level. More...
 
void FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
 Enables or disables the specified FLASH interrupts. More...
 
FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
 Checks whether the specified FLASH flag is set or not. More...
 
void FLASH_ClearFlag (uint32_t FLASH_FLAG)
 Clears the FLASH's pending flags. More...
 
FLASH_Status FLASH_GetStatus (void)
 Returns the FLASH Status. More...
 
FLASH_Status FLASH_WaitForLastOperation (void)
 Waits for a FLASH operation to complete. More...
 
__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
 __RAM_FUNC definition More...
 
__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
 Enable/Disable the flash sleep while System Run. More...
 
+

Detailed Description

+

FLASH driver modules.

+

FLASH RAMFUNC driver modules.

+

Function Documentation

+ +
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void FLASH_ClearFlag (uint32_t FLASH_FLAG)
+
+ +

Clears the FLASH's pending flags.

+
Parameters
+ + +
FLASH_FLAGspecifies the FLASH flags to clear. This parameter can be any combination of the following values:
    +
  • FLASH_FLAG_EOP: FLASH End of Operation flag
    • +
  • FLASH_FLAG_OPERR: FLASH operation Error flag
    • +
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
    • +
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
    • +
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
    • +
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
    • +
  • FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
    • +
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Return values
+ + +
None
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void FLASH_DataCacheCmd (FunctionalState NewState)
+
+ +

Enables or disables the Data Cache feature.

+
Parameters
+ + +
NewStatenew state of the Data Cache. This parameter can be: ENABLE or DISABLE.
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Return values
+ + +
None
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void FLASH_DataCacheReset (void )
+
+ +

Resets the Data Cache.

+
Note
This function must be used only when the Data Cache is disabled.
+
Parameters
+ + +
None
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Return values
+ + +
None
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FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors in Bank 1.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
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Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors in Bank 2.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
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+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors.

+
Note
If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector,
uint8_t VoltageRange 
)
+
+ +

Erases a specified FLASH Sector.

+
Note
If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
FLASH_SectorThe Sector number to be erased.
+
+
+
Note
For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11.
+

For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_23.

+

For STM32F401xx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_5.

+

For STM32F411xE devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_7.

+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
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Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
+
+ +

__RAM_FUNC definition

+

__RAM_FUNC definition

+
Note
This mode is only available for STM32F411xx devices.
+
+This mode could n't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
+
Parameters
+ + +
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
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+
Return values
+ + +
None
+
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__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
+
+ +

Enable/Disable the flash sleep while System Run.

+
Note
This mode is only available for STM32F411xx devices.
+
+This mode could n't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
+
Parameters
+ + +
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
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+
Return values
+ + +
None
+
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FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
+
+ +

Checks whether the specified FLASH flag is set or not.

+
Parameters
+ + +
FLASH_FLAGspecifies the FLASH flag to check. This parameter can be one of the following values:
    +
  • FLASH_FLAG_EOP: FLASH End of Operation flag
    • +
  • FLASH_FLAG_OPERR: FLASH operation Error flag
    • +
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
    • +
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
    • +
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
    • +
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
    • +
  • FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
    • +
  • FLASH_FLAG_BSY: FLASH Busy flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of FLASH_FLAG (SET or RESET).
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FLASH_Status FLASH_GetStatus (void )
+
+ +

Returns the FLASH Status.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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void FLASH_InstructionCacheCmd (FunctionalState NewState)
+
+ +

Enables or disables the Instruction Cache feature.

+
Parameters
+ + +
NewStatenew state of the Instruction Cache. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
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void FLASH_InstructionCacheReset (void )
+
+ +

Resets the Instruction Cache.

+
Note
This function must be used only when the Instruction Cache is disabled.
+
Parameters
+ + +
None
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+
Return values
+ + +
None
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void FLASH_ITConfig (uint32_t FLASH_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified FLASH interrupts.

+
Parameters
+ + +
FLASH_ITspecifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • FLASH_IT_ERR: FLASH Error Interrupt
    • +
  • FLASH_IT_EOP: FLASH end of operation Interrupt
    • +
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Return values
+ + +
None
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void FLASH_Lock (void )
+
+ +

Locks the FLASH control register access.

+
Parameters
+ + +
None
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Return values
+ + +
None
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void FLASH_OB_BootConfig (uint8_t OB_BOOT)
+
+ +

Configure the Dual Bank Boot.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
OB_BOOTspecifies the Dual Bank Boot Option byte. This parameter can be one of the following values:
    +
  • OB_Dual_BootEnabled: Dual Bank Boot Enable
    • +
  • OB_Dual_BootDisabled: Dual Bank Boot Disabled
    • +
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Return values
+ + +
None
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void FLASH_OB_BORConfig (uint8_t OB_BOR)
+
+ +

Sets the BOR Level.

+
Parameters
+ + +
OB_BORspecifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
    +
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
    • +
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
    • +
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
    • +
  • OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
    • +
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Return values
+ + +
None
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uint8_t FLASH_OB_GetBOR (void )
+
+ +

Returns the FLASH BOR level.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH BOR level:
    +
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
    • +
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
    • +
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
    • +
  • OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
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uint16_t FLASH_OB_GetPCROP (void )
+
+ +

Returns the FLASH PC Read/Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH PC Read/Write Protection Option Bytes value
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uint16_t FLASH_OB_GetPCROP1 (void )
+
+ +

Returns the FLASH PC Read/Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH PC Read/Write Protection Option Bytes value
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FlagStatus FLASH_OB_GetRDP (void )
+
+ +

Returns the FLASH Read Protection level.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHReadOut Protection Status:
    +
  • SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
    • +
  • RESET, when OB_RDP_Level_0 is set
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uint8_t FLASH_OB_GetUser (void )
+
+ +

Returns the FLASH User Option Bytes values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).
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uint16_t FLASH_OB_GetWRP (void )
+
+ +

Returns the FLASH Write Protection Option Bytes value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH Write Protection Option Bytes value
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uint16_t FLASH_OB_GetWRP1 (void )
+
+ +

Returns the FLASH Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH Write Protection Option Bytes value
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FLASH_Status FLASH_OB_Launch (void )
+
+ +

Launch the option byte loading.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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void FLASH_OB_Lock (void )
+
+ +

Locks the FLASH Option Control Registers access.

+
Parameters
+ + +
None
+
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Return values
+ + +
None
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void FLASH_OB_PCROP1Config (uint32_t OB_PCROP,
FunctionalState NewState 
)
+
+ +

Enables or disables the read/write protection (PCROP) of the desired sectors.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + + +
OB_PCROPspecifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
    • +
  • OB_PCROP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
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Return values
+ + +
None
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void FLASH_OB_PCROPConfig (uint32_t OB_PCROP,
FunctionalState NewState 
)
+
+ +

Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash.

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
Parameters
+ + + +
OB_PCROPspecifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and OB_PCROP_Sector5 for STM32F401xx/411xE devices.
    • +
  • OB_PCROP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
+
+ +

Select the Protection Mode (SPRMOD).

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
+After PCROP activation, Option Byte modification is not possible. Exception made for the global Read Out Protection modification level (level1 to level0)
+
+Once SPRMOD bit is active unprotection of a protected sector is not possible
+
+Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+
+Some Precautions should be taken when activating the PCROP feature : The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 and WRPi = 1 (default value), then the user sector i is read/write protected. In order to avoid activation of PCROP Mode for undesired sectors, please follow the below safety sequence :
    +
  • Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
    • +
  • Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
    • +
  • Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
    • +
+
+
Parameters
+ + +
OB_PCROPSelect the Protection Mode of nWPRi bits This parameter can be one of the following values:
    +
  • OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
    • +
  • OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
+
+ +

Sets the read protection level.

+
Parameters
+ + +
OB_RDPspecifies the read protection level. This parameter can be one of the following values:
    +
  • OB_RDP_Level_0: No protection
    • +
  • OB_RDP_Level_1: Read protection of the memory
    • +
  • OB_RDP_Level_2: Full chip protection
    • +
+/!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+ + + + + + + + +
void FLASH_OB_Unlock (void )
+
+ +

Unlocks the FLASH Option Control Registers access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void FLASH_OB_UserConfig (uint8_t OB_IWDG,
uint8_t OB_STOP,
uint8_t OB_STDBY 
)
+
+ +

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

+
Parameters
+ + + + +
OB_IWDGSelects the IWDG mode This parameter can be one of the following values:
    +
  • OB_IWDG_SW: Software IWDG selected
    • +
  • OB_IWDG_HW: Hardware IWDG selected
    • +
+
OB_STOPReset event when entering STOP mode. This parameter can be one of the following values:
    +
  • OB_STOP_NoRST: No reset generated when entering in STOP
    • +
  • OB_STOP_RST: Reset generated when entering in STOP
    • +
+
OB_STDBYReset event when entering Standby mode. This parameter can be one of the following values:
    +
  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
    • +
  • OB_STDBY_RST: Reset generated when entering in STANDBY
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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void FLASH_OB_WRP1Config (uint32_t OB_WRP,
FunctionalState NewState 
)
+
+ +

Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+When the memory read out protection is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+
+Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+
Parameters
+ + + +
OB_WRPspecifies the sector(s) to be write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
    • +
  • OB_WRP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + + + + + + + + + + + +
void FLASH_OB_WRPConfig (uint32_t OB_WRP,
FunctionalState NewState 
)
+
+ +

Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash.

+
Note
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+
+Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+
Parameters
+ + + +
OB_WRPspecifies the sector(s) to be write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
    • +
  • OB_WRP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
+
+ +

Enables or disables the Prefetch Buffer.

+
Parameters
+ + +
NewStatenew state of the Prefetch Buffer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FLASH_Status FLASH_ProgramByte (uint32_t Address,
uint8_t Data 
)
+
+ +

Programs a byte (8-bit) at a specified address.

+
Note
This function can be used within all the device supply voltage ranges.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
+
+ +

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FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address,
uint64_t Data 
)
+
+ +

Programs a double word (64-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.7V to 3.6V and an External Vpp is present.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
+
+ +

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+ + + + + + + + + + + + + + + + + + +
FLASH_Status FLASH_ProgramHalfWord (uint32_t Address,
uint16_t Data 
)
+
+ +

Programs a half word (16-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.1V to 3.6V.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
+
+ +

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+ +
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+ + + + + + + + + + + + + + + + + + +
FLASH_Status FLASH_ProgramWord (uint32_t Address,
uint32_t Data 
)
+
+ +

Programs a word (32-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.7V to 3.6V.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
+
+ +

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void FLASH_SetLatency (uint32_t FLASH_Latency)
+
+ +

Sets the code latency value.

+
Parameters
+ + +
FLASH_Latencyspecifies the FLASH Latency value. This parameter can be one of the following values:
    +
  • FLASH_Latency_0: FLASH Zero Latency cycle
    • +
  • FLASH_Latency_1: FLASH One Latency cycle
    • +
  • FLASH_Latency_2: FLASH Two Latency cycles
    • +
  • FLASH_Latency_3: FLASH Three Latency cycles
    • +
  • FLASH_Latency_4: FLASH Four Latency cycles
    • +
  • FLASH_Latency_5: FLASH Five Latency cycles
    • +
  • FLASH_Latency_6: FLASH Six Latency cycles
    • +
  • FLASH_Latency_7: FLASH Seven Latency cycles
    • +
  • FLASH_Latency_8: FLASH Eight Latency cycles
    • +
  • FLASH_Latency_9: FLASH Nine Latency cycles
    • +
  • FLASH_Latency_10: FLASH Teen Latency cycles
    • +
  • FLASH_Latency_11: FLASH Eleven Latency cycles
    • +
  • FLASH_Latency_12: FLASH Twelve Latency cycles
    • +
  • FLASH_Latency_13: FLASH Thirteen Latency cycles
    • +
  • FLASH_Latency_14: FLASH Fourteen Latency cycles
    • +
  • FLASH_Latency_15: FLASH Fifteen Latency cycles
    • +
+
+
+
+
Note
For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
+
+For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_15.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_Unlock (void )
+
+ +

Unlocks the FLASH control register access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FLASH_Status FLASH_WaitForLastOperation (void )
+
+ +

Waits for a FLASH operation to complete.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
+
+ +

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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h.map b/group___f_l_a_s_h.map new file mode 100644 index 0000000..3723503 --- /dev/null +++ b/group___f_l_a_s_h.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___f_l_a_s_h.md5 b/group___f_l_a_s_h.md5 new file mode 100644 index 0000000..70af85e --- /dev/null +++ b/group___f_l_a_s_h.md5 @@ -0,0 +1 @@ +485454ac6f62db2c83a175feffaadc33 \ No newline at end of file diff --git a/group___f_l_a_s_h.png b/group___f_l_a_s_h.png new file mode 100644 index 0000000..570930d Binary files /dev/null and b/group___f_l_a_s_h.png differ diff --git a/group___f_l_a_s_h___b_o_r___reset___level.html b/group___f_l_a_s_h___b_o_r___reset___level.html new file mode 100644 index 0000000..19887ae --- /dev/null +++ b/group___f_l_a_s_h___b_o_r___reset___level.html @@ -0,0 +1,191 @@ + + + + + + +discoverpixy: FLASH_BOR_Reset_Level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_BOR_Reset_Level
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_BOR_Reset_Level:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define OB_BOR_LEVEL3   ((uint8_t)0x00)
 
#define OB_BOR_LEVEL2   ((uint8_t)0x04)
 
#define OB_BOR_LEVEL1   ((uint8_t)0x08)
 
#define OB_BOR_OFF   ((uint8_t)0x0C)
 
#define IS_OB_BOR(LEVEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_OB_BOR( LEVEL)
+
+Value:
(((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
OB_BOR_LEVEL1
#define OB_BOR_LEVEL1
Definition: stm32f4xx_flash.h:321
+
OB_BOR_LEVEL2
#define OB_BOR_LEVEL2
Definition: stm32f4xx_flash.h:320
+
OB_BOR_OFF
#define OB_BOR_OFF
Definition: stm32f4xx_flash.h:322
+
OB_BOR_LEVEL3
#define OB_BOR_LEVEL3
Definition: stm32f4xx_flash.h:319
+
+
+
+ +
+
+ + + + +
#define OB_BOR_LEVEL1   ((uint8_t)0x08)
+
+

Supply voltage ranges from 2.10 to 2.40 V

+ +
+
+ +
+
+ + + + +
#define OB_BOR_LEVEL2   ((uint8_t)0x04)
+
+

Supply voltage ranges from 2.40 to 2.70 V

+ +
+
+ +
+
+ + + + +
#define OB_BOR_LEVEL3   ((uint8_t)0x00)
+
+

Supply voltage ranges from 2.70 to 3.60 V

+ +
+
+ +
+
+ + + + +
#define OB_BOR_OFF   ((uint8_t)0x0C)
+
+

Supply voltage ranges from 1.62 to 2.10 V

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___b_o_r___reset___level.map b/group___f_l_a_s_h___b_o_r___reset___level.map new file mode 100644 index 0000000..616b3da --- /dev/null +++ b/group___f_l_a_s_h___b_o_r___reset___level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___b_o_r___reset___level.md5 b/group___f_l_a_s_h___b_o_r___reset___level.md5 new file mode 100644 index 0000000..56af590 --- /dev/null +++ b/group___f_l_a_s_h___b_o_r___reset___level.md5 @@ -0,0 +1 @@ +d69ba99bde0924dfc8e3fb5f41b7f95a \ No newline at end of file diff --git a/group___f_l_a_s_h___b_o_r___reset___level.png b/group___f_l_a_s_h___b_o_r___reset___level.png new file mode 100644 index 0000000..53670e6 Binary files /dev/null and b/group___f_l_a_s_h___b_o_r___reset___level.png differ diff --git a/group___f_l_a_s_h___dual___boot.html b/group___f_l_a_s_h___dual___boot.html new file mode 100644 index 0000000..12f419a --- /dev/null +++ b/group___f_l_a_s_h___dual___boot.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: FLASH_Dual_Boot + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Dual_Boot
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Dual_Boot:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define OB_Dual_BootEnabled   ((uint8_t)0x10)
 
#define OB_Dual_BootDisabled   ((uint8_t)0x00)
 
+#define IS_OB_BOOT(BOOT)   (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_Dual_BootDisabled   ((uint8_t)0x00)
+
+

Dual Bank Boot Disable, always boot on User Flash

+ +
+
+ +
+
+ + + + +
#define OB_Dual_BootEnabled   ((uint8_t)0x10)
+
+

Dual Bank Boot Enable

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___dual___boot.map b/group___f_l_a_s_h___dual___boot.map new file mode 100644 index 0000000..1589bae --- /dev/null +++ b/group___f_l_a_s_h___dual___boot.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___dual___boot.md5 b/group___f_l_a_s_h___dual___boot.md5 new file mode 100644 index 0000000..aeea468 --- /dev/null +++ b/group___f_l_a_s_h___dual___boot.md5 @@ -0,0 +1 @@ +c9be71aa07e28e9016940bcd65f7a585 \ No newline at end of file diff --git a/group___f_l_a_s_h___dual___boot.png b/group___f_l_a_s_h___dual___boot.png new file mode 100644 index 0000000..14c65d1 Binary files /dev/null and b/group___f_l_a_s_h___dual___boot.png differ diff --git a/group___f_l_a_s_h___exported___constants.html b/group___f_l_a_s_h___exported___constants.html new file mode 100644 index 0000000..0b36b64 --- /dev/null +++ b/group___f_l_a_s_h___exported___constants.html @@ -0,0 +1,166 @@ + + + + + + +discoverpixy: FLASH_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
FLASH_Exported_Constants
STM32F4xx_StdPeriph_Driver » RAMFUNC
+
+
+
+Collaboration diagram for FLASH_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Flash_Latency
 
 FLASH_Voltage_Range
 
 FLASH_Sectors
 
 Option_Bytes_Write_Protection
 
 Selection_Protection_Mode
 
 Option_Bytes_PC_ReadWrite_Protection
 
 FLASH_Option_Bytes_Read_Protection
 
 FLASH_Option_Bytes_IWatchdog
 
 FLASH_Option_Bytes_nRST_STOP
 
 FLASH_Option_Bytes_nRST_STDBY
 
 FLASH_BOR_Reset_Level
 
 FLASH_Dual_Boot
 
 FLASH_Interrupts
 
 FLASH_Flags
 
 FLASH_Program_Parallelism
 
 FLASH_Keys
 
+ + + + + + + + + + + + + + + + + + + +

+Macros

+#define ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
 ACR register byte 0 (Bits[7:0]) base address.
 
+#define OPTCR_BYTE0_ADDRESS   ((uint32_t)0x40023C14)
 OPTCR register byte 0 (Bits[7:0]) base address.
 
+#define OPTCR_BYTE1_ADDRESS   ((uint32_t)0x40023C15)
 OPTCR register byte 1 (Bits[15:8]) base address.
 
+#define OPTCR_BYTE2_ADDRESS   ((uint32_t)0x40023C16)
 OPTCR register byte 2 (Bits[23:16]) base address.
 
+#define OPTCR_BYTE3_ADDRESS   ((uint32_t)0x40023C17)
 OPTCR register byte 3 (Bits[31:24]) base address.
 
+#define OPTCR1_BYTE2_ADDRESS   ((uint32_t)0x40023C1A)
 OPTCR1 register byte 0 (Bits[7:0]) base address.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___exported___constants.map b/group___f_l_a_s_h___exported___constants.map new file mode 100644 index 0000000..2219b08 --- /dev/null +++ b/group___f_l_a_s_h___exported___constants.map @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/group___f_l_a_s_h___exported___constants.md5 b/group___f_l_a_s_h___exported___constants.md5 new file mode 100644 index 0000000..59f3029 --- /dev/null +++ b/group___f_l_a_s_h___exported___constants.md5 @@ -0,0 +1 @@ +4d2b30be1810f7e5038b459a9ec45cd1 \ No newline at end of file diff --git a/group___f_l_a_s_h___exported___constants.png b/group___f_l_a_s_h___exported___constants.png new file mode 100644 index 0000000..415cb5d Binary files /dev/null and b/group___f_l_a_s_h___exported___constants.png differ diff --git a/group___f_l_a_s_h___flags.html b/group___f_l_a_s_h___flags.html new file mode 100644 index 0000000..5ed7a8f --- /dev/null +++ b/group___f_l_a_s_h___flags.html @@ -0,0 +1,260 @@ + + + + + + +discoverpixy: FLASH_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Flags
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define FLASH_FLAG_EOP   ((uint32_t)0x00000001)
 
#define FLASH_FLAG_OPERR   ((uint32_t)0x00000002)
 
#define FLASH_FLAG_WRPERR   ((uint32_t)0x00000010)
 
#define FLASH_FLAG_PGAERR   ((uint32_t)0x00000020)
 
#define FLASH_FLAG_PGPERR   ((uint32_t)0x00000040)
 
#define FLASH_FLAG_PGSERR   ((uint32_t)0x00000080)
 
#define FLASH_FLAG_RDERR   ((uint32_t)0x00000100)
 
#define FLASH_FLAG_BSY   ((uint32_t)0x00010000)
 
+#define IS_FLASH_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
 
#define IS_FLASH_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define FLASH_FLAG_BSY   ((uint32_t)0x00010000)
+
+

FLASH Busy flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_EOP   ((uint32_t)0x00000001)
+
+

FLASH End of Operation flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_OPERR   ((uint32_t)0x00000002)
+
+

FLASH operation Error flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_PGAERR   ((uint32_t)0x00000020)
+
+

FLASH Programming Alignment error flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_PGPERR   ((uint32_t)0x00000040)
+
+

FLASH Programming Parallelism error flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_PGSERR   ((uint32_t)0x00000080)
+
+

FLASH Programming Sequence error flag

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_RDERR   ((uint32_t)0x00000100)
+
+

Read Protection error flag (PCROP)

+ +
+
+ +
+
+ + + + +
#define FLASH_FLAG_WRPERR   ((uint32_t)0x00000010)
+
+

FLASH Write protected error flag

+ +
+
+ +
+
+ + + + + + + + +
#define IS_FLASH_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
+
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
+
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
+
((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
+
FLASH_FLAG_PGAERR
#define FLASH_FLAG_PGAERR
Definition: stm32f4xx_flash.h:355
+
FLASH_FLAG_RDERR
#define FLASH_FLAG_RDERR
Definition: stm32f4xx_flash.h:358
+
FLASH_FLAG_PGSERR
#define FLASH_FLAG_PGSERR
Definition: stm32f4xx_flash.h:357
+
FLASH_FLAG_EOP
#define FLASH_FLAG_EOP
Definition: stm32f4xx_flash.h:352
+
FLASH_FLAG_BSY
#define FLASH_FLAG_BSY
Definition: stm32f4xx_flash.h:359
+
FLASH_FLAG_PGPERR
#define FLASH_FLAG_PGPERR
Definition: stm32f4xx_flash.h:356
+
FLASH_FLAG_WRPERR
#define FLASH_FLAG_WRPERR
Definition: stm32f4xx_flash.h:354
+
FLASH_FLAG_OPERR
#define FLASH_FLAG_OPERR
Definition: stm32f4xx_flash.h:353
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___flags.map b/group___f_l_a_s_h___flags.map new file mode 100644 index 0000000..47ee761 --- /dev/null +++ b/group___f_l_a_s_h___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___flags.md5 b/group___f_l_a_s_h___flags.md5 new file mode 100644 index 0000000..1331582 --- /dev/null +++ b/group___f_l_a_s_h___flags.md5 @@ -0,0 +1 @@ +c20f4d816809d1d635b3f54042bd064d \ No newline at end of file diff --git a/group___f_l_a_s_h___flags.png b/group___f_l_a_s_h___flags.png new file mode 100644 index 0000000..5729bb5 Binary files /dev/null and b/group___f_l_a_s_h___flags.png differ diff --git a/group___f_l_a_s_h___group1.html b/group___f_l_a_s_h___group1.html new file mode 100644 index 0000000..98d6884 --- /dev/null +++ b/group___f_l_a_s_h___group1.html @@ -0,0 +1,473 @@ + + + + + + +discoverpixy: FLASH Interface configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
FLASH Interface configuration functions
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Private_Functions
+
+
+ +

FLASH Interface configuration functions. +More...

+
+Collaboration diagram for FLASH Interface configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void FLASH_SetLatency (uint32_t FLASH_Latency)
 Sets the code latency value. More...
 
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
 Enables or disables the Prefetch Buffer. More...
 
void FLASH_InstructionCacheCmd (FunctionalState NewState)
 Enables or disables the Instruction Cache feature. More...
 
void FLASH_DataCacheCmd (FunctionalState NewState)
 Enables or disables the Data Cache feature. More...
 
void FLASH_InstructionCacheReset (void)
 Resets the Instruction Cache. More...
 
void FLASH_DataCacheReset (void)
 Resets the Data Cache. More...
 
+

Detailed Description

+

FLASH Interface configuration functions.

+
 ===============================================================================
+              ##### FLASH Interface configuration functions #####
+ ===============================================================================
+    [..]
+      This group includes the following functions:
+      (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
+          To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+          must be correctly programmed according to the frequency of the CPU clock 
+          (HCLK) and the supply voltage of the device.
+    [..]      
+      For STM32F405xx/07xx and STM32F415xx/17xx devices
+ +-------------------------------------------------------------------------------------+
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)|      NA        |      NA        |154 < HCLK <= 168|140 < HCLK <= 160|
+ +---------------|----------------|----------------|-----------------|-----------------+
+
+    [..]      
+      For STM32F42xxx/43xxx devices
+ +-------------------------------------------------------------------------------------+
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)|      NA        |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |8WS(9CPU cycle)|      NA        |      NA        |176 < HCLK <= 180|160 < HCLK <= 168|
+ +-------------------------------------------------------------------------------------+
+   
+    [..]
+    For STM32F401x devices
+ +-------------------------------------------------------------------------------------+
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|      NA        |72 < HCLK <= 84 |66 < HCLK <= 84  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|      NA        |      NA        |      NA         |80 < HCLK <= 84  |
+ +-------------------------------------------------------------------------------------+
+
+    [..]
+    For STM32F411xE devices
+ +-------------------------------------------------------------------------------------+
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|      NA        |96 < HCLK <= 100|72 < HCLK <= 90  |64 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|      NA        |       NA       |90 < HCLK <= 100 |80 < HCLK <= 96  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)|      NA        |       NA       |        NA       |96 < HCLK <= 100 |
+ +-------------------------------------------------------------------------------------+
+ 
+ [..]
+ +-------------------------------------------------------------------------------------------------------------------+
+ |               | voltage range  | voltage range  | voltage range   | voltage range   | voltage range 2.7 V - 3.6 V |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   | with External Vpp = 9V      |
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
+ |Max Parallelism|      x32       |               x16                |       x8        |          x64                |
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
+ |PSIZE[1:0]     |      10        |               01                 |       00        |           11                |
+ +-------------------------------------------------------------------------------------------------------------------+
+
+      -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: 
+           (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. 
+           (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. 
+          [..] 
+          On STM32F42xxx/43xxx devices:
+           (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
+           (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
+           (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. 
+          [..]
+          On STM32F401x devices:
+           (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
+           (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
+          [..]  
+          On STM32F411xE devices:
+           (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
+           (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
+           (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
+
+        For more details please refer product DataSheet 
+           You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
+
+      (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+      (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
+      (+) void FLASH_DataCacheCmd(FunctionalState NewState)
+      (+) void FLASH_InstructionCacheReset(void)
+      (+) void FLASH_DataCacheReset(void)
+      
+    [..]   
+      The unlock sequence is not needed for these functions.

Function Documentation

+ +
+
+ + + + + + + + +
void FLASH_DataCacheCmd (FunctionalState NewState)
+
+ +

Enables or disables the Data Cache feature.

+
Parameters
+ + +
NewStatenew state of the Data Cache. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_DataCacheReset (void )
+
+ +

Resets the Data Cache.

+
Note
This function must be used only when the Data Cache is disabled.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_InstructionCacheCmd (FunctionalState NewState)
+
+ +

Enables or disables the Instruction Cache feature.

+
Parameters
+ + +
NewStatenew state of the Instruction Cache. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_InstructionCacheReset (void )
+
+ +

Resets the Instruction Cache.

+
Note
This function must be used only when the Instruction Cache is disabled.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
+
+ +

Enables or disables the Prefetch Buffer.

+
Parameters
+ + +
NewStatenew state of the Prefetch Buffer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_SetLatency (uint32_t FLASH_Latency)
+
+ +

Sets the code latency value.

+
Parameters
+ + +
FLASH_Latencyspecifies the FLASH Latency value. This parameter can be one of the following values:
    +
  • FLASH_Latency_0: FLASH Zero Latency cycle
    • +
  • FLASH_Latency_1: FLASH One Latency cycle
    • +
  • FLASH_Latency_2: FLASH Two Latency cycles
    • +
  • FLASH_Latency_3: FLASH Three Latency cycles
    • +
  • FLASH_Latency_4: FLASH Four Latency cycles
    • +
  • FLASH_Latency_5: FLASH Five Latency cycles
    • +
  • FLASH_Latency_6: FLASH Six Latency cycles
    • +
  • FLASH_Latency_7: FLASH Seven Latency cycles
    • +
  • FLASH_Latency_8: FLASH Eight Latency cycles
    • +
  • FLASH_Latency_9: FLASH Nine Latency cycles
    • +
  • FLASH_Latency_10: FLASH Teen Latency cycles
    • +
  • FLASH_Latency_11: FLASH Eleven Latency cycles
    • +
  • FLASH_Latency_12: FLASH Twelve Latency cycles
    • +
  • FLASH_Latency_13: FLASH Thirteen Latency cycles
    • +
  • FLASH_Latency_14: FLASH Fourteen Latency cycles
    • +
  • FLASH_Latency_15: FLASH Fifteen Latency cycles
    • +
+
+
+
+
Note
For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
+
+For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_15.
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___group1.map b/group___f_l_a_s_h___group1.map new file mode 100644 index 0000000..8681de2 --- /dev/null +++ b/group___f_l_a_s_h___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___group1.md5 b/group___f_l_a_s_h___group1.md5 new file mode 100644 index 0000000..27ae814 --- /dev/null +++ b/group___f_l_a_s_h___group1.md5 @@ -0,0 +1 @@ +dc0a4d2953d58dede1b570482b7d00d0 \ No newline at end of file diff --git a/group___f_l_a_s_h___group1.png b/group___f_l_a_s_h___group1.png new file mode 100644 index 0000000..cc7f07d Binary files /dev/null and b/group___f_l_a_s_h___group1.png differ diff --git a/group___f_l_a_s_h___group2.html b/group___f_l_a_s_h___group2.html new file mode 100644 index 0000000..7a97567 --- /dev/null +++ b/group___f_l_a_s_h___group2.html @@ -0,0 +1,644 @@ + + + + + + +discoverpixy: FLASH Memory Programming functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
FLASH Memory Programming functions
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Private_Functions
+
+
+ +

FLASH Memory Programming functions. +More...

+
+Collaboration diagram for FLASH Memory Programming functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FLASH_Unlock (void)
 Unlocks the FLASH control register access. More...
 
void FLASH_Lock (void)
 Locks the FLASH control register access. More...
 
FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector, uint8_t VoltageRange)
 Erases a specified FLASH Sector. More...
 
FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
 Erases all FLASH Sectors. More...
 
FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 1. More...
 
FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 2. More...
 
FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address, uint64_t Data)
 Programs a double word (64-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramWord (uint32_t Address, uint32_t Data)
 Programs a word (32-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
 Programs a half word (16-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramByte (uint32_t Address, uint8_t Data)
 Programs a byte (8-bit) at a specified address. More...
 
+

Detailed Description

+

FLASH Memory Programming functions.

+
 ===============================================================================
+                ##### FLASH Memory Programming functions #####
+ ===============================================================================   
+    [..]
+      This group includes the following functions:
+      (+) void FLASH_Unlock(void)
+      (+) void FLASH_Lock(void)
+      (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
+      (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)       
+      (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
+      (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+      (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+      (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+          The following functions can be used only for STM32F42xxx/43xxx devices. 
+      (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
+      (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)    
+    [..]   
+      Any operation of erase or program should follow these steps:
+      (#) Call the FLASH_Unlock() function to enable the FLASH control register access
+
+      (#) Call the desired function to erase sector(s) or program data
+
+      (#) Call the FLASH_Lock() function to disable the FLASH control register access
+          (recommended to protect the FLASH memory against possible unwanted operation)

Function Documentation

+ +
+
+ + + + + + + + +
FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors in Bank 1.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors in Bank 2.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
+
+ +

Erases all FLASH Sectors.

+
Note
If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector,
uint8_t VoltageRange 
)
+
+ +

Erases a specified FLASH Sector.

+
Note
If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + +
FLASH_SectorThe Sector number to be erased.
+
+
+
Note
For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11.
+

For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_23.

+

For STM32F401xx devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_5.

+

For STM32F411xE devices this parameter can be a value between FLASH_Sector_0 and FLASH_Sector_7.

+
Parameters
+ + +
VoltageRangeThe device voltage range which defines the erase parallelism. This parameter can be one of the following values:
    +
  • VoltageRange_1: when the device voltage range is 1.8V to 2.1V, the operation will be done by byte (8-bit)
    • +
  • VoltageRange_2: when the device voltage range is 2.1V to 2.7V, the operation will be done by half word (16-bit)
    • +
  • VoltageRange_3: when the device voltage range is 2.7V to 3.6V, the operation will be done by word (32-bit)
    • +
  • VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, the operation will be done by double word (64-bit)
    • +
+
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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void FLASH_Lock (void )
+
+ +

Locks the FLASH control register access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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FLASH_Status FLASH_ProgramByte (uint32_t Address,
uint8_t Data 
)
+
+ +

Programs a byte (8-bit) at a specified address.

+
Note
This function can be used within all the device supply voltage ranges.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address,
uint64_t Data 
)
+
+ +

Programs a double word (64-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.7V to 3.6V and an External Vpp is present.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_ProgramHalfWord (uint32_t Address,
uint16_t Data 
)
+
+ +

Programs a half word (16-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.1V to 3.6V.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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FLASH_Status FLASH_ProgramWord (uint32_t Address,
uint32_t Data 
)
+
+ +

Programs a word (32-bit) at a specified address.

+
Note
This function must be used when the device voltage range is from 2.7V to 3.6V.
+
+If an erase and a program operations are requested simustaneously, the erase operation is performed before the program one.
+
Parameters
+ + + +
Addressspecifies the address to be programmed. This parameter can be any address in Program memory zone or in OTP zone.
Dataspecifies the data to be programmed.
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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void FLASH_Unlock (void )
+
+ +

Unlocks the FLASH control register access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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b/group___f_l_a_s_h___group3.html @@ -0,0 +1,998 @@ + + + + + + +discoverpixy: Option Bytes Programming functions + + + + + + + + + + +
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+Functions
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+
Option Bytes Programming functions
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Private_Functions
+
+
+ +

Option Bytes Programming functions. +More...

+
+Collaboration diagram for Option Bytes Programming functions:
+
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+Functions

void FLASH_OB_Unlock (void)
 Unlocks the FLASH Option Control Registers access. More...
 
void FLASH_OB_Lock (void)
 Locks the FLASH Option Control Registers access. More...
 
void FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash. More...
 
void FLASH_OB_WRP1Config (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash. More...
 
void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
 Select the Protection Mode (SPRMOD). More...
 
void FLASH_OB_PCROPConfig (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash. More...
 
void FLASH_OB_PCROP1Config (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors. More...
 
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
 Sets the read protection level. More...
 
void FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. More...
 
void FLASH_OB_BootConfig (uint8_t OB_BOOT)
 Configure the Dual Bank Boot. More...
 
void FLASH_OB_BORConfig (uint8_t OB_BOR)
 Sets the BOR Level. More...
 
FLASH_Status FLASH_OB_Launch (void)
 Launch the option byte loading. More...
 
uint8_t FLASH_OB_GetUser (void)
 Returns the FLASH User Option Bytes values. More...
 
uint16_t FLASH_OB_GetWRP (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetWRP1 (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP1 (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
FlagStatus FLASH_OB_GetRDP (void)
 Returns the FLASH Read Protection level. More...
 
uint8_t FLASH_OB_GetBOR (void)
 Returns the FLASH BOR level. More...
 
+

Detailed Description

+

Option Bytes Programming functions.

+
 ===============================================================================
+                ##### Option Bytes Programming functions #####
+ ===============================================================================  
+    [..]
+      This group includes the following functions:
+      (+) void FLASH_OB_Unlock(void)
+      (+) void FLASH_OB_Lock(void)
+      (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
+      (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)  
+      (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
+      (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
+      (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) 
+      (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
+      (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+      (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
+      (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
+      (+) FLASH_Status FLASH_OB_Launch(void)
+      (+) uint32_t FLASH_OB_GetUser(void)
+      (+) uint8_t FLASH_OB_GetWRP(void)
+      (+) uint8_t FLASH_OB_GetWRP1(void)
+      (+) uint8_t FLASH_OB_GetPCROP(void)
+      (+) uint8_t FLASH_OB_GetPCROP1(void)
+      (+) uint8_t FLASH_OB_GetRDP(void)
+      (+) uint8_t FLASH_OB_GetBOR(void)
+    [..]  
+      The following function can be used only for STM32F42xxx/43xxx devices. 
+      (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
+    [..]   
+     Any operation of erase or program should follow these steps:
+      (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control 
+          register access
+
+      (#) Call one or several functions to program the desired Option Bytes:
+        (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) 
+             => to Enable/Disable the desired sector write protection
+        (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read 
+             Protection Level
+        (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) 
+             => to configure the user Option Bytes.
+        (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level             
+
+      (#) Once all needed Option Bytes to be programmed are correctly written, 
+          call the FLASH_OB_Launch() function to launch the Option Bytes 
+          programming process.
+     
+      -@- When changing the IWDG mode from HW to SW or from SW to HW, a system 
+          reset is needed to make the change effective.  
+
+      (#) Call the FLASH_OB_Lock() function to disable the FLASH option control 
+          register access (recommended to protect the Option Bytes against 
+          possible unwanted operations)

Function Documentation

+ +
+
+ + + + + + + + +
void FLASH_OB_BootConfig (uint8_t OB_BOOT)
+
+ +

Configure the Dual Bank Boot.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
OB_BOOTspecifies the Dual Bank Boot Option byte. This parameter can be one of the following values:
    +
  • OB_Dual_BootEnabled: Dual Bank Boot Enable
    • +
  • OB_Dual_BootDisabled: Dual Bank Boot Disabled
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FLASH_OB_BORConfig (uint8_t OB_BOR)
+
+ +

Sets the BOR Level.

+
Parameters
+ + +
OB_BORspecifies the Option Bytes BOR Reset Level. This parameter can be one of the following values:
    +
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
    • +
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
    • +
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
    • +
  • OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t FLASH_OB_GetBOR (void )
+
+ +

Returns the FLASH BOR level.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH BOR level:
    +
  • OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
    • +
  • OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
    • +
  • OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
    • +
  • OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
    • +
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uint16_t FLASH_OB_GetPCROP (void )
+
+ +

Returns the FLASH PC Read/Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH PC Read/Write Protection Option Bytes value
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t FLASH_OB_GetPCROP1 (void )
+
+ +

Returns the FLASH PC Read/Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH PC Read/Write Protection Option Bytes value
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus FLASH_OB_GetRDP (void )
+
+ +

Returns the FLASH Read Protection level.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHReadOut Protection Status:
    +
  • SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
    • +
  • RESET, when OB_RDP_Level_0 is set
    • +
+
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+ +
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uint8_t FLASH_OB_GetUser (void )
+
+ +

Returns the FLASH User Option Bytes values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) and RST_STDBY(Bit2).
+
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+ +
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+ +
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+ + + + + + + + +
uint16_t FLASH_OB_GetWRP (void )
+
+ +

Returns the FLASH Write Protection Option Bytes value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH Write Protection Option Bytes value
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t FLASH_OB_GetWRP1 (void )
+
+ +

Returns the FLASH Write Protection Option Bytes value.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheFLASH Write Protection Option Bytes value
+
+
+ +
+
+ +
+
+ + + + + + + + +
FLASH_Status FLASH_OB_Launch (void )
+
+ +

Launch the option byte loading.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+
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void FLASH_OB_Lock (void )
+
+ +

Locks the FLASH Option Control Registers access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
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void FLASH_OB_PCROP1Config (uint32_t OB_PCROP,
FunctionalState NewState 
)
+
+ +

Enables or disables the read/write protection (PCROP) of the desired sectors.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + + +
OB_PCROPspecifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
    • +
  • OB_PCROP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
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void FLASH_OB_PCROPConfig (uint32_t OB_PCROP,
FunctionalState NewState 
)
+
+ +

Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash.

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
Parameters
+ + + +
OB_PCROPspecifies the sector(s) to be read/write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and OB_PCROP_Sector5 for STM32F401xx/411xE devices.
    • +
  • OB_PCROP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
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void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
+
+ +

Select the Protection Mode (SPRMOD).

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
+After PCROP activation, Option Byte modification is not possible. Exception made for the global Read Out Protection modification level (level1 to level0)
+
+Once SPRMOD bit is active unprotection of a protected sector is not possible
+
+Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+
+Some Precautions should be taken when activating the PCROP feature : The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 and WRPi = 1 (default value), then the user sector i is read/write protected. In order to avoid activation of PCROP Mode for undesired sectors, please follow the below safety sequence :
    +
  • Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
    • +
  • Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
    • +
  • Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
    • +
+
+
Parameters
+ + +
OB_PCROPSelect the Protection Mode of nWPRi bits This parameter can be one of the following values:
    +
  • OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
    • +
  • OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
+
+ +

Sets the read protection level.

+
Parameters
+ + +
OB_RDPspecifies the read protection level. This parameter can be one of the following values:
    +
  • OB_RDP_Level_0: No protection
    • +
  • OB_RDP_Level_1: Read protection of the memory
    • +
  • OB_RDP_Level_2: Full chip protection
    • +
+/!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+
+
+
Return values
+ + +
None
+
+
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void FLASH_OB_Unlock (void )
+
+ +

Unlocks the FLASH Option Control Registers access.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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void FLASH_OB_UserConfig (uint8_t OB_IWDG,
uint8_t OB_STOP,
uint8_t OB_STDBY 
)
+
+ +

Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.

+
Parameters
+ + + + +
OB_IWDGSelects the IWDG mode This parameter can be one of the following values:
    +
  • OB_IWDG_SW: Software IWDG selected
    • +
  • OB_IWDG_HW: Hardware IWDG selected
    • +
+
OB_STOPReset event when entering STOP mode. This parameter can be one of the following values:
    +
  • OB_STOP_NoRST: No reset generated when entering in STOP
    • +
  • OB_STOP_RST: Reset generated when entering in STOP
    • +
+
OB_STDBYReset event when entering Standby mode. This parameter can be one of the following values:
    +
  • OB_STDBY_NoRST: No reset generated when entering in STANDBY
    • +
  • OB_STDBY_RST: Reset generated when entering in STANDBY
    • +
+
+
+
+
Return values
+ + +
None
+
+
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void FLASH_OB_WRP1Config (uint32_t OB_WRP,
FunctionalState NewState 
)
+
+ +

Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+When the memory read out protection is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+
+Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+
Parameters
+ + + +
OB_WRPspecifies the sector(s) to be write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
    • +
  • OB_WRP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
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void FLASH_OB_WRPConfig (uint32_t OB_WRP,
FunctionalState NewState 
)
+
+ +

Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash.

+
Note
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash sector i if CortexM4 debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+
+Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+
Parameters
+ + + +
OB_WRPspecifies the sector(s) to be write protected or unprotected. This parameter can be one of the following values:
    +
  • OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
    • +
  • OB_WRP_Sector_All
    • +
+
Newstatenew state of the Write Protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Functions
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Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Private_Functions
+
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+ +

Interrupts and flags management functions. +More...

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+Collaboration diagram for Interrupts and flags management functions:
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+Functions

void FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
 Enables or disables the specified FLASH interrupts. More...
 
FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
 Checks whether the specified FLASH flag is set or not. More...
 
void FLASH_ClearFlag (uint32_t FLASH_FLAG)
 Clears the FLASH's pending flags. More...
 
FLASH_Status FLASH_GetStatus (void)
 Returns the FLASH Status. More...
 
FLASH_Status FLASH_WaitForLastOperation (void)
 Waits for a FLASH operation to complete. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+

Function Documentation

+ +
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+ + + + + + + + +
void FLASH_ClearFlag (uint32_t FLASH_FLAG)
+
+ +

Clears the FLASH's pending flags.

+
Parameters
+ + +
FLASH_FLAGspecifies the FLASH flags to clear. This parameter can be any combination of the following values:
    +
  • FLASH_FLAG_EOP: FLASH End of Operation flag
    • +
  • FLASH_FLAG_OPERR: FLASH operation Error flag
    • +
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
    • +
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
    • +
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
    • +
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
    • +
  • FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
    • +
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Return values
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None
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FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
+
+ +

Checks whether the specified FLASH flag is set or not.

+
Parameters
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FLASH_FLAGspecifies the FLASH flag to check. This parameter can be one of the following values:
    +
  • FLASH_FLAG_EOP: FLASH End of Operation flag
    • +
  • FLASH_FLAG_OPERR: FLASH operation Error flag
    • +
  • FLASH_FLAG_WRPERR: FLASH Write protected error flag
    • +
  • FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
    • +
  • FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
    • +
  • FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
    • +
  • FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
    • +
  • FLASH_FLAG_BSY: FLASH Busy flag
    • +
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Return values
+ + +
Thenew state of FLASH_FLAG (SET or RESET).
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FLASH_Status FLASH_GetStatus (void )
+
+ +

Returns the FLASH Status.

+
Parameters
+ + +
None
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Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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void FLASH_ITConfig (uint32_t FLASH_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified FLASH interrupts.

+
Parameters
+ + +
FLASH_ITspecifies the FLASH interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • FLASH_IT_ERR: FLASH Error Interrupt
    • +
  • FLASH_IT_EOP: FLASH end of operation Interrupt
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Return values
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None
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FLASH_Status FLASH_WaitForLastOperation (void )
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Waits for a FLASH operation to complete.

+
Parameters
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None
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Return values
+ + +
FLASHStatus: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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FLASH_Interrupts
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
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+Macros

#define FLASH_IT_EOP   ((uint32_t)0x01000000)
 
#define FLASH_IT_ERR   ((uint32_t)0x02000000)
 
+#define IS_FLASH_IT(IT)   ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
 
+

Detailed Description

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Macro Definition Documentation

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#define FLASH_IT_EOP   ((uint32_t)0x01000000)
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+

End of FLASH Operation Interrupt source

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#define FLASH_IT_ERR   ((uint32_t)0x02000000)
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Error Interrupt source

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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___interrupts.map b/group___f_l_a_s_h___interrupts.map new file mode 100644 index 0000000..b368dc1 --- /dev/null +++ b/group___f_l_a_s_h___interrupts.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___interrupts.md5 b/group___f_l_a_s_h___interrupts.md5 new file mode 100644 index 0000000..e98a8c6 --- /dev/null +++ b/group___f_l_a_s_h___interrupts.md5 @@ -0,0 +1 @@ +88a78ab34314532cb71b563e034d8b40 \ No newline at end of file diff --git a/group___f_l_a_s_h___interrupts.png b/group___f_l_a_s_h___interrupts.png new file mode 100644 index 0000000..d80da11 Binary files /dev/null and b/group___f_l_a_s_h___interrupts.png differ diff --git a/group___f_l_a_s_h___keys.html b/group___f_l_a_s_h___keys.html new file mode 100644 index 0000000..981fc2a --- /dev/null +++ b/group___f_l_a_s_h___keys.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: FLASH_Keys + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Keys
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Keys:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define RDP_KEY   ((uint16_t)0x00A5)
 
+#define FLASH_KEY1   ((uint32_t)0x45670123)
 
+#define FLASH_KEY2   ((uint32_t)0xCDEF89AB)
 
+#define FLASH_OPT_KEY1   ((uint32_t)0x08192A3B)
 
+#define FLASH_OPT_KEY2   ((uint32_t)0x4C5D6E7F)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___keys.map b/group___f_l_a_s_h___keys.map new file mode 100644 index 0000000..6b81585 --- /dev/null +++ b/group___f_l_a_s_h___keys.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___keys.md5 b/group___f_l_a_s_h___keys.md5 new file mode 100644 index 0000000..a3bb89f --- /dev/null +++ b/group___f_l_a_s_h___keys.md5 @@ -0,0 +1 @@ +c7f57f3fd271574fb9d0631c29bc9612 \ No newline at end of file diff --git a/group___f_l_a_s_h___keys.png b/group___f_l_a_s_h___keys.png new file mode 100644 index 0000000..4424ff4 Binary files /dev/null and b/group___f_l_a_s_h___keys.png differ diff --git a/group___f_l_a_s_h___option___bytes___i_watchdog.html b/group___f_l_a_s_h___option___bytes___i_watchdog.html new file mode 100644 index 0000000..7906cd3 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___i_watchdog.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: FLASH_Option_Bytes_IWatchdog + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Option_Bytes_IWatchdog
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Option_Bytes_IWatchdog:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define OB_IWDG_SW   ((uint8_t)0x20)
 
#define OB_IWDG_HW   ((uint8_t)0x00)
 
+#define IS_OB_IWDG_SOURCE(SOURCE)   (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_IWDG_HW   ((uint8_t)0x00)
+
+

Hardware IWDG selected

+ +
+
+ +
+
+ + + + +
#define OB_IWDG_SW   ((uint8_t)0x20)
+
+

Software IWDG selected

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___option___bytes___i_watchdog.map b/group___f_l_a_s_h___option___bytes___i_watchdog.map new file mode 100644 index 0000000..5608755 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___i_watchdog.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___option___bytes___i_watchdog.md5 b/group___f_l_a_s_h___option___bytes___i_watchdog.md5 new file mode 100644 index 0000000..1668b4e --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___i_watchdog.md5 @@ -0,0 +1 @@ +6e1ad9dfbbca795fc1b28a51007ee5ee \ No newline at end of file diff --git a/group___f_l_a_s_h___option___bytes___i_watchdog.png b/group___f_l_a_s_h___option___bytes___i_watchdog.png new file mode 100644 index 0000000..5d58d0a Binary files /dev/null and b/group___f_l_a_s_h___option___bytes___i_watchdog.png differ diff --git a/group___f_l_a_s_h___option___bytes___read___protection.html b/group___f_l_a_s_h___option___bytes___read___protection.html new file mode 100644 index 0000000..0c42a52 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___read___protection.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: FLASH_Option_Bytes_Read_Protection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Option_Bytes_Read_Protection
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Option_Bytes_Read_Protection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define OB_RDP_Level_0   ((uint8_t)0xAA)
 
+#define OB_RDP_Level_1   ((uint8_t)0x55)
 
#define IS_OB_RDP(LEVEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_OB_RDP( LEVEL)
+
+Value:
(((LEVEL) == OB_RDP_Level_0)||\
+
((LEVEL) == OB_RDP_Level_1))/*||\
+
((LEVEL) == OB_RDP_Level_2))*/
+

< Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___option___bytes___read___protection.map b/group___f_l_a_s_h___option___bytes___read___protection.map new file mode 100644 index 0000000..57f6446 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___read___protection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___option___bytes___read___protection.md5 b/group___f_l_a_s_h___option___bytes___read___protection.md5 new file mode 100644 index 0000000..6beb3c5 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes___read___protection.md5 @@ -0,0 +1 @@ +7bcb751ec8a12f1f7f9a073bafea120d \ No newline at end of file diff --git a/group___f_l_a_s_h___option___bytes___read___protection.png b/group___f_l_a_s_h___option___bytes___read___protection.png new file mode 100644 index 0000000..1ed6d7c Binary files /dev/null and b/group___f_l_a_s_h___option___bytes___read___protection.png differ diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.html b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.html new file mode 100644 index 0000000..5e1caa2 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: FLASH_Option_Bytes_nRST_STDBY + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Option_Bytes_nRST_STDBY
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Option_Bytes_nRST_STDBY:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define OB_STDBY_NoRST   ((uint8_t)0x80)
 
#define OB_STDBY_RST   ((uint8_t)0x00)
 
+#define IS_OB_STDBY_SOURCE(SOURCE)   (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_STDBY_NoRST   ((uint8_t)0x80)
+
+

No reset generated when entering in STANDBY

+ +
+
+ +
+
+ + + + +
#define OB_STDBY_RST   ((uint8_t)0x00)
+
+

Reset generated when entering in STANDBY

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.map b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.map new file mode 100644 index 0000000..ae5e89c --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.md5 b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.md5 new file mode 100644 index 0000000..35d85fa --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.md5 @@ -0,0 +1 @@ +63f0a543e5cc90c6679deb66aaba3c10 \ No newline at end of file diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.png b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.png new file mode 100644 index 0000000..7ac738a Binary files /dev/null and b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_d_b_y.png differ diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.html b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.html new file mode 100644 index 0000000..a274df9 --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: FLASH_Option_Bytes_nRST_STOP + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Option_Bytes_nRST_STOP
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Option_Bytes_nRST_STOP:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define OB_STOP_NoRST   ((uint8_t)0x40)
 
#define OB_STOP_RST   ((uint8_t)0x00)
 
+#define IS_OB_STOP_SOURCE(SOURCE)   (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_STOP_NoRST   ((uint8_t)0x40)
+
+

No reset generated when entering in STOP

+ +
+
+ +
+
+ + + + +
#define OB_STOP_RST   ((uint8_t)0x00)
+
+

Reset generated when entering in STOP

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.map b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.map new file mode 100644 index 0000000..a4d2f0e --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.md5 b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.md5 new file mode 100644 index 0000000..14b950a --- /dev/null +++ b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.md5 @@ -0,0 +1 @@ +6433f8d3d9f342d4441e303c2de1e91d \ No newline at end of file diff --git a/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.png b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.png new file mode 100644 index 0000000..a0d4301 Binary files /dev/null and b/group___f_l_a_s_h___option___bytes__n_r_s_t___s_t_o_p.png differ diff --git a/group___f_l_a_s_h___private___functions.html b/group___f_l_a_s_h___private___functions.html new file mode 100644 index 0000000..83030a8 --- /dev/null +++ b/group___f_l_a_s_h___private___functions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: FLASH_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
FLASH_Private_Functions
STM32F4xx_StdPeriph_Driver » RAMFUNC
+
+
+
+Collaboration diagram for FLASH_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 FLASH Interface configuration functions
 FLASH Interface configuration functions.
 
 FLASH Memory Programming functions
 FLASH Memory Programming functions.
 
 Option Bytes Programming functions
 Option Bytes Programming functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___private___functions.map b/group___f_l_a_s_h___private___functions.map new file mode 100644 index 0000000..82fac9d --- /dev/null +++ b/group___f_l_a_s_h___private___functions.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___f_l_a_s_h___private___functions.md5 b/group___f_l_a_s_h___private___functions.md5 new file mode 100644 index 0000000..6bbeb63 --- /dev/null +++ b/group___f_l_a_s_h___private___functions.md5 @@ -0,0 +1 @@ +7f22aa4f628c9ef3d21a679ba298a492 \ No newline at end of file diff --git a/group___f_l_a_s_h___private___functions.png b/group___f_l_a_s_h___private___functions.png new file mode 100644 index 0000000..dfc00e0 Binary files /dev/null and b/group___f_l_a_s_h___private___functions.png differ diff --git a/group___f_l_a_s_h___program___parallelism.html b/group___f_l_a_s_h___program___parallelism.html new file mode 100644 index 0000000..1c4eaa1 --- /dev/null +++ b/group___f_l_a_s_h___program___parallelism.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: FLASH_Program_Parallelism + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FLASH_Program_Parallelism
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Program_Parallelism:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define FLASH_PSIZE_BYTE   ((uint32_t)0x00000000)
 
+#define FLASH_PSIZE_HALF_WORD   ((uint32_t)0x00000100)
 
+#define FLASH_PSIZE_WORD   ((uint32_t)0x00000200)
 
+#define FLASH_PSIZE_DOUBLE_WORD   ((uint32_t)0x00000300)
 
+#define CR_PSIZE_MASK   ((uint32_t)0xFFFFFCFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___program___parallelism.map b/group___f_l_a_s_h___program___parallelism.map new file mode 100644 index 0000000..efba01f --- /dev/null +++ b/group___f_l_a_s_h___program___parallelism.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___program___parallelism.md5 b/group___f_l_a_s_h___program___parallelism.md5 new file mode 100644 index 0000000..5f936b7 --- /dev/null +++ b/group___f_l_a_s_h___program___parallelism.md5 @@ -0,0 +1 @@ +20560cab48d20184cca8dd9f683da4fb \ No newline at end of file diff --git a/group___f_l_a_s_h___program___parallelism.png b/group___f_l_a_s_h___program___parallelism.png new file mode 100644 index 0000000..9f14e22 Binary files /dev/null and b/group___f_l_a_s_h___program___parallelism.png differ diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.html b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.html new file mode 100644 index 0000000..861ba18 --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: Peripheral features functions executed from internal RAM + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Peripheral features functions executed from internal RAM
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_RAMFUNC_Private_Functions
+
+
+ +

Peripheral Extended features functions. +More...

+
+Collaboration diagram for Peripheral features functions executed from internal RAM:
+
+
+ + +
+
+ + + + + + + + +

+Functions

__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
 Start/Stop the flash interface while System Run. More...
 
__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
 Enable/Disable the flash sleep while System Run. More...
 
+

Detailed Description

+

Peripheral Extended features functions.

+
 ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions that should be executed from RAM 
+    transfers.

Function Documentation

+ +
+
+ + + + + + + + +
__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
+
+ +

Start/Stop the flash interface while System Run.

+

__RAM_FUNC definition

+
Note
This mode is only available for STM32F411xx devices.
+
+This mode could n't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
+
Parameters
+ + +
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
+
+ +

Enable/Disable the flash sleep while System Run.

+
Note
This mode is only available for STM32F411xx devices.
+
+This mode could n't be set while executing with the flash itself. It should be done with specific routine executed from RAM.
+
Parameters
+ + +
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.map b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.map new file mode 100644 index 0000000..b5f34a8 --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.md5 b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.md5 new file mode 100644 index 0000000..c66a028 --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.md5 @@ -0,0 +1 @@ +599f8728d945e2ad2c9f14c92f4741c5 \ No newline at end of file diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.png b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.png new file mode 100644 index 0000000..044b733 Binary files /dev/null and b/group___f_l_a_s_h___r_a_m_f_u_n_c___group1.png differ diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.html b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.html new file mode 100644 index 0000000..edc4412 --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FLASH_RAMFUNC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
FLASH_RAMFUNC_Private_Functions
STM32F4xx_StdPeriph_Driver » RAMFUNC
+
+
+
+Collaboration diagram for FLASH_RAMFUNC_Private_Functions:
+
+
+ + +
+
+ + + + + +

+Modules

 Peripheral features functions executed from internal RAM
 Peripheral Extended features functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.map b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.map new file mode 100644 index 0000000..7e2c1ea --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.md5 b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.md5 new file mode 100644 index 0000000..8f0eddc --- /dev/null +++ b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.md5 @@ -0,0 +1 @@ +704281f1b1512f2c9d68baa33ec43ad6 \ No newline at end of file diff --git a/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.png b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.png new file mode 100644 index 0000000..43c50bc Binary files /dev/null and b/group___f_l_a_s_h___r_a_m_f_u_n_c___private___functions.png differ diff --git a/group___f_l_a_s_h___sectors.html b/group___f_l_a_s_h___sectors.html new file mode 100644 index 0000000..0ba4719 --- /dev/null +++ b/group___f_l_a_s_h___sectors.html @@ -0,0 +1,541 @@ + + + + + + +discoverpixy: FLASH_Sectors + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+ +
+ +
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+Macros
+
+
FLASH_Sectors
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Sectors:
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define FLASH_Sector_0   ((uint16_t)0x0000)
 
#define FLASH_Sector_1   ((uint16_t)0x0008)
 
#define FLASH_Sector_2   ((uint16_t)0x0010)
 
#define FLASH_Sector_3   ((uint16_t)0x0018)
 
#define FLASH_Sector_4   ((uint16_t)0x0020)
 
#define FLASH_Sector_5   ((uint16_t)0x0028)
 
#define FLASH_Sector_6   ((uint16_t)0x0030)
 
#define FLASH_Sector_7   ((uint16_t)0x0038)
 
#define FLASH_Sector_8   ((uint16_t)0x0040)
 
#define FLASH_Sector_9   ((uint16_t)0x0048)
 
#define FLASH_Sector_10   ((uint16_t)0x0050)
 
#define FLASH_Sector_11   ((uint16_t)0x0058)
 
#define FLASH_Sector_12   ((uint16_t)0x0080)
 
#define FLASH_Sector_13   ((uint16_t)0x0088)
 
#define FLASH_Sector_14   ((uint16_t)0x0090)
 
#define FLASH_Sector_15   ((uint16_t)0x0098)
 
#define FLASH_Sector_16   ((uint16_t)0x00A0)
 
#define FLASH_Sector_17   ((uint16_t)0x00A8)
 
#define FLASH_Sector_18   ((uint16_t)0x00B0)
 
#define FLASH_Sector_19   ((uint16_t)0x00B8)
 
#define FLASH_Sector_20   ((uint16_t)0x00C0)
 
#define FLASH_Sector_21   ((uint16_t)0x00C8)
 
#define FLASH_Sector_22   ((uint16_t)0x00D0)
 
#define FLASH_Sector_23   ((uint16_t)0x00D8)
 
#define IS_FLASH_SECTOR(SECTOR)
 
#define IS_FLASH_ADDRESS(ADDRESS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define FLASH_Sector_0   ((uint16_t)0x0000)
+
+

Sector Number 0

+ +
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+ +
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+ + + + +
#define FLASH_Sector_1   ((uint16_t)0x0008)
+
+

Sector Number 1

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+ +
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+ + + + +
#define FLASH_Sector_10   ((uint16_t)0x0050)
+
+

Sector Number 10

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#define FLASH_Sector_11   ((uint16_t)0x0058)
+
+

Sector Number 11

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+ + + + +
#define FLASH_Sector_12   ((uint16_t)0x0080)
+
+

Sector Number 12

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+ + + + +
#define FLASH_Sector_13   ((uint16_t)0x0088)
+
+

Sector Number 13

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+ +
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+ + + + +
#define FLASH_Sector_14   ((uint16_t)0x0090)
+
+

Sector Number 14

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+ +
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+ + + + +
#define FLASH_Sector_15   ((uint16_t)0x0098)
+
+

Sector Number 15

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+ +
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+ + + + +
#define FLASH_Sector_16   ((uint16_t)0x00A0)
+
+

Sector Number 16

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+ +
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+ + + + +
#define FLASH_Sector_17   ((uint16_t)0x00A8)
+
+

Sector Number 17

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+ +
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+ + + + +
#define FLASH_Sector_18   ((uint16_t)0x00B0)
+
+

Sector Number 18

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+ +
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+ + + + +
#define FLASH_Sector_19   ((uint16_t)0x00B8)
+
+

Sector Number 19

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#define FLASH_Sector_2   ((uint16_t)0x0010)
+
+

Sector Number 2

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+ + + + +
#define FLASH_Sector_20   ((uint16_t)0x00C0)
+
+

Sector Number 20

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+ +
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+ + + + +
#define FLASH_Sector_21   ((uint16_t)0x00C8)
+
+

Sector Number 21

+ +
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+ +
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+ + + + +
#define FLASH_Sector_22   ((uint16_t)0x00D0)
+
+

Sector Number 22

+ +
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+ +
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+ + + + +
#define FLASH_Sector_23   ((uint16_t)0x00D8)
+
+

Sector Number 23

+ +
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+ +
+
+ + + + +
#define FLASH_Sector_3   ((uint16_t)0x0018)
+
+

Sector Number 3

+ +
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+ +
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+ + + + +
#define FLASH_Sector_4   ((uint16_t)0x0020)
+
+

Sector Number 4

+ +
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+ +
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+ + + + +
#define FLASH_Sector_5   ((uint16_t)0x0028)
+
+

Sector Number 5

+ +
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+ +
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+ + + + +
#define FLASH_Sector_6   ((uint16_t)0x0030)
+
+

Sector Number 6

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+ +
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+ + + + +
#define FLASH_Sector_7   ((uint16_t)0x0038)
+
+

Sector Number 7

+ +
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+ +
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+ + + + +
#define FLASH_Sector_8   ((uint16_t)0x0040)
+
+

Sector Number 8

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+ +
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+ + + + +
#define FLASH_Sector_9   ((uint16_t)0x0048)
+
+

Sector Number 9

+ +
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+ +
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+ + + + + + + + +
#define IS_FLASH_ADDRESS( ADDRESS)
+
+Value:
((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
+
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_FLASH_SECTOR( SECTOR)
+
+Value:
(((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
+
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
+
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
+
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
+
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
+
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\
+
((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\
+
((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\
+
((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\
+
((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\
+
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
+
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
+
FLASH_Sector_2
#define FLASH_Sector_2
Definition: stm32f4xx_flash.h:133
+
FLASH_Sector_6
#define FLASH_Sector_6
Definition: stm32f4xx_flash.h:137
+
FLASH_Sector_17
#define FLASH_Sector_17
Definition: stm32f4xx_flash.h:148
+
FLASH_Sector_22
#define FLASH_Sector_22
Definition: stm32f4xx_flash.h:153
+
FLASH_Sector_16
#define FLASH_Sector_16
Definition: stm32f4xx_flash.h:147
+
FLASH_Sector_8
#define FLASH_Sector_8
Definition: stm32f4xx_flash.h:139
+
FLASH_Sector_13
#define FLASH_Sector_13
Definition: stm32f4xx_flash.h:144
+
FLASH_Sector_20
#define FLASH_Sector_20
Definition: stm32f4xx_flash.h:151
+
FLASH_Sector_7
#define FLASH_Sector_7
Definition: stm32f4xx_flash.h:138
+
FLASH_Sector_1
#define FLASH_Sector_1
Definition: stm32f4xx_flash.h:132
+
FLASH_Sector_10
#define FLASH_Sector_10
Definition: stm32f4xx_flash.h:141
+
FLASH_Sector_12
#define FLASH_Sector_12
Definition: stm32f4xx_flash.h:143
+
FLASH_Sector_5
#define FLASH_Sector_5
Definition: stm32f4xx_flash.h:136
+
FLASH_Sector_9
#define FLASH_Sector_9
Definition: stm32f4xx_flash.h:140
+
FLASH_Sector_0
#define FLASH_Sector_0
Definition: stm32f4xx_flash.h:131
+
FLASH_Sector_19
#define FLASH_Sector_19
Definition: stm32f4xx_flash.h:150
+
FLASH_Sector_21
#define FLASH_Sector_21
Definition: stm32f4xx_flash.h:152
+
FLASH_Sector_15
#define FLASH_Sector_15
Definition: stm32f4xx_flash.h:146
+
FLASH_Sector_11
#define FLASH_Sector_11
Definition: stm32f4xx_flash.h:142
+
FLASH_Sector_14
#define FLASH_Sector_14
Definition: stm32f4xx_flash.h:145
+
FLASH_Sector_4
#define FLASH_Sector_4
Definition: stm32f4xx_flash.h:135
+
FLASH_Sector_23
#define FLASH_Sector_23
Definition: stm32f4xx_flash.h:154
+
FLASH_Sector_18
#define FLASH_Sector_18
Definition: stm32f4xx_flash.h:149
+
FLASH_Sector_3
#define FLASH_Sector_3
Definition: stm32f4xx_flash.h:134
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_l_a_s_h___sectors.map b/group___f_l_a_s_h___sectors.map new file mode 100644 index 0000000..7f44943 --- /dev/null +++ b/group___f_l_a_s_h___sectors.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_l_a_s_h___sectors.md5 b/group___f_l_a_s_h___sectors.md5 new file mode 100644 index 0000000..118f6c4 --- /dev/null +++ b/group___f_l_a_s_h___sectors.md5 @@ -0,0 +1 @@ +6b314f968ac38097f9b150d9f410e14e \ No newline at end of file diff --git a/group___f_l_a_s_h___sectors.png b/group___f_l_a_s_h___sectors.png new file mode 100644 index 0000000..d7ef907 Binary files /dev/null and b/group___f_l_a_s_h___sectors.png differ diff --git a/group___f_l_a_s_h___voltage___range.html b/group___f_l_a_s_h___voltage___range.html new file mode 100644 index 0000000..3aaa03a --- /dev/null +++ b/group___f_l_a_s_h___voltage___range.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: FLASH_Voltage_Range + + + + + + + + + + +
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discoverpixy +
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+Macros
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+
FLASH_Voltage_Range
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for FLASH_Voltage_Range:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define VoltageRange_1   ((uint8_t)0x00)
 
#define VoltageRange_2   ((uint8_t)0x01)
 
#define VoltageRange_3   ((uint8_t)0x02)
 
#define VoltageRange_4   ((uint8_t)0x03)
 
#define IS_VOLTAGERANGE(RANGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_VOLTAGERANGE( RANGE)
+
+Value:
(((RANGE) == VoltageRange_1) || \
+
((RANGE) == VoltageRange_2) || \
+
((RANGE) == VoltageRange_3) || \
+
((RANGE) == VoltageRange_4))
+
VoltageRange_2
#define VoltageRange_2
Definition: stm32f4xx_flash.h:116
+
VoltageRange_1
#define VoltageRange_1
Definition: stm32f4xx_flash.h:115
+
VoltageRange_4
#define VoltageRange_4
Definition: stm32f4xx_flash.h:118
+
VoltageRange_3
#define VoltageRange_3
Definition: stm32f4xx_flash.h:117
+
+
+
+ +
+
+ + + + +
#define VoltageRange_1   ((uint8_t)0x00)
+
+

Device operating range: 1.8V to 2.1V

+ +
+
+ +
+
+ + + + +
#define VoltageRange_2   ((uint8_t)0x01)
+
+

Device operating range: 2.1V to 2.7V

+ +
+
+ +
+
+ + + + +
#define VoltageRange_3   ((uint8_t)0x02)
+
+

Device operating range: 2.7V to 3.6V

+ +
+
+ +
+
+ + + + +
#define VoltageRange_4   ((uint8_t)0x03)
+
+

Device operating range: 2.7V to 3.6V + External Vpp

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
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+Modules | +Classes | +Macros | +Functions | +Variables
+
+
FSMC
STM32F4xx_StdPeriph_Driver
+
+
+ +

FSMC driver modules. +More...

+
+Collaboration diagram for FSMC:
+
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+ + + + + + +

+Modules

 FSMC_Exported_Constants
 
 FSMC_Private_Functions
 
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+Classes

struct  FSMC_NORSRAMTimingInitTypeDef
 Timing parameters For NOR/SRAM Banks. More...
 
struct  FSMC_NORSRAMInitTypeDef
 FSMC NOR/SRAM Init structure definition. More...
 
struct  FSMC_NAND_PCCARDTimingInitTypeDef
 Timing parameters For FSMC NAND and PCCARD Banks. More...
 
struct  FSMC_NANDInitTypeDef
 FSMC NAND Init structure definition. More...
 
struct  FSMC_PCCARDInitTypeDef
 FSMC PCCARD Init structure definition. More...
 
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+Macros

+#define BCR_MBKEN_SET   ((uint32_t)0x00000001)
 
+#define BCR_MBKEN_RESET   ((uint32_t)0x000FFFFE)
 
+#define BCR_FACCEN_SET   ((uint32_t)0x00000040)
 
+#define PCR_PBKEN_SET   ((uint32_t)0x00000004)
 
+#define PCR_PBKEN_RESET   ((uint32_t)0x000FFFFB)
 
+#define PCR_ECCEN_SET   ((uint32_t)0x00000040)
 
+#define PCR_ECCEN_RESET   ((uint32_t)0x000FFFBF)
 
+#define PCR_MEMORYTYPE_NAND   ((uint32_t)0x00000008)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NOR/SRAM Banks registers to their default reset values. More...
 
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct. More...
 
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Fills each FSMC_NORSRAMInitStruct member with its default value. More...
 
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NOR/SRAM Memory Bank. More...
 
void FSMC_NANDDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NAND Banks registers to their default reset values. More...
 
void FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct. More...
 
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Fills each FSMC_NANDInitStruct member with its default value. More...
 
void FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NAND Memory Bank. More...
 
void FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the FSMC NAND ECC feature. More...
 
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
 Returns the error correction code register value. More...
 
void FSMC_PCCARDDeInit (void)
 De-initializes the FSMC PCCARD Bank registers to their default reset values. More...
 
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct. More...
 
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Fills each FSMC_PCCARDInitStruct member with its default value. More...
 
void FSMC_PCCARDCmd (FunctionalState NewState)
 Enables or disables the PCCARD Memory Bank. More...
 
void FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
 Enables or disables the specified FSMC interrupts. More...
 
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Checks whether the specified FSMC flag is set or not. More...
 
void FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Clears the FSMC's pending flags. More...
 
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Checks whether the specified FSMC interrupt has occurred or not. More...
 
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Clears the FSMC's interrupt pending bits. More...
 
+ + + +

+Variables

const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct
 
+

Detailed Description

+

FSMC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_ClearFlag (uint32_t FSMC_Bank,
uint32_t FSMC_FLAG 
)
+
+ +

Clears the FSMC's pending flags.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • FSMC_FLAG_RisingEdge: Rising edge detection Flag.
    • +
  • FSMC_FLAG_Level: Level detection Flag.
    • +
  • FSMC_FLAG_FallingEdge: Falling edge detection Flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank,
uint32_t FSMC_IT 
)
+
+ +

Clears the FSMC's interrupt pending bits.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
+
+ +

Returns the error correction code register value.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
+
+
+
Return values
+ + +
TheError Correction Code (ECC) value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank,
uint32_t FSMC_FLAG 
)
+
+ +

Checks whether the specified FSMC flag is set or not.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • FSMC_FLAG_RisingEdge: Rising edge detection Flag.
    • +
  • FSMC_FLAG_Level: Level detection Flag.
    • +
  • FSMC_FLAG_FallingEdge: Falling edge detection Flag.
    • +
  • FSMC_FLAG_FEMPT: Fifo empty Flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of FSMC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank,
uint32_t FSMC_IT 
)
+
+ +

Checks whether the specified FSMC interrupt has occurred or not.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the FSMC interrupt source to check. This parameter can be one of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of FSMC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void FSMC_ITConfig (uint32_t FSMC_Bank,
uint32_t FSMC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified FSMC interrupts.

+
Parameters
+ + + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the FSMC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
NewStatenew state of the specified FSMC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NANDCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified NAND Memory Bank.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
NewStatenew state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDDeInit (uint32_t FSMC_Bank)
+
+ +

De-initializes the FSMC NAND Banks registers to their default reset values.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NANDECCCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the FSMC NAND ECC feature.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
NewStatenew state of the FSMC NAND ECC feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDInit (FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)
+
+ +

Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.

+
Parameters
+ + +
FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure that contains the configuration information for the FSMC NAND specified Banks.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)
+
+ +

Fills each FSMC_NANDInitStruct member with its default value.

+
Parameters
+ + +
FSMC_NANDInitStructpointer to a FSMC_NANDInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified NOR/SRAM Memory Bank.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
    • +
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
    • +
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
    • +
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
    • +
+
NewStatenew state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
+
+ +

De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
    • +
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
    • +
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
    • +
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)
+
+ +

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

+
Parameters
+ + +
FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)
+
+ +

Fills each FSMC_NORSRAMInitStruct member with its default value.

+
Parameters
+ + +
FSMC_NORSRAMInitStructpointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDCmd (FunctionalState NewState)
+
+ +

Enables or disables the PCCARD Memory Bank.

+
Parameters
+ + +
NewStatenew state of the PCCARD Memory Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDDeInit (void )
+
+ +

De-initializes the FSMC PCCARD Bank registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)
+
+ +

Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.

+
Parameters
+ + +
FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure that contains the configuration information for the FSMC PCCARD Bank.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)
+
+ +

Fills each FSMC_PCCARDInitStruct member with its default value.

+
Parameters
+ + +
FSMC_PCCARDInitStructpointer to a FSMC_PCCARDInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct
+
+Initial value:
= {0x0F,
+
0x0F,
+
0xFF,
+
0x0F,
+
0x0F,
+
0x0F,
+
FSMC_AccessMode_A
+
}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c.map b/group___f_s_m_c.map new file mode 100644 index 0000000..90986b2 --- /dev/null +++ b/group___f_s_m_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___f_s_m_c.md5 b/group___f_s_m_c.md5 new file mode 100644 index 0000000..4130acb --- /dev/null +++ b/group___f_s_m_c.md5 @@ -0,0 +1 @@ +15a09fad58762afec9fbff3930cd251e \ No newline at end of file diff --git a/group___f_s_m_c.png b/group___f_s_m_c.png new file mode 100644 index 0000000..76131b5 Binary files /dev/null and b/group___f_s_m_c.png differ diff --git a/group___f_s_m_c___access___mode.html b/group___f_s_m_c___access___mode.html new file mode 100644 index 0000000..a893852 --- /dev/null +++ b/group___f_s_m_c___access___mode.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: FSMC_Access_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Access_Mode
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Access_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define FSMC_AccessMode_A   ((uint32_t)0x00000000)
 
+#define FSMC_AccessMode_B   ((uint32_t)0x10000000)
 
+#define FSMC_AccessMode_C   ((uint32_t)0x20000000)
 
+#define FSMC_AccessMode_D   ((uint32_t)0x30000000)
 
#define IS_FSMC_ACCESS_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_ACCESS_MODE( MODE)
+
+Value:
(((MODE) == FSMC_AccessMode_A) || \
+
((MODE) == FSMC_AccessMode_B) || \
+
((MODE) == FSMC_AccessMode_C) || \
+
((MODE) == FSMC_AccessMode_D))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___access___mode.map b/group___f_s_m_c___access___mode.map new file mode 100644 index 0000000..cd034aa --- /dev/null +++ b/group___f_s_m_c___access___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___access___mode.md5 b/group___f_s_m_c___access___mode.md5 new file mode 100644 index 0000000..5eb68fb --- /dev/null +++ b/group___f_s_m_c___access___mode.md5 @@ -0,0 +1 @@ +93c6bbdc86ee8a0ba2762fc654027ac4 \ No newline at end of file diff --git a/group___f_s_m_c___access___mode.png b/group___f_s_m_c___access___mode.png new file mode 100644 index 0000000..9e5b4cd Binary files /dev/null and b/group___f_s_m_c___access___mode.png differ diff --git a/group___f_s_m_c___address___hold___time.html b/group___f_s_m_c___address___hold___time.html new file mode 100644 index 0000000..495c0f6 --- /dev/null +++ b/group___f_s_m_c___address___hold___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Address_Hold_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Address_Hold_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Address_Hold_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME)   ((TIME) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___address___hold___time.map b/group___f_s_m_c___address___hold___time.map new file mode 100644 index 0000000..476ff61 --- /dev/null +++ b/group___f_s_m_c___address___hold___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___address___hold___time.md5 b/group___f_s_m_c___address___hold___time.md5 new file mode 100644 index 0000000..bedbc6c --- /dev/null +++ b/group___f_s_m_c___address___hold___time.md5 @@ -0,0 +1 @@ +3927217fbd964d6011b4a152c849ac10 \ No newline at end of file diff --git a/group___f_s_m_c___address___hold___time.png b/group___f_s_m_c___address___hold___time.png new file mode 100644 index 0000000..215ea51 Binary files /dev/null and b/group___f_s_m_c___address___hold___time.png differ diff --git a/group___f_s_m_c___address___setup___time.html b/group___f_s_m_c___address___setup___time.html new file mode 100644 index 0000000..1dd7fb6 --- /dev/null +++ b/group___f_s_m_c___address___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Address_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Address_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Address_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME)   ((TIME) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___address___setup___time.map b/group___f_s_m_c___address___setup___time.map new file mode 100644 index 0000000..d0d5733 --- /dev/null +++ b/group___f_s_m_c___address___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___address___setup___time.md5 b/group___f_s_m_c___address___setup___time.md5 new file mode 100644 index 0000000..86d3133 --- /dev/null +++ b/group___f_s_m_c___address___setup___time.md5 @@ -0,0 +1 @@ +91fa28789367f38d5a10de29c999d4b2 \ No newline at end of file diff --git a/group___f_s_m_c___address___setup___time.png b/group___f_s_m_c___address___setup___time.png new file mode 100644 index 0000000..82d859b Binary files /dev/null and b/group___f_s_m_c___address___setup___time.png differ diff --git a/group___f_s_m_c___asynchronous_wait.html b/group___f_s_m_c___asynchronous_wait.html new file mode 100644 index 0000000..bc8b600 --- /dev/null +++ b/group___f_s_m_c___asynchronous_wait.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_AsynchronousWait + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_AsynchronousWait
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_AsynchronousWait:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_AsynchronousWait_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_AsynchronousWait_Enable   ((uint32_t)0x00008000)
 
#define IS_FSMC_ASYNWAIT(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_ASYNWAIT( STATE)
+
+Value:
(((STATE) == FSMC_AsynchronousWait_Disable) || \
+
((STATE) == FSMC_AsynchronousWait_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___asynchronous_wait.map b/group___f_s_m_c___asynchronous_wait.map new file mode 100644 index 0000000..489da15 --- /dev/null +++ b/group___f_s_m_c___asynchronous_wait.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___asynchronous_wait.md5 b/group___f_s_m_c___asynchronous_wait.md5 new file mode 100644 index 0000000..83add66 --- /dev/null +++ b/group___f_s_m_c___asynchronous_wait.md5 @@ -0,0 +1 @@ +b15ffa33ee6ee974626e4432a1b22020 \ No newline at end of file diff --git a/group___f_s_m_c___asynchronous_wait.png b/group___f_s_m_c___asynchronous_wait.png new file mode 100644 index 0000000..e894fd8 Binary files /dev/null and b/group___f_s_m_c___asynchronous_wait.png differ diff --git a/group___f_s_m_c___burst___access___mode.html b/group___f_s_m_c___burst___access___mode.html new file mode 100644 index 0000000..2d32d39 --- /dev/null +++ b/group___f_s_m_c___burst___access___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Burst_Access_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Burst_Access_Mode
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Burst_Access_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_BurstAccessMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_BurstAccessMode_Enable   ((uint32_t)0x00000100)
 
#define IS_FSMC_BURSTMODE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_BURSTMODE( STATE)
+
+Value:
(((STATE) == FSMC_BurstAccessMode_Disable) || \
+
((STATE) == FSMC_BurstAccessMode_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___burst___access___mode.map b/group___f_s_m_c___burst___access___mode.map new file mode 100644 index 0000000..e114183 --- /dev/null +++ b/group___f_s_m_c___burst___access___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___burst___access___mode.md5 b/group___f_s_m_c___burst___access___mode.md5 new file mode 100644 index 0000000..a6b8594 --- /dev/null +++ b/group___f_s_m_c___burst___access___mode.md5 @@ -0,0 +1 @@ +e516303527fd602f18022b8f7e21a645 \ No newline at end of file diff --git a/group___f_s_m_c___burst___access___mode.png b/group___f_s_m_c___burst___access___mode.png new file mode 100644 index 0000000..37151ed Binary files /dev/null and b/group___f_s_m_c___burst___access___mode.png differ diff --git a/group___f_s_m_c___bus___turn__around___duration.html b/group___f_s_m_c___bus___turn__around___duration.html new file mode 100644 index 0000000..57f24e6 --- /dev/null +++ b/group___f_s_m_c___bus___turn__around___duration.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Bus_Turn_around_Duration + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Bus_Turn_around_Duration
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Bus_Turn_around_Duration:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_TURNAROUND_TIME(TIME)   ((TIME) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___bus___turn__around___duration.map b/group___f_s_m_c___bus___turn__around___duration.map new file mode 100644 index 0000000..a805558 --- /dev/null +++ b/group___f_s_m_c___bus___turn__around___duration.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___bus___turn__around___duration.md5 b/group___f_s_m_c___bus___turn__around___duration.md5 new file mode 100644 index 0000000..a386e53 --- /dev/null +++ b/group___f_s_m_c___bus___turn__around___duration.md5 @@ -0,0 +1 @@ +cc9b22e1c479c67f3904735f0734ec66 \ No newline at end of file diff --git a/group___f_s_m_c___bus___turn__around___duration.png b/group___f_s_m_c___bus___turn__around___duration.png new file mode 100644 index 0000000..293d03d Binary files /dev/null and b/group___f_s_m_c___bus___turn__around___duration.png differ diff --git a/group___f_s_m_c___c_l_k___division.html b/group___f_s_m_c___c_l_k___division.html new file mode 100644 index 0000000..aead561 --- /dev/null +++ b/group___f_s_m_c___c_l_k___division.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_CLK_Division + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_CLK_Division
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_CLK_Division:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_CLK_DIV(DIV)   ((DIV) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___c_l_k___division.map b/group___f_s_m_c___c_l_k___division.map new file mode 100644 index 0000000..3f2a44b --- /dev/null +++ b/group___f_s_m_c___c_l_k___division.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___c_l_k___division.md5 b/group___f_s_m_c___c_l_k___division.md5 new file mode 100644 index 0000000..52dbb3c --- /dev/null +++ b/group___f_s_m_c___c_l_k___division.md5 @@ -0,0 +1 @@ +bd39ca7342cc27a9233887d8bfc02979 \ No newline at end of file diff --git a/group___f_s_m_c___c_l_k___division.png b/group___f_s_m_c___c_l_k___division.png new file mode 100644 index 0000000..3ba8a98 Binary files /dev/null and b/group___f_s_m_c___c_l_k___division.png differ diff --git a/group___f_s_m_c___data___address___bus___multiplexing.html b/group___f_s_m_c___data___address___bus___multiplexing.html new file mode 100644 index 0000000..51e9775 --- /dev/null +++ b/group___f_s_m_c___data___address___bus___multiplexing.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Data_Address_Bus_Multiplexing + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Data_Address_Bus_Multiplexing
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Data_Address_Bus_Multiplexing:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_DataAddressMux_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_DataAddressMux_Enable   ((uint32_t)0x00000002)
 
#define IS_FSMC_MUX(MUX)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_MUX( MUX)
+
+Value:
(((MUX) == FSMC_DataAddressMux_Disable) || \
+
((MUX) == FSMC_DataAddressMux_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___data___address___bus___multiplexing.map b/group___f_s_m_c___data___address___bus___multiplexing.map new file mode 100644 index 0000000..94f2aeb --- /dev/null +++ b/group___f_s_m_c___data___address___bus___multiplexing.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___data___address___bus___multiplexing.md5 b/group___f_s_m_c___data___address___bus___multiplexing.md5 new file mode 100644 index 0000000..ba7e37d --- /dev/null +++ b/group___f_s_m_c___data___address___bus___multiplexing.md5 @@ -0,0 +1 @@ +a94a7d2d98f11171da6200fd5afd3035 \ No newline at end of file diff --git a/group___f_s_m_c___data___address___bus___multiplexing.png b/group___f_s_m_c___data___address___bus___multiplexing.png new file mode 100644 index 0000000..651e3c3 Binary files /dev/null and b/group___f_s_m_c___data___address___bus___multiplexing.png differ diff --git a/group___f_s_m_c___data___latency.html b/group___f_s_m_c___data___latency.html new file mode 100644 index 0000000..d752445 --- /dev/null +++ b/group___f_s_m_c___data___latency.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Data_Latency + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Data_Latency
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Data_Latency:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_DATA_LATENCY(LATENCY)   ((LATENCY) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___data___latency.map b/group___f_s_m_c___data___latency.map new file mode 100644 index 0000000..d85118c --- /dev/null +++ b/group___f_s_m_c___data___latency.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___data___latency.md5 b/group___f_s_m_c___data___latency.md5 new file mode 100644 index 0000000..ee579ed --- /dev/null +++ b/group___f_s_m_c___data___latency.md5 @@ -0,0 +1 @@ +05fc8f025771310f771b0eb5f60ed2b2 \ No newline at end of file diff --git a/group___f_s_m_c___data___latency.png b/group___f_s_m_c___data___latency.png new file mode 100644 index 0000000..4597ae1 Binary files /dev/null and b/group___f_s_m_c___data___latency.png differ diff --git a/group___f_s_m_c___data___setup___time.html b/group___f_s_m_c___data___setup___time.html new file mode 100644 index 0000000..4787dfa --- /dev/null +++ b/group___f_s_m_c___data___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Data_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Data_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Data_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_DATASETUP_TIME(TIME)   (((TIME) > 0) && ((TIME) <= 0xFF))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___data___setup___time.map b/group___f_s_m_c___data___setup___time.map new file mode 100644 index 0000000..6e593aa --- /dev/null +++ b/group___f_s_m_c___data___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___data___setup___time.md5 b/group___f_s_m_c___data___setup___time.md5 new file mode 100644 index 0000000..8babcc5 --- /dev/null +++ b/group___f_s_m_c___data___setup___time.md5 @@ -0,0 +1 @@ +ab5d82a6bf156eaf8051538b66d1088e \ No newline at end of file diff --git a/group___f_s_m_c___data___setup___time.png b/group___f_s_m_c___data___setup___time.png new file mode 100644 index 0000000..09cba7e Binary files /dev/null and b/group___f_s_m_c___data___setup___time.png differ diff --git a/group___f_s_m_c___data___width.html b/group___f_s_m_c___data___width.html new file mode 100644 index 0000000..cfcd13b --- /dev/null +++ b/group___f_s_m_c___data___width.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Data_Width + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Data_Width
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Data_Width:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_MemoryDataWidth_8b   ((uint32_t)0x00000000)
 
+#define FSMC_MemoryDataWidth_16b   ((uint32_t)0x00000010)
 
#define IS_FSMC_MEMORY_WIDTH(WIDTH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_MEMORY_WIDTH( WIDTH)
+
+Value:
(((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+
((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___data___width.map b/group___f_s_m_c___data___width.map new file mode 100644 index 0000000..0bca729 --- /dev/null +++ b/group___f_s_m_c___data___width.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___data___width.md5 b/group___f_s_m_c___data___width.md5 new file mode 100644 index 0000000..0ebf0ba --- /dev/null +++ b/group___f_s_m_c___data___width.md5 @@ -0,0 +1 @@ +08786ab3be5fb2e813da9e8d854d5193 \ No newline at end of file diff --git a/group___f_s_m_c___data___width.png b/group___f_s_m_c___data___width.png new file mode 100644 index 0000000..6b1a827 Binary files /dev/null and b/group___f_s_m_c___data___width.png differ diff --git a/group___f_s_m_c___e_c_c.html b/group___f_s_m_c___e_c_c.html new file mode 100644 index 0000000..928aecc --- /dev/null +++ b/group___f_s_m_c___e_c_c.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_ECC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_ECC
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_ECC:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_ECC_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_ECC_Enable   ((uint32_t)0x00000040)
 
#define IS_FSMC_ECC_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_ECC_STATE( STATE)
+
+Value:
(((STATE) == FSMC_ECC_Disable) || \
+
((STATE) == FSMC_ECC_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___e_c_c.map b/group___f_s_m_c___e_c_c.map new file mode 100644 index 0000000..1559940 --- /dev/null +++ b/group___f_s_m_c___e_c_c.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___e_c_c.md5 b/group___f_s_m_c___e_c_c.md5 new file mode 100644 index 0000000..c42cdc9 --- /dev/null +++ b/group___f_s_m_c___e_c_c.md5 @@ -0,0 +1 @@ +76bd7774ee2a4f597ba5534b07ece831 \ No newline at end of file diff --git a/group___f_s_m_c___e_c_c.png b/group___f_s_m_c___e_c_c.png new file mode 100644 index 0000000..801407a Binary files /dev/null and b/group___f_s_m_c___e_c_c.png differ diff --git a/group___f_s_m_c___e_c_c___page___size.html b/group___f_s_m_c___e_c_c___page___size.html new file mode 100644 index 0000000..dc0a36d --- /dev/null +++ b/group___f_s_m_c___e_c_c___page___size.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: FSMC_ECC_Page_Size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_ECC_Page_Size
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_ECC_Page_Size:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define FSMC_ECCPageSize_256Bytes   ((uint32_t)0x00000000)
 
+#define FSMC_ECCPageSize_512Bytes   ((uint32_t)0x00020000)
 
+#define FSMC_ECCPageSize_1024Bytes   ((uint32_t)0x00040000)
 
+#define FSMC_ECCPageSize_2048Bytes   ((uint32_t)0x00060000)
 
+#define FSMC_ECCPageSize_4096Bytes   ((uint32_t)0x00080000)
 
+#define FSMC_ECCPageSize_8192Bytes   ((uint32_t)0x000A0000)
 
#define IS_FSMC_ECCPAGE_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_ECCPAGE_SIZE( SIZE)
+
+Value:
(((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+
((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___e_c_c___page___size.map b/group___f_s_m_c___e_c_c___page___size.map new file mode 100644 index 0000000..8c0a1d4 --- /dev/null +++ b/group___f_s_m_c___e_c_c___page___size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___e_c_c___page___size.md5 b/group___f_s_m_c___e_c_c___page___size.md5 new file mode 100644 index 0000000..1e1a9c3 --- /dev/null +++ b/group___f_s_m_c___e_c_c___page___size.md5 @@ -0,0 +1 @@ +d575de856ff31dd9e6243806547c6734 \ No newline at end of file diff --git a/group___f_s_m_c___e_c_c___page___size.png b/group___f_s_m_c___e_c_c___page___size.png new file mode 100644 index 0000000..ee75a59 Binary files /dev/null and b/group___f_s_m_c___e_c_c___page___size.png differ diff --git a/group___f_s_m_c___exported___constants.html b/group___f_s_m_c___exported___constants.html new file mode 100644 index 0000000..4f3f5c7 --- /dev/null +++ b/group___f_s_m_c___exported___constants.html @@ -0,0 +1,205 @@ + + + + + + +discoverpixy: FSMC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
FSMC_Exported_Constants
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+
+Collaboration diagram for FSMC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Modules

 FSMC_NORSRAM_Bank
 
 FSMC_NAND_Bank
 
 FSMC_PCCARD_Bank
 
 FSMC_NOR_SRAM_Controller
 
 FSMC_NAND_PCCARD_Controller
 
+ + + + + + + + + +

+Macros

#define IS_FSMC_NORSRAM_BANK(BANK)
 
#define IS_FSMC_NAND_BANK(BANK)
 
#define IS_FSMC_GETFLAG_BANK(BANK)
 
#define IS_FSMC_IT_BANK(BANK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_GETFLAG_BANK( BANK)
+
+Value:
(((BANK) == FSMC_Bank2_NAND) || \
+
((BANK) == FSMC_Bank3_NAND) || \
+
((BANK) == FSMC_Bank4_PCCARD))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_FSMC_IT_BANK( BANK)
+
+Value:
(((BANK) == FSMC_Bank2_NAND) || \
+
((BANK) == FSMC_Bank3_NAND) || \
+
((BANK) == FSMC_Bank4_PCCARD))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_FSMC_NAND_BANK( BANK)
+
+Value:
(((BANK) == FSMC_Bank2_NAND) || \
+
((BANK) == FSMC_Bank3_NAND))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_FSMC_NORSRAM_BANK( BANK)
+
+Value:
(((BANK) == FSMC_Bank1_NORSRAM1) || \
+
((BANK) == FSMC_Bank1_NORSRAM2) || \
+
((BANK) == FSMC_Bank1_NORSRAM3) || \
+
((BANK) == FSMC_Bank1_NORSRAM4))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___exported___constants.map b/group___f_s_m_c___exported___constants.map new file mode 100644 index 0000000..c8bd779 --- /dev/null +++ b/group___f_s_m_c___exported___constants.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___f_s_m_c___exported___constants.md5 b/group___f_s_m_c___exported___constants.md5 new file mode 100644 index 0000000..c31c5f3 --- /dev/null +++ b/group___f_s_m_c___exported___constants.md5 @@ -0,0 +1 @@ +dc5b996540886b3b3956e60abf382703 \ No newline at end of file diff --git a/group___f_s_m_c___exported___constants.png b/group___f_s_m_c___exported___constants.png new file mode 100644 index 0000000..2bc0790 Binary files /dev/null and b/group___f_s_m_c___exported___constants.png differ diff --git a/group___f_s_m_c___extended___mode.html b/group___f_s_m_c___extended___mode.html new file mode 100644 index 0000000..163e097 --- /dev/null +++ b/group___f_s_m_c___extended___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Extended_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
FSMC_Extended_Mode
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Extended_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_ExtendedMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_ExtendedMode_Enable   ((uint32_t)0x00004000)
 
#define IS_FSMC_EXTENDED_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_EXTENDED_MODE( MODE)
+
+Value:
(((MODE) == FSMC_ExtendedMode_Disable) || \
+
((MODE) == FSMC_ExtendedMode_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___extended___mode.map b/group___f_s_m_c___extended___mode.map new file mode 100644 index 0000000..2f5e4d9 --- /dev/null +++ b/group___f_s_m_c___extended___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___extended___mode.md5 b/group___f_s_m_c___extended___mode.md5 new file mode 100644 index 0000000..57815f4 --- /dev/null +++ b/group___f_s_m_c___extended___mode.md5 @@ -0,0 +1 @@ +2ba96da94bfb522cad473422c386608e \ No newline at end of file diff --git a/group___f_s_m_c___extended___mode.png b/group___f_s_m_c___extended___mode.png new file mode 100644 index 0000000..e42a9da Binary files /dev/null and b/group___f_s_m_c___extended___mode.png differ diff --git a/group___f_s_m_c___flags.html b/group___f_s_m_c___flags.html new file mode 100644 index 0000000..dae2419 --- /dev/null +++ b/group___f_s_m_c___flags.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: FSMC_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
FSMC_Flags
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define FSMC_FLAG_RisingEdge   ((uint32_t)0x00000001)
 
+#define FSMC_FLAG_Level   ((uint32_t)0x00000002)
 
+#define FSMC_FLAG_FallingEdge   ((uint32_t)0x00000004)
 
+#define FSMC_FLAG_FEMPT   ((uint32_t)0x00000040)
 
#define IS_FSMC_GET_FLAG(FLAG)
 
+#define IS_FSMC_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == FSMC_FLAG_RisingEdge) || \
+
((FLAG) == FSMC_FLAG_Level) || \
+
((FLAG) == FSMC_FLAG_FallingEdge) || \
+
((FLAG) == FSMC_FLAG_FEMPT))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___flags.map b/group___f_s_m_c___flags.map new file mode 100644 index 0000000..4471883 --- /dev/null +++ b/group___f_s_m_c___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___flags.md5 b/group___f_s_m_c___flags.md5 new file mode 100644 index 0000000..8c70db8 --- /dev/null +++ b/group___f_s_m_c___flags.md5 @@ -0,0 +1 @@ +15b08f3b013a10ae623dd4689db8f576 \ No newline at end of file diff --git a/group___f_s_m_c___flags.png b/group___f_s_m_c___flags.png new file mode 100644 index 0000000..753f98f Binary files /dev/null and b/group___f_s_m_c___flags.png differ diff --git a/group___f_s_m_c___group1.html b/group___f_s_m_c___group1.html new file mode 100644 index 0000000..b28d5b4 --- /dev/null +++ b/group___f_s_m_c___group1.html @@ -0,0 +1,294 @@ + + + + + + +discoverpixy: NOR/SRAM Controller functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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+ + +
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+Functions
+
+
NOR/SRAM Controller functions
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Private_Functions
+
+
+ +

NOR/SRAM Controller functions. +More...

+
+Collaboration diagram for NOR/SRAM Controller functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NOR/SRAM Banks registers to their default reset values. More...
 
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct. More...
 
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Fills each FSMC_NORSRAMInitStruct member with its default value. More...
 
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NOR/SRAM Memory Bank. More...
 
+

Detailed Description

+

NOR/SRAM Controller functions.

+
 ===============================================================================
+                    ##### NOR and SRAM Controller functions #####
+ ===============================================================================  
+
+ [..] The following sequence should be followed to configure the FSMC to interface
+      with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
+ 
+   (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+   (#) FSMC pins configuration 
+       (++) Connect the involved FSMC pins to AF12 using the following function 
+            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       (++) Configure these FSMC pins in alternate function mode by calling the function
+            GPIO_Init();    
+       
+   (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
+          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
+      the structure member.
+      
+   (#) Initialize the NOR/SRAM Controller by calling the function
+          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+   (#) Then enable the NOR/SRAM Bank, for example:
+          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);  
+
+   (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified NOR/SRAM Memory Bank.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
    • +
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
    • +
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
    • +
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
    • +
+
NewStatenew state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
+
+ +

De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
    • +
  • FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
    • +
  • FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
    • +
  • FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)
+
+ +

Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct.

+
Parameters
+ + +
FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure that contains the configuration information for the FSMC NOR/SRAM specified Banks.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)
+
+ +

Fills each FSMC_NORSRAMInitStruct member with its default value.

+
Parameters
+ + +
FSMC_NORSRAMInitStructpointer to a FSMC_NORSRAMInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___group1.map b/group___f_s_m_c___group1.map new file mode 100644 index 0000000..96018af --- /dev/null +++ b/group___f_s_m_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___group1.md5 b/group___f_s_m_c___group1.md5 new file mode 100644 index 0000000..d73d68c --- /dev/null +++ b/group___f_s_m_c___group1.md5 @@ -0,0 +1 @@ +fb83bb148bda78dac359a4039eef469c \ No newline at end of file diff --git a/group___f_s_m_c___group1.png b/group___f_s_m_c___group1.png new file mode 100644 index 0000000..71a11e8 Binary files /dev/null and b/group___f_s_m_c___group1.png differ diff --git a/group___f_s_m_c___group2.html b/group___f_s_m_c___group2.html new file mode 100644 index 0000000..4985579 --- /dev/null +++ b/group___f_s_m_c___group2.html @@ -0,0 +1,382 @@ + + + + + + +discoverpixy: NAND Controller functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
NAND Controller functions
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Private_Functions
+
+
+ +

NAND Controller functions. +More...

+
+Collaboration diagram for NAND Controller functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void FSMC_NANDDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NAND Banks registers to their default reset values. More...
 
void FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct. More...
 
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Fills each FSMC_NANDInitStruct member with its default value. More...
 
void FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NAND Memory Bank. More...
 
void FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the FSMC NAND ECC feature. More...
 
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
 Returns the error correction code register value. More...
 
+

Detailed Description

+

NAND Controller functions.

+
 ===============================================================================
+                    ##### NAND Controller functions #####
+ ===============================================================================  
+
+ [..]  The following sequence should be followed to configure the FSMC to interface 
+       with 8-bit or 16-bit NAND memory connected to the NAND Bank:
+ 
+  (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
+      (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+      (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+  (#) FSMC pins configuration 
+      (++) Connect the involved FSMC pins to AF12 using the following function 
+           GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+      (++) Configure these FSMC pins in alternate function mode by calling the function
+           GPIO_Init();    
+       
+  (#) Declare a FSMC_NANDInitTypeDef structure, for example:
+      FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;
+      and fill the FSMC_NANDInitStructure variable with the allowed values of
+      the structure member.
+      
+  (#) Initialize the NAND Controller by calling the function
+      FSMC_NANDInit(&FSMC_NANDInitStructure); 
+
+  (#) Then enable the NAND Bank, for example:
+      FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);  
+
+  (#) At this stage you can read/write from/to the memory connected to the NAND Bank. 
+   
+ [..]
+  (@) To enable the Error Correction Code (ECC), you have to use the function
+      FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);  
+ [..]
+  (@) and to get the current ECC value you have to use the function
+      ECCval = FSMC_GetECC(FSMC_Bank3_NAND);

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
+
+ +

Returns the error correction code register value.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
+
+
+
Return values
+ + +
TheError Correction Code (ECC) value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NANDCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified NAND Memory Bank.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
NewStatenew state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDDeInit (uint32_t FSMC_Bank)
+
+ +

De-initializes the FSMC NAND Banks registers to their default reset values.

+
Parameters
+ + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_NANDECCCmd (uint32_t FSMC_Bank,
FunctionalState NewState 
)
+
+ +

Enables or disables the FSMC NAND ECC feature.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
+
NewStatenew state of the FSMC NAND ECC feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDInit (FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)
+
+ +

Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.

+
Parameters
+ + +
FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure that contains the configuration information for the FSMC NAND specified Banks.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)
+
+ +

Fills each FSMC_NANDInitStruct member with its default value.

+
Parameters
+ + +
FSMC_NANDInitStructpointer to a FSMC_NANDInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___group2.map b/group___f_s_m_c___group2.map new file mode 100644 index 0000000..62f90d9 --- /dev/null +++ b/group___f_s_m_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___group2.md5 b/group___f_s_m_c___group2.md5 new file mode 100644 index 0000000..465d5f7 --- /dev/null +++ b/group___f_s_m_c___group2.md5 @@ -0,0 +1 @@ +8a82ed82074517def3362723fd1fac26 \ No newline at end of file diff --git a/group___f_s_m_c___group2.png b/group___f_s_m_c___group2.png new file mode 100644 index 0000000..d815058 Binary files /dev/null and b/group___f_s_m_c___group2.png differ diff --git a/group___f_s_m_c___group3.html b/group___f_s_m_c___group3.html new file mode 100644 index 0000000..5f2b6b8 --- /dev/null +++ b/group___f_s_m_c___group3.html @@ -0,0 +1,271 @@ + + + + + + +discoverpixy: PCCARD Controller functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Functions
+
+
PCCARD Controller functions
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Private_Functions
+
+
+ +

PCCARD Controller functions. +More...

+
+Collaboration diagram for PCCARD Controller functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void FSMC_PCCARDDeInit (void)
 De-initializes the FSMC PCCARD Bank registers to their default reset values. More...
 
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct. More...
 
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Fills each FSMC_PCCARDInitStruct member with its default value. More...
 
void FSMC_PCCARDCmd (FunctionalState NewState)
 Enables or disables the PCCARD Memory Bank. More...
 
+

Detailed Description

+

PCCARD Controller functions.

+
 ===============================================================================
+                    ##### PCCARD Controller functions #####
+ ===============================================================================  
+
+ [..]  he following sequence should be followed to configure the FSMC to interface 
+       with 16-bit PC Card compatible memory connected to the PCCARD Bank:
+ 
+  (#)  Enable the clock for the FSMC and associated GPIOs using the following functions:
+       (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+       (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+  (#) FSMC pins configuration 
+       (++) Connect the involved FSMC pins to AF12 using the following function 
+            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       (++) Configure these FSMC pins in alternate function mode by calling the function
+            GPIO_Init();    
+       
+  (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
+      FSMC_PCCARDInitTypeDef  FSMC_PCCARDInitStructure;
+      and fill the FSMC_PCCARDInitStructure variable with the allowed values of
+      the structure member.
+      
+  (#) Initialize the PCCARD Controller by calling the function
+      FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); 
+
+  (#) Then enable the PCCARD Bank:
+      FSMC_PCCARDCmd(ENABLE);  
+
+  (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.

Function Documentation

+ +
+
+ + + + + + + + +
void FSMC_PCCARDCmd (FunctionalState NewState)
+
+ +

Enables or disables the PCCARD Memory Bank.

+
Parameters
+ + +
NewStatenew state of the PCCARD Memory Bank. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDDeInit (void )
+
+ +

De-initializes the FSMC PCCARD Bank registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)
+
+ +

Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.

+
Parameters
+ + +
FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure that contains the configuration information for the FSMC PCCARD Bank.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)
+
+ +

Fills each FSMC_PCCARDInitStruct member with its default value.

+
Parameters
+ + +
FSMC_PCCARDInitStructpointer to a FSMC_PCCARDInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___group3.map b/group___f_s_m_c___group3.map new file mode 100644 index 0000000..c1b71a3 --- /dev/null +++ b/group___f_s_m_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___group3.md5 b/group___f_s_m_c___group3.md5 new file mode 100644 index 0000000..7f0d58c --- /dev/null +++ b/group___f_s_m_c___group3.md5 @@ -0,0 +1 @@ +f6bd7288805b5b54aee6f79f64e8781f \ No newline at end of file diff --git a/group___f_s_m_c___group3.png b/group___f_s_m_c___group3.png new file mode 100644 index 0000000..7a08bc5 Binary files /dev/null and b/group___f_s_m_c___group3.png differ diff --git a/group___f_s_m_c___group4.html b/group___f_s_m_c___group4.html new file mode 100644 index 0000000..bdf0e8d --- /dev/null +++ b/group___f_s_m_c___group4.html @@ -0,0 +1,391 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
 Enables or disables the specified FSMC interrupts. More...
 
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Checks whether the specified FSMC flag is set or not. More...
 
void FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Clears the FSMC's pending flags. More...
 
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Checks whether the specified FSMC interrupt has occurred or not. More...
 
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Clears the FSMC's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_ClearFlag (uint32_t FSMC_Bank,
uint32_t FSMC_FLAG 
)
+
+ +

Clears the FSMC's pending flags.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • FSMC_FLAG_RisingEdge: Rising edge detection Flag.
    • +
  • FSMC_FLAG_Level: Level detection Flag.
    • +
  • FSMC_FLAG_FallingEdge: Falling edge detection Flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank,
uint32_t FSMC_IT 
)
+
+ +

Clears the FSMC's interrupt pending bits.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank,
uint32_t FSMC_FLAG 
)
+
+ +

Checks whether the specified FSMC flag is set or not.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • FSMC_FLAG_RisingEdge: Rising edge detection Flag.
    • +
  • FSMC_FLAG_Level: Level detection Flag.
    • +
  • FSMC_FLAG_FallingEdge: Falling edge detection Flag.
    • +
  • FSMC_FLAG_FEMPT: Fifo empty Flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of FSMC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank,
uint32_t FSMC_IT 
)
+
+ +

Checks whether the specified FSMC interrupt has occurred or not.

+
Parameters
+ + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the FSMC interrupt source to check. This parameter can be one of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of FSMC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void FSMC_ITConfig (uint32_t FSMC_Bank,
uint32_t FSMC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified FSMC interrupts.

+
Parameters
+ + + + +
FSMC_Bankspecifies the FSMC Bank to be used This parameter can be one of the following values:
    +
  • FSMC_Bank2_NAND: FSMC Bank2 NAND
    • +
  • FSMC_Bank3_NAND: FSMC Bank3 NAND
    • +
  • FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
    • +
+
FSMC_ITspecifies the FSMC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • FSMC_IT_RisingEdge: Rising edge detection interrupt.
    • +
  • FSMC_IT_Level: Level edge detection interrupt.
    • +
  • FSMC_IT_FallingEdge: Falling edge detection interrupt.
    • +
+
NewStatenew state of the specified FSMC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___group4.map b/group___f_s_m_c___group4.map new file mode 100644 index 0000000..dbb35f0 --- /dev/null +++ b/group___f_s_m_c___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___group4.md5 b/group___f_s_m_c___group4.md5 new file mode 100644 index 0000000..d6aa8af --- /dev/null +++ b/group___f_s_m_c___group4.md5 @@ -0,0 +1 @@ +2a16acb3d63a0810c81c6518447041c0 \ No newline at end of file diff --git a/group___f_s_m_c___group4.png b/group___f_s_m_c___group4.png new file mode 100644 index 0000000..bc546df Binary files /dev/null and b/group___f_s_m_c___group4.png differ diff --git a/group___f_s_m_c___hi_z___setup___time.html b/group___f_s_m_c___hi_z___setup___time.html new file mode 100644 index 0000000..702a8b3 --- /dev/null +++ b/group___f_s_m_c___hi_z___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_HiZ_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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+ + +
+ +
+ +
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+Macros
+
+
FSMC_HiZ_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_HiZ_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_HIZ_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___hi_z___setup___time.map b/group___f_s_m_c___hi_z___setup___time.map new file mode 100644 index 0000000..df0c9e6 --- /dev/null +++ b/group___f_s_m_c___hi_z___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___hi_z___setup___time.md5 b/group___f_s_m_c___hi_z___setup___time.md5 new file mode 100644 index 0000000..0f55ba4 --- /dev/null +++ b/group___f_s_m_c___hi_z___setup___time.md5 @@ -0,0 +1 @@ +a3bb1cb8345debfa7a8f192c9999fbf2 \ No newline at end of file diff --git a/group___f_s_m_c___hi_z___setup___time.png b/group___f_s_m_c___hi_z___setup___time.png new file mode 100644 index 0000000..db4c1d4 Binary files /dev/null and b/group___f_s_m_c___hi_z___setup___time.png differ diff --git a/group___f_s_m_c___hold___setup___time.html b/group___f_s_m_c___hold___setup___time.html new file mode 100644 index 0000000..f0ded7c --- /dev/null +++ b/group___f_s_m_c___hold___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Hold_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
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+ +
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+Macros
+
+
FSMC_Hold_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Hold_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_HOLD_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___hold___setup___time.map b/group___f_s_m_c___hold___setup___time.map new file mode 100644 index 0000000..28ed594 --- /dev/null +++ b/group___f_s_m_c___hold___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___hold___setup___time.md5 b/group___f_s_m_c___hold___setup___time.md5 new file mode 100644 index 0000000..86a7164 --- /dev/null +++ b/group___f_s_m_c___hold___setup___time.md5 @@ -0,0 +1 @@ +13d469c6cb20b398be9d3dbc419a4412 \ No newline at end of file diff --git a/group___f_s_m_c___hold___setup___time.png b/group___f_s_m_c___hold___setup___time.png new file mode 100644 index 0000000..03b8f1e Binary files /dev/null and b/group___f_s_m_c___hold___setup___time.png differ diff --git a/group___f_s_m_c___interrupt__sources.html b/group___f_s_m_c___interrupt__sources.html new file mode 100644 index 0000000..5c98425 --- /dev/null +++ b/group___f_s_m_c___interrupt__sources.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: FSMC_Interrupt_sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
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+Macros
+
+
FSMC_Interrupt_sources
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Interrupt_sources:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define FSMC_IT_RisingEdge   ((uint32_t)0x00000008)
 
+#define FSMC_IT_Level   ((uint32_t)0x00000010)
 
+#define FSMC_IT_FallingEdge   ((uint32_t)0x00000020)
 
+#define IS_FSMC_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
 
#define IS_FSMC_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_GET_IT( IT)
+
+Value:
(((IT) == FSMC_IT_RisingEdge) || \
+
((IT) == FSMC_IT_Level) || \
+
((IT) == FSMC_IT_FallingEdge))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___interrupt__sources.map b/group___f_s_m_c___interrupt__sources.map new file mode 100644 index 0000000..8a157e3 --- /dev/null +++ b/group___f_s_m_c___interrupt__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___interrupt__sources.md5 b/group___f_s_m_c___interrupt__sources.md5 new file mode 100644 index 0000000..d96e2ef --- /dev/null +++ b/group___f_s_m_c___interrupt__sources.md5 @@ -0,0 +1 @@ +6b83ddd59d5e37d5a396f3856af2b2ae \ No newline at end of file diff --git a/group___f_s_m_c___interrupt__sources.png b/group___f_s_m_c___interrupt__sources.png new file mode 100644 index 0000000..7155022 Binary files /dev/null and b/group___f_s_m_c___interrupt__sources.png differ diff --git a/group___f_s_m_c___memory___type.html b/group___f_s_m_c___memory___type.html new file mode 100644 index 0000000..85593d9 --- /dev/null +++ b/group___f_s_m_c___memory___type.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: FSMC_Memory_Type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Memory_Type
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Memory_Type:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define FSMC_MemoryType_SRAM   ((uint32_t)0x00000000)
 
+#define FSMC_MemoryType_PSRAM   ((uint32_t)0x00000004)
 
+#define FSMC_MemoryType_NOR   ((uint32_t)0x00000008)
 
#define IS_FSMC_MEMORY(MEMORY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_MEMORY( MEMORY)
+
+Value:
(((MEMORY) == FSMC_MemoryType_SRAM) || \
+
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+
((MEMORY) == FSMC_MemoryType_NOR))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___memory___type.map b/group___f_s_m_c___memory___type.map new file mode 100644 index 0000000..5b0bbf8 --- /dev/null +++ b/group___f_s_m_c___memory___type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___memory___type.md5 b/group___f_s_m_c___memory___type.md5 new file mode 100644 index 0000000..b0a7af3 --- /dev/null +++ b/group___f_s_m_c___memory___type.md5 @@ -0,0 +1 @@ +ac47785a2a8c63213a326219ee89f0cc \ No newline at end of file diff --git a/group___f_s_m_c___memory___type.png b/group___f_s_m_c___memory___type.png new file mode 100644 index 0000000..b0da396 Binary files /dev/null and b/group___f_s_m_c___memory___type.png differ diff --git a/group___f_s_m_c___n_a_n_d___bank.html b/group___f_s_m_c___n_a_n_d___bank.html new file mode 100644 index 0000000..eda9735 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___bank.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: FSMC_NAND_Bank + + + + + + + + + + +
+
+ + + + + + +
+
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+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_NAND_Bank
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants
+
+
+
+Collaboration diagram for FSMC_NAND_Bank:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define FSMC_Bank2_NAND   ((uint32_t)0x00000010)
 
+#define FSMC_Bank3_NAND   ((uint32_t)0x00000100)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___n_a_n_d___bank.map b/group___f_s_m_c___n_a_n_d___bank.map new file mode 100644 index 0000000..6a53271 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___bank.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___n_a_n_d___bank.md5 b/group___f_s_m_c___n_a_n_d___bank.md5 new file mode 100644 index 0000000..e0b2d89 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___bank.md5 @@ -0,0 +1 @@ +afe4b309c720d84d32931be4de630d32 \ No newline at end of file diff --git a/group___f_s_m_c___n_a_n_d___bank.png b/group___f_s_m_c___n_a_n_d___bank.png new file mode 100644 index 0000000..85da0d6 Binary files /dev/null and b/group___f_s_m_c___n_a_n_d___bank.png differ diff --git a/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.html b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.html new file mode 100644 index 0000000..5ae9b61 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: FSMC_NAND_PCCARD_Controller + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
FSMC_NAND_PCCARD_Controller
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants
+
+
+
+Collaboration diagram for FSMC_NAND_PCCARD_Controller:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 FSMC_Wait_feature
 
 FSMC_ECC
 
 FSMC_ECC_Page_Size
 
 FSMC_TCLR_Setup_Time
 
 FSMC_TAR_Setup_Time
 
 FSMC_Setup_Time
 
 FSMC_Wait_Setup_Time
 
 FSMC_Hold_Setup_Time
 
 FSMC_HiZ_Setup_Time
 
 FSMC_Interrupt_sources
 
 FSMC_Flags
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.map b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.map new file mode 100644 index 0000000..c8eb0a2 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.md5 b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.md5 new file mode 100644 index 0000000..686aa94 --- /dev/null +++ b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.md5 @@ -0,0 +1 @@ +bcb0c0f55862a6e4e0144981cdb517fd \ No newline at end of file diff --git a/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.png b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.png new file mode 100644 index 0000000..098bd0e Binary files /dev/null and b/group___f_s_m_c___n_a_n_d___p_c_c_a_r_d___controller.png differ diff --git a/group___f_s_m_c___n_o_r___s_r_a_m___controller.html b/group___f_s_m_c___n_o_r___s_r_a_m___controller.html new file mode 100644 index 0000000..74e3fc3 --- /dev/null +++ b/group___f_s_m_c___n_o_r___s_r_a_m___controller.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: FSMC_NOR_SRAM_Controller + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
FSMC_NOR_SRAM_Controller
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants
+
+
+
+Collaboration diagram for FSMC_NOR_SRAM_Controller:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 FSMC_Data_Address_Bus_Multiplexing
 
 FSMC_Memory_Type
 
 FSMC_Data_Width
 
 FSMC_Burst_Access_Mode
 
 FSMC_AsynchronousWait
 
 FSMC_Wait_Signal_Polarity
 
 FSMC_Wrap_Mode
 
 FSMC_Wait_Timing
 
 FSMC_Write_Operation
 
 FSMC_Wait_Signal
 
 FSMC_Extended_Mode
 
 FSMC_Write_Burst
 
 FSMC_Address_Setup_Time
 
 FSMC_Address_Hold_Time
 
 FSMC_Data_Setup_Time
 
 FSMC_Bus_Turn_around_Duration
 
 FSMC_CLK_Division
 
 FSMC_Data_Latency
 
 FSMC_Access_Mode
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___n_o_r___s_r_a_m___controller.map b/group___f_s_m_c___n_o_r___s_r_a_m___controller.map new file mode 100644 index 0000000..3c09bc0 --- /dev/null +++ b/group___f_s_m_c___n_o_r___s_r_a_m___controller.map @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___f_s_m_c___n_o_r___s_r_a_m___controller.md5 b/group___f_s_m_c___n_o_r___s_r_a_m___controller.md5 new file mode 100644 index 0000000..71194ef --- /dev/null +++ b/group___f_s_m_c___n_o_r___s_r_a_m___controller.md5 @@ -0,0 +1 @@ +d87054589cf80218ce67f827c4767350 \ No newline at end of file diff --git a/group___f_s_m_c___n_o_r___s_r_a_m___controller.png b/group___f_s_m_c___n_o_r___s_r_a_m___controller.png new file mode 100644 index 0000000..3e3f3a7 Binary files /dev/null and b/group___f_s_m_c___n_o_r___s_r_a_m___controller.png differ diff --git a/group___f_s_m_c___n_o_r_s_r_a_m___bank.html b/group___f_s_m_c___n_o_r_s_r_a_m___bank.html new file mode 100644 index 0000000..d1f19aa --- /dev/null +++ b/group___f_s_m_c___n_o_r_s_r_a_m___bank.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: FSMC_NORSRAM_Bank + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_NORSRAM_Bank
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants
+
+
+
+Collaboration diagram for FSMC_NORSRAM_Bank:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define FSMC_Bank1_NORSRAM1   ((uint32_t)0x00000000)
 
+#define FSMC_Bank1_NORSRAM2   ((uint32_t)0x00000002)
 
+#define FSMC_Bank1_NORSRAM3   ((uint32_t)0x00000004)
 
+#define FSMC_Bank1_NORSRAM4   ((uint32_t)0x00000006)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___n_o_r_s_r_a_m___bank.map b/group___f_s_m_c___n_o_r_s_r_a_m___bank.map new file mode 100644 index 0000000..760c92d --- /dev/null +++ b/group___f_s_m_c___n_o_r_s_r_a_m___bank.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___n_o_r_s_r_a_m___bank.md5 b/group___f_s_m_c___n_o_r_s_r_a_m___bank.md5 new file mode 100644 index 0000000..f9b32b6 --- /dev/null +++ b/group___f_s_m_c___n_o_r_s_r_a_m___bank.md5 @@ -0,0 +1 @@ +90776015151a01e003cef04631dad0c3 \ No newline at end of file diff --git a/group___f_s_m_c___n_o_r_s_r_a_m___bank.png b/group___f_s_m_c___n_o_r_s_r_a_m___bank.png new file mode 100644 index 0000000..d455783 Binary files /dev/null and b/group___f_s_m_c___n_o_r_s_r_a_m___bank.png differ diff --git a/group___f_s_m_c___p_c_c_a_r_d___bank.html b/group___f_s_m_c___p_c_c_a_r_d___bank.html new file mode 100644 index 0000000..68f9ebf --- /dev/null +++ b/group___f_s_m_c___p_c_c_a_r_d___bank.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_PCCARD_Bank + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_PCCARD_Bank
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants
+
+
+
+Collaboration diagram for FSMC_PCCARD_Bank:
+
+
+ + +
+
+ + + + +

+Macros

+#define FSMC_Bank4_PCCARD   ((uint32_t)0x00001000)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___p_c_c_a_r_d___bank.map b/group___f_s_m_c___p_c_c_a_r_d___bank.map new file mode 100644 index 0000000..958b968 --- /dev/null +++ b/group___f_s_m_c___p_c_c_a_r_d___bank.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___p_c_c_a_r_d___bank.md5 b/group___f_s_m_c___p_c_c_a_r_d___bank.md5 new file mode 100644 index 0000000..37e6bf5 --- /dev/null +++ b/group___f_s_m_c___p_c_c_a_r_d___bank.md5 @@ -0,0 +1 @@ +df3ab1ff2caa51a067d24beccbd20e41 \ No newline at end of file diff --git a/group___f_s_m_c___p_c_c_a_r_d___bank.png b/group___f_s_m_c___p_c_c_a_r_d___bank.png new file mode 100644 index 0000000..7700037 Binary files /dev/null and b/group___f_s_m_c___p_c_c_a_r_d___bank.png differ diff --git a/group___f_s_m_c___private___functions.html b/group___f_s_m_c___private___functions.html new file mode 100644 index 0000000..2a32e1f --- /dev/null +++ b/group___f_s_m_c___private___functions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: FSMC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
FSMC_Private_Functions
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+
+Collaboration diagram for FSMC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 NOR/SRAM Controller functions
 NOR/SRAM Controller functions.
 
 NAND Controller functions
 NAND Controller functions.
 
 PCCARD Controller functions
 PCCARD Controller functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___private___functions.map b/group___f_s_m_c___private___functions.map new file mode 100644 index 0000000..8e46af1 --- /dev/null +++ b/group___f_s_m_c___private___functions.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___f_s_m_c___private___functions.md5 b/group___f_s_m_c___private___functions.md5 new file mode 100644 index 0000000..1523138 --- /dev/null +++ b/group___f_s_m_c___private___functions.md5 @@ -0,0 +1 @@ +132dcced3ca2f1078ac74af5521a208d \ No newline at end of file diff --git a/group___f_s_m_c___private___functions.png b/group___f_s_m_c___private___functions.png new file mode 100644 index 0000000..ea06ff3 Binary files /dev/null and b/group___f_s_m_c___private___functions.png differ diff --git a/group___f_s_m_c___setup___time.html b/group___f_s_m_c___setup___time.html new file mode 100644 index 0000000..663a262 --- /dev/null +++ b/group___f_s_m_c___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_SETUP_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___setup___time.map b/group___f_s_m_c___setup___time.map new file mode 100644 index 0000000..e106a60 --- /dev/null +++ b/group___f_s_m_c___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___setup___time.md5 b/group___f_s_m_c___setup___time.md5 new file mode 100644 index 0000000..492aacb --- /dev/null +++ b/group___f_s_m_c___setup___time.md5 @@ -0,0 +1 @@ +1a9f8e7ac3de9525c9e4bdce9ebd0814 \ No newline at end of file diff --git a/group___f_s_m_c___setup___time.png b/group___f_s_m_c___setup___time.png new file mode 100644 index 0000000..ba76482 Binary files /dev/null and b/group___f_s_m_c___setup___time.png differ diff --git a/group___f_s_m_c___t_a_r___setup___time.html b/group___f_s_m_c___t_a_r___setup___time.html new file mode 100644 index 0000000..7682d2c --- /dev/null +++ b/group___f_s_m_c___t_a_r___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_TAR_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_TAR_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_TAR_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_TAR_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___t_a_r___setup___time.map b/group___f_s_m_c___t_a_r___setup___time.map new file mode 100644 index 0000000..9fe0373 --- /dev/null +++ b/group___f_s_m_c___t_a_r___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___t_a_r___setup___time.md5 b/group___f_s_m_c___t_a_r___setup___time.md5 new file mode 100644 index 0000000..e0d0b60 --- /dev/null +++ b/group___f_s_m_c___t_a_r___setup___time.md5 @@ -0,0 +1 @@ +d8b41b63aa91964b703abdf51d30295b \ No newline at end of file diff --git a/group___f_s_m_c___t_a_r___setup___time.png b/group___f_s_m_c___t_a_r___setup___time.png new file mode 100644 index 0000000..5f40546 Binary files /dev/null and b/group___f_s_m_c___t_a_r___setup___time.png differ diff --git a/group___f_s_m_c___t_c_l_r___setup___time.html b/group___f_s_m_c___t_c_l_r___setup___time.html new file mode 100644 index 0000000..324e309 --- /dev/null +++ b/group___f_s_m_c___t_c_l_r___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_TCLR_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_TCLR_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_TCLR_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_TCLR_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___t_c_l_r___setup___time.map b/group___f_s_m_c___t_c_l_r___setup___time.map new file mode 100644 index 0000000..d4b13c4 --- /dev/null +++ b/group___f_s_m_c___t_c_l_r___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___t_c_l_r___setup___time.md5 b/group___f_s_m_c___t_c_l_r___setup___time.md5 new file mode 100644 index 0000000..7f24a9b --- /dev/null +++ b/group___f_s_m_c___t_c_l_r___setup___time.md5 @@ -0,0 +1 @@ +4b0bdaec66f5a17b55dacafc398d3155 \ No newline at end of file diff --git a/group___f_s_m_c___t_c_l_r___setup___time.png b/group___f_s_m_c___t_c_l_r___setup___time.png new file mode 100644 index 0000000..277392a Binary files /dev/null and b/group___f_s_m_c___t_c_l_r___setup___time.png differ diff --git a/group___f_s_m_c___wait___setup___time.html b/group___f_s_m_c___wait___setup___time.html new file mode 100644 index 0000000..80cc23f --- /dev/null +++ b/group___f_s_m_c___wait___setup___time.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: FSMC_Wait_Setup_Time + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wait_Setup_Time
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Wait_Setup_Time:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_FSMC_WAIT_TIME(TIME)   ((TIME) <= 0xFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wait___setup___time.map b/group___f_s_m_c___wait___setup___time.map new file mode 100644 index 0000000..d5cc5aa --- /dev/null +++ b/group___f_s_m_c___wait___setup___time.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wait___setup___time.md5 b/group___f_s_m_c___wait___setup___time.md5 new file mode 100644 index 0000000..a7da0b2 --- /dev/null +++ b/group___f_s_m_c___wait___setup___time.md5 @@ -0,0 +1 @@ +ca1db73ee9fd5470fe6d261a75aa5452 \ No newline at end of file diff --git a/group___f_s_m_c___wait___setup___time.png b/group___f_s_m_c___wait___setup___time.png new file mode 100644 index 0000000..aaf0054 Binary files /dev/null and b/group___f_s_m_c___wait___setup___time.png differ diff --git a/group___f_s_m_c___wait___signal.html b/group___f_s_m_c___wait___signal.html new file mode 100644 index 0000000..051f280 --- /dev/null +++ b/group___f_s_m_c___wait___signal.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Wait_Signal + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wait_Signal
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Wait_Signal:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WaitSignal_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignal_Enable   ((uint32_t)0x00002000)
 
#define IS_FSMC_WAITE_SIGNAL(SIGNAL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WAITE_SIGNAL( SIGNAL)
+
+Value:
(((SIGNAL) == FSMC_WaitSignal_Disable) || \
+
((SIGNAL) == FSMC_WaitSignal_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wait___signal.map b/group___f_s_m_c___wait___signal.map new file mode 100644 index 0000000..429f8dd --- /dev/null +++ b/group___f_s_m_c___wait___signal.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wait___signal.md5 b/group___f_s_m_c___wait___signal.md5 new file mode 100644 index 0000000..aa8891c --- /dev/null +++ b/group___f_s_m_c___wait___signal.md5 @@ -0,0 +1 @@ +85c9dab134cdaf8c101afc33f745a2dc \ No newline at end of file diff --git a/group___f_s_m_c___wait___signal.png b/group___f_s_m_c___wait___signal.png new file mode 100644 index 0000000..bf76c77 Binary files /dev/null and b/group___f_s_m_c___wait___signal.png differ diff --git a/group___f_s_m_c___wait___signal___polarity.html b/group___f_s_m_c___wait___signal___polarity.html new file mode 100644 index 0000000..fa208c1 --- /dev/null +++ b/group___f_s_m_c___wait___signal___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Wait_Signal_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wait_Signal_Polarity
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Wait_Signal_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WaitSignalPolarity_Low   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalPolarity_High   ((uint32_t)0x00000200)
 
#define IS_FSMC_WAIT_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WAIT_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+
((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wait___signal___polarity.map b/group___f_s_m_c___wait___signal___polarity.map new file mode 100644 index 0000000..ebedc3b --- /dev/null +++ b/group___f_s_m_c___wait___signal___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wait___signal___polarity.md5 b/group___f_s_m_c___wait___signal___polarity.md5 new file mode 100644 index 0000000..1c56034 --- /dev/null +++ b/group___f_s_m_c___wait___signal___polarity.md5 @@ -0,0 +1 @@ +2dc6b96210cc3b03dc1bdd1e0ed9b462 \ No newline at end of file diff --git a/group___f_s_m_c___wait___signal___polarity.png b/group___f_s_m_c___wait___signal___polarity.png new file mode 100644 index 0000000..0062916 Binary files /dev/null and b/group___f_s_m_c___wait___signal___polarity.png differ diff --git a/group___f_s_m_c___wait___timing.html b/group___f_s_m_c___wait___timing.html new file mode 100644 index 0000000..7adfffe --- /dev/null +++ b/group___f_s_m_c___wait___timing.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Wait_Timing + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wait_Timing
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Wait_Timing:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WaitSignalActive_BeforeWaitState   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalActive_DuringWaitState   ((uint32_t)0x00000800)
 
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WAIT_SIGNAL_ACTIVE( ACTIVE)
+
+Value:
(((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wait___timing.map b/group___f_s_m_c___wait___timing.map new file mode 100644 index 0000000..a7d7a7b --- /dev/null +++ b/group___f_s_m_c___wait___timing.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wait___timing.md5 b/group___f_s_m_c___wait___timing.md5 new file mode 100644 index 0000000..fd5f985 --- /dev/null +++ b/group___f_s_m_c___wait___timing.md5 @@ -0,0 +1 @@ +89a691650b19340b7f5082722b23b729 \ No newline at end of file diff --git a/group___f_s_m_c___wait___timing.png b/group___f_s_m_c___wait___timing.png new file mode 100644 index 0000000..132b49b Binary files /dev/null and b/group___f_s_m_c___wait___timing.png differ diff --git a/group___f_s_m_c___wait__feature.html b/group___f_s_m_c___wait__feature.html new file mode 100644 index 0000000..7a00b5f --- /dev/null +++ b/group___f_s_m_c___wait__feature.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Wait_feature + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wait_feature
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NAND_PCCARD_Controller
+
+
+
+Collaboration diagram for FSMC_Wait_feature:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_Waitfeature_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_Waitfeature_Enable   ((uint32_t)0x00000002)
 
#define IS_FSMC_WAIT_FEATURE(FEATURE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WAIT_FEATURE( FEATURE)
+
+Value:
(((FEATURE) == FSMC_Waitfeature_Disable) || \
+
((FEATURE) == FSMC_Waitfeature_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wait__feature.map b/group___f_s_m_c___wait__feature.map new file mode 100644 index 0000000..76580d6 --- /dev/null +++ b/group___f_s_m_c___wait__feature.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wait__feature.md5 b/group___f_s_m_c___wait__feature.md5 new file mode 100644 index 0000000..45652b3 --- /dev/null +++ b/group___f_s_m_c___wait__feature.md5 @@ -0,0 +1 @@ +17fcd3b56e0c823f2077edaabc789a87 \ No newline at end of file diff --git a/group___f_s_m_c___wait__feature.png b/group___f_s_m_c___wait__feature.png new file mode 100644 index 0000000..efcab56 Binary files /dev/null and b/group___f_s_m_c___wait__feature.png differ diff --git a/group___f_s_m_c___wrap___mode.html b/group___f_s_m_c___wrap___mode.html new file mode 100644 index 0000000..65347d6 --- /dev/null +++ b/group___f_s_m_c___wrap___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Wrap_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Wrap_Mode
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Wrap_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WrapMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WrapMode_Enable   ((uint32_t)0x00000400)
 
#define IS_FSMC_WRAP_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WRAP_MODE( MODE)
+
+Value:
(((MODE) == FSMC_WrapMode_Disable) || \
+
((MODE) == FSMC_WrapMode_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___wrap___mode.map b/group___f_s_m_c___wrap___mode.map new file mode 100644 index 0000000..c07e826 --- /dev/null +++ b/group___f_s_m_c___wrap___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___wrap___mode.md5 b/group___f_s_m_c___wrap___mode.md5 new file mode 100644 index 0000000..5041709 --- /dev/null +++ b/group___f_s_m_c___wrap___mode.md5 @@ -0,0 +1 @@ +50fa8f0fd4305070da22cf271c865d2e \ No newline at end of file diff --git a/group___f_s_m_c___wrap___mode.png b/group___f_s_m_c___wrap___mode.png new file mode 100644 index 0000000..26a2cea Binary files /dev/null and b/group___f_s_m_c___wrap___mode.png differ diff --git a/group___f_s_m_c___write___burst.html b/group___f_s_m_c___write___burst.html new file mode 100644 index 0000000..62c919f --- /dev/null +++ b/group___f_s_m_c___write___burst.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Write_Burst + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Write_Burst
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Write_Burst:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WriteBurst_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WriteBurst_Enable   ((uint32_t)0x00080000)
 
#define IS_FSMC_WRITE_BURST(BURST)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WRITE_BURST( BURST)
+
+Value:
(((BURST) == FSMC_WriteBurst_Disable) || \
+
((BURST) == FSMC_WriteBurst_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___write___burst.map b/group___f_s_m_c___write___burst.map new file mode 100644 index 0000000..cdabed5 --- /dev/null +++ b/group___f_s_m_c___write___burst.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___write___burst.md5 b/group___f_s_m_c___write___burst.md5 new file mode 100644 index 0000000..241860e --- /dev/null +++ b/group___f_s_m_c___write___burst.md5 @@ -0,0 +1 @@ +b7c1257d9d84856061737cb09e5fd6de \ No newline at end of file diff --git a/group___f_s_m_c___write___burst.png b/group___f_s_m_c___write___burst.png new file mode 100644 index 0000000..cb8a7a7 Binary files /dev/null and b/group___f_s_m_c___write___burst.png differ diff --git a/group___f_s_m_c___write___operation.html b/group___f_s_m_c___write___operation.html new file mode 100644 index 0000000..dad4afe --- /dev/null +++ b/group___f_s_m_c___write___operation.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: FSMC_Write_Operation + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
FSMC_Write_Operation
STM32F4xx_StdPeriph_Driver » FSMC » FSMC_Exported_Constants » FSMC_NOR_SRAM_Controller
+
+
+
+Collaboration diagram for FSMC_Write_Operation:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define FSMC_WriteOperation_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WriteOperation_Enable   ((uint32_t)0x00001000)
 
#define IS_FSMC_WRITE_OPERATION(OPERATION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_FSMC_WRITE_OPERATION( OPERATION)
+
+Value:
(((OPERATION) == FSMC_WriteOperation_Disable) || \
+
((OPERATION) == FSMC_WriteOperation_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___f_s_m_c___write___operation.map b/group___f_s_m_c___write___operation.map new file mode 100644 index 0000000..62bf779 --- /dev/null +++ b/group___f_s_m_c___write___operation.map @@ -0,0 +1,3 @@ + + + diff --git a/group___f_s_m_c___write___operation.md5 b/group___f_s_m_c___write___operation.md5 new file mode 100644 index 0000000..c18f744 --- /dev/null +++ b/group___f_s_m_c___write___operation.md5 @@ -0,0 +1 @@ +ffd0f9920c15830f4669dbb2e72c54b7 \ No newline at end of file diff --git a/group___f_s_m_c___write___operation.png b/group___f_s_m_c___write___operation.png new file mode 100644 index 0000000..357ee61 Binary files /dev/null and b/group___f_s_m_c___write___operation.png differ diff --git a/group___filtered___data___selection___mode__selection.html b/group___filtered___data___selection___mode__selection.html new file mode 100644 index 0000000..5e7f014 --- /dev/null +++ b/group___filtered___data___selection___mode__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Filtered_Data_Selection_Mode_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Filtered_Data_Selection_Mode_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Filtered_Data_Selection_Mode_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_FILTEREDDATASELECTION_BYPASSED   ((uint8_t)0x00)
 
+#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER   ((uint8_t)0x20)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___filtered___data___selection___mode__selection.map b/group___filtered___data___selection___mode__selection.map new file mode 100644 index 0000000..599199b --- /dev/null +++ b/group___filtered___data___selection___mode__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___filtered___data___selection___mode__selection.md5 b/group___filtered___data___selection___mode__selection.md5 new file mode 100644 index 0000000..3da543a --- /dev/null +++ b/group___filtered___data___selection___mode__selection.md5 @@ -0,0 +1 @@ +278f5cbbd122e12e1124363473aba32a \ No newline at end of file diff --git a/group___filtered___data___selection___mode__selection.png b/group___filtered___data___selection___mode__selection.png new file mode 100644 index 0000000..0c59404 Binary files /dev/null and b/group___filtered___data___selection___mode__selection.png differ diff --git a/group___flash___latency.html b/group___flash___latency.html new file mode 100644 index 0000000..3151bf0 --- /dev/null +++ b/group___flash___latency.html @@ -0,0 +1,397 @@ + + + + + + +discoverpixy: Flash_Latency + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Flash_Latency
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for Flash_Latency:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define FLASH_Latency_0   ((uint8_t)0x0000)
 
#define FLASH_Latency_1   ((uint8_t)0x0001)
 
#define FLASH_Latency_2   ((uint8_t)0x0002)
 
#define FLASH_Latency_3   ((uint8_t)0x0003)
 
#define FLASH_Latency_4   ((uint8_t)0x0004)
 
#define FLASH_Latency_5   ((uint8_t)0x0005)
 
#define FLASH_Latency_6   ((uint8_t)0x0006)
 
#define FLASH_Latency_7   ((uint8_t)0x0007)
 
#define FLASH_Latency_8   ((uint8_t)0x0008)
 
#define FLASH_Latency_9   ((uint8_t)0x0009)
 
#define FLASH_Latency_10   ((uint8_t)0x000A)
 
#define FLASH_Latency_11   ((uint8_t)0x000B)
 
#define FLASH_Latency_12   ((uint8_t)0x000C)
 
#define FLASH_Latency_13   ((uint8_t)0x000D)
 
#define FLASH_Latency_14   ((uint8_t)0x000E)
 
#define FLASH_Latency_15   ((uint8_t)0x000F)
 
#define IS_FLASH_LATENCY(LATENCY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define FLASH_Latency_0   ((uint8_t)0x0000)
+
+

FLASH Zero Latency cycle

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_1   ((uint8_t)0x0001)
+
+

FLASH One Latency cycle

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_10   ((uint8_t)0x000A)
+
+

FLASH Ten Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_11   ((uint8_t)0x000B)
+
+

FLASH Eleven Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_12   ((uint8_t)0x000C)
+
+

FLASH Twelve Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_13   ((uint8_t)0x000D)
+
+

FLASH Thirteen Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_14   ((uint8_t)0x000E)
+
+

FLASH Fourteen Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_15   ((uint8_t)0x000F)
+
+

FLASH Fifteen Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_2   ((uint8_t)0x0002)
+
+

FLASH Two Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_3   ((uint8_t)0x0003)
+
+

FLASH Three Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_4   ((uint8_t)0x0004)
+
+

FLASH Four Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_5   ((uint8_t)0x0005)
+
+

FLASH Five Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_6   ((uint8_t)0x0006)
+
+

FLASH Six Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_7   ((uint8_t)0x0007)
+
+

FLASH Seven Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_8   ((uint8_t)0x0008)
+
+

FLASH Eight Latency cycles

+ +
+
+ +
+
+ + + + +
#define FLASH_Latency_9   ((uint8_t)0x0009)
+
+

FLASH Nine Latency cycles

+ +
+
+ +
+
+ + + + + + + + +
#define IS_FLASH_LATENCY( LATENCY)
+
+Value:
(((LATENCY) == FLASH_Latency_0) || \
+
((LATENCY) == FLASH_Latency_1) || \
+
((LATENCY) == FLASH_Latency_2) || \
+
((LATENCY) == FLASH_Latency_3) || \
+
((LATENCY) == FLASH_Latency_4) || \
+
((LATENCY) == FLASH_Latency_5) || \
+
((LATENCY) == FLASH_Latency_6) || \
+
((LATENCY) == FLASH_Latency_7) || \
+
((LATENCY) == FLASH_Latency_8) || \
+
((LATENCY) == FLASH_Latency_9) || \
+
((LATENCY) == FLASH_Latency_10) || \
+
((LATENCY) == FLASH_Latency_11) || \
+
((LATENCY) == FLASH_Latency_12) || \
+
((LATENCY) == FLASH_Latency_13) || \
+
((LATENCY) == FLASH_Latency_14) || \
+
((LATENCY) == FLASH_Latency_15))
+
FLASH_Latency_14
#define FLASH_Latency_14
Definition: stm32f4xx_flash.h:88
+
FLASH_Latency_4
#define FLASH_Latency_4
Definition: stm32f4xx_flash.h:78
+
FLASH_Latency_3
#define FLASH_Latency_3
Definition: stm32f4xx_flash.h:77
+
FLASH_Latency_10
#define FLASH_Latency_10
Definition: stm32f4xx_flash.h:84
+
FLASH_Latency_13
#define FLASH_Latency_13
Definition: stm32f4xx_flash.h:87
+
FLASH_Latency_1
#define FLASH_Latency_1
Definition: stm32f4xx_flash.h:75
+
FLASH_Latency_7
#define FLASH_Latency_7
Definition: stm32f4xx_flash.h:81
+
FLASH_Latency_9
#define FLASH_Latency_9
Definition: stm32f4xx_flash.h:83
+
FLASH_Latency_8
#define FLASH_Latency_8
Definition: stm32f4xx_flash.h:82
+
FLASH_Latency_11
#define FLASH_Latency_11
Definition: stm32f4xx_flash.h:85
+
FLASH_Latency_6
#define FLASH_Latency_6
Definition: stm32f4xx_flash.h:80
+
FLASH_Latency_5
#define FLASH_Latency_5
Definition: stm32f4xx_flash.h:79
+
FLASH_Latency_15
#define FLASH_Latency_15
Definition: stm32f4xx_flash.h:89
+
FLASH_Latency_2
#define FLASH_Latency_2
Definition: stm32f4xx_flash.h:76
+
FLASH_Latency_0
#define FLASH_Latency_0
Definition: stm32f4xx_flash.h:74
+
FLASH_Latency_12
#define FLASH_Latency_12
Definition: stm32f4xx_flash.h:86
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___flash___latency.map b/group___flash___latency.map new file mode 100644 index 0000000..a8b4d47 --- /dev/null +++ b/group___flash___latency.map @@ -0,0 +1,3 @@ + + + diff --git a/group___flash___latency.md5 b/group___flash___latency.md5 new file mode 100644 index 0000000..564aac5 --- /dev/null +++ b/group___flash___latency.md5 @@ -0,0 +1 @@ +41a7b995b842c22e72cd983488dbdf30 \ No newline at end of file diff --git a/group___flash___latency.png b/group___flash___latency.png new file mode 100644 index 0000000..3f85155 Binary files /dev/null and b/group___flash___latency.png differ diff --git a/group___full___scale__selection.html b/group___full___scale__selection.html new file mode 100644 index 0000000..3de1f84 --- /dev/null +++ b/group___full___scale__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Full_Scale_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Full_Scale_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Full_Scale_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_FULLSCALE_2_3   ((uint8_t)0x00)
 
+#define LIS302DL_FULLSCALE_9_2   ((uint8_t)0x20)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___full___scale__selection.map b/group___full___scale__selection.map new file mode 100644 index 0000000..81e9731 --- /dev/null +++ b/group___full___scale__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___full___scale__selection.md5 b/group___full___scale__selection.md5 new file mode 100644 index 0000000..4e9a048 --- /dev/null +++ b/group___full___scale__selection.md5 @@ -0,0 +1 @@ +0e15041ce79870853dc7b6777b785194 \ No newline at end of file diff --git a/group___full___scale__selection.png b/group___full___scale__selection.png new file mode 100644 index 0000000..fd125fe Binary files /dev/null and b/group___full___scale__selection.png differ diff --git a/group___g_p_i_o.html b/group___g_p_i_o.html new file mode 100644 index 0000000..28ce2d1 --- /dev/null +++ b/group___g_p_i_o.html @@ -0,0 +1,1019 @@ + + + + + + +discoverpixy: GPIO + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Enumerations | +Functions
+
+
GPIO
STM32F4xx_StdPeriph_Driver
+
+
+ +

GPIO driver modules. +More...

+
+Collaboration diagram for GPIO:
+
+
+ + +
+
+ + + + + + +

+Modules

 GPIO_Exported_Constants
 
 GPIO_Private_Functions
 
+ + + + +

+Classes

struct  GPIO_InitTypeDef
 GPIO Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_GPIO_ALL_PERIPH(PERIPH)
 
#define IS_GPIO_MODE(MODE)
 
+#define IS_GPIO_OTYPE(OTYPE)   (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
 
+#define GPIO_Speed_2MHz   GPIO_Low_Speed
 
+#define GPIO_Speed_25MHz   GPIO_Medium_Speed
 
+#define GPIO_Speed_50MHz   GPIO_Fast_Speed
 
+#define GPIO_Speed_100MHz   GPIO_High_Speed
 
#define IS_GPIO_SPEED(SPEED)
 
#define IS_GPIO_PUPD(PUPD)
 
+#define IS_GPIO_BIT_ACTION(ACTION)   (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
 
+ + + + + + + + + + + + + + + + +

+Enumerations

enum  GPIOMode_TypeDef { GPIO_Mode_IN = 0x00, +GPIO_Mode_OUT = 0x01, +GPIO_Mode_AF = 0x02, +GPIO_Mode_AN = 0x03 + }
 GPIO Configuration Mode enumeration. More...
 
enum  GPIOOType_TypeDef { GPIO_OType_PP = 0x00, +GPIO_OType_OD = 0x01 + }
 GPIO Output type enumeration.
 
enum  GPIOSpeed_TypeDef { GPIO_Low_Speed = 0x00, +GPIO_Medium_Speed = 0x01, +GPIO_Fast_Speed = 0x02, +GPIO_High_Speed = 0x03 + }
 GPIO Output Maximum frequency enumeration. More...
 
enum  GPIOPuPd_TypeDef { GPIO_PuPd_NOPULL = 0x00, +GPIO_PuPd_UP = 0x01, +GPIO_PuPd_DOWN = 0x02 + }
 GPIO Configuration PullUp PullDown enumeration.
 
enum  BitAction { Bit_RESET = 0, +Bit_SET + }
 GPIO Bit SET and Bit RESET enumeration.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void GPIO_DeInit (GPIO_TypeDef *GPIOx)
 De-initializes the GPIOx peripheral registers to their default reset values. More...
 
void GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
 Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. More...
 
void GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
 Fills each GPIO_InitStruct member with its default value. More...
 
void GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Locks GPIO Pins configuration registers. More...
 
uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified input port pin. More...
 
uint16_t GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO input data port. More...
 
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified output data port bit. More...
 
uint16_t GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO output data port. More...
 
void GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Sets the selected data port bits. More...
 
void GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Clears the selected data port bits. More...
 
void GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 Sets or clears the selected data port bit. More...
 
void GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
 Writes data to the specified GPIO data port. More...
 
void GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Toggles the specified GPIO pins.. More...
 
void GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 Changes the mapping of the specified pin. More...
 
+

Detailed Description

+

GPIO driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_GPIO_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == GPIOA) || \
+
((PERIPH) == GPIOB) || \
+
((PERIPH) == GPIOC) || \
+
((PERIPH) == GPIOD) || \
+
((PERIPH) == GPIOE) || \
+
((PERIPH) == GPIOF) || \
+
((PERIPH) == GPIOG) || \
+
((PERIPH) == GPIOH) || \
+
((PERIPH) == GPIOI) || \
+
((PERIPH) == GPIOJ) || \
+
((PERIPH) == GPIOK))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_GPIO_MODE( MODE)
+
+Value:
(((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
+
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
GPIO_Mode_IN
Definition: stm32f4xx_gpio.h:67
+
GPIO_Mode_AF
Definition: stm32f4xx_gpio.h:69
+
GPIO_Mode_AN
Definition: stm32f4xx_gpio.h:70
+
GPIO_Mode_OUT
Definition: stm32f4xx_gpio.h:68
+
+
+
+ +
+
+ + + + + + + + +
#define IS_GPIO_PUPD( PUPD)
+
+Value:
(((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+
((PUPD) == GPIO_PuPd_DOWN))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_GPIO_SPEED( SPEED)
+
+Value:
(((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
+
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
+
GPIO_Fast_Speed
Definition: stm32f4xx_gpio.h:93
+
GPIO_Medium_Speed
Definition: stm32f4xx_gpio.h:92
+
GPIO_Low_Speed
Definition: stm32f4xx_gpio.h:91
+
GPIO_High_Speed
Definition: stm32f4xx_gpio.h:94
+
+
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum GPIOMode_TypeDef
+
+ +

GPIO Configuration Mode enumeration.

+ + + + + +
Enumerator
GPIO_Mode_IN  +

GPIO Input Mode

+
GPIO_Mode_OUT  +

GPIO Output Mode

+
GPIO_Mode_AF  +

GPIO Alternate function Mode

+
GPIO_Mode_AN  +

GPIO Analog Mode

+
+ +
+
+ +
+
+ + + + +
enum GPIOSpeed_TypeDef
+
+ +

GPIO Output Maximum frequency enumeration.

+ + + + + +
Enumerator
GPIO_Low_Speed  +

Low speed

+
GPIO_Medium_Speed  +

Medium speed

+
GPIO_Fast_Speed  +

Fast speed

+
GPIO_High_Speed  +

High speed

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void GPIO_DeInit (GPIO_TypeDef * GPIOx)
+
+ +

De-initializes the GPIOx peripheral registers to their default reset values.

+
Note
By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_Init (GPIO_TypeDef * GPIOx,
GPIO_InitTypeDef * GPIO_InitStruct 
)
+
+ +

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_InitStructpointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_PinAFConfig (GPIO_TypeDef * GPIOx,
uint16_t GPIO_PinSource,
uint8_t GPIO_AF 
)
+
+ +

Changes the mapping of the specified pin.

+
Parameters
+ + + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_PinSourcespecifies the pin for the Alternate function. This parameter can be GPIO_PinSourcex where x can be (0..15).
GPIO_AFSelectionselects the pin to used as Alternate function. This parameter can be one of the following values:
    +
  • GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
    • +
  • GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
    • +
  • GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
    • +
  • GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
    • +
  • GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
    • +
  • GPIO_AF_TIM1: Connect TIM1 pins to AF1
    • +
  • GPIO_AF_TIM2: Connect TIM2 pins to AF1
    • +
  • GPIO_AF_TIM3: Connect TIM3 pins to AF2
    • +
  • GPIO_AF_TIM4: Connect TIM4 pins to AF2
    • +
  • GPIO_AF_TIM5: Connect TIM5 pins to AF2
    • +
  • GPIO_AF_TIM8: Connect TIM8 pins to AF3
    • +
  • GPIO_AF_TIM9: Connect TIM9 pins to AF3
    • +
  • GPIO_AF_TIM10: Connect TIM10 pins to AF3
    • +
  • GPIO_AF_TIM11: Connect TIM11 pins to AF3
    • +
  • GPIO_AF_I2C1: Connect I2C1 pins to AF4
    • +
  • GPIO_AF_I2C2: Connect I2C2 pins to AF4
    • +
  • GPIO_AF_I2C3: Connect I2C3 pins to AF4
    • +
  • GPIO_AF_SPI1: Connect SPI1 pins to AF5
    • +
  • GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
    • +
  • GPIO_AF_SPI4: Connect SPI4 pins to AF5
    • +
  • GPIO_AF_SPI5: Connect SPI5 pins to AF5
    • +
  • GPIO_AF_SPI6: Connect SPI6 pins to AF5
    • +
  • GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
    • +
  • GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
    • +
  • GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
    • +
  • GPIO_AF_USART1: Connect USART1 pins to AF7
    • +
  • GPIO_AF_USART2: Connect USART2 pins to AF7
    • +
  • GPIO_AF_USART3: Connect USART3 pins to AF7
    • +
  • GPIO_AF_UART4: Connect UART4 pins to AF8
    • +
  • GPIO_AF_UART5: Connect UART5 pins to AF8
    • +
  • GPIO_AF_USART6: Connect USART6 pins to AF8
    • +
  • GPIO_AF_UART7: Connect UART7 pins to AF8
    • +
  • GPIO_AF_UART8: Connect UART8 pins to AF8
    • +
  • GPIO_AF_CAN1: Connect CAN1 pins to AF9
    • +
  • GPIO_AF_CAN2: Connect CAN2 pins to AF9
    • +
  • GPIO_AF_TIM12: Connect TIM12 pins to AF9
    • +
  • GPIO_AF_TIM13: Connect TIM13 pins to AF9
    • +
  • GPIO_AF_TIM14: Connect TIM14 pins to AF9
    • +
  • GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
    • +
  • GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
    • +
  • GPIO_AF_ETH: Connect ETHERNET pins to AF11
    • +
  • GPIO_AF_FSMC: Connect FSMC pins to AF12
    • +
  • GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
    • +
  • GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
    • +
  • GPIO_AF_SDIO: Connect SDIO pins to AF12
    • +
  • GPIO_AF_DCMI: Connect DCMI pins to AF13
    • +
  • GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
    • +
  • GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_PinLockConfig (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Locks GPIO Pins configuration registers.

+
Note
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+
+The configuration of the locked GPIO pins can no longer be modified until the next reset.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t GPIO_ReadInputData (GPIO_TypeDef * GPIOx)
+
+ +

Reads the specified GPIO input data port.

+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
GPIOinput data port value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Reads the specified input port pin.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
Theinput port pin value.
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint16_t GPIO_ReadOutputData (GPIO_TypeDef * GPIOx)
+
+ +

Reads the specified GPIO output data port.

+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
GPIOoutput data port value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Reads the specified output data port bit.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
Theoutput port pin value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_ResetBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Clears the selected data port bits.

+
Note
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_SetBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Sets the selected data port bits.

+
Note
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void GPIO_StructInit (GPIO_InitTypeDef * GPIO_InitStruct)
+
+ +

Fills each GPIO_InitStruct member with its default value.

+
Parameters
+ + +
GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_ToggleBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Toggles the specified GPIO pins..

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_PinSpecifies the pins to be toggled.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_Write (GPIO_TypeDef * GPIOx,
uint16_t PortVal 
)
+
+ +

Writes data to the specified GPIO data port.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
PortValspecifies the value to be written to the port output data register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_WriteBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin,
BitAction BitVal 
)
+
+ +

Sets or clears the selected data port bit.

+
Parameters
+ + + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitValspecifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:
    +
  • Bit_RESET: to clear the port pin
    • +
  • Bit_SET: to set the port pin
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o.map b/group___g_p_i_o.map new file mode 100644 index 0000000..a843576 --- /dev/null +++ b/group___g_p_i_o.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___g_p_i_o.md5 b/group___g_p_i_o.md5 new file mode 100644 index 0000000..21bb46d --- /dev/null +++ b/group___g_p_i_o.md5 @@ -0,0 +1 @@ +22e8e51bc38ad3b2bc941788f5765db1 \ No newline at end of file diff --git a/group___g_p_i_o.png b/group___g_p_i_o.png new file mode 100644 index 0000000..2635c69 Binary files /dev/null and b/group___g_p_i_o.png differ diff --git a/group___g_p_i_o___alternat__function__selection__define.html b/group___g_p_i_o___alternat__function__selection__define.html new file mode 100644 index 0000000..012dd19 --- /dev/null +++ b/group___g_p_i_o___alternat__function__selection__define.html @@ -0,0 +1,337 @@ + + + + + + +discoverpixy: GPIO_Alternat_function_selection_define + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Macros
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+
GPIO_Alternat_function_selection_define
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Exported_Constants
+
+
+
+Collaboration diagram for GPIO_Alternat_function_selection_define:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define GPIO_AF_RTC_50Hz   ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
 AF 0 selection.
 
+#define GPIO_AF_MCO   ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
 
+#define GPIO_AF_TAMPER   ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
 
+#define GPIO_AF_SWJ   ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
 
+#define GPIO_AF_TRACE   ((uint8_t)0x00) /* TRACE Alternate Function mapping */
 
+#define GPIO_AF_TIM1   ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
 AF 1 selection.
 
+#define GPIO_AF_TIM2   ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
 
+#define GPIO_AF_TIM3   ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
 AF 2 selection.
 
+#define GPIO_AF_TIM4   ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
 
+#define GPIO_AF_TIM5   ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
 
+#define GPIO_AF_TIM8   ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
 AF 3 selection.
 
+#define GPIO_AF_TIM9   ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
 
+#define GPIO_AF_TIM10   ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
 
+#define GPIO_AF_TIM11   ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
 
+#define GPIO_AF_I2C1   ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
 AF 4 selection.
 
+#define GPIO_AF_I2C2   ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
 
+#define GPIO_AF_I2C3   ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
 
+#define GPIO_AF_SPI1   ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
 AF 5 selection.
 
+#define GPIO_AF_SPI2   ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
 
+#define GPIO_AF5_SPI3   ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF_SPI4   ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
 
+#define GPIO_AF_SPI5   ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
 
+#define GPIO_AF_SPI6   ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
 
+#define GPIO_AF_SPI3   ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
 AF 6 selection.
 
+#define GPIO_AF6_SPI2   ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF6_SPI4   ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF6_SPI5   ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF_SAI1   ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
 
+#define GPIO_AF_USART1   ((uint8_t)0x07) /* USART1 Alternate Function mapping */
 AF 7 selection.
 
+#define GPIO_AF_USART2   ((uint8_t)0x07) /* USART2 Alternate Function mapping */
 
+#define GPIO_AF_USART3   ((uint8_t)0x07) /* USART3 Alternate Function mapping */
 
+#define GPIO_AF7_SPI3   ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
 
+#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
 AF 7 selection Legacy.
 
+#define GPIO_AF_UART4   ((uint8_t)0x08) /* UART4 Alternate Function mapping */
 AF 8 selection.
 
+#define GPIO_AF_UART5   ((uint8_t)0x08) /* UART5 Alternate Function mapping */
 
+#define GPIO_AF_USART6   ((uint8_t)0x08) /* USART6 Alternate Function mapping */
 
+#define GPIO_AF_UART7   ((uint8_t)0x08) /* UART7 Alternate Function mapping */
 
+#define GPIO_AF_UART8   ((uint8_t)0x08) /* UART8 Alternate Function mapping */
 
+#define GPIO_AF_CAN1   ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
 AF 9 selection.
 
+#define GPIO_AF_CAN2   ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
 
+#define GPIO_AF_TIM12   ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
 
+#define GPIO_AF_TIM13   ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
 
+#define GPIO_AF_TIM14   ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
 
+#define GPIO_AF9_I2C2   ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
 
+#define GPIO_AF9_I2C3   ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
 
+#define GPIO_AF_OTG_FS   ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
 AF 10 selection.
 
+#define GPIO_AF_OTG_HS   ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
 
+#define GPIO_AF_ETH   ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
 AF 11 selection.
 
+#define GPIO_AF_FSMC   ((uint8_t)0xC) /* FSMC Alternate Function mapping */
 AF 12 selection.
 
+#define GPIO_AF_OTG_HS_FS   ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
 
+#define GPIO_AF_SDIO   ((uint8_t)0xC) /* SDIO Alternate Function mapping */
 
+#define GPIO_AF_DCMI   ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
 AF 13 selection.
 
+#define GPIO_AF_LTDC   ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
 AF 14 selection.
 
+#define GPIO_AF_EVENTOUT   ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
 AF 15 selection.
 
#define IS_GPIO_AF(AF)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_GPIO_AF( AF)
+
+Value:
(((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
+
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
+
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
+
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
+
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
+
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
+
GPIO_AF_SPI1
#define GPIO_AF_SPI1
AF 5 selection.
Definition: stm32f4xx_gpio.h:283
+
GPIO_AF_I2C1
#define GPIO_AF_I2C1
AF 4 selection.
Definition: stm32f4xx_gpio.h:276
+
GPIO_AF_TIM8
#define GPIO_AF_TIM8
AF 3 selection.
Definition: stm32f4xx_gpio.h:268
+
GPIO_AF_EVENTOUT
#define GPIO_AF_EVENTOUT
AF 15 selection.
Definition: stm32f4xx_gpio.h:372
+
GPIO_AF_ETH
#define GPIO_AF_ETH
AF 11 selection.
Definition: stm32f4xx_gpio.h:342
+
GPIO_AF_RTC_50Hz
#define GPIO_AF_RTC_50Hz
AF 0 selection.
Definition: stm32f4xx_gpio.h:246
+
GPIO_AF_TIM1
#define GPIO_AF_TIM1
AF 1 selection.
Definition: stm32f4xx_gpio.h:255
+
GPIO_AF_TIM3
#define GPIO_AF_TIM3
AF 2 selection.
Definition: stm32f4xx_gpio.h:261
+
GPIO_AF_CAN1
#define GPIO_AF_CAN1
AF 9 selection.
Definition: stm32f4xx_gpio.h:324
+
GPIO_AF_OTG_FS
#define GPIO_AF_OTG_FS
AF 10 selection.
Definition: stm32f4xx_gpio.h:336
+
GPIO_AF_UART4
#define GPIO_AF_UART4
AF 8 selection.
Definition: stm32f4xx_gpio.h:315
+
GPIO_AF_USART1
#define GPIO_AF_USART1
AF 7 selection.
Definition: stm32f4xx_gpio.h:302
+
GPIO_AF_DCMI
#define GPIO_AF_DCMI
AF 13 selection.
Definition: stm32f4xx_gpio.h:361
+
GPIO_AF_FSMC
#define GPIO_AF_FSMC
AF 12 selection.
Definition: stm32f4xx_gpio.h:348
+
GPIO_AF_SPI3
#define GPIO_AF_SPI3
AF 6 selection.
Definition: stm32f4xx_gpio.h:293
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___alternat__function__selection__define.map b/group___g_p_i_o___alternat__function__selection__define.map new file mode 100644 index 0000000..ec01c3a --- /dev/null +++ b/group___g_p_i_o___alternat__function__selection__define.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___alternat__function__selection__define.md5 b/group___g_p_i_o___alternat__function__selection__define.md5 new file mode 100644 index 0000000..64c9fc6 --- /dev/null +++ b/group___g_p_i_o___alternat__function__selection__define.md5 @@ -0,0 +1 @@ +00d83e91c98a1e4695657c789c3b847c \ No newline at end of file diff --git a/group___g_p_i_o___alternat__function__selection__define.png b/group___g_p_i_o___alternat__function__selection__define.png new file mode 100644 index 0000000..2b61b06 Binary files /dev/null and b/group___g_p_i_o___alternat__function__selection__define.png differ diff --git a/group___g_p_i_o___exported___constants.html b/group___g_p_i_o___exported___constants.html new file mode 100644 index 0000000..ab095cb --- /dev/null +++ b/group___g_p_i_o___exported___constants.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: GPIO_Exported_Constants + + + + + + + + + + +
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+Modules
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GPIO_Exported_Constants
STM32F4xx_StdPeriph_Driver » GPIO
+
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+Collaboration diagram for GPIO_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + +

+Modules

 GPIO_pins_define
 
 GPIO_Pin_sources
 
 GPIO_Alternat_function_selection_define
 
 GPIO_Legacy
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___exported___constants.map b/group___g_p_i_o___exported___constants.map new file mode 100644 index 0000000..7c69b61 --- /dev/null +++ b/group___g_p_i_o___exported___constants.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___g_p_i_o___exported___constants.md5 b/group___g_p_i_o___exported___constants.md5 new file mode 100644 index 0000000..440eb2f --- /dev/null +++ b/group___g_p_i_o___exported___constants.md5 @@ -0,0 +1 @@ +3294edb97b985d373c2d2f608d5ae3ad \ No newline at end of file diff --git a/group___g_p_i_o___exported___constants.png b/group___g_p_i_o___exported___constants.png new file mode 100644 index 0000000..b50555e Binary files /dev/null and b/group___g_p_i_o___exported___constants.png differ diff --git a/group___g_p_i_o___group1.html b/group___g_p_i_o___group1.html new file mode 100644 index 0000000..6ece2f4 --- /dev/null +++ b/group___g_p_i_o___group1.html @@ -0,0 +1,289 @@ + + + + + + +discoverpixy: Initialization and Configuration + + + + + + + + + + +
+
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discoverpixy +
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+Functions
+
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Initialization and Configuration
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Private_Functions
+
+
+ +

Initialization and Configuration. +More...

+
+Collaboration diagram for Initialization and Configuration:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void GPIO_DeInit (GPIO_TypeDef *GPIOx)
 De-initializes the GPIOx peripheral registers to their default reset values. More...
 
void GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
 Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. More...
 
void GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
 Fills each GPIO_InitStruct member with its default value. More...
 
void GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Locks GPIO Pins configuration registers. More...
 
+

Detailed Description

+

Initialization and Configuration.

+
 ===============================================================================
+                 ##### Initialization and Configuration #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void GPIO_DeInit (GPIO_TypeDef * GPIOx)
+
+ +

De-initializes the GPIOx peripheral registers to their default reset values.

+
Note
By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_Init (GPIO_TypeDef * GPIOx,
GPIO_InitTypeDef * GPIO_InitStruct 
)
+
+ +

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_InitStructpointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_PinLockConfig (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Locks GPIO Pins configuration registers.

+
Note
The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+
+The configuration of the locked GPIO pins can no longer be modified until the next reset.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void GPIO_StructInit (GPIO_InitTypeDef * GPIO_InitStruct)
+
+ +

Fills each GPIO_InitStruct member with its default value.

+
Parameters
+ + +
GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___group1.map b/group___g_p_i_o___group1.map new file mode 100644 index 0000000..58e11c8 --- /dev/null +++ b/group___g_p_i_o___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___group1.md5 b/group___g_p_i_o___group1.md5 new file mode 100644 index 0000000..096dede --- /dev/null +++ b/group___g_p_i_o___group1.md5 @@ -0,0 +1 @@ +2e282e1e4ac38257edf6b287687bf465 \ No newline at end of file diff --git a/group___g_p_i_o___group1.png b/group___g_p_i_o___group1.png new file mode 100644 index 0000000..f0528d5 Binary files /dev/null and b/group___g_p_i_o___group1.png differ diff --git a/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.map b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.map new file mode 100644 index 0000000..1d1e3b9 --- /dev/null +++ b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 new file mode 100644 index 0000000..f4d5bff --- /dev/null +++ b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 @@ -0,0 +1 @@ +c1f090d09e5e24d3be81542def084077 \ No newline at end of file diff --git a/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.png b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.png new file mode 100644 index 0000000..f288fa8 Binary files /dev/null and b/group___g_p_i_o___group1_ga71abf9404261370d03cca449b88d3a65_icgraph.png differ diff --git a/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map new file mode 100644 index 0000000..0f8decb --- /dev/null +++ b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 new file mode 100644 index 0000000..1c0ffec --- /dev/null +++ b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 @@ -0,0 +1 @@ +9df65cbd2ac4a16813033c8465c130af \ No newline at end of file diff --git a/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png new file mode 100644 index 0000000..88b60ca Binary files /dev/null and b/group___g_p_i_o___group1_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png differ diff --git a/group___g_p_i_o___group2.html b/group___g_p_i_o___group2.html new file mode 100644 index 0000000..8d17bc0 --- /dev/null +++ b/group___g_p_i_o___group2.html @@ -0,0 +1,509 @@ + + + + + + +discoverpixy: GPIO Read and Write + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
GPIO Read and Write
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Private_Functions
+
+
+ +

GPIO Read and Write. +More...

+
+Collaboration diagram for GPIO Read and Write:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified input port pin. More...
 
uint16_t GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO input data port. More...
 
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified output data port bit. More...
 
uint16_t GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO output data port. More...
 
void GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Sets the selected data port bits. More...
 
void GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Clears the selected data port bits. More...
 
void GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 Sets or clears the selected data port bit. More...
 
void GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
 Writes data to the specified GPIO data port. More...
 
void GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Toggles the specified GPIO pins.. More...
 
+

Detailed Description

+

GPIO Read and Write.

+
 ===============================================================================
+                         ##### GPIO Read and Write #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t GPIO_ReadInputData (GPIO_TypeDef * GPIOx)
+
+ +

Reads the specified GPIO input data port.

+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
GPIOinput data port value.
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Reads the specified input port pin.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
Theinput port pin value.
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
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+ +
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+ + + + + + + + +
uint16_t GPIO_ReadOutputData (GPIO_TypeDef * GPIOx)
+
+ +

Reads the specified GPIO output data port.

+
Parameters
+ + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
+
+
+
Return values
+ + +
GPIOoutput data port value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Reads the specified output data port bit.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to read. This parameter can be GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
Theoutput port pin value.
+
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+ +
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+ +
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void GPIO_ResetBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Clears the selected data port bits.

+
Note
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
void GPIO_SetBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Sets the selected data port bits.

+
Note
This functions uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bits to be written. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
void GPIO_ToggleBits (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin 
)
+
+ +

Toggles the specified GPIO pins..

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_PinSpecifies the pins to be toggled.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void GPIO_Write (GPIO_TypeDef * GPIOx,
uint16_t PortVal 
)
+
+ +

Writes data to the specified GPIO data port.

+
Parameters
+ + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
PortValspecifies the value to be written to the port output data register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_WriteBit (GPIO_TypeDef * GPIOx,
uint16_t GPIO_Pin,
BitAction BitVal 
)
+
+ +

Sets or clears the selected data port bit.

+
Parameters
+ + + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_Pinspecifies the port bit to be written. This parameter can be one of GPIO_Pin_x where x can be (0..15).
BitValspecifies the value to be written to the selected bit. This parameter can be one of the BitAction enum values:
    +
  • Bit_RESET: to clear the port pin
    • +
  • Bit_SET: to set the port pin
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___group2.map b/group___g_p_i_o___group2.map new file mode 100644 index 0000000..c13cc18 --- /dev/null +++ b/group___g_p_i_o___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___group2.md5 b/group___g_p_i_o___group2.md5 new file mode 100644 index 0000000..ca3c27a --- /dev/null +++ b/group___g_p_i_o___group2.md5 @@ -0,0 +1 @@ +2196b5b5321edc5c2f7e5f69d7e01cf0 \ No newline at end of file diff --git a/group___g_p_i_o___group2.png b/group___g_p_i_o___group2.png new file mode 100644 index 0000000..87b8dc7 Binary files /dev/null and b/group___g_p_i_o___group2.png differ diff --git a/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map new file mode 100644 index 0000000..fb94820 --- /dev/null +++ b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 new file mode 100644 index 0000000..c1784a7 --- /dev/null +++ b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 @@ -0,0 +1 @@ +4e9b1406822a72492f60945db8c1f760 \ No newline at end of file diff --git a/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png new file mode 100644 index 0000000..5a80237 Binary files /dev/null and b/group___g_p_i_o___group2_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png differ diff --git a/group___g_p_i_o___group3.html b/group___g_p_i_o___group3.html new file mode 100644 index 0000000..f4ed083 --- /dev/null +++ b/group___g_p_i_o___group3.html @@ -0,0 +1,223 @@ + + + + + + +discoverpixy: GPIO Alternate functions configuration function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
GPIO Alternate functions configuration function
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Private_Functions
+
+
+ +

GPIO Alternate functions configuration function. +More...

+
+Collaboration diagram for GPIO Alternate functions configuration function:
+
+
+ + +
+
+ + + + + +

+Functions

void GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 Changes the mapping of the specified pin. More...
 
+

Detailed Description

+

GPIO Alternate functions configuration function.

+
 ===============================================================================
+           ##### GPIO Alternate functions configuration function #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void GPIO_PinAFConfig (GPIO_TypeDef * GPIOx,
uint16_t GPIO_PinSource,
uint8_t GPIO_AF 
)
+
+ +

Changes the mapping of the specified pin.

+
Parameters
+ + + + +
GPIOxwhere x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
GPIO_PinSourcespecifies the pin for the Alternate function. This parameter can be GPIO_PinSourcex where x can be (0..15).
GPIO_AFSelectionselects the pin to used as Alternate function. This parameter can be one of the following values:
    +
  • GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
    • +
  • GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
    • +
  • GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
    • +
  • GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
    • +
  • GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
    • +
  • GPIO_AF_TIM1: Connect TIM1 pins to AF1
    • +
  • GPIO_AF_TIM2: Connect TIM2 pins to AF1
    • +
  • GPIO_AF_TIM3: Connect TIM3 pins to AF2
    • +
  • GPIO_AF_TIM4: Connect TIM4 pins to AF2
    • +
  • GPIO_AF_TIM5: Connect TIM5 pins to AF2
    • +
  • GPIO_AF_TIM8: Connect TIM8 pins to AF3
    • +
  • GPIO_AF_TIM9: Connect TIM9 pins to AF3
    • +
  • GPIO_AF_TIM10: Connect TIM10 pins to AF3
    • +
  • GPIO_AF_TIM11: Connect TIM11 pins to AF3
    • +
  • GPIO_AF_I2C1: Connect I2C1 pins to AF4
    • +
  • GPIO_AF_I2C2: Connect I2C2 pins to AF4
    • +
  • GPIO_AF_I2C3: Connect I2C3 pins to AF4
    • +
  • GPIO_AF_SPI1: Connect SPI1 pins to AF5
    • +
  • GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
    • +
  • GPIO_AF_SPI4: Connect SPI4 pins to AF5
    • +
  • GPIO_AF_SPI5: Connect SPI5 pins to AF5
    • +
  • GPIO_AF_SPI6: Connect SPI6 pins to AF5
    • +
  • GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
    • +
  • GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
    • +
  • GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
    • +
  • GPIO_AF_USART1: Connect USART1 pins to AF7
    • +
  • GPIO_AF_USART2: Connect USART2 pins to AF7
    • +
  • GPIO_AF_USART3: Connect USART3 pins to AF7
    • +
  • GPIO_AF_UART4: Connect UART4 pins to AF8
    • +
  • GPIO_AF_UART5: Connect UART5 pins to AF8
    • +
  • GPIO_AF_USART6: Connect USART6 pins to AF8
    • +
  • GPIO_AF_UART7: Connect UART7 pins to AF8
    • +
  • GPIO_AF_UART8: Connect UART8 pins to AF8
    • +
  • GPIO_AF_CAN1: Connect CAN1 pins to AF9
    • +
  • GPIO_AF_CAN2: Connect CAN2 pins to AF9
    • +
  • GPIO_AF_TIM12: Connect TIM12 pins to AF9
    • +
  • GPIO_AF_TIM13: Connect TIM13 pins to AF9
    • +
  • GPIO_AF_TIM14: Connect TIM14 pins to AF9
    • +
  • GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
    • +
  • GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
    • +
  • GPIO_AF_ETH: Connect ETHERNET pins to AF11
    • +
  • GPIO_AF_FSMC: Connect FSMC pins to AF12
    • +
  • GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
    • +
  • GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
    • +
  • GPIO_AF_SDIO: Connect SDIO pins to AF12
    • +
  • GPIO_AF_DCMI: Connect DCMI pins to AF13
    • +
  • GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
    • +
  • GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___group3.map b/group___g_p_i_o___group3.map new file mode 100644 index 0000000..22c874a --- /dev/null +++ b/group___g_p_i_o___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___group3.md5 b/group___g_p_i_o___group3.md5 new file mode 100644 index 0000000..d97b1d9 --- /dev/null +++ b/group___g_p_i_o___group3.md5 @@ -0,0 +1 @@ +2423939055df160b081317e89f35486c \ No newline at end of file diff --git a/group___g_p_i_o___group3.png b/group___g_p_i_o___group3.png new file mode 100644 index 0000000..f013dad Binary files /dev/null and b/group___g_p_i_o___group3.png differ diff --git a/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.map b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.map new file mode 100644 index 0000000..5bac456 --- /dev/null +++ b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 new file mode 100644 index 0000000..a796c93 --- /dev/null +++ b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 @@ -0,0 +1 @@ +e4977b3793d09d2c9ea1fb6a0ce8a690 \ No newline at end of file diff --git a/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.png b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.png new file mode 100644 index 0000000..19c6ba5 Binary files /dev/null and b/group___g_p_i_o___group3_ga0a77617a322562ae84f8d72486032c5d_icgraph.png differ diff --git a/group___g_p_i_o___legacy.html b/group___g_p_i_o___legacy.html new file mode 100644 index 0000000..c10a67a --- /dev/null +++ b/group___g_p_i_o___legacy.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: GPIO_Legacy + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
GPIO_Legacy
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Exported_Constants
+
+
+
+Collaboration diagram for GPIO_Legacy:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define GPIO_Mode_AIN   GPIO_Mode_AN
 
+#define GPIO_AF_OTG1_FS   GPIO_AF_OTG_FS
 
+#define GPIO_AF_OTG2_HS   GPIO_AF_OTG_HS
 
+#define GPIO_AF_OTG2_FS   GPIO_AF_OTG_HS_FS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___legacy.map b/group___g_p_i_o___legacy.map new file mode 100644 index 0000000..91a5821 --- /dev/null +++ b/group___g_p_i_o___legacy.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___legacy.md5 b/group___g_p_i_o___legacy.md5 new file mode 100644 index 0000000..0337790 --- /dev/null +++ b/group___g_p_i_o___legacy.md5 @@ -0,0 +1 @@ +f9a19f70a056710d67c6b6709edbc3ea \ No newline at end of file diff --git a/group___g_p_i_o___legacy.png b/group___g_p_i_o___legacy.png new file mode 100644 index 0000000..b147e7f Binary files /dev/null and b/group___g_p_i_o___legacy.png differ diff --git a/group___g_p_i_o___pin__sources.html b/group___g_p_i_o___pin__sources.html new file mode 100644 index 0000000..5991815 --- /dev/null +++ b/group___g_p_i_o___pin__sources.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: GPIO_Pin_sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
GPIO_Pin_sources
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Exported_Constants
+
+
+
+Collaboration diagram for GPIO_Pin_sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define GPIO_PinSource0   ((uint8_t)0x00)
 
+#define GPIO_PinSource1   ((uint8_t)0x01)
 
+#define GPIO_PinSource2   ((uint8_t)0x02)
 
+#define GPIO_PinSource3   ((uint8_t)0x03)
 
+#define GPIO_PinSource4   ((uint8_t)0x04)
 
+#define GPIO_PinSource5   ((uint8_t)0x05)
 
+#define GPIO_PinSource6   ((uint8_t)0x06)
 
+#define GPIO_PinSource7   ((uint8_t)0x07)
 
+#define GPIO_PinSource8   ((uint8_t)0x08)
 
+#define GPIO_PinSource9   ((uint8_t)0x09)
 
+#define GPIO_PinSource10   ((uint8_t)0x0A)
 
+#define GPIO_PinSource11   ((uint8_t)0x0B)
 
+#define GPIO_PinSource12   ((uint8_t)0x0C)
 
+#define GPIO_PinSource13   ((uint8_t)0x0D)
 
+#define GPIO_PinSource14   ((uint8_t)0x0E)
 
+#define GPIO_PinSource15   ((uint8_t)0x0F)
 
#define IS_GPIO_PIN_SOURCE(PINSOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_GPIO_PIN_SOURCE( PINSOURCE)
+
+Value:
(((PINSOURCE) == GPIO_PinSource0) || \
+
((PINSOURCE) == GPIO_PinSource1) || \
+
((PINSOURCE) == GPIO_PinSource2) || \
+
((PINSOURCE) == GPIO_PinSource3) || \
+
((PINSOURCE) == GPIO_PinSource4) || \
+
((PINSOURCE) == GPIO_PinSource5) || \
+
((PINSOURCE) == GPIO_PinSource6) || \
+
((PINSOURCE) == GPIO_PinSource7) || \
+
((PINSOURCE) == GPIO_PinSource8) || \
+
((PINSOURCE) == GPIO_PinSource9) || \
+
((PINSOURCE) == GPIO_PinSource10) || \
+
((PINSOURCE) == GPIO_PinSource11) || \
+
((PINSOURCE) == GPIO_PinSource12) || \
+
((PINSOURCE) == GPIO_PinSource13) || \
+
((PINSOURCE) == GPIO_PinSource14) || \
+
((PINSOURCE) == GPIO_PinSource15))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___pin__sources.map b/group___g_p_i_o___pin__sources.map new file mode 100644 index 0000000..b2c8864 --- /dev/null +++ b/group___g_p_i_o___pin__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o___pin__sources.md5 b/group___g_p_i_o___pin__sources.md5 new file mode 100644 index 0000000..ccda2b7 --- /dev/null +++ b/group___g_p_i_o___pin__sources.md5 @@ -0,0 +1 @@ +088a9b83cf44c95df8456989f7ac3a9b \ No newline at end of file diff --git a/group___g_p_i_o___pin__sources.png b/group___g_p_i_o___pin__sources.png new file mode 100644 index 0000000..164721f Binary files /dev/null and b/group___g_p_i_o___pin__sources.png differ diff --git a/group___g_p_i_o___private___functions.html b/group___g_p_i_o___private___functions.html new file mode 100644 index 0000000..6e5307b --- /dev/null +++ b/group___g_p_i_o___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: GPIO_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
GPIO_Private_Functions
STM32F4xx_StdPeriph_Driver » GPIO
+
+
+
+Collaboration diagram for GPIO_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 Initialization and Configuration
 Initialization and Configuration.
 
 GPIO Read and Write
 GPIO Read and Write.
 
 GPIO Alternate functions configuration function
 GPIO Alternate functions configuration function.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o___private___functions.map b/group___g_p_i_o___private___functions.map new file mode 100644 index 0000000..cb36a9a --- /dev/null +++ b/group___g_p_i_o___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___g_p_i_o___private___functions.md5 b/group___g_p_i_o___private___functions.md5 new file mode 100644 index 0000000..64e7d07 --- /dev/null +++ b/group___g_p_i_o___private___functions.md5 @@ -0,0 +1 @@ +5a6c7ba79060816276cf25d3a931ece3 \ No newline at end of file diff --git a/group___g_p_i_o___private___functions.png b/group___g_p_i_o___private___functions.png new file mode 100644 index 0000000..ecb9b08 Binary files /dev/null and b/group___g_p_i_o___private___functions.png differ diff --git a/group___g_p_i_o__pins__define.html b/group___g_p_i_o__pins__define.html new file mode 100644 index 0000000..00832d9 --- /dev/null +++ b/group___g_p_i_o__pins__define.html @@ -0,0 +1,198 @@ + + + + + + +discoverpixy: GPIO_pins_define + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
GPIO_pins_define
STM32F4xx_StdPeriph_Driver » GPIO » GPIO_Exported_Constants
+
+
+
+Collaboration diagram for GPIO_pins_define:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define GPIO_Pin_0   ((uint16_t)0x0001) /* Pin 0 selected */
 
+#define GPIO_Pin_1   ((uint16_t)0x0002) /* Pin 1 selected */
 
+#define GPIO_Pin_2   ((uint16_t)0x0004) /* Pin 2 selected */
 
+#define GPIO_Pin_3   ((uint16_t)0x0008) /* Pin 3 selected */
 
+#define GPIO_Pin_4   ((uint16_t)0x0010) /* Pin 4 selected */
 
+#define GPIO_Pin_5   ((uint16_t)0x0020) /* Pin 5 selected */
 
+#define GPIO_Pin_6   ((uint16_t)0x0040) /* Pin 6 selected */
 
+#define GPIO_Pin_7   ((uint16_t)0x0080) /* Pin 7 selected */
 
+#define GPIO_Pin_8   ((uint16_t)0x0100) /* Pin 8 selected */
 
+#define GPIO_Pin_9   ((uint16_t)0x0200) /* Pin 9 selected */
 
+#define GPIO_Pin_10   ((uint16_t)0x0400) /* Pin 10 selected */
 
+#define GPIO_Pin_11   ((uint16_t)0x0800) /* Pin 11 selected */
 
+#define GPIO_Pin_12   ((uint16_t)0x1000) /* Pin 12 selected */
 
+#define GPIO_Pin_13   ((uint16_t)0x2000) /* Pin 13 selected */
 
+#define GPIO_Pin_14   ((uint16_t)0x4000) /* Pin 14 selected */
 
+#define GPIO_Pin_15   ((uint16_t)0x8000) /* Pin 15 selected */
 
+#define GPIO_Pin_All   ((uint16_t)0xFFFF) /* All pins selected */
 
+#define GPIO_PIN_MASK   ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
 
+#define IS_GPIO_PIN(PIN)   (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
 
#define IS_GET_GPIO_PIN(PIN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_GET_GPIO_PIN( PIN)
+
+Value:
(((PIN) == GPIO_Pin_0) || \
+
((PIN) == GPIO_Pin_1) || \
+
((PIN) == GPIO_Pin_2) || \
+
((PIN) == GPIO_Pin_3) || \
+
((PIN) == GPIO_Pin_4) || \
+
((PIN) == GPIO_Pin_5) || \
+
((PIN) == GPIO_Pin_6) || \
+
((PIN) == GPIO_Pin_7) || \
+
((PIN) == GPIO_Pin_8) || \
+
((PIN) == GPIO_Pin_9) || \
+
((PIN) == GPIO_Pin_10) || \
+
((PIN) == GPIO_Pin_11) || \
+
((PIN) == GPIO_Pin_12) || \
+
((PIN) == GPIO_Pin_13) || \
+
((PIN) == GPIO_Pin_14) || \
+
((PIN) == GPIO_Pin_15))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___g_p_i_o__pins__define.map b/group___g_p_i_o__pins__define.map new file mode 100644 index 0000000..3b352fe --- /dev/null +++ b/group___g_p_i_o__pins__define.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o__pins__define.md5 b/group___g_p_i_o__pins__define.md5 new file mode 100644 index 0000000..09474d0 --- /dev/null +++ b/group___g_p_i_o__pins__define.md5 @@ -0,0 +1 @@ +4fbb95d01de84bd8f327e60401dec40b \ No newline at end of file diff --git a/group___g_p_i_o__pins__define.png b/group___g_p_i_o__pins__define.png new file mode 100644 index 0000000..1a84e25 Binary files /dev/null and b/group___g_p_i_o__pins__define.png differ diff --git a/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.map b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.map new file mode 100644 index 0000000..5bac456 --- /dev/null +++ b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 new file mode 100644 index 0000000..a796c93 --- /dev/null +++ b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.md5 @@ -0,0 +1 @@ +e4977b3793d09d2c9ea1fb6a0ce8a690 \ No newline at end of file diff --git a/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.png b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.png new file mode 100644 index 0000000..19c6ba5 Binary files /dev/null and b/group___g_p_i_o_ga0a77617a322562ae84f8d72486032c5d_icgraph.png differ diff --git a/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.map b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.map new file mode 100644 index 0000000..1d1e3b9 --- /dev/null +++ b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 new file mode 100644 index 0000000..f4d5bff --- /dev/null +++ b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.md5 @@ -0,0 +1 @@ +c1f090d09e5e24d3be81542def084077 \ No newline at end of file diff --git a/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.png b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.png new file mode 100644 index 0000000..f288fa8 Binary files /dev/null and b/group___g_p_i_o_ga71abf9404261370d03cca449b88d3a65_icgraph.png differ diff --git a/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map new file mode 100644 index 0000000..fb94820 --- /dev/null +++ b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 new file mode 100644 index 0000000..c1784a7 --- /dev/null +++ b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.md5 @@ -0,0 +1 @@ +4e9b1406822a72492f60945db8c1f760 \ No newline at end of file diff --git a/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png new file mode 100644 index 0000000..5a80237 Binary files /dev/null and b/group___g_p_i_o_ga98772ef6b639b3fa06c8ae5ba28d3aaa_icgraph.png differ diff --git a/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map new file mode 100644 index 0000000..0f8decb --- /dev/null +++ b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 new file mode 100644 index 0000000..1c0ffec --- /dev/null +++ b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.md5 @@ -0,0 +1 @@ +9df65cbd2ac4a16813033c8465c130af \ No newline at end of file diff --git a/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png new file mode 100644 index 0000000..88b60ca Binary files /dev/null and b/group___g_p_i_o_gaa60bdf3182c44b5fa818f237042f52ee_cgraph.png differ diff --git a/group___h_a_s_h.html b/group___h_a_s_h.html new file mode 100644 index 0000000..61ac606 --- /dev/null +++ b/group___h_a_s_h.html @@ -0,0 +1,1143 @@ + + + + + + +discoverpixy: HASH + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
HASH
STM32F4xx_StdPeriph_Driver
+
+
+ +

HASH driver modules. +More...

+
+Collaboration diagram for HASH:
+
+
+ + +
+
+ + + + + + +

+Modules

 HASH_Exported_Constants
 
 HASH_Private_Functions
 
+ + + + + + + + + + +

+Classes

struct  HASH_InitTypeDef
 HASH Init structure definition. More...
 
struct  HASH_MsgDigest
 HASH message digest result structure definition. More...
 
struct  HASH_Context
 HASH context swapping structure definition. More...
 
+ + + + + +

+Macros

+#define MD5BUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+#define SHA1BUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void HASH_DeInit (void)
 De-initializes the HASH peripheral registers to their default reset values. More...
 
void HASH_Init (HASH_InitTypeDef *HASH_InitStruct)
 Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure. More...
 
void HASH_StructInit (HASH_InitTypeDef *HASH_InitStruct)
 Fills each HASH_InitStruct member with its default value. More...
 
void HASH_Reset (void)
 Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message. More...
 
void HASH_DataIn (uint32_t Data)
 Writes data in the Data Input FIFO. More...
 
uint8_t HASH_GetInFIFOWordsNbr (void)
 Returns the number of words already pushed into the IN FIFO. More...
 
void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
 Configure the Number of valid bits in last word of the message. More...
 
void HASH_StartDigest (void)
 Starts the message padding and calculation of the final message. More...
 
void HASH_AutoStartDigest (FunctionalState NewState)
 Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer. More...
 
void HASH_GetDigest (HASH_MsgDigest *HASH_MessageDigest)
 Provides the message digest result. More...
 
void HASH_SaveContext (HASH_Context *HASH_ContextSave)
 Save the Hash peripheral Context. More...
 
void HASH_RestoreContext (HASH_Context *HASH_ContextRestore)
 Restore the Hash peripheral Context. More...
 
void HASH_DMACmd (FunctionalState NewState)
 Enables or disables the HASH DMA interface. More...
 
void HASH_ITConfig (uint32_t HASH_IT, FunctionalState NewState)
 Enables or disables the specified HASH interrupts. More...
 
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
 Checks whether the specified HASH flag is set or not. More...
 
void HASH_ClearFlag (uint32_t HASH_FLAG)
 Clears the HASH flags. More...
 
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
 Checks whether the specified HASH interrupt has occurred or not. More...
 
void HASH_ClearITPendingBit (uint32_t HASH_IT)
 Clears the HASH interrupt pending bit(s). More...
 
ErrorStatus HASH_SHA1 (uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HASH SHA1 digest. More...
 
ErrorStatus HMAC_SHA1 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HMAC SHA1 digest. More...
 
ErrorStatus HASH_MD5 (uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HASH MD5 digest. More...
 
ErrorStatus HMAC_MD5 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HMAC MD5 digest. More...
 
+

Detailed Description

+

HASH driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_AutoStartDigest (FunctionalState NewState)
+
+ +

Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer.

+
Parameters
+ + +
NewStatenew state of the selected HASH DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_ClearFlag (uint32_t HASH_FLAG)
+
+ +

Clears the HASH flags.

+
Parameters
+ + +
HASH_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • HASH_FLAG_DINIS: Data Input Flag
    • +
  • HASH_FLAG_DCIS: Digest Calculation Completion Flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_ClearITPendingBit (uint32_t HASH_IT)
+
+ +

Clears the HASH interrupt pending bit(s).

+
Parameters
+ + +
HASH_ITspecifies the HASH interrupt pending bit(s) to clear. This parameter can be any combination of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_DataIn (uint32_t Data)
+
+ +

Writes data in the Data Input FIFO.

+
Parameters
+ + +
Datanew data of the message to be processed.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void HASH_DeInit (void )
+
+ +

De-initializes the HASH peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void HASH_DMACmd (FunctionalState NewState)
+
+ +

Enables or disables the HASH DMA interface.

+
Note
The DMA is disabled by hardware after the end of transfer.
+
Parameters
+ + +
NewStatenew state of the selected HASH DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_GetDigest (HASH_MsgDigest * HASH_MessageDigest)
+
+ +

Provides the message digest result.

+
Note
In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used and is read as zero. In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used and is read as zero. In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used and is read as zero.
+
Parameters
+ + +
HASH_MessageDigestpointer to a HASH_MsgDigest structure which will hold the message digest result
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
+
+ +

Checks whether the specified HASH flag is set or not.

+
Parameters
+ + +
HASH_FLAGspecifies the HASH flag to check. This parameter can be one of the following values:
    +
  • HASH_FLAG_DINIS: Data input interrupt status flag
    • +
  • HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
    • +
  • HASH_FLAG_BUSY: Busy flag
    • +
  • HASH_FLAG_DMAS: DMAS Status flag
    • +
  • HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of HASH_FLAG (SET or RESET)
+
+
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uint8_t HASH_GetInFIFOWordsNbr (void )
+
+ +

Returns the number of words already pushed into the IN FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thevalue of words already pushed into the IN FIFO.
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
+
+ +

Checks whether the specified HASH interrupt has occurred or not.

+
Parameters
+ + +
HASH_ITspecifies the HASH interrupt source to check. This parameter can be one of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of HASH_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_Init (HASH_InitTypeDef * HASH_InitStruct)
+
+ +

Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure.

+
Note
the hash processor is reset when calling this function so that the HASH will be ready to compute the message digest of a new message. There is no need to call HASH_Reset() function.
+
Parameters
+ + +
HASH_InitStructpointer to a HASH_InitTypeDef structure that contains the configuration information for the HASH peripheral.
+
+
+
Note
The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only if the algorithm mode is HMAC.
+
Return values
+ + +
None
+
+
+ +

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void HASH_ITConfig (uint32_t HASH_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified HASH interrupts.

+
Parameters
+ + + +
HASH_ITspecifies the HASH interrupt source to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
NewStatenew state of the specified HASH interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus HASH_MD5 (uint8_t * Input,
uint32_t Ilen,
uint8_t Output[16] 
)
+
+ +

Compute the HASH MD5 digest.

+
Parameters
+ + + + +
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
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void HASH_Reset (void )
+
+ +

Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message.

+
Note
Calling this function will clear the HASH_SR_DCIS (Digest calculation completion interrupt status) bit corresponding to HASH_IT_DCI interrupt and HASH_FLAG_DCIS flag.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_RestoreContext (HASH_Context * HASH_ContextRestore)
+
+ +

Restore the Hash peripheral Context.

+
Note
After calling this function, user can restart the processing from the point where it has been interrupted.
+
Parameters
+ + +
HASH_ContextRestorepointer to a HASH_Context structure that contains the repository for saved context.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_SaveContext (HASH_Context * HASH_ContextSave)
+
+ +

Save the Hash peripheral Context.

+
Note
The context can be saved only when no block is currently being processed. So user must wait for DINIS = 1 (the last block has been processed and the input FIFO is empty) or NBW != 0 (the FIFO is not full and no processing is ongoing).
+
Parameters
+ + +
HASH_ContextSavepointer to a HASH_Context structure that contains the repository for current context.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
+
+ +

Configure the Number of valid bits in last word of the message.

+
Parameters
+ + +
ValidNumberNumber of valid bits in last word of the message. This parameter must be a number between 0 and 0x1F.
    +
  • 0x00: All 32 bits of the last data written are valid
    • +
  • 0x01: Only bit [0] of the last data written is valid
    • +
  • 0x02: Only bits[1:0] of the last data written are valid
    • +
  • 0x03: Only bits[2:0] of the last data written are valid
    • +
  • ...
    • +
  • 0x1F: Only bits[30:0] of the last data written are valid
    • +
+
+
+
+
Note
The Number of valid bits must be set before to start the message digest competition (in Hash and HMAC) and key treatment(in HMAC).
+
Return values
+ + +
None
+
+
+ +

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ErrorStatus HASH_SHA1 (uint8_t * Input,
uint32_t Ilen,
uint8_t Output[20] 
)
+
+ +

Compute the HASH SHA1 digest.

+
Parameters
+ + + + +
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
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+ + + + + + + + +
void HASH_StartDigest (void )
+
+ +

Starts the message padding and calculation of the final message.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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+ +
+
+ +
+
+ + + + + + + + +
void HASH_StructInit (HASH_InitTypeDef * HASH_InitStruct)
+
+ +

Fills each HASH_InitStruct member with its default value.

+
Parameters
+ + +
HASH_InitStruct: pointer to a HASH_InitTypeDef structure which will be initialized.
+
+
+
Note
The default values set are : Processor mode is HASH, Algorithm selected is SHA1, Data type selected is 32b and HMAC Key Type is short key.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus HMAC_MD5 (uint8_t * Key,
uint32_t Keylen,
uint8_t * Input,
uint32_t Ilen,
uint8_t Output[16] 
)
+
+ +

Compute the HMAC MD5 digest.

+
Parameters
+ + + + + + +
Keypointer to the Key used for HMAC.
Keylenlength of the Key used for HMAC.
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
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ErrorStatus HMAC_SHA1 (uint8_t * Key,
uint32_t Keylen,
uint8_t * Input,
uint32_t Ilen,
uint8_t Output[20] 
)
+
+ +

Compute the HMAC SHA1 digest.

+
Parameters
+ + + + + + +
Keypointer to the Key used for HMAC.
Keylenlength of the Key used for HMAC.
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
+ +

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+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h.map b/group___h_a_s_h.map new file mode 100644 index 0000000..e202008 --- /dev/null +++ b/group___h_a_s_h.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___h_a_s_h.md5 b/group___h_a_s_h.md5 new file mode 100644 index 0000000..b63a30b --- /dev/null +++ b/group___h_a_s_h.md5 @@ -0,0 +1 @@ +12c5179131bd194e28fc2454791ba40b \ No newline at end of file diff --git a/group___h_a_s_h.png b/group___h_a_s_h.png new file mode 100644 index 0000000..badcb92 Binary files /dev/null and b/group___h_a_s_h.png differ diff --git a/group___h_a_s_h___algo___selection.html b/group___h_a_s_h___algo___selection.html new file mode 100644 index 0000000..ad66811 --- /dev/null +++ b/group___h_a_s_h___algo___selection.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: HASH_Algo_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
HASH_Algo_Selection
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_Algo_Selection:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define HASH_AlgoSelection_SHA1   ((uint32_t)0x0000)
 
#define HASH_AlgoSelection_SHA224   HASH_CR_ALGO_1
 
#define HASH_AlgoSelection_SHA256   HASH_CR_ALGO
 
#define HASH_AlgoSelection_MD5   HASH_CR_ALGO_0
 
#define IS_HASH_ALGOSELECTION(ALGOSELECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_AlgoSelection_MD5   HASH_CR_ALGO_0
+
+

HASH function is MD5

+ +
+
+ +
+
+ + + + +
#define HASH_AlgoSelection_SHA1   ((uint32_t)0x0000)
+
+

HASH function is SHA1

+ +
+
+ +
+
+ + + + +
#define HASH_AlgoSelection_SHA224   HASH_CR_ALGO_1
+
+

HASH function is SHA224

+ +
+
+ +
+
+ + + + +
#define HASH_AlgoSelection_SHA256   HASH_CR_ALGO
+
+

HASH function is SHA256

+ +
+
+ +
+
+ + + + + + + + +
#define IS_HASH_ALGOSELECTION( ALGOSELECTION)
+
+Value:
(((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+
((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+
((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+
((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+
HASH_AlgoSelection_SHA256
#define HASH_AlgoSelection_SHA256
Definition: stm32f4xx_hash.h:99
+
HASH_AlgoSelection_MD5
#define HASH_AlgoSelection_MD5
Definition: stm32f4xx_hash.h:100
+
HASH_AlgoSelection_SHA224
#define HASH_AlgoSelection_SHA224
Definition: stm32f4xx_hash.h:98
+
HASH_AlgoSelection_SHA1
#define HASH_AlgoSelection_SHA1
Definition: stm32f4xx_hash.h:97
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___algo___selection.map b/group___h_a_s_h___algo___selection.map new file mode 100644 index 0000000..12027a3 --- /dev/null +++ b/group___h_a_s_h___algo___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___algo___selection.md5 b/group___h_a_s_h___algo___selection.md5 new file mode 100644 index 0000000..93f7efd --- /dev/null +++ b/group___h_a_s_h___algo___selection.md5 @@ -0,0 +1 @@ +f357790b1a877dac53eb9959f1f38784 \ No newline at end of file diff --git a/group___h_a_s_h___algo___selection.png b/group___h_a_s_h___algo___selection.png new file mode 100644 index 0000000..1898763 Binary files /dev/null and b/group___h_a_s_h___algo___selection.png differ diff --git a/group___h_a_s_h___data___type.html b/group___h_a_s_h___data___type.html new file mode 100644 index 0000000..967ef26 --- /dev/null +++ b/group___h_a_s_h___data___type.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: HASH_Data_Type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
HASH_Data_Type
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_Data_Type:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define HASH_DataType_32b   ((uint32_t)0x0000)
 
#define HASH_DataType_16b   HASH_CR_DATATYPE_0
 
#define HASH_DataType_8b   HASH_CR_DATATYPE_1
 
#define HASH_DataType_1b   HASH_CR_DATATYPE
 
#define IS_HASH_DATATYPE(DATATYPE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_DataType_16b   HASH_CR_DATATYPE_0
+
+

16-bit data. Each half word is swapped

+ +
+
+ +
+
+ + + + +
#define HASH_DataType_1b   HASH_CR_DATATYPE
+
+

1-bit data. In the word all bits are swapped

+ +
+
+ +
+
+ + + + +
#define HASH_DataType_32b   ((uint32_t)0x0000)
+
+

32-bit data. No swapping

+ +
+
+ +
+
+ + + + +
#define HASH_DataType_8b   HASH_CR_DATATYPE_1
+
+

8-bit data. All bytes are swapped

+ +
+
+ +
+
+ + + + + + + + +
#define IS_HASH_DATATYPE( DATATYPE)
+
+Value:
(((DATATYPE) == HASH_DataType_32b)|| \
+
((DATATYPE) == HASH_DataType_16b)|| \
+
((DATATYPE) == HASH_DataType_8b) || \
+
((DATATYPE) == HASH_DataType_1b))
+
HASH_DataType_16b
#define HASH_DataType_16b
Definition: stm32f4xx_hash.h:126
+
HASH_DataType_1b
#define HASH_DataType_1b
Definition: stm32f4xx_hash.h:128
+
HASH_DataType_32b
#define HASH_DataType_32b
Definition: stm32f4xx_hash.h:125
+
HASH_DataType_8b
#define HASH_DataType_8b
Definition: stm32f4xx_hash.h:127
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___data___type.map b/group___h_a_s_h___data___type.map new file mode 100644 index 0000000..e654e69 --- /dev/null +++ b/group___h_a_s_h___data___type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___data___type.md5 b/group___h_a_s_h___data___type.md5 new file mode 100644 index 0000000..6220127 --- /dev/null +++ b/group___h_a_s_h___data___type.md5 @@ -0,0 +1 @@ +039c5f3254c070296f15622e6b7823cd \ No newline at end of file diff --git a/group___h_a_s_h___data___type.png b/group___h_a_s_h___data___type.png new file mode 100644 index 0000000..752f3fe Binary files /dev/null and b/group___h_a_s_h___data___type.png differ diff --git a/group___h_a_s_h___exported___constants.html b/group___h_a_s_h___exported___constants.html new file mode 100644 index 0000000..14b0c58 --- /dev/null +++ b/group___h_a_s_h___exported___constants.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: HASH_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
HASH_Exported_Constants
STM32F4xx_StdPeriph_Driver » HASH
+
+
+
+Collaboration diagram for HASH_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Modules

 HASH_Algo_Selection
 
 HASH_processor_Algorithm_Mode
 
 HASH_Data_Type
 
 HASH_HMAC_Long_key_only_for_HMAC_mode
 
 Number_of_valid_bits_in_last_word_of_the_message
 
 HASH_interrupts_definition
 
 HASH_flags_definition
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___exported___constants.map b/group___h_a_s_h___exported___constants.map new file mode 100644 index 0000000..ac6682c --- /dev/null +++ b/group___h_a_s_h___exported___constants.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___exported___constants.md5 b/group___h_a_s_h___exported___constants.md5 new file mode 100644 index 0000000..c46fe2d --- /dev/null +++ b/group___h_a_s_h___exported___constants.md5 @@ -0,0 +1 @@ +ad749c2340fc9dce47b1a6524f90bd11 \ No newline at end of file diff --git a/group___h_a_s_h___exported___constants.png b/group___h_a_s_h___exported___constants.png new file mode 100644 index 0000000..4fb6b92 Binary files /dev/null and b/group___h_a_s_h___exported___constants.png differ diff --git a/group___h_a_s_h___group1.html b/group___h_a_s_h___group1.html new file mode 100644 index 0000000..e23c5e3 --- /dev/null +++ b/group___h_a_s_h___group1.html @@ -0,0 +1,284 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void HASH_DeInit (void)
 De-initializes the HASH peripheral registers to their default reset values. More...
 
void HASH_Init (HASH_InitTypeDef *HASH_InitStruct)
 Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure. More...
 
void HASH_StructInit (HASH_InitTypeDef *HASH_InitStruct)
 Fills each HASH_InitStruct member with its default value. More...
 
void HASH_Reset (void)
 Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the HASH peripheral
+   (+) Configure the HASH Processor 
+   (+) MD5/SHA1, 
+   (+) HASH/HMAC, 
+   (+) datatype 
+   (+) HMAC Key (if mode = HMAC)
+   (+) Reset the HASH Processor

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_DeInit (void )
+
+ +

De-initializes the HASH peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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+ +
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+ +
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+ + + + + + + + +
void HASH_Init (HASH_InitTypeDef * HASH_InitStruct)
+
+ +

Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure.

+
Note
the hash processor is reset when calling this function so that the HASH will be ready to compute the message digest of a new message. There is no need to call HASH_Reset() function.
+
Parameters
+ + +
HASH_InitStructpointer to a HASH_InitTypeDef structure that contains the configuration information for the HASH peripheral.
+
+
+
Note
The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only if the algorithm mode is HMAC.
+
Return values
+ + +
None
+
+
+ +

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+ +
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+
+ + + + + + + + +
void HASH_Reset (void )
+
+ +

Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message.

+
Note
Calling this function will clear the HASH_SR_DCIS (Digest calculation completion interrupt status) bit corresponding to HASH_IT_DCI interrupt and HASH_FLAG_DCIS flag.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_StructInit (HASH_InitTypeDef * HASH_InitStruct)
+
+ +

Fills each HASH_InitStruct member with its default value.

+
Parameters
+ + +
HASH_InitStruct: pointer to a HASH_InitTypeDef structure which will be initialized.
+
+
+
Note
The default values set are : Processor mode is HASH, Algorithm selected is SHA1, Data type selected is 32b and HMAC Key Type is short key.
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group1.map b/group___h_a_s_h___group1.map new file mode 100644 index 0000000..ce1e77b --- /dev/null +++ b/group___h_a_s_h___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group1.md5 b/group___h_a_s_h___group1.md5 new file mode 100644 index 0000000..dde0bc9 --- /dev/null +++ b/group___h_a_s_h___group1.md5 @@ -0,0 +1 @@ +98083f8dad32938a3795df71f2865838 \ No newline at end of file diff --git a/group___h_a_s_h___group1.png b/group___h_a_s_h___group1.png new file mode 100644 index 0000000..2a327bf Binary files /dev/null and b/group___h_a_s_h___group1.png differ diff --git a/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.map b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.map new file mode 100644 index 0000000..afa57db --- /dev/null +++ b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.md5 b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.md5 new file mode 100644 index 0000000..44610f7 --- /dev/null +++ b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.md5 @@ -0,0 +1 @@ +1f095ce2315219dc00fa47e4489c8deb \ No newline at end of file diff --git a/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.png b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.png new file mode 100644 index 0000000..f7e133c Binary files /dev/null and b/group___h_a_s_h___group1_ga4a7d33f0954ac0463a6cda81121635cf_icgraph.png differ diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.map b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.map new file mode 100644 index 0000000..c211e76 --- /dev/null +++ b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.md5 b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.md5 new file mode 100644 index 0000000..ebd6b01 --- /dev/null +++ b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.md5 @@ -0,0 +1 @@ +56064f693ecb97052192ba1f75404d34 \ No newline at end of file diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.png b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.png new file mode 100644 index 0000000..5269b32 Binary files /dev/null and b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_cgraph.png differ diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.map b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.map new file mode 100644 index 0000000..8d77270 --- /dev/null +++ b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.md5 b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.md5 new file mode 100644 index 0000000..5b19e7b --- /dev/null +++ b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.md5 @@ -0,0 +1 @@ +bad814d8fff7534137bad2bc24ef4dc1 \ No newline at end of file diff --git a/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.png b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.png new file mode 100644 index 0000000..814f447 Binary files /dev/null and b/group___h_a_s_h___group1_ga88717fe3a4f557182841a958e1dcd9c7_icgraph.png differ diff --git a/group___h_a_s_h___group2.html b/group___h_a_s_h___group2.html new file mode 100644 index 0000000..a848e08 --- /dev/null +++ b/group___h_a_s_h___group2.html @@ -0,0 +1,330 @@ + + + + + + +discoverpixy: Message Digest generation functions + + + + + + + + + + +
+
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+
discoverpixy +
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+Functions
+
+
Message Digest generation functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

Message Digest generation functions. +More...

+
+Collaboration diagram for Message Digest generation functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
 Configure the Number of valid bits in last word of the message. More...
 
void HASH_DataIn (uint32_t Data)
 Writes data in the Data Input FIFO. More...
 
uint8_t HASH_GetInFIFOWordsNbr (void)
 Returns the number of words already pushed into the IN FIFO. More...
 
void HASH_GetDigest (HASH_MsgDigest *HASH_MessageDigest)
 Provides the message digest result. More...
 
void HASH_StartDigest (void)
 Starts the message padding and calculation of the final message. More...
 
+

Detailed Description

+

Message Digest generation functions.

+
 ===============================================================================
+                  ##### Message Digest generation functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing the generation of message digest: 
+   (+) Push data in the IN FIFO : using HASH_DataIn()
+   (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()  
+   (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() 
+   (+) start digest calculation : using HASH_StartDigest()
+   (+) Get the Digest message : using HASH_GetDigest()

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_DataIn (uint32_t Data)
+
+ +

Writes data in the Data Input FIFO.

+
Parameters
+ + +
Datanew data of the message to be processed.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void HASH_GetDigest (HASH_MsgDigest * HASH_MessageDigest)
+
+ +

Provides the message digest result.

+
Note
In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used and is read as zero. In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used and is read as zero. In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used and is read as zero.
+
Parameters
+ + +
HASH_MessageDigestpointer to a HASH_MsgDigest structure which will hold the message digest result
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint8_t HASH_GetInFIFOWordsNbr (void )
+
+ +

Returns the number of words already pushed into the IN FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thevalue of words already pushed into the IN FIFO.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
+
+ +

Configure the Number of valid bits in last word of the message.

+
Parameters
+ + +
ValidNumberNumber of valid bits in last word of the message. This parameter must be a number between 0 and 0x1F.
    +
  • 0x00: All 32 bits of the last data written are valid
    • +
  • 0x01: Only bit [0] of the last data written is valid
    • +
  • 0x02: Only bits[1:0] of the last data written are valid
    • +
  • 0x03: Only bits[2:0] of the last data written are valid
    • +
  • ...
    • +
  • 0x1F: Only bits[30:0] of the last data written are valid
    • +
+
+
+
+
Note
The Number of valid bits must be set before to start the message digest competition (in Hash and HMAC) and key treatment(in HMAC).
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void HASH_StartDigest (void )
+
+ +

Starts the message padding and calculation of the final message.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group2.map b/group___h_a_s_h___group2.map new file mode 100644 index 0000000..c756083 --- /dev/null +++ b/group___h_a_s_h___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group2.md5 b/group___h_a_s_h___group2.md5 new file mode 100644 index 0000000..1846f7e --- /dev/null +++ b/group___h_a_s_h___group2.md5 @@ -0,0 +1 @@ +2aa3609aee8b70dfb8f58707172826b2 \ No newline at end of file diff --git a/group___h_a_s_h___group2.png b/group___h_a_s_h___group2.png new file mode 100644 index 0000000..9a2a10e Binary files /dev/null and b/group___h_a_s_h___group2.png differ diff --git a/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.map b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.map new file mode 100644 index 0000000..f26d42d --- /dev/null +++ b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.md5 b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.md5 new file mode 100644 index 0000000..990fc56 --- /dev/null +++ b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.md5 @@ -0,0 +1 @@ +ce2b8a2921252c22c06b1f67ba743d03 \ No newline at end of file diff --git a/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.png b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.png new file mode 100644 index 0000000..ae50e00 Binary files /dev/null and b/group___h_a_s_h___group2_ga23018d770837d6ab9f46941f105cc017_icgraph.png differ diff --git a/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.map b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.map new file mode 100644 index 0000000..c07c0a0 --- /dev/null +++ b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.md5 b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.md5 new file mode 100644 index 0000000..f2a6428 --- /dev/null +++ b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.md5 @@ -0,0 +1 @@ +e8b16153d04fd1ea681e88ed67276251 \ No newline at end of file diff --git a/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.png b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.png new file mode 100644 index 0000000..7630298 Binary files /dev/null and b/group___h_a_s_h___group2_ga84ac2b64179fd37b75c4d5f665126e93_icgraph.png differ diff --git a/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.map b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.map new file mode 100644 index 0000000..1dc6f3d --- /dev/null +++ b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.md5 b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.md5 new file mode 100644 index 0000000..6d9f7a1 --- /dev/null +++ b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.md5 @@ -0,0 +1 @@ +d0c62f33abcfb31a9e5748d5318e52ee \ No newline at end of file diff --git a/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.png b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.png new file mode 100644 index 0000000..2ea10e8 Binary files /dev/null and b/group___h_a_s_h___group2_ga9c4c0cebdeb1ce2631dd2eeab82107ef_icgraph.png differ diff --git a/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.map b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.map new file mode 100644 index 0000000..64b08c1 --- /dev/null +++ b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.md5 b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.md5 new file mode 100644 index 0000000..776a2b5 --- /dev/null +++ b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.md5 @@ -0,0 +1 @@ +6b4aaf7499a122beabf3f9413648e245 \ No newline at end of file diff --git a/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.png b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.png new file mode 100644 index 0000000..4880b5f Binary files /dev/null and b/group___h_a_s_h___group2_gac4d1fa51c9240ad0287b371564b5d2a6_icgraph.png differ diff --git a/group___h_a_s_h___group3.html b/group___h_a_s_h___group3.html new file mode 100644 index 0000000..6414df4 --- /dev/null +++ b/group___h_a_s_h___group3.html @@ -0,0 +1,192 @@ + + + + + + +discoverpixy: Context swapping functions + + + + + + + + + + +
+
+ + + + + + +
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+Functions
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Context swapping functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

Context swapping functions. +More...

+
+Collaboration diagram for Context swapping functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void HASH_SaveContext (HASH_Context *HASH_ContextSave)
 Save the Hash peripheral Context. More...
 
void HASH_RestoreContext (HASH_Context *HASH_ContextRestore)
 Restore the Hash peripheral Context. More...
 
+

Detailed Description

+

Context swapping functions.

+
 ===============================================================================
+                      ##### Context swapping functions #####
+ ===============================================================================  
+ 
+ [..] This section provides functions allowing to save and store HASH Context
+  
+ [..] It is possible to interrupt a HASH/HMAC process to perform another processing 
+      with a higher priority, and to complete the interrupted process later on, when 
+      the higher priority task is complete. To do so, the context of the interrupted 
+      task must be saved from the HASH registers to memory, and then be restored 
+      from memory to the HASH registers.
+  
+   (#) To save the current context, use HASH_SaveContext() function
+   (#) To restore the saved context, use HASH_RestoreContext() function

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_RestoreContext (HASH_Context * HASH_ContextRestore)
+
+ +

Restore the Hash peripheral Context.

+
Note
After calling this function, user can restart the processing from the point where it has been interrupted.
+
Parameters
+ + +
HASH_ContextRestorepointer to a HASH_Context structure that contains the repository for saved context.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_SaveContext (HASH_Context * HASH_ContextSave)
+
+ +

Save the Hash peripheral Context.

+
Note
The context can be saved only when no block is currently being processed. So user must wait for DINIS = 1 (the last block has been processed and the input FIFO is empty) or NBW != 0 (the FIFO is not full and no processing is ongoing).
+
Parameters
+ + +
HASH_ContextSavepointer to a HASH_Context structure that contains the repository for current context.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group3.map b/group___h_a_s_h___group3.map new file mode 100644 index 0000000..579fcce --- /dev/null +++ b/group___h_a_s_h___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group3.md5 b/group___h_a_s_h___group3.md5 new file mode 100644 index 0000000..c539ed0 --- /dev/null +++ b/group___h_a_s_h___group3.md5 @@ -0,0 +1 @@ +0b79941f8ecb6b7847f673e72cd08332 \ No newline at end of file diff --git a/group___h_a_s_h___group3.png b/group___h_a_s_h___group3.png new file mode 100644 index 0000000..fa10e12 Binary files /dev/null and b/group___h_a_s_h___group3.png differ diff --git a/group___h_a_s_h___group4.html b/group___h_a_s_h___group4.html new file mode 100644 index 0000000..dc88557 --- /dev/null +++ b/group___h_a_s_h___group4.html @@ -0,0 +1,186 @@ + + + + + + +discoverpixy: HASH's DMA interface Configuration function + + + + + + + + + + +
+
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+
discoverpixy +
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HASH's DMA interface Configuration function
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

HASH's DMA interface Configuration function. +More...

+
+Collaboration diagram for HASH's DMA interface Configuration function:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void HASH_AutoStartDigest (FunctionalState NewState)
 Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer. More...
 
void HASH_DMACmd (FunctionalState NewState)
 Enables or disables the HASH DMA interface. More...
 
+

Detailed Description

+

HASH's DMA interface Configuration function.

+
 ===============================================================================
+               ##### HASH's DMA interface Configuration function #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the DMA interface for 
+      HASH/ HMAC data input transfer.
+   
+ [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be 
+      sent to the IN FIFO using the DMA peripheral.

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_AutoStartDigest (FunctionalState NewState)
+
+ +

Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer.

+
Parameters
+ + +
NewStatenew state of the selected HASH DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_DMACmd (FunctionalState NewState)
+
+ +

Enables or disables the HASH DMA interface.

+
Note
The DMA is disabled by hardware after the end of transfer.
+
Parameters
+ + +
NewStatenew state of the selected HASH DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group4.map b/group___h_a_s_h___group4.map new file mode 100644 index 0000000..1d15a8e --- /dev/null +++ b/group___h_a_s_h___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group4.md5 b/group___h_a_s_h___group4.md5 new file mode 100644 index 0000000..74d56b3 --- /dev/null +++ b/group___h_a_s_h___group4.md5 @@ -0,0 +1 @@ +1096bd90e38e63b89566e80a0083060c \ No newline at end of file diff --git a/group___h_a_s_h___group4.png b/group___h_a_s_h___group4.png new file mode 100644 index 0000000..d29d0be Binary files /dev/null and b/group___h_a_s_h___group4.png differ diff --git a/group___h_a_s_h___group5.html b/group___h_a_s_h___group5.html new file mode 100644 index 0000000..a9cd54e --- /dev/null +++ b/group___h_a_s_h___group5.html @@ -0,0 +1,371 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
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+Functions
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+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void HASH_ITConfig (uint32_t HASH_IT, FunctionalState NewState)
 Enables or disables the specified HASH interrupts. More...
 
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
 Checks whether the specified HASH flag is set or not. More...
 
void HASH_ClearFlag (uint32_t HASH_FLAG)
 Clears the HASH flags. More...
 
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
 Checks whether the specified HASH interrupt has occurred or not. More...
 
void HASH_ClearITPendingBit (uint32_t HASH_IT)
 Clears the HASH interrupt pending bit(s). More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+               ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the HASH Interrupts and 
+      to get the status and clear flags and Interrupts pending bits.
+  
+ [..] The HASH provides 2 Interrupts sources and 5 Flags:
+  
+ *** Flags : ***
+ =============== 
+ [..]
+   (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO 
+      which means that a  new block (512 bit) can be entered into the input buffer.
+                          
+   (#) HASH_FLAG_DCIS :  set when Digest calculation is complete
+      
+   (#) HASH_FLAG_DMAS :  set when HASH's DMA interface is enabled (DMAE=1) or 
+       a transfer is ongoing. This Flag is cleared only by hardware.
+                           
+   (#) HASH_FLAG_BUSY :  set when The hash core is processing a block of data
+       This Flag is cleared only by hardware. 
+                           
+   (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that 
+       the Data IN FIFO contains at least one word of data. This Flag is cleared 
+       only by hardware.
+     
+ *** Interrupts : ***
+ ====================
+ [..]   
+   (#) HASH_IT_DINI  : if enabled, this interrupt source is pending when 16 
+       locations are free in the Data IN FIFO  which means that a new block (512 bit)
+       can be entered into the input buffer. This interrupt source is cleared using 
+       HASH_ClearITPendingBit(HASH_IT_DINI) function.
+   
+   (#) HASH_IT_DCI   : if enabled, this interrupt source is pending when Digest 
+       calculation is complete. This interrupt source is cleared using 
+       HASH_ClearITPendingBit(HASH_IT_DCI) function.
+
+ *** Managing the HASH controller events : ***
+ =============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the HASH controller events: Polling mode or Interrupt mode.
+  
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) HASH_GetFlagStatus() : to check if flags events occur. 
+       (++) HASH_ClearFlag()     : to clear the flags events.
+    
+   (#)  In the Interrupt Mode it is advised to use the following functions:
+       (++) HASH_ITConfig()       : to enable or disable the interrupt source.
+       (++) HASH_GetITStatus()    : to check if Interrupt occurs.
+       (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit 
+            (corresponding Flag).

Function Documentation

+ +
+
+ + + + + + + + +
void HASH_ClearFlag (uint32_t HASH_FLAG)
+
+ +

Clears the HASH flags.

+
Parameters
+ + +
HASH_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • HASH_FLAG_DINIS: Data Input Flag
    • +
  • HASH_FLAG_DCIS: Digest Calculation Completion Flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void HASH_ClearITPendingBit (uint32_t HASH_IT)
+
+ +

Clears the HASH interrupt pending bit(s).

+
Parameters
+ + +
HASH_ITspecifies the HASH interrupt pending bit(s) to clear. This parameter can be any combination of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
+
+ +

Checks whether the specified HASH flag is set or not.

+
Parameters
+ + +
HASH_FLAGspecifies the HASH flag to check. This parameter can be one of the following values:
    +
  • HASH_FLAG_DINIS: Data input interrupt status flag
    • +
  • HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
    • +
  • HASH_FLAG_BUSY: Busy flag
    • +
  • HASH_FLAG_DMAS: DMAS Status flag
    • +
  • HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of HASH_FLAG (SET or RESET)
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
+
+ +

Checks whether the specified HASH interrupt has occurred or not.

+
Parameters
+ + +
HASH_ITspecifies the HASH interrupt source to check. This parameter can be one of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of HASH_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void HASH_ITConfig (uint32_t HASH_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified HASH interrupts.

+
Parameters
+ + + +
HASH_ITspecifies the HASH interrupt source to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • HASH_IT_DINI: Data Input interrupt
    • +
  • HASH_IT_DCI: Digest Calculation Completion Interrupt
    • +
+
NewStatenew state of the specified HASH interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group5.map b/group___h_a_s_h___group5.map new file mode 100644 index 0000000..5e006c9 --- /dev/null +++ b/group___h_a_s_h___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group5.md5 b/group___h_a_s_h___group5.md5 new file mode 100644 index 0000000..5705891 --- /dev/null +++ b/group___h_a_s_h___group5.md5 @@ -0,0 +1 @@ +6221cadf149dd53094a8e962fa775dbe \ No newline at end of file diff --git a/group___h_a_s_h___group5.png b/group___h_a_s_h___group5.png new file mode 100644 index 0000000..6535883 Binary files /dev/null and b/group___h_a_s_h___group5.png differ diff --git a/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.map b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.map new file mode 100644 index 0000000..739bd9c --- /dev/null +++ b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.md5 b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.md5 new file mode 100644 index 0000000..0c0a4d0 --- /dev/null +++ b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.md5 @@ -0,0 +1 @@ +7af5b3c90692d1fc7b5bafada8295931 \ No newline at end of file diff --git a/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.png b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.png new file mode 100644 index 0000000..6002803 Binary files /dev/null and b/group___h_a_s_h___group5_ga826f7bbe15d07c123446cc3d30959f72_icgraph.png differ diff --git a/group___h_a_s_h___group6.html b/group___h_a_s_h___group6.html new file mode 100644 index 0000000..014301e --- /dev/null +++ b/group___h_a_s_h___group6.html @@ -0,0 +1,255 @@ + + + + + + +discoverpixy: High Level SHA1 functions + + + + + + + + + + +
+
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discoverpixy +
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+Functions
+
+
High Level SHA1 functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

High Level SHA1 Hash and HMAC functions. +More...

+
+Collaboration diagram for High Level SHA1 functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

ErrorStatus HASH_SHA1 (uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HASH SHA1 digest. More...
 
ErrorStatus HMAC_SHA1 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HMAC SHA1 digest. More...
 
+

Detailed Description

+

High Level SHA1 Hash and HMAC functions.

+
 ===============================================================================
+               ##### High Level SHA1 Hash and HMAC functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus HASH_SHA1 (uint8_t * Input,
uint32_t Ilen,
uint8_t Output[20] 
)
+
+ +

Compute the HASH SHA1 digest.

+
Parameters
+ + + + +
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
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ErrorStatus HMAC_SHA1 (uint8_t * Key,
uint32_t Keylen,
uint8_t * Input,
uint32_t Ilen,
uint8_t Output[20] 
)
+
+ +

Compute the HMAC SHA1 digest.

+
Parameters
+ + + + + + +
Keypointer to the Key used for HMAC.
Keylenlength of the Key used for HMAC.
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group6.map b/group___h_a_s_h___group6.map new file mode 100644 index 0000000..1675016 --- /dev/null +++ b/group___h_a_s_h___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group6.md5 b/group___h_a_s_h___group6.md5 new file mode 100644 index 0000000..9f2e131 --- /dev/null +++ b/group___h_a_s_h___group6.md5 @@ -0,0 +1 @@ +8ea2b9d260853028adacee4f86730465 \ No newline at end of file diff --git a/group___h_a_s_h___group6.png b/group___h_a_s_h___group6.png new file mode 100644 index 0000000..e28fe9a Binary files /dev/null and b/group___h_a_s_h___group6.png differ diff --git a/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.map b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.map new file mode 100644 index 0000000..22804ca --- /dev/null +++ b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.md5 b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.md5 new file mode 100644 index 0000000..d48f498 --- /dev/null +++ b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.md5 @@ -0,0 +1 @@ +2055b7c402e787e09b9b406ca0ffa4b8 \ No newline at end of file diff --git a/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.png b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.png new file mode 100644 index 0000000..566ec54 Binary files /dev/null and b/group___h_a_s_h___group6_ga2728c02c36de6d800e1ede56ea7789cb_cgraph.png differ diff --git a/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.map b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.map new file mode 100644 index 0000000..92d52c4 --- /dev/null +++ b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.md5 b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.md5 new file mode 100644 index 0000000..b59df17 --- /dev/null +++ b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.md5 @@ -0,0 +1 @@ +5a2acdf4dca78e952790f491825dc9db \ No newline at end of file diff --git a/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.png b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.png new file mode 100644 index 0000000..d96f38f Binary files /dev/null and b/group___h_a_s_h___group6_ga2e38e900ca7838c1cea17cef19953a5e_cgraph.png differ diff --git a/group___h_a_s_h___group7.html b/group___h_a_s_h___group7.html new file mode 100644 index 0000000..f9c4eb0 --- /dev/null +++ b/group___h_a_s_h___group7.html @@ -0,0 +1,255 @@ + + + + + + +discoverpixy: High Level MD5 functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
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+
+Functions
+
+
High Level MD5 functions
STM32F4xx_StdPeriph_Driver » HASH » HASH_Private_Functions
+
+
+ +

High Level MD5 Hash and HMAC functions. +More...

+
+Collaboration diagram for High Level MD5 functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

ErrorStatus HASH_MD5 (uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HASH MD5 digest. More...
 
ErrorStatus HMAC_MD5 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HMAC MD5 digest. More...
 
+

Detailed Description

+

High Level MD5 Hash and HMAC functions.

+
 ===============================================================================
+              ##### High Level MD5 Hash and HMAC functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus HASH_MD5 (uint8_t * Input,
uint32_t Ilen,
uint8_t Output[16] 
)
+
+ +

Compute the HASH MD5 digest.

+
Parameters
+ + + + +
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
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+

+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus HMAC_MD5 (uint8_t * Key,
uint32_t Keylen,
uint8_t * Input,
uint32_t Ilen,
uint8_t Output[16] 
)
+
+ +

Compute the HMAC MD5 digest.

+
Parameters
+ + + + + + +
Keypointer to the Key used for HMAC.
Keylenlength of the Key used for HMAC.
Inputpointer to the Input buffer to be treated.
Ilenlength of the Input buffer.
Outputthe returned digest
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: digest computation done
    • +
  • ERROR: digest computation failed
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
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+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___group7.map b/group___h_a_s_h___group7.map new file mode 100644 index 0000000..30598bb --- /dev/null +++ b/group___h_a_s_h___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___group7.md5 b/group___h_a_s_h___group7.md5 new file mode 100644 index 0000000..da70f92 --- /dev/null +++ b/group___h_a_s_h___group7.md5 @@ -0,0 +1 @@ +6d9199d3a5c610431f1ea444de06c575 \ No newline at end of file diff --git a/group___h_a_s_h___group7.png b/group___h_a_s_h___group7.png new file mode 100644 index 0000000..df9e2b3 Binary files /dev/null and b/group___h_a_s_h___group7.png differ diff --git a/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.map b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.map new file mode 100644 index 0000000..dd17222 --- /dev/null +++ b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.md5 b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.md5 new file mode 100644 index 0000000..f93a0aa --- /dev/null +++ b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.md5 @@ -0,0 +1 @@ +4c8560967c179398fb87eeb55fb9d404 \ No newline at end of file diff --git a/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.png b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.png new file mode 100644 index 0000000..069cf3f Binary files /dev/null and b/group___h_a_s_h___group7_ga82a155884e458cc6b7c1a4565c1ac8e9_cgraph.png differ diff --git a/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.map b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.map new file mode 100644 index 0000000..02bae3c --- /dev/null +++ b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.md5 b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.md5 new file mode 100644 index 0000000..b9b0467 --- /dev/null +++ b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.md5 @@ -0,0 +1 @@ +a7ba02a812a21ac5d4f54de15d917c64 \ No newline at end of file diff --git a/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.png b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.png new file mode 100644 index 0000000..3b19ac1 Binary files /dev/null and b/group___h_a_s_h___group7_gac61733e7aa66bdd2f21be4b34165b5be_cgraph.png differ diff --git a/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.html b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.html new file mode 100644 index 0000000..b35e16a --- /dev/null +++ b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: HASH_HMAC_Long_key_only_for_HMAC_mode + + + + + + + + + + +
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discoverpixy +
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+Macros
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+
HASH_HMAC_Long_key_only_for_HMAC_mode
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_HMAC_Long_key_only_for_HMAC_mode:
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+
+ + +
+
+ + + + + + + + +

+Macros

#define HASH_HMACKeyType_ShortKey   ((uint32_t)0x00000000)
 
#define HASH_HMACKeyType_LongKey   HASH_CR_LKEY
 
#define IS_HASH_HMAC_KEYTYPE(KEYTYPE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_HMACKeyType_LongKey   HASH_CR_LKEY
+
+

HMAC Key is > 64 bytes

+ +
+
+ +
+
+ + + + +
#define HASH_HMACKeyType_ShortKey   ((uint32_t)0x00000000)
+
+

HMAC Key is <= 64 bytes

+ +
+
+ +
+
+ + + + + + + + +
#define IS_HASH_HMAC_KEYTYPE( KEYTYPE)
+
+Value:
(((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+
((KEYTYPE) == HASH_HMACKeyType_LongKey))
+
HASH_HMACKeyType_ShortKey
#define HASH_HMACKeyType_ShortKey
Definition: stm32f4xx_hash.h:141
+
HASH_HMACKeyType_LongKey
#define HASH_HMACKeyType_LongKey
Definition: stm32f4xx_hash.h:142
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.map b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.map new file mode 100644 index 0000000..87acad0 --- /dev/null +++ b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.md5 b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.md5 new file mode 100644 index 0000000..a450c60 --- /dev/null +++ b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.md5 @@ -0,0 +1 @@ +6669307ce5bd87e4220d0e80b9420e69 \ No newline at end of file diff --git a/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.png b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.png new file mode 100644 index 0000000..7310edb Binary files /dev/null and b/group___h_a_s_h___h_m_a_c___long__key__only__for___h_m_a_c__mode.png differ diff --git a/group___h_a_s_h___private___functions.html b/group___h_a_s_h___private___functions.html new file mode 100644 index 0000000..0fafe72 --- /dev/null +++ b/group___h_a_s_h___private___functions.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: HASH_Private_Functions + + + + + + + + + + +
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discoverpixy +
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+Modules
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+
HASH_Private_Functions
STM32F4xx_StdPeriph_Driver » HASH
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+Collaboration diagram for HASH_Private_Functions:
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+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Message Digest generation functions
 Message Digest generation functions.
 
 Context swapping functions
 Context swapping functions.
 
 HASH's DMA interface Configuration function
 HASH's DMA interface Configuration function.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
 High Level MD5 functions
 High Level MD5 Hash and HMAC functions.
 
 High Level SHA1 functions
 High Level SHA1 Hash and HMAC functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h___private___functions.map b/group___h_a_s_h___private___functions.map new file mode 100644 index 0000000..d17396c --- /dev/null +++ b/group___h_a_s_h___private___functions.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___h_a_s_h___private___functions.md5 b/group___h_a_s_h___private___functions.md5 new file mode 100644 index 0000000..708da01 --- /dev/null +++ b/group___h_a_s_h___private___functions.md5 @@ -0,0 +1 @@ +aff560e6c390ed36705a8ede6cce69c2 \ No newline at end of file diff --git a/group___h_a_s_h___private___functions.png b/group___h_a_s_h___private___functions.png new file mode 100644 index 0000000..fa9380a Binary files /dev/null and b/group___h_a_s_h___private___functions.png differ diff --git a/group___h_a_s_h__flags__definition.html b/group___h_a_s_h__flags__definition.html new file mode 100644 index 0000000..1cbe9df --- /dev/null +++ b/group___h_a_s_h__flags__definition.html @@ -0,0 +1,232 @@ + + + + + + +discoverpixy: HASH_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
+ +
+ +
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+Macros
+
+
HASH_flags_definition
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_flags_definition:
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+ + + + + + + + + + + + + + + + +

+Macros

#define HASH_FLAG_DINIS   HASH_SR_DINIS
 
#define HASH_FLAG_DCIS   HASH_SR_DCIS
 
#define HASH_FLAG_DMAS   HASH_SR_DMAS
 
#define HASH_FLAG_BUSY   HASH_SR_BUSY
 
#define HASH_FLAG_DINNE   HASH_CR_DINNE
 
#define IS_HASH_GET_FLAG(FLAG)
 
#define IS_HASH_CLEAR_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_FLAG_BUSY   HASH_SR_BUSY
+
+

The hash core is Busy : processing a block of data

+ +
+
+ +
+
+ + + + +
#define HASH_FLAG_DCIS   HASH_SR_DCIS
+
+

Digest calculation complete

+ +
+
+ +
+
+ + + + +
#define HASH_FLAG_DINIS   HASH_SR_DINIS
+
+

16 locations are free in the DIN : A new block can be entered into the input buffer

+ +
+
+ +
+
+ + + + +
#define HASH_FLAG_DINNE   HASH_CR_DINNE
+
+

DIN not empty : The input buffer contains at least one word of data

+ +
+
+ +
+
+ + + + +
#define HASH_FLAG_DMAS   HASH_SR_DMAS
+
+

DMA interface is enabled (DMAE=1) or a transfer is ongoing

+ +
+
+ +
+
+ + + + + + + + +
#define IS_HASH_CLEAR_FLAG( FLAG)
+
+Value:
(((FLAG) == HASH_FLAG_DINIS) || \
+
((FLAG) == HASH_FLAG_DCIS))
+
HASH_FLAG_DCIS
#define HASH_FLAG_DCIS
Definition: stm32f4xx_hash.h:176
+
HASH_FLAG_DINIS
#define HASH_FLAG_DINIS
Definition: stm32f4xx_hash.h:175
+
+
+
+ +
+
+ + + + + + + + +
#define IS_HASH_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == HASH_FLAG_DINIS) || \
+
((FLAG) == HASH_FLAG_DCIS) || \
+
((FLAG) == HASH_FLAG_DMAS) || \
+
((FLAG) == HASH_FLAG_BUSY) || \
+
((FLAG) == HASH_FLAG_DINNE))
+
HASH_FLAG_DINNE
#define HASH_FLAG_DINNE
Definition: stm32f4xx_hash.h:179
+
HASH_FLAG_DCIS
#define HASH_FLAG_DCIS
Definition: stm32f4xx_hash.h:176
+
HASH_FLAG_BUSY
#define HASH_FLAG_BUSY
Definition: stm32f4xx_hash.h:178
+
HASH_FLAG_DINIS
#define HASH_FLAG_DINIS
Definition: stm32f4xx_hash.h:175
+
HASH_FLAG_DMAS
#define HASH_FLAG_DMAS
Definition: stm32f4xx_hash.h:177
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h__flags__definition.map b/group___h_a_s_h__flags__definition.map new file mode 100644 index 0000000..729d977 --- /dev/null +++ b/group___h_a_s_h__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h__flags__definition.md5 b/group___h_a_s_h__flags__definition.md5 new file mode 100644 index 0000000..5a91794 --- /dev/null +++ b/group___h_a_s_h__flags__definition.md5 @@ -0,0 +1 @@ +5d17c1745297245629d4f5a5fcdadea0 \ No newline at end of file diff --git a/group___h_a_s_h__flags__definition.png b/group___h_a_s_h__flags__definition.png new file mode 100644 index 0000000..7a25ea6 Binary files /dev/null and b/group___h_a_s_h__flags__definition.png differ diff --git a/group___h_a_s_h__interrupts__definition.html b/group___h_a_s_h__interrupts__definition.html new file mode 100644 index 0000000..22fb61d --- /dev/null +++ b/group___h_a_s_h__interrupts__definition.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: HASH_interrupts_definition + + + + + + + + + + +
+
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discoverpixy +
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+Macros
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HASH_interrupts_definition
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_interrupts_definition:
+
+
+ + +
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+ + + + + + + + + + +

+Macros

#define HASH_IT_DINI   HASH_IMR_DINIM
 
#define HASH_IT_DCI   HASH_IMR_DCIM
 
+#define IS_HASH_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
 
+#define IS_HASH_GET_IT(IT)   (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_IT_DCI   HASH_IMR_DCIM
+
+

Digest calculation complete

+ +
+
+ +
+
+ + + + +
#define HASH_IT_DINI   HASH_IMR_DINIM
+
+

A new block can be entered into the input buffer (DIN)

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___h_a_s_h__interrupts__definition.map b/group___h_a_s_h__interrupts__definition.map new file mode 100644 index 0000000..56aa144 --- /dev/null +++ b/group___h_a_s_h__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___h_a_s_h__interrupts__definition.md5 b/group___h_a_s_h__interrupts__definition.md5 new file mode 100644 index 0000000..d6dc790 --- /dev/null +++ b/group___h_a_s_h__interrupts__definition.md5 @@ -0,0 +1 @@ +862dc0b43440c7cd9498f285563fdc72 \ No newline at end of file diff --git a/group___h_a_s_h__interrupts__definition.png b/group___h_a_s_h__interrupts__definition.png new file mode 100644 index 0000000..b0bdeed Binary files /dev/null and b/group___h_a_s_h__interrupts__definition.png differ diff --git a/group___h_a_s_h__processor___algorithm___mode.html b/group___h_a_s_h__processor___algorithm___mode.html new file mode 100644 index 0000000..237352b --- /dev/null +++ b/group___h_a_s_h__processor___algorithm___mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: HASH_processor_Algorithm_Mode + + + + + + + + + + +
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+Macros
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HASH_processor_Algorithm_Mode
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for HASH_processor_Algorithm_Mode:
+
+
+ + +
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+ + + + + + + + +

+Macros

#define HASH_AlgoMode_HASH   ((uint32_t)0x00000000)
 
#define HASH_AlgoMode_HMAC   HASH_CR_MODE
 
#define IS_HASH_ALGOMODE(ALGOMODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define HASH_AlgoMode_HASH   ((uint32_t)0x00000000)
+
+

Algorithm is HASH

+ +
+
+ +
+
+ + + + +
#define HASH_AlgoMode_HMAC   HASH_CR_MODE
+
+

Algorithm is HMAC

+ +
+
+ +
+
+ + + + + + + + +
#define IS_HASH_ALGOMODE( ALGOMODE)
+
+Value:
(((ALGOMODE) == HASH_AlgoMode_HASH) || \
+
((ALGOMODE) == HASH_AlgoMode_HMAC))
+
HASH_AlgoMode_HMAC
#define HASH_AlgoMode_HMAC
Definition: stm32f4xx_hash.h:114
+
HASH_AlgoMode_HASH
#define HASH_AlgoMode_HASH
Definition: stm32f4xx_hash.h:113
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Macros
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+
High_Pass_Filter_Interrupt_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
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+
+
+Collaboration diagram for High_Pass_Filter_Interrupt_selection:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF   ((uint8_t)0x00)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1   ((uint8_t)0x04)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_2   ((uint8_t)0x08)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2   ((uint8_t)0x0C)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___high___pass___filter___interrupt__selection.map b/group___high___pass___filter___interrupt__selection.map new file mode 100644 index 0000000..872c5bd --- /dev/null +++ b/group___high___pass___filter___interrupt__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___high___pass___filter___interrupt__selection.md5 b/group___high___pass___filter___interrupt__selection.md5 new file mode 100644 index 0000000..ca3f3b7 --- /dev/null +++ b/group___high___pass___filter___interrupt__selection.md5 @@ -0,0 +1 @@ +bd225157a949e1e7563745704f617453 \ No newline at end of file diff --git a/group___high___pass___filter___interrupt__selection.png b/group___high___pass___filter___interrupt__selection.png new file mode 100644 index 0000000..952b874 Binary files /dev/null and b/group___high___pass___filter___interrupt__selection.png differ diff --git a/group___high___pass___filter__selection.html b/group___high___pass___filter__selection.html new file mode 100644 index 0000000..1e7d662 --- /dev/null +++ b/group___high___pass___filter__selection.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: High_Pass_Filter_selection + + + + + + + + + + +
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discoverpixy +
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+Macros
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+
High_Pass_Filter_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for High_Pass_Filter_selection:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define LIS302DL_HIGHPASSFILTER_LEVEL_0   ((uint8_t)0x00)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_1   ((uint8_t)0x01)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_2   ((uint8_t)0x02)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_3   ((uint8_t)0x03)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___high___pass___filter__selection.map b/group___high___pass___filter__selection.map new file mode 100644 index 0000000..d0bc33d --- /dev/null +++ b/group___high___pass___filter__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___high___pass___filter__selection.md5 b/group___high___pass___filter__selection.md5 new file mode 100644 index 0000000..9fdfe96 --- /dev/null +++ b/group___high___pass___filter__selection.md5 @@ -0,0 +1 @@ +853fc8a181e8b16ea03dca811bc632ec \ No newline at end of file diff --git a/group___high___pass___filter__selection.png b/group___high___pass___filter__selection.png new file mode 100644 index 0000000..8aea12f Binary files /dev/null and b/group___high___pass___filter__selection.png differ diff --git a/group___i2_c.html b/group___i2_c.html new file mode 100644 index 0000000..a177e13 --- /dev/null +++ b/group___i2_c.html @@ -0,0 +1,1803 @@ + + + + + + +discoverpixy: I2C + + + + + + + + + + +
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+Modules | +Classes | +Macros | +Functions
+
+
I2C
STM32F4xx_StdPeriph_Driver
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+
+ +

I2C driver modules. +More...

+
+Collaboration diagram for I2C:
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+ + + + + + +

+Modules

 I2C_Exported_Constants
 
 I2C_Private_Functions
 
+ + + + +

+Classes

struct  I2C_InitTypeDef
 I2C Init structure definition. More...
 
+ + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint16_t)0xFBF5) /*<! I2C registers Masks */
 
+#define FLAG_MASK   ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */
 
+#define ITEN_MASK   ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void I2C_DeInit (I2C_TypeDef *I2Cx)
 Deinitialize the I2Cx peripheral registers to their default reset values. More...
 
void I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
 Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. More...
 
void I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
 Fills each I2C_InitStruct member with its default value. More...
 
void I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C peripheral. More...
 
void I2C_DigitalFilterConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DigitalFilter)
 Configures the Digital noise filter of I2C peripheral. More...
 
void I2C_AnalogFilterCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the Analog filter of I2C peripheral. More...
 
void I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication START condition. More...
 
void I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication STOP condition. More...
 
void I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
 Transmits the address byte to select the slave device. More...
 
void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C acknowledge feature. More...
 
void I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
 Configures the specified I2C own address2. More...
 
void I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C dual addressing mode. More...
 
void I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C general call feature. More...
 
void I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C software reset. More...
 
void I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C Clock stretching. More...
 
void I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
 Selects the specified I2C fast mode duty cycle. More...
 
void I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
 Selects the specified I2C NACK position in master receiver mode. More...
 
void I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
 Drives the SMBusAlert pin high or low for the specified I2C. More...
 
void I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C ARP. More...
 
void I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
 Sends a data byte through the I2Cx peripheral. More...
 
uint8_t I2C_ReceiveData (I2C_TypeDef *I2Cx)
 Returns the most recent received data by the I2Cx peripheral. More...
 
void I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C PEC transfer. More...
 
void I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
 Selects the specified I2C PEC position. More...
 
void I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the PEC value calculation of the transferred bytes. More...
 
uint8_t I2C_GetPEC (I2C_TypeDef *I2Cx)
 Returns the PEC value for the specified I2C. More...
 
void I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C DMA requests. More...
 
void I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Specifies that the next DMA transfer is the last one. More...
 
uint16_t I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
 Reads the specified I2C register and returns its value. More...
 
void I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
 Enables or disables the specified I2C interrupts. More...
 
ErrorStatus I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 Checks whether the last I2Cx Event is equal to the one passed as parameter. More...
 
uint32_t I2C_GetLastEvent (I2C_TypeDef *I2Cx)
 Returns the last I2Cx Event. More...
 
FlagStatus I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Checks whether the specified I2C flag is set or not. More...
 
void I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Clears the I2Cx's pending flags. More...
 
ITStatus I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Checks whether the specified I2C interrupt has occurred or not. More...
 
void I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Clears the I2Cx's interrupt pending bits. More...
 
+

Detailed Description

+

I2C driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_AcknowledgeConfig (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C acknowledge feature.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_AnalogFilterCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the Analog filter of I2C peripheral.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the Analog filter. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
This function should be called before initializing and enabling the I2C Peripheral.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ARPCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C ARP.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_CalculatePEC (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the PEC value calculation of the transferred bytes.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus I2C_CheckEvent (I2C_TypeDef * I2Cx,
uint32_t I2C_EVENT 
)
+
+ +

Checks whether the last I2Cx Event is equal to the one passed as parameter.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_EVENTspecifies the event to be checked. This parameter can be one of the following values:
    +
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
    • +
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
    • +
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
    • +
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
    • +
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
    • +
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
    • +
  • I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
    • +
  • I2C_EVENT_SLAVE_STOP_DETECTED: EV4
    • +
  • I2C_EVENT_MASTER_MODE_SELECT: EV5
    • +
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
    • +
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
    • +
  • I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
    • +
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
    • +
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
    • +
  • I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
    • +
+
+
+
+
Note
For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Last event is equal to the I2C_EVENT
    • +
  • ERROR: Last event is different from the I2C_EVENT
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ClearFlag (I2C_TypeDef * I2Cx,
uint32_t I2C_FLAG 
)
+
+ +

Clears the I2Cx's pending flags.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • I2C_FLAG_SMBALERT: SMBus Alert flag
    • +
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_FLAG_PECERR: PEC error in reception flag
    • +
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_FLAG_AF: Acknowledge failure flag
    • +
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_FLAG_BERR: Bus error flag
    • +
+
+
+
+
Note
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+
+ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
+
+BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
+
+ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
+
+SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ClearITPendingBit (I2C_TypeDef * I2Cx,
uint32_t I2C_IT 
)
+
+ +

Clears the I2Cx's interrupt pending bits.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • I2C_IT_SMBALERT: SMBus Alert interrupt
    • +
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
    • +
  • I2C_IT_PECERR: PEC error in reception interrupt
    • +
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
    • +
  • I2C_IT_AF: Acknowledge failure interrupt
    • +
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
    • +
  • I2C_IT_BERR: Bus error interrupt
    • +
+
+
+
+
Note
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+
+ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
+
+BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
+
+ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
+
+SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_Cmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C peripheral.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2C_DeInit (I2C_TypeDef * I2Cx)
+
+ +

Deinitialize the I2Cx peripheral registers to their default reset values.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

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+
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void I2C_DigitalFilterConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_DigitalFilter 
)
+
+ +

Configures the Digital noise filter of I2C peripheral.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_DigitalFilterCoefficient of digital noise filter. This parameter can be a number between 0x00 and 0x0F.
+
+
+
Note
This function should be called before initializing and enabling the I2C Peripheral.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DMACmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C DMA requests.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DMALastTransferCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Specifies that the next DMA transfer is the last one.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DualAddressCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C dual addressing mode.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_FastModeDutyCycleConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_DutyCycle 
)
+
+ +

Selects the specified I2C fast mode duty cycle.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_DutyCyclespecifies the fast mode duty cycle. This parameter can be one of the following values:
    +
  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
    • +
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_GeneralCallCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C general call feature.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C General call. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_GenerateSTART (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Generates I2Cx communication START condition.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_GenerateSTOP (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Generates I2Cx communication STOP condition.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus I2C_GetFlagStatus (I2C_TypeDef * I2Cx,
uint32_t I2C_FLAG 
)
+
+ +

Checks whether the specified I2C flag is set or not.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • I2C_FLAG_DUALF: Dual flag (Slave mode)
    • +
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
    • +
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
    • +
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
    • +
  • I2C_FLAG_TRA: Transmitter/Receiver flag
    • +
  • I2C_FLAG_BUSY: Bus busy flag
    • +
  • I2C_FLAG_MSL: Master/Slave flag
    • +
  • I2C_FLAG_SMBALERT: SMBus Alert flag
    • +
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_FLAG_PECERR: PEC error in reception flag
    • +
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_FLAG_AF: Acknowledge failure flag
    • +
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_FLAG_BERR: Bus error flag
    • +
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
    • +
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
    • +
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
    • +
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
    • +
  • I2C_FLAG_BTF: Byte transfer finished flag
    • +
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
    • +
  • I2C_FLAG_SB: Start bit flag (Master mode)
    • +
+
+
+
+
Return values
+ + +
Thenew state of I2C_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus I2C_GetITStatus (I2C_TypeDef * I2Cx,
uint32_t I2C_IT 
)
+
+ +

Checks whether the specified I2C interrupt has occurred or not.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the interrupt source to check. This parameter can be one of the following values:
    +
  • I2C_IT_SMBALERT: SMBus Alert flag
    • +
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_IT_PECERR: PEC error in reception flag
    • +
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_IT_AF: Acknowledge failure flag
    • +
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_IT_BERR: Bus error flag
    • +
  • I2C_IT_TXE: Data register empty flag (Transmitter)
    • +
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
    • +
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
    • +
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
    • +
  • I2C_IT_BTF: Byte transfer finished flag
    • +
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
    • +
  • I2C_IT_SB: Start bit flag (Master mode)
    • +
+
+
+
+
Return values
+ + +
Thenew state of I2C_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t I2C_GetLastEvent (I2C_TypeDef * I2Cx)
+
+ +

Returns the last I2Cx Event.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Note
For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file.
+
Return values
+ + +
Thelast event
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t I2C_GetPEC (I2C_TypeDef * I2Cx)
+
+ +

Returns the PEC value for the specified I2C.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
ThePEC value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_Init (I2C_TypeDef * I2Cx,
I2C_InitTypeDef * I2C_InitStruct 
)
+
+ +

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

+
Note
To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_InitStructpointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

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+
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void I2C_ITConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C interrupts.

+
Parameters
+ + + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • I2C_IT_BUF: Buffer interrupt mask
    • +
  • I2C_IT_EVT: Event interrupt mask
    • +
  • I2C_IT_ERR: Error interrupt mask
    • +
+
NewStatenew state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_NACKPositionConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_NACKPosition 
)
+
+ +

Selects the specified I2C NACK position in master receiver mode.

+
Note
This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_NACKPositionspecifies the NACK position. This parameter can be one of the following values:
    +
  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
    • +
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
    • +
+
+
+
+
Note
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_OwnAddress2Config (I2C_TypeDef * I2Cx,
uint8_t Address 
)
+
+ +

Configures the specified I2C own address2.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
Addressspecifies the 7bit I2C own address2.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_PECPositionConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_PECPosition 
)
+
+ +

Selects the specified I2C PEC position.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_PECPositionspecifies the PEC position. This parameter can be one of the following values:
    +
  • I2C_PECPosition_Next: indicates that the next byte is PEC
    • +
  • I2C_PECPosition_Current: indicates that current byte is PEC
    • +
+
+
+
+
Note
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t I2C_ReadRegister (I2C_TypeDef * I2Cx,
uint8_t I2C_Register 
)
+
+ +

Reads the specified I2C register and returns its value.

+
Parameters
+ + +
I2C_Registerspecifies the register to read. This parameter can be one of the following values:
    +
  • I2C_Register_CR1: CR1 register.
    • +
  • I2C_Register_CR2: CR2 register.
    • +
  • I2C_Register_OAR1: OAR1 register.
    • +
  • I2C_Register_OAR2: OAR2 register.
    • +
  • I2C_Register_DR: DR register.
    • +
  • I2C_Register_SR1: SR1 register.
    • +
  • I2C_Register_SR2: SR2 register.
    • +
  • I2C_Register_CCR: CCR register.
    • +
  • I2C_Register_TRISE: TRISE register.
    • +
+
+
+
+
Return values
+ + +
Thevalue of the read register.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t I2C_ReceiveData (I2C_TypeDef * I2Cx)
+
+ +

Returns the most recent received data by the I2Cx peripheral.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void I2C_Send7bitAddress (I2C_TypeDef * I2Cx,
uint8_t Address,
uint8_t I2C_Direction 
)
+
+ +

Transmits the address byte to select the slave device.

+
Parameters
+ + + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
Addressspecifies the slave address which will be transmitted
I2C_Directionspecifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values
    +
  • I2C_Direction_Transmitter: Transmitter mode
    • +
  • I2C_Direction_Receiver: Receiver mode
    • +
+
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_SendData (I2C_TypeDef * I2Cx,
uint8_t Data 
)
+
+ +

Sends a data byte through the I2Cx peripheral.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
DataByte to be transmitted..
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_SMBusAlertConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_SMBusAlert 
)
+
+ +

Drives the SMBusAlert pin high or low for the specified I2C.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_SMBusAlertspecifies SMBAlert pin level. This parameter can be one of the following values:
    +
  • I2C_SMBusAlert_Low: SMBAlert pin driven low
    • +
  • I2C_SMBusAlert_High: SMBAlert pin driven high
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_SoftwareResetCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C software reset.

+
Note
When software reset is enabled, the I2C IOs are released (this can be useful to recover from bus errors).
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_StretchClockCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C Clock stretching.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2C_StructInit (I2C_InitTypeDef * I2C_InitStruct)
+
+ +

Fills each I2C_InitStruct member with its default value.

+
Parameters
+ + +
I2C_InitStructpointer to an I2C_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_TransmitPEC (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C PEC transfer.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c.map b/group___i2_c.map new file mode 100644 index 0000000..b3cefd7 --- /dev/null +++ b/group___i2_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___i2_c.md5 b/group___i2_c.md5 new file mode 100644 index 0000000..bd331a0 --- /dev/null +++ b/group___i2_c.md5 @@ -0,0 +1 @@ +151207a73790b07d8d5b87e438ff660d \ No newline at end of file diff --git a/group___i2_c.png b/group___i2_c.png new file mode 100644 index 0000000..d00cc41 Binary files /dev/null and b/group___i2_c.png differ diff --git a/group___i2_c___digital___filter.html b/group___i2_c___digital___filter.html new file mode 100644 index 0000000..d56286e --- /dev/null +++ b/group___i2_c___digital___filter.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: I2C_Digital_Filter + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
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+Macros
+
+
I2C_Digital_Filter
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_Digital_Filter:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___digital___filter.map b/group___i2_c___digital___filter.map new file mode 100644 index 0000000..46e6de8 --- /dev/null +++ b/group___i2_c___digital___filter.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___digital___filter.md5 b/group___i2_c___digital___filter.md5 new file mode 100644 index 0000000..df29010 --- /dev/null +++ b/group___i2_c___digital___filter.md5 @@ -0,0 +1 @@ +8a843f23def6ff4782f279909d6c31e8 \ No newline at end of file diff --git a/group___i2_c___digital___filter.png b/group___i2_c___digital___filter.png new file mode 100644 index 0000000..069e312 Binary files /dev/null and b/group___i2_c___digital___filter.png differ diff --git a/group___i2_c___events.html b/group___i2_c___events.html new file mode 100644 index 0000000..20d7c7d --- /dev/null +++ b/group___i2_c___events.html @@ -0,0 +1,304 @@ + + + + + + +discoverpixy: I2C_Events + + + + + + + + + + +
+
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+Macros
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+
I2C_Events
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_Events:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define I2C_EVENT_MASTER_MODE_SELECT   ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
 Communication start. More...
 
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED   ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
 Address Acknowledge. More...
 
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED   ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
 
+#define I2C_EVENT_MASTER_MODE_ADDRESS10   ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
 
#define I2C_EVENT_MASTER_BYTE_RECEIVED   ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
 Communication events. More...
 
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING   ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
 
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED   ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
 
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED   ((uint32_t)0x00020002) /* BUSY and ADDR flags */
 Communication start events. More...
 
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED   ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
 
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED   ((uint32_t)0x00820000) /* DUALF and BUSY flags */
 
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED   ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
 
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED   ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
 
#define I2C_EVENT_SLAVE_BYTE_RECEIVED   ((uint32_t)0x00020040) /* BUSY and RXNE flags */
 Communication events. More...
 
+#define I2C_EVENT_SLAVE_STOP_DETECTED   ((uint32_t)0x00000010) /* STOPF flag */
 
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED   ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
 
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING   ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
 
+#define I2C_EVENT_SLAVE_ACK_FAILURE   ((uint32_t)0x00000400) /* AF flag */
 
#define IS_I2C_EVENT(EVENT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define I2C_EVENT_MASTER_BYTE_RECEIVED   ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+ +

Communication events.

+

If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures:

+

1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function).

+

2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar:

    +
  • EV8 means that the data has been written in the data register and is being shifted out.
    • +
  • EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensure more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation).
    • +
+
Note
In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.
+ +
+
+ +
+
+ + + + +
#define I2C_EVENT_MASTER_MODE_SELECT   ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+ +

Communication start.

+

===============================================================================

I2C Master Events (Events grouped in order of communication)

+

After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating).

+ +
+
+ +
+
+ + + + +
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED   ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+
+ +

Address Acknowledge.

+

After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set:

+

1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.

+

2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set

+

3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6.

+ +
+
+ +
+
+ + + + +
#define I2C_EVENT_SLAVE_BYTE_RECEIVED   ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+
+ +

Communication events.

+

Wait on one of these events when EV1 has already been checked and:

+
    +
  • Slave RECEIVER mode:
      +
    • EV2: When the application is expecting a data byte to be received.
      • +
    • EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped.
      • +
    +
    • +

  • Slave Transmitter mode:

      +
    • EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of transfer.
      • +
    • EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus.
      • +
    +
    Note
    In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower.
    +
    • +
+ +
+
+ +
+
+ + + + +
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED   ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+
+ +

Communication start events.

+

===============================================================================

I2C Slave Events (Events grouped in order of communication)

+

Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set :

+

1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER).

+

2) In case the address sent by the master matches the second address of the peripheral (configured by the function I2C_OwnAddress2Config() and enabled by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED (where XXX could be TRANSMITTER or RECEIVER) are set.

+

3) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.

+ +
+
+ +
+
+ + + + + + + + +
#define IS_I2C_EVENT( EVENT)
+
+Value:
(((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+
I2C_EVENT_MASTER_MODE_SELECT
#define I2C_EVENT_MASTER_MODE_SELECT
Communication start.
Definition: stm32f4xx_i2c.h:335
+
I2C_FLAG_DUALF
#define I2C_FLAG_DUALF
SR2 register flags.
Definition: stm32f4xx_i2c.h:272
+
I2C_EVENT_SLAVE_BYTE_RECEIVED
#define I2C_EVENT_SLAVE_BYTE_RECEIVED
Communication events.
Definition: stm32f4xx_i2c.h:481
+
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED
Communication start events.
Definition: stm32f4xx_i2c.h:442
+
I2C_EVENT_MASTER_BYTE_RECEIVED
#define I2C_EVENT_MASTER_BYTE_RECEIVED
Communication events.
Definition: stm32f4xx_i2c.h:399
+
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
Address Acknowledge.
Definition: stm32f4xx_i2c.h:363
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___events.map b/group___i2_c___events.map new file mode 100644 index 0000000..c03cdec --- /dev/null +++ b/group___i2_c___events.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___events.md5 b/group___i2_c___events.md5 new file mode 100644 index 0000000..ab63018 --- /dev/null +++ b/group___i2_c___events.md5 @@ -0,0 +1 @@ +4757f4fc67fe9c4b33ef312ae687ef4c \ No newline at end of file diff --git a/group___i2_c___events.png b/group___i2_c___events.png new file mode 100644 index 0000000..982071c Binary files /dev/null and b/group___i2_c___events.png differ diff --git a/group___i2_c___exported___constants.html b/group___i2_c___exported___constants.html new file mode 100644 index 0000000..d26a873 --- /dev/null +++ b/group___i2_c___exported___constants.html @@ -0,0 +1,162 @@ + + + + + + +discoverpixy: I2C_Exported_Constants + + + + + + + + + + +
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+Modules | +Macros
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I2C_Exported_Constants
STM32F4xx_StdPeriph_Driver » I2C
+
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+Collaboration diagram for I2C_Exported_Constants:
+
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+Modules

 I2C_Digital_Filter
 
 I2C_mode
 
 I2C_duty_cycle_in_fast_mode
 
 I2C_acknowledgement
 
 I2C_transfer_direction
 
 I2C_acknowledged_address
 
 I2C_registers
 
 I2C_NACK_position
 
 I2C_SMBus_alert_pin_level
 
 I2C_PEC_position
 
 I2C_interrupts_definition
 
 I2C_flags_definition
 
 I2C_Events
 
 I2C_own_address1
 
 I2C_clock_speed
 
+ + + +

+Macros

#define IS_I2C_ALL_PERIPH(PERIPH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == I2C1) || \
+
((PERIPH) == I2C2) || \
+
((PERIPH) == I2C3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___exported___constants.map b/group___i2_c___exported___constants.map new file mode 100644 index 0000000..f39d1de --- /dev/null +++ b/group___i2_c___exported___constants.map @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/group___i2_c___exported___constants.md5 b/group___i2_c___exported___constants.md5 new file mode 100644 index 0000000..6b20a1f --- /dev/null +++ b/group___i2_c___exported___constants.md5 @@ -0,0 +1 @@ +5a6a0b65af3f8f894231bfe9b4d62f01 \ No newline at end of file diff --git a/group___i2_c___exported___constants.png b/group___i2_c___exported___constants.png new file mode 100644 index 0000000..ff8dfd0 Binary files /dev/null and b/group___i2_c___exported___constants.png differ diff --git a/group___i2_c___group1.html b/group___i2_c___group1.html new file mode 100644 index 0000000..9ab758b --- /dev/null +++ b/group___i2_c___group1.html @@ -0,0 +1,976 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » I2C » I2C_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void I2C_DeInit (I2C_TypeDef *I2Cx)
 Deinitialize the I2Cx peripheral registers to their default reset values. More...
 
void I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
 Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. More...
 
void I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
 Fills each I2C_InitStruct member with its default value. More...
 
void I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C peripheral. More...
 
void I2C_AnalogFilterCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the Analog filter of I2C peripheral. More...
 
void I2C_DigitalFilterConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DigitalFilter)
 Configures the Digital noise filter of I2C peripheral. More...
 
void I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication START condition. More...
 
void I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication STOP condition. More...
 
void I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
 Transmits the address byte to select the slave device. More...
 
void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C acknowledge feature. More...
 
void I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
 Configures the specified I2C own address2. More...
 
void I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C dual addressing mode. More...
 
void I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C general call feature. More...
 
void I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C software reset. More...
 
void I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C Clock stretching. More...
 
void I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
 Selects the specified I2C fast mode duty cycle. More...
 
void I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
 Selects the specified I2C NACK position in master receiver mode. More...
 
void I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
 Drives the SMBusAlert pin high or low for the specified I2C. More...
 
void I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C ARP. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_AcknowledgeConfig (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C acknowledge feature.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C Acknowledgement. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
void I2C_AnalogFilterCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the Analog filter of I2C peripheral.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the Analog filter. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
This function should be called before initializing and enabling the I2C Peripheral.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ARPCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C ARP.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx ARP. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_Cmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C peripheral.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2C_DeInit (I2C_TypeDef * I2Cx)
+
+ +

Deinitialize the I2Cx peripheral registers to their default reset values.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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void I2C_DigitalFilterConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_DigitalFilter 
)
+
+ +

Configures the Digital noise filter of I2C peripheral.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_DigitalFilterCoefficient of digital noise filter. This parameter can be a number between 0x00 and 0x0F.
+
+
+
Note
This function should be called before initializing and enabling the I2C Peripheral.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DualAddressCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C dual addressing mode.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C dual addressing mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_FastModeDutyCycleConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_DutyCycle 
)
+
+ +

Selects the specified I2C fast mode duty cycle.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_DutyCyclespecifies the fast mode duty cycle. This parameter can be one of the following values:
    +
  • I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
    • +
  • I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_GeneralCallCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C general call feature.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C General call. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
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+ +
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void I2C_GenerateSTART (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Generates I2Cx communication START condition.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C START condition generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_GenerateSTOP (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Generates I2Cx communication STOP condition.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C STOP condition generation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
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void I2C_Init (I2C_TypeDef * I2Cx,
I2C_InitTypeDef * I2C_InitStruct 
)
+
+ +

Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.

+
Note
To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_InitStructpointer to a I2C_InitTypeDef structure that contains the configuration information for the specified I2C peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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void I2C_NACKPositionConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_NACKPosition 
)
+
+ +

Selects the specified I2C NACK position in master receiver mode.

+
Note
This function is useful in I2C Master Receiver mode when the number of data to be received is equal to 2. In this case, this function should be called (with parameter I2C_NACKPosition_Next) before data reception starts,as described in the 2-byte reception procedure recommended in Reference Manual in Section: Master receiver.
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_NACKPositionspecifies the NACK position. This parameter can be one of the following values:
    +
  • I2C_NACKPosition_Next: indicates that the next byte will be the last received byte.
    • +
  • I2C_NACKPosition_Current: indicates that current byte is the last received byte.
    • +
+
+
+
+
Note
This function configures the same bit (POS) as I2C_PECPositionConfig() but is intended to be used in I2C mode while I2C_PECPositionConfig() is intended to used in SMBUS mode.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
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void I2C_OwnAddress2Config (I2C_TypeDef * I2Cx,
uint8_t Address 
)
+
+ +

Configures the specified I2C own address2.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
Addressspecifies the 7bit I2C own address2.
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
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void I2C_Send7bitAddress (I2C_TypeDef * I2Cx,
uint8_t Address,
uint8_t I2C_Direction 
)
+
+ +

Transmits the address byte to select the slave device.

+
Parameters
+ + + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
Addressspecifies the slave address which will be transmitted
I2C_Directionspecifies whether the I2C device will be a Transmitter or a Receiver. This parameter can be one of the following values
    +
  • I2C_Direction_Transmitter: Transmitter mode
    • +
  • I2C_Direction_Receiver: Receiver mode
    • +
+
+
+
+
Return values
+ + +
None.
+
+
+ +
+
+ +
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void I2C_SMBusAlertConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_SMBusAlert 
)
+
+ +

Drives the SMBusAlert pin high or low for the specified I2C.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_SMBusAlertspecifies SMBAlert pin level. This parameter can be one of the following values:
    +
  • I2C_SMBusAlert_Low: SMBAlert pin driven low
    • +
  • I2C_SMBusAlert_High: SMBAlert pin driven high
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_SoftwareResetCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C software reset.

+
Note
When software reset is enabled, the I2C IOs are released (this can be useful to recover from bus errors).
+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C software reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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void I2C_StretchClockCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C Clock stretching.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx Clock stretching. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2C_StructInit (I2C_InitTypeDef * I2C_InitStruct)
+
+ +

Fills each I2C_InitStruct member with its default value.

+
Parameters
+ + +
I2C_InitStructpointer to an I2C_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___group1.map b/group___i2_c___group1.map new file mode 100644 index 0000000..84a59c5 --- /dev/null +++ b/group___i2_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group1.md5 b/group___i2_c___group1.md5 new file mode 100644 index 0000000..f9d59a9 --- /dev/null +++ b/group___i2_c___group1.md5 @@ -0,0 +1 @@ +48f6eab0ca5786bfe7d8fe0e6de43524 \ No newline at end of file diff --git a/group___i2_c___group1.png b/group___i2_c___group1.png new file mode 100644 index 0000000..47c42c6 Binary files /dev/null and b/group___i2_c___group1.png differ diff --git a/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map new file mode 100644 index 0000000..f89c54e --- /dev/null +++ b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 new file mode 100644 index 0000000..d7b9411 --- /dev/null +++ b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 @@ -0,0 +1 @@ +516b1e77d556fa82602c8bbc36721e98 \ No newline at end of file diff --git a/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png new file mode 100644 index 0000000..a43905c Binary files /dev/null and b/group___i2_c___group1_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png differ diff --git a/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map new file mode 100644 index 0000000..99b289d --- /dev/null +++ b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 new file mode 100644 index 0000000..46d36ba --- /dev/null +++ b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 @@ -0,0 +1 @@ +f540da808c02942412bab6e4ecca9e6e \ No newline at end of file diff --git a/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png new file mode 100644 index 0000000..bef5362 Binary files /dev/null and b/group___i2_c___group1_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png differ diff --git a/group___i2_c___group2.html b/group___i2_c___group2.html new file mode 100644 index 0000000..9c53db8 --- /dev/null +++ b/group___i2_c___group2.html @@ -0,0 +1,190 @@ + + + + + + +discoverpixy: Data transfers functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Functions
+
+
Data transfers functions
STM32F4xx_StdPeriph_Driver » I2C » I2C_Private_Functions
+
+
+ +

Data transfers functions. +More...

+
+Collaboration diagram for Data transfers functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
 Sends a data byte through the I2Cx peripheral. More...
 
uint8_t I2C_ReceiveData (I2C_TypeDef *I2Cx)
 Returns the most recent received data by the I2Cx peripheral. More...
 
+

Detailed Description

+

Data transfers functions.

+
 ===============================================================================
+                  ##### Data transfers functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
uint8_t I2C_ReceiveData (I2C_TypeDef * I2Cx)
+
+ +

Returns the most recent received data by the I2Cx peripheral.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_SendData (I2C_TypeDef * I2Cx,
uint8_t Data 
)
+
+ +

Sends a data byte through the I2Cx peripheral.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
DataByte to be transmitted..
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
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discoverpixy +
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+Functions
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+
PEC management functions
STM32F4xx_StdPeriph_Driver » I2C » I2C_Private_Functions
+
+
+ +

PEC management functions. +More...

+
+Collaboration diagram for PEC management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C PEC transfer. More...
 
void I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
 Selects the specified I2C PEC position. More...
 
void I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the PEC value calculation of the transferred bytes. More...
 
uint8_t I2C_GetPEC (I2C_TypeDef *I2Cx)
 Returns the PEC value for the specified I2C. More...
 
+

Detailed Description

+

PEC management functions.

+
 ===============================================================================
+                  ##### PEC management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_CalculatePEC (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the PEC value calculation of the transferred bytes.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2Cx PEC value calculation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t I2C_GetPEC (I2C_TypeDef * I2Cx)
+
+ +

Returns the PEC value for the specified I2C.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Return values
+ + +
ThePEC value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_PECPositionConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_PECPosition 
)
+
+ +

Selects the specified I2C PEC position.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_PECPositionspecifies the PEC position. This parameter can be one of the following values:
    +
  • I2C_PECPosition_Next: indicates that the next byte is PEC
    • +
  • I2C_PECPosition_Current: indicates that current byte is PEC
    • +
+
+
+
+
Note
This function configures the same bit (POS) as I2C_NACKPositionConfig() but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() is intended to used in I2C mode.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_TransmitPEC (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C PEC transfer.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C PEC transmission. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___group3.map b/group___i2_c___group3.map new file mode 100644 index 0000000..aad5a2e --- /dev/null +++ b/group___i2_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group3.md5 b/group___i2_c___group3.md5 new file mode 100644 index 0000000..7aee6ff --- /dev/null +++ b/group___i2_c___group3.md5 @@ -0,0 +1 @@ +5bfdc1ada8b9581ceaa68be59c1e0f5f \ No newline at end of file diff --git a/group___i2_c___group3.png b/group___i2_c___group3.png new file mode 100644 index 0000000..df3a884 Binary files /dev/null and b/group___i2_c___group3.png differ diff --git a/group___i2_c___group4.html b/group___i2_c___group4.html new file mode 100644 index 0000000..a457a6f --- /dev/null +++ b/group___i2_c___group4.html @@ -0,0 +1,203 @@ + + + + + + +discoverpixy: DMA transfers management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
DMA transfers management functions
STM32F4xx_StdPeriph_Driver » I2C » I2C_Private_Functions
+
+
+ +

DMA transfers management functions. +More...

+
+Collaboration diagram for DMA transfers management functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C DMA requests. More...
 
void I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Specifies that the next DMA transfer is the last one. More...
 
+

Detailed Description

+

DMA transfers management functions.

+
 ===============================================================================
+                ##### DMA transfers management functions #####
+ ===============================================================================  
+  This section provides functions allowing to configure the I2C DMA channels 
+  requests.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DMACmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C DMA requests.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C DMA transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_DMALastTransferCmd (I2C_TypeDef * I2Cx,
FunctionalState NewState 
)
+
+ +

Specifies that the next DMA transfer is the last one.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
NewStatenew state of the I2C DMA last transfer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___group4.map b/group___i2_c___group4.map new file mode 100644 index 0000000..a35624c --- /dev/null +++ b/group___i2_c___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group4.md5 b/group___i2_c___group4.md5 new file mode 100644 index 0000000..b7d34ed --- /dev/null +++ b/group___i2_c___group4.md5 @@ -0,0 +1 @@ +ceb7a31253a8660be515591e944cf49e \ No newline at end of file diff --git a/group___i2_c___group4.png b/group___i2_c___group4.png new file mode 100644 index 0000000..eb2ca2c Binary files /dev/null and b/group___i2_c___group4.png differ diff --git a/group___i2_c___group5.html b/group___i2_c___group5.html new file mode 100644 index 0000000..8a2940e --- /dev/null +++ b/group___i2_c___group5.html @@ -0,0 +1,669 @@ + + + + + + +discoverpixy: Interrupts events and flags management functions + + + + + + + + + + +
+
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discoverpixy +
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+Functions
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+
Interrupts events and flags management functions
STM32F4xx_StdPeriph_Driver » I2C » I2C_Private_Functions
+
+
+ +

Interrupts, events and flags management functions. +More...

+
+Collaboration diagram for Interrupts events and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint16_t I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
 Reads the specified I2C register and returns its value. More...
 
void I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
 Enables or disables the specified I2C interrupts. More...
 
ErrorStatus I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 Checks whether the last I2Cx Event is equal to the one passed as parameter. More...
 
uint32_t I2C_GetLastEvent (I2C_TypeDef *I2Cx)
 Returns the last I2Cx Event. More...
 
FlagStatus I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Checks whether the specified I2C flag is set or not. More...
 
void I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Clears the I2Cx's pending flags. More...
 
ITStatus I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Checks whether the specified I2C interrupt has occurred or not. More...
 
void I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Clears the I2Cx's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts, events and flags management functions.

+
 ===============================================================================
+          ##### Interrupts, events and flags management functions #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to configure the I2C Interrupts 
+    sources and check or clear the flags or pending bits status.
+    The user should identify which mode will be used in his application to manage 
+    the communication: Polling mode, Interrupt mode or DMA mode. 
+
+
+                ##### I2C State Monitoring Functions #####                   
+ =============================================================================== 
+    [..]  
+    This I2C driver provides three different ways for I2C state monitoring
+    depending on the application requirements and constraints:
+         
+   
+     (#) Basic state monitoring (Using I2C_CheckEvent() function)
+     
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+          (++) When to use
+             (+++) This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
+             (+++) It is also suitable for users who need to define their own events.
+
+          (++) Limitations
+               If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     -@@- For error management, it is advised to use the following functions:
+        (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+        (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+              Where x is the peripheral instance (I2C1, I2C2 ...)
+        (+@@) I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+              I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+        (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+              and/or I2C_GenerateStop() in order to clear the error flag and source 
+              and return to correct  communication status.
+             
+ 
+     (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
+
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          (++) When to use
+             (+++) This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             (+++) The returned value could be compared to events already defined in 
+               the library (stm32f4xx_i2c.h) or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             (+++) At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          (++) Limitations
+             (+++) User may need to define his own events.
+             (+++) Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          (++) When to use
+             (+++) This function could be used for specific applications or in debug 
+               phase.
+             (+++) It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          (++) Limitations: 
+             (+++) When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             (+++) Function may need to be called twice or more in order to monitor 
+               one single event.
+ 
+   For detailed description of Events, please refer to section I2C_Events in 
+   stm32f4xx_i2c.h file.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus I2C_CheckEvent (I2C_TypeDef * I2Cx,
uint32_t I2C_EVENT 
)
+
+ +

Checks whether the last I2Cx Event is equal to the one passed as parameter.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_EVENTspecifies the event to be checked. This parameter can be one of the following values:
    +
  • I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
    • +
  • I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
    • +
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
    • +
  • (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
    • +
  • I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
    • +
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
    • +
  • (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
    • +
  • I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
    • +
  • I2C_EVENT_SLAVE_STOP_DETECTED: EV4
    • +
  • I2C_EVENT_MASTER_MODE_SELECT: EV5
    • +
  • I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
    • +
  • I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
    • +
  • I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
    • +
  • I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
    • +
  • I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
    • +
  • I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
    • +
+
+
+
+
Note
For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: Last event is equal to the I2C_EVENT
    • +
  • ERROR: Last event is different from the I2C_EVENT
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ClearFlag (I2C_TypeDef * I2Cx,
uint32_t I2C_FLAG 
)
+
+ +

Clears the I2Cx's pending flags.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • I2C_FLAG_SMBALERT: SMBus Alert flag
    • +
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_FLAG_PECERR: PEC error in reception flag
    • +
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_FLAG_AF: Acknowledge failure flag
    • +
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_FLAG_BERR: Bus error flag
    • +
+
+
+
+
Note
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+
+ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the second byte of the address in DR register.
+
+BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
+
+ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
+
+SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2C_ClearITPendingBit (I2C_TypeDef * I2Cx,
uint32_t I2C_IT 
)
+
+ +

Clears the I2Cx's interrupt pending bits.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • I2C_IT_SMBALERT: SMBus Alert interrupt
    • +
  • I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
    • +
  • I2C_IT_PECERR: PEC error in reception interrupt
    • +
  • I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
    • +
  • I2C_IT_AF: Acknowledge failure interrupt
    • +
  • I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
    • +
  • I2C_IT_BERR: Bus error interrupt
    • +
+
+
+
+
Note
STOPF (STOP detection) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+
+ADD10 (10-bit header sent) is cleared by software sequence: a read operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second byte of the address in I2C_DR register.
+
+BTF (Byte Transfer Finished) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read/write to I2C_DR register (I2C_SendData()).
+
+ADDR (Address sent) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to I2C_SR2 register ((void)(I2Cx->SR2)).
+
+SB (Start Bit) is cleared by software sequence: a read operation to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to I2C_DR register (I2C_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus I2C_GetFlagStatus (I2C_TypeDef * I2Cx,
uint32_t I2C_FLAG 
)
+
+ +

Checks whether the specified I2C flag is set or not.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • I2C_FLAG_DUALF: Dual flag (Slave mode)
    • +
  • I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
    • +
  • I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
    • +
  • I2C_FLAG_GENCALL: General call header flag (Slave mode)
    • +
  • I2C_FLAG_TRA: Transmitter/Receiver flag
    • +
  • I2C_FLAG_BUSY: Bus busy flag
    • +
  • I2C_FLAG_MSL: Master/Slave flag
    • +
  • I2C_FLAG_SMBALERT: SMBus Alert flag
    • +
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_FLAG_PECERR: PEC error in reception flag
    • +
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_FLAG_AF: Acknowledge failure flag
    • +
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_FLAG_BERR: Bus error flag
    • +
  • I2C_FLAG_TXE: Data register empty flag (Transmitter)
    • +
  • I2C_FLAG_RXNE: Data register not empty (Receiver) flag
    • +
  • I2C_FLAG_STOPF: Stop detection flag (Slave mode)
    • +
  • I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
    • +
  • I2C_FLAG_BTF: Byte transfer finished flag
    • +
  • I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
    • +
  • I2C_FLAG_SB: Start bit flag (Master mode)
    • +
+
+
+
+
Return values
+ + +
Thenew state of I2C_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus I2C_GetITStatus (I2C_TypeDef * I2Cx,
uint32_t I2C_IT 
)
+
+ +

Checks whether the specified I2C interrupt has occurred or not.

+
Parameters
+ + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the interrupt source to check. This parameter can be one of the following values:
    +
  • I2C_IT_SMBALERT: SMBus Alert flag
    • +
  • I2C_IT_TIMEOUT: Timeout or Tlow error flag
    • +
  • I2C_IT_PECERR: PEC error in reception flag
    • +
  • I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
    • +
  • I2C_IT_AF: Acknowledge failure flag
    • +
  • I2C_IT_ARLO: Arbitration lost flag (Master mode)
    • +
  • I2C_IT_BERR: Bus error flag
    • +
  • I2C_IT_TXE: Data register empty flag (Transmitter)
    • +
  • I2C_IT_RXNE: Data register not empty (Receiver) flag
    • +
  • I2C_IT_STOPF: Stop detection flag (Slave mode)
    • +
  • I2C_IT_ADD10: 10-bit header sent flag (Master mode)
    • +
  • I2C_IT_BTF: Byte transfer finished flag
    • +
  • I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched flag (Slave mode)"ENDAD"
    • +
  • I2C_IT_SB: Start bit flag (Master mode)
    • +
+
+
+
+
Return values
+ + +
Thenew state of I2C_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t I2C_GetLastEvent (I2C_TypeDef * I2Cx)
+
+ +

Returns the last I2Cx Event.

+
Parameters
+ + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
+
+
+
Note
For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file.
+
Return values
+ + +
Thelast event
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void I2C_ITConfig (I2C_TypeDef * I2Cx,
uint16_t I2C_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified I2C interrupts.

+
Parameters
+ + + + +
I2Cxwhere x can be 1, 2 or 3 to select the I2C peripheral.
I2C_ITspecifies the I2C interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • I2C_IT_BUF: Buffer interrupt mask
    • +
  • I2C_IT_EVT: Event interrupt mask
    • +
  • I2C_IT_ERR: Error interrupt mask
    • +
+
NewStatenew state of the specified I2C interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t I2C_ReadRegister (I2C_TypeDef * I2Cx,
uint8_t I2C_Register 
)
+
+ +

Reads the specified I2C register and returns its value.

+
Parameters
+ + +
I2C_Registerspecifies the register to read. This parameter can be one of the following values:
    +
  • I2C_Register_CR1: CR1 register.
    • +
  • I2C_Register_CR2: CR2 register.
    • +
  • I2C_Register_OAR1: OAR1 register.
    • +
  • I2C_Register_OAR2: OAR2 register.
    • +
  • I2C_Register_DR: DR register.
    • +
  • I2C_Register_SR1: SR1 register.
    • +
  • I2C_Register_SR2: SR2 register.
    • +
  • I2C_Register_CCR: CCR register.
    • +
  • I2C_Register_TRISE: TRISE register.
    • +
+
+
+
+
Return values
+ + +
Thevalue of the read register.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___group5.map b/group___i2_c___group5.map new file mode 100644 index 0000000..1f205fe --- /dev/null +++ b/group___i2_c___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___group5.md5 b/group___i2_c___group5.md5 new file mode 100644 index 0000000..0763b2b --- /dev/null +++ b/group___i2_c___group5.md5 @@ -0,0 +1 @@ +5c11ec24eb55638a51392f3dee51cc45 \ No newline at end of file diff --git a/group___i2_c___group5.png b/group___i2_c___group5.png new file mode 100644 index 0000000..885f29b Binary files /dev/null and b/group___i2_c___group5.png differ diff --git a/group___i2_c___n_a_c_k__position.html b/group___i2_c___n_a_c_k__position.html new file mode 100644 index 0000000..db4612b --- /dev/null +++ b/group___i2_c___n_a_c_k__position.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_NACK_position + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_NACK_position
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_NACK_position:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_NACKPosition_Next   ((uint16_t)0x0800)
 
+#define I2C_NACKPosition_Current   ((uint16_t)0xF7FF)
 
#define IS_I2C_NACK_POSITION(POSITION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_NACK_POSITION( POSITION)
+
+Value:
(((POSITION) == I2C_NACKPosition_Next) || \
+
((POSITION) == I2C_NACKPosition_Current))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___n_a_c_k__position.map b/group___i2_c___n_a_c_k__position.map new file mode 100644 index 0000000..4ae4175 --- /dev/null +++ b/group___i2_c___n_a_c_k__position.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___n_a_c_k__position.md5 b/group___i2_c___n_a_c_k__position.md5 new file mode 100644 index 0000000..c146ca9 --- /dev/null +++ b/group___i2_c___n_a_c_k__position.md5 @@ -0,0 +1 @@ +282a30e6bd45acea40ed0e782785ede8 \ No newline at end of file diff --git a/group___i2_c___n_a_c_k__position.png b/group___i2_c___n_a_c_k__position.png new file mode 100644 index 0000000..01786ea Binary files /dev/null and b/group___i2_c___n_a_c_k__position.png differ diff --git a/group___i2_c___p_e_c__position.html b/group___i2_c___p_e_c__position.html new file mode 100644 index 0000000..b4da78c --- /dev/null +++ b/group___i2_c___p_e_c__position.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_PEC_position + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_PEC_position
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_PEC_position:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_PECPosition_Next   ((uint16_t)0x0800)
 
+#define I2C_PECPosition_Current   ((uint16_t)0xF7FF)
 
#define IS_I2C_PEC_POSITION(POSITION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_PEC_POSITION( POSITION)
+
+Value:
(((POSITION) == I2C_PECPosition_Next) || \
+
((POSITION) == I2C_PECPosition_Current))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___p_e_c__position.map b/group___i2_c___p_e_c__position.map new file mode 100644 index 0000000..1f0cdce --- /dev/null +++ b/group___i2_c___p_e_c__position.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___p_e_c__position.md5 b/group___i2_c___p_e_c__position.md5 new file mode 100644 index 0000000..af21c85 --- /dev/null +++ b/group___i2_c___p_e_c__position.md5 @@ -0,0 +1 @@ +db5e145cde6f2151b27103c6619d4599 \ No newline at end of file diff --git a/group___i2_c___p_e_c__position.png b/group___i2_c___p_e_c__position.png new file mode 100644 index 0000000..f5f5258 Binary files /dev/null and b/group___i2_c___p_e_c__position.png differ diff --git a/group___i2_c___private___functions.html b/group___i2_c___private___functions.html new file mode 100644 index 0000000..19945d5 --- /dev/null +++ b/group___i2_c___private___functions.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: I2C_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
I2C_Private_Functions
STM32F4xx_StdPeriph_Driver » I2C
+
+
+
+Collaboration diagram for I2C_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Data transfers functions
 Data transfers functions.
 
 PEC management functions
 PEC management functions.
 
 DMA transfers management functions
 DMA transfers management functions.
 
 Interrupts events and flags management functions
 Interrupts, events and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___private___functions.map b/group___i2_c___private___functions.map new file mode 100644 index 0000000..b1318ba --- /dev/null +++ b/group___i2_c___private___functions.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___i2_c___private___functions.md5 b/group___i2_c___private___functions.md5 new file mode 100644 index 0000000..6c09f98 --- /dev/null +++ b/group___i2_c___private___functions.md5 @@ -0,0 +1 @@ +735cb384884f5b08ab6d801dbb9e3c5e \ No newline at end of file diff --git a/group___i2_c___private___functions.png b/group___i2_c___private___functions.png new file mode 100644 index 0000000..d894f4b Binary files /dev/null and b/group___i2_c___private___functions.png differ diff --git a/group___i2_c___s_m_bus__alert__pin__level.html b/group___i2_c___s_m_bus__alert__pin__level.html new file mode 100644 index 0000000..303a125 --- /dev/null +++ b/group___i2_c___s_m_bus__alert__pin__level.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_SMBus_alert_pin_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_SMBus_alert_pin_level
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_SMBus_alert_pin_level:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_SMBusAlert_Low   ((uint16_t)0x2000)
 
+#define I2C_SMBusAlert_High   ((uint16_t)0xDFFF)
 
#define IS_I2C_SMBUS_ALERT(ALERT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_SMBUS_ALERT( ALERT)
+
+Value:
(((ALERT) == I2C_SMBusAlert_Low) || \
+
((ALERT) == I2C_SMBusAlert_High))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c___s_m_bus__alert__pin__level.map b/group___i2_c___s_m_bus__alert__pin__level.map new file mode 100644 index 0000000..0861f54 --- /dev/null +++ b/group___i2_c___s_m_bus__alert__pin__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c___s_m_bus__alert__pin__level.md5 b/group___i2_c___s_m_bus__alert__pin__level.md5 new file mode 100644 index 0000000..4aa1a8b --- /dev/null +++ b/group___i2_c___s_m_bus__alert__pin__level.md5 @@ -0,0 +1 @@ +edaab0a526d4aa05217f4a67d4c474d1 \ No newline at end of file diff --git a/group___i2_c___s_m_bus__alert__pin__level.png b/group___i2_c___s_m_bus__alert__pin__level.png new file mode 100644 index 0000000..b0120a1 Binary files /dev/null and b/group___i2_c___s_m_bus__alert__pin__level.png differ diff --git a/group___i2_c__acknowledged__address.html b/group___i2_c__acknowledged__address.html new file mode 100644 index 0000000..f691f12 --- /dev/null +++ b/group___i2_c__acknowledged__address.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_acknowledged_address + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_acknowledged_address
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_acknowledged_address:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_AcknowledgedAddress_7bit   ((uint16_t)0x4000)
 
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
 
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_ACKNOWLEDGE_ADDRESS( ADDRESS)
+
+Value:
(((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__acknowledged__address.map b/group___i2_c__acknowledged__address.map new file mode 100644 index 0000000..5a32bd2 --- /dev/null +++ b/group___i2_c__acknowledged__address.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__acknowledged__address.md5 b/group___i2_c__acknowledged__address.md5 new file mode 100644 index 0000000..2d1f970 --- /dev/null +++ b/group___i2_c__acknowledged__address.md5 @@ -0,0 +1 @@ +73306bb116443050bb71b00bbce9e079 \ No newline at end of file diff --git a/group___i2_c__acknowledged__address.png b/group___i2_c__acknowledged__address.png new file mode 100644 index 0000000..ddc12c6 Binary files /dev/null and b/group___i2_c__acknowledged__address.png differ diff --git a/group___i2_c__acknowledgement.html b/group___i2_c__acknowledgement.html new file mode 100644 index 0000000..cf1e124 --- /dev/null +++ b/group___i2_c__acknowledgement.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_acknowledgement + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_acknowledgement
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_acknowledgement:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_Ack_Enable   ((uint16_t)0x0400)
 
+#define I2C_Ack_Disable   ((uint16_t)0x0000)
 
#define IS_I2C_ACK_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_ACK_STATE( STATE)
+
+Value:
(((STATE) == I2C_Ack_Enable) || \
+
((STATE) == I2C_Ack_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__acknowledgement.map b/group___i2_c__acknowledgement.map new file mode 100644 index 0000000..9c9d6c5 --- /dev/null +++ b/group___i2_c__acknowledgement.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__acknowledgement.md5 b/group___i2_c__acknowledgement.md5 new file mode 100644 index 0000000..e606373 --- /dev/null +++ b/group___i2_c__acknowledgement.md5 @@ -0,0 +1 @@ +1182d25ad3e7b6c5453bdb887d5c86e4 \ No newline at end of file diff --git a/group___i2_c__acknowledgement.png b/group___i2_c__acknowledgement.png new file mode 100644 index 0000000..e21336a Binary files /dev/null and b/group___i2_c__acknowledgement.png differ diff --git a/group___i2_c__clock__speed.html b/group___i2_c__clock__speed.html new file mode 100644 index 0000000..f06c7d5 --- /dev/null +++ b/group___i2_c__clock__speed.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: I2C_clock_speed + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_clock_speed
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_clock_speed:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_I2C_CLOCK_SPEED(SPEED)   (((SPEED) >= 0x1) && ((SPEED) <= 400000))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__clock__speed.map b/group___i2_c__clock__speed.map new file mode 100644 index 0000000..0499870 --- /dev/null +++ b/group___i2_c__clock__speed.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__clock__speed.md5 b/group___i2_c__clock__speed.md5 new file mode 100644 index 0000000..7057f31 --- /dev/null +++ b/group___i2_c__clock__speed.md5 @@ -0,0 +1 @@ +ba40ba5bb61283faccc965cce27d4d21 \ No newline at end of file diff --git a/group___i2_c__clock__speed.png b/group___i2_c__clock__speed.png new file mode 100644 index 0000000..a6b35db Binary files /dev/null and b/group___i2_c__clock__speed.png differ diff --git a/group___i2_c__duty__cycle__in__fast__mode.html b/group___i2_c__duty__cycle__in__fast__mode.html new file mode 100644 index 0000000..3f473f1 --- /dev/null +++ b/group___i2_c__duty__cycle__in__fast__mode.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: I2C_duty_cycle_in_fast_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_duty_cycle_in_fast_mode
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_duty_cycle_in_fast_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define I2C_DutyCycle_16_9   ((uint16_t)0x4000)
 
#define I2C_DutyCycle_2   ((uint16_t)0xBFFF)
 
#define IS_I2C_DUTY_CYCLE(CYCLE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define I2C_DutyCycle_16_9   ((uint16_t)0x4000)
+
+

I2C fast mode Tlow/Thigh = 16/9

+ +
+
+ +
+
+ + + + +
#define I2C_DutyCycle_2   ((uint16_t)0xBFFF)
+
+

I2C fast mode Tlow/Thigh = 2

+ +
+
+ +
+
+ + + + + + + + +
#define IS_I2C_DUTY_CYCLE( CYCLE)
+
+Value:
(((CYCLE) == I2C_DutyCycle_16_9) || \
+
((CYCLE) == I2C_DutyCycle_2))
+
I2C_DutyCycle_2
#define I2C_DutyCycle_2
Definition: stm32f4xx_i2c.h:115
+
I2C_DutyCycle_16_9
#define I2C_DutyCycle_16_9
Definition: stm32f4xx_i2c.h:114
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__duty__cycle__in__fast__mode.map b/group___i2_c__duty__cycle__in__fast__mode.map new file mode 100644 index 0000000..5933d56 --- /dev/null +++ b/group___i2_c__duty__cycle__in__fast__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__duty__cycle__in__fast__mode.md5 b/group___i2_c__duty__cycle__in__fast__mode.md5 new file mode 100644 index 0000000..c499bcb --- /dev/null +++ b/group___i2_c__duty__cycle__in__fast__mode.md5 @@ -0,0 +1 @@ +3537a03416e98107415b0fb30423fe8f \ No newline at end of file diff --git a/group___i2_c__duty__cycle__in__fast__mode.png b/group___i2_c__duty__cycle__in__fast__mode.png new file mode 100644 index 0000000..158b184 Binary files /dev/null and b/group___i2_c__duty__cycle__in__fast__mode.png differ diff --git a/group___i2_c__flags__definition.html b/group___i2_c__flags__definition.html new file mode 100644 index 0000000..6caca29 --- /dev/null +++ b/group___i2_c__flags__definition.html @@ -0,0 +1,206 @@ + + + + + + +discoverpixy: I2C_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_flags_definition
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_flags_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define I2C_FLAG_DUALF   ((uint32_t)0x00800000)
 SR2 register flags.
 
+#define I2C_FLAG_SMBHOST   ((uint32_t)0x00400000)
 
+#define I2C_FLAG_SMBDEFAULT   ((uint32_t)0x00200000)
 
+#define I2C_FLAG_GENCALL   ((uint32_t)0x00100000)
 
+#define I2C_FLAG_TRA   ((uint32_t)0x00040000)
 
+#define I2C_FLAG_BUSY   ((uint32_t)0x00020000)
 
+#define I2C_FLAG_MSL   ((uint32_t)0x00010000)
 
+#define I2C_FLAG_SMBALERT   ((uint32_t)0x10008000)
 SR1 register flags.
 
+#define I2C_FLAG_TIMEOUT   ((uint32_t)0x10004000)
 
+#define I2C_FLAG_PECERR   ((uint32_t)0x10001000)
 
+#define I2C_FLAG_OVR   ((uint32_t)0x10000800)
 
+#define I2C_FLAG_AF   ((uint32_t)0x10000400)
 
+#define I2C_FLAG_ARLO   ((uint32_t)0x10000200)
 
+#define I2C_FLAG_BERR   ((uint32_t)0x10000100)
 
+#define I2C_FLAG_TXE   ((uint32_t)0x10000080)
 
+#define I2C_FLAG_RXNE   ((uint32_t)0x10000040)
 
+#define I2C_FLAG_STOPF   ((uint32_t)0x10000010)
 
+#define I2C_FLAG_ADD10   ((uint32_t)0x10000008)
 
+#define I2C_FLAG_BTF   ((uint32_t)0x10000004)
 
+#define I2C_FLAG_ADDR   ((uint32_t)0x10000002)
 
+#define I2C_FLAG_SB   ((uint32_t)0x10000001)
 
+#define IS_I2C_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
#define IS_I2C_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+
((FLAG) == I2C_FLAG_SB))
+
I2C_FLAG_SMBALERT
#define I2C_FLAG_SMBALERT
SR1 register flags.
Definition: stm32f4xx_i2c.h:284
+
I2C_FLAG_DUALF
#define I2C_FLAG_DUALF
SR2 register flags.
Definition: stm32f4xx_i2c.h:272
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__flags__definition.map b/group___i2_c__flags__definition.map new file mode 100644 index 0000000..d9c5e5c --- /dev/null +++ b/group___i2_c__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__flags__definition.md5 b/group___i2_c__flags__definition.md5 new file mode 100644 index 0000000..8e74d82 --- /dev/null +++ b/group___i2_c__flags__definition.md5 @@ -0,0 +1 @@ +c77ed1346c1f95f9947a1b11159db186 \ No newline at end of file diff --git a/group___i2_c__flags__definition.png b/group___i2_c__flags__definition.png new file mode 100644 index 0000000..68fdb9f Binary files /dev/null and b/group___i2_c__flags__definition.png differ diff --git a/group___i2_c__interrupts__definition.html b/group___i2_c__interrupts__definition.html new file mode 100644 index 0000000..2f6a6fa --- /dev/null +++ b/group___i2_c__interrupts__definition.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: I2C_interrupts_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
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+ +
+
+Macros
+
+
I2C_interrupts_definition
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_interrupts_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define I2C_IT_BUF   ((uint16_t)0x0400)
 
+#define I2C_IT_EVT   ((uint16_t)0x0200)
 
+#define I2C_IT_ERR   ((uint16_t)0x0100)
 
+#define IS_I2C_CONFIG_IT(IT)   ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
 
+#define I2C_IT_SMBALERT   ((uint32_t)0x01008000)
 
+#define I2C_IT_TIMEOUT   ((uint32_t)0x01004000)
 
+#define I2C_IT_PECERR   ((uint32_t)0x01001000)
 
+#define I2C_IT_OVR   ((uint32_t)0x01000800)
 
+#define I2C_IT_AF   ((uint32_t)0x01000400)
 
+#define I2C_IT_ARLO   ((uint32_t)0x01000200)
 
+#define I2C_IT_BERR   ((uint32_t)0x01000100)
 
+#define I2C_IT_TXE   ((uint32_t)0x06000080)
 
+#define I2C_IT_RXNE   ((uint32_t)0x06000040)
 
+#define I2C_IT_STOPF   ((uint32_t)0x02000010)
 
+#define I2C_IT_ADD10   ((uint32_t)0x02000008)
 
+#define I2C_IT_BTF   ((uint32_t)0x02000004)
 
+#define I2C_IT_ADDR   ((uint32_t)0x02000002)
 
+#define I2C_IT_SB   ((uint32_t)0x02000001)
 
+#define IS_I2C_CLEAR_IT(IT)   ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
 
#define IS_I2C_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_GET_IT( IT)
+
+Value:
(((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__interrupts__definition.map b/group___i2_c__interrupts__definition.map new file mode 100644 index 0000000..ed9171b --- /dev/null +++ b/group___i2_c__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__interrupts__definition.md5 b/group___i2_c__interrupts__definition.md5 new file mode 100644 index 0000000..e56db76 --- /dev/null +++ b/group___i2_c__interrupts__definition.md5 @@ -0,0 +1 @@ +5d350dc205e2ff90df53462eb98a1149 \ No newline at end of file diff --git a/group___i2_c__interrupts__definition.png b/group___i2_c__interrupts__definition.png new file mode 100644 index 0000000..ec48efc Binary files /dev/null and b/group___i2_c__interrupts__definition.png differ diff --git a/group___i2_c__mode.html b/group___i2_c__mode.html new file mode 100644 index 0000000..ff4cc01 --- /dev/null +++ b/group___i2_c__mode.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: I2C_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_mode
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_mode:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define I2C_Mode_I2C   ((uint16_t)0x0000)
 
+#define I2C_Mode_SMBusDevice   ((uint16_t)0x0002)
 
+#define I2C_Mode_SMBusHost   ((uint16_t)0x000A)
 
#define IS_I2C_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_MODE( MODE)
+
+Value:
(((MODE) == I2C_Mode_I2C) || \
+
((MODE) == I2C_Mode_SMBusDevice) || \
+
((MODE) == I2C_Mode_SMBusHost))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__mode.map b/group___i2_c__mode.map new file mode 100644 index 0000000..7ad4437 --- /dev/null +++ b/group___i2_c__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__mode.md5 b/group___i2_c__mode.md5 new file mode 100644 index 0000000..c076955 --- /dev/null +++ b/group___i2_c__mode.md5 @@ -0,0 +1 @@ +3578f56a8cfaac1afb96b06a93ae5198 \ No newline at end of file diff --git a/group___i2_c__mode.png b/group___i2_c__mode.png new file mode 100644 index 0000000..9c2814e Binary files /dev/null and b/group___i2_c__mode.png differ diff --git a/group___i2_c__own__address1.html b/group___i2_c__own__address1.html new file mode 100644 index 0000000..1727721 --- /dev/null +++ b/group___i2_c__own__address1.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: I2C_own_address1 + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_own_address1
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_own_address1:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= 0x3FF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__own__address1.map b/group___i2_c__own__address1.map new file mode 100644 index 0000000..531208b --- /dev/null +++ b/group___i2_c__own__address1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__own__address1.md5 b/group___i2_c__own__address1.md5 new file mode 100644 index 0000000..183d7ad --- /dev/null +++ b/group___i2_c__own__address1.md5 @@ -0,0 +1 @@ +3e714e35952815494e3f2bbbdbc9f03a \ No newline at end of file diff --git a/group___i2_c__own__address1.png b/group___i2_c__own__address1.png new file mode 100644 index 0000000..e7dc77d Binary files /dev/null and b/group___i2_c__own__address1.png differ diff --git a/group___i2_c__registers.html b/group___i2_c__registers.html new file mode 100644 index 0000000..b87981d --- /dev/null +++ b/group___i2_c__registers.html @@ -0,0 +1,161 @@ + + + + + + +discoverpixy: I2C_registers + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_registers
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_registers:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define I2C_Register_CR1   ((uint8_t)0x00)
 
+#define I2C_Register_CR2   ((uint8_t)0x04)
 
+#define I2C_Register_OAR1   ((uint8_t)0x08)
 
+#define I2C_Register_OAR2   ((uint8_t)0x0C)
 
+#define I2C_Register_DR   ((uint8_t)0x10)
 
+#define I2C_Register_SR1   ((uint8_t)0x14)
 
+#define I2C_Register_SR2   ((uint8_t)0x18)
 
+#define I2C_Register_CCR   ((uint8_t)0x1C)
 
+#define I2C_Register_TRISE   ((uint8_t)0x20)
 
#define IS_I2C_REGISTER(REGISTER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_REGISTER( REGISTER)
+
+Value:
(((REGISTER) == I2C_Register_CR1) || \
+
((REGISTER) == I2C_Register_CR2) || \
+
((REGISTER) == I2C_Register_OAR1) || \
+
((REGISTER) == I2C_Register_OAR2) || \
+
((REGISTER) == I2C_Register_DR) || \
+
((REGISTER) == I2C_Register_SR1) || \
+
((REGISTER) == I2C_Register_SR2) || \
+
((REGISTER) == I2C_Register_CCR) || \
+
((REGISTER) == I2C_Register_TRISE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__registers.map b/group___i2_c__registers.map new file mode 100644 index 0000000..3924672 --- /dev/null +++ b/group___i2_c__registers.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__registers.md5 b/group___i2_c__registers.md5 new file mode 100644 index 0000000..59fc382 --- /dev/null +++ b/group___i2_c__registers.md5 @@ -0,0 +1 @@ +d222a5ea610396ba8cfc4be00c15685d \ No newline at end of file diff --git a/group___i2_c__registers.png b/group___i2_c__registers.png new file mode 100644 index 0000000..209d3ba Binary files /dev/null and b/group___i2_c__registers.png differ diff --git a/group___i2_c__transfer__direction.html b/group___i2_c__transfer__direction.html new file mode 100644 index 0000000..9e5f64b --- /dev/null +++ b/group___i2_c__transfer__direction.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: I2C_transfer_direction + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
I2C_transfer_direction
STM32F4xx_StdPeriph_Driver » I2C » I2C_Exported_Constants
+
+
+
+Collaboration diagram for I2C_transfer_direction:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2C_Direction_Transmitter   ((uint8_t)0x00)
 
+#define I2C_Direction_Receiver   ((uint8_t)0x01)
 
#define IS_I2C_DIRECTION(DIRECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2C_DIRECTION( DIRECTION)
+
+Value:
(((DIRECTION) == I2C_Direction_Transmitter) || \
+
((DIRECTION) == I2C_Direction_Receiver))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i2_c__transfer__direction.map b/group___i2_c__transfer__direction.map new file mode 100644 index 0000000..7df8ea7 --- /dev/null +++ b/group___i2_c__transfer__direction.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c__transfer__direction.md5 b/group___i2_c__transfer__direction.md5 new file mode 100644 index 0000000..ed0c1c8 --- /dev/null +++ b/group___i2_c__transfer__direction.md5 @@ -0,0 +1 @@ +f48a27b0770a251c264033acf60e452f \ No newline at end of file diff --git a/group___i2_c__transfer__direction.png b/group___i2_c__transfer__direction.png new file mode 100644 index 0000000..862c3ee Binary files /dev/null and b/group___i2_c__transfer__direction.png differ diff --git a/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map new file mode 100644 index 0000000..f89c54e --- /dev/null +++ b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 new file mode 100644 index 0000000..d7b9411 --- /dev/null +++ b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.md5 @@ -0,0 +1 @@ +516b1e77d556fa82602c8bbc36721e98 \ No newline at end of file diff --git a/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png new file mode 100644 index 0000000..a43905c Binary files /dev/null and b/group___i2_c_ga2ee214364603059ad5d9089f749f5bfd_cgraph.png differ diff --git a/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map new file mode 100644 index 0000000..99b289d --- /dev/null +++ b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 new file mode 100644 index 0000000..46d36ba --- /dev/null +++ b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.md5 @@ -0,0 +1 @@ +f540da808c02942412bab6e4ecca9e6e \ No newline at end of file diff --git a/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png new file mode 100644 index 0000000..bef5362 Binary files /dev/null and b/group___i2_c_gaac29465bca70fbc91c2f922ab67bb88e_cgraph.png differ diff --git a/group___i_w_d_g.html b/group___i_w_d_g.html new file mode 100644 index 0000000..9ef21b4 --- /dev/null +++ b/group___i_w_d_g.html @@ -0,0 +1,344 @@ + + + + + + +discoverpixy: IWDG + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros | +Functions
+
+
IWDG
STM32F4xx_StdPeriph_Driver
+
+
+ +

IWDG driver modules. +More...

+
+Collaboration diagram for IWDG:
+
+
+ + +
+
+ + + + + + +

+Modules

 IWDG_Exported_Constants
 
 IWDG_Private_Functions
 
+ + + + + +

+Macros

+#define KR_KEY_RELOAD   ((uint16_t)0xAAAA)
 
+#define KR_KEY_ENABLE   ((uint16_t)0xCCCC)
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
 Enables or disables write access to IWDG_PR and IWDG_RLR registers. More...
 
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
 Sets IWDG Prescaler value. More...
 
void IWDG_SetReload (uint16_t Reload)
 Sets IWDG Reload value. More...
 
void IWDG_ReloadCounter (void)
 Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
void IWDG_Enable (void)
 Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
 Checks whether the specified IWDG flag is set or not. More...
 
+

Detailed Description

+

IWDG driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void IWDG_Enable (void )
+
+ +

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
+
+ +

Checks whether the specified IWDG flag is set or not.

+
Parameters
+ + +
IWDG_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • IWDG_FLAG_PVU: Prescaler Value Update on going
    • +
  • IWDG_FLAG_RVU: Reload Value Update on going
    • +
+
+
+
+
Return values
+ + +
Thenew state of IWDG_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_ReloadCounter (void )
+
+ +

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
+
+ +

Sets IWDG Prescaler value.

+
Parameters
+ + +
IWDG_Prescalerspecifies the IWDG Prescaler value. This parameter can be one of the following values:
    +
  • IWDG_Prescaler_4: IWDG prescaler set to 4
    • +
  • IWDG_Prescaler_8: IWDG prescaler set to 8
    • +
  • IWDG_Prescaler_16: IWDG prescaler set to 16
    • +
  • IWDG_Prescaler_32: IWDG prescaler set to 32
    • +
  • IWDG_Prescaler_64: IWDG prescaler set to 64
    • +
  • IWDG_Prescaler_128: IWDG prescaler set to 128
    • +
  • IWDG_Prescaler_256: IWDG prescaler set to 256
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_SetReload (uint16_t Reload)
+
+ +

Sets IWDG Reload value.

+
Parameters
+ + +
Reloadspecifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
+
+ +

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

+
Parameters
+ + +
IWDG_WriteAccessnew state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:
    +
  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
    • +
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g.map b/group___i_w_d_g.map new file mode 100644 index 0000000..833d5b3 --- /dev/null +++ b/group___i_w_d_g.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___i_w_d_g.md5 b/group___i_w_d_g.md5 new file mode 100644 index 0000000..0f0e246 --- /dev/null +++ b/group___i_w_d_g.md5 @@ -0,0 +1 @@ +35cfa687c270e164ec8e330e3c4b77df \ No newline at end of file diff --git a/group___i_w_d_g.png b/group___i_w_d_g.png new file mode 100644 index 0000000..6da0d11 Binary files /dev/null and b/group___i_w_d_g.png differ diff --git a/group___i_w_d_g___exported___constants.html b/group___i_w_d_g___exported___constants.html new file mode 100644 index 0000000..caca29f --- /dev/null +++ b/group___i_w_d_g___exported___constants.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: IWDG_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
IWDG_Exported_Constants
STM32F4xx_StdPeriph_Driver » IWDG
+
+
+
+Collaboration diagram for IWDG_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + +

+Modules

 IWDG_WriteAccess
 
 IWDG_prescaler
 
 IWDG_Flag
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___exported___constants.map b/group___i_w_d_g___exported___constants.map new file mode 100644 index 0000000..a8d9d5b --- /dev/null +++ b/group___i_w_d_g___exported___constants.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___i_w_d_g___exported___constants.md5 b/group___i_w_d_g___exported___constants.md5 new file mode 100644 index 0000000..fc1101e --- /dev/null +++ b/group___i_w_d_g___exported___constants.md5 @@ -0,0 +1 @@ +1442e0aa57b46c85a54f663988322d15 \ No newline at end of file diff --git a/group___i_w_d_g___exported___constants.png b/group___i_w_d_g___exported___constants.png new file mode 100644 index 0000000..bcd8fdb Binary files /dev/null and b/group___i_w_d_g___exported___constants.png differ diff --git a/group___i_w_d_g___flag.html b/group___i_w_d_g___flag.html new file mode 100644 index 0000000..4ac64c7 --- /dev/null +++ b/group___i_w_d_g___flag.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: IWDG_Flag + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
IWDG_Flag
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Exported_Constants
+
+
+
+Collaboration diagram for IWDG_Flag:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define IWDG_FLAG_PVU   ((uint16_t)0x0001)
 
+#define IWDG_FLAG_RVU   ((uint16_t)0x0002)
 
+#define IS_IWDG_FLAG(FLAG)   (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
 
+#define IS_IWDG_RELOAD(RELOAD)   ((RELOAD) <= 0xFFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___flag.map b/group___i_w_d_g___flag.map new file mode 100644 index 0000000..95abb24 --- /dev/null +++ b/group___i_w_d_g___flag.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g___flag.md5 b/group___i_w_d_g___flag.md5 new file mode 100644 index 0000000..81ddd42 --- /dev/null +++ b/group___i_w_d_g___flag.md5 @@ -0,0 +1 @@ +dd15a5fa481cb7cfb21f00d5e3263996 \ No newline at end of file diff --git a/group___i_w_d_g___flag.png b/group___i_w_d_g___flag.png new file mode 100644 index 0000000..d611130 Binary files /dev/null and b/group___i_w_d_g___flag.png differ diff --git a/group___i_w_d_g___group1.html b/group___i_w_d_g___group1.html new file mode 100644 index 0000000..f140a9c --- /dev/null +++ b/group___i_w_d_g___group1.html @@ -0,0 +1,258 @@ + + + + + + +discoverpixy: Prescaler and Counter configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Prescaler and Counter configuration functions
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Private_Functions
+
+
+ +

Prescaler and Counter configuration functions. +More...

+
+Collaboration diagram for Prescaler and Counter configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
 Enables or disables write access to IWDG_PR and IWDG_RLR registers. More...
 
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
 Sets IWDG Prescaler value. More...
 
void IWDG_SetReload (uint16_t Reload)
 Sets IWDG Reload value. More...
 
void IWDG_ReloadCounter (void)
 Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
+

Detailed Description

+

Prescaler and Counter configuration functions.

+
 ===============================================================================
+              ##### Prescaler and Counter configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void IWDG_ReloadCounter (void )
+
+ +

Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
+
+ +

Sets IWDG Prescaler value.

+
Parameters
+ + +
IWDG_Prescalerspecifies the IWDG Prescaler value. This parameter can be one of the following values:
    +
  • IWDG_Prescaler_4: IWDG prescaler set to 4
    • +
  • IWDG_Prescaler_8: IWDG prescaler set to 8
    • +
  • IWDG_Prescaler_16: IWDG prescaler set to 16
    • +
  • IWDG_Prescaler_32: IWDG prescaler set to 32
    • +
  • IWDG_Prescaler_64: IWDG prescaler set to 64
    • +
  • IWDG_Prescaler_128: IWDG prescaler set to 128
    • +
  • IWDG_Prescaler_256: IWDG prescaler set to 256
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_SetReload (uint16_t Reload)
+
+ +

Sets IWDG Reload value.

+
Parameters
+ + +
Reloadspecifies the IWDG Reload value. This parameter must be a number between 0 and 0x0FFF.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
+
+ +

Enables or disables write access to IWDG_PR and IWDG_RLR registers.

+
Parameters
+ + +
IWDG_WriteAccessnew state of write access to IWDG_PR and IWDG_RLR registers. This parameter can be one of the following values:
    +
  • IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
    • +
  • IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___group1.map b/group___i_w_d_g___group1.map new file mode 100644 index 0000000..22226e3 --- /dev/null +++ b/group___i_w_d_g___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g___group1.md5 b/group___i_w_d_g___group1.md5 new file mode 100644 index 0000000..14e4276 --- /dev/null +++ b/group___i_w_d_g___group1.md5 @@ -0,0 +1 @@ +043d828daf314c7f866d9ce1ac713059 \ No newline at end of file diff --git a/group___i_w_d_g___group1.png b/group___i_w_d_g___group1.png new file mode 100644 index 0000000..9bcc94a Binary files /dev/null and b/group___i_w_d_g___group1.png differ diff --git a/group___i_w_d_g___group2.html b/group___i_w_d_g___group2.html new file mode 100644 index 0000000..579a8bd --- /dev/null +++ b/group___i_w_d_g___group2.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: IWDG activation function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
IWDG activation function
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Private_Functions
+
+
+ +

IWDG activation function. +More...

+
+Collaboration diagram for IWDG activation function:
+
+
+ + +
+
+ + + + + +

+Functions

void IWDG_Enable (void)
 Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
+

Detailed Description

+

IWDG activation function.

+
 ===============================================================================
+                    ##### IWDG activation function #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void IWDG_Enable (void )
+
+ +

Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___group2.map b/group___i_w_d_g___group2.map new file mode 100644 index 0000000..c2c5840 --- /dev/null +++ b/group___i_w_d_g___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g___group2.md5 b/group___i_w_d_g___group2.md5 new file mode 100644 index 0000000..3388000 --- /dev/null +++ b/group___i_w_d_g___group2.md5 @@ -0,0 +1 @@ +4678dbea39ca5129a92ef84218c86377 \ No newline at end of file diff --git a/group___i_w_d_g___group2.png b/group___i_w_d_g___group2.png new file mode 100644 index 0000000..665e701 Binary files /dev/null and b/group___i_w_d_g___group2.png differ diff --git a/group___i_w_d_g___group3.html b/group___i_w_d_g___group3.html new file mode 100644 index 0000000..0430a15 --- /dev/null +++ b/group___i_w_d_g___group3.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: Flag management function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Flag management function
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Private_Functions
+
+
+ +

Flag management function. +More...

+
+Collaboration diagram for Flag management function:
+
+
+ + +
+
+ + + + + +

+Functions

FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
 Checks whether the specified IWDG flag is set or not. More...
 
+

Detailed Description

+

Flag management function.

+
 ===============================================================================
+                    ##### Flag management function #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
+
+ +

Checks whether the specified IWDG flag is set or not.

+
Parameters
+ + +
IWDG_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • IWDG_FLAG_PVU: Prescaler Value Update on going
    • +
  • IWDG_FLAG_RVU: Reload Value Update on going
    • +
+
+
+
+
Return values
+ + +
Thenew state of IWDG_FLAG (SET or RESET).
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___group3.map b/group___i_w_d_g___group3.map new file mode 100644 index 0000000..e5a48e3 --- /dev/null +++ b/group___i_w_d_g___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g___group3.md5 b/group___i_w_d_g___group3.md5 new file mode 100644 index 0000000..feb06bc --- /dev/null +++ b/group___i_w_d_g___group3.md5 @@ -0,0 +1 @@ +f36578bf69183d394d0c4de8b2649cf3 \ No newline at end of file diff --git a/group___i_w_d_g___group3.png b/group___i_w_d_g___group3.png new file mode 100644 index 0000000..7c34550 Binary files /dev/null and b/group___i_w_d_g___group3.png differ diff --git a/group___i_w_d_g___private___functions.html b/group___i_w_d_g___private___functions.html new file mode 100644 index 0000000..48643d8 --- /dev/null +++ b/group___i_w_d_g___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: IWDG_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
IWDG_Private_Functions
STM32F4xx_StdPeriph_Driver » IWDG
+
+
+
+Collaboration diagram for IWDG_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 Prescaler and Counter configuration functions
 Prescaler and Counter configuration functions.
 
 IWDG activation function
 IWDG activation function.
 
 Flag management function
 Flag management function.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___private___functions.map b/group___i_w_d_g___private___functions.map new file mode 100644 index 0000000..20409d5 --- /dev/null +++ b/group___i_w_d_g___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___i_w_d_g___private___functions.md5 b/group___i_w_d_g___private___functions.md5 new file mode 100644 index 0000000..56b3cb3 --- /dev/null +++ b/group___i_w_d_g___private___functions.md5 @@ -0,0 +1 @@ +bdd8256d5f5475dfed6ee776de197828 \ No newline at end of file diff --git a/group___i_w_d_g___private___functions.png b/group___i_w_d_g___private___functions.png new file mode 100644 index 0000000..76eb7b2 Binary files /dev/null and b/group___i_w_d_g___private___functions.png differ diff --git a/group___i_w_d_g___write_access.html b/group___i_w_d_g___write_access.html new file mode 100644 index 0000000..54bf0fa --- /dev/null +++ b/group___i_w_d_g___write_access.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: IWDG_WriteAccess + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
IWDG_WriteAccess
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Exported_Constants
+
+
+
+Collaboration diagram for IWDG_WriteAccess:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define IWDG_WriteAccess_Enable   ((uint16_t)0x5555)
 
+#define IWDG_WriteAccess_Disable   ((uint16_t)0x0000)
 
#define IS_IWDG_WRITE_ACCESS(ACCESS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_IWDG_WRITE_ACCESS( ACCESS)
+
+Value:
(((ACCESS) == IWDG_WriteAccess_Enable) || \
+
((ACCESS) == IWDG_WriteAccess_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g___write_access.map b/group___i_w_d_g___write_access.map new file mode 100644 index 0000000..91e34c1 --- /dev/null +++ b/group___i_w_d_g___write_access.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g___write_access.md5 b/group___i_w_d_g___write_access.md5 new file mode 100644 index 0000000..1f173d7 --- /dev/null +++ b/group___i_w_d_g___write_access.md5 @@ -0,0 +1 @@ +fd78c51405cd0984b5f748f855484d65 \ No newline at end of file diff --git a/group___i_w_d_g___write_access.png b/group___i_w_d_g___write_access.png new file mode 100644 index 0000000..22283c3 Binary files /dev/null and b/group___i_w_d_g___write_access.png differ diff --git a/group___i_w_d_g__prescaler.html b/group___i_w_d_g__prescaler.html new file mode 100644 index 0000000..80d0d6f --- /dev/null +++ b/group___i_w_d_g__prescaler.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: IWDG_prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
IWDG_prescaler
STM32F4xx_StdPeriph_Driver » IWDG » IWDG_Exported_Constants
+
+
+
+Collaboration diagram for IWDG_prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define IWDG_Prescaler_4   ((uint8_t)0x00)
 
+#define IWDG_Prescaler_8   ((uint8_t)0x01)
 
+#define IWDG_Prescaler_16   ((uint8_t)0x02)
 
+#define IWDG_Prescaler_32   ((uint8_t)0x03)
 
+#define IWDG_Prescaler_64   ((uint8_t)0x04)
 
+#define IWDG_Prescaler_128   ((uint8_t)0x05)
 
+#define IWDG_Prescaler_256   ((uint8_t)0x06)
 
#define IS_IWDG_PRESCALER(PRESCALER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_IWDG_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == IWDG_Prescaler_4) || \
+
((PRESCALER) == IWDG_Prescaler_8) || \
+
((PRESCALER) == IWDG_Prescaler_16) || \
+
((PRESCALER) == IWDG_Prescaler_32) || \
+
((PRESCALER) == IWDG_Prescaler_64) || \
+
((PRESCALER) == IWDG_Prescaler_128)|| \
+
((PRESCALER) == IWDG_Prescaler_256))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___i_w_d_g__prescaler.map b/group___i_w_d_g__prescaler.map new file mode 100644 index 0000000..d381ac0 --- /dev/null +++ b/group___i_w_d_g__prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___i_w_d_g__prescaler.md5 b/group___i_w_d_g__prescaler.md5 new file mode 100644 index 0000000..f0c367c --- /dev/null +++ b/group___i_w_d_g__prescaler.md5 @@ -0,0 +1 @@ +ae42a657d0aab842360779fec5584593 \ No newline at end of file diff --git a/group___i_w_d_g__prescaler.png b/group___i_w_d_g__prescaler.png new file mode 100644 index 0000000..b7374e1 Binary files /dev/null and b/group___i_w_d_g__prescaler.png differ diff --git a/group___internal___macro.html b/group___internal___macro.html new file mode 100644 index 0000000..b93ae80 --- /dev/null +++ b/group___internal___macro.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: 's + + + + + + + + + + +
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discoverpixy +
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+Macros | +Enumerations
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's
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for 's:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USB_OTG_READ_REG32(reg)   (*(__IO uint32_t *)reg)
 
+#define USB_OTG_WRITE_REG32(reg, value)   (*(__IO uint32_t *)reg = value)
 
+#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)   USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
 
+ + + +

+Enumerations

enum  USB_OTG_SPEED { USB_SPEED_UNKNOWN = 0, +USB_SPEED_LOW, +USB_SPEED_FULL, +USB_SPEED_HIGH + }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___internal___macro.map b/group___internal___macro.map new file mode 100644 index 0000000..d114e09 --- /dev/null +++ b/group___internal___macro.map @@ -0,0 +1,3 @@ + + + diff --git a/group___internal___macro.md5 b/group___internal___macro.md5 new file mode 100644 index 0000000..6066759 --- /dev/null +++ b/group___internal___macro.md5 @@ -0,0 +1 @@ +6de191a404291ef6448bcb9bb3563d34 \ No newline at end of file diff --git a/group___internal___macro.png b/group___internal___macro.png new file mode 100644 index 0000000..c42a54b Binary files /dev/null and b/group___internal___macro.png differ diff --git a/group___l_t_d_c.html b/group___l_t_d_c.html new file mode 100644 index 0000000..641a472 --- /dev/null +++ b/group___l_t_d_c.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: LTDC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Macros
+
+
LTDC
STM32F4xx_StdPeriph_Driver
+
+
+ +

LTDC driver modules. +More...

+
+Collaboration diagram for LTDC:
+
+
+ + +
+
+ + + + + + +

+Modules

 LTDC_Exported_Constants
 
 LTDC_Private_Functions
 
+ + + + + + + + + + + + + + + + +

+Classes

struct  LTDC_InitTypeDef
 LTDC Init structure definition. More...
 
struct  LTDC_Layer_InitTypeDef
 LTDC Layer structure definition. More...
 
struct  LTDC_PosTypeDef
 LTDC Position structure definition. More...
 
struct  LTDC_RGBTypeDef
 
struct  LTDC_ColorKeying_InitTypeDef
 
struct  LTDC_CLUT_InitTypeDef
 
+ + + +

+Macros

+#define GCR_MASK   ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */
 
+

Detailed Description

+

LTDC driver modules.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c.map b/group___l_t_d_c.map new file mode 100644 index 0000000..bc396e5 --- /dev/null +++ b/group___l_t_d_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___l_t_d_c.md5 b/group___l_t_d_c.md5 new file mode 100644 index 0000000..f4867a7 --- /dev/null +++ b/group___l_t_d_c.md5 @@ -0,0 +1 @@ +e0a5acef349e648e583f7e12e257f8d5 \ No newline at end of file diff --git a/group___l_t_d_c.png b/group___l_t_d_c.png new file mode 100644 index 0000000..1341adc Binary files /dev/null and b/group___l_t_d_c.png differ diff --git a/group___l_t_d_c___back___color.html b/group___l_t_d_c___back___color.html new file mode 100644 index 0000000..da98b2e --- /dev/null +++ b/group___l_t_d_c___back___color.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: LTDC_Back_Color + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Back_Color
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Back_Color:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define LTDC_Back_Color   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_BackBlueValue(BBLUE)   ((BBLUE) <= LTDC_Back_Color)
 
+#define IS_LTDC_BackGreenValue(BGREEN)   ((BGREEN) <= LTDC_Back_Color)
 
+#define IS_LTDC_BackRedValue(BRED)   ((BRED) <= LTDC_Back_Color)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___back___color.map b/group___l_t_d_c___back___color.map new file mode 100644 index 0000000..da51dbd --- /dev/null +++ b/group___l_t_d_c___back___color.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___back___color.md5 b/group___l_t_d_c___back___color.md5 new file mode 100644 index 0000000..803c9b4 --- /dev/null +++ b/group___l_t_d_c___back___color.md5 @@ -0,0 +1 @@ +003246ee0ebe658efbc443ab354e51c6 \ No newline at end of file diff --git a/group___l_t_d_c___back___color.png b/group___l_t_d_c___back___color.png new file mode 100644 index 0000000..7dc6fc2 Binary files /dev/null and b/group___l_t_d_c___back___color.png differ diff --git a/group___l_t_d_c___blending_factor1.html b/group___l_t_d_c___blending_factor1.html new file mode 100644 index 0000000..36baeba --- /dev/null +++ b/group___l_t_d_c___blending_factor1.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: LTDC_BlendingFactor1 + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_BlendingFactor1
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_BlendingFactor1:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define LTDC_BlendingFactor1_CA   ((uint32_t)0x00000400)
 
+#define LTDC_BlendingFactor1_PAxCA   ((uint32_t)0x00000600)
 
+#define IS_LTDC_BlendingFactor1(BlendingFactor1)   (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___blending_factor1.map b/group___l_t_d_c___blending_factor1.map new file mode 100644 index 0000000..7157ed3 --- /dev/null +++ b/group___l_t_d_c___blending_factor1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___blending_factor1.md5 b/group___l_t_d_c___blending_factor1.md5 new file mode 100644 index 0000000..cd06b9d --- /dev/null +++ b/group___l_t_d_c___blending_factor1.md5 @@ -0,0 +1 @@ +1445291d556a889038e39ed9ee0fdb85 \ No newline at end of file diff --git a/group___l_t_d_c___blending_factor1.png b/group___l_t_d_c___blending_factor1.png new file mode 100644 index 0000000..d156f4f Binary files /dev/null and b/group___l_t_d_c___blending_factor1.png differ diff --git a/group___l_t_d_c___blending_factor2.html b/group___l_t_d_c___blending_factor2.html new file mode 100644 index 0000000..a95b686 --- /dev/null +++ b/group___l_t_d_c___blending_factor2.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: LTDC_BlendingFactor2 + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_BlendingFactor2
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_BlendingFactor2:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define LTDC_BlendingFactor2_CA   ((uint32_t)0x00000005)
 
+#define LTDC_BlendingFactor2_PAxCA   ((uint32_t)0x00000007)
 
+#define IS_LTDC_BlendingFactor2(BlendingFactor2)   (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___blending_factor2.map b/group___l_t_d_c___blending_factor2.map new file mode 100644 index 0000000..781b5a4 --- /dev/null +++ b/group___l_t_d_c___blending_factor2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___blending_factor2.md5 b/group___l_t_d_c___blending_factor2.md5 new file mode 100644 index 0000000..1c1ef6b --- /dev/null +++ b/group___l_t_d_c___blending_factor2.md5 @@ -0,0 +1 @@ +e9ee3a82f857f952331329ed6484ed7c \ No newline at end of file diff --git a/group___l_t_d_c___blending_factor2.png b/group___l_t_d_c___blending_factor2.png new file mode 100644 index 0000000..81dea52 Binary files /dev/null and b/group___l_t_d_c___blending_factor2.png differ diff --git a/group___l_t_d_c___c_l_u_t___config.html b/group___l_t_d_c___c_l_u_t___config.html new file mode 100644 index 0000000..a4de4d5 --- /dev/null +++ b/group___l_t_d_c___c_l_u_t___config.html @@ -0,0 +1,1325 @@ + + + + + + +discoverpixy: LTDC_CLUT_Config + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Functions
+
+
LTDC_CLUT_Config
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_CLUT_Config:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LTDC_CLUTWR   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_CLUTWR(CLUTWR)   ((CLUTWR) <= LTDC_CLUTWR)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LTDC_DeInit (void)
 Deinitializes the LTDC peripheral registers to their default reset values. More...
 
void LTDC_Init (LTDC_InitTypeDef *LTDC_InitStruct)
 Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct. More...
 
void LTDC_StructInit (LTDC_InitTypeDef *LTDC_InitStruct)
 Fills each LTDC_InitStruct member with its default value. More...
 
void LTDC_Cmd (FunctionalState NewState)
 Enables or disables the LTDC Controller. More...
 
void LTDC_DitherCmd (FunctionalState NewState)
 Enables or disables Dither. More...
 
LTDC_RGBTypeDef LTDC_GetRGBWidth (void)
 Get the dither RGB width. More...
 
void LTDC_RGBStructInit (LTDC_RGBTypeDef *LTDC_RGB_InitStruct)
 Fills each LTDC_RGBStruct member with its default value. More...
 
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
 Define the position of the line interrupt . More...
 
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
 reload layers registers with new parameters More...
 
void LTDC_LayerInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct. More...
 
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Fills each LTDC_Layer_InitStruct member with its default value. More...
 
void LTDC_LayerCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables the LTDC_Layer Controller. More...
 
LTDC_PosTypeDef LTDC_GetPosStatus (void)
 Get the current position. More...
 
void LTDC_PosStructInit (LTDC_PosTypeDef *LTDC_Pos_InitStruct)
 Fills each LTDC_Pos_InitStruct member with its default value. More...
 
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct, FunctionalState NewState)
 Set and configure the color keying. More...
 
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct)
 Fills each LTDC_colorkeying_InitStruct member with its default value. More...
 
void LTDC_CLUTCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables CLUT. More...
 
void LTDC_CLUTInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 configure the CLUT. More...
 
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 Fills each LTDC_CLUT_InitStruct member with its default value. More...
 
void LTDC_LayerPosition (LTDC_Layer_TypeDef *LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
 reconfigure the layer position. More...
 
void LTDC_LayerAlpha (LTDC_Layer_TypeDef *LTDC_Layerx, uint8_t ConstantAlpha)
 reconfigure constant alpha. More...
 
void LTDC_LayerAddress (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Address)
 reconfigure layer address. More...
 
void LTDC_LayerSize (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Width, uint32_t Height)
 reconfigure layer size. More...
 
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t PixelFormat)
 reconfigure layer pixel format. More...
 
void LTDC_ITConfig (uint32_t LTDC_IT, FunctionalState NewState)
 Enables or disables the specified LTDC's interrupts. More...
 
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
 Clears the LTDC's pending flags. More...
 
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
 Checks whether the specified LTDC's interrupt has occurred or not. More...
 
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
 Clears the LTDC's interrupt pending bits. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
+
+ +

Clears the LTDC's pending flags.

+
Parameters
+ + +
LTDC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • LTDC_FLAG_LI: Line Interrupt flag.
    • +
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
    • +
  • LTDC_FLAG_TERR: Transfer Error Interrupt flag.
    • +
  • LTDC_FLAG_RR: Register Reload interrupt flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
+
+ +

Clears the LTDC's interrupt pending bits.

+
Parameters
+ + +
LTDC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • LTDC_IT_LIE: Line Interrupt.
    • +
  • LTDC_IT_FUIE: FIFO Underrun Interrupt.
    • +
  • LTDC_IT_TERRIE: Transfer Error Interrupt.
    • +
  • LTDC_IT_RRIE: Register Reload interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_CLUTCmd (LTDC_Layer_TypeDef * LTDC_Layerx,
FunctionalState NewState 
)
+
+ +

Enables or disables CLUT.

+
Parameters
+ + + +
NewStatenew state of CLUT.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2 This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_CLUTInit (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_CLUT_InitTypeDef * LTDC_CLUT_InitStruct 
)
+
+ +

configure the CLUT.

+
Parameters
+ + + +
LTDC_CLUT_InitStructpointer to a LTDC_CLUT_InitTypeDef structure that contains the CLUT configuration.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef * LTDC_CLUT_InitStruct)
+
+ +

Fills each LTDC_CLUT_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_CLUT_InitStructpointer to a LTDC_CLUT_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the CLUT adress and RGB values

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the LTDC Controller.

+
Parameters
+ + +
NewStatenew state of the LTDC peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_ColorKeying_InitTypeDef * LTDC_colorkeying_InitStruct,
FunctionalState NewState 
)
+
+ +

Set and configure the color keying.

+
Parameters
+ + + +
LTDC_colorkeying_InitStructpointer to a LTDC_ColorKeying_InitTypeDef structure that contains the color keying configuration.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef * LTDC_colorkeying_InitStruct)
+
+ +

Fills each LTDC_colorkeying_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_colorkeying_InitStructpointer to a LTDC_ColorKeying_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the color keying values

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_DeInit (void )
+
+ +

Deinitializes the LTDC peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_DitherCmd (FunctionalState NewState)
+
+ +

Enables or disables Dither.

+
Parameters
+ + +
NewStatenew state of the Dither. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
+
+ +

Checks whether the specified LTDC's flag is set or not.

+
Parameters
+ + +
LTDC_CDspecifies the flag to check. This parameter can be one of the following values:
    +
  • LTDC_CD_VDES: vertical data enable current status.
    • +
  • LTDC_CD_HDES: horizontal data enable current status.
    • +
  • LTDC_CD_VSYNC: Vertical Synchronization current status.
    • +
  • LTDC_CD_HSYNC: Horizontal Synchronization current status.
    • +
+
+
+
+
Return values
+ + +
Thenew state of LTDC_CD (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
+
+ +

Checks whether the specified LTDC's flag is set or not.

+
Parameters
+ + +
LTDC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • LTDC_FLAG_LI: Line Interrupt flag.
    • +
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
    • +
  • LTDC_FLAG_TERR: Transfer Error Interrupt flag.
    • +
  • LTDC_FLAG_RR: Register Reload interrupt flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of LTDC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
+
+ +

Checks whether the specified LTDC's interrupt has occurred or not.

+
Parameters
+ + +
LTDC_ITspecifies the LTDC interrupts sources to check. This parameter can be one of the following values:
    +
  • LTDC_IT_LI: Line Interrupt Enable.
    • +
  • LTDC_IT_FU: FIFO Underrun Interrupt Enable.
    • +
  • LTDC_IT_TERR: Transfer Error Interrupt Enable.
    • +
  • LTDC_IT_RR: Register Reload interrupt Enable.
    • +
+
+
+
+
Return values
+ + +
Thenew state of the LTDC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
LTDC_PosTypeDef LTDC_GetPosStatus (void )
+
+ +

Get the current position.

+
Parameters
+ + +
LTDC_Pos_InitStructpointer to a LTDC_PosTypeDef structure that contains the current position.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
LTDC_RGBTypeDef LTDC_GetRGBWidth (void )
+
+ +

Get the dither RGB width.

+
Parameters
+ + +
LTDC_RGB_InitStructpointer to a LTDC_RGBTypeDef structure that contains the Dither RGB width.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_Init (LTDC_InitTypeDef * LTDC_InitStruct)
+
+ +

Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct.

+
Note
This function can be used only when the LTDC is disabled.
+
Parameters
+ + +
LTDC_InitStructpointer to a LTDC_InitTypeDef structure that contains the configuration information for the specified LTDC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_ITConfig (uint32_t LTDC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified LTDC's interrupts.

+
Parameters
+ + + +
LTDC_ITspecifies the LTDC interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • LTDC_IT_LI: Line Interrupt Enable.
    • +
  • LTDC_IT_FU: FIFO Underrun Interrupt Enable.
    • +
  • LTDC_IT_TERR: Transfer Error Interrupt Enable.
    • +
  • LTDC_IT_RR: Register Reload interrupt enable.
    • +
+
NewStatenew state of the specified LTDC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerAddress (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t Address 
)
+
+ +

reconfigure layer address.

+
Parameters
+ + + +
AddressThe color frame buffer start address.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer address reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerAlpha (LTDC_Layer_TypeDef * LTDC_Layerx,
uint8_t ConstantAlpha 
)
+
+ +

reconfigure constant alpha.

+
Parameters
+ + + +
ConstantAlphaconstant alpha value.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after constant alpha reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerCmd (LTDC_Layer_TypeDef * LTDC_Layerx,
FunctionalState NewState 
)
+
+ +

Enables or disables the LTDC_Layer Controller.

+
Parameters
+ + + +
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
NewStatenew state of the LTDC_Layer peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerInit (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct 
)
+
+ +

Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct.

+
Note
This function can be used only when the LTDC is disabled.
+
Parameters
+ + + +
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
LTDC_LayerStructpointer to a LTDC_LayerTypeDef structure that contains the configuration information for the specified LTDC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t PixelFormat 
)
+
+ +

reconfigure layer pixel format.

+
Parameters
+ + + +
PixelFormatreconfigure the pixel format, this parameter can be one of the following values:LTDC_Pixelformat.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer pixel format reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_LayerPosition (LTDC_Layer_TypeDef * LTDC_Layerx,
uint16_t OffsetX,
uint16_t OffsetY 
)
+
+ +

reconfigure the layer position.

+
Parameters
+ + + + +
OffsetXhorizontal offset from start active width .
OffsetYvertical offset from start active height.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer position reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_LayerSize (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t Width,
uint32_t Height 
)
+
+ +

reconfigure layer size.

+
Parameters
+ + + + +
Widthlayer window width.
Heightlayer window height.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer size reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct)
+
+ +

Fills each LTDC_Layer_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_Layer_InitStructpointer to a LTDC_LayerTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the horizontal limit member

+

< Initialize the vertical limit member

+

< Initialize the pixel format member

+

< Initialize the constant alpha value

+

< Initialize the default color values

+

< Initialize the blending factors

+

< Initialize the frame buffer start address

+

< Initialize the frame buffer pitch and line length

+

< Initialize the frame buffer line number

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
+
+ +

Define the position of the line interrupt .

+
Parameters
+ + +
LTDC_LIPositionConfigLine Interrupt Position.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_PosStructInit (LTDC_PosTypeDef * LTDC_Pos_InitStruct)
+
+ +

Fills each LTDC_Pos_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_Pos_InitStructpointer to a LTDC_PosTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
+
+ +

reload layers registers with new parameters

+
Parameters
+ + +
LTDC_Reloadspecifies the type of reload. This parameter can be one of the following values:
    +
  • LTDC_IMReload: Vertical blanking reload.
    • +
  • LTDC_VBReload: Immediate reload.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_RGBStructInit (LTDC_RGBTypeDef * LTDC_RGB_InitStruct)
+
+ +

Fills each LTDC_RGBStruct member with its default value.

+
Parameters
+ + +
LTDC_RGB_InitStructpointer to a LTDC_RGBTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_StructInit (LTDC_InitTypeDef * LTDC_InitStruct)
+
+ +

Fills each LTDC_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_InitStructpointer to a LTDC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the LTDC_HSPolarity member

+

< Initialize the LTDC_VSPolarity member

+

< Initialize the LTDC_DEPolarity member

+

< Initialize the LTDC_PCPolarity member

+

< Initialize the LTDC_HorizontalSync member

+

< Initialize the LTDC_VerticalSync member

+

< Initialize the LTDC_AccumulatedHBP member

+

< Initialize the LTDC_AccumulatedVBP member

+

< Initialize the LTDC_AccumulatedActiveW member

+

< Initialize the LTDC_AccumulatedActiveH member

+

< Initialize the LTDC_TotalWidth member

+

< Initialize the LTDC_TotalHeigh member

+

< Initialize the LTDC_BackgroundRedValue member

+

< Initialize the LTDC_BackgroundGreenValue member

+

< Initialize the LTDC_BackgroundBlueValue member

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___c_l_u_t___config.map b/group___l_t_d_c___c_l_u_t___config.map new file mode 100644 index 0000000..6a9062d --- /dev/null +++ b/group___l_t_d_c___c_l_u_t___config.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___c_l_u_t___config.md5 b/group___l_t_d_c___c_l_u_t___config.md5 new file mode 100644 index 0000000..498508c --- /dev/null +++ b/group___l_t_d_c___c_l_u_t___config.md5 @@ -0,0 +1 @@ +1b80fedde6129a3f970e86201c4088c1 \ No newline at end of file diff --git a/group___l_t_d_c___c_l_u_t___config.png b/group___l_t_d_c___c_l_u_t___config.png new file mode 100644 index 0000000..1fa0ac7 Binary files /dev/null and b/group___l_t_d_c___c_l_u_t___config.png differ diff --git a/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.map b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.map new file mode 100644 index 0000000..47e5688 --- /dev/null +++ b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 new file mode 100644 index 0000000..ad9f042 --- /dev/null +++ b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 @@ -0,0 +1 @@ +c81e56ef3f482a04f58650be0fd3190c \ No newline at end of file diff --git a/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.png b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.png new file mode 100644 index 0000000..31421ba Binary files /dev/null and b/group___l_t_d_c___c_l_u_t___config_gad3522837b5ef2b99653e230e649fc149_cgraph.png differ diff --git a/group___l_t_d_c___current_status.html b/group___l_t_d_c___current_status.html new file mode 100644 index 0000000..d0f57b5 --- /dev/null +++ b/group___l_t_d_c___current_status.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: LTDC_CurrentStatus + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_CurrentStatus
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_CurrentStatus:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define LTDC_CD_VDES   LTDC_CDSR_VDES
 
+#define LTDC_CD_HDES   LTDC_CDSR_HDES
 
+#define LTDC_CD_VSYNC   LTDC_CDSR_VSYNCS
 
+#define LTDC_CD_HSYNC   LTDC_CDSR_HSYNCS
 
#define IS_LTDC_GET_CD(CD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_GET_CD( CD)
+
+Value:
(((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
+
((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___current_status.map b/group___l_t_d_c___current_status.map new file mode 100644 index 0000000..a32e9b1 --- /dev/null +++ b/group___l_t_d_c___current_status.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___current_status.md5 b/group___l_t_d_c___current_status.md5 new file mode 100644 index 0000000..ea986bd --- /dev/null +++ b/group___l_t_d_c___current_status.md5 @@ -0,0 +1 @@ +52a54e0a72d4cbcf3981fb53e4475922 \ No newline at end of file diff --git a/group___l_t_d_c___current_status.png b/group___l_t_d_c___current_status.png new file mode 100644 index 0000000..066fa27 Binary files /dev/null and b/group___l_t_d_c___current_status.png differ diff --git a/group___l_t_d_c___d_e_polarity.html b/group___l_t_d_c___d_e_polarity.html new file mode 100644 index 0000000..e51fff5 --- /dev/null +++ b/group___l_t_d_c___d_e_polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: LTDC_DEPolarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_DEPolarity
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_DEPolarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define LTDC_DEPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_DEPolarity_AH   LTDC_GCR_DEPOL
 
#define IS_LTDC_DEPOL(DEPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_DEPOL( DEPOL)
+
+Value:
(((DEPOL) == LTDC_VSPolarity_AL) || \
+
((DEPOL) == LTDC_DEPolarity_AH))
+
LTDC_VSPolarity_AL
#define LTDC_VSPolarity_AL
Definition: stm32f4xx_ltdc.h:242
+
LTDC_DEPolarity_AH
#define LTDC_DEPolarity_AH
Definition: stm32f4xx_ltdc.h:256
+
+
+
+ +
+
+ + + + +
#define LTDC_DEPolarity_AH   LTDC_GCR_DEPOL
+
+

Data Enable, is active high.

+ +
+
+ +
+
+ + + + +
#define LTDC_DEPolarity_AL   ((uint32_t)0x00000000)
+
+

Data Enable, is active low.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___d_e_polarity.map b/group___l_t_d_c___d_e_polarity.map new file mode 100644 index 0000000..6b26266 --- /dev/null +++ b/group___l_t_d_c___d_e_polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___d_e_polarity.md5 b/group___l_t_d_c___d_e_polarity.md5 new file mode 100644 index 0000000..f2476f6 --- /dev/null +++ b/group___l_t_d_c___d_e_polarity.md5 @@ -0,0 +1 @@ +39b9557d43c1df027f8c036368927974 \ No newline at end of file diff --git a/group___l_t_d_c___d_e_polarity.png b/group___l_t_d_c___d_e_polarity.png new file mode 100644 index 0000000..df2e294 Binary files /dev/null and b/group___l_t_d_c___d_e_polarity.png differ diff --git a/group___l_t_d_c___exported___constants.html b/group___l_t_d_c___exported___constants.html new file mode 100644 index 0000000..0633f55 --- /dev/null +++ b/group___l_t_d_c___exported___constants.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: LTDC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+
LTDC_Exported_Constants
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+
+Collaboration diagram for LTDC_Exported_Constants:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___exported___constants.map b/group___l_t_d_c___exported___constants.map new file mode 100644 index 0000000..ead306f --- /dev/null +++ b/group___l_t_d_c___exported___constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___exported___constants.md5 b/group___l_t_d_c___exported___constants.md5 new file mode 100644 index 0000000..eea59fd --- /dev/null +++ b/group___l_t_d_c___exported___constants.md5 @@ -0,0 +1 @@ +7404e629f06df26f1f9efb5c96f44a56 \ No newline at end of file diff --git a/group___l_t_d_c___exported___constants.png b/group___l_t_d_c___exported___constants.png new file mode 100644 index 0000000..e46c42e Binary files /dev/null and b/group___l_t_d_c___exported___constants.png differ diff --git a/group___l_t_d_c___flag.html b/group___l_t_d_c___flag.html new file mode 100644 index 0000000..d1d2535 --- /dev/null +++ b/group___l_t_d_c___flag.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: LTDC_Flag + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Flag
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Flag:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define LTDC_FLAG_LI   LTDC_ISR_LIF
 
+#define LTDC_FLAG_FU   LTDC_ISR_FUIF
 
+#define LTDC_FLAG_TERR   LTDC_ISR_TERRIF
 
+#define LTDC_FLAG_RR   LTDC_ISR_RRIF
 
#define IS_LTDC_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_FLAG( FLAG)
+
+Value:
(((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___flag.map b/group___l_t_d_c___flag.map new file mode 100644 index 0000000..6994dc6 --- /dev/null +++ b/group___l_t_d_c___flag.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___flag.md5 b/group___l_t_d_c___flag.md5 new file mode 100644 index 0000000..7a216ea --- /dev/null +++ b/group___l_t_d_c___flag.md5 @@ -0,0 +1 @@ +3cbaf5bfc8984ec6e8e52e65b17b5702 \ No newline at end of file diff --git a/group___l_t_d_c___flag.png b/group___l_t_d_c___flag.png new file mode 100644 index 0000000..99ee359 Binary files /dev/null and b/group___l_t_d_c___flag.png differ diff --git a/group___l_t_d_c___group1.html b/group___l_t_d_c___group1.html new file mode 100644 index 0000000..4369d1f --- /dev/null +++ b/group___l_t_d_c___group1.html @@ -0,0 +1,1123 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » LTDC » LTDC_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LTDC_DeInit (void)
 Deinitializes the LTDC peripheral registers to their default reset values. More...
 
void LTDC_Init (LTDC_InitTypeDef *LTDC_InitStruct)
 Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct. More...
 
void LTDC_StructInit (LTDC_InitTypeDef *LTDC_InitStruct)
 Fills each LTDC_InitStruct member with its default value. More...
 
void LTDC_Cmd (FunctionalState NewState)
 Enables or disables the LTDC Controller. More...
 
void LTDC_DitherCmd (FunctionalState NewState)
 Enables or disables Dither. More...
 
LTDC_RGBTypeDef LTDC_GetRGBWidth (void)
 Get the dither RGB width. More...
 
void LTDC_RGBStructInit (LTDC_RGBTypeDef *LTDC_RGB_InitStruct)
 Fills each LTDC_RGBStruct member with its default value. More...
 
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
 Define the position of the line interrupt . More...
 
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
 reload layers registers with new parameters More...
 
void LTDC_LayerInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct. More...
 
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Fills each LTDC_Layer_InitStruct member with its default value. More...
 
void LTDC_LayerCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables the LTDC_Layer Controller. More...
 
LTDC_PosTypeDef LTDC_GetPosStatus (void)
 Get the current position. More...
 
void LTDC_PosStructInit (LTDC_PosTypeDef *LTDC_Pos_InitStruct)
 Fills each LTDC_Pos_InitStruct member with its default value. More...
 
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct, FunctionalState NewState)
 Set and configure the color keying. More...
 
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct)
 Fills each LTDC_colorkeying_InitStruct member with its default value. More...
 
void LTDC_CLUTCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables CLUT. More...
 
void LTDC_CLUTInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 configure the CLUT. More...
 
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 Fills each LTDC_CLUT_InitStruct member with its default value. More...
 
void LTDC_LayerPosition (LTDC_Layer_TypeDef *LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
 reconfigure the layer position. More...
 
void LTDC_LayerAlpha (LTDC_Layer_TypeDef *LTDC_Layerx, uint8_t ConstantAlpha)
 reconfigure constant alpha. More...
 
void LTDC_LayerAddress (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Address)
 reconfigure layer address. More...
 
void LTDC_LayerSize (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Width, uint32_t Height)
 reconfigure layer size. More...
 
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t PixelFormat)
 reconfigure layer pixel format. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the LTDC
+      (+) Enable or Disable Dither
+      (+) Define the position of the line interrupt
+      (+) reload layers registers with new parameters
+      (+) Initialize and configure layer1 and layer2
+      (+) Set and configure the color keying functionality
+      (+) Configure and Enables or disables CLUT

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_CLUTCmd (LTDC_Layer_TypeDef * LTDC_Layerx,
FunctionalState NewState 
)
+
+ +

Enables or disables CLUT.

+
Parameters
+ + + +
NewStatenew state of CLUT.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2 This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_CLUTInit (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_CLUT_InitTypeDef * LTDC_CLUT_InitStruct 
)
+
+ +

configure the CLUT.

+
Parameters
+ + + +
LTDC_CLUT_InitStructpointer to a LTDC_CLUT_InitTypeDef structure that contains the CLUT configuration.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef * LTDC_CLUT_InitStruct)
+
+ +

Fills each LTDC_CLUT_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_CLUT_InitStructpointer to a LTDC_CLUT_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the CLUT adress and RGB values

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the LTDC Controller.

+
Parameters
+ + +
NewStatenew state of the LTDC peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_ColorKeying_InitTypeDef * LTDC_colorkeying_InitStruct,
FunctionalState NewState 
)
+
+ +

Set and configure the color keying.

+
Parameters
+ + + +
LTDC_colorkeying_InitStructpointer to a LTDC_ColorKeying_InitTypeDef structure that contains the color keying configuration.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef * LTDC_colorkeying_InitStruct)
+
+ +

Fills each LTDC_colorkeying_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_colorkeying_InitStructpointer to a LTDC_ColorKeying_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the color keying values

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_DeInit (void )
+
+ +

Deinitializes the LTDC peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_DitherCmd (FunctionalState NewState)
+
+ +

Enables or disables Dither.

+
Parameters
+ + +
NewStatenew state of the Dither. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
+
+ +

Checks whether the specified LTDC's flag is set or not.

+
Parameters
+ + +
LTDC_CDspecifies the flag to check. This parameter can be one of the following values:
    +
  • LTDC_CD_VDES: vertical data enable current status.
    • +
  • LTDC_CD_HDES: horizontal data enable current status.
    • +
  • LTDC_CD_VSYNC: Vertical Synchronization current status.
    • +
  • LTDC_CD_HSYNC: Horizontal Synchronization current status.
    • +
+
+
+
+
Return values
+ + +
Thenew state of LTDC_CD (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
LTDC_PosTypeDef LTDC_GetPosStatus (void )
+
+ +

Get the current position.

+
Parameters
+ + +
LTDC_Pos_InitStructpointer to a LTDC_PosTypeDef structure that contains the current position.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
LTDC_RGBTypeDef LTDC_GetRGBWidth (void )
+
+ +

Get the dither RGB width.

+
Parameters
+ + +
LTDC_RGB_InitStructpointer to a LTDC_RGBTypeDef structure that contains the Dither RGB width.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_Init (LTDC_InitTypeDef * LTDC_InitStruct)
+
+ +

Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct.

+
Note
This function can be used only when the LTDC is disabled.
+
Parameters
+ + +
LTDC_InitStructpointer to a LTDC_InitTypeDef structure that contains the configuration information for the specified LTDC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerAddress (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t Address 
)
+
+ +

reconfigure layer address.

+
Parameters
+ + + +
AddressThe color frame buffer start address.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer address reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerAlpha (LTDC_Layer_TypeDef * LTDC_Layerx,
uint8_t ConstantAlpha 
)
+
+ +

reconfigure constant alpha.

+
Parameters
+ + + +
ConstantAlphaconstant alpha value.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after constant alpha reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerCmd (LTDC_Layer_TypeDef * LTDC_Layerx,
FunctionalState NewState 
)
+
+ +

Enables or disables the LTDC_Layer Controller.

+
Parameters
+ + + +
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
NewStatenew state of the LTDC_Layer peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerInit (LTDC_Layer_TypeDef * LTDC_Layerx,
LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct 
)
+
+ +

Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct.

+
Note
This function can be used only when the LTDC is disabled.
+
Parameters
+ + + +
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
LTDC_LayerStructpointer to a LTDC_LayerTypeDef structure that contains the configuration information for the specified LTDC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t PixelFormat 
)
+
+ +

reconfigure layer pixel format.

+
Parameters
+ + + +
PixelFormatreconfigure the pixel format, this parameter can be one of the following values:LTDC_Pixelformat.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer pixel format reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_LayerPosition (LTDC_Layer_TypeDef * LTDC_Layerx,
uint16_t OffsetX,
uint16_t OffsetY 
)
+
+ +

reconfigure the layer position.

+
Parameters
+ + + + +
OffsetXhorizontal offset from start active width .
OffsetYvertical offset from start active height.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer position reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LTDC_LayerSize (LTDC_Layer_TypeDef * LTDC_Layerx,
uint32_t Width,
uint32_t Height 
)
+
+ +

reconfigure layer size.

+
Parameters
+ + + + +
Widthlayer window width.
Heightlayer window height.
LTDC_layerxSelect the layer to be configured, this parameter can be one of the following values: LTDC_Layer1, LTDC_Layer2
+
+
+
Return values
+ + +
Reloadof the shadow registers values must be applied after layer size reconfiguration.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct)
+
+ +

Fills each LTDC_Layer_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_Layer_InitStructpointer to a LTDC_LayerTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the horizontal limit member

+

< Initialize the vertical limit member

+

< Initialize the pixel format member

+

< Initialize the constant alpha value

+

< Initialize the default color values

+

< Initialize the blending factors

+

< Initialize the frame buffer start address

+

< Initialize the frame buffer pitch and line length

+

< Initialize the frame buffer line number

+ +
+
+ +
+
+ + + + + + + + +
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
+
+ +

Define the position of the line interrupt .

+
Parameters
+ + +
LTDC_LIPositionConfigLine Interrupt Position.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_PosStructInit (LTDC_PosTypeDef * LTDC_Pos_InitStruct)
+
+ +

Fills each LTDC_Pos_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_Pos_InitStructpointer to a LTDC_PosTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
+
+ +

reload layers registers with new parameters

+
Parameters
+ + +
LTDC_Reloadspecifies the type of reload. This parameter can be one of the following values:
    +
  • LTDC_IMReload: Vertical blanking reload.
    • +
  • LTDC_VBReload: Immediate reload.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_RGBStructInit (LTDC_RGBTypeDef * LTDC_RGB_InitStruct)
+
+ +

Fills each LTDC_RGBStruct member with its default value.

+
Parameters
+ + +
LTDC_RGB_InitStructpointer to a LTDC_RGBTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_StructInit (LTDC_InitTypeDef * LTDC_InitStruct)
+
+ +

Fills each LTDC_InitStruct member with its default value.

+
Parameters
+ + +
LTDC_InitStructpointer to a LTDC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+

< Initialize the LTDC_HSPolarity member

+

< Initialize the LTDC_VSPolarity member

+

< Initialize the LTDC_DEPolarity member

+

< Initialize the LTDC_PCPolarity member

+

< Initialize the LTDC_HorizontalSync member

+

< Initialize the LTDC_VerticalSync member

+

< Initialize the LTDC_AccumulatedHBP member

+

< Initialize the LTDC_AccumulatedVBP member

+

< Initialize the LTDC_AccumulatedActiveW member

+

< Initialize the LTDC_AccumulatedActiveH member

+

< Initialize the LTDC_TotalWidth member

+

< Initialize the LTDC_TotalHeigh member

+

< Initialize the LTDC_BackgroundRedValue member

+

< Initialize the LTDC_BackgroundGreenValue member

+

< Initialize the LTDC_BackgroundBlueValue member

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___group1.map b/group___l_t_d_c___group1.map new file mode 100644 index 0000000..d7ad832 --- /dev/null +++ b/group___l_t_d_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___group1.md5 b/group___l_t_d_c___group1.md5 new file mode 100644 index 0000000..7ff4dfc --- /dev/null +++ b/group___l_t_d_c___group1.md5 @@ -0,0 +1 @@ +5af6764584387b7a73ff553c8efcd576 \ No newline at end of file diff --git a/group___l_t_d_c___group1.png b/group___l_t_d_c___group1.png new file mode 100644 index 0000000..f1cdbad Binary files /dev/null and b/group___l_t_d_c___group1.png differ diff --git a/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.map b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.map new file mode 100644 index 0000000..47e5688 --- /dev/null +++ b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 new file mode 100644 index 0000000..ad9f042 --- /dev/null +++ b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.md5 @@ -0,0 +1 @@ +c81e56ef3f482a04f58650be0fd3190c \ No newline at end of file diff --git a/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.png b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.png new file mode 100644 index 0000000..31421ba Binary files /dev/null and b/group___l_t_d_c___group1_gad3522837b5ef2b99653e230e649fc149_cgraph.png differ diff --git a/group___l_t_d_c___group2.html b/group___l_t_d_c___group2.html new file mode 100644 index 0000000..051ab58 --- /dev/null +++ b/group___l_t_d_c___group2.html @@ -0,0 +1,346 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » LTDC » LTDC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void LTDC_ITConfig (uint32_t LTDC_IT, FunctionalState NewState)
 Enables or disables the specified LTDC's interrupts. More...
 
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
 Clears the LTDC's pending flags. More...
 
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
 Checks whether the specified LTDC's interrupt has occurred or not. More...
 
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
 Clears the LTDC's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+    [..] This section provides functions allowing to configure the LTDC Interrupts 
+         and to get the status and clear flags and Interrupts pending bits.
+  
+    [..] The LTDC provides 4 Interrupts sources and 4 Flags
+    
+    *** Flags ***
+    =============
+    [..]
+      (+) LTDC_FLAG_LI:   Line Interrupt flag.
+      (+) LTDC_FLAG_FU:   FIFO Underrun Interrupt flag.
+      (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag.
+      (+) LTDC_FLAG_RR:   Register Reload interrupt flag.
+      
+    *** Interrupts ***
+    ==================
+    [..]
+      (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line 
+                      is reached. The line interrupt position is programmed in 
+                      the LTDC_LIPR register.
+      (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested 
+                      from an empty layer FIFO
+      (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus 
+                        error occurs during data transfer.
+      (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow 
+                      registers reload was performed during the vertical blanking 
+                      period.

Function Documentation

+ +
+
+ + + + + + + + +
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
+
+ +

Clears the LTDC's pending flags.

+
Parameters
+ + +
LTDC_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • LTDC_FLAG_LI: Line Interrupt flag.
    • +
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
    • +
  • LTDC_FLAG_TERR: Transfer Error Interrupt flag.
    • +
  • LTDC_FLAG_RR: Register Reload interrupt flag.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
+
+ +

Clears the LTDC's interrupt pending bits.

+
Parameters
+ + +
LTDC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • LTDC_IT_LIE: Line Interrupt.
    • +
  • LTDC_IT_FUIE: FIFO Underrun Interrupt.
    • +
  • LTDC_IT_TERRIE: Transfer Error Interrupt.
    • +
  • LTDC_IT_RRIE: Register Reload interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
+
+ +

Checks whether the specified LTDC's flag is set or not.

+
Parameters
+ + +
LTDC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • LTDC_FLAG_LI: Line Interrupt flag.
    • +
  • LTDC_FLAG_FU: FIFO Underrun Interrupt flag.
    • +
  • LTDC_FLAG_TERR: Transfer Error Interrupt flag.
    • +
  • LTDC_FLAG_RR: Register Reload interrupt flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of LTDC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
+
+ +

Checks whether the specified LTDC's interrupt has occurred or not.

+
Parameters
+ + +
LTDC_ITspecifies the LTDC interrupts sources to check. This parameter can be one of the following values:
    +
  • LTDC_IT_LI: Line Interrupt Enable.
    • +
  • LTDC_IT_FU: FIFO Underrun Interrupt Enable.
    • +
  • LTDC_IT_TERR: Transfer Error Interrupt Enable.
    • +
  • LTDC_IT_RR: Register Reload interrupt Enable.
    • +
+
+
+
+
Return values
+ + +
Thenew state of the LTDC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void LTDC_ITConfig (uint32_t LTDC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified LTDC's interrupts.

+
Parameters
+ + + +
LTDC_ITspecifies the LTDC interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • LTDC_IT_LI: Line Interrupt Enable.
    • +
  • LTDC_IT_FU: FIFO Underrun Interrupt Enable.
    • +
  • LTDC_IT_TERR: Transfer Error Interrupt Enable.
    • +
  • LTDC_IT_RR: Register Reload interrupt enable.
    • +
+
NewStatenew state of the specified LTDC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___group2.map b/group___l_t_d_c___group2.map new file mode 100644 index 0000000..1b13179 --- /dev/null +++ b/group___l_t_d_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___group2.md5 b/group___l_t_d_c___group2.md5 new file mode 100644 index 0000000..ccd143b --- /dev/null +++ b/group___l_t_d_c___group2.md5 @@ -0,0 +1 @@ +db2af9920cd23ff967ec39b28f06e592 \ No newline at end of file diff --git a/group___l_t_d_c___group2.png b/group___l_t_d_c___group2.png new file mode 100644 index 0000000..5d4f4ec Binary files /dev/null and b/group___l_t_d_c___group2.png differ diff --git a/group___l_t_d_c___h_s_polarity.html b/group___l_t_d_c___h_s_polarity.html new file mode 100644 index 0000000..5354c0c --- /dev/null +++ b/group___l_t_d_c___h_s_polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: LTDC_HSPolarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
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+ + +
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+Macros
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+
LTDC_HSPolarity
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_HSPolarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define LTDC_HSPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_HSPolarity_AH   LTDC_GCR_HSPOL
 
#define IS_LTDC_HSPOL(HSPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_HSPOL( HSPOL)
+
+Value:
(((HSPOL) == LTDC_HSPolarity_AL) || \
+
((HSPOL) == LTDC_HSPolarity_AH))
+
LTDC_HSPolarity_AL
#define LTDC_HSPolarity_AL
Definition: stm32f4xx_ltdc.h:229
+
LTDC_HSPolarity_AH
#define LTDC_HSPolarity_AH
Definition: stm32f4xx_ltdc.h:230
+
+
+
+ +
+
+ + + + +
#define LTDC_HSPolarity_AH   LTDC_GCR_HSPOL
+
+

Horizontal Synchronization is active high.

+ +
+
+ +
+
+ + + + +
#define LTDC_HSPolarity_AL   ((uint32_t)0x00000000)
+
+

Horizontal Synchronization is active low.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___h_s_polarity.map b/group___l_t_d_c___h_s_polarity.map new file mode 100644 index 0000000..8ea7dbe --- /dev/null +++ b/group___l_t_d_c___h_s_polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___h_s_polarity.md5 b/group___l_t_d_c___h_s_polarity.md5 new file mode 100644 index 0000000..afad7c7 --- /dev/null +++ b/group___l_t_d_c___h_s_polarity.md5 @@ -0,0 +1 @@ +7eabaa2163b45ad35eaa8b0ad91a7068 \ No newline at end of file diff --git a/group___l_t_d_c___h_s_polarity.png b/group___l_t_d_c___h_s_polarity.png new file mode 100644 index 0000000..0ed6b20 Binary files /dev/null and b/group___l_t_d_c___h_s_polarity.png differ diff --git a/group___l_t_d_c___interrupts.html b/group___l_t_d_c___interrupts.html new file mode 100644 index 0000000..55b4dd8 --- /dev/null +++ b/group___l_t_d_c___interrupts.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: LTDC_Interrupts + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Interrupts
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Interrupts:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define LTDC_IT_LI   LTDC_IER_LIE
 
+#define LTDC_IT_FU   LTDC_IER_FUIE
 
+#define LTDC_IT_TERR   LTDC_IER_TERRIE
 
+#define LTDC_IT_RR   LTDC_IER_RRIE
 
+#define IS_LTDC_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___interrupts.map b/group___l_t_d_c___interrupts.map new file mode 100644 index 0000000..c5e2fcd --- /dev/null +++ b/group___l_t_d_c___interrupts.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___interrupts.md5 b/group___l_t_d_c___interrupts.md5 new file mode 100644 index 0000000..57f6ce4 --- /dev/null +++ b/group___l_t_d_c___interrupts.md5 @@ -0,0 +1 @@ +23264b08ee8e1311ffa547eb7ca02617 \ No newline at end of file diff --git a/group___l_t_d_c___interrupts.png b/group___l_t_d_c___interrupts.png new file mode 100644 index 0000000..f72ee69 Binary files /dev/null and b/group___l_t_d_c___interrupts.png differ diff --git a/group___l_t_d_c___l_a_y_e_r___config.html b/group___l_t_d_c___l_a_y_e_r___config.html new file mode 100644 index 0000000..442f33f --- /dev/null +++ b/group___l_t_d_c___l_a_y_e_r___config.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: LTDC_LAYER_Config + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_LAYER_Config
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_LAYER_Config:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LTDC_STOPPosition   ((uint32_t)0x0000FFFF)
 
+#define LTDC_STARTPosition   ((uint32_t)0x00000FFF)
 
+#define LTDC_DefaultColorConfig   ((uint32_t)0x000000FF)
 
+#define LTDC_ColorFrameBuffer   ((uint32_t)0x00001FFF)
 
+#define LTDC_LineNumber   ((uint32_t)0x000007FF)
 
+#define IS_LTDC_HCONFIGST(HCONFIGST)   ((HCONFIGST) <= LTDC_STARTPosition)
 
+#define IS_LTDC_HCONFIGSP(HCONFIGSP)   ((HCONFIGSP) <= LTDC_STOPPosition)
 
+#define IS_LTDC_VCONFIGST(VCONFIGST)   ((VCONFIGST) <= LTDC_STARTPosition)
 
+#define IS_LTDC_VCONFIGSP(VCONFIGSP)   ((VCONFIGSP) <= LTDC_STOPPosition)
 
+#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR)   ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
 
+#define IS_LTDC_CFBP(CFBP)   ((CFBP) <= LTDC_ColorFrameBuffer)
 
+#define IS_LTDC_CFBLL(CFBLL)   ((CFBLL) <= LTDC_ColorFrameBuffer)
 
+#define IS_LTDC_CFBLNBR(CFBLNBR)   ((CFBLNBR) <= LTDC_LineNumber)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___l_a_y_e_r___config.map b/group___l_t_d_c___l_a_y_e_r___config.map new file mode 100644 index 0000000..85e338c --- /dev/null +++ b/group___l_t_d_c___l_a_y_e_r___config.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___l_a_y_e_r___config.md5 b/group___l_t_d_c___l_a_y_e_r___config.md5 new file mode 100644 index 0000000..e74a246 --- /dev/null +++ b/group___l_t_d_c___l_a_y_e_r___config.md5 @@ -0,0 +1 @@ +d6d47faa557e11400c027ecf2277f03e \ No newline at end of file diff --git a/group___l_t_d_c___l_a_y_e_r___config.png b/group___l_t_d_c___l_a_y_e_r___config.png new file mode 100644 index 0000000..63b6b51 Binary files /dev/null and b/group___l_t_d_c___l_a_y_e_r___config.png differ diff --git a/group___l_t_d_c___l_i_position.html b/group___l_t_d_c___l_i_position.html new file mode 100644 index 0000000..97b07de --- /dev/null +++ b/group___l_t_d_c___l_i_position.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: LTDC_LIPosition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_LIPosition
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_LIPosition:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_LTDC_LIPOS(LIPOS)   ((LIPOS) <= 0x7FF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___l_i_position.map b/group___l_t_d_c___l_i_position.map new file mode 100644 index 0000000..5576ffd --- /dev/null +++ b/group___l_t_d_c___l_i_position.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___l_i_position.md5 b/group___l_t_d_c___l_i_position.md5 new file mode 100644 index 0000000..7a9b238 --- /dev/null +++ b/group___l_t_d_c___l_i_position.md5 @@ -0,0 +1 @@ +bec60b5da282747d5e0ec347c62c2c03 \ No newline at end of file diff --git a/group___l_t_d_c___l_i_position.png b/group___l_t_d_c___l_i_position.png new file mode 100644 index 0000000..7ef7950 Binary files /dev/null and b/group___l_t_d_c___l_i_position.png differ diff --git a/group___l_t_d_c___p_c_polarity.html b/group___l_t_d_c___p_c_polarity.html new file mode 100644 index 0000000..a9e1eae --- /dev/null +++ b/group___l_t_d_c___p_c_polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: LTDC_PCPolarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_PCPolarity
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_PCPolarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define LTDC_PCPolarity_IPC   ((uint32_t)0x00000000)
 
#define LTDC_PCPolarity_IIPC   LTDC_GCR_PCPOL
 
#define IS_LTDC_PCPOL(PCPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_PCPOL( PCPOL)
+
+Value:
(((PCPOL) == LTDC_PCPolarity_IPC) || \
+
((PCPOL) == LTDC_PCPolarity_IIPC))
+
LTDC_PCPolarity_IIPC
#define LTDC_PCPolarity_IIPC
Definition: stm32f4xx_ltdc.h:269
+
LTDC_PCPolarity_IPC
#define LTDC_PCPolarity_IPC
Definition: stm32f4xx_ltdc.h:268
+
+
+
+ +
+
+ + + + +
#define LTDC_PCPolarity_IIPC   LTDC_GCR_PCPOL
+
+

inverted input pixel clock.

+ +
+
+ +
+
+ + + + +
#define LTDC_PCPolarity_IPC   ((uint32_t)0x00000000)
+
+

input pixel clock.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___p_c_polarity.map b/group___l_t_d_c___p_c_polarity.map new file mode 100644 index 0000000..7a0cd1b --- /dev/null +++ b/group___l_t_d_c___p_c_polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___p_c_polarity.md5 b/group___l_t_d_c___p_c_polarity.md5 new file mode 100644 index 0000000..bdadf67 --- /dev/null +++ b/group___l_t_d_c___p_c_polarity.md5 @@ -0,0 +1 @@ +808116375893eece603e79407ff1e1a3 \ No newline at end of file diff --git a/group___l_t_d_c___p_c_polarity.png b/group___l_t_d_c___p_c_polarity.png new file mode 100644 index 0000000..4dca51b Binary files /dev/null and b/group___l_t_d_c___p_c_polarity.png differ diff --git a/group___l_t_d_c___pixelformat.html b/group___l_t_d_c___pixelformat.html new file mode 100644 index 0000000..d5e503a --- /dev/null +++ b/group___l_t_d_c___pixelformat.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: LTDC_Pixelformat + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Pixelformat
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Pixelformat:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LTDC_Pixelformat_ARGB8888   ((uint32_t)0x00000000)
 
+#define LTDC_Pixelformat_RGB888   ((uint32_t)0x00000001)
 
+#define LTDC_Pixelformat_RGB565   ((uint32_t)0x00000002)
 
+#define LTDC_Pixelformat_ARGB1555   ((uint32_t)0x00000003)
 
+#define LTDC_Pixelformat_ARGB4444   ((uint32_t)0x00000004)
 
+#define LTDC_Pixelformat_L8   ((uint32_t)0x00000005)
 
+#define LTDC_Pixelformat_AL44   ((uint32_t)0x00000006)
 
+#define LTDC_Pixelformat_AL88   ((uint32_t)0x00000007)
 
#define IS_LTDC_Pixelformat(Pixelformat)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_Pixelformat( Pixelformat)
+
+Value:
(((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \
+
((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
+
((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \
+
((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___pixelformat.map b/group___l_t_d_c___pixelformat.map new file mode 100644 index 0000000..ea027a3 --- /dev/null +++ b/group___l_t_d_c___pixelformat.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___pixelformat.md5 b/group___l_t_d_c___pixelformat.md5 new file mode 100644 index 0000000..af0ec9c --- /dev/null +++ b/group___l_t_d_c___pixelformat.md5 @@ -0,0 +1 @@ +89f3db0930532d1e8d3787bd7773d3b7 \ No newline at end of file diff --git a/group___l_t_d_c___pixelformat.png b/group___l_t_d_c___pixelformat.png new file mode 100644 index 0000000..c2a7d17 Binary files /dev/null and b/group___l_t_d_c___pixelformat.png differ diff --git a/group___l_t_d_c___position.html b/group___l_t_d_c___position.html new file mode 100644 index 0000000..ad07a56 --- /dev/null +++ b/group___l_t_d_c___position.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: LTDC_Position + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Position
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Position:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define LTDC_POS_CY   LTDC_CPSR_CYPOS
 
+#define LTDC_POS_CX   LTDC_CPSR_CXPOS
 
+#define IS_LTDC_GET_POS(POS)   (((POS) <= LTDC_POS_CY))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___position.map b/group___l_t_d_c___position.map new file mode 100644 index 0000000..a19d038 --- /dev/null +++ b/group___l_t_d_c___position.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___position.md5 b/group___l_t_d_c___position.md5 new file mode 100644 index 0000000..e8f43eb --- /dev/null +++ b/group___l_t_d_c___position.md5 @@ -0,0 +1 @@ +084fbc902706e9986770393a22b7e289 \ No newline at end of file diff --git a/group___l_t_d_c___position.png b/group___l_t_d_c___position.png new file mode 100644 index 0000000..34e452e Binary files /dev/null and b/group___l_t_d_c___position.png differ diff --git a/group___l_t_d_c___private___functions.html b/group___l_t_d_c___private___functions.html new file mode 100644 index 0000000..30f7baa --- /dev/null +++ b/group___l_t_d_c___private___functions.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: LTDC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
LTDC_Private_Functions
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+
+Collaboration diagram for LTDC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___private___functions.map b/group___l_t_d_c___private___functions.map new file mode 100644 index 0000000..17a608a --- /dev/null +++ b/group___l_t_d_c___private___functions.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___l_t_d_c___private___functions.md5 b/group___l_t_d_c___private___functions.md5 new file mode 100644 index 0000000..7778739 --- /dev/null +++ b/group___l_t_d_c___private___functions.md5 @@ -0,0 +1 @@ +937fb61ca38c9388ec9cbbfdfedbc601 \ No newline at end of file diff --git a/group___l_t_d_c___private___functions.png b/group___l_t_d_c___private___functions.png new file mode 100644 index 0000000..2288ade Binary files /dev/null and b/group___l_t_d_c___private___functions.png differ diff --git a/group___l_t_d_c___reload.html b/group___l_t_d_c___reload.html new file mode 100644 index 0000000..6f113ff --- /dev/null +++ b/group___l_t_d_c___reload.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: LTDC_Reload + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_Reload
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_Reload:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define LTDC_IMReload   LTDC_SRCR_IMR
 
#define LTDC_VBReload   LTDC_SRCR_VBR
 
#define IS_LTDC_RELOAD(RELOAD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_RELOAD( RELOAD)
+
+Value:
(((RELOAD) == LTDC_IMReload) || \
+
((RELOAD) == LTDC_VBReload))
+
LTDC_IMReload
#define LTDC_IMReload
Definition: stm32f4xx_ltdc.h:281
+
LTDC_VBReload
#define LTDC_VBReload
Definition: stm32f4xx_ltdc.h:282
+
+
+
+ +
+
+ + + + +
#define LTDC_IMReload   LTDC_SRCR_IMR
+
+

Immediately Reload.

+ +
+
+ +
+
+ + + + +
#define LTDC_VBReload   LTDC_SRCR_VBR
+
+

Vertical Blanking Reload.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___reload.map b/group___l_t_d_c___reload.map new file mode 100644 index 0000000..34a07e3 --- /dev/null +++ b/group___l_t_d_c___reload.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___reload.md5 b/group___l_t_d_c___reload.md5 new file mode 100644 index 0000000..c84d866 --- /dev/null +++ b/group___l_t_d_c___reload.md5 @@ -0,0 +1 @@ +5c4383432bbc2e963f51fcba3d332ebe \ No newline at end of file diff --git a/group___l_t_d_c___reload.png b/group___l_t_d_c___reload.png new file mode 100644 index 0000000..5d67727 Binary files /dev/null and b/group___l_t_d_c___reload.png differ diff --git a/group___l_t_d_c___s_y_n_c.html b/group___l_t_d_c___s_y_n_c.html new file mode 100644 index 0000000..7dc78b9 --- /dev/null +++ b/group___l_t_d_c___s_y_n_c.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: LTDC_SYNC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_SYNC
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_SYNC:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LTDC_HorizontalSYNC   ((uint32_t)0x00000FFF)
 
+#define LTDC_VerticalSYNC   ((uint32_t)0x000007FF)
 
+#define IS_LTDC_HSYNC(HSYNC)   ((HSYNC) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_VSYNC(VSYNC)   ((VSYNC) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_AHBP(AHBP)   ((AHBP) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_AVBP(AVBP)   ((AVBP) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_AAW(AAW)   ((AAW) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_AAH(AAH)   ((AAH) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_TOTALW(TOTALW)   ((TOTALW) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_TOTALH(TOTALH)   ((TOTALH) <= LTDC_VerticalSYNC)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___s_y_n_c.map b/group___l_t_d_c___s_y_n_c.map new file mode 100644 index 0000000..0cce87e --- /dev/null +++ b/group___l_t_d_c___s_y_n_c.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___s_y_n_c.md5 b/group___l_t_d_c___s_y_n_c.md5 new file mode 100644 index 0000000..91551ad --- /dev/null +++ b/group___l_t_d_c___s_y_n_c.md5 @@ -0,0 +1 @@ +40e922a2a20821a738fbebc23ba23996 \ No newline at end of file diff --git a/group___l_t_d_c___s_y_n_c.png b/group___l_t_d_c___s_y_n_c.png new file mode 100644 index 0000000..fc8fcaa Binary files /dev/null and b/group___l_t_d_c___s_y_n_c.png differ diff --git a/group___l_t_d_c___v_s_polarity.html b/group___l_t_d_c___v_s_polarity.html new file mode 100644 index 0000000..9f09810 --- /dev/null +++ b/group___l_t_d_c___v_s_polarity.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: LTDC_VSPolarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_VSPolarity
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_VSPolarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define LTDC_VSPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_VSPolarity_AH   LTDC_GCR_VSPOL
 
#define IS_LTDC_VSPOL(VSPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_LTDC_VSPOL( VSPOL)
+
+Value:
(((VSPOL) == LTDC_VSPolarity_AL) || \
+
((VSPOL) == LTDC_VSPolarity_AH))
+
LTDC_VSPolarity_AL
#define LTDC_VSPolarity_AL
Definition: stm32f4xx_ltdc.h:242
+
LTDC_VSPolarity_AH
#define LTDC_VSPolarity_AH
Definition: stm32f4xx_ltdc.h:243
+
+
+
+ +
+
+ + + + +
#define LTDC_VSPolarity_AH   LTDC_GCR_VSPOL
+
+

Vertical Synchronization is active high.

+ +
+
+ +
+
+ + + + +
#define LTDC_VSPolarity_AL   ((uint32_t)0x00000000)
+
+

Vertical Synchronization is active low.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c___v_s_polarity.map b/group___l_t_d_c___v_s_polarity.map new file mode 100644 index 0000000..2ce8091 --- /dev/null +++ b/group___l_t_d_c___v_s_polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c___v_s_polarity.md5 b/group___l_t_d_c___v_s_polarity.md5 new file mode 100644 index 0000000..489d8a6 --- /dev/null +++ b/group___l_t_d_c___v_s_polarity.md5 @@ -0,0 +1 @@ +42fe54ed09dd7c702cb1d649f5ab3f92 \ No newline at end of file diff --git a/group___l_t_d_c___v_s_polarity.png b/group___l_t_d_c___v_s_polarity.png new file mode 100644 index 0000000..3a8ed73 Binary files /dev/null and b/group___l_t_d_c___v_s_polarity.png differ diff --git a/group___l_t_d_c__colorkeying___config.html b/group___l_t_d_c__colorkeying___config.html new file mode 100644 index 0000000..bc3246c --- /dev/null +++ b/group___l_t_d_c__colorkeying___config.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: LTDC_colorkeying_Config + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
LTDC_colorkeying_Config
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for LTDC_colorkeying_Config:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LTDC_colorkeyingConfig   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_CKEYING(CKEYING)   ((CKEYING) <= LTDC_colorkeyingConfig)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___l_t_d_c__colorkeying___config.map b/group___l_t_d_c__colorkeying___config.map new file mode 100644 index 0000000..c398474 --- /dev/null +++ b/group___l_t_d_c__colorkeying___config.map @@ -0,0 +1,3 @@ + + + diff --git a/group___l_t_d_c__colorkeying___config.md5 b/group___l_t_d_c__colorkeying___config.md5 new file mode 100644 index 0000000..a534d67 --- /dev/null +++ b/group___l_t_d_c__colorkeying___config.md5 @@ -0,0 +1 @@ +7ebdea9d6e4b5cafa761b4d83c23fb3a \ No newline at end of file diff --git a/group___l_t_d_c__colorkeying___config.png b/group___l_t_d_c__colorkeying___config.png new file mode 100644 index 0000000..7eb94e1 Binary files /dev/null and b/group___l_t_d_c__colorkeying___config.png differ diff --git a/group___library__configuration__section.html b/group___library__configuration__section.html new file mode 100644 index 0000000..3d53e41 --- /dev/null +++ b/group___library__configuration__section.html @@ -0,0 +1,279 @@ + + + + + + +discoverpixy: Library_configuration_section + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Library_configuration_section
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Library_configuration_section:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define STM32F40_41xxx
 
#define USE_STDPERIPH_DRIVER
 Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers. More...
 
#define HSE_VALUE   ((uint32_t)8000000)
 In the following line adjust the value of External High Speed oscillator (HSE) used in your application. More...
 
#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x05000)
 In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value. More...
 
#define HSI_VALUE   ((uint32_t)16000000)
 
#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01)
 STM32F4XX Standard Peripherals Library version number V1.4.0. More...
 
#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x04)
 
#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00)
 
#define __STM32F4XX_STDPERIPH_VERSION_RC   (0x00)
 
#define __STM32F4XX_STDPERIPH_VERSION
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define __STM32F4XX_STDPERIPH_VERSION
+
+Value:
((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
+
|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
+
|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
+
|(__STM32F4XX_STDPERIPH_VERSION_RC))
+
__STM32F4XX_STDPERIPH_VERSION_SUB2
#define __STM32F4XX_STDPERIPH_VERSION_SUB2
Definition: stm32f4xx.h:146
+
__STM32F4XX_STDPERIPH_VERSION_RC
#define __STM32F4XX_STDPERIPH_VERSION_RC
Definition: stm32f4xx.h:147
+
__STM32F4XX_STDPERIPH_VERSION_SUB1
#define __STM32F4XX_STDPERIPH_VERSION_SUB1
Definition: stm32f4xx.h:145
+
__STM32F4XX_STDPERIPH_VERSION_MAIN
#define __STM32F4XX_STDPERIPH_VERSION_MAIN
STM32F4XX Standard Peripherals Library version number V1.4.0.
Definition: stm32f4xx.h:144
+
+
+
+ +
+
+ + + + +
#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01)
+
+ +

STM32F4XX Standard Peripherals Library version number V1.4.0.

+

[31:24] main version

+ +
+
+ +
+
+ + + + +
#define __STM32F4XX_STDPERIPH_VERSION_RC   (0x00)
+
+

[7:0] release candidate

+ +
+
+ +
+
+ + + + +
#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x04)
+
+

[23:16] sub1 version

+ +
+
+ +
+
+ + + + +
#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00)
+
+

[15:8] sub2 version

+ +
+
+ +
+
+ + + + +
#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x05000)
+
+ +

In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value.

+

Time out for HSE start up

+ +
+
+ +
+
+ + + + +
#define HSE_VALUE   ((uint32_t)8000000)
+
+ +

In the following line adjust the value of External High Speed oscillator (HSE) used in your application.

+

Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor.Value of the External oscillator in Hz

+ +
+
+ +
+
+ + + + +
#define HSI_VALUE   ((uint32_t)16000000)
+
+

Value of the Internal oscillator in Hz

+ +
+
+ +
+
+ + + + +
#define STM32F40_41xxx
+
+

STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices

+ +
+
+ +
+
+ + + + +
#define USE_STDPERIPH_DRIVER
+
+ +

Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers.

+

< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices

+

< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, STM32F439IG and STM32F439II Devices

+

< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices

+

< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___library__configuration__section.map b/group___library__configuration__section.map new file mode 100644 index 0000000..ced0eb8 --- /dev/null +++ b/group___library__configuration__section.map @@ -0,0 +1,3 @@ + + + diff --git a/group___library__configuration__section.md5 b/group___library__configuration__section.md5 new file mode 100644 index 0000000..54340c6 --- /dev/null +++ b/group___library__configuration__section.md5 @@ -0,0 +1 @@ +98c5fbf360997a828b882a0e65d308c2 \ No newline at end of file diff --git a/group___library__configuration__section.png b/group___library__configuration__section.png new file mode 100644 index 0000000..228862c Binary files /dev/null and b/group___library__configuration__section.png differ diff --git a/group___m_i_s_c.html b/group___m_i_s_c.html new file mode 100644 index 0000000..897f9e4 --- /dev/null +++ b/group___m_i_s_c.html @@ -0,0 +1,360 @@ + + + + + + +discoverpixy: MISC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
MISC
STM32F4xx_StdPeriph_Driver
+
+
+ +

MISC driver modules. +More...

+
+Collaboration diagram for MISC:
+
+
+ + +
+
+ + + + + + +

+Modules

 MISC_Exported_Constants
 
 MISC_Private_Functions
 
+ + + + +

+Classes

struct  NVIC_InitTypeDef
 NVIC Init Structure definition. More...
 
+ + + +

+Macros

+#define AIRCR_VECTKEY_MASK   ((uint32_t)0x05FA0000)
 
+ + + + + + + + + + + + + + + + +

+Functions

void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
 Configures the priority grouping: pre-emption priority and subpriority. More...
 
void NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
 Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. More...
 
void NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
 Sets the vector table location and Offset. More...
 
void NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
 Selects the condition for the system to enter low power mode. More...
 
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
 Configures the SysTick clock source. More...
 
+

Detailed Description

+

MISC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_Init (NVIC_InitTypeDef * NVIC_InitStruct)
+
+ +

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

+
Note
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
+
Parameters
+ + +
NVIC_InitStructpointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
+
+ +

Configures the priority grouping: pre-emption priority and subpriority.

+
Parameters
+ + +
NVIC_PriorityGroupspecifies the priority grouping bits length. This parameter can be one of the following values:
    +
  • NVIC_PriorityGroup_0: 0 bits for pre-emption priority 4 bits for subpriority
    • +
  • NVIC_PriorityGroup_1: 1 bits for pre-emption priority 3 bits for subpriority
    • +
  • NVIC_PriorityGroup_2: 2 bits for pre-emption priority 2 bits for subpriority
    • +
  • NVIC_PriorityGroup_3: 3 bits for pre-emption priority 1 bits for subpriority
    • +
  • NVIC_PriorityGroup_4: 4 bits for pre-emption priority 0 bits for subpriority
    • +
+
+
+
+
Note
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetVectorTable (uint32_t NVIC_VectTab,
uint32_t Offset 
)
+
+ +

Sets the vector table location and Offset.

+
Parameters
+ + + +
NVIC_VectTabspecifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:
    +
  • NVIC_VectTab_RAM: Vector Table in internal SRAM.
    • +
  • NVIC_VectTab_FLASH: Vector Table in internal FLASH.
    • +
+
OffsetVector Table base offset field. This value must be a multiple of 0x200.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SystemLPConfig (uint8_t LowPowerMode,
FunctionalState NewState 
)
+
+ +

Selects the condition for the system to enter low power mode.

+
Parameters
+ + + +
LowPowerModeSpecifies the new mode for the system to enter low power mode. This parameter can be one of the following values:
    +
  • NVIC_LP_SEVONPEND: Low Power SEV on Pend.
    • +
  • NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
    • +
  • NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
    • +
+
NewStatenew state of LP condition. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
+
+ +

Configures the SysTick clock source.

+
Parameters
+ + +
SysTick_CLKSourcespecifies the SysTick clock source. This parameter can be one of the following values:
    +
  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
    • +
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c.map b/group___m_i_s_c.map new file mode 100644 index 0000000..fb6f243 --- /dev/null +++ b/group___m_i_s_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___m_i_s_c.md5 b/group___m_i_s_c.md5 new file mode 100644 index 0000000..fc13d20 --- /dev/null +++ b/group___m_i_s_c.md5 @@ -0,0 +1 @@ +a627bd0a9a83217da36404f522f5d54b \ No newline at end of file diff --git a/group___m_i_s_c.png b/group___m_i_s_c.png new file mode 100644 index 0000000..003e9e8 Binary files /dev/null and b/group___m_i_s_c.png differ diff --git a/group___m_i_s_c___exported___constants.html b/group___m_i_s_c___exported___constants.html new file mode 100644 index 0000000..12edc8e --- /dev/null +++ b/group___m_i_s_c___exported___constants.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: MISC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
MISC_Exported_Constants
STM32F4xx_StdPeriph_Driver » MISC
+
+
+
+Collaboration diagram for MISC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + +

+Modules

 MISC_Vector_Table_Base
 
 MISC_System_Low_Power
 
 MISC_Preemption_Priority_Group
 
 MISC_SysTick_clock_source
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___exported___constants.map b/group___m_i_s_c___exported___constants.map new file mode 100644 index 0000000..2f7fa3a --- /dev/null +++ b/group___m_i_s_c___exported___constants.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___m_i_s_c___exported___constants.md5 b/group___m_i_s_c___exported___constants.md5 new file mode 100644 index 0000000..4aa7876 --- /dev/null +++ b/group___m_i_s_c___exported___constants.md5 @@ -0,0 +1 @@ +d99973e5bd032e3b5d09cd3f6f3f1648 \ No newline at end of file diff --git a/group___m_i_s_c___exported___constants.png b/group___m_i_s_c___exported___constants.png new file mode 100644 index 0000000..0aa5dba Binary files /dev/null and b/group___m_i_s_c___exported___constants.png differ diff --git a/group___m_i_s_c___preemption___priority___group.html b/group___m_i_s_c___preemption___priority___group.html new file mode 100644 index 0000000..3552526 --- /dev/null +++ b/group___m_i_s_c___preemption___priority___group.html @@ -0,0 +1,219 @@ + + + + + + +discoverpixy: MISC_Preemption_Priority_Group + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
MISC_Preemption_Priority_Group
STM32F4xx_StdPeriph_Driver » MISC » MISC_Exported_Constants
+
+
+
+Collaboration diagram for MISC_Preemption_Priority_Group:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define NVIC_PriorityGroup_0   ((uint32_t)0x700)
 
#define NVIC_PriorityGroup_1   ((uint32_t)0x600)
 
#define NVIC_PriorityGroup_2   ((uint32_t)0x500)
 
#define NVIC_PriorityGroup_3   ((uint32_t)0x400)
 
#define NVIC_PriorityGroup_4   ((uint32_t)0x300)
 
#define IS_NVIC_PRIORITY_GROUP(GROUP)
 
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)   ((PRIORITY) < 0x10)
 
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)   ((PRIORITY) < 0x10)
 
+#define IS_NVIC_OFFSET(OFFSET)   ((OFFSET) < 0x000FFFFF)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_NVIC_PRIORITY_GROUP( GROUP)
+
+Value:
(((GROUP) == NVIC_PriorityGroup_0) || \
+
((GROUP) == NVIC_PriorityGroup_1) || \
+
((GROUP) == NVIC_PriorityGroup_2) || \
+
((GROUP) == NVIC_PriorityGroup_3) || \
+
((GROUP) == NVIC_PriorityGroup_4))
+
NVIC_PriorityGroup_2
#define NVIC_PriorityGroup_2
Definition: misc.h:118
+
NVIC_PriorityGroup_0
#define NVIC_PriorityGroup_0
Definition: misc.h:112
+
NVIC_PriorityGroup_1
#define NVIC_PriorityGroup_1
Definition: misc.h:115
+
NVIC_PriorityGroup_4
#define NVIC_PriorityGroup_4
Definition: misc.h:124
+
NVIC_PriorityGroup_3
#define NVIC_PriorityGroup_3
Definition: misc.h:121
+
+
+
+ +
+
+ + + + +
#define NVIC_PriorityGroup_0   ((uint32_t)0x700)
+
+

0 bits for pre-emption priority 4 bits for subpriority

+ +
+
+ +
+
+ + + + +
#define NVIC_PriorityGroup_1   ((uint32_t)0x600)
+
+

1 bits for pre-emption priority 3 bits for subpriority

+ +
+
+ +
+
+ + + + +
#define NVIC_PriorityGroup_2   ((uint32_t)0x500)
+
+

2 bits for pre-emption priority 2 bits for subpriority

+ +
+
+ +
+
+ + + + +
#define NVIC_PriorityGroup_3   ((uint32_t)0x400)
+
+

3 bits for pre-emption priority 1 bits for subpriority

+ +
+
+ +
+
+ + + + +
#define NVIC_PriorityGroup_4   ((uint32_t)0x300)
+
+

4 bits for pre-emption priority 0 bits for subpriority

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___preemption___priority___group.map b/group___m_i_s_c___preemption___priority___group.map new file mode 100644 index 0000000..f093f5c --- /dev/null +++ b/group___m_i_s_c___preemption___priority___group.map @@ -0,0 +1,3 @@ + + + diff --git a/group___m_i_s_c___preemption___priority___group.md5 b/group___m_i_s_c___preemption___priority___group.md5 new file mode 100644 index 0000000..06244bd --- /dev/null +++ b/group___m_i_s_c___preemption___priority___group.md5 @@ -0,0 +1 @@ +45b26c2a38ca7df5e21eac118759115c \ No newline at end of file diff --git a/group___m_i_s_c___preemption___priority___group.png b/group___m_i_s_c___preemption___priority___group.png new file mode 100644 index 0000000..47a81de Binary files /dev/null and b/group___m_i_s_c___preemption___priority___group.png differ diff --git a/group___m_i_s_c___private___functions.html b/group___m_i_s_c___private___functions.html new file mode 100644 index 0000000..80c2ba3 --- /dev/null +++ b/group___m_i_s_c___private___functions.html @@ -0,0 +1,334 @@ + + + + + + +discoverpixy: MISC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
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+ +
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+Functions
+
+
MISC_Private_Functions
STM32F4xx_StdPeriph_Driver » MISC
+
+
+
+Collaboration diagram for MISC_Private_Functions:
+
+
+ + +
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+ + + + + + + + + + + + + + + + + +

+Functions

void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
 Configures the priority grouping: pre-emption priority and subpriority. More...
 
void NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
 Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. More...
 
void NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
 Sets the vector table location and Offset. More...
 
void NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
 Selects the condition for the system to enter low power mode. More...
 
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
 Configures the SysTick clock source. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_Init (NVIC_InitTypeDef * NVIC_InitStruct)
+
+ +

Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.

+
Note
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
+
Parameters
+ + +
NVIC_InitStructpointer to a NVIC_InitTypeDef structure that contains the configuration information for the specified NVIC peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
+
+ +

Configures the priority grouping: pre-emption priority and subpriority.

+
Parameters
+ + +
NVIC_PriorityGroupspecifies the priority grouping bits length. This parameter can be one of the following values:
    +
  • NVIC_PriorityGroup_0: 0 bits for pre-emption priority 4 bits for subpriority
    • +
  • NVIC_PriorityGroup_1: 1 bits for pre-emption priority 3 bits for subpriority
    • +
  • NVIC_PriorityGroup_2: 2 bits for pre-emption priority 2 bits for subpriority
    • +
  • NVIC_PriorityGroup_3: 3 bits for pre-emption priority 1 bits for subpriority
    • +
  • NVIC_PriorityGroup_4: 4 bits for pre-emption priority 0 bits for subpriority
    • +
+
+
+
+
Note
When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the subpriority.
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetVectorTable (uint32_t NVIC_VectTab,
uint32_t Offset 
)
+
+ +

Sets the vector table location and Offset.

+
Parameters
+ + + +
NVIC_VectTabspecifies if the vector table is in RAM or FLASH memory. This parameter can be one of the following values:
    +
  • NVIC_VectTab_RAM: Vector Table in internal SRAM.
    • +
  • NVIC_VectTab_FLASH: Vector Table in internal FLASH.
    • +
+
OffsetVector Table base offset field. This value must be a multiple of 0x200.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SystemLPConfig (uint8_t LowPowerMode,
FunctionalState NewState 
)
+
+ +

Selects the condition for the system to enter low power mode.

+
Parameters
+ + + +
LowPowerModeSpecifies the new mode for the system to enter low power mode. This parameter can be one of the following values:
    +
  • NVIC_LP_SEVONPEND: Low Power SEV on Pend.
    • +
  • NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
    • +
  • NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
    • +
+
NewStatenew state of LP condition. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
+
+ +

Configures the SysTick clock source.

+
Parameters
+ + +
SysTick_CLKSourcespecifies the SysTick clock source. This parameter can be one of the following values:
    +
  • SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
    • +
  • SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___private___functions.map b/group___m_i_s_c___private___functions.map new file mode 100644 index 0000000..11cc83e --- /dev/null +++ b/group___m_i_s_c___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___m_i_s_c___private___functions.md5 b/group___m_i_s_c___private___functions.md5 new file mode 100644 index 0000000..fe58bf7 --- /dev/null +++ b/group___m_i_s_c___private___functions.md5 @@ -0,0 +1 @@ +41ce05a1bff758de1507bde43b0ce589 \ No newline at end of file diff --git a/group___m_i_s_c___private___functions.png b/group___m_i_s_c___private___functions.png new file mode 100644 index 0000000..2d2a812 Binary files /dev/null and b/group___m_i_s_c___private___functions.png differ diff --git a/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map new file mode 100644 index 0000000..575c74b --- /dev/null +++ b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 new file mode 100644 index 0000000..1a6e5d1 --- /dev/null +++ b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 @@ -0,0 +1 @@ +d350b3f8188255ca87dbcdd5c800fde0 \ No newline at end of file diff --git a/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png new file mode 100644 index 0000000..6cd57e0 Binary files /dev/null and b/group___m_i_s_c___private___functions_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png differ diff --git a/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.map b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.map new file mode 100644 index 0000000..b030181 --- /dev/null +++ b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 new file mode 100644 index 0000000..72c2b1f --- /dev/null +++ b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 @@ -0,0 +1 @@ +066693802e763d19dfa49cf4728024d8 \ No newline at end of file diff --git a/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.png b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.png new file mode 100644 index 0000000..2550ab8 Binary files /dev/null and b/group___m_i_s_c___private___functions_gadfb1f34f803ce54c976643db8c484442_icgraph.png differ diff --git a/group___m_i_s_c___sys_tick__clock__source.html b/group___m_i_s_c___sys_tick__clock__source.html new file mode 100644 index 0000000..6618927 --- /dev/null +++ b/group___m_i_s_c___sys_tick__clock__source.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: MISC_SysTick_clock_source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
+ +
+ +
+
+Macros
+
+
MISC_SysTick_clock_source
STM32F4xx_StdPeriph_Driver » MISC » MISC_Exported_Constants
+
+
+
+Collaboration diagram for MISC_SysTick_clock_source:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SysTick_CLKSource_HCLK_Div8   ((uint32_t)0xFFFFFFFB)
 
+#define SysTick_CLKSource_HCLK   ((uint32_t)0x00000004)
 
#define IS_SYSTICK_CLK_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SYSTICK_CLK_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == SysTick_CLKSource_HCLK) || \
+
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___sys_tick__clock__source.map b/group___m_i_s_c___sys_tick__clock__source.map new file mode 100644 index 0000000..6fbc763 --- /dev/null +++ b/group___m_i_s_c___sys_tick__clock__source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___m_i_s_c___sys_tick__clock__source.md5 b/group___m_i_s_c___sys_tick__clock__source.md5 new file mode 100644 index 0000000..9f4de45 --- /dev/null +++ b/group___m_i_s_c___sys_tick__clock__source.md5 @@ -0,0 +1 @@ +7d792a0d037b351d1ea473da958fb4ce \ No newline at end of file diff --git a/group___m_i_s_c___sys_tick__clock__source.png b/group___m_i_s_c___sys_tick__clock__source.png new file mode 100644 index 0000000..588e605 Binary files /dev/null and b/group___m_i_s_c___sys_tick__clock__source.png differ diff --git a/group___m_i_s_c___system___low___power.html b/group___m_i_s_c___system___low___power.html new file mode 100644 index 0000000..672f2ab --- /dev/null +++ b/group___m_i_s_c___system___low___power.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: MISC_System_Low_Power + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+Macros
+
+
MISC_System_Low_Power
STM32F4xx_StdPeriph_Driver » MISC » MISC_Exported_Constants
+
+
+
+Collaboration diagram for MISC_System_Low_Power:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define NVIC_LP_SEVONPEND   ((uint8_t)0x10)
 
+#define NVIC_LP_SLEEPDEEP   ((uint8_t)0x04)
 
+#define NVIC_LP_SLEEPONEXIT   ((uint8_t)0x02)
 
#define IS_NVIC_LP(LP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_NVIC_LP( LP)
+
+Value:
(((LP) == NVIC_LP_SEVONPEND) || \
+
((LP) == NVIC_LP_SLEEPDEEP) || \
+
((LP) == NVIC_LP_SLEEPONEXIT))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___system___low___power.map b/group___m_i_s_c___system___low___power.map new file mode 100644 index 0000000..22a9a82 --- /dev/null +++ b/group___m_i_s_c___system___low___power.map @@ -0,0 +1,3 @@ + + + diff --git a/group___m_i_s_c___system___low___power.md5 b/group___m_i_s_c___system___low___power.md5 new file mode 100644 index 0000000..9ab7320 --- /dev/null +++ b/group___m_i_s_c___system___low___power.md5 @@ -0,0 +1 @@ +2a622f05359f6f387d90cb53c885f386 \ No newline at end of file diff --git a/group___m_i_s_c___system___low___power.png b/group___m_i_s_c___system___low___power.png new file mode 100644 index 0000000..743a7bb Binary files /dev/null and b/group___m_i_s_c___system___low___power.png differ diff --git a/group___m_i_s_c___vector___table___base.html b/group___m_i_s_c___vector___table___base.html new file mode 100644 index 0000000..a53f09f --- /dev/null +++ b/group___m_i_s_c___vector___table___base.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: MISC_Vector_Table_Base + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
MISC_Vector_Table_Base
STM32F4xx_StdPeriph_Driver » MISC » MISC_Exported_Constants
+
+
+
+Collaboration diagram for MISC_Vector_Table_Base:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define NVIC_VectTab_RAM   ((uint32_t)0x20000000)
 
+#define NVIC_VectTab_FLASH   ((uint32_t)0x08000000)
 
#define IS_NVIC_VECTTAB(VECTTAB)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_NVIC_VECTTAB( VECTTAB)
+
+Value:
(((VECTTAB) == NVIC_VectTab_RAM) || \
+
((VECTTAB) == NVIC_VectTab_FLASH))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___m_i_s_c___vector___table___base.map b/group___m_i_s_c___vector___table___base.map new file mode 100644 index 0000000..0dadce8 --- /dev/null +++ b/group___m_i_s_c___vector___table___base.map @@ -0,0 +1,3 @@ + + + diff --git a/group___m_i_s_c___vector___table___base.md5 b/group___m_i_s_c___vector___table___base.md5 new file mode 100644 index 0000000..7f77ddc --- /dev/null +++ b/group___m_i_s_c___vector___table___base.md5 @@ -0,0 +1 @@ +71f1251934b15e92f42d68621e38a873 \ No newline at end of file diff --git a/group___m_i_s_c___vector___table___base.png b/group___m_i_s_c___vector___table___base.png new file mode 100644 index 0000000..4f50515 Binary files /dev/null and b/group___m_i_s_c___vector___table___base.png differ diff --git a/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map new file mode 100644 index 0000000..575c74b --- /dev/null +++ b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 new file mode 100644 index 0000000..1a6e5d1 --- /dev/null +++ b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.md5 @@ -0,0 +1 @@ +d350b3f8188255ca87dbcdd5c800fde0 \ No newline at end of file diff --git a/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png new file mode 100644 index 0000000..6cd57e0 Binary files /dev/null and b/group___m_i_s_c_ga4ab373ed0870c06fca5eb51d639adf41_icgraph.png differ diff --git a/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.map b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.map new file mode 100644 index 0000000..b030181 --- /dev/null +++ b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 new file mode 100644 index 0000000..72c2b1f --- /dev/null +++ b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.md5 @@ -0,0 +1 @@ +066693802e763d19dfa49cf4728024d8 \ No newline at end of file diff --git a/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.png b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.png new file mode 100644 index 0000000..2550ab8 Binary files /dev/null and b/group___m_i_s_c_gadfb1f34f803ce54c976643db8c484442_icgraph.png differ diff --git a/group___number__of__valid__bits__in__last__word__of__the__message.html b/group___number__of__valid__bits__in__last__word__of__the__message.html new file mode 100644 index 0000000..8c59dd6 --- /dev/null +++ b/group___number__of__valid__bits__in__last__word__of__the__message.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Number_of_valid_bits_in_last_word_of_the_message + + + + + + + + + + +
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discoverpixy +
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+Macros
+
+
Number_of_valid_bits_in_last_word_of_the_message
STM32F4xx_StdPeriph_Driver » HASH » HASH_Exported_Constants
+
+
+
+Collaboration diagram for Number_of_valid_bits_in_last_word_of_the_message:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS)   ((VALIDBITS) <= 0x1F)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___number__of__valid__bits__in__last__word__of__the__message.map b/group___number__of__valid__bits__in__last__word__of__the__message.map new file mode 100644 index 0000000..b891551 --- /dev/null +++ b/group___number__of__valid__bits__in__last__word__of__the__message.map @@ -0,0 +1,3 @@ + + + diff --git a/group___number__of__valid__bits__in__last__word__of__the__message.md5 b/group___number__of__valid__bits__in__last__word__of__the__message.md5 new file mode 100644 index 0000000..b237a10 --- /dev/null +++ b/group___number__of__valid__bits__in__last__word__of__the__message.md5 @@ -0,0 +1 @@ +c98de765a872af80d3e3d4a5d62fa4c7 \ No newline at end of file diff --git a/group___number__of__valid__bits__in__last__word__of__the__message.png b/group___number__of__valid__bits__in__last__word__of__the__message.png new file mode 100644 index 0000000..79c5b6c Binary files /dev/null and b/group___number__of__valid__bits__in__last__word__of__the__message.png differ diff --git a/group___option___bytes___p_c___read_write___protection.html b/group___option___bytes___p_c___read_write___protection.html new file mode 100644 index 0000000..ffd0784 --- /dev/null +++ b/group___option___bytes___p_c___read_write___protection.html @@ -0,0 +1,485 @@ + + + + + + +discoverpixy: Option_Bytes_PC_ReadWrite_Protection + + + + + + + + + + +
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+Macros
+
+
Option_Bytes_PC_ReadWrite_Protection
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for Option_Bytes_PC_ReadWrite_Protection:
+
+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define OB_PCROP_Sector_0   ((uint32_t)0x00000001)
 
#define OB_PCROP_Sector_1   ((uint32_t)0x00000002)
 
#define OB_PCROP_Sector_2   ((uint32_t)0x00000004)
 
#define OB_PCROP_Sector_3   ((uint32_t)0x00000008)
 
#define OB_PCROP_Sector_4   ((uint32_t)0x00000010)
 
#define OB_PCROP_Sector_5   ((uint32_t)0x00000020)
 
#define OB_PCROP_Sector_6   ((uint32_t)0x00000040)
 
#define OB_PCROP_Sector_7   ((uint32_t)0x00000080)
 
#define OB_PCROP_Sector_8   ((uint32_t)0x00000100)
 
#define OB_PCROP_Sector_9   ((uint32_t)0x00000200)
 
#define OB_PCROP_Sector_10   ((uint32_t)0x00000400)
 
#define OB_PCROP_Sector_11   ((uint32_t)0x00000800)
 
#define OB_PCROP_Sector_12   ((uint32_t)0x00000001)
 
#define OB_PCROP_Sector_13   ((uint32_t)0x00000002)
 
#define OB_PCROP_Sector_14   ((uint32_t)0x00000004)
 
#define OB_PCROP_Sector_15   ((uint32_t)0x00000008)
 
#define OB_PCROP_Sector_16   ((uint32_t)0x00000010)
 
#define OB_PCROP_Sector_17   ((uint32_t)0x00000020)
 
#define OB_PCROP_Sector_18   ((uint32_t)0x00000040)
 
#define OB_PCROP_Sector_19   ((uint32_t)0x00000080)
 
#define OB_PCROP_Sector_20   ((uint32_t)0x00000100)
 
#define OB_PCROP_Sector_21   ((uint32_t)0x00000200)
 
#define OB_PCROP_Sector_22   ((uint32_t)0x00000400)
 
#define OB_PCROP_Sector_23   ((uint32_t)0x00000800)
 
#define OB_PCROP_Sector_All   ((uint32_t)0x00000FFF)
 
+#define IS_OB_PCROP(SECTOR)   ((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_PCROP_Sector_0   ((uint32_t)0x00000001)
+
+

PC Read/Write protection of Sector0

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_1   ((uint32_t)0x00000002)
+
+

PC Read/Write protection of Sector1

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_10   ((uint32_t)0x00000400)
+
+

PC Read/Write protection of Sector10

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_11   ((uint32_t)0x00000800)
+
+

PC Read/Write protection of Sector11

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_12   ((uint32_t)0x00000001)
+
+

PC Read/Write protection of Sector12

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_13   ((uint32_t)0x00000002)
+
+

PC Read/Write protection of Sector13

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_14   ((uint32_t)0x00000004)
+
+

PC Read/Write protection of Sector14

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_15   ((uint32_t)0x00000008)
+
+

PC Read/Write protection of Sector15

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_16   ((uint32_t)0x00000010)
+
+

PC Read/Write protection of Sector16

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_17   ((uint32_t)0x00000020)
+
+

PC Read/Write protection of Sector17

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_18   ((uint32_t)0x00000040)
+
+

PC Read/Write protection of Sector18

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_19   ((uint32_t)0x00000080)
+
+

PC Read/Write protection of Sector19

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_2   ((uint32_t)0x00000004)
+
+

PC Read/Write protection of Sector2

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_20   ((uint32_t)0x00000100)
+
+

PC Read/Write protection of Sector20

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_21   ((uint32_t)0x00000200)
+
+

PC Read/Write protection of Sector21

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_22   ((uint32_t)0x00000400)
+
+

PC Read/Write protection of Sector22

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_23   ((uint32_t)0x00000800)
+
+

PC Read/Write protection of Sector23

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_3   ((uint32_t)0x00000008)
+
+

PC Read/Write protection of Sector3

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_4   ((uint32_t)0x00000010)
+
+

PC Read/Write protection of Sector4

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_5   ((uint32_t)0x00000020)
+
+

PC Read/Write protection of Sector5

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_6   ((uint32_t)0x00000040)
+
+

PC Read/Write protection of Sector6

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_7   ((uint32_t)0x00000080)
+
+

PC Read/Write protection of Sector7

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_8   ((uint32_t)0x00000100)
+
+

PC Read/Write protection of Sector8

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_9   ((uint32_t)0x00000200)
+
+

PC Read/Write protection of Sector9

+ +
+
+ +
+
+ + + + +
#define OB_PCROP_Sector_All   ((uint32_t)0x00000FFF)
+
+

PC Read/Write protection of all Sectors

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___option___bytes___p_c___read_write___protection.map b/group___option___bytes___p_c___read_write___protection.map new file mode 100644 index 0000000..ef51835 --- /dev/null +++ b/group___option___bytes___p_c___read_write___protection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___option___bytes___p_c___read_write___protection.md5 b/group___option___bytes___p_c___read_write___protection.md5 new file mode 100644 index 0000000..4e672b3 --- /dev/null +++ b/group___option___bytes___p_c___read_write___protection.md5 @@ -0,0 +1 @@ +b7ce8cf4364a61b8c6d5d6e14731bae9 \ No newline at end of file diff --git a/group___option___bytes___p_c___read_write___protection.png b/group___option___bytes___p_c___read_write___protection.png new file mode 100644 index 0000000..f58e588 Binary files /dev/null and b/group___option___bytes___p_c___read_write___protection.png differ diff --git a/group___option___bytes___write___protection.html b/group___option___bytes___write___protection.html new file mode 100644 index 0000000..b77c08e --- /dev/null +++ b/group___option___bytes___write___protection.html @@ -0,0 +1,485 @@ + + + + + + +discoverpixy: Option_Bytes_Write_Protection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Option_Bytes_Write_Protection
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for Option_Bytes_Write_Protection:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define OB_WRP_Sector_0   ((uint32_t)0x00000001)
 
#define OB_WRP_Sector_1   ((uint32_t)0x00000002)
 
#define OB_WRP_Sector_2   ((uint32_t)0x00000004)
 
#define OB_WRP_Sector_3   ((uint32_t)0x00000008)
 
#define OB_WRP_Sector_4   ((uint32_t)0x00000010)
 
#define OB_WRP_Sector_5   ((uint32_t)0x00000020)
 
#define OB_WRP_Sector_6   ((uint32_t)0x00000040)
 
#define OB_WRP_Sector_7   ((uint32_t)0x00000080)
 
#define OB_WRP_Sector_8   ((uint32_t)0x00000100)
 
#define OB_WRP_Sector_9   ((uint32_t)0x00000200)
 
#define OB_WRP_Sector_10   ((uint32_t)0x00000400)
 
#define OB_WRP_Sector_11   ((uint32_t)0x00000800)
 
#define OB_WRP_Sector_12   ((uint32_t)0x00000001)
 
#define OB_WRP_Sector_13   ((uint32_t)0x00000002)
 
#define OB_WRP_Sector_14   ((uint32_t)0x00000004)
 
#define OB_WRP_Sector_15   ((uint32_t)0x00000008)
 
#define OB_WRP_Sector_16   ((uint32_t)0x00000010)
 
#define OB_WRP_Sector_17   ((uint32_t)0x00000020)
 
#define OB_WRP_Sector_18   ((uint32_t)0x00000040)
 
#define OB_WRP_Sector_19   ((uint32_t)0x00000080)
 
#define OB_WRP_Sector_20   ((uint32_t)0x00000100)
 
#define OB_WRP_Sector_21   ((uint32_t)0x00000200)
 
#define OB_WRP_Sector_22   ((uint32_t)0x00000400)
 
#define OB_WRP_Sector_23   ((uint32_t)0x00000800)
 
#define OB_WRP_Sector_All   ((uint32_t)0x00000FFF)
 
+#define IS_OB_WRP(SECTOR)   ((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_WRP_Sector_0   ((uint32_t)0x00000001)
+
+

Write protection of Sector0

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_1   ((uint32_t)0x00000002)
+
+

Write protection of Sector1

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_10   ((uint32_t)0x00000400)
+
+

Write protection of Sector10

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_11   ((uint32_t)0x00000800)
+
+

Write protection of Sector11

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_12   ((uint32_t)0x00000001)
+
+

Write protection of Sector12

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_13   ((uint32_t)0x00000002)
+
+

Write protection of Sector13

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_14   ((uint32_t)0x00000004)
+
+

Write protection of Sector14

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_15   ((uint32_t)0x00000008)
+
+

Write protection of Sector15

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_16   ((uint32_t)0x00000010)
+
+

Write protection of Sector16

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_17   ((uint32_t)0x00000020)
+
+

Write protection of Sector17

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_18   ((uint32_t)0x00000040)
+
+

Write protection of Sector18

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_19   ((uint32_t)0x00000080)
+
+

Write protection of Sector19

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_2   ((uint32_t)0x00000004)
+
+

Write protection of Sector2

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_20   ((uint32_t)0x00000100)
+
+

Write protection of Sector20

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_21   ((uint32_t)0x00000200)
+
+

Write protection of Sector21

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_22   ((uint32_t)0x00000400)
+
+

Write protection of Sector22

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_23   ((uint32_t)0x00000800)
+
+

Write protection of Sector23

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_3   ((uint32_t)0x00000008)
+
+

Write protection of Sector3

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_4   ((uint32_t)0x00000010)
+
+

Write protection of Sector4

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_5   ((uint32_t)0x00000020)
+
+

Write protection of Sector5

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_6   ((uint32_t)0x00000040)
+
+

Write protection of Sector6

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_7   ((uint32_t)0x00000080)
+
+

Write protection of Sector7

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_8   ((uint32_t)0x00000100)
+
+

Write protection of Sector8

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_9   ((uint32_t)0x00000200)
+
+

Write protection of Sector9

+ +
+
+ +
+
+ + + + +
#define OB_WRP_Sector_All   ((uint32_t)0x00000FFF)
+
+

Write protection of all Sectors

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___option___bytes___write___protection.map b/group___option___bytes___write___protection.map new file mode 100644 index 0000000..835db46 --- /dev/null +++ b/group___option___bytes___write___protection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___option___bytes___write___protection.md5 b/group___option___bytes___write___protection.md5 new file mode 100644 index 0000000..ff200dc --- /dev/null +++ b/group___option___bytes___write___protection.md5 @@ -0,0 +1 @@ +7afb0ac06dfc70e01dcb12c3860abccb \ No newline at end of file diff --git a/group___option___bytes___write___protection.png b/group___option___bytes___write___protection.png new file mode 100644 index 0000000..11225ae Binary files /dev/null and b/group___option___bytes___write___protection.png differ diff --git a/group___p_w_r.html b/group___p_w_r.html new file mode 100644 index 0000000..e4f4127 --- /dev/null +++ b/group___p_w_r.html @@ -0,0 +1,908 @@ + + + + + + +discoverpixy: PWR + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros | +Functions
+
+
PWR
STM32F4xx_StdPeriph_Driver
+
+
+ +

PWR driver modules. +More...

+
+Collaboration diagram for PWR:
+
+
+ + +
+
+ + + + + + +

+Modules

 PWR_Exported_Constants
 
 PWR_Private_Functions
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define PWR_OFFSET   (PWR_BASE - PERIPH_BASE)
 
+#define CR_OFFSET   (PWR_OFFSET + 0x00)
 
+#define DBP_BitNumber   0x08
 
+#define CR_DBP_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
 
+#define PVDE_BitNumber   0x04
 
+#define CR_PVDE_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
 
+#define FPDS_BitNumber   0x09
 
+#define CR_FPDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
 
+#define PMODE_BitNumber   0x0E
 
+#define CR_PMODE_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
 
+#define ODEN_BitNumber   0x10
 
+#define CR_ODEN_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
 
+#define ODSWEN_BitNumber   0x11
 
+#define CR_ODSWEN_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
 
+#define MRLVDS_BitNumber   0x0B
 
+#define CR_MRLVDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
 
+#define LPLVDS_BitNumber   0x0A
 
+#define CR_LPLVDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
 
+#define CSR_OFFSET   (PWR_OFFSET + 0x04)
 
+#define EWUP_BitNumber   0x08
 
+#define CSR_EWUP_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
 
+#define BRE_BitNumber   0x09
 
+#define CSR_BRE_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
 
+#define CR_DS_MASK   ((uint32_t)0xFFFFF3FC)
 
+#define CR_PLS_MASK   ((uint32_t)0xFFFFFF1F)
 
+#define CR_VOS_MASK   ((uint32_t)0xFFFF3FFF)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void PWR_DeInit (void)
 Deinitializes the PWR peripheral registers to their default reset values. More...
 
void PWR_BackupAccessCmd (FunctionalState NewState)
 Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM). More...
 
void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
 Configures the voltage threshold detected by the Power Voltage Detector(PVD). More...
 
void PWR_PVDCmd (FunctionalState NewState)
 Enables or disables the Power Voltage Detector(PVD). More...
 
void PWR_WakeUpPinCmd (FunctionalState NewState)
 Enables or disables the WakeUp Pin functionality. More...
 
void PWR_BackupRegulatorCmd (FunctionalState NewState)
 Enables or disables the Backup Regulator. More...
 
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
 Configures the main internal regulator output voltage. More...
 
void PWR_OverDriveCmd (FunctionalState NewState)
 Enables or disables the Over-Drive. More...
 
void PWR_OverDriveSWCmd (FunctionalState NewState)
 Enables or disables the Over-Drive switching. More...
 
void PWR_UnderDriveCmd (FunctionalState NewState)
 Enables or disables the Under-Drive mode. More...
 
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Main Regulator low voltage mode. More...
 
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Low Power Regulator low voltage mode. More...
 
void PWR_FlashPowerDownCmd (FunctionalState NewState)
 Enables or disables the Flash Power Down in STOP mode. More...
 
void PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters STOP mode. More...
 
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters in Under-Drive STOP mode. More...
 
void PWR_EnterSTANDBYMode (void)
 Enters STANDBY mode. More...
 
FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
 Checks whether the specified PWR flag is set or not. More...
 
void PWR_ClearFlag (uint32_t PWR_FLAG)
 Clears the PWR's pending flags. More...
 
+

Detailed Description

+

PWR driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_BackupAccessCmd (FunctionalState NewState)
+
+ +

Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

+
Note
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
+
Parameters
+ + +
NewStatenew state of the access to the backup domain. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_BackupRegulatorCmd (FunctionalState NewState)
+
+ +

Enables or disables the Backup Regulator.

+
Parameters
+ + +
NewStatenew state of the Backup Regulator. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_ClearFlag (uint32_t PWR_FLAG)
+
+ +

Clears the PWR's pending flags.

+
Parameters
+ + +
PWR_FLAGspecifies the flag to clear. This parameter can be one of the following values:
    +
  • PWR_FLAG_WU: Wake Up flag
    • +
  • PWR_FLAG_SB: StandBy flag
    • +
  • PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_DeInit (void )
+
+ +

Deinitializes the PWR peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void PWR_EnterSTANDBYMode (void )
+
+ +

Enters STANDBY mode.

+
Note
In Standby mode, all I/O pins are high impedance except for:
    +
  • Reset pad (still available)
    • +
  • RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC Alarm out, or RTC clock calibration out.
    • +
  • RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
    • +
  • WKUP pin 1 (PA0) if enabled.
    • +
+
+
+The Wakeup flag (WUF) need to be cleared at application level before to call this function
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void PWR_EnterSTOPMode (uint32_t PWR_Regulator,
uint8_t PWR_STOPEntry 
)
+
+ +

Enters STOP mode.

+
Note
In Stop mode, all I/O pins keep the same state as in Run mode.
+
+When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
+
+When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
+
Parameters
+ + + +
PWR_Regulatorspecifies the regulator state in STOP mode. This parameter can be one of the following values:
    +
  • PWR_MainRegulator_ON: STOP mode with regulator ON
    • +
  • PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
    • +
+
PWR_STOPEntryspecifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
    +
  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
    • +
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator,
uint8_t PWR_STOPEntry 
)
+
+ +

Enters in Under-Drive STOP mode.

+
Note
This mode is only available for STM32F42xxx/STM3243xxx devices.
+
+This mode can be selected only when the Under-Drive is already active
+
+In Stop mode, all I/O pins keep the same state as in Run mode.
+
+When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
+
+When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
+
Parameters
+ + + +
PWR_Regulatorspecifies the regulator state in STOP mode. This parameter can be one of the following values:
    +
  • PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
    • +
  • PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
    • +
+
PWR_STOPEntryspecifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
    +
  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
    • +
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_FlashPowerDownCmd (FunctionalState NewState)
+
+ +

Enables or disables the Flash Power Down in STOP mode.

+
Parameters
+ + +
NewStatenew state of the Flash power mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
+
+ +

Checks whether the specified PWR flag is set or not.

+
Parameters
+ + +
PWR_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
    • +
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
    • +
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the PWR_PVDCmd() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
    • +
  • PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
    • +
  • PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
    • +
  • PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode is ready (STM32F42xxx/43xxx devices)
    • +
  • PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode switcching is ready (STM32F42xxx/43xxx devices)
    • +
  • PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode is enabled in Stop mode (STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
Thenew state of PWR_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
+
+ +

Enables or disables the Low Power Regulator low voltage mode.

+
Note
This mode is only available for STM32F401xx/STM32F411xx devices.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
+
+ +

Enables or disables the Main Regulator low voltage mode.

+
Note
This mode is only available for STM32F401xx/STM32F411xx devices.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
+
+ +

Configures the main internal regulator output voltage.

+
Parameters
+ + +
PWR_Regulator_Voltagespecifies the regulator output voltage to achieve a tradeoff between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheets for more details). This parameter can be one of the following values:
    +
  • PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, System frequency up to 168 MHz.
    • +
  • PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, System frequency up to 144 MHz.
    • +
  • PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_OverDriveCmd (FunctionalState NewState)
+
+ +

Enables or disables the Over-Drive.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices. This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
+
+It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.
+
Parameters
+ + +
NewStatenew state of the Over Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_OverDriveSWCmd (FunctionalState NewState)
+
+ +

Enables or disables the Over-Drive switching.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices.
+
Parameters
+ + +
NewStatenew state of the Over Drive switching mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_PVDCmd (FunctionalState NewState)
+
+ +

Enables or disables the Power Voltage Detector(PVD).

+
Parameters
+ + +
NewStatenew state of the PVD. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
+
+ +

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

+
Parameters
+ + +
PWR_PVDLevelspecifies the PVD detection level This parameter can be one of the following values:
    +
  • PWR_PVDLevel_0
    • +
  • PWR_PVDLevel_1
    • +
  • PWR_PVDLevel_2
    • +
  • PWR_PVDLevel_3
    • +
  • PWR_PVDLevel_4
    • +
  • PWR_PVDLevel_5
    • +
  • PWR_PVDLevel_6
    • +
  • PWR_PVDLevel_7
    • +
+
+
+
+
Note
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_UnderDriveCmd (FunctionalState NewState)
+
+ +

Enables or disables the Under-Drive mode.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices.
+
+This mode is enabled only with STOP low power mode. In this mode, the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode
+
+If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode. When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_WakeUpPinCmd (FunctionalState NewState)
+
+ +

Enables or disables the WakeUp Pin functionality.

+
Parameters
+ + +
NewStatenew state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r.map b/group___p_w_r.map new file mode 100644 index 0000000..420ccd0 --- /dev/null +++ b/group___p_w_r.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___p_w_r.md5 b/group___p_w_r.md5 new file mode 100644 index 0000000..98b7d76 --- /dev/null +++ b/group___p_w_r.md5 @@ -0,0 +1 @@ +68df84356e5e3f1c4f99bdcb1c3a0b04 \ No newline at end of file diff --git a/group___p_w_r.png b/group___p_w_r.png new file mode 100644 index 0000000..8ccfbed Binary files /dev/null and b/group___p_w_r.png differ diff --git a/group___p_w_r___exported___constants.html b/group___p_w_r___exported___constants.html new file mode 100644 index 0000000..6741ed8 --- /dev/null +++ b/group___p_w_r___exported___constants.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: PWR_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
PWR_Exported_Constants
STM32F4xx_StdPeriph_Driver » PWR
+
+
+
+Collaboration diagram for PWR_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 PWR_PVD_detection_level
 
 PWR_Regulator_state_in_STOP_mode
 
 PWR_Regulator_state_in_UnderDrive_mode
 
 PWR_STOP_mode_entry
 
 PWR_Regulator_Voltage_Scale
 
 PWR_Flag
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___exported___constants.map b/group___p_w_r___exported___constants.map new file mode 100644 index 0000000..b0b9a75 --- /dev/null +++ b/group___p_w_r___exported___constants.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/group___p_w_r___exported___constants.md5 b/group___p_w_r___exported___constants.md5 new file mode 100644 index 0000000..a62e9b4 --- /dev/null +++ b/group___p_w_r___exported___constants.md5 @@ -0,0 +1 @@ +9e472c9c1675cc0471594eb88609b2a1 \ No newline at end of file diff --git a/group___p_w_r___exported___constants.png b/group___p_w_r___exported___constants.png new file mode 100644 index 0000000..40fcfe5 Binary files /dev/null and b/group___p_w_r___exported___constants.png differ diff --git a/group___p_w_r___flag.html b/group___p_w_r___flag.html new file mode 100644 index 0000000..883afb2 --- /dev/null +++ b/group___p_w_r___flag.html @@ -0,0 +1,176 @@ + + + + + + +discoverpixy: PWR_Flag + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_Flag
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_Flag:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define PWR_FLAG_WU   PWR_CSR_WUF
 
+#define PWR_FLAG_SB   PWR_CSR_SBF
 
+#define PWR_FLAG_PVDO   PWR_CSR_PVDO
 
+#define PWR_FLAG_BRR   PWR_CSR_BRR
 
+#define PWR_FLAG_VOSRDY   PWR_CSR_VOSRDY
 
+#define PWR_FLAG_ODRDY   PWR_CSR_ODRDY
 
+#define PWR_FLAG_ODSWRDY   PWR_CSR_ODSWRDY
 
+#define PWR_FLAG_UDRDY   PWR_CSR_UDSWRDY
 
+#define PWR_FLAG_REGRDY   PWR_FLAG_VOSRDY
 
#define IS_PWR_GET_FLAG(FLAG)
 
#define IS_PWR_CLEAR_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_PWR_CLEAR_FLAG( FLAG)
+
+Value:
(((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+
((FLAG) == PWR_FLAG_UDRDY))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_PWR_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
+
((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
+
((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___flag.map b/group___p_w_r___flag.map new file mode 100644 index 0000000..33ff591 --- /dev/null +++ b/group___p_w_r___flag.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___flag.md5 b/group___p_w_r___flag.md5 new file mode 100644 index 0000000..209cb76 --- /dev/null +++ b/group___p_w_r___flag.md5 @@ -0,0 +1 @@ +25d7071b4f65f11a110ed5ab5a1bdb52 \ No newline at end of file diff --git a/group___p_w_r___flag.png b/group___p_w_r___flag.png new file mode 100644 index 0000000..35f2503 Binary files /dev/null and b/group___p_w_r___flag.png differ diff --git a/group___p_w_r___group1.html b/group___p_w_r___group1.html new file mode 100644 index 0000000..0b40cf5 --- /dev/null +++ b/group___p_w_r___group1.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: Backup Domain Access function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Functions
+
+
Backup Domain Access function
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

Backup Domain Access function. +More...

+
+Collaboration diagram for Backup Domain Access function:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void PWR_DeInit (void)
 Deinitializes the PWR peripheral registers to their default reset values. More...
 
void PWR_BackupAccessCmd (FunctionalState NewState)
 Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM). More...
 
+

Detailed Description

+

Backup Domain Access function.

+
 ===============================================================================
+                  ##### Backup Domain Access function #####
+ ===============================================================================  
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted 
+      write accesses. 
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            RCC_APB1PeriphClockCmd() function.
+        (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_BackupAccessCmd (FunctionalState NewState)
+
+ +

Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM).

+
Note
If the HSE divided by 2, 3, ..31 is used as the RTC clock, the Backup Domain Access should be kept enabled.
+
Parameters
+ + +
NewStatenew state of the access to the backup domain. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_DeInit (void )
+
+ +

Deinitializes the PWR peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group1.map b/group___p_w_r___group1.map new file mode 100644 index 0000000..1cd9f12 --- /dev/null +++ b/group___p_w_r___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group1.md5 b/group___p_w_r___group1.md5 new file mode 100644 index 0000000..be1eac8 --- /dev/null +++ b/group___p_w_r___group1.md5 @@ -0,0 +1 @@ +73859f4d3f9cda40fe3666a4978eb132 \ No newline at end of file diff --git a/group___p_w_r___group1.png b/group___p_w_r___group1.png new file mode 100644 index 0000000..852b6ae Binary files /dev/null and b/group___p_w_r___group1.png differ diff --git a/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.map b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.map new file mode 100644 index 0000000..5caff01 --- /dev/null +++ b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.md5 b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.md5 new file mode 100644 index 0000000..10a1991 --- /dev/null +++ b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.md5 @@ -0,0 +1 @@ +7b1266b04f64cff3a87f3751fbd28dd7 \ No newline at end of file diff --git a/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.png b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.png new file mode 100644 index 0000000..293050c Binary files /dev/null and b/group___p_w_r___group1_gad03a0aac7bc3bc3a9fd012f3769a6990_cgraph.png differ diff --git a/group___p_w_r___group2.html b/group___p_w_r___group2.html new file mode 100644 index 0000000..d0f7d39 --- /dev/null +++ b/group___p_w_r___group2.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: PVD configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
PVD configuration functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

PVD configuration functions. +More...

+
+Collaboration diagram for PVD configuration functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
 Configures the voltage threshold detected by the Power Voltage Detector(PVD). More...
 
void PWR_PVDCmd (FunctionalState NewState)
 Enables or disables the Power Voltage Detector(PVD). More...
 
+

Detailed Description

+

PVD configuration functions.

+
 ===============================================================================
+                    ##### PVD configuration functions #####
+ ===============================================================================  
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+          than the PVD threshold. This event is internally connected to the EXTI 
+          line16 and can generate an interrupt if enabled through the EXTI registers.
+      (+) The PVD is stopped in Standby mode.

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_PVDCmd (FunctionalState NewState)
+
+ +

Enables or disables the Power Voltage Detector(PVD).

+
Parameters
+ + +
NewStatenew state of the PVD. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
+
+ +

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

+
Parameters
+ + +
PWR_PVDLevelspecifies the PVD detection level This parameter can be one of the following values:
    +
  • PWR_PVDLevel_0
    • +
  • PWR_PVDLevel_1
    • +
  • PWR_PVDLevel_2
    • +
  • PWR_PVDLevel_3
    • +
  • PWR_PVDLevel_4
    • +
  • PWR_PVDLevel_5
    • +
  • PWR_PVDLevel_6
    • +
  • PWR_PVDLevel_7
    • +
+
+
+
+
Note
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group2.map b/group___p_w_r___group2.map new file mode 100644 index 0000000..f517920 --- /dev/null +++ b/group___p_w_r___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group2.md5 b/group___p_w_r___group2.md5 new file mode 100644 index 0000000..94f84c7 --- /dev/null +++ b/group___p_w_r___group2.md5 @@ -0,0 +1 @@ +ce09479503c65c075d6e5eb02be59cac \ No newline at end of file diff --git a/group___p_w_r___group2.png b/group___p_w_r___group2.png new file mode 100644 index 0000000..2fc7386 Binary files /dev/null and b/group___p_w_r___group2.png differ diff --git a/group___p_w_r___group3.html b/group___p_w_r___group3.html new file mode 100644 index 0000000..700596a --- /dev/null +++ b/group___p_w_r___group3.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: WakeUp pin configuration functions + + + + + + + + + + +
+
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+Functions
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+
WakeUp pin configuration functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

WakeUp pin configuration functions. +More...

+
+Collaboration diagram for WakeUp pin configuration functions:
+
+
+ + +
+
+ + + + + +

+Functions

void PWR_WakeUpPinCmd (FunctionalState NewState)
 Enables or disables the WakeUp Pin functionality. More...
 
+

Detailed Description

+

WakeUp pin configuration functions.

+
 ===============================================================================
+                 ##### WakeUp pin configuration functions #####
+ ===============================================================================  
+    [..]
+      (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is 
+          forced in input pull down configuration and is active on rising edges.
+      (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_WakeUpPinCmd (FunctionalState NewState)
+
+ +

Enables or disables the WakeUp Pin functionality.

+
Parameters
+ + +
NewStatenew state of the WakeUp Pin functionality. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group3.map b/group___p_w_r___group3.map new file mode 100644 index 0000000..9e6df62 --- /dev/null +++ b/group___p_w_r___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group3.md5 b/group___p_w_r___group3.md5 new file mode 100644 index 0000000..3645a61 --- /dev/null +++ b/group___p_w_r___group3.md5 @@ -0,0 +1 @@ +b8d3cd713f44ce96b10ab575c011c263 \ No newline at end of file diff --git a/group___p_w_r___group3.png b/group___p_w_r___group3.png new file mode 100644 index 0000000..bba4869 Binary files /dev/null and b/group___p_w_r___group3.png differ diff --git a/group___p_w_r___group4.html b/group___p_w_r___group4.html new file mode 100644 index 0000000..eafb3c1 --- /dev/null +++ b/group___p_w_r___group4.html @@ -0,0 +1,427 @@ + + + + + + +discoverpixy: Main and Backup Regulators configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
Main and Backup Regulators configuration functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

Main and Backup Regulators configuration functions. +More...

+
+Collaboration diagram for Main and Backup Regulators configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void PWR_BackupRegulatorCmd (FunctionalState NewState)
 Enables or disables the Backup Regulator. More...
 
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
 Configures the main internal regulator output voltage. More...
 
void PWR_OverDriveCmd (FunctionalState NewState)
 Enables or disables the Over-Drive. More...
 
void PWR_OverDriveSWCmd (FunctionalState NewState)
 Enables or disables the Over-Drive switching. More...
 
void PWR_UnderDriveCmd (FunctionalState NewState)
 Enables or disables the Under-Drive mode. More...
 
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Main Regulator low voltage mode. More...
 
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Low Power Regulator low voltage mode. More...
 
+

Detailed Description

+

Main and Backup Regulators configuration functions.

+
 ===============================================================================
+          ##### Main and Backup Regulators configuration functions #####
+ ===============================================================================  
+    [..]
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+          retained even in Standby or VBAT mode when the low power backup regulator
+          is enabled. It can be considered as an internal EEPROM when VBAT is 
+          always present. You can use the PWR_BackupRegulatorCmd() function to 
+          enable the low power backup regulator and use the PWR_GetFlagStatus
+          (PWR_FLAG_BRR) to check if it is ready or not. 
+
+      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+          save battery life.
+
+      (+) The backup SRAM is not mass erased by an tamper event. It is read 
+          protected to prevent confidential data, such as cryptographic private 
+          key, from being accessed. The backup SRAM can be erased only through 
+          the Flash interface when a protection level change from level 1 to 
+          level 0 is requested. 
+      -@- Refer to the description of Read protection (RDP) in the reference manual.
+
+      (+) The main internal regulator can be configured to have a tradeoff between 
+          performance and power consumption when the device does not operate at 
+          the maximum frequency. 
+      (+) For STM32F405xx/407xx and STM32F415xx/417xx  Devices, the regulator can be     
+          configured on the fly through PWR_MainRegulatorModeConfig() function which  
+          configure VOS bit in PWR_CR register:
+        (++) When this bit is set (Regulator voltage output Scale 1 mode selected) 
+             the System frequency can go up to 168 MHz. 
+        (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) 
+             the System frequency can go up to 144 MHz.
+             
+       (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through    
+           PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
+           PWR_CR register:  
+           which configure VOS[1:0] bits in PWR_CR register: 
+        (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) 
+             the System frequency can go up to 168 MHz. 
+        (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) 
+             the System frequency can go up to 144 MHz.  
+        (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) 
+             the System frequency can go up to 120 MHz. 
+                          
+       (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL 
+           is OFF and the HSI or HSE clock source is selected as system clock. 
+           The new value programmed is active only when the PLL is ON.
+           When the PLL is OFF, the voltage scale 3 is automatically selected. 
+        Refer to the datasheets for more details.
+        
+       (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
+           2 operating modes available:
+        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+             voltage scaling (scale 1, scale 2 or scale 3)
+        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+            higher frequency than the normal mode for a given voltage scaling (scale 1,  
+            scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
+            PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow 
+            the sequence described in Reference manual.
+             
+       (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator 
+           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
+           and internal SRAM. 2 operating modes are available:
+         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+              available when the main regulator or the low power regulator is used in Scale 3 or 
+              low voltage mode.
+         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+              available when the main regulator or the low power regulator is in low voltage mode.
+              This mode is enabled through PWR_UnderDriveCmd() function.

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_BackupRegulatorCmd (FunctionalState NewState)
+
+ +

Enables or disables the Backup Regulator.

+
Parameters
+ + +
NewStatenew state of the Backup Regulator. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
+
+ +

Enables or disables the Low Power Regulator low voltage mode.

+
Note
This mode is only available for STM32F401xx/STM32F411xx devices.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
+
+ +

Enables or disables the Main Regulator low voltage mode.

+
Note
This mode is only available for STM32F401xx/STM32F411xx devices.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
+
+ +

Configures the main internal regulator output voltage.

+
Parameters
+ + +
PWR_Regulator_Voltagespecifies the regulator output voltage to achieve a tradeoff between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheets for more details). This parameter can be one of the following values:
    +
  • PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, System frequency up to 168 MHz.
    • +
  • PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, System frequency up to 144 MHz.
    • +
  • PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_OverDriveCmd (FunctionalState NewState)
+
+ +

Enables or disables the Over-Drive.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices. This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
+
+It is recommended to enter or exit Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.
+
Parameters
+ + +
NewStatenew state of the Over Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_OverDriveSWCmd (FunctionalState NewState)
+
+ +

Enables or disables the Over-Drive switching.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices.
+
Parameters
+ + +
NewStatenew state of the Over Drive switching mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void PWR_UnderDriveCmd (FunctionalState NewState)
+
+ +

Enables or disables the Under-Drive mode.

+
Note
This function can be used only for STM32F42xxx/STM3243xxx devices.
+
+This mode is enabled only with STOP low power mode. In this mode, the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode
+
+If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode. When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.
+
Parameters
+ + +
NewStatenew state of the Under Drive mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group4.map b/group___p_w_r___group4.map new file mode 100644 index 0000000..83fa08c --- /dev/null +++ b/group___p_w_r___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group4.md5 b/group___p_w_r___group4.md5 new file mode 100644 index 0000000..d2b0013 --- /dev/null +++ b/group___p_w_r___group4.md5 @@ -0,0 +1 @@ +e2cb9db5be939cd1f346964e39764725 \ No newline at end of file diff --git a/group___p_w_r___group4.png b/group___p_w_r___group4.png new file mode 100644 index 0000000..d1dee39 Binary files /dev/null and b/group___p_w_r___group4.png differ diff --git a/group___p_w_r___group5.html b/group___p_w_r___group5.html new file mode 100644 index 0000000..f97307b --- /dev/null +++ b/group___p_w_r___group5.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: FLASH Power Down configuration functions + + + + + + + + + + +
+
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+Functions
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+
FLASH Power Down configuration functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

FLASH Power Down configuration functions. +More...

+
+Collaboration diagram for FLASH Power Down configuration functions:
+
+
+ + +
+
+ + + + + +

+Functions

void PWR_FlashPowerDownCmd (FunctionalState NewState)
 Enables or disables the Flash Power Down in STOP mode. More...
 
+

Detailed Description

+

FLASH Power Down configuration functions.

+
 ===============================================================================
+             ##### FLASH Power Down configuration functions #####
+ ===============================================================================  
+    [..]
+      (+) By setting the FPDS bit in the PWR_CR register by using the 
+          PWR_FlashPowerDownCmd() function, the Flash memory also enters power 
+          down mode when the device enters Stop mode. When the Flash memory 
+          is in power down mode, an additional startup delay is incurred when 
+          waking up from Stop mode.
+

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_FlashPowerDownCmd (FunctionalState NewState)
+
+ +

Enables or disables the Flash Power Down in STOP mode.

+
Parameters
+ + +
NewStatenew state of the Flash power mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group5.map b/group___p_w_r___group5.map new file mode 100644 index 0000000..d47e710 --- /dev/null +++ b/group___p_w_r___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group5.md5 b/group___p_w_r___group5.md5 new file mode 100644 index 0000000..d297d4b --- /dev/null +++ b/group___p_w_r___group5.md5 @@ -0,0 +1 @@ +11eeddba78ba53953cd68296e1392576 \ No newline at end of file diff --git a/group___p_w_r___group5.png b/group___p_w_r___group5.png new file mode 100644 index 0000000..dec5625 Binary files /dev/null and b/group___p_w_r___group5.png differ diff --git a/group___p_w_r___group6.html b/group___p_w_r___group6.html new file mode 100644 index 0000000..f9818ea --- /dev/null +++ b/group___p_w_r___group6.html @@ -0,0 +1,374 @@ + + + + + + +discoverpixy: Low Power modes configuration functions + + + + + + + + + + +
+
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+Functions
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+
Low Power modes configuration functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

Low Power modes configuration functions. +More...

+
+Collaboration diagram for Low Power modes configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters STOP mode. More...
 
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters in Under-Drive STOP mode. More...
 
void PWR_EnterSTANDBYMode (void)
 Enters STANDBY mode. More...
 
+

Detailed Description

+

Low Power modes configuration functions.

+
 ===============================================================================
+              ##### Low Power modes configuration functions #####
+ ===============================================================================  
+    [..]
+      The devices feature 3 low-power modes:
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+      (+) Stop mode: all clocks are stopped, regulator running, regulator 
+          in low power mode
+      (+) Standby mode: 1.2V domain powered off.
+   
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+        (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
+      (+) Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
+             controller (NVIC) can wake up the device from Sleep mode.
+
+   *** Stop mode ***
+   =================
+    [..]
+      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+      are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption In Stop mode, FLASH can be powered off before 
+      entering the Stop mode. It can be switched on again by software after exiting 
+      the Stop mode using the PWR_FlashPowerDownCmd() function. 
+   
+      (+) Entry:
+        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) 
+             function with:
+          (+++) Main regulator ON.
+          (+++) Low Power regulator ON.
+      (+) Exit:
+        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+      
+   *** Standby mode ***
+   ====================
+    [..]
+      The Standby mode allows to achieve the lowest power consumption. It is based 
+      on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+      the HSE oscillator are also switched off. SRAM and register contents are lost 
+      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+      circuitry.
+   
+      The voltage regulator is OFF.
+      
+      (+) Entry:
+        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+      (+) Exit:
+        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.              
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+      without depending on an external interrupt (Auto-wakeup mode).
+
+      (#) RTC auto-wakeup (AWU) from the Stop mode
+       
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+          (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+                or Event modes) using the EXTI_Init() function.
+          (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+          (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                and RTC_AlarmCmd() functions.
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+          (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt 
+                or Event modes) using the EXTI_Init() function.
+          (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                function
+          (+++) Configure the RTC to detect the tamper or time stamp event using the
+                RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                functions.
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
+           (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt 
+                 or Event modes) using the EXTI_Init() function.
+           (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+           (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+                 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+      (#) RTC auto-wakeup (AWU) from the Standby mode
+   
+        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+          (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+          (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+                and RTC_AlarmCmd() functions.
+        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+             is necessary to:
+          (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+                function
+          (+++) Configure the RTC to detect the tamper or time stamp event using the
+                RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+                functions.
+        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
+          (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+          (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+                RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_EnterSTANDBYMode (void )
+
+ +

Enters STANDBY mode.

+
Note
In Standby mode, all I/O pins are high impedance except for:
    +
  • Reset pad (still available)
    • +
  • RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC Alarm out, or RTC clock calibration out.
    • +
  • RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
    • +
  • WKUP pin 1 (PA0) if enabled.
    • +
+
+
+The Wakeup flag (WUF) need to be cleared at application level before to call this function
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void PWR_EnterSTOPMode (uint32_t PWR_Regulator,
uint8_t PWR_STOPEntry 
)
+
+ +

Enters STOP mode.

+
Note
In Stop mode, all I/O pins keep the same state as in Run mode.
+
+When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
+
+When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
+
Parameters
+ + + +
PWR_Regulatorspecifies the regulator state in STOP mode. This parameter can be one of the following values:
    +
  • PWR_MainRegulator_ON: STOP mode with regulator ON
    • +
  • PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
    • +
+
PWR_STOPEntryspecifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
    +
  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
    • +
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator,
uint8_t PWR_STOPEntry 
)
+
+ +

Enters in Under-Drive STOP mode.

+
Note
This mode is only available for STM32F42xxx/STM3243xxx devices.
+
+This mode can be selected only when the Under-Drive is already active
+
+In Stop mode, all I/O pins keep the same state as in Run mode.
+
+When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.
+
+When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
+
Parameters
+ + + +
PWR_Regulatorspecifies the regulator state in STOP mode. This parameter can be one of the following values:
    +
  • PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
    • +
  • PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode
    • +
+
PWR_STOPEntryspecifies if STOP mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
    +
  • PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
    • +
  • PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group6.map b/group___p_w_r___group6.map new file mode 100644 index 0000000..c4c77bf --- /dev/null +++ b/group___p_w_r___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group6.md5 b/group___p_w_r___group6.md5 new file mode 100644 index 0000000..7adc9dc --- /dev/null +++ b/group___p_w_r___group6.md5 @@ -0,0 +1 @@ +4f4219aef15ce458d1d412b033d224e7 \ No newline at end of file diff --git a/group___p_w_r___group6.png b/group___p_w_r___group6.png new file mode 100644 index 0000000..7e5f45d Binary files /dev/null and b/group___p_w_r___group6.png differ diff --git a/group___p_w_r___group7.html b/group___p_w_r___group7.html new file mode 100644 index 0000000..d8ce46f --- /dev/null +++ b/group___p_w_r___group7.html @@ -0,0 +1,194 @@ + + + + + + +discoverpixy: Flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Flags management functions
STM32F4xx_StdPeriph_Driver » PWR » PWR_Private_Functions
+
+
+ +

Flags management functions. +More...

+
+Collaboration diagram for Flags management functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
 Checks whether the specified PWR flag is set or not. More...
 
void PWR_ClearFlag (uint32_t PWR_FLAG)
 Clears the PWR's pending flags. More...
 
+

Detailed Description

+

Flags management functions.

+
 ===============================================================================
+                    ##### Flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void PWR_ClearFlag (uint32_t PWR_FLAG)
+
+ +

Clears the PWR's pending flags.

+
Parameters
+ + +
PWR_FLAGspecifies the flag to clear. This parameter can be one of the following values:
    +
  • PWR_FLAG_WU: Wake Up flag
    • +
  • PWR_FLAG_SB: StandBy flag
    • +
  • PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
+
+ +

Checks whether the specified PWR flag is set or not.

+
Parameters
+ + +
PWR_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
    • +
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
    • +
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the PWR_PVDCmd() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
    • +
  • PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.
    • +
  • PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage scaling output selection is ready.
    • +
  • PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode is ready (STM32F42xxx/43xxx devices)
    • +
  • PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode switcching is ready (STM32F42xxx/43xxx devices)
    • +
  • PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode is enabled in Stop mode (STM32F42xxx/43xxx devices)
    • +
+
+
+
+
Return values
+ + +
Thenew state of PWR_FLAG (SET or RESET).
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___group7.map b/group___p_w_r___group7.map new file mode 100644 index 0000000..87ed634 --- /dev/null +++ b/group___p_w_r___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___group7.md5 b/group___p_w_r___group7.md5 new file mode 100644 index 0000000..5255dbb --- /dev/null +++ b/group___p_w_r___group7.md5 @@ -0,0 +1 @@ +fe9380dd2f03c776a4325a85b003dee4 \ No newline at end of file diff --git a/group___p_w_r___group7.png b/group___p_w_r___group7.png new file mode 100644 index 0000000..1abbfd6 Binary files /dev/null and b/group___p_w_r___group7.png differ diff --git a/group___p_w_r___p_v_d__detection__level.html b/group___p_w_r___p_v_d__detection__level.html new file mode 100644 index 0000000..899fd47 --- /dev/null +++ b/group___p_w_r___p_v_d__detection__level.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: PWR_PVD_detection_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_PVD_detection_level
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_PVD_detection_level:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define PWR_PVDLevel_0   PWR_CR_PLS_LEV0
 
+#define PWR_PVDLevel_1   PWR_CR_PLS_LEV1
 
+#define PWR_PVDLevel_2   PWR_CR_PLS_LEV2
 
+#define PWR_PVDLevel_3   PWR_CR_PLS_LEV3
 
+#define PWR_PVDLevel_4   PWR_CR_PLS_LEV4
 
+#define PWR_PVDLevel_5   PWR_CR_PLS_LEV5
 
+#define PWR_PVDLevel_6   PWR_CR_PLS_LEV6
 
+#define PWR_PVDLevel_7   PWR_CR_PLS_LEV7
 
#define IS_PWR_PVD_LEVEL(LEVEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_PWR_PVD_LEVEL( LEVEL)
+
+Value:
(((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___p_v_d__detection__level.map b/group___p_w_r___p_v_d__detection__level.map new file mode 100644 index 0000000..fab4d82 --- /dev/null +++ b/group___p_w_r___p_v_d__detection__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___p_v_d__detection__level.md5 b/group___p_w_r___p_v_d__detection__level.md5 new file mode 100644 index 0000000..5ad6e58 --- /dev/null +++ b/group___p_w_r___p_v_d__detection__level.md5 @@ -0,0 +1 @@ +e45856e6cd7564a381e6bf83087cf286 \ No newline at end of file diff --git a/group___p_w_r___p_v_d__detection__level.png b/group___p_w_r___p_v_d__detection__level.png new file mode 100644 index 0000000..47028e2 Binary files /dev/null and b/group___p_w_r___p_v_d__detection__level.png differ diff --git a/group___p_w_r___private___functions.html b/group___p_w_r___private___functions.html new file mode 100644 index 0000000..c75025a --- /dev/null +++ b/group___p_w_r___private___functions.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: PWR_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
PWR_Private_Functions
STM32F4xx_StdPeriph_Driver » PWR
+
+
+
+Collaboration diagram for PWR_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Backup Domain Access function
 Backup Domain Access function.
 
 PVD configuration functions
 PVD configuration functions.
 
 WakeUp pin configuration functions
 WakeUp pin configuration functions.
 
 Main and Backup Regulators configuration functions
 Main and Backup Regulators configuration functions.
 
 FLASH Power Down configuration functions
 FLASH Power Down configuration functions.
 
 Low Power modes configuration functions
 Low Power modes configuration functions.
 
 Flags management functions
 Flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___private___functions.map b/group___p_w_r___private___functions.map new file mode 100644 index 0000000..4608646 --- /dev/null +++ b/group___p_w_r___private___functions.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___p_w_r___private___functions.md5 b/group___p_w_r___private___functions.md5 new file mode 100644 index 0000000..8156dbf --- /dev/null +++ b/group___p_w_r___private___functions.md5 @@ -0,0 +1 @@ +7c3d7a04ed806ae1146c2779cd9aab7f \ No newline at end of file diff --git a/group___p_w_r___private___functions.png b/group___p_w_r___private___functions.png new file mode 100644 index 0000000..838cdcc Binary files /dev/null and b/group___p_w_r___private___functions.png differ diff --git a/group___p_w_r___regulator___voltage___scale.html b/group___p_w_r___regulator___voltage___scale.html new file mode 100644 index 0000000..0fdbdef --- /dev/null +++ b/group___p_w_r___regulator___voltage___scale.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: PWR_Regulator_Voltage_Scale + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_Regulator_Voltage_Scale
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_Regulator_Voltage_Scale:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define PWR_Regulator_Voltage_Scale1   ((uint32_t)0x0000C000)
 
+#define PWR_Regulator_Voltage_Scale2   ((uint32_t)0x00008000)
 
+#define PWR_Regulator_Voltage_Scale3   ((uint32_t)0x00004000)
 
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_PWR_REGULATOR_VOLTAGE( VOLTAGE)
+
+Value:
(((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
+
((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
+
((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___regulator___voltage___scale.map b/group___p_w_r___regulator___voltage___scale.map new file mode 100644 index 0000000..cc8d006 --- /dev/null +++ b/group___p_w_r___regulator___voltage___scale.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___regulator___voltage___scale.md5 b/group___p_w_r___regulator___voltage___scale.md5 new file mode 100644 index 0000000..ff7430c --- /dev/null +++ b/group___p_w_r___regulator___voltage___scale.md5 @@ -0,0 +1 @@ +96f62304103b009bffa0d8ad0eb4b704 \ No newline at end of file diff --git a/group___p_w_r___regulator___voltage___scale.png b/group___p_w_r___regulator___voltage___scale.png new file mode 100644 index 0000000..3866d59 Binary files /dev/null and b/group___p_w_r___regulator___voltage___scale.png differ diff --git a/group___p_w_r___regulator__state__in___s_t_o_p__mode.html b/group___p_w_r___regulator__state__in___s_t_o_p__mode.html new file mode 100644 index 0000000..5e8b99a --- /dev/null +++ b/group___p_w_r___regulator__state__in___s_t_o_p__mode.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: PWR_Regulator_state_in_STOP_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_Regulator_state_in_STOP_mode
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_Regulator_state_in_STOP_mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define PWR_MainRegulator_ON   ((uint32_t)0x00000000)
 
+#define PWR_LowPowerRegulator_ON   PWR_CR_LPDS
 
+#define PWR_Regulator_ON   PWR_MainRegulator_ON
 
+#define PWR_Regulator_LowPower   PWR_LowPowerRegulator_ON
 
#define IS_PWR_REGULATOR(REGULATOR)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_PWR_REGULATOR( REGULATOR)
+
+Value:
(((REGULATOR) == PWR_MainRegulator_ON) || \
+
((REGULATOR) == PWR_LowPowerRegulator_ON))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___regulator__state__in___s_t_o_p__mode.map b/group___p_w_r___regulator__state__in___s_t_o_p__mode.map new file mode 100644 index 0000000..9a65ae7 --- /dev/null +++ b/group___p_w_r___regulator__state__in___s_t_o_p__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___regulator__state__in___s_t_o_p__mode.md5 b/group___p_w_r___regulator__state__in___s_t_o_p__mode.md5 new file mode 100644 index 0000000..7e45156 --- /dev/null +++ b/group___p_w_r___regulator__state__in___s_t_o_p__mode.md5 @@ -0,0 +1 @@ +e68ea11b3b4d06425e9c524804962d67 \ No newline at end of file diff --git a/group___p_w_r___regulator__state__in___s_t_o_p__mode.png b/group___p_w_r___regulator__state__in___s_t_o_p__mode.png new file mode 100644 index 0000000..db92e55 Binary files /dev/null and b/group___p_w_r___regulator__state__in___s_t_o_p__mode.png differ diff --git a/group___p_w_r___regulator__state__in___under_drive__mode.html b/group___p_w_r___regulator__state__in___under_drive__mode.html new file mode 100644 index 0000000..c9e0b3a --- /dev/null +++ b/group___p_w_r___regulator__state__in___under_drive__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: PWR_Regulator_state_in_UnderDrive_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_Regulator_state_in_UnderDrive_mode
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_Regulator_state_in_UnderDrive_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define PWR_MainRegulator_UnderDrive_ON   PWR_CR_MRUDS
 
+#define PWR_LowPowerRegulator_UnderDrive_ON   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
 
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_PWR_REGULATOR_UNDERDRIVE( REGULATOR)
+
+Value:
(((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
+
((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___p_w_r___regulator__state__in___under_drive__mode.map b/group___p_w_r___regulator__state__in___under_drive__mode.map new file mode 100644 index 0000000..e400339 --- /dev/null +++ b/group___p_w_r___regulator__state__in___under_drive__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___p_w_r___regulator__state__in___under_drive__mode.md5 b/group___p_w_r___regulator__state__in___under_drive__mode.md5 new file mode 100644 index 0000000..3597c5f --- /dev/null +++ b/group___p_w_r___regulator__state__in___under_drive__mode.md5 @@ -0,0 +1 @@ +c886f2982054416fd19b34de6fa1b1ca \ No newline at end of file diff --git a/group___p_w_r___regulator__state__in___under_drive__mode.png b/group___p_w_r___regulator__state__in___under_drive__mode.png new file mode 100644 index 0000000..9c5758e Binary files /dev/null and b/group___p_w_r___regulator__state__in___under_drive__mode.png differ diff --git a/group___p_w_r___s_t_o_p__mode__entry.html b/group___p_w_r___s_t_o_p__mode__entry.html new file mode 100644 index 0000000..34c247f --- /dev/null +++ b/group___p_w_r___s_t_o_p__mode__entry.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: PWR_STOP_mode_entry + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
PWR_STOP_mode_entry
STM32F4xx_StdPeriph_Driver » PWR » PWR_Exported_Constants
+
+
+
+Collaboration diagram for PWR_STOP_mode_entry:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define PWR_STOPEntry_WFI   ((uint8_t)0x01)
 
+#define PWR_STOPEntry_WFE   ((uint8_t)0x02)
 
+#define IS_PWR_STOP_ENTRY(ENTRY)   (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define ADC_SR_AWD   ((uint8_t)0x01)
 
#define ADC_SR_EOC   ((uint8_t)0x02)
 
#define ADC_SR_JEOC   ((uint8_t)0x04)
 
#define ADC_SR_JSTRT   ((uint8_t)0x08)
 
#define ADC_SR_STRT   ((uint8_t)0x10)
 
#define ADC_SR_OVR   ((uint8_t)0x20)
 
#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
 
#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
 
#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
 
#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
 
#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
 
#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
 
#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)
 
#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)
 
#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
 
#define ADC_CR1_SCAN   ((uint32_t)0x00000100)
 
#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
 
#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)
 
#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)
 
#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
 
#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
 
#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
 
#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
 
#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
 
#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
 
#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)
 
#define ADC_CR1_RES   ((uint32_t)0x03000000)
 
#define ADC_CR1_RES_0   ((uint32_t)0x01000000)
 
#define ADC_CR1_RES_1   ((uint32_t)0x02000000)
 
#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)
 
#define ADC_CR2_ADON   ((uint32_t)0x00000001)
 
#define ADC_CR2_CONT   ((uint32_t)0x00000002)
 
#define ADC_CR2_DMA   ((uint32_t)0x00000100)
 
#define ADC_CR2_DDS   ((uint32_t)0x00000200)
 
#define ADC_CR2_EOCS   ((uint32_t)0x00000400)
 
#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)
 
#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
 
#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
 
#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
 
#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
 
#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
 
#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
 
#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
 
#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
 
#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
 
#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
 
#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
 
#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
 
#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
 
#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
 
#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)
 
#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
 
#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
 
#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)
 
#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
 
#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
 
#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
 
#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
 
#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
 
#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
 
#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
 
#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
 
#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
 
#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
 
#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
 
#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
 
#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
 
#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
 
#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
 
#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
 
#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
 
#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
 
#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
 
#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
 
#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
 
#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
 
#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
 
#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
 
#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
 
#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
 
#define ADC_HTR_HT   ((uint16_t)0x0FFF)
 
#define ADC_LTR_LT   ((uint16_t)0x0FFF)
 
#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
 
#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
 
#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
 
#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
 
#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
 
#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
 
#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
 
#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
 
#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
 
#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
 
#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
 
#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
 
#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
 
#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
 
#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
 
#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
 
#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
 
#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
 
#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
 
#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
 
#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
 
#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
 
#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
 
#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
 
#define ADC_SQR1_L   ((uint32_t)0x00F00000)
 
#define ADC_SQR1_L_0   ((uint32_t)0x00100000)
 
#define ADC_SQR1_L_1   ((uint32_t)0x00200000)
 
#define ADC_SQR1_L_2   ((uint32_t)0x00400000)
 
#define ADC_SQR1_L_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
 
#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
 
#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
 
#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
 
#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
 
#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
 
#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
 
#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
 
#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
 
#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
 
#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
 
#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
 
#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
 
#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
 
#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
 
#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
 
#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
 
#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
 
#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
 
#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
 
#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
 
#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
 
#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
 
#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
 
#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
 
#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
 
#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
 
#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
 
#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
 
#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
 
#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
 
#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
 
#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
 
#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
 
#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
 
#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
 
#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
 
#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
 
#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
 
#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
 
#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
 
#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
 
#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
 
#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
 
#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
 
#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
 
#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
 
#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
 
#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
 
#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
 
#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
 
#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
 
#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
 
#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
 
#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
 
#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
 
#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
 
#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
 
#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
 
#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
 
#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
 
#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
 
#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
 
#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
 
#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
 
#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
 
#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
 
#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
 
#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
 
#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
 
#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
 
#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
 
#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
 
#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
 
#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
 
#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
 
#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
 
#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
 
#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
 
#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
 
#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
 
#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
 
#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
 
#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
 
#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
 
#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
 
#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
 
#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
 
#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
 
#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
 
#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
 
#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
 
#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
 
#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
 
#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
 
#define ADC_JSQR_JL   ((uint32_t)0x00300000)
 
#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)
 
#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)
 
#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)
 
#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
 
#define ADC_CSR_AWD1   ((uint32_t)0x00000001)
 
#define ADC_CSR_EOC1   ((uint32_t)0x00000002)
 
#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)
 
#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
 
#define ADC_CSR_STRT1   ((uint32_t)0x00000010)
 
#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)
 
#define ADC_CSR_AWD2   ((uint32_t)0x00000100)
 
#define ADC_CSR_EOC2   ((uint32_t)0x00000200)
 
#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)
 
#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
 
#define ADC_CSR_STRT2   ((uint32_t)0x00001000)
 
#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)
 
#define ADC_CSR_AWD3   ((uint32_t)0x00010000)
 
#define ADC_CSR_EOC3   ((uint32_t)0x00020000)
 
#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)
 
#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
 
#define ADC_CSR_STRT3   ((uint32_t)0x00100000)
 
#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)
 
#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)
 
#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
 
#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
 
#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
 
#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
 
#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
 
#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)
 
#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
 
#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
 
#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
 
#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
 
#define ADC_CCR_DDS   ((uint32_t)0x00002000)
 
#define ADC_CCR_DMA   ((uint32_t)0x0000C000)
 
#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)
 
#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)
 
#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
 
#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
 
#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
 
#define ADC_CCR_VBATE   ((uint32_t)0x00400000)
 
#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
 
#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
 
#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
 
#define CAN_MCR_INRQ   ((uint16_t)0x0001)
 
#define CAN_MCR_SLEEP   ((uint16_t)0x0002)
 
#define CAN_MCR_TXFP   ((uint16_t)0x0004)
 
#define CAN_MCR_RFLM   ((uint16_t)0x0008)
 
#define CAN_MCR_NART   ((uint16_t)0x0010)
 
#define CAN_MCR_AWUM   ((uint16_t)0x0020)
 
#define CAN_MCR_ABOM   ((uint16_t)0x0040)
 
#define CAN_MCR_TTCM   ((uint16_t)0x0080)
 
#define CAN_MCR_RESET   ((uint16_t)0x8000)
 
#define CAN_MSR_INAK   ((uint16_t)0x0001)
 
#define CAN_MSR_SLAK   ((uint16_t)0x0002)
 
#define CAN_MSR_ERRI   ((uint16_t)0x0004)
 
#define CAN_MSR_WKUI   ((uint16_t)0x0008)
 
#define CAN_MSR_SLAKI   ((uint16_t)0x0010)
 
#define CAN_MSR_TXM   ((uint16_t)0x0100)
 
#define CAN_MSR_RXM   ((uint16_t)0x0200)
 
#define CAN_MSR_SAMP   ((uint16_t)0x0400)
 
#define CAN_MSR_RX   ((uint16_t)0x0800)
 
#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)
 
#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)
 
#define CAN_TSR_ALST0   ((uint32_t)0x00000004)
 
#define CAN_TSR_TERR0   ((uint32_t)0x00000008)
 
#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
 
#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)
 
#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)
 
#define CAN_TSR_ALST1   ((uint32_t)0x00000400)
 
#define CAN_TSR_TERR1   ((uint32_t)0x00000800)
 
#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
 
#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)
 
#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)
 
#define CAN_TSR_ALST2   ((uint32_t)0x00040000)
 
#define CAN_TSR_TERR2   ((uint32_t)0x00080000)
 
#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
 
#define CAN_TSR_CODE   ((uint32_t)0x03000000)
 
#define CAN_TSR_TME   ((uint32_t)0x1C000000)
 
#define CAN_TSR_TME0   ((uint32_t)0x04000000)
 
#define CAN_TSR_TME1   ((uint32_t)0x08000000)
 
#define CAN_TSR_TME2   ((uint32_t)0x10000000)
 
#define CAN_TSR_LOW   ((uint32_t)0xE0000000)
 
#define CAN_TSR_LOW0   ((uint32_t)0x20000000)
 
#define CAN_TSR_LOW1   ((uint32_t)0x40000000)
 
#define CAN_TSR_LOW2   ((uint32_t)0x80000000)
 
#define CAN_RF0R_FMP0   ((uint8_t)0x03)
 
#define CAN_RF0R_FULL0   ((uint8_t)0x08)
 
#define CAN_RF0R_FOVR0   ((uint8_t)0x10)
 
#define CAN_RF0R_RFOM0   ((uint8_t)0x20)
 
#define CAN_RF1R_FMP1   ((uint8_t)0x03)
 
#define CAN_RF1R_FULL1   ((uint8_t)0x08)
 
#define CAN_RF1R_FOVR1   ((uint8_t)0x10)
 
#define CAN_RF1R_RFOM1   ((uint8_t)0x20)
 
#define CAN_IER_TMEIE   ((uint32_t)0x00000001)
 
#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)
 
#define CAN_IER_FFIE0   ((uint32_t)0x00000004)
 
#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)
 
#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)
 
#define CAN_IER_FFIE1   ((uint32_t)0x00000020)
 
#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)
 
#define CAN_IER_EWGIE   ((uint32_t)0x00000100)
 
#define CAN_IER_EPVIE   ((uint32_t)0x00000200)
 
#define CAN_IER_BOFIE   ((uint32_t)0x00000400)
 
#define CAN_IER_LECIE   ((uint32_t)0x00000800)
 
#define CAN_IER_ERRIE   ((uint32_t)0x00008000)
 
#define CAN_IER_WKUIE   ((uint32_t)0x00010000)
 
#define CAN_IER_SLKIE   ((uint32_t)0x00020000)
 
#define CAN_ESR_EWGF   ((uint32_t)0x00000001)
 
#define CAN_ESR_EPVF   ((uint32_t)0x00000002)
 
#define CAN_ESR_BOFF   ((uint32_t)0x00000004)
 
#define CAN_ESR_LEC   ((uint32_t)0x00000070)
 
#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)
 
#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)
 
#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)
 
#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)
 
#define CAN_ESR_REC   ((uint32_t)0xFF000000)
 
#define CAN_BTR_BRP   ((uint32_t)0x000003FF)
 
#define CAN_BTR_TS1   ((uint32_t)0x000F0000)
 
#define CAN_BTR_TS2   ((uint32_t)0x00700000)
 
#define CAN_BTR_SJW   ((uint32_t)0x03000000)
 
#define CAN_BTR_LBKM   ((uint32_t)0x40000000)
 
#define CAN_BTR_SILM   ((uint32_t)0x80000000)
 
#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI2R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI2R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_FMR_FINIT   ((uint8_t)0x01)
 
#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)
 
#define CAN_FM1R_FBM0   ((uint16_t)0x0001)
 
#define CAN_FM1R_FBM1   ((uint16_t)0x0002)
 
#define CAN_FM1R_FBM2   ((uint16_t)0x0004)
 
#define CAN_FM1R_FBM3   ((uint16_t)0x0008)
 
#define CAN_FM1R_FBM4   ((uint16_t)0x0010)
 
#define CAN_FM1R_FBM5   ((uint16_t)0x0020)
 
#define CAN_FM1R_FBM6   ((uint16_t)0x0040)
 
#define CAN_FM1R_FBM7   ((uint16_t)0x0080)
 
#define CAN_FM1R_FBM8   ((uint16_t)0x0100)
 
#define CAN_FM1R_FBM9   ((uint16_t)0x0200)
 
#define CAN_FM1R_FBM10   ((uint16_t)0x0400)
 
#define CAN_FM1R_FBM11   ((uint16_t)0x0800)
 
#define CAN_FM1R_FBM12   ((uint16_t)0x1000)
 
#define CAN_FM1R_FBM13   ((uint16_t)0x2000)
 
#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)
 
#define CAN_FS1R_FSC0   ((uint16_t)0x0001)
 
#define CAN_FS1R_FSC1   ((uint16_t)0x0002)
 
#define CAN_FS1R_FSC2   ((uint16_t)0x0004)
 
#define CAN_FS1R_FSC3   ((uint16_t)0x0008)
 
#define CAN_FS1R_FSC4   ((uint16_t)0x0010)
 
#define CAN_FS1R_FSC5   ((uint16_t)0x0020)
 
#define CAN_FS1R_FSC6   ((uint16_t)0x0040)
 
#define CAN_FS1R_FSC7   ((uint16_t)0x0080)
 
#define CAN_FS1R_FSC8   ((uint16_t)0x0100)
 
#define CAN_FS1R_FSC9   ((uint16_t)0x0200)
 
#define CAN_FS1R_FSC10   ((uint16_t)0x0400)
 
#define CAN_FS1R_FSC11   ((uint16_t)0x0800)
 
#define CAN_FS1R_FSC12   ((uint16_t)0x1000)
 
#define CAN_FS1R_FSC13   ((uint16_t)0x2000)
 
#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
 
#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)
 
#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)
 
#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)
 
#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)
 
#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)
 
#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)
 
#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)
 
#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)
 
#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)
 
#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)
 
#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)
 
#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)
 
#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)
 
#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)
 
#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)
 
#define CAN_FA1R_FACT0   ((uint16_t)0x0001)
 
#define CAN_FA1R_FACT1   ((uint16_t)0x0002)
 
#define CAN_FA1R_FACT2   ((uint16_t)0x0004)
 
#define CAN_FA1R_FACT3   ((uint16_t)0x0008)
 
#define CAN_FA1R_FACT4   ((uint16_t)0x0010)
 
#define CAN_FA1R_FACT5   ((uint16_t)0x0020)
 
#define CAN_FA1R_FACT6   ((uint16_t)0x0040)
 
#define CAN_FA1R_FACT7   ((uint16_t)0x0080)
 
#define CAN_FA1R_FACT8   ((uint16_t)0x0100)
 
#define CAN_FA1R_FACT9   ((uint16_t)0x0200)
 
#define CAN_FA1R_FACT10   ((uint16_t)0x0400)
 
#define CAN_FA1R_FACT11   ((uint16_t)0x0800)
 
#define CAN_FA1R_FACT12   ((uint16_t)0x1000)
 
#define CAN_FA1R_FACT13   ((uint16_t)0x2000)
 
#define CAN_F0R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F0R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R2_FB31   ((uint32_t)0x80000000)
 
#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
 
#define CRC_IDR_IDR   ((uint8_t)0xFF)
 
#define CRC_CR_RESET   ((uint8_t)0x01)
 
+#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)
 
+#define CRYP_CR_ALGOMODE   ((uint32_t)0x00080038)
 
+#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)
 
+#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)
 
+#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)
 
+#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)
 
+#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)
 
+#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)
 
+#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)
 
+#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)
 
+#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)
 
+#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)
 
+#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)
 
+#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)
 
+#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)
 
+#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)
 
+#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)
 
+#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)
 
+#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)
 
+#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)
 
+#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)
 
+#define CRYP_CR_GCM_CCMPH   ((uint32_t)0x00030000)
 
+#define CRYP_CR_GCM_CCMPH_0   ((uint32_t)0x00010000)
 
+#define CRYP_CR_GCM_CCMPH_1   ((uint32_t)0x00020000)
 
+#define CRYP_CR_ALGOMODE_3   ((uint32_t)0x00080000)
 
+#define CRYP_SR_IFEM   ((uint32_t)0x00000001)
 
+#define CRYP_SR_IFNF   ((uint32_t)0x00000002)
 
+#define CRYP_SR_OFNE   ((uint32_t)0x00000004)
 
+#define CRYP_SR_OFFU   ((uint32_t)0x00000008)
 
+#define CRYP_SR_BUSY   ((uint32_t)0x00000010)
 
+#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)
 
+#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)
 
+#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)
 
+#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)
 
+#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)
 
+#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)
 
+#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)
 
+#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)
 
#define DAC_CR_EN1   ((uint32_t)0x00000001)
 
#define DAC_CR_BOFF1   ((uint32_t)0x00000002)
 
#define DAC_CR_TEN1   ((uint32_t)0x00000004)
 
#define DAC_CR_TSEL1   ((uint32_t)0x00000038)
 
#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
 
#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
 
#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
 
#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)
 
#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
 
#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
 
#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)
 
#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
 
#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
 
#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
 
#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
 
#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)
 
#define DAC_CR_EN2   ((uint32_t)0x00010000)
 
#define DAC_CR_BOFF2   ((uint32_t)0x00020000)
 
#define DAC_CR_TEN2   ((uint32_t)0x00040000)
 
#define DAC_CR_TSEL2   ((uint32_t)0x00380000)
 
#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
 
#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
 
#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
 
#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)
 
#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
 
#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
 
#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)
 
#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
 
#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
 
#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
 
#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
 
#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)
 
#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
 
#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
 
#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
 
#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
 
#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
 
#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
 
#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
 
#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
 
#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
 
#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
 
#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
 
#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
 
+#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)
 
+#define DCMI_CR_CM   ((uint32_t)0x00000002)
 
+#define DCMI_CR_CROP   ((uint32_t)0x00000004)
 
+#define DCMI_CR_JPEG   ((uint32_t)0x00000008)
 
+#define DCMI_CR_ESS   ((uint32_t)0x00000010)
 
+#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)
 
+#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)
 
+#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)
 
+#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)
 
+#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)
 
+#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)
 
+#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)
 
+#define DCMI_CR_CRE   ((uint32_t)0x00001000)
 
+#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)
 
+#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)
 
+#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)
 
+#define DCMI_SR_FNE   ((uint32_t)0x00000004)
 
+#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)
 
+#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)
 
+#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)
 
+#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)
 
+#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)
 
+#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)
 
+#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)
 
+#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)
 
+#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)
 
+#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)
 
+#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)
 
+#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)
 
+#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)
 
+#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)
 
+#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)
 
+#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)
 
+#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)
 
+#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)
 
+#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)
 
+#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)
 
+#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)
 
+#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)
 
+#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)
 
+#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)
 
+#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)
 
+#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)
 
+#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)
 
+#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)
 
+#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)
 
+#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)
 
+#define DMA_SxCR_ACK   ((uint32_t)0x00100000)
 
+#define DMA_SxCR_CT   ((uint32_t)0x00080000)
 
+#define DMA_SxCR_DBM   ((uint32_t)0x00040000)
 
+#define DMA_SxCR_PL   ((uint32_t)0x00030000)
 
+#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)
 
+#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)
 
+#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)
 
+#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)
 
+#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)
 
+#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)
 
+#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)
 
+#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)
 
+#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)
 
+#define DMA_SxCR_MINC   ((uint32_t)0x00000400)
 
+#define DMA_SxCR_PINC   ((uint32_t)0x00000200)
 
+#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)
 
+#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)
 
+#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)
 
+#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)
 
+#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)
 
+#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)
 
+#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)
 
+#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)
 
+#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)
 
+#define DMA_SxCR_EN   ((uint32_t)0x00000001)
 
+#define DMA_SxNDT   ((uint32_t)0x0000FFFF)
 
+#define DMA_SxNDT_0   ((uint32_t)0x00000001)
 
+#define DMA_SxNDT_1   ((uint32_t)0x00000002)
 
+#define DMA_SxNDT_2   ((uint32_t)0x00000004)
 
+#define DMA_SxNDT_3   ((uint32_t)0x00000008)
 
+#define DMA_SxNDT_4   ((uint32_t)0x00000010)
 
+#define DMA_SxNDT_5   ((uint32_t)0x00000020)
 
+#define DMA_SxNDT_6   ((uint32_t)0x00000040)
 
+#define DMA_SxNDT_7   ((uint32_t)0x00000080)
 
+#define DMA_SxNDT_8   ((uint32_t)0x00000100)
 
+#define DMA_SxNDT_9   ((uint32_t)0x00000200)
 
+#define DMA_SxNDT_10   ((uint32_t)0x00000400)
 
+#define DMA_SxNDT_11   ((uint32_t)0x00000800)
 
+#define DMA_SxNDT_12   ((uint32_t)0x00001000)
 
+#define DMA_SxNDT_13   ((uint32_t)0x00002000)
 
+#define DMA_SxNDT_14   ((uint32_t)0x00004000)
 
+#define DMA_SxNDT_15   ((uint32_t)0x00008000)
 
+#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)
 
+#define DMA_SxFCR_FS   ((uint32_t)0x00000038)
 
+#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)
 
+#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)
 
+#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)
 
+#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)
 
+#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)
 
+#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)
 
+#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)
 
+#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)
 
+#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)
 
+#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)
 
+#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)
 
+#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)
 
+#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)
 
+#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)
 
+#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)
 
+#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)
 
+#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)
 
+#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)
 
+#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)
 
+#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)
 
+#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)
 
+#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)
 
+#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)
 
+#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)
 
+#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)
 
+#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)
 
+#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)
 
+#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)
 
+#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)
 
+#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)
 
+#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)
 
+#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)
 
+#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)
 
+#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)
 
+#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)
 
+#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)
 
+#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)
 
+#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)
 
+#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)
 
+#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)
 
+#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)
 
+#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)
 
+#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)
 
+#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)
 
+#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)
 
+#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)
 
+#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)
 
+#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)
 
+#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)
 
+#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)
 
+#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)
 
+#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)
 
+#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)
 
+#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)
 
+#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)
 
+#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)
 
+#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)
 
+#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)
 
+#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)
 
+#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)
 
+#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)
 
+#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)
 
+#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)
 
+#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)
 
+#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)
 
+#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)
 
+#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)
 
+#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)
 
+#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)
 
+#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)
 
+#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)
 
+#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)
 
+#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)
 
+#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)
 
+#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)
 
+#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)
 
+#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)
 
+#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)
 
+#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)
 
+#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)
 
+#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)
 
+#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)
 
+#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)
 
+#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)
 
+#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)
 
+#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)
 
+#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)
 
#define DMA2D_CR_START   ((uint32_t)0x00000001)
 
#define DMA2D_CR_SUSP   ((uint32_t)0x00000002)
 
#define DMA2D_CR_ABORT   ((uint32_t)0x00000004)
 
#define DMA2D_CR_TEIE   ((uint32_t)0x00000100)
 
#define DMA2D_CR_TCIE   ((uint32_t)0x00000200)
 
#define DMA2D_CR_TWIE   ((uint32_t)0x00000400)
 
#define DMA2D_CR_CAEIE   ((uint32_t)0x00000800)
 
#define DMA2D_CR_CTCIE   ((uint32_t)0x00001000)
 
#define DMA2D_CR_CEIE   ((uint32_t)0x00002000)
 
#define DMA2D_CR_MODE   ((uint32_t)0x00030000)
 
#define DMA2D_ISR_TEIF   ((uint32_t)0x00000001)
 
#define DMA2D_ISR_TCIF   ((uint32_t)0x00000002)
 
#define DMA2D_ISR_TWIF   ((uint32_t)0x00000004)
 
#define DMA2D_ISR_CAEIF   ((uint32_t)0x00000008)
 
#define DMA2D_ISR_CTCIF   ((uint32_t)0x00000010)
 
#define DMA2D_ISR_CEIF   ((uint32_t)0x00000020)
 
#define DMA2D_IFSR_CTEIF   ((uint32_t)0x00000001)
 
#define DMA2D_IFSR_CTCIF   ((uint32_t)0x00000002)
 
#define DMA2D_IFSR_CTWIF   ((uint32_t)0x00000004)
 
#define DMA2D_IFSR_CCAEIF   ((uint32_t)0x00000008)
 
#define DMA2D_IFSR_CCTCIF   ((uint32_t)0x00000010)
 
#define DMA2D_IFSR_CCEIF   ((uint32_t)0x00000020)
 
#define DMA2D_FGMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_FGOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_BGMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_BGOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_FGPFCCR_CM   ((uint32_t)0x0000000F)
 
#define DMA2D_FGPFCCR_CCM   ((uint32_t)0x00000010)
 
#define DMA2D_FGPFCCR_START   ((uint32_t)0x00000020)
 
#define DMA2D_FGPFCCR_CS   ((uint32_t)0x0000FF00)
 
#define DMA2D_FGPFCCR_AM   ((uint32_t)0x00030000)
 
#define DMA2D_FGPFCCR_ALPHA   ((uint32_t)0xFF000000)
 
#define DMA2D_FGCOLR_BLUE   ((uint32_t)0x000000FF)
 
#define DMA2D_FGCOLR_GREEN   ((uint32_t)0x0000FF00)
 
#define DMA2D_FGCOLR_RED   ((uint32_t)0x00FF0000)
 
#define DMA2D_BGPFCCR_CM   ((uint32_t)0x0000000F)
 
#define DMA2D_BGPFCCR_CCM   ((uint32_t)0x00000010)
 
#define DMA2D_BGPFCCR_START   ((uint32_t)0x00000020)
 
#define DMA2D_BGPFCCR_CS   ((uint32_t)0x0000FF00)
 
#define DMA2D_BGPFCCR_AM   ((uint32_t)0x00030000)
 
#define DMA2D_BGPFCCR_ALPHA   ((uint32_t)0xFF000000)
 
#define DMA2D_BGCOLR_BLUE   ((uint32_t)0x000000FF)
 
#define DMA2D_BGCOLR_GREEN   ((uint32_t)0x0000FF00)
 
#define DMA2D_BGCOLR_RED   ((uint32_t)0x00FF0000)
 
#define DMA2D_FGCMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_BGCMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_OPFCCR_CM   ((uint32_t)0x00000007)
 
#define DMA2D_OCOLR_BLUE_1   ((uint32_t)0x000000FF)
 
#define DMA2D_OCOLR_GREEN_1   ((uint32_t)0x0000FF00)
 
#define DMA2D_OCOLR_RED_1   ((uint32_t)0x00FF0000)
 
#define DMA2D_OCOLR_ALPHA_1   ((uint32_t)0xFF000000)
 
#define DMA2D_OCOLR_BLUE_2   ((uint32_t)0x0000001F)
 
#define DMA2D_OCOLR_GREEN_2   ((uint32_t)0x000007E0)
 
#define DMA2D_OCOLR_RED_2   ((uint32_t)0x0000F800)
 
#define DMA2D_OCOLR_BLUE_3   ((uint32_t)0x0000001F)
 
#define DMA2D_OCOLR_GREEN_3   ((uint32_t)0x000003E0)
 
#define DMA2D_OCOLR_RED_3   ((uint32_t)0x00007C00)
 
#define DMA2D_OCOLR_ALPHA_3   ((uint32_t)0x00008000)
 
#define DMA2D_OCOLR_BLUE_4   ((uint32_t)0x0000000F)
 
#define DMA2D_OCOLR_GREEN_4   ((uint32_t)0x000000F0)
 
#define DMA2D_OCOLR_RED_4   ((uint32_t)0x00000F00)
 
#define DMA2D_OCOLR_ALPHA_4   ((uint32_t)0x0000F000)
 
#define DMA2D_OMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_OOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_NLR_NL   ((uint32_t)0x0000FFFF)
 
#define DMA2D_NLR_PL   ((uint32_t)0x3FFF0000)
 
#define DMA2D_LWR_LW   ((uint32_t)0x0000FFFF)
 
#define DMA2D_AMTCR_EN   ((uint32_t)0x00000001)
 
#define DMA2D_AMTCR_DT   ((uint32_t)0x0000FF00)
 
#define EXTI_IMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_IMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_IMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_IMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_IMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_IMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_IMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_IMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_IMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_IMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_IMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_IMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_IMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_IMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_IMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_IMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_IMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_IMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_IMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_IMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_EMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_EMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_EMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_EMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_EMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_EMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_EMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_EMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_EMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_EMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_EMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_EMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_EMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_EMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_EMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_EMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_EMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_EMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_EMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_EMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
 
#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
 
#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
 
#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
 
#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
 
#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
 
#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
 
#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
 
#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
 
#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
 
#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
 
#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
 
#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
 
#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
 
#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
 
#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
 
#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
 
#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
 
#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
 
#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
 
#define EXTI_PR_PR0   ((uint32_t)0x00000001)
 
#define EXTI_PR_PR1   ((uint32_t)0x00000002)
 
#define EXTI_PR_PR2   ((uint32_t)0x00000004)
 
#define EXTI_PR_PR3   ((uint32_t)0x00000008)
 
#define EXTI_PR_PR4   ((uint32_t)0x00000010)
 
#define EXTI_PR_PR5   ((uint32_t)0x00000020)
 
#define EXTI_PR_PR6   ((uint32_t)0x00000040)
 
#define EXTI_PR_PR7   ((uint32_t)0x00000080)
 
#define EXTI_PR_PR8   ((uint32_t)0x00000100)
 
#define EXTI_PR_PR9   ((uint32_t)0x00000200)
 
#define EXTI_PR_PR10   ((uint32_t)0x00000400)
 
#define EXTI_PR_PR11   ((uint32_t)0x00000800)
 
#define EXTI_PR_PR12   ((uint32_t)0x00001000)
 
#define EXTI_PR_PR13   ((uint32_t)0x00002000)
 
#define EXTI_PR_PR14   ((uint32_t)0x00004000)
 
#define EXTI_PR_PR15   ((uint32_t)0x00008000)
 
#define EXTI_PR_PR16   ((uint32_t)0x00010000)
 
#define EXTI_PR_PR17   ((uint32_t)0x00020000)
 
#define EXTI_PR_PR18   ((uint32_t)0x00040000)
 
#define EXTI_PR_PR19   ((uint32_t)0x00080000)
 
+#define FLASH_ACR_LATENCY   ((uint32_t)0x0000000F)
 
+#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)
 
+#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)
 
+#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)
 
+#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)
 
+#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)
 
+#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)
 
+#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)
 
+#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)
 
+#define FLASH_ACR_LATENCY_8WS   ((uint32_t)0x00000008)
 
+#define FLASH_ACR_LATENCY_9WS   ((uint32_t)0x00000009)
 
+#define FLASH_ACR_LATENCY_10WS   ((uint32_t)0x0000000A)
 
+#define FLASH_ACR_LATENCY_11WS   ((uint32_t)0x0000000B)
 
+#define FLASH_ACR_LATENCY_12WS   ((uint32_t)0x0000000C)
 
+#define FLASH_ACR_LATENCY_13WS   ((uint32_t)0x0000000D)
 
+#define FLASH_ACR_LATENCY_14WS   ((uint32_t)0x0000000E)
 
+#define FLASH_ACR_LATENCY_15WS   ((uint32_t)0x0000000F)
 
+#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)
 
+#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)
 
+#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)
 
+#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)
 
+#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)
 
+#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
 
+#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)
 
+#define FLASH_SR_EOP   ((uint32_t)0x00000001)
 
+#define FLASH_SR_SOP   ((uint32_t)0x00000002)
 
+#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)
 
+#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)
 
+#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)
 
+#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)
 
+#define FLASH_SR_BSY   ((uint32_t)0x00010000)
 
+#define FLASH_CR_PG   ((uint32_t)0x00000001)
 
+#define FLASH_CR_SER   ((uint32_t)0x00000002)
 
+#define FLASH_CR_MER   ((uint32_t)0x00000004)
 
+#define FLASH_CR_MER1   FLASH_CR_MER
 
+#define FLASH_CR_SNB   ((uint32_t)0x000000F8)
 
+#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)
 
+#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)
 
+#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)
 
+#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)
 
+#define FLASH_CR_SNB_4   ((uint32_t)0x00000040)
 
+#define FLASH_CR_PSIZE   ((uint32_t)0x00000300)
 
+#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)
 
+#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)
 
+#define FLASH_CR_MER2   ((uint32_t)0x00008000)
 
+#define FLASH_CR_STRT   ((uint32_t)0x00010000)
 
+#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)
 
+#define FLASH_CR_LOCK   ((uint32_t)0x80000000)
 
+#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)
 
+#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)
 
+#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)
 
+#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)
 
+#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)
 
+#define FLASH_OPTCR_BFB2   ((uint32_t)0x00000010)
 
+#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)
 
+#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)
 
+#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)
 
+#define FLASH_OPTCR_RDP   ((uint32_t)0x0000FF00)
 
+#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)
 
+#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)
 
+#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)
 
+#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)
 
+#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)
 
+#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)
 
+#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)
 
+#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)
 
+#define FLASH_OPTCR_nWRP   ((uint32_t)0x0FFF0000)
 
+#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)
 
+#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)
 
+#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)
 
+#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)
 
+#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)
 
+#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)
 
+#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)
 
+#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)
 
+#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)
 
+#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)
 
+#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)
 
+#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)
 
+#define FLASH_OPTCR_DB1M   ((uint32_t)0x40000000)
 
+#define FLASH_OPTCR_SPRMOD   ((uint32_t)0x80000000)
 
+#define FLASH_OPTCR1_nWRP   ((uint32_t)0x0FFF0000)
 
+#define FLASH_OPTCR1_nWRP_0   ((uint32_t)0x00010000)
 
+#define FLASH_OPTCR1_nWRP_1   ((uint32_t)0x00020000)
 
+#define FLASH_OPTCR1_nWRP_2   ((uint32_t)0x00040000)
 
+#define FLASH_OPTCR1_nWRP_3   ((uint32_t)0x00080000)
 
+#define FLASH_OPTCR1_nWRP_4   ((uint32_t)0x00100000)
 
+#define FLASH_OPTCR1_nWRP_5   ((uint32_t)0x00200000)
 
+#define FLASH_OPTCR1_nWRP_6   ((uint32_t)0x00400000)
 
+#define FLASH_OPTCR1_nWRP_7   ((uint32_t)0x00800000)
 
+#define FLASH_OPTCR1_nWRP_8   ((uint32_t)0x01000000)
 
+#define FLASH_OPTCR1_nWRP_9   ((uint32_t)0x02000000)
 
+#define FLASH_OPTCR1_nWRP_10   ((uint32_t)0x04000000)
 
+#define FLASH_OPTCR1_nWRP_11   ((uint32_t)0x08000000)
 
#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_SR2_IRS   ((uint8_t)0x01)
 
#define FSMC_SR2_ILS   ((uint8_t)0x02)
 
#define FSMC_SR2_IFS   ((uint8_t)0x04)
 
#define FSMC_SR2_IREN   ((uint8_t)0x08)
 
#define FSMC_SR2_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR2_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR2_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR3_IRS   ((uint8_t)0x01)
 
#define FSMC_SR3_ILS   ((uint8_t)0x02)
 
#define FSMC_SR3_IFS   ((uint8_t)0x04)
 
#define FSMC_SR3_IREN   ((uint8_t)0x08)
 
#define FSMC_SR3_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR3_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR3_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR4_IRS   ((uint8_t)0x01)
 
#define FSMC_SR4_ILS   ((uint8_t)0x02)
 
#define FSMC_SR4_IFS   ((uint8_t)0x04)
 
#define FSMC_SR4_IREN   ((uint8_t)0x08)
 
#define FSMC_SR4_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR4_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR4_FEMPT   ((uint8_t)0x40)
 
#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
 
#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
 
+#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)
 
+#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
 
+#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
 
+#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
 
+#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
 
+#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
 
+#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)
 
+#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
 
+#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
 
+#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
 
+#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
 
+#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
 
+#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)
 
+#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
 
+#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
 
+#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
 
+#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
 
+#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
 
+#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)
 
+#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
 
+#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
 
+#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
 
+#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
 
+#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
 
+#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)
 
+#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
 
+#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
 
+#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
 
+#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
 
+#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
 
+#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)
 
+#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
 
+#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
 
+#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
 
+#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
 
+#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
 
+#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)
 
+#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
 
+#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
 
+#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
 
+#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
 
+#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
 
+#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)
 
+#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
 
+#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
 
+#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
 
+#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
 
+#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
 
+#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
 
+#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
 
+#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
 
+#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
 
+#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
 
+#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
 
+#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
 
+#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
 
+#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
 
+#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
 
+#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
 
+#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
 
+#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
 
+#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
 
+#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
 
+#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
 
+#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
 
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
 
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
 
+#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
 
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
 
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
 
+#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
 
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
 
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
 
+#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
 
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
 
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
 
+#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
 
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
 
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
 
+#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
 
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
 
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
 
+#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
 
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
 
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
 
+#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
 
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
 
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
 
+#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
 
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
 
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
 
+#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
 
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
 
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
 
+#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
 
+#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
 
+#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
 
+#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
 
+#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
 
+#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
 
+#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
 
+#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
 
+#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
 
+#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
 
+#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
 
+#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
 
+#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
 
+#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
 
+#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
 
+#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
 
+#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
 
+#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
 
+#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
 
+#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
 
+#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
 
+#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
 
+#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
 
+#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
 
+#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
 
+#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
 
+#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
 
+#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
 
+#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
 
+#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
 
+#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
 
+#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
 
+#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
 
+#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
 
+#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
 
+#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
 
+#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
 
+#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
 
+#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
 
+#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
 
+#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
 
+#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
 
+#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
 
+#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
 
+#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
 
+#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
 
+#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
 
+#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
 
+#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
 
+#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
 
+#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
 
+#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
 
+#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
 
+#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
 
+#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
 
+#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
 
+#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
 
+#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)
 
+#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)
 
+#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)
 
+#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)
 
+#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)
 
+#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)
 
+#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)
 
+#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)
 
+#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)
 
+#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)
 
+#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)
 
+#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)
 
+#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)
 
+#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)
 
+#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)
 
+#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)
 
+#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0
 
+#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1
 
+#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2
 
+#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3
 
+#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4
 
+#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5
 
+#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6
 
+#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7
 
+#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8
 
+#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9
 
+#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10
 
+#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11
 
+#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12
 
+#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13
 
+#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14
 
+#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15
 
+#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)
 
+#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)
 
+#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)
 
+#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)
 
+#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)
 
+#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)
 
+#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)
 
+#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)
 
+#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)
 
+#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)
 
+#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)
 
+#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)
 
+#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)
 
+#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)
 
+#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)
 
+#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)
 
+#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0
 
+#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1
 
+#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2
 
+#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3
 
+#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4
 
+#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5
 
+#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6
 
+#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7
 
+#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8
 
+#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9
 
+#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10
 
+#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11
 
+#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12
 
+#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13
 
+#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14
 
+#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15
 
+#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
 
+#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
 
+#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
 
+#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
 
+#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
 
+#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
 
+#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
 
+#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
 
+#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
 
+#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
 
+#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
 
+#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
 
+#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
 
+#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
 
+#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
 
+#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
 
+#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
 
+#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
 
+#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
 
+#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
 
+#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
 
+#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
 
+#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
 
+#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
 
+#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
 
+#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
 
+#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
 
+#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
 
+#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
 
+#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
 
+#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
 
+#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
 
+#define HASH_CR_INIT   ((uint32_t)0x00000004)
 
+#define HASH_CR_DMAE   ((uint32_t)0x00000008)
 
+#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)
 
+#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)
 
+#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)
 
+#define HASH_CR_MODE   ((uint32_t)0x00000040)
 
+#define HASH_CR_ALGO   ((uint32_t)0x00040080)
 
+#define HASH_CR_ALGO_0   ((uint32_t)0x00000080)
 
+#define HASH_CR_ALGO_1   ((uint32_t)0x00040000)
 
+#define HASH_CR_NBW   ((uint32_t)0x00000F00)
 
+#define HASH_CR_NBW_0   ((uint32_t)0x00000100)
 
+#define HASH_CR_NBW_1   ((uint32_t)0x00000200)
 
+#define HASH_CR_NBW_2   ((uint32_t)0x00000400)
 
+#define HASH_CR_NBW_3   ((uint32_t)0x00000800)
 
+#define HASH_CR_DINNE   ((uint32_t)0x00001000)
 
+#define HASH_CR_MDMAT   ((uint32_t)0x00002000)
 
+#define HASH_CR_LKEY   ((uint32_t)0x00010000)
 
+#define HASH_STR_NBW   ((uint32_t)0x0000001F)
 
+#define HASH_STR_NBW_0   ((uint32_t)0x00000001)
 
+#define HASH_STR_NBW_1   ((uint32_t)0x00000002)
 
+#define HASH_STR_NBW_2   ((uint32_t)0x00000004)
 
+#define HASH_STR_NBW_3   ((uint32_t)0x00000008)
 
+#define HASH_STR_NBW_4   ((uint32_t)0x00000010)
 
+#define HASH_STR_DCAL   ((uint32_t)0x00000100)
 
+#define HASH_IMR_DINIM   ((uint32_t)0x00000001)
 
+#define HASH_IMR_DCIM   ((uint32_t)0x00000002)
 
+#define HASH_SR_DINIS   ((uint32_t)0x00000001)
 
+#define HASH_SR_DCIS   ((uint32_t)0x00000002)
 
+#define HASH_SR_DMAS   ((uint32_t)0x00000004)
 
+#define HASH_SR_BUSY   ((uint32_t)0x00000008)
 
#define I2C_CR1_PE   ((uint16_t)0x0001)
 
#define I2C_CR1_SMBUS   ((uint16_t)0x0002)
 
#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
 
#define I2C_CR1_ENARP   ((uint16_t)0x0010)
 
#define I2C_CR1_ENPEC   ((uint16_t)0x0020)
 
#define I2C_CR1_ENGC   ((uint16_t)0x0040)
 
#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
 
#define I2C_CR1_START   ((uint16_t)0x0100)
 
#define I2C_CR1_STOP   ((uint16_t)0x0200)
 
#define I2C_CR1_ACK   ((uint16_t)0x0400)
 
#define I2C_CR1_POS   ((uint16_t)0x0800)
 
#define I2C_CR1_PEC   ((uint16_t)0x1000)
 
#define I2C_CR1_ALERT   ((uint16_t)0x2000)
 
#define I2C_CR1_SWRST   ((uint16_t)0x8000)
 
#define I2C_CR2_FREQ   ((uint16_t)0x003F)
 
#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)
 
#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)
 
#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)
 
#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)
 
#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)
 
#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)
 
#define I2C_CR2_ITERREN   ((uint16_t)0x0100)
 
#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
 
#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
 
#define I2C_CR2_DMAEN   ((uint16_t)0x0800)
 
#define I2C_CR2_LAST   ((uint16_t)0x1000)
 
#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
 
#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
 
#define I2C_OAR1_ADD0   ((uint16_t)0x0001)
 
#define I2C_OAR1_ADD1   ((uint16_t)0x0002)
 
#define I2C_OAR1_ADD2   ((uint16_t)0x0004)
 
#define I2C_OAR1_ADD3   ((uint16_t)0x0008)
 
#define I2C_OAR1_ADD4   ((uint16_t)0x0010)
 
#define I2C_OAR1_ADD5   ((uint16_t)0x0020)
 
#define I2C_OAR1_ADD6   ((uint16_t)0x0040)
 
#define I2C_OAR1_ADD7   ((uint16_t)0x0080)
 
#define I2C_OAR1_ADD8   ((uint16_t)0x0100)
 
#define I2C_OAR1_ADD9   ((uint16_t)0x0200)
 
#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
 
#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)
 
#define I2C_OAR2_ADD2   ((uint8_t)0xFE)
 
#define I2C_DR_DR   ((uint8_t)0xFF)
 
#define I2C_SR1_SB   ((uint16_t)0x0001)
 
#define I2C_SR1_ADDR   ((uint16_t)0x0002)
 
#define I2C_SR1_BTF   ((uint16_t)0x0004)
 
#define I2C_SR1_ADD10   ((uint16_t)0x0008)
 
#define I2C_SR1_STOPF   ((uint16_t)0x0010)
 
#define I2C_SR1_RXNE   ((uint16_t)0x0040)
 
#define I2C_SR1_TXE   ((uint16_t)0x0080)
 
#define I2C_SR1_BERR   ((uint16_t)0x0100)
 
#define I2C_SR1_ARLO   ((uint16_t)0x0200)
 
#define I2C_SR1_AF   ((uint16_t)0x0400)
 
#define I2C_SR1_OVR   ((uint16_t)0x0800)
 
#define I2C_SR1_PECERR   ((uint16_t)0x1000)
 
#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
 
#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)
 
#define I2C_SR2_MSL   ((uint16_t)0x0001)
 
#define I2C_SR2_BUSY   ((uint16_t)0x0002)
 
#define I2C_SR2_TRA   ((uint16_t)0x0004)
 
#define I2C_SR2_GENCALL   ((uint16_t)0x0010)
 
#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
 
#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)
 
#define I2C_SR2_DUALF   ((uint16_t)0x0080)
 
#define I2C_SR2_PEC   ((uint16_t)0xFF00)
 
#define I2C_CCR_CCR   ((uint16_t)0x0FFF)
 
#define I2C_CCR_DUTY   ((uint16_t)0x4000)
 
#define I2C_CCR_FS   ((uint16_t)0x8000)
 
#define I2C_TRISE_TRISE   ((uint8_t)0x3F)
 
#define I2C_FLTR_DNF   ((uint8_t)0x0F)
 
#define I2C_FLTR_ANOFF   ((uint8_t)0x10)
 
#define IWDG_KR_KEY   ((uint16_t)0xFFFF)
 
#define IWDG_PR_PR   ((uint8_t)0x07)
 
#define IWDG_PR_PR_0   ((uint8_t)0x01)
 
#define IWDG_PR_PR_1   ((uint8_t)0x02)
 
#define IWDG_PR_PR_2   ((uint8_t)0x04)
 
#define IWDG_RLR_RL   ((uint16_t)0x0FFF)
 
#define IWDG_SR_PVU   ((uint8_t)0x01)
 
#define IWDG_SR_RVU   ((uint8_t)0x02)
 
#define LTDC_SSCR_VSH   ((uint32_t)0x000007FF)
 
#define LTDC_SSCR_HSW   ((uint32_t)0x0FFF0000)
 
#define LTDC_BPCR_AVBP   ((uint32_t)0x000007FF)
 
#define LTDC_BPCR_AHBP   ((uint32_t)0x0FFF0000)
 
#define LTDC_AWCR_AAH   ((uint32_t)0x000007FF)
 
#define LTDC_AWCR_AAW   ((uint32_t)0x0FFF0000)
 
#define LTDC_TWCR_TOTALH   ((uint32_t)0x000007FF)
 
#define LTDC_TWCR_TOTALW   ((uint32_t)0x0FFF0000)
 
#define LTDC_GCR_LTDCEN   ((uint32_t)0x00000001)
 
#define LTDC_GCR_DBW   ((uint32_t)0x00000070)
 
#define LTDC_GCR_DGW   ((uint32_t)0x00000700)
 
#define LTDC_GCR_DRW   ((uint32_t)0x00007000)
 
#define LTDC_GCR_DTEN   ((uint32_t)0x00010000)
 
#define LTDC_GCR_PCPOL   ((uint32_t)0x10000000)
 
#define LTDC_GCR_DEPOL   ((uint32_t)0x20000000)
 
#define LTDC_GCR_VSPOL   ((uint32_t)0x40000000)
 
#define LTDC_GCR_HSPOL   ((uint32_t)0x80000000)
 
#define LTDC_SRCR_IMR   ((uint32_t)0x00000001)
 
#define LTDC_SRCR_VBR   ((uint32_t)0x00000002)
 
#define LTDC_BCCR_BCBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_BCCR_BCGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_BCCR_BCRED   ((uint32_t)0x00FF0000)
 
#define LTDC_IER_LIE   ((uint32_t)0x00000001)
 
#define LTDC_IER_FUIE   ((uint32_t)0x00000002)
 
#define LTDC_IER_TERRIE   ((uint32_t)0x00000004)
 
#define LTDC_IER_RRIE   ((uint32_t)0x00000008)
 
#define LTDC_ISR_LIF   ((uint32_t)0x00000001)
 
#define LTDC_ISR_FUIF   ((uint32_t)0x00000002)
 
#define LTDC_ISR_TERRIF   ((uint32_t)0x00000004)
 
#define LTDC_ISR_RRIF   ((uint32_t)0x00000008)
 
#define LTDC_ICR_CLIF   ((uint32_t)0x00000001)
 
#define LTDC_ICR_CFUIF   ((uint32_t)0x00000002)
 
#define LTDC_ICR_CTERRIF   ((uint32_t)0x00000004)
 
#define LTDC_ICR_CRRIF   ((uint32_t)0x00000008)
 
#define LTDC_LIPCR_LIPOS   ((uint32_t)0x000007FF)
 
#define LTDC_CPSR_CYPOS   ((uint32_t)0x0000FFFF)
 
#define LTDC_CPSR_CXPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_CDSR_VDES   ((uint32_t)0x00000001)
 
#define LTDC_CDSR_HDES   ((uint32_t)0x00000002)
 
#define LTDC_CDSR_VSYNCS   ((uint32_t)0x00000004)
 
#define LTDC_CDSR_HSYNCS   ((uint32_t)0x00000008)
 
#define LTDC_LxCR_LEN   ((uint32_t)0x00000001)
 
#define LTDC_LxCR_COLKEN   ((uint32_t)0x00000002)
 
#define LTDC_LxCR_CLUTEN   ((uint32_t)0x00000010)
 
#define LTDC_LxWHPCR_WHSTPOS   ((uint32_t)0x00000FFF)
 
#define LTDC_LxWHPCR_WHSPPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_LxWVPCR_WVSTPOS   ((uint32_t)0x00000FFF)
 
#define LTDC_LxWVPCR_WVSPPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_LxCKCR_CKBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxCKCR_CKGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxCKCR_CKRED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxPFCR_PF   ((uint32_t)0x00000007)
 
#define LTDC_LxCACR_CONSTA   ((uint32_t)0x000000FF)
 
#define LTDC_LxDCCR_DCBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxDCCR_DCGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxDCCR_DCRED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxDCCR_DCALPHA   ((uint32_t)0xFF000000)
 
#define LTDC_LxBFCR_BF2   ((uint32_t)0x00000007)
 
#define LTDC_LxBFCR_BF1   ((uint32_t)0x00000700)
 
#define LTDC_LxCFBAR_CFBADD   ((uint32_t)0xFFFFFFFF)
 
#define LTDC_LxCFBLR_CFBLL   ((uint32_t)0x00001FFF)
 
#define LTDC_LxCFBLR_CFBP   ((uint32_t)0x1FFF0000)
 
#define LTDC_LxCFBLNR_CFBLNBR   ((uint32_t)0x000007FF)
 
#define LTDC_LxCLUTWR_BLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxCLUTWR_GREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxCLUTWR_RED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxCLUTWR_CLUTADD   ((uint32_t)0xFF000000)
 
#define PWR_CR_LPDS   ((uint32_t)0x00000001)
 
#define PWR_CR_PDDS   ((uint32_t)0x00000002)
 
#define PWR_CR_CWUF   ((uint32_t)0x00000004)
 
#define PWR_CR_CSBF   ((uint32_t)0x00000008)
 
#define PWR_CR_PVDE   ((uint32_t)0x00000010)
 
#define PWR_CR_PLS   ((uint32_t)0x000000E0)
 
#define PWR_CR_PLS_0   ((uint32_t)0x00000020)
 
#define PWR_CR_PLS_1   ((uint32_t)0x00000040)
 
#define PWR_CR_PLS_2   ((uint32_t)0x00000080)
 
#define PWR_CR_PLS_LEV0   ((uint32_t)0x00000000)
 
#define PWR_CR_PLS_LEV1   ((uint32_t)0x00000020)
 
#define PWR_CR_PLS_LEV2   ((uint32_t)0x00000040)
 
#define PWR_CR_PLS_LEV3   ((uint32_t)0x00000060)
 
#define PWR_CR_PLS_LEV4   ((uint32_t)0x00000080)
 
#define PWR_CR_PLS_LEV5   ((uint32_t)0x000000A0)
 
#define PWR_CR_PLS_LEV6   ((uint32_t)0x000000C0)
 
#define PWR_CR_PLS_LEV7   ((uint32_t)0x000000E0)
 
#define PWR_CR_DBP   ((uint32_t)0x00000100)
 
#define PWR_CR_FPDS   ((uint32_t)0x00000200)
 
#define PWR_CR_LPUDS   ((uint32_t)0x00000400)
 
#define PWR_CR_MRUDS   ((uint32_t)0x00000800)
 
#define PWR_CR_LPLVDS   ((uint32_t)0x00000400)
 
#define PWR_CR_MRLVDS   ((uint32_t)0x00000800)
 
#define PWR_CR_ADCDC1   ((uint32_t)0x00002000)
 
#define PWR_CR_VOS   ((uint32_t)0x0000C000)
 
#define PWR_CR_VOS_0   ((uint32_t)0x00004000)
 
#define PWR_CR_VOS_1   ((uint32_t)0x00008000)
 
#define PWR_CR_ODEN   ((uint32_t)0x00010000)
 
#define PWR_CR_ODSWEN   ((uint32_t)0x00020000)
 
#define PWR_CR_UDEN   ((uint32_t)0x000C0000)
 
#define PWR_CR_UDEN_0   ((uint32_t)0x00040000)
 
#define PWR_CR_UDEN_1   ((uint32_t)0x00080000)
 
#define PWR_CR_FMSSR   ((uint32_t)0x00100000)
 
#define PWR_CR_FISSR   ((uint32_t)0x00200000)
 
+#define PWR_CR_PMODE   PWR_CR_VOS
 
#define PWR_CSR_WUF   ((uint32_t)0x00000001)
 
#define PWR_CSR_SBF   ((uint32_t)0x00000002)
 
#define PWR_CSR_PVDO   ((uint32_t)0x00000004)
 
#define PWR_CSR_BRR   ((uint32_t)0x00000008)
 
#define PWR_CSR_EWUP   ((uint32_t)0x00000100)
 
#define PWR_CSR_BRE   ((uint32_t)0x00000200)
 
#define PWR_CSR_VOSRDY   ((uint32_t)0x00004000)
 
#define PWR_CSR_ODRDY   ((uint32_t)0x00010000)
 
#define PWR_CSR_ODSWRDY   ((uint32_t)0x00020000)
 
#define PWR_CSR_UDSWRDY   ((uint32_t)0x000C0000)
 
+#define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
 
+#define RCC_CR_HSION   ((uint32_t)0x00000001)
 
+#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)
 
+#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
 
#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)
 
#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)
 
#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)
 
#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)
 
#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)
 
+#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
 
#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100)
 
#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200)
 
#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400)
 
#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800)
 
#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000)
 
#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000)
 
#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000)
 
#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000)
 
+#define RCC_CR_HSEON   ((uint32_t)0x00010000)
 
+#define RCC_CR_HSERDY   ((uint32_t)0x00020000)
 
+#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)
 
+#define RCC_CR_CSSON   ((uint32_t)0x00080000)
 
+#define RCC_CR_PLLON   ((uint32_t)0x01000000)
 
+#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)
 
+#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)
 
+#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)
 
+#define RCC_CR_PLLSAION   ((uint32_t)0x10000000)
 
+#define RCC_CR_PLLSAIRDY   ((uint32_t)0x20000000)
 
+#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)
 
+#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)
 
+#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)
 
+#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)
 
+#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)
 
+#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)
 
+#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)
 
+#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)
 
+#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)
 
+#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)
 
+#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)
 
+#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)
 
+#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)
 
+#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)
 
+#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)
 
+#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)
 
+#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)
 
+#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)
 
+#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)
 
+#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)
 
+#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)
 
+#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
 
+#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)
 
+#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)
 
+#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)
 
+#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)
 
#define RCC_CFGR_SW   ((uint32_t)0x00000003)
 
#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)
 
#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
 
#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
 
#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
 
#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
 
#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
 
#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
 
#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
 
#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
 
#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
 
#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
 
#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
 
#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
 
#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
 
#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
 
#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
 
#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
 
#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
 
#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
 
#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
 
#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
 
#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)
 
+#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)
 
+#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)
 
+#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)
 
+#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)
 
+#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)
 
#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
 
+#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)
 
+#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)
 
+#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)
 
+#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)
 
+#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)
 
+#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)
 
+#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)
 
+#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)
 
+#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)
 
+#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)
 
+#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)
 
+#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)
 
+#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)
 
+#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)
 
+#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)
 
+#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
 
+#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
 
+#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
 
+#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
 
+#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
 
+#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)
 
+#define RCC_CIR_PLLSAIRDYF   ((uint32_t)0x00000040)
 
+#define RCC_CIR_CSSF   ((uint32_t)0x00000080)
 
+#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
 
+#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
 
+#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
 
+#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
 
+#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
 
+#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)
 
+#define RCC_CIR_PLLSAIRDYIE   ((uint32_t)0x00004000)
 
+#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
 
+#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
 
+#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
 
+#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
 
+#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
 
+#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)
 
+#define RCC_CIR_PLLSAIRDYC   ((uint32_t)0x00400000)
 
+#define RCC_CIR_CSSC   ((uint32_t)0x00800000)
 
+#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)
 
+#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)
 
+#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)
 
+#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)
 
+#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)
 
+#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)
 
+#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)
 
+#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)
 
+#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)
 
+#define RCC_AHB1RSTR_GPIOJRST   ((uint32_t)0x00000200)
 
+#define RCC_AHB1RSTR_GPIOKRST   ((uint32_t)0x00000400)
 
+#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)
 
+#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)
 
+#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)
 
+#define RCC_AHB1RSTR_DMA2DRST   ((uint32_t)0x00800000)
 
+#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)
 
+#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)
 
+#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)
 
+#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)
 
+#define RCC_AHB2RSTR_HASHRST   ((uint32_t)0x00000020)
 
+#define RCC_AHB2RSTR_HSAHRST   RCC_AHB2RSTR_HASHRST
 
+#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)
 
+#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)
 
+#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)
 
+#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
 
+#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
 
+#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
 
+#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
 
+#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
 
+#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
 
+#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)
 
+#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)
 
+#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)
 
+#define RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)
 
+#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)
 
+#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00008000)
 
+#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
 
+#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
 
+#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
 
+#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
 
+#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
 
+#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
 
+#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)
 
+#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
 
+#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)
 
+#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
 
+#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
 
+#define RCC_APB1RSTR_UART7RST   ((uint32_t)0x40000000)
 
+#define RCC_APB1RSTR_UART8RST   ((uint32_t)0x80000000)
 
+#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)
 
+#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)
 
+#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)
 
+#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)
 
+#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)
 
+#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
 
+#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
 
+#define RCC_APB2RSTR_SPI4RST   ((uint32_t)0x00002000)
 
+#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)
 
+#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)
 
+#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)
 
+#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)
 
+#define RCC_APB2RSTR_SPI5RST   ((uint32_t)0x00100000)
 
+#define RCC_APB2RSTR_SPI6RST   ((uint32_t)0x00200000)
 
+#define RCC_APB2RSTR_SAI1RST   ((uint32_t)0x00400000)
 
+#define RCC_APB2RSTR_LTDCRST   ((uint32_t)0x04000000)
 
+#define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
 
+#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)
 
+#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)
 
+#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)
 
+#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)
 
+#define RCC_AHB1ENR_GPIOJEN   ((uint32_t)0x00000200)
 
+#define RCC_AHB1ENR_GPIOKEN   ((uint32_t)0x00000400)
 
+#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)
 
+#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)
 
+#define RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)
 
+#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)
 
+#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)
 
+#define RCC_AHB1ENR_DMA2DEN   ((uint32_t)0x00800000)
 
+#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)
 
+#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)
 
+#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)
 
+#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)
 
+#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)
 
+#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
 
+#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
 
+#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
 
+#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
 
+#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
 
+#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
 
+#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)
 
+#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)
 
+#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)
 
+#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
 
+#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
 
+#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
 
+#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
 
+#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
 
+#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
 
+#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
 
+#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
 
+#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
 
+#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)
 
+#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
 
+#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)
 
+#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
 
+#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
 
+#define RCC_APB1ENR_UART7EN   ((uint32_t)0x40000000)
 
+#define RCC_APB1ENR_UART8EN   ((uint32_t)0x80000000)
 
+#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)
 
+#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)
 
+#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)
 
+#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)
 
+#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)
 
+#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)
 
+#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)
 
+#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
 
+#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
 
+#define RCC_APB2ENR_SPI4EN   ((uint32_t)0x00002000)
 
+#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)
 
+#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)
 
+#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)
 
+#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)
 
+#define RCC_APB2ENR_SPI5EN   ((uint32_t)0x00100000)
 
+#define RCC_APB2ENR_SPI6EN   ((uint32_t)0x00200000)
 
+#define RCC_APB2ENR_SAI1EN   ((uint32_t)0x00400000)
 
+#define RCC_APB2ENR_LTDCEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)
 
+#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)
 
+#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)
 
+#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)
 
+#define RCC_AHB1LPENR_GPIOJLPEN   ((uint32_t)0x00000200)
 
+#define RCC_AHB1LPENR_GPIOKLPEN   ((uint32_t)0x00000400)
 
+#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)
 
+#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)
 
+#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)
 
+#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)
 
+#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)
 
+#define RCC_AHB1LPENR_SRAM3LPEN   ((uint32_t)0x00080000)
 
+#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)
 
+#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)
 
+#define RCC_AHB1LPENR_DMA2DLPEN   ((uint32_t)0x00800000)
 
+#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)
 
+#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)
 
+#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)
 
+#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)
 
+#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)
 
+#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
 
+#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
 
+#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
 
+#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
 
+#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
 
+#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)
 
+#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)
 
+#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)
 
+#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
 
+#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
 
+#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
 
+#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
 
+#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
 
+#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
 
+#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
 
+#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
 
+#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
 
+#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)
 
+#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)
 
+#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)
 
+#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
 
+#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
 
+#define RCC_APB1LPENR_UART7LPEN   ((uint32_t)0x40000000)
 
+#define RCC_APB1LPENR_UART8LPEN   ((uint32_t)0x80000000)
 
+#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)
 
+#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)
 
+#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)
 
+#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)
 
+#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)
 
+#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)
 
+#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
 
+#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
 
+#define RCC_APB2LPENR_SPI4LPEN   ((uint32_t)0x00002000)
 
+#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)
 
+#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)
 
+#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)
 
+#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)
 
+#define RCC_APB2LPENR_SPI5LPEN   ((uint32_t)0x00100000)
 
+#define RCC_APB2LPENR_SPI6LPEN   ((uint32_t)0x00200000)
 
+#define RCC_APB2LPENR_SAI1LPEN   ((uint32_t)0x00400000)
 
+#define RCC_APB2LPENR_LTDCLPEN   ((uint32_t)0x04000000)
 
+#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)
 
+#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
 
+#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
 
+#define RCC_BDCR_LSEMOD   ((uint32_t)0x00000008)
 
+#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
 
+#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
 
+#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
 
+#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
 
+#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)
 
+#define RCC_CSR_LSION   ((uint32_t)0x00000001)
 
+#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
 
+#define RCC_CSR_RMVF   ((uint32_t)0x01000000)
 
+#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)
 
+#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)
 
+#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
 
+#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
 
+#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)
 
+#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
 
+#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
 
+#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)
 
+#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)
 
+#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)
 
+#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)
 
+#define RCC_PLLI2SCFGR_PLLI2SM   ((uint32_t)0x0000003F)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_0   ((uint32_t)0x00000001)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_1   ((uint32_t)0x00000002)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_2   ((uint32_t)0x00000004)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_3   ((uint32_t)0x00000008)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_4   ((uint32_t)0x00000010)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_5   ((uint32_t)0x00000020)
 
+#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLI2SCFGR_PLLI2SQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)
 
+#define RCC_PLLSAICFGR_PLLI2SN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLSAICFGR_PLLI2SQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLSAICFGR_PLLI2SR   ((uint32_t)0x70000000)
 
+#define RCC_DCKCFGR_PLLI2SDIVQ   ((uint32_t)0x0000001F)
 
+#define RCC_DCKCFGR_PLLSAIDIVQ   ((uint32_t)0x00001F00)
 
+#define RCC_DCKCFGR_PLLSAIDIVR   ((uint32_t)0x00030000)
 
+#define RCC_DCKCFGR_SAI1ASRC   ((uint32_t)0x00300000)
 
+#define RCC_DCKCFGR_SAI1BSRC   ((uint32_t)0x00C00000)
 
+#define RCC_DCKCFGR_TIMPRE   ((uint32_t)0x01000000)
 
+#define RNG_CR_RNGEN   ((uint32_t)0x00000004)
 
+#define RNG_CR_IE   ((uint32_t)0x00000008)
 
+#define RNG_SR_DRDY   ((uint32_t)0x00000001)
 
+#define RNG_SR_CECS   ((uint32_t)0x00000002)
 
+#define RNG_SR_SECS   ((uint32_t)0x00000004)
 
+#define RNG_SR_CEIS   ((uint32_t)0x00000020)
 
+#define RNG_SR_SEIS   ((uint32_t)0x00000040)
 
+#define RTC_TR_PM   ((uint32_t)0x00400000)
 
+#define RTC_TR_HT   ((uint32_t)0x00300000)
 
+#define RTC_TR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_TR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_TR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_TR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_TR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_TR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_TR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_TR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_TR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_TR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_TR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_TR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_TR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_TR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_TR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_TR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_TR_ST   ((uint32_t)0x00000070)
 
+#define RTC_TR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_TR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_TR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_TR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_TR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_TR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_TR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_TR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_DR_YT   ((uint32_t)0x00F00000)
 
+#define RTC_DR_YT_0   ((uint32_t)0x00100000)
 
+#define RTC_DR_YT_1   ((uint32_t)0x00200000)
 
+#define RTC_DR_YT_2   ((uint32_t)0x00400000)
 
+#define RTC_DR_YT_3   ((uint32_t)0x00800000)
 
+#define RTC_DR_YU   ((uint32_t)0x000F0000)
 
+#define RTC_DR_YU_0   ((uint32_t)0x00010000)
 
+#define RTC_DR_YU_1   ((uint32_t)0x00020000)
 
+#define RTC_DR_YU_2   ((uint32_t)0x00040000)
 
+#define RTC_DR_YU_3   ((uint32_t)0x00080000)
 
+#define RTC_DR_WDU   ((uint32_t)0x0000E000)
 
+#define RTC_DR_WDU_0   ((uint32_t)0x00002000)
 
+#define RTC_DR_WDU_1   ((uint32_t)0x00004000)
 
+#define RTC_DR_WDU_2   ((uint32_t)0x00008000)
 
+#define RTC_DR_MT   ((uint32_t)0x00001000)
 
+#define RTC_DR_MU   ((uint32_t)0x00000F00)
 
+#define RTC_DR_MU_0   ((uint32_t)0x00000100)
 
+#define RTC_DR_MU_1   ((uint32_t)0x00000200)
 
+#define RTC_DR_MU_2   ((uint32_t)0x00000400)
 
+#define RTC_DR_MU_3   ((uint32_t)0x00000800)
 
+#define RTC_DR_DT   ((uint32_t)0x00000030)
 
+#define RTC_DR_DT_0   ((uint32_t)0x00000010)
 
+#define RTC_DR_DT_1   ((uint32_t)0x00000020)
 
+#define RTC_DR_DU   ((uint32_t)0x0000000F)
 
+#define RTC_DR_DU_0   ((uint32_t)0x00000001)
 
+#define RTC_DR_DU_1   ((uint32_t)0x00000002)
 
+#define RTC_DR_DU_2   ((uint32_t)0x00000004)
 
+#define RTC_DR_DU_3   ((uint32_t)0x00000008)
 
+#define RTC_CR_COE   ((uint32_t)0x00800000)
 
+#define RTC_CR_OSEL   ((uint32_t)0x00600000)
 
+#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)
 
+#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)
 
+#define RTC_CR_POL   ((uint32_t)0x00100000)
 
+#define RTC_CR_COSEL   ((uint32_t)0x00080000)
 
+#define RTC_CR_BCK   ((uint32_t)0x00040000)
 
+#define RTC_CR_SUB1H   ((uint32_t)0x00020000)
 
+#define RTC_CR_ADD1H   ((uint32_t)0x00010000)
 
+#define RTC_CR_TSIE   ((uint32_t)0x00008000)
 
+#define RTC_CR_WUTIE   ((uint32_t)0x00004000)
 
+#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)
 
+#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)
 
+#define RTC_CR_TSE   ((uint32_t)0x00000800)
 
+#define RTC_CR_WUTE   ((uint32_t)0x00000400)
 
+#define RTC_CR_ALRBE   ((uint32_t)0x00000200)
 
+#define RTC_CR_ALRAE   ((uint32_t)0x00000100)
 
+#define RTC_CR_DCE   ((uint32_t)0x00000080)
 
+#define RTC_CR_FMT   ((uint32_t)0x00000040)
 
+#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)
 
+#define RTC_CR_REFCKON   ((uint32_t)0x00000010)
 
+#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)
 
+#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
 
+#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
 
+#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
 
+#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
 
+#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)
 
+#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
 
+#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)
 
+#define RTC_ISR_TSF   ((uint32_t)0x00000800)
 
+#define RTC_ISR_WUTF   ((uint32_t)0x00000400)
 
+#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)
 
+#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)
 
+#define RTC_ISR_INIT   ((uint32_t)0x00000080)
 
+#define RTC_ISR_INITF   ((uint32_t)0x00000040)
 
+#define RTC_ISR_RSF   ((uint32_t)0x00000020)
 
+#define RTC_ISR_INITS   ((uint32_t)0x00000010)
 
+#define RTC_ISR_SHPF   ((uint32_t)0x00000008)
 
+#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)
 
+#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
 
+#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
 
+#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
 
+#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)
 
+#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
 
+#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)
 
+#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)
 
+#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
 
+#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
 
+#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)
 
+#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
 
+#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
 
+#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
 
+#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)
 
+#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)
 
+#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
 
+#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
 
+#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)
 
+#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
 
+#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
 
+#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)
 
+#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
 
+#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
 
+#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
 
+#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)
 
+#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)
 
+#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
 
+#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
 
+#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)
 
+#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_WPR_KEY   ((uint32_t)0x000000FF)
 
+#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)
 
+#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)
 
+#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)
 
+#define RTC_TSTR_PM   ((uint32_t)0x00400000)
 
+#define RTC_TSTR_HT   ((uint32_t)0x00300000)
 
+#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_TSTR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_TSTR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_TSTR_ST   ((uint32_t)0x00000070)
 
+#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_TSTR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)
 
+#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
 
+#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
 
+#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
 
+#define RTC_TSDR_MT   ((uint32_t)0x00001000)
 
+#define RTC_TSDR_MU   ((uint32_t)0x00000F00)
 
+#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)
 
+#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)
 
+#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)
 
+#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)
 
+#define RTC_TSDR_DT   ((uint32_t)0x00000030)
 
+#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)
 
+#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)
 
+#define RTC_TSDR_DU   ((uint32_t)0x0000000F)
 
+#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)
 
+#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)
 
+#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)
 
+#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)
 
+#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)
 
+#define RTC_CALR_CALP   ((uint32_t)0x00008000)
 
+#define RTC_CALR_CALW8   ((uint32_t)0x00004000)
 
+#define RTC_CALR_CALW16   ((uint32_t)0x00002000)
 
+#define RTC_CALR_CALM   ((uint32_t)0x000001FF)
 
+#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)
 
+#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)
 
+#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)
 
+#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)
 
+#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)
 
+#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)
 
+#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)
 
+#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)
 
+#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)
 
+#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
 
+#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)
 
+#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)
 
+#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)
 
+#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)
 
+#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)
 
+#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)
 
+#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)
 
+#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)
 
+#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)
 
+#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)
 
+#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)
 
+#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)
 
+#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)
 
+#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)
 
+#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
 
+#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
 
+#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
 
+#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)
 
+#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)
 
+#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
 
#define SAI_GCR_SYNCIN   ((uint32_t)0x00000003)
 
#define SAI_GCR_SYNCIN_0   ((uint32_t)0x00000001)
 
#define SAI_GCR_SYNCIN_1   ((uint32_t)0x00000002)
 
#define SAI_GCR_SYNCOUT   ((uint32_t)0x00000030)
 
#define SAI_GCR_SYNCOUT_0   ((uint32_t)0x00000010)
 
#define SAI_GCR_SYNCOUT_1   ((uint32_t)0x00000020)
 
#define SAI_xCR1_MODE   ((uint32_t)0x00000003)
 
#define SAI_xCR1_MODE_0   ((uint32_t)0x00000001)
 
#define SAI_xCR1_MODE_1   ((uint32_t)0x00000002)
 
#define SAI_xCR1_PRTCFG   ((uint32_t)0x0000000C)
 
#define SAI_xCR1_PRTCFG_0   ((uint32_t)0x00000004)
 
#define SAI_xCR1_PRTCFG_1   ((uint32_t)0x00000008)
 
#define SAI_xCR1_DS   ((uint32_t)0x000000E0)
 
#define SAI_xCR1_DS_0   ((uint32_t)0x00000020)
 
#define SAI_xCR1_DS_1   ((uint32_t)0x00000040)
 
#define SAI_xCR1_DS_2   ((uint32_t)0x00000080)
 
#define SAI_xCR1_LSBFIRST   ((uint32_t)0x00000100)
 
#define SAI_xCR1_CKSTR   ((uint32_t)0x00000200)
 
#define SAI_xCR1_SYNCEN   ((uint32_t)0x00000C00)
 
#define SAI_xCR1_SYNCEN_0   ((uint32_t)0x00000400)
 
#define SAI_xCR1_SYNCEN_1   ((uint32_t)0x00000800)
 
#define SAI_xCR1_MONO   ((uint32_t)0x00001000)
 
#define SAI_xCR1_OUTDRIV   ((uint32_t)0x00002000)
 
#define SAI_xCR1_SAIEN   ((uint32_t)0x00010000)
 
#define SAI_xCR1_DMAEN   ((uint32_t)0x00020000)
 
#define SAI_xCR1_NODIV   ((uint32_t)0x00080000)
 
#define SAI_xCR1_MCKDIV   ((uint32_t)0x00780000)
 
#define SAI_xCR1_MCKDIV_0   ((uint32_t)0x00080000)
 
#define SAI_xCR1_MCKDIV_1   ((uint32_t)0x00100000)
 
#define SAI_xCR1_MCKDIV_2   ((uint32_t)0x00200000)
 
#define SAI_xCR1_MCKDIV_3   ((uint32_t)0x00400000)
 
#define SAI_xCR2_FTH   ((uint32_t)0x00000003)
 
#define SAI_xCR2_FTH_0   ((uint32_t)0x00000001)
 
#define SAI_xCR2_FTH_1   ((uint32_t)0x00000002)
 
#define SAI_xCR2_FFLUSH   ((uint32_t)0x00000008)
 
#define SAI_xCR2_TRIS   ((uint32_t)0x00000010)
 
#define SAI_xCR2_MUTE   ((uint32_t)0x00000020)
 
#define SAI_xCR2_MUTEVAL   ((uint32_t)0x00000040)
 
#define SAI_xCR2_MUTECNT   ((uint32_t)0x00001F80)
 
#define SAI_xCR2_MUTECNT_0   ((uint32_t)0x00000080)
 
#define SAI_xCR2_MUTECNT_1   ((uint32_t)0x00000100)
 
#define SAI_xCR2_MUTECNT_2   ((uint32_t)0x00000200)
 
#define SAI_xCR2_MUTECNT_3   ((uint32_t)0x00000400)
 
#define SAI_xCR2_MUTECNT_4   ((uint32_t)0x00000800)
 
#define SAI_xCR2_MUTECNT_5   ((uint32_t)0x00001000)
 
#define SAI_xCR2_CPL   ((uint32_t)0x00080000)
 
#define SAI_xCR2_COMP   ((uint32_t)0x0000C000)
 
#define SAI_xCR2_COMP_0   ((uint32_t)0x00004000)
 
#define SAI_xCR2_COMP_1   ((uint32_t)0x00008000)
 
#define SAI_xFRCR_FRL   ((uint32_t)0x000000FF)
 
#define SAI_xFRCR_FRL_0   ((uint32_t)0x00000001)
 
#define SAI_xFRCR_FRL_1   ((uint32_t)0x00000002)
 
#define SAI_xFRCR_FRL_2   ((uint32_t)0x00000004)
 
#define SAI_xFRCR_FRL_3   ((uint32_t)0x00000008)
 
#define SAI_xFRCR_FRL_4   ((uint32_t)0x00000010)
 
#define SAI_xFRCR_FRL_5   ((uint32_t)0x00000020)
 
#define SAI_xFRCR_FRL_6   ((uint32_t)0x00000040)
 
#define SAI_xFRCR_FRL_7   ((uint32_t)0x00000080)
 
#define SAI_xFRCR_FSALL   ((uint32_t)0x00007F00)
 
#define SAI_xFRCR_FSALL_0   ((uint32_t)0x00000100)
 
#define SAI_xFRCR_FSALL_1   ((uint32_t)0x00000200)
 
#define SAI_xFRCR_FSALL_2   ((uint32_t)0x00000400)
 
#define SAI_xFRCR_FSALL_3   ((uint32_t)0x00000800)
 
#define SAI_xFRCR_FSALL_4   ((uint32_t)0x00001000)
 
#define SAI_xFRCR_FSALL_5   ((uint32_t)0x00002000)
 
#define SAI_xFRCR_FSALL_6   ((uint32_t)0x00004000)
 
#define SAI_xFRCR_FSDEF   ((uint32_t)0x00010000)
 
#define SAI_xFRCR_FSPO   ((uint32_t)0x00020000)
 
#define SAI_xFRCR_FSOFF   ((uint32_t)0x00040000)
 
#define SAI_xSLOTR_FBOFF   ((uint32_t)0x0000001F)
 
#define SAI_xSLOTR_FBOFF_0   ((uint32_t)0x00000001)
 
#define SAI_xSLOTR_FBOFF_1   ((uint32_t)0x00000002)
 
#define SAI_xSLOTR_FBOFF_2   ((uint32_t)0x00000004)
 
#define SAI_xSLOTR_FBOFF_3   ((uint32_t)0x00000008)
 
#define SAI_xSLOTR_FBOFF_4   ((uint32_t)0x00000010)
 
#define SAI_xSLOTR_SLOTSZ   ((uint32_t)0x000000C0)
 
#define SAI_xSLOTR_SLOTSZ_0   ((uint32_t)0x00000040)
 
#define SAI_xSLOTR_SLOTSZ_1   ((uint32_t)0x00000080)
 
#define SAI_xSLOTR_NBSLOT   ((uint32_t)0x00000F00)
 
#define SAI_xSLOTR_NBSLOT_0   ((uint32_t)0x00000100)
 
#define SAI_xSLOTR_NBSLOT_1   ((uint32_t)0x00000200)
 
#define SAI_xSLOTR_NBSLOT_2   ((uint32_t)0x00000400)
 
#define SAI_xSLOTR_NBSLOT_3   ((uint32_t)0x00000800)
 
#define SAI_xSLOTR_SLOTEN   ((uint32_t)0xFFFF0000)
 
#define SAI_xIMR_OVRUDRIE   ((uint32_t)0x00000001)
 
#define SAI_xIMR_MUTEDETIE   ((uint32_t)0x00000002)
 
#define SAI_xIMR_WCKCFGIE   ((uint32_t)0x00000004)
 
#define SAI_xIMR_FREQIE   ((uint32_t)0x00000008)
 
#define SAI_xIMR_CNRDYIE   ((uint32_t)0x00000010)
 
#define SAI_xIMR_AFSDETIE   ((uint32_t)0x00000020)
 
#define SAI_xIMR_LFSDETIE   ((uint32_t)0x00000040)
 
#define SAI_xSR_OVRUDR   ((uint32_t)0x00000001)
 
#define SAI_xSR_MUTEDET   ((uint32_t)0x00000002)
 
#define SAI_xSR_WCKCFG   ((uint32_t)0x00000004)
 
#define SAI_xSR_FREQ   ((uint32_t)0x00000008)
 
#define SAI_xSR_CNRDY   ((uint32_t)0x00000010)
 
#define SAI_xSR_AFSDET   ((uint32_t)0x00000020)
 
#define SAI_xSR_LFSDET   ((uint32_t)0x00000040)
 
#define SAI_xSR_FLVL   ((uint32_t)0x00070000)
 
#define SAI_xSR_FLVL_0   ((uint32_t)0x00010000)
 
#define SAI_xSR_FLVL_1   ((uint32_t)0x00020000)
 
#define SAI_xSR_FLVL_2   ((uint32_t)0x00030000)
 
#define SAI_xCLRFR_COVRUDR   ((uint32_t)0x00000001)
 
#define SAI_xCLRFR_CMUTEDET   ((uint32_t)0x00000002)
 
#define SAI_xCLRFR_CWCKCFG   ((uint32_t)0x00000004)
 
#define SAI_xCLRFR_CFREQ   ((uint32_t)0x00000008)
 
#define SAI_xCLRFR_CCNRDY   ((uint32_t)0x00000010)
 
#define SAI_xCLRFR_CAFSDET   ((uint32_t)0x00000020)
 
#define SAI_xCLRFR_CLFSDET   ((uint32_t)0x00000040)
 
+#define SAI_xDR_DATA   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
 
#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
 
#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
 
#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
 
#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
 
#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
 
#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
 
#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
 
#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
 
#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
 
#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
 
#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
 
#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
 
#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
 
#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
 
#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
 
#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)
 
#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
 
#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
 
#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
 
#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
 
#define SDIO_CMD_NIEN   ((uint16_t)0x2000)
 
#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
 
#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
 
#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
 
#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
 
#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
 
#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
 
#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
 
#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
 
#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
 
#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
 
#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
 
#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
 
#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
 
#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
 
#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
 
#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
 
#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
 
#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
 
#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
 
#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
 
#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
 
#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
 
#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
 
#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)
 
#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
 
#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)
 
#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)
 
#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
 
#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)
 
#define SDIO_STA_TXACT   ((uint32_t)0x00001000)
 
#define SDIO_STA_RXACT   ((uint32_t)0x00002000)
 
#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
 
#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
 
#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
 
#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
 
#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
 
#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
 
#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
 
#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
 
#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
 
#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
 
#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
 
#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
 
#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
 
#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
 
#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
 
#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
 
#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
 
#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
 
#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
 
#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
 
#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
 
#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
 
#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
 
#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
 
#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
 
#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
 
#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
 
#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
 
#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
 
#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
 
#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
 
#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
 
#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
 
#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
 
#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
 
#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
 
#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
 
#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
 
#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
 
#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
 
#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
 
#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
 
#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
 
#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
 
#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
 
#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
 
#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
 
#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
 
#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
 
#define SPI_CR1_CPHA   ((uint16_t)0x0001)
 
#define SPI_CR1_CPOL   ((uint16_t)0x0002)
 
#define SPI_CR1_MSTR   ((uint16_t)0x0004)
 
#define SPI_CR1_BR   ((uint16_t)0x0038)
 
#define SPI_CR1_BR_0   ((uint16_t)0x0008)
 
#define SPI_CR1_BR_1   ((uint16_t)0x0010)
 
#define SPI_CR1_BR_2   ((uint16_t)0x0020)
 
#define SPI_CR1_SPE   ((uint16_t)0x0040)
 
#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
 
#define SPI_CR1_SSI   ((uint16_t)0x0100)
 
#define SPI_CR1_SSM   ((uint16_t)0x0200)
 
#define SPI_CR1_RXONLY   ((uint16_t)0x0400)
 
#define SPI_CR1_DFF   ((uint16_t)0x0800)
 
#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
 
#define SPI_CR1_CRCEN   ((uint16_t)0x2000)
 
#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)
 
#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
 
#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)
 
#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)
 
#define SPI_CR2_SSOE   ((uint8_t)0x04)
 
#define SPI_CR2_ERRIE   ((uint8_t)0x20)
 
#define SPI_CR2_RXNEIE   ((uint8_t)0x40)
 
#define SPI_CR2_TXEIE   ((uint8_t)0x80)
 
#define SPI_SR_RXNE   ((uint8_t)0x01)
 
#define SPI_SR_TXE   ((uint8_t)0x02)
 
#define SPI_SR_CHSIDE   ((uint8_t)0x04)
 
#define SPI_SR_UDR   ((uint8_t)0x08)
 
#define SPI_SR_CRCERR   ((uint8_t)0x10)
 
#define SPI_SR_MODF   ((uint8_t)0x20)
 
#define SPI_SR_OVR   ((uint8_t)0x40)
 
#define SPI_SR_BSY   ((uint8_t)0x80)
 
#define SPI_DR_DR   ((uint16_t)0xFFFF)
 
#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
 
#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
 
#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
 
#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
 
#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
 
#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
 
#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
 
#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
 
#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
 
#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
 
#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
 
#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
 
#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
 
#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
 
#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
 
#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
 
#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
 
#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
 
#define SPI_I2SPR_ODD   ((uint16_t)0x0100)
 
#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
 
#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000007)
 
#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
 
#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
 
#define SYSCFG_MEMRMP_MEM_MODE_2   ((uint32_t)0x00000004)
 
#define SYSCFG_MEMRMP_FB_MODE   ((uint32_t)0x00000100)
 
#define SYSCFG_MEMRMP_SWP_FMC   ((uint32_t)0x00000C00)
 
#define SYSCFG_MEMRMP_SWP_FMC_0   ((uint32_t)0x00000400)
 
#define SYSCFG_MEMRMP_SWP_FMC_1   ((uint32_t)0x00000800)
 
#define SYSCFG_PMC_ADCxDC2   ((uint32_t)0x00070000)
 
#define SYSCFG_PMC_ADC1DC2   ((uint32_t)0x00010000)
 
#define SYSCFG_PMC_ADC2DC2   ((uint32_t)0x00020000)
 
#define SYSCFG_PMC_ADC3DC2   ((uint32_t)0x00040000)
 
#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)
 
+#define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
 
#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
 EXTI0 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR1_EXTI0_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR1_EXTI0_PK   ((uint16_t)0x000A)
 
#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
 EXTI1 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR1_EXTI1_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR1_EXTI1_PK   ((uint16_t)0x00A0)
 
#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
 EXTI2 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR1_EXTI2_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR1_EXTI2_PK   ((uint16_t)0x0A00)
 
#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
 EXTI3 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR1_EXTI3_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR1_EXTI3_PK   ((uint16_t)0xA000)
 
#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
 EXTI4 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR2_EXTI4_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR2_EXTI4_PK   ((uint16_t)0x000A)
 
#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
 EXTI5 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR2_EXTI5_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR2_EXTI5_PK   ((uint16_t)0x00A0)
 
#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
 EXTI6 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR2_EXTI6_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR2_EXTI6_PK   ((uint16_t)0x0A00)
 
#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
 EXTI7 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR2_EXTI7_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR2_EXTI7_PK   ((uint16_t)0xA000)
 
#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
 EXTI8 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR3_EXTI8_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
 EXTI9 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR3_EXTI9_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
 EXTI10 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR3_EXTI10_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
 EXTI11 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR3_EXTI11_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
 EXTI12 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR4_EXTI12_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR4_EXTI12_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR4_EXTI12_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
 EXTI13 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR4_EXTI13_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR4_EXTI13_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR4_EXTI13_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
 EXTI14 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR4_EXTI14_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR4_EXTI14_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR4_EXTI14_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
 EXTI15 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR4_EXTI15_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR4_EXTI15_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR4_EXTI15_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
 
#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
 
#define TIM_CR1_CEN   ((uint16_t)0x0001)
 
#define TIM_CR1_UDIS   ((uint16_t)0x0002)
 
#define TIM_CR1_URS   ((uint16_t)0x0004)
 
#define TIM_CR1_OPM   ((uint16_t)0x0008)
 
#define TIM_CR1_DIR   ((uint16_t)0x0010)
 
#define TIM_CR1_CMS   ((uint16_t)0x0060)
 
#define TIM_CR1_CMS_0   ((uint16_t)0x0020)
 
#define TIM_CR1_CMS_1   ((uint16_t)0x0040)
 
#define TIM_CR1_ARPE   ((uint16_t)0x0080)
 
#define TIM_CR1_CKD   ((uint16_t)0x0300)
 
#define TIM_CR1_CKD_0   ((uint16_t)0x0100)
 
#define TIM_CR1_CKD_1   ((uint16_t)0x0200)
 
#define TIM_CR2_CCPC   ((uint16_t)0x0001)
 
#define TIM_CR2_CCUS   ((uint16_t)0x0004)
 
#define TIM_CR2_CCDS   ((uint16_t)0x0008)
 
#define TIM_CR2_MMS   ((uint16_t)0x0070)
 
#define TIM_CR2_MMS_0   ((uint16_t)0x0010)
 
#define TIM_CR2_MMS_1   ((uint16_t)0x0020)
 
#define TIM_CR2_MMS_2   ((uint16_t)0x0040)
 
#define TIM_CR2_TI1S   ((uint16_t)0x0080)
 
#define TIM_CR2_OIS1   ((uint16_t)0x0100)
 
#define TIM_CR2_OIS1N   ((uint16_t)0x0200)
 
#define TIM_CR2_OIS2   ((uint16_t)0x0400)
 
#define TIM_CR2_OIS2N   ((uint16_t)0x0800)
 
#define TIM_CR2_OIS3   ((uint16_t)0x1000)
 
#define TIM_CR2_OIS3N   ((uint16_t)0x2000)
 
#define TIM_CR2_OIS4   ((uint16_t)0x4000)
 
#define TIM_SMCR_SMS   ((uint16_t)0x0007)
 
#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)
 
#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)
 
#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)
 
#define TIM_SMCR_TS   ((uint16_t)0x0070)
 
#define TIM_SMCR_TS_0   ((uint16_t)0x0010)
 
#define TIM_SMCR_TS_1   ((uint16_t)0x0020)
 
#define TIM_SMCR_TS_2   ((uint16_t)0x0040)
 
#define TIM_SMCR_MSM   ((uint16_t)0x0080)
 
#define TIM_SMCR_ETF   ((uint16_t)0x0F00)
 
#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)
 
#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)
 
#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)
 
#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)
 
#define TIM_SMCR_ETPS   ((uint16_t)0x3000)
 
#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
 
#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
 
#define TIM_SMCR_ECE   ((uint16_t)0x4000)
 
#define TIM_SMCR_ETP   ((uint16_t)0x8000)
 
#define TIM_DIER_UIE   ((uint16_t)0x0001)
 
#define TIM_DIER_CC1IE   ((uint16_t)0x0002)
 
#define TIM_DIER_CC2IE   ((uint16_t)0x0004)
 
#define TIM_DIER_CC3IE   ((uint16_t)0x0008)
 
#define TIM_DIER_CC4IE   ((uint16_t)0x0010)
 
#define TIM_DIER_COMIE   ((uint16_t)0x0020)
 
#define TIM_DIER_TIE   ((uint16_t)0x0040)
 
#define TIM_DIER_BIE   ((uint16_t)0x0080)
 
#define TIM_DIER_UDE   ((uint16_t)0x0100)
 
#define TIM_DIER_CC1DE   ((uint16_t)0x0200)
 
#define TIM_DIER_CC2DE   ((uint16_t)0x0400)
 
#define TIM_DIER_CC3DE   ((uint16_t)0x0800)
 
#define TIM_DIER_CC4DE   ((uint16_t)0x1000)
 
#define TIM_DIER_COMDE   ((uint16_t)0x2000)
 
#define TIM_DIER_TDE   ((uint16_t)0x4000)
 
#define TIM_SR_UIF   ((uint16_t)0x0001)
 
#define TIM_SR_CC1IF   ((uint16_t)0x0002)
 
#define TIM_SR_CC2IF   ((uint16_t)0x0004)
 
#define TIM_SR_CC3IF   ((uint16_t)0x0008)
 
#define TIM_SR_CC4IF   ((uint16_t)0x0010)
 
#define TIM_SR_COMIF   ((uint16_t)0x0020)
 
#define TIM_SR_TIF   ((uint16_t)0x0040)
 
#define TIM_SR_BIF   ((uint16_t)0x0080)
 
#define TIM_SR_CC1OF   ((uint16_t)0x0200)
 
#define TIM_SR_CC2OF   ((uint16_t)0x0400)
 
#define TIM_SR_CC3OF   ((uint16_t)0x0800)
 
#define TIM_SR_CC4OF   ((uint16_t)0x1000)
 
#define TIM_EGR_UG   ((uint8_t)0x01)
 
#define TIM_EGR_CC1G   ((uint8_t)0x02)
 
#define TIM_EGR_CC2G   ((uint8_t)0x04)
 
#define TIM_EGR_CC3G   ((uint8_t)0x08)
 
#define TIM_EGR_CC4G   ((uint8_t)0x10)
 
#define TIM_EGR_COMG   ((uint8_t)0x20)
 
#define TIM_EGR_TG   ((uint8_t)0x40)
 
#define TIM_EGR_BG   ((uint8_t)0x80)
 
#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)
 
#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
 
#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
 
#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)
 
#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
 
#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)
 
#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
 
#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
 
#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)
 
#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
 
#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
 
#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)
 
#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
 
#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)
 
#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
 
#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
 
#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)
 
#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
 
#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)
 
#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
 
#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
 
#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)
 
#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
 
#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
 
#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)
 
#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
 
#define TIM_CCER_CC1E   ((uint16_t)0x0001)
 
#define TIM_CCER_CC1P   ((uint16_t)0x0002)
 
#define TIM_CCER_CC1NE   ((uint16_t)0x0004)
 
#define TIM_CCER_CC1NP   ((uint16_t)0x0008)
 
#define TIM_CCER_CC2E   ((uint16_t)0x0010)
 
#define TIM_CCER_CC2P   ((uint16_t)0x0020)
 
#define TIM_CCER_CC2NE   ((uint16_t)0x0040)
 
#define TIM_CCER_CC2NP   ((uint16_t)0x0080)
 
#define TIM_CCER_CC3E   ((uint16_t)0x0100)
 
#define TIM_CCER_CC3P   ((uint16_t)0x0200)
 
#define TIM_CCER_CC3NE   ((uint16_t)0x0400)
 
#define TIM_CCER_CC3NP   ((uint16_t)0x0800)
 
#define TIM_CCER_CC4E   ((uint16_t)0x1000)
 
#define TIM_CCER_CC4P   ((uint16_t)0x2000)
 
#define TIM_CCER_CC4NP   ((uint16_t)0x8000)
 
#define TIM_CNT_CNT   ((uint16_t)0xFFFF)
 
#define TIM_PSC_PSC   ((uint16_t)0xFFFF)
 
#define TIM_ARR_ARR   ((uint16_t)0xFFFF)
 
#define TIM_RCR_REP   ((uint8_t)0xFF)
 
#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
 
#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
 
#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
 
#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
 
#define TIM_BDTR_DTG   ((uint16_t)0x00FF)
 
#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)
 
#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)
 
#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)
 
#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)
 
#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)
 
#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)
 
#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)
 
#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)
 
#define TIM_BDTR_LOCK   ((uint16_t)0x0300)
 
#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
 
#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
 
#define TIM_BDTR_OSSI   ((uint16_t)0x0400)
 
#define TIM_BDTR_OSSR   ((uint16_t)0x0800)
 
#define TIM_BDTR_BKE   ((uint16_t)0x1000)
 
#define TIM_BDTR_BKP   ((uint16_t)0x2000)
 
#define TIM_BDTR_AOE   ((uint16_t)0x4000)
 
#define TIM_BDTR_MOE   ((uint16_t)0x8000)
 
#define TIM_DCR_DBA   ((uint16_t)0x001F)
 
#define TIM_DCR_DBA_0   ((uint16_t)0x0001)
 
#define TIM_DCR_DBA_1   ((uint16_t)0x0002)
 
#define TIM_DCR_DBA_2   ((uint16_t)0x0004)
 
#define TIM_DCR_DBA_3   ((uint16_t)0x0008)
 
#define TIM_DCR_DBA_4   ((uint16_t)0x0010)
 
#define TIM_DCR_DBL   ((uint16_t)0x1F00)
 
#define TIM_DCR_DBL_0   ((uint16_t)0x0100)
 
#define TIM_DCR_DBL_1   ((uint16_t)0x0200)
 
#define TIM_DCR_DBL_2   ((uint16_t)0x0400)
 
#define TIM_DCR_DBL_3   ((uint16_t)0x0800)
 
#define TIM_DCR_DBL_4   ((uint16_t)0x1000)
 
#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
 
#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
 
#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
 
#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
 
#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
 
#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
 
#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
 
#define USART_SR_PE   ((uint16_t)0x0001)
 
#define USART_SR_FE   ((uint16_t)0x0002)
 
#define USART_SR_NE   ((uint16_t)0x0004)
 
#define USART_SR_ORE   ((uint16_t)0x0008)
 
#define USART_SR_IDLE   ((uint16_t)0x0010)
 
#define USART_SR_RXNE   ((uint16_t)0x0020)
 
#define USART_SR_TC   ((uint16_t)0x0040)
 
#define USART_SR_TXE   ((uint16_t)0x0080)
 
#define USART_SR_LBD   ((uint16_t)0x0100)
 
#define USART_SR_CTS   ((uint16_t)0x0200)
 
#define USART_DR_DR   ((uint16_t)0x01FF)
 
#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
 
#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
 
#define USART_CR1_SBK   ((uint16_t)0x0001)
 
#define USART_CR1_RWU   ((uint16_t)0x0002)
 
#define USART_CR1_RE   ((uint16_t)0x0004)
 
#define USART_CR1_TE   ((uint16_t)0x0008)
 
#define USART_CR1_IDLEIE   ((uint16_t)0x0010)
 
#define USART_CR1_RXNEIE   ((uint16_t)0x0020)
 
#define USART_CR1_TCIE   ((uint16_t)0x0040)
 
#define USART_CR1_TXEIE   ((uint16_t)0x0080)
 
#define USART_CR1_PEIE   ((uint16_t)0x0100)
 
#define USART_CR1_PS   ((uint16_t)0x0200)
 
#define USART_CR1_PCE   ((uint16_t)0x0400)
 
#define USART_CR1_WAKE   ((uint16_t)0x0800)
 
#define USART_CR1_M   ((uint16_t)0x1000)
 
#define USART_CR1_UE   ((uint16_t)0x2000)
 
#define USART_CR1_OVER8   ((uint16_t)0x8000)
 
#define USART_CR2_ADD   ((uint16_t)0x000F)
 
#define USART_CR2_LBDL   ((uint16_t)0x0020)
 
#define USART_CR2_LBDIE   ((uint16_t)0x0040)
 
#define USART_CR2_LBCL   ((uint16_t)0x0100)
 
#define USART_CR2_CPHA   ((uint16_t)0x0200)
 
#define USART_CR2_CPOL   ((uint16_t)0x0400)
 
#define USART_CR2_CLKEN   ((uint16_t)0x0800)
 
#define USART_CR2_STOP   ((uint16_t)0x3000)
 
#define USART_CR2_STOP_0   ((uint16_t)0x1000)
 
#define USART_CR2_STOP_1   ((uint16_t)0x2000)
 
#define USART_CR2_LINEN   ((uint16_t)0x4000)
 
#define USART_CR3_EIE   ((uint16_t)0x0001)
 
#define USART_CR3_IREN   ((uint16_t)0x0002)
 
#define USART_CR3_IRLP   ((uint16_t)0x0004)
 
#define USART_CR3_HDSEL   ((uint16_t)0x0008)
 
#define USART_CR3_NACK   ((uint16_t)0x0010)
 
#define USART_CR3_SCEN   ((uint16_t)0x0020)
 
#define USART_CR3_DMAR   ((uint16_t)0x0040)
 
#define USART_CR3_DMAT   ((uint16_t)0x0080)
 
#define USART_CR3_RTSE   ((uint16_t)0x0100)
 
#define USART_CR3_CTSE   ((uint16_t)0x0200)
 
#define USART_CR3_CTSIE   ((uint16_t)0x0400)
 
#define USART_CR3_ONEBIT   ((uint16_t)0x0800)
 
#define USART_GTPR_PSC   ((uint16_t)0x00FF)
 
#define USART_GTPR_PSC_0   ((uint16_t)0x0001)
 
#define USART_GTPR_PSC_1   ((uint16_t)0x0002)
 
#define USART_GTPR_PSC_2   ((uint16_t)0x0004)
 
#define USART_GTPR_PSC_3   ((uint16_t)0x0008)
 
#define USART_GTPR_PSC_4   ((uint16_t)0x0010)
 
#define USART_GTPR_PSC_5   ((uint16_t)0x0020)
 
#define USART_GTPR_PSC_6   ((uint16_t)0x0040)
 
#define USART_GTPR_PSC_7   ((uint16_t)0x0080)
 
#define USART_GTPR_GT   ((uint16_t)0xFF00)
 
#define WWDG_CR_T   ((uint8_t)0x7F)
 
#define WWDG_CR_T0   ((uint8_t)0x01)
 
#define WWDG_CR_T1   ((uint8_t)0x02)
 
#define WWDG_CR_T2   ((uint8_t)0x04)
 
#define WWDG_CR_T3   ((uint8_t)0x08)
 
#define WWDG_CR_T4   ((uint8_t)0x10)
 
#define WWDG_CR_T5   ((uint8_t)0x20)
 
#define WWDG_CR_T6   ((uint8_t)0x40)
 
#define WWDG_CR_WDGA   ((uint8_t)0x80)
 
#define WWDG_CFR_W   ((uint16_t)0x007F)
 
#define WWDG_CFR_W0   ((uint16_t)0x0001)
 
#define WWDG_CFR_W1   ((uint16_t)0x0002)
 
#define WWDG_CFR_W2   ((uint16_t)0x0004)
 
#define WWDG_CFR_W3   ((uint16_t)0x0008)
 
#define WWDG_CFR_W4   ((uint16_t)0x0010)
 
#define WWDG_CFR_W5   ((uint16_t)0x0020)
 
#define WWDG_CFR_W6   ((uint16_t)0x0040)
 
#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)
 
#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
 
#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
 
#define WWDG_CFR_EWI   ((uint16_t)0x0200)
 
#define WWDG_SR_EWIF   ((uint8_t)0x01)
 
+#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
 
+#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
 
+#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
 
+#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
 
+#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
 
+#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
 
#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
 
#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
 
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
 
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
 
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)
 
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)
 
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)
 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
 
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)
 
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)
 
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)
 
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)
 
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)
 
+#define ETH_MACCR_WD   ((uint32_t)0x00800000) /* Watchdog disable */
 
+#define ETH_MACCR_JD   ((uint32_t)0x00400000) /* Jabber disable */
 
+#define ETH_MACCR_IFG   ((uint32_t)0x000E0000) /* Inter-frame gap */
 
+#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
 
+#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
 
+#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
 
+#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
 
+#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
 
+#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
 
+#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
 
+#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
 
+#define ETH_MACCR_CSD   ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
 
+#define ETH_MACCR_FES   ((uint32_t)0x00004000) /* Fast ethernet speed */
 
+#define ETH_MACCR_ROD   ((uint32_t)0x00002000) /* Receive own disable */
 
+#define ETH_MACCR_LM   ((uint32_t)0x00001000) /* loopback mode */
 
+#define ETH_MACCR_DM   ((uint32_t)0x00000800) /* Duplex mode */
 
+#define ETH_MACCR_IPCO   ((uint32_t)0x00000400) /* IP Checksum offload */
 
+#define ETH_MACCR_RD   ((uint32_t)0x00000200) /* Retry disable */
 
+#define ETH_MACCR_APCS   ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
 
#define ETH_MACCR_BL
 
+#define ETH_MACCR_BL_10   ((uint32_t)0x00000000) /* k = min (n, 10) */
 
+#define ETH_MACCR_BL_8   ((uint32_t)0x00000020) /* k = min (n, 8) */
 
+#define ETH_MACCR_BL_4   ((uint32_t)0x00000040) /* k = min (n, 4) */
 
+#define ETH_MACCR_BL_1   ((uint32_t)0x00000060) /* k = min (n, 1) */
 
+#define ETH_MACCR_DC   ((uint32_t)0x00000010) /* Defferal check */
 
+#define ETH_MACCR_TE   ((uint32_t)0x00000008) /* Transmitter enable */
 
+#define ETH_MACCR_RE   ((uint32_t)0x00000004) /* Receiver enable */
 
+#define ETH_MACFFR_RA   ((uint32_t)0x80000000) /* Receive all */
 
+#define ETH_MACFFR_HPF   ((uint32_t)0x00000400) /* Hash or perfect filter */
 
+#define ETH_MACFFR_SAF   ((uint32_t)0x00000200) /* Source address filter enable */
 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100) /* SA inverse filtering */
 
+#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
 
+#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
 
+#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
 
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
 
+#define ETH_MACFFR_BFD   ((uint32_t)0x00000020) /* Broadcast frame disable */
 
+#define ETH_MACFFR_PAM   ((uint32_t)0x00000010) /* Pass all mutlicast */
 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008) /* DA Inverse filtering */
 
+#define ETH_MACFFR_HM   ((uint32_t)0x00000004) /* Hash multicast */
 
+#define ETH_MACFFR_HU   ((uint32_t)0x00000002) /* Hash unicast */
 
+#define ETH_MACFFR_PM   ((uint32_t)0x00000001) /* Promiscuous mode */
 
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF) /* Hash table high */
 
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF) /* Hash table low */
 
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800) /* Physical layer address */
 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0) /* MII register in the selected PHY */
 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
 
+#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 
+#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 
+#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 
+#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 
+#define ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
 
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002) /* MII write */
 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001) /* MII busy */
 
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
 
+#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000) /* Pause time */
 
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080) /* Zero-quanta pause disable */
 
+#define ETH_MACFCR_PLT   ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
 
+#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
 
+#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
 
+#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
 
+#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
 
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008) /* Unicast pause frame detect */
 
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004) /* Receive flow control enable */
 
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002) /* Transmit flow control enable */
 
+#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
 
+#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
 
+#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
 
+#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
 
+#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200) /* Global Unicast */
 
+#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040) /* Wake-Up Frame Received */
 
+#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020) /* Magic Packet Received */
 
+#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
 
+#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002) /* Magic Packet Enable */
 
+#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001) /* Power Down */
 
+#define ETH_MACSR_TSTS   ((uint32_t)0x00000200) /* Time stamp trigger status */
 
+#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040) /* MMC transmit status */
 
+#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020) /* MMC receive status */
 
+#define ETH_MACSR_MMCS   ((uint32_t)0x00000010) /* MMC status */
 
+#define ETH_MACSR_PMTS   ((uint32_t)0x00000008) /* PMT status */
 
+#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
 
+#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008) /* PMT interrupt mask */
 
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF) /* MAC address0 high */
 
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
 
+#define ETH_MACA1HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA1HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
 
+#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
 
+#define ETH_MACA2HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA2HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
+#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
 
+#define ETH_MACA3HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA3HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
+#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF) /* MAC address3 high */
 
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
 
+#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
 
+#define ETH_MMCCR_MCP   ((uint32_t)0x00000010) /* MMC counter preset */
 
+#define ETH_MMCCR_MCF   ((uint32_t)0x00000008) /* MMC Counter Freeze */
 
+#define ETH_MMCCR_ROR   ((uint32_t)0x00000004) /* Reset on Read */
 
+#define ETH_MMCCR_CSR   ((uint32_t)0x00000002) /* Counter Stop Rollover */
 
+#define ETH_MMCCR_CR   ((uint32_t)0x00000001) /* Counters Reset */
 
+#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
 
+#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
 
+#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
+#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
+#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
 
+#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
 
+#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
 
+#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
 
+#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000) /* Time stamp clock node type */
 
+#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
 
+#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
 
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
 
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
 
+#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
 
+#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
 
+#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
 
+#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
 
+#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020) /* Addend register update */
 
+#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
 
+#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008) /* Time stamp update */
 
+#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004) /* Time stamp initialize */
 
+#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
 
+#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001) /* Time stamp enable */
 
+#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF) /* System time Sub-second increment value */
 
+#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF) /* System Time second */
 
+#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000) /* System Time Positive or negative time */
 
+#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
 
+#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
 
+#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
 
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
 
+#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
 
+#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
 
+#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
 
+#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020) /* Time stamp target time reached */
 
+#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010) /* Time stamp seconds overflow */
 
+#define ETH_DMABMR_AAB   ((uint32_t)0x02000000) /* Address-Aligned beats */
 
+#define ETH_DMABMR_FPM   ((uint32_t)0x01000000) /* 4xPBL mode */
 
+#define ETH_DMABMR_USP   ((uint32_t)0x00800000) /* Use separate PBL */
 
+#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000) /* RxDMA PBL */
 
+#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
 
+#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
 
+#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
+#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
+#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
 
+#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
 
+#define ETH_DMABMR_FB   ((uint32_t)0x00010000) /* Fixed Burst */
 
+#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00) /* Programmable burst length */
 
+#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
 
+#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
 
+#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
+#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
+#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
 
+#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 
+#define ETH_DMABMR_EDE   ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
 
+#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C) /* Descriptor Skip Length */
 
+#define ETH_DMABMR_DA   ((uint32_t)0x00000002) /* DMA arbitration scheme */
 
+#define ETH_DMABMR_SR   ((uint32_t)0x00000001) /* Software reset */
 
+#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
 
+#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
 
+#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF) /* Start of receive list */
 
+#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
 
+#define ETH_DMASR_TSTS   ((uint32_t)0x20000000) /* Time-stamp trigger status */
 
+#define ETH_DMASR_PMTS   ((uint32_t)0x10000000) /* PMT status */
 
+#define ETH_DMASR_MMCS   ((uint32_t)0x08000000) /* MMC status */
 
+#define ETH_DMASR_EBS   ((uint32_t)0x03800000) /* Error bits status */
 
+#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
 
+#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
 
+#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
 
+#define ETH_DMASR_TPS   ((uint32_t)0x00700000) /* Transmit process state */
 
+#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
 
+#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
 
+#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000) /* Running - waiting for status */
 
+#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000) /* Running - reading the data from host memory */
 
+#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
 
+#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
 
+#define ETH_DMASR_RPS   ((uint32_t)0x000E0000) /* Receive process state */
 
+#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
 
+#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
 
+#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000) /* Running - waiting for packet */
 
+#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
 
+#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000) /* Running - closing descriptor */
 
+#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
 
+#define ETH_DMASR_NIS   ((uint32_t)0x00010000) /* Normal interrupt summary */
 
+#define ETH_DMASR_AIS   ((uint32_t)0x00008000) /* Abnormal interrupt summary */
 
+#define ETH_DMASR_ERS   ((uint32_t)0x00004000) /* Early receive status */
 
+#define ETH_DMASR_FBES   ((uint32_t)0x00002000) /* Fatal bus error status */
 
+#define ETH_DMASR_ETS   ((uint32_t)0x00000400) /* Early transmit status */
 
+#define ETH_DMASR_RWTS   ((uint32_t)0x00000200) /* Receive watchdog timeout status */
 
+#define ETH_DMASR_RPSS   ((uint32_t)0x00000100) /* Receive process stopped status */
 
+#define ETH_DMASR_RBUS   ((uint32_t)0x00000080) /* Receive buffer unavailable status */
 
+#define ETH_DMASR_RS   ((uint32_t)0x00000040) /* Receive status */
 
+#define ETH_DMASR_TUS   ((uint32_t)0x00000020) /* Transmit underflow status */
 
+#define ETH_DMASR_ROS   ((uint32_t)0x00000010) /* Receive overflow status */
 
+#define ETH_DMASR_TJTS   ((uint32_t)0x00000008) /* Transmit jabber timeout status */
 
+#define ETH_DMASR_TBUS   ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
 
+#define ETH_DMASR_TPSS   ((uint32_t)0x00000002) /* Transmit process stopped status */
 
+#define ETH_DMASR_TS   ((uint32_t)0x00000001) /* Transmit status */
 
+#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
 
+#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000) /* Receive store and forward */
 
+#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000) /* Disable flushing of received frames */
 
+#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000) /* Transmit store and forward */
 
+#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000) /* Flush transmit FIFO */
 
+#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000) /* Transmit threshold control */
 
+#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
 
+#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
 
+#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
 
+#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
 
+#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
 
+#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
 
+#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
 
+#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
 
+#define ETH_DMAOMR_ST   ((uint32_t)0x00002000) /* Start/stop transmission command */
 
+#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080) /* Forward error frames */
 
+#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040) /* Forward undersized good frames */
 
+#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018) /* receive threshold control */
 
+#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
 
+#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
 
+#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
 
+#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
 
+#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004) /* operate on second frame */
 
+#define ETH_DMAOMR_SR   ((uint32_t)0x00000002) /* Start/stop receive */
 
+#define ETH_DMAIER_NISE   ((uint32_t)0x00010000) /* Normal interrupt summary enable */
 
+#define ETH_DMAIER_AISE   ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
 
+#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000) /* Early receive interrupt enable */
 
+#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
 
+#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400) /* Early transmit interrupt enable */
 
+#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
 
+#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
 
+#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
 
+#define ETH_DMAIER_RIE   ((uint32_t)0x00000040) /* Receive interrupt enable */
 
+#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
 
+#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
 
+#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
 
+#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
 
+#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
 
+#define ETH_DMAIER_TIE   ((uint32_t)0x00000001) /* Transmit interrupt enable */
 
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
 
+#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
 
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
 
+#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
 
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
 
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
 
+#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
 
+#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
+
+

ADCPRE[1:0] bits (ADC prescaler)

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DDS   ((uint32_t)0x00002000)
+
+

DMA disable selection (Multi-ADC mode)

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)
+
+

DELAY[3:0] bits (Delay between 2 sampling phases)

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DMA   ((uint32_t)0x0000C000)
+
+

DMA[1:0] bits (Direct Memory Access mode for multimode)

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)
+
+

MULTI[4:0] bits (Multi-ADC mode selection)

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
+
+

Temperature Sensor and VREFINT Enable

+ +
+
+ +
+
+ + + + +
#define ADC_CCR_VBATE   ((uint32_t)0x00400000)
+
+

VBAT Enable

+ +
+
+ +
+
+ + + + +
#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
+
+

1st data of a pair of regular conversions

+ +
+
+ +
+
+ + + + +
#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
+
+

2nd data of a pair of regular conversions

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
+
+

AWDCH[4:0] bits (Analog watchdog channel select bits)

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)
+
+

Analog watchdog enable on regular channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)
+
+

AAnalog Watchdog interrupt enable

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
+
+

Enable the watchdog on a single channel in scan mode

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)
+
+

Discontinuous mode on regular channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
+
+

DISCNUM[2:0] bits (Discontinuous mode channel count)

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)
+
+

Interrupt enable for EOC

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)
+
+

Automatic injected group conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
+
+

Analog watchdog enable on injected channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
+
+

Discontinuous mode on injected channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
+
+

Interrupt enable for injected channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)
+
+

overrun interrupt enable

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_RES   ((uint32_t)0x03000000)
+
+

RES[2:0] bits (Resolution)

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_RES_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_RES_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR1_SCAN   ((uint32_t)0x00000100)
+
+

Scan mode

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_ADON   ((uint32_t)0x00000001)
+
+

A/D Converter ON / OFF

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)
+
+

Data Alignment

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_CONT   ((uint32_t)0x00000002)
+
+

Continuous Conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_DDS   ((uint32_t)0x00000200)
+
+

DMA disable selection (Single ADC)

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_DMA   ((uint32_t)0x00000100)
+
+

Direct Memory access mode

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EOCS   ((uint32_t)0x00000400)
+
+

End of conversion selection

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)
+
+

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
+
+

EXTSEL[3:0] bits (External Event Select for regular group)

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
+
+

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
+
+

JEXTSEL[3:0] bits (External event select for injected group)

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
+
+

Start Conversion of injected channels

+ +
+
+ +
+
+ + + + +
#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)
+
+

Start Conversion of regular channels

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_AWD1   ((uint32_t)0x00000001)
+
+

ADC1 Analog watchdog flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_AWD2   ((uint32_t)0x00000100)
+
+

ADC2 Analog watchdog flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_AWD3   ((uint32_t)0x00010000)
+
+

ADC3 Analog watchdog flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)
+
+

ADC1 DMA overrun flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)
+
+

ADC2 DMA overrun flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)
+
+

ADC3 DMA overrun flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_EOC1   ((uint32_t)0x00000002)
+
+

ADC1 End of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_EOC2   ((uint32_t)0x00000200)
+
+

ADC2 End of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_EOC3   ((uint32_t)0x00020000)
+
+

ADC3 End of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)
+
+

ADC1 Injected channel end of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)
+
+

ADC2 Injected channel end of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)
+
+

ADC3 Injected channel end of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
+
+

ADC1 Injected channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
+
+

ADC2 Injected channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
+
+

ADC3 Injected channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_STRT1   ((uint32_t)0x00000010)
+
+

ADC1 Regular channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_STRT2   ((uint32_t)0x00001000)
+
+

ADC2 Regular channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_CSR_STRT3   ((uint32_t)0x00100000)
+
+

ADC3 Regular channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
+
+

ADC2 data

+ +
+
+ +
+
+ + + + +
#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)
+
+

Regular data

+ +
+
+ +
+
+ + + + +
#define ADC_HTR_HT   ((uint16_t)0x0FFF)
+
+

Analog watchdog high threshold

+ +
+
+ +
+
+ + + + +
#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
+
+

Injected data

+ +
+
+ +
+
+ + + + +
#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
+
+

Injected data

+ +
+
+ +
+
+ + + + +
#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
+
+

Injected data

+ +
+
+ +
+
+ + + + +
#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
+
+

Injected data

+ +
+
+ +
+
+ + + + +
#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
+
+

Data offset for injected channel 1

+ +
+
+ +
+
+ + + + +
#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
+
+

Data offset for injected channel 2

+ +
+
+ +
+
+ + + + +
#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
+
+

Data offset for injected channel 3

+ +
+
+ +
+
+ + + + +
#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
+
+

Data offset for injected channel 4

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JL   ((uint32_t)0x00300000)
+
+

JL[1:0] bits (Injected Sequence length)

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
+
+

JSQ1[4:0] bits (1st conversion in injected sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
+
+

JSQ2[4:0] bits (2nd conversion in injected sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
+
+

JSQ3[4:0] bits (3rd conversion in injected sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
+
+

JSQ4[4:0] bits (4th conversion in injected sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_LTR_LT   ((uint16_t)0x0FFF)
+
+

Analog watchdog low threshold

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
+
+

SMP10[2:0] bits (Channel 10 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
+
+

SMP11[2:0] bits (Channel 11 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
+
+

SMP12[2:0] bits (Channel 12 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
+
+

SMP13[2:0] bits (Channel 13 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
+
+

SMP14[2:0] bits (Channel 14 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
+
+

SMP15[2:0] bits (Channel 15 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
+
+

SMP16[2:0] bits (Channel 16 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
+
+

SMP17[2:0] bits (Channel 17 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
+
+

SMP18[2:0] bits (Channel 18 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
+
+

SMP0[2:0] bits (Channel 0 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
+
+

SMP1[2:0] bits (Channel 1 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
+
+

SMP2[2:0] bits (Channel 2 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
+
+

SMP3[2:0] bits (Channel 3 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
+
+

SMP4[2:0] bits (Channel 4 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
+
+

SMP5[2:0] bits (Channel 5 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
+
+

SMP6[2:0] bits (Channel 6 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
+
+

SMP7[2:0] bits (Channel 7 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
+
+

SMP8[2:0] bits (Channel 8 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
+
+

SMP9[2:0] bits (Channel 9 Sample time selection)

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_L   ((uint32_t)0x00F00000)
+
+

L[3:0] bits (Regular channel sequence length)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_L_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_L_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_L_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_L_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
+
+

SQ13[4:0] bits (13th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
+
+

SQ14[4:0] bits (14th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
+
+

SQ15[4:0] bits (15th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
+
+

SQ16[4:0] bits (16th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
+
+

SQ10[4:0] bits (10th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
+
+

SQ11[4:0] bits (11th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
+
+

SQ12[4:0] bits (12th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
+
+

SQ7[4:0] bits (7th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
+
+

SQ8[4:0] bits (8th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
+
+

SQ9[4:0] bits (9th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
+
+

SQ1[4:0] bits (1st conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
+
+

SQ2[4:0] bits (2nd conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
+
+

SQ3[4:0] bits (3rd conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
+
+

SQ4[4:0] bits (4th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
+
+

SQ5[4:0] bits (5th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
+
+

SQ6[4:0] bits (6th conversion in regular sequence)

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define ADC_SR_AWD   ((uint8_t)0x01)
+
+

Analog watchdog flag

+ +
+
+ +
+
+ + + + +
#define ADC_SR_EOC   ((uint8_t)0x02)
+
+

End of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_SR_JEOC   ((uint8_t)0x04)
+
+

Injected channel end of conversion

+ +
+
+ +
+
+ + + + +
#define ADC_SR_JSTRT   ((uint8_t)0x08)
+
+

Injected channel Start flag

+ +
+
+ +
+
+ + + + +
#define ADC_SR_OVR   ((uint8_t)0x20)
+
+

Overrun flag

+ +
+
+ +
+
+ + + + +
#define ADC_SR_STRT   ((uint8_t)0x10)
+
+

Regular channel Start flag

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_BRP   ((uint32_t)0x000003FF)
+
+

Baud Rate Prescaler

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_LBKM   ((uint32_t)0x40000000)
+
+

Loop Back Mode (Debug)

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_SILM   ((uint32_t)0x80000000)
+
+

Silent Mode Mailbox registers

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_SJW   ((uint32_t)0x03000000)
+
+

Resynchronization Jump Width

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_TS1   ((uint32_t)0x000F0000)
+
+

Time Segment 1

+ +
+
+ +
+
+ + + + +
#define CAN_BTR_TS2   ((uint32_t)0x00700000)
+
+

Time Segment 2

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_BOFF   ((uint32_t)0x00000004)
+
+

Bus-Off Flag

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_EPVF   ((uint32_t)0x00000002)
+
+

Error Passive Flag

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_EWGF   ((uint32_t)0x00000001)
+
+

Error Warning Flag

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_LEC   ((uint32_t)0x00000070)
+
+

LEC[2:0] bits (Last Error Code)

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_REC   ((uint32_t)0xFF000000)
+
+

Receive Error Counter

+ +
+
+ +
+
+ + + + +
#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)
+
+

Least significant byte of the 9-bit Transmit Error Counter

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F0R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F0R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F10R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F10R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F11R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F11R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F12R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F12R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F13R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F13R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F1R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F1R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F2R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F2R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F3R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F3R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F4R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F4R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F5R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F5R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F6R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F6R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F7R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F7R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F8R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F8R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F9R1_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB0   ((uint32_t)0x00000001)
+
+

Filter bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB1   ((uint32_t)0x00000002)
+
+

Filter bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB10   ((uint32_t)0x00000400)
+
+

Filter bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB11   ((uint32_t)0x00000800)
+
+

Filter bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB12   ((uint32_t)0x00001000)
+
+

Filter bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB13   ((uint32_t)0x00002000)
+
+

Filter bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB14   ((uint32_t)0x00004000)
+
+

Filter bit 14

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB15   ((uint32_t)0x00008000)
+
+

Filter bit 15

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB16   ((uint32_t)0x00010000)
+
+

Filter bit 16

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB17   ((uint32_t)0x00020000)
+
+

Filter bit 17

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB18   ((uint32_t)0x00040000)
+
+

Filter bit 18

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB19   ((uint32_t)0x00080000)
+
+

Filter bit 19

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB2   ((uint32_t)0x00000004)
+
+

Filter bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB20   ((uint32_t)0x00100000)
+
+

Filter bit 20

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB21   ((uint32_t)0x00200000)
+
+

Filter bit 21

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB22   ((uint32_t)0x00400000)
+
+

Filter bit 22

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB23   ((uint32_t)0x00800000)
+
+

Filter bit 23

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB24   ((uint32_t)0x01000000)
+
+

Filter bit 24

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB25   ((uint32_t)0x02000000)
+
+

Filter bit 25

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB26   ((uint32_t)0x04000000)
+
+

Filter bit 26

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB27   ((uint32_t)0x08000000)
+
+

Filter bit 27

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB28   ((uint32_t)0x10000000)
+
+

Filter bit 28

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB29   ((uint32_t)0x20000000)
+
+

Filter bit 29

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB3   ((uint32_t)0x00000008)
+
+

Filter bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB30   ((uint32_t)0x40000000)
+
+

Filter bit 30

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB31   ((uint32_t)0x80000000)
+
+

Filter bit 31

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB4   ((uint32_t)0x00000010)
+
+

Filter bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB5   ((uint32_t)0x00000020)
+
+

Filter bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB6   ((uint32_t)0x00000040)
+
+

Filter bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB7   ((uint32_t)0x00000080)
+
+

Filter bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB8   ((uint32_t)0x00000100)
+
+

Filter bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_F9R2_FB9   ((uint32_t)0x00000200)
+
+

Filter bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)
+
+

Filter Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT0   ((uint16_t)0x0001)
+
+

Filter 0 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT1   ((uint16_t)0x0002)
+
+

Filter 1 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT10   ((uint16_t)0x0400)
+
+

Filter 10 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT11   ((uint16_t)0x0800)
+
+

Filter 11 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT12   ((uint16_t)0x1000)
+
+

Filter 12 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT13   ((uint16_t)0x2000)
+
+

Filter 13 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT2   ((uint16_t)0x0004)
+
+

Filter 2 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT3   ((uint16_t)0x0008)
+
+

Filter 3 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT4   ((uint16_t)0x0010)
+
+

Filter 4 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT5   ((uint16_t)0x0020)
+
+

Filter 5 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT6   ((uint16_t)0x0040)
+
+

Filter 6 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT7   ((uint16_t)0x0080)
+
+

Filter 7 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT8   ((uint16_t)0x0100)
+
+

Filter 8 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FA1R_FACT9   ((uint16_t)0x0200)
+
+

Filter 9 Active

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
+
+

Filter FIFO Assignment

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)
+
+

Filter FIFO Assignment for Filter 0

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)
+
+

Filter FIFO Assignment for Filter 1

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)
+
+

Filter FIFO Assignment for Filter 10

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)
+
+

Filter FIFO Assignment for Filter 11

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)
+
+

Filter FIFO Assignment for Filter 12

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)
+
+

Filter FIFO Assignment for Filter 13

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)
+
+

Filter FIFO Assignment for Filter 2

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)
+
+

Filter FIFO Assignment for Filter 3

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)
+
+

Filter FIFO Assignment for Filter 4

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)
+
+

Filter FIFO Assignment for Filter 5

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)
+
+

Filter FIFO Assignment for Filter 6

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)
+
+

Filter FIFO Assignment for Filter 7

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)
+
+

Filter FIFO Assignment for Filter 8

+ +
+
+ +
+
+ + + + +
#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)
+
+

Filter FIFO Assignment for Filter 9

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)
+
+

Filter Mode

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM0   ((uint16_t)0x0001)
+
+

Filter Init Mode bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM1   ((uint16_t)0x0002)
+
+

Filter Init Mode bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM10   ((uint16_t)0x0400)
+
+

Filter Init Mode bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM11   ((uint16_t)0x0800)
+
+

Filter Init Mode bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM12   ((uint16_t)0x1000)
+
+

Filter Init Mode bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM13   ((uint16_t)0x2000)
+
+

Filter Init Mode bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM2   ((uint16_t)0x0004)
+
+

Filter Init Mode bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM3   ((uint16_t)0x0008)
+
+

Filter Init Mode bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM4   ((uint16_t)0x0010)
+
+

Filter Init Mode bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM5   ((uint16_t)0x0020)
+
+

Filter Init Mode bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM6   ((uint16_t)0x0040)
+
+

Filter Init Mode bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM7   ((uint16_t)0x0080)
+
+

Filter Init Mode bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM8   ((uint16_t)0x0100)
+
+

Filter Init Mode bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_FM1R_FBM9   ((uint16_t)0x0200)
+
+

Filter Init Mode bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_FMR_FINIT   ((uint8_t)0x01)
+
+

Filter Init Mode

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)
+
+

Filter Scale Configuration

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC0   ((uint16_t)0x0001)
+
+

Filter Scale Configuration bit 0

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC1   ((uint16_t)0x0002)
+
+

Filter Scale Configuration bit 1

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC10   ((uint16_t)0x0400)
+
+

Filter Scale Configuration bit 10

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC11   ((uint16_t)0x0800)
+
+

Filter Scale Configuration bit 11

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC12   ((uint16_t)0x1000)
+
+

Filter Scale Configuration bit 12

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC13   ((uint16_t)0x2000)
+
+

Filter Scale Configuration bit 13

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC2   ((uint16_t)0x0004)
+
+

Filter Scale Configuration bit 2

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC3   ((uint16_t)0x0008)
+
+

Filter Scale Configuration bit 3

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC4   ((uint16_t)0x0010)
+
+

Filter Scale Configuration bit 4

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC5   ((uint16_t)0x0020)
+
+

Filter Scale Configuration bit 5

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC6   ((uint16_t)0x0040)
+
+

Filter Scale Configuration bit 6

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC7   ((uint16_t)0x0080)
+
+

Filter Scale Configuration bit 7

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC8   ((uint16_t)0x0100)
+
+

Filter Scale Configuration bit 8

+ +
+
+ +
+
+ + + + +
#define CAN_FS1R_FSC9   ((uint16_t)0x0200)
+
+

Filter Scale Configuration bit 9

+ +
+
+ +
+
+ + + + +
#define CAN_IER_BOFIE   ((uint32_t)0x00000400)
+
+

Bus-Off Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_EPVIE   ((uint32_t)0x00000200)
+
+

Error Passive Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_ERRIE   ((uint32_t)0x00008000)
+
+

Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_EWGIE   ((uint32_t)0x00000100)
+
+

Error Warning Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FFIE0   ((uint32_t)0x00000004)
+
+

FIFO Full Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FFIE1   ((uint32_t)0x00000020)
+
+

FIFO Full Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)
+
+

FIFO Message Pending Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)
+
+

FIFO Message Pending Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)
+
+

FIFO Overrun Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)
+
+

FIFO Overrun Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_LECIE   ((uint32_t)0x00000800)
+
+

Last Error Code Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_SLKIE   ((uint32_t)0x00020000)
+
+

Sleep Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_TMEIE   ((uint32_t)0x00000001)
+
+

Transmit Mailbox Empty Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_IER_WKUIE   ((uint32_t)0x00010000)
+
+

Wakeup Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_ABOM   ((uint16_t)0x0040)
+
+

Automatic Bus-Off Management

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_AWUM   ((uint16_t)0x0020)
+
+

Automatic Wakeup Mode

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_INRQ   ((uint16_t)0x0001)
+
+

<CAN control and status registers Initialization Request

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_NART   ((uint16_t)0x0010)
+
+

No Automatic Retransmission

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_RESET   ((uint16_t)0x8000)
+
+

bxCAN software master reset

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_RFLM   ((uint16_t)0x0008)
+
+

Receive FIFO Locked Mode

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_SLEEP   ((uint16_t)0x0002)
+
+

Sleep Mode Request

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_TTCM   ((uint16_t)0x0080)
+
+

Time Triggered Communication Mode

+ +
+
+ +
+
+ + + + +
#define CAN_MCR_TXFP   ((uint16_t)0x0004)
+
+

Transmit FIFO Priority

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_ERRI   ((uint16_t)0x0004)
+
+

Error Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_INAK   ((uint16_t)0x0001)
+
+

Initialization Acknowledge

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_RX   ((uint16_t)0x0800)
+
+

CAN Rx Signal

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_RXM   ((uint16_t)0x0200)
+
+

Receive Mode

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_SAMP   ((uint16_t)0x0400)
+
+

Last Sample Point

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_SLAK   ((uint16_t)0x0002)
+
+

Sleep Acknowledge

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_SLAKI   ((uint16_t)0x0010)
+
+

Sleep Acknowledge Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_TXM   ((uint16_t)0x0100)
+
+

Transmit Mode

+ +
+
+ +
+
+ + + + +
#define CAN_MSR_WKUI   ((uint16_t)0x0008)
+
+

Wakeup Interrupt

+ +
+
+ +
+
+ + + + +
#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
+
+

Data byte 4

+ +
+
+ +
+
+ + + + +
#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
+
+

Data byte 5

+ +
+
+ +
+
+ + + + +
#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
+
+

Data byte 6

+ +
+
+ +
+
+ + + + +
#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
+
+

Data byte 7

+ +
+
+ +
+
+ + + + +
#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
+
+

Data byte 4

+ +
+
+ +
+
+ + + + +
#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
+
+

Data byte 5

+ +
+
+ +
+
+ + + + +
#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
+
+

Data byte 6

+ +
+
+ +
+
+ + + + +
#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
+
+

Data byte 7 CAN filter registers

+ +
+
+ +
+
+ + + + +
#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
+
+

Data byte 0

+ +
+
+ +
+
+ + + + +
#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
+
+

Data byte 1

+ +
+
+ +
+
+ + + + +
#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
+
+

Data byte 2

+ +
+
+ +
+
+ + + + +
#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
+
+

Data byte 3

+ +
+
+ +
+
+ + + + +
#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
+
+

Data byte 0

+ +
+
+ +
+
+ + + + +
#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
+
+

Data byte 1

+ +
+
+ +
+
+ + + + +
#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
+
+

Data byte 2

+ +
+
+ +
+
+ + + + +
#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
+
+

Data byte 3

+ +
+
+ +
+
+ + + + +
#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
+
+

Data Length Code

+ +
+
+ +
+
+ + + + +
#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
+
+

Filter Match Index

+ +
+
+ +
+
+ + + + +
#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
+
+

Message Time Stamp

+ +
+
+ +
+
+ + + + +
#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
+
+

Data Length Code

+ +
+
+ +
+
+ + + + +
#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
+
+

Filter Match Index

+ +
+
+ +
+
+ + + + +
#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
+
+

Message Time Stamp

+ +
+
+ +
+
+ + + + +
#define CAN_RF0R_FMP0   ((uint8_t)0x03)
+
+

FIFO 0 Message Pending

+ +
+
+ +
+
+ + + + +
#define CAN_RF0R_FOVR0   ((uint8_t)0x10)
+
+

FIFO 0 Overrun

+ +
+
+ +
+
+ + + + +
#define CAN_RF0R_FULL0   ((uint8_t)0x08)
+
+

FIFO 0 Full

+ +
+
+ +
+
+ + + + +
#define CAN_RF0R_RFOM0   ((uint8_t)0x20)
+
+

Release FIFO 0 Output Mailbox

+ +
+
+ +
+
+ + + + +
#define CAN_RF1R_FMP1   ((uint8_t)0x03)
+
+

FIFO 1 Message Pending

+ +
+
+ +
+
+ + + + +
#define CAN_RF1R_FOVR1   ((uint8_t)0x10)
+
+

FIFO 1 Overrun

+ +
+
+ +
+
+ + + + +
#define CAN_RF1R_FULL1   ((uint8_t)0x08)
+
+

FIFO 1 Full

+ +
+
+ +
+
+ + + + +
#define CAN_RF1R_RFOM1   ((uint8_t)0x20)
+
+

Release FIFO 1 Output Mailbox

+ +
+
+ +
+
+ + + + +
#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
+
+

Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_RI0R_IDE   ((uint32_t)0x00000004)
+
+

Identifier Extension

+ +
+
+ +
+
+ + + + +
#define CAN_RI0R_RTR   ((uint32_t)0x00000002)
+
+

Remote Transmission Request

+ +
+
+ +
+
+ + + + +
#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)
+
+

Standard Identifier or Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
+
+

Extended identifier

+ +
+
+ +
+
+ + + + +
#define CAN_RI1R_IDE   ((uint32_t)0x00000004)
+
+

Identifier Extension

+ +
+
+ +
+
+ + + + +
#define CAN_RI1R_RTR   ((uint32_t)0x00000002)
+
+

Remote Transmission Request

+ +
+
+ +
+
+ + + + +
#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)
+
+

Standard Identifier or Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
+
+

Data byte 4

+ +
+
+ +
+
+ + + + +
#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
+
+

Data byte 5

+ +
+
+ +
+
+ + + + +
#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
+
+

Data byte 6

+ +
+
+ +
+
+ + + + +
#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
+
+

Data byte 7

+ +
+
+ +
+
+ + + + +
#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
+
+

Data byte 4

+ +
+
+ +
+
+ + + + +
#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
+
+

Data byte 5

+ +
+
+ +
+
+ + + + +
#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
+
+

Data byte 6

+ +
+
+ +
+
+ + + + +
#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
+
+

Data byte 7

+ +
+
+ +
+
+ + + + +
#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
+
+

Data byte 4

+ +
+
+ +
+
+ + + + +
#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
+
+

Data byte 5

+ +
+
+ +
+
+ + + + +
#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
+
+

Data byte 6

+ +
+
+ +
+
+ + + + +
#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
+
+

Data byte 7

+ +
+
+ +
+
+ + + + +
#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
+
+

Data byte 0

+ +
+
+ +
+
+ + + + +
#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
+
+

Data byte 1

+ +
+
+ +
+
+ + + + +
#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
+
+

Data byte 2

+ +
+
+ +
+
+ + + + +
#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
+
+

Data byte 3

+ +
+
+ +
+
+ + + + +
#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
+
+

Data byte 0

+ +
+
+ +
+
+ + + + +
#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
+
+

Data byte 1

+ +
+
+ +
+
+ + + + +
#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
+
+

Data byte 2

+ +
+
+ +
+
+ + + + +
#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
+
+

Data byte 3

+ +
+
+ +
+
+ + + + +
#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
+
+

Data byte 0

+ +
+
+ +
+
+ + + + +
#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
+
+

Data byte 1

+ +
+
+ +
+
+ + + + +
#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
+
+

Data byte 2

+ +
+
+ +
+
+ + + + +
#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
+
+

Data byte 3

+ +
+
+ +
+
+ + + + +
#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
+
+

Data Length Code

+ +
+
+ +
+
+ + + + +
#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)
+
+

Transmit Global Time

+ +
+
+ +
+
+ + + + +
#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
+
+

Message Time Stamp

+ +
+
+ +
+
+ + + + +
#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
+
+

Data Length Code

+ +
+
+ +
+
+ + + + +
#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)
+
+

Transmit Global Time

+ +
+
+ +
+
+ + + + +
#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
+
+

Message Time Stamp

+ +
+
+ +
+
+ + + + +
#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
+
+

Data Length Code

+ +
+
+ +
+
+ + + + +
#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)
+
+

Transmit Global Time

+ +
+
+ +
+
+ + + + +
#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
+
+

Message Time Stamp

+ +
+
+ +
+
+ + + + +
#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
+
+

Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI0R_IDE   ((uint32_t)0x00000004)
+
+

Identifier Extension

+ +
+
+ +
+
+ + + + +
#define CAN_TI0R_RTR   ((uint32_t)0x00000002)
+
+

Remote Transmission Request

+ +
+
+ +
+
+ + + + +
#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)
+
+

Standard Identifier or Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
+
+

Transmit Mailbox Request

+ +
+
+ +
+
+ + + + +
#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
+
+

Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI1R_IDE   ((uint32_t)0x00000004)
+
+

Identifier Extension

+ +
+
+ +
+
+ + + + +
#define CAN_TI1R_RTR   ((uint32_t)0x00000002)
+
+

Remote Transmission Request

+ +
+
+ +
+
+ + + + +
#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)
+
+

Standard Identifier or Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
+
+

Transmit Mailbox Request

+ +
+
+ +
+
+ + + + +
#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
+
+

Extended identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI2R_IDE   ((uint32_t)0x00000004)
+
+

Identifier Extension

+ +
+
+ +
+
+ + + + +
#define CAN_TI2R_RTR   ((uint32_t)0x00000002)
+
+

Remote Transmission Request

+ +
+
+ +
+
+ + + + +
#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)
+
+

Standard Identifier or Extended Identifier

+ +
+
+ +
+
+ + + + +
#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
+
+

Transmit Mailbox Request

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
+
+

Abort Request for Mailbox0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
+
+

Abort Request for Mailbox 1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
+
+

Abort Request for Mailbox 2

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ALST0   ((uint32_t)0x00000004)
+
+

Arbitration Lost for Mailbox0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ALST1   ((uint32_t)0x00000400)
+
+

Arbitration Lost for Mailbox1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_ALST2   ((uint32_t)0x00040000)
+
+

Arbitration Lost for mailbox 2

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_CODE   ((uint32_t)0x03000000)
+
+

Mailbox Code

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_LOW   ((uint32_t)0xE0000000)
+
+

LOW[2:0] bits

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_LOW0   ((uint32_t)0x20000000)
+
+

Lowest Priority Flag for Mailbox 0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_LOW1   ((uint32_t)0x40000000)
+
+

Lowest Priority Flag for Mailbox 1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_LOW2   ((uint32_t)0x80000000)
+
+

Lowest Priority Flag for Mailbox 2

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)
+
+

Request Completed Mailbox0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)
+
+

Request Completed Mailbox1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)
+
+

Request Completed Mailbox2

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TERR0   ((uint32_t)0x00000008)
+
+

Transmission Error of Mailbox0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TERR1   ((uint32_t)0x00000800)
+
+

Transmission Error of Mailbox1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TERR2   ((uint32_t)0x00080000)
+
+

Transmission Error of Mailbox 2

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TME   ((uint32_t)0x1C000000)
+
+

TME[2:0] bits

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TME0   ((uint32_t)0x04000000)
+
+

Transmit Mailbox 0 Empty

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TME1   ((uint32_t)0x08000000)
+
+

Transmit Mailbox 1 Empty

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TME2   ((uint32_t)0x10000000)
+
+

Transmit Mailbox 2 Empty

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)
+
+

Transmission OK of Mailbox0

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)
+
+

Transmission OK of Mailbox1

+ +
+
+ +
+
+ + + + +
#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)
+
+

Transmission OK of Mailbox 2

+ +
+
+ +
+
+ + + + +
#define CRC_CR_RESET   ((uint8_t)0x01)
+
+

RESET bit

+ +
+
+ +
+
+ + + + +
#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
+
+

Data register bits

+ +
+
+ +
+
+ + + + +
#define CRC_IDR_IDR   ((uint8_t)0xFF)
+
+

General-purpose 8-bit data register bits

+ +
+
+ +
+
+ + + + +
#define DAC_CR_BOFF1   ((uint32_t)0x00000002)
+
+

DAC channel1 output buffer disable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_BOFF2   ((uint32_t)0x00020000)
+
+

DAC channel2 output buffer disable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)
+
+

DAC channel1 DMA enable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)
+
+

DAC channel2 DMA enabled

+ +
+
+ +
+
+ + + + +
#define DAC_CR_EN1   ((uint32_t)0x00000001)
+
+

DAC channel1 enable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_EN2   ((uint32_t)0x00010000)
+
+

DAC channel2 enable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)
+
+

MAMP13:0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)
+
+

MAMP23:0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TEN1   ((uint32_t)0x00000004)
+
+

DAC channel1 Trigger enable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TEN2   ((uint32_t)0x00040000)
+
+

DAC channel2 Trigger enable

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL1   ((uint32_t)0x00000038)
+
+

TSEL1[2:0] (DAC channel1 Trigger selection)

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL2   ((uint32_t)0x00380000)
+
+

TSEL2[2:0] (DAC channel2 Trigger selection)

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)
+
+

WAVE11:0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)
+
+

WAVE21:0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
+
+

DAC channel1 12-bit Left aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
+
+

DAC channel2 12-bit Left aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
+
+

DAC channel1 12-bit Left aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
+
+

DAC channel2 12-bit Left aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
+
+

DAC channel1 12-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
+
+

DAC channel2 12-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
+
+

DAC channel1 12-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
+
+

DAC channel2 12-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
+
+

DAC channel1 8-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
+
+

DAC channel2 8-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
+
+

DAC channel1 8-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
+
+

DAC channel2 8-bit Right aligned data

+ +
+
+ +
+
+ + + + +
#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
+
+

DAC channel1 data output

+ +
+
+ +
+
+ + + + +
#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
+
+

DAC channel2 data output

+ +
+
+ +
+
+ + + + +
#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
+
+

DAC channel1 DMA underrun flag

+ +
+
+ +
+
+ + + + +
#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
+
+

DAC channel2 DMA underrun flag

+ +
+
+ +
+
+ + + + +
#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
+
+

DAC channel1 software trigger

+ +
+
+ +
+
+ + + + +
#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
+
+

DAC channel2 software trigger

+ +
+
+ +
+
+ + + + +
#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define DMA2D_AMTCR_DT   ((uint32_t)0x0000FF00)
+
+

Dead Time

+ +
+
+ +
+
+ + + + +
#define DMA2D_AMTCR_EN   ((uint32_t)0x00000001)
+
+

Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGCMAR_MA   ((uint32_t)0xFFFFFFFF)
+
+

Memory Address

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGCOLR_BLUE   ((uint32_t)0x000000FF)
+
+

Blue Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGCOLR_GREEN   ((uint32_t)0x0000FF00)
+
+

Green Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGCOLR_RED   ((uint32_t)0x00FF0000)
+
+

Red Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGMAR_MA   ((uint32_t)0xFFFFFFFF)
+
+

Memory Address

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGOR_LO   ((uint32_t)0x00003FFF)
+
+

Line Offset

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_ALPHA   ((uint32_t)0xFF000000)
+
+

Alpha value

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_AM   ((uint32_t)0x00030000)
+
+

Alpha Mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_CCM   ((uint32_t)0x00000010)
+
+

CLUT Color mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_CM   ((uint32_t)0x0000000F)
+
+

Color mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_CS   ((uint32_t)0x0000FF00)
+
+

CLUT size

+ +
+
+ +
+
+ + + + +
#define DMA2D_BGPFCCR_START   ((uint32_t)0x00000020)
+
+

Start

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_ABORT   ((uint32_t)0x00000004)
+
+

Abort transfer

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_CAEIE   ((uint32_t)0x00000800)
+
+

CLUT Access Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_CEIE   ((uint32_t)0x00002000)
+
+

Configuration Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_CTCIE   ((uint32_t)0x00001000)
+
+

CLUT Transfer Complete Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_MODE   ((uint32_t)0x00030000)
+
+

DMA2D Mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_START   ((uint32_t)0x00000001)
+
+

Start transfer

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_SUSP   ((uint32_t)0x00000002)
+
+

Suspend transfer

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_TCIE   ((uint32_t)0x00000200)
+
+

Transfer Complete Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_TEIE   ((uint32_t)0x00000100)
+
+

Transfer Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_CR_TWIE   ((uint32_t)0x00000400)
+
+

Transfer Watermark Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGCMAR_MA   ((uint32_t)0xFFFFFFFF)
+
+

Memory Address

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGCOLR_BLUE   ((uint32_t)0x000000FF)
+
+

Blue Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGCOLR_GREEN   ((uint32_t)0x0000FF00)
+
+

Green Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGCOLR_RED   ((uint32_t)0x00FF0000)
+
+

Red Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGMAR_MA   ((uint32_t)0xFFFFFFFF)
+
+

Memory Address

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGOR_LO   ((uint32_t)0x00003FFF)
+
+

Line Offset

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_ALPHA   ((uint32_t)0xFF000000)
+
+

Alpha value

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_AM   ((uint32_t)0x00030000)
+
+

Alpha mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_CCM   ((uint32_t)0x00000010)
+
+

CLUT Color mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_CM   ((uint32_t)0x0000000F)
+
+

Color mode

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_CS   ((uint32_t)0x0000FF00)
+
+

CLUT size

+ +
+
+ +
+
+ + + + +
#define DMA2D_FGPFCCR_START   ((uint32_t)0x00000020)
+
+

Start

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CCAEIF   ((uint32_t)0x00000008)
+
+

Clears CLUT Access Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CCEIF   ((uint32_t)0x00000020)
+
+

Clears Configuration Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CCTCIF   ((uint32_t)0x00000010)
+
+

Clears CLUT Transfer Complete Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CTCIF   ((uint32_t)0x00000002)
+
+

Clears Transfer Complete Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CTEIF   ((uint32_t)0x00000001)
+
+

Clears Transfer Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_IFSR_CTWIF   ((uint32_t)0x00000004)
+
+

Clears Transfer Watermark Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_CAEIF   ((uint32_t)0x00000008)
+
+

CLUT Access Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_CEIF   ((uint32_t)0x00000020)
+
+

Configuration Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_CTCIF   ((uint32_t)0x00000010)
+
+

CLUT Transfer Complete Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_TCIF   ((uint32_t)0x00000002)
+
+

Transfer Complete Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_TEIF   ((uint32_t)0x00000001)
+
+

Transfer Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_ISR_TWIF   ((uint32_t)0x00000004)
+
+

Transfer Watermark Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define DMA2D_LWR_LW   ((uint32_t)0x0000FFFF)
+
+

Line Watermark

+ +
+
+ +
+
+ + + + +
#define DMA2D_NLR_NL   ((uint32_t)0x0000FFFF)
+
+

Number of Lines

+ +
+
+ +
+
+ + + + +
#define DMA2D_NLR_PL   ((uint32_t)0x3FFF0000)
+
+

Pixel per Lines

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_ALPHA_1   ((uint32_t)0xFF000000)
+
+

Alpha Channel Value Mode_RGB565

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_ALPHA_3   ((uint32_t)0x00008000)
+
+

Alpha Channel Value Mode_ARGB4444

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_ALPHA_4   ((uint32_t)0x0000F000)
+
+

Alpha Channel Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_BLUE_1   ((uint32_t)0x000000FF)
+
+

<Mode_ARGB8888/RGB888 BLUE Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_BLUE_2   ((uint32_t)0x0000001F)
+
+

BLUE Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_BLUE_3   ((uint32_t)0x0000001F)
+
+

BLUE Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_BLUE_4   ((uint32_t)0x0000000F)
+
+

BLUE Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_GREEN_1   ((uint32_t)0x0000FF00)
+
+

GREEN Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_GREEN_2   ((uint32_t)0x000007E0)
+
+

GREEN Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_GREEN_3   ((uint32_t)0x000003E0)
+
+

GREEN Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_GREEN_4   ((uint32_t)0x000000F0)
+
+

GREEN Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_RED_1   ((uint32_t)0x00FF0000)
+
+

Red Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_RED_2   ((uint32_t)0x0000F800)
+
+

Red Value Mode_ARGB1555

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_RED_3   ((uint32_t)0x00007C00)
+
+

Red Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OCOLR_RED_4   ((uint32_t)0x00000F00)
+
+

Red Value

+ +
+
+ +
+
+ + + + +
#define DMA2D_OMAR_MA   ((uint32_t)0xFFFFFFFF)
+
+

Memory Address

+ +
+
+ +
+
+ + + + +
#define DMA2D_OOR_LO   ((uint32_t)0x00003FFF)
+
+

Line Offset

+ +
+
+ +
+
+ + + + +
#define DMA2D_OPFCCR_CM   ((uint32_t)0x00000007)
+
+

Color mode

+ +
+
+ +
+
+ + + + +
#define ETH_MACCR_BL
+
+Value:
((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+
a transmission attempt during retries after a collision: 0 =< r <2^k */
+
+
+
+ +
+
+ + + + +
#define EXTI_EMR_MR0   ((uint32_t)0x00000001)
+
+

Event Mask on line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR1   ((uint32_t)0x00000002)
+
+

Event Mask on line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR10   ((uint32_t)0x00000400)
+
+

Event Mask on line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR11   ((uint32_t)0x00000800)
+
+

Event Mask on line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR12   ((uint32_t)0x00001000)
+
+

Event Mask on line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR13   ((uint32_t)0x00002000)
+
+

Event Mask on line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR14   ((uint32_t)0x00004000)
+
+

Event Mask on line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR15   ((uint32_t)0x00008000)
+
+

Event Mask on line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR16   ((uint32_t)0x00010000)
+
+

Event Mask on line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR17   ((uint32_t)0x00020000)
+
+

Event Mask on line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR18   ((uint32_t)0x00040000)
+
+

Event Mask on line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR19   ((uint32_t)0x00080000)
+
+

Event Mask on line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR2   ((uint32_t)0x00000004)
+
+

Event Mask on line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR3   ((uint32_t)0x00000008)
+
+

Event Mask on line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR4   ((uint32_t)0x00000010)
+
+

Event Mask on line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR5   ((uint32_t)0x00000020)
+
+

Event Mask on line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR6   ((uint32_t)0x00000040)
+
+

Event Mask on line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR7   ((uint32_t)0x00000080)
+
+

Event Mask on line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR8   ((uint32_t)0x00000100)
+
+

Event Mask on line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_EMR_MR9   ((uint32_t)0x00000200)
+
+

Event Mask on line 9

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)
+
+

Falling trigger event configuration bit of line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)
+
+

Falling trigger event configuration bit of line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)
+
+

Falling trigger event configuration bit of line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)
+
+

Falling trigger event configuration bit of line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)
+
+

Falling trigger event configuration bit of line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)
+
+

Falling trigger event configuration bit of line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)
+
+

Falling trigger event configuration bit of line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)
+
+

Falling trigger event configuration bit of line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)
+
+

Falling trigger event configuration bit of line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)
+
+

Falling trigger event configuration bit of line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)
+
+

Falling trigger event configuration bit of line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)
+
+

Falling trigger event configuration bit of line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)
+
+

Falling trigger event configuration bit of line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)
+
+

Falling trigger event configuration bit of line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)
+
+

Falling trigger event configuration bit of line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)
+
+

Falling trigger event configuration bit of line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)
+
+

Falling trigger event configuration bit of line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)
+
+

Falling trigger event configuration bit of line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)
+
+

Falling trigger event configuration bit of line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)
+
+

Falling trigger event configuration bit of line 9

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR0   ((uint32_t)0x00000001)
+
+

Interrupt Mask on line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR1   ((uint32_t)0x00000002)
+
+

Interrupt Mask on line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR10   ((uint32_t)0x00000400)
+
+

Interrupt Mask on line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR11   ((uint32_t)0x00000800)
+
+

Interrupt Mask on line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR12   ((uint32_t)0x00001000)
+
+

Interrupt Mask on line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR13   ((uint32_t)0x00002000)
+
+

Interrupt Mask on line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR14   ((uint32_t)0x00004000)
+
+

Interrupt Mask on line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR15   ((uint32_t)0x00008000)
+
+

Interrupt Mask on line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR16   ((uint32_t)0x00010000)
+
+

Interrupt Mask on line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR17   ((uint32_t)0x00020000)
+
+

Interrupt Mask on line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR18   ((uint32_t)0x00040000)
+
+

Interrupt Mask on line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR19   ((uint32_t)0x00080000)
+
+

Interrupt Mask on line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR2   ((uint32_t)0x00000004)
+
+

Interrupt Mask on line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR3   ((uint32_t)0x00000008)
+
+

Interrupt Mask on line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR4   ((uint32_t)0x00000010)
+
+

Interrupt Mask on line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR5   ((uint32_t)0x00000020)
+
+

Interrupt Mask on line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR6   ((uint32_t)0x00000040)
+
+

Interrupt Mask on line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR7   ((uint32_t)0x00000080)
+
+

Interrupt Mask on line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR8   ((uint32_t)0x00000100)
+
+

Interrupt Mask on line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_IMR_MR9   ((uint32_t)0x00000200)
+
+

Interrupt Mask on line 9

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR0   ((uint32_t)0x00000001)
+
+

Pending bit for line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR1   ((uint32_t)0x00000002)
+
+

Pending bit for line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR10   ((uint32_t)0x00000400)
+
+

Pending bit for line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR11   ((uint32_t)0x00000800)
+
+

Pending bit for line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR12   ((uint32_t)0x00001000)
+
+

Pending bit for line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR13   ((uint32_t)0x00002000)
+
+

Pending bit for line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR14   ((uint32_t)0x00004000)
+
+

Pending bit for line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR15   ((uint32_t)0x00008000)
+
+

Pending bit for line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR16   ((uint32_t)0x00010000)
+
+

Pending bit for line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR17   ((uint32_t)0x00020000)
+
+

Pending bit for line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR18   ((uint32_t)0x00040000)
+
+

Pending bit for line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR19   ((uint32_t)0x00080000)
+
+

Pending bit for line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR2   ((uint32_t)0x00000004)
+
+

Pending bit for line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR3   ((uint32_t)0x00000008)
+
+

Pending bit for line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR4   ((uint32_t)0x00000010)
+
+

Pending bit for line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR5   ((uint32_t)0x00000020)
+
+

Pending bit for line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR6   ((uint32_t)0x00000040)
+
+

Pending bit for line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR7   ((uint32_t)0x00000080)
+
+

Pending bit for line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR8   ((uint32_t)0x00000100)
+
+

Pending bit for line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_PR_PR9   ((uint32_t)0x00000200)
+
+

Pending bit for line 9

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)
+
+

Rising trigger event configuration bit of line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)
+
+

Rising trigger event configuration bit of line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)
+
+

Rising trigger event configuration bit of line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)
+
+

Rising trigger event configuration bit of line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)
+
+

Rising trigger event configuration bit of line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)
+
+

Rising trigger event configuration bit of line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)
+
+

Rising trigger event configuration bit of line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)
+
+

Rising trigger event configuration bit of line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)
+
+

Rising trigger event configuration bit of line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)
+
+

Rising trigger event configuration bit of line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)
+
+

Rising trigger event configuration bit of line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)
+
+

Rising trigger event configuration bit of line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)
+
+

Rising trigger event configuration bit of line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)
+
+

Rising trigger event configuration bit of line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)
+
+

Rising trigger event configuration bit of line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)
+
+

Rising trigger event configuration bit of line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)
+
+

Rising trigger event configuration bit of line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)
+
+

Rising trigger event configuration bit of line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)
+
+

Rising trigger event configuration bit of line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)
+
+

Rising trigger event configuration bit of line 9

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
+
+

Software Interrupt on line 0

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
+
+

Software Interrupt on line 1

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
+
+

Software Interrupt on line 10

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
+
+

Software Interrupt on line 11

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
+
+

Software Interrupt on line 12

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
+
+

Software Interrupt on line 13

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
+
+

Software Interrupt on line 14

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
+
+

Software Interrupt on line 15

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
+
+

Software Interrupt on line 16

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
+
+

Software Interrupt on line 17

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
+
+

Software Interrupt on line 18

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
+
+

Software Interrupt on line 19

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
+
+

Software Interrupt on line 2

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
+
+

Software Interrupt on line 3

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
+
+

Software Interrupt on line 4

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
+
+

Software Interrupt on line 5

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
+
+

Software Interrupt on line 6

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
+
+

Software Interrupt on line 7

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
+
+

Software Interrupt on line 8

+ +
+
+ +
+
+ + + + +
#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
+
+

Software Interrupt on line 9

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
+
+

Asynchronous wait

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
+
+

Burst enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
+
+

Write burst enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
+
+

Extended mode enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
+
+

Flash access enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
+
+

Memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
+
+

MTYP[1:0] bits (Memory type)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
+
+

Address/data multiplexing enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)
+
+

MWID[1:0] bits (Memory data bus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
+
+

Wait timing configuration

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
+
+

Wait enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
+
+

Wait signal polarity bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
+
+

Wrapped burst mode support

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)
+
+

Write enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
+
+

Asynchronous wait

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
+
+

Burst enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
+
+

Write burst enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
+
+

Extended mode enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
+
+

Flash access enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
+
+

Memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
+
+

MTYP[1:0] bits (Memory type)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
+
+

Address/data multiplexing enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)
+
+

MWID[1:0] bits (Memory data bus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
+
+

Wait timing configuration

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
+
+

Wait enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
+
+

Wait signal polarity bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
+
+

Wrapped burst mode support

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)
+
+

Write enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
+
+

Asynchronous wait

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
+
+

Burst enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
+
+

Write burst enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
+
+

Extended mode enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
+
+

Flash access enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
+
+

Memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
+
+

MTYP[1:0] bits (Memory type)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
+
+

Address/data multiplexing enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)
+
+

MWID[1:0] bits (Memory data bus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
+
+

Wait timing configuration

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
+
+

Wait enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
+
+

Wait signal polarity bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
+
+

Wrapped burst mode support

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)
+
+

Write enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
+
+

Asynchronous wait

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
+
+

Burst enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
+
+

Write burst enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
+
+

Extended mode enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
+
+

Flash access enable

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
+
+

Memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
+
+

MTYP[1:0] bits (Memory type)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
+
+

Address/data multiplexing enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)
+
+

MWID[1:0] bits (Memory data bus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
+
+

Wait timing configuration

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
+
+

Wait enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
+
+

Wait signal polarity bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
+
+

Wrapped burst mode support

+ +
+
+ +
+
+ + + + +
#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)
+
+

Write enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
+
+

BUSTURN[3:0] bits (Bus turnaround phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
+
+

BUSTURN[3:0] bits (Bus turnaround phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
+
+

BUSTURN[3:0] bits (Bus turnaround phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
+
+

BUSTURN[3:0] bits (Bus turnaround phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
+
+

ACCMOD[1:0] bits (Access mode)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
+
+

ADDHLD[3:0] bits (Address-hold phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
+
+

ADDSET[3:0] bits (Address setup phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
+
+

CLKDIV[3:0] bits (Clock divide ratio)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
+
+

DATAST [3:0] bits (Data-phase duration)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
+
+

DATLA[3:0] bits (Data latency)

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
+
+

ECC result

+ +
+
+ +
+
+ + + + +
#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
+
+

ECC result

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
+
+

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
+
+

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
+
+

ATTSET2[7:0] bits (Attribute memory 2 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
+
+

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
+
+

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
+
+

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
+
+

ATTSET3[7:0] bits (Attribute memory 3 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
+
+

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
+
+

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
+
+

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
+
+

ATTSET4[7:0] bits (Attribute memory 4 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
+
+

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
+
+

ECC computation logic enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
+
+

ECCPS[1:0] bits (ECC page size)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
+
+

PC Card/NAND Flash memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
+
+

Memory type

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
+
+

Wait feature enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)
+
+

PWID[1:0] bits (NAND Flash databus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
+
+

TAR[3:0] bits (ALE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
+
+

TCLR[3:0] bits (CLE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
+
+

ECC computation logic enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
+
+

ECCPS[2:0] bits (ECC page size)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
+
+

PC Card/NAND Flash memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
+
+

Memory type

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
+
+

Wait feature enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)
+
+

PWID[1:0] bits (NAND Flash databus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
+
+

TAR[3:0] bits (ALE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
+
+

TCLR[3:0] bits (CLE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
+
+

ECC computation logic enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
+
+

ECCPS[2:0] bits (ECC page size)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
+
+

PC Card/NAND Flash memory bank enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
+
+

Memory type

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
+
+

Wait feature enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)
+
+

PWID[1:0] bits (NAND Flash databus width)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
+
+

TAR[3:0] bits (ALE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
+
+

TCLR[3:0] bits (CLE to RE delay)

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
+
+

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
+
+

IOHOLD4[7:0] bits (I/O 4 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
+
+

IOSET4[7:0] bits (I/O 4 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
+
+

IOWAIT4[7:0] bits (I/O 4 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
+
+

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
+
+

MEMHOLD2[7:0] bits (Common memory 2 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
+
+

MEMSET2[7:0] bits (Common memory 2 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
+
+

MEMWAIT2[7:0] bits (Common memory 2 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
+
+

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
+
+

MEMHOLD3[7:0] bits (Common memory 3 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
+
+

MEMSET3[7:0] bits (Common memory 3 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
+
+

MEMWAIT3[7:0] bits (Common memory 3 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
+
+

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
+
+

MEMHOLD4[7:0] bits (Common memory 4 hold time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
+
+

MEMSET4[7:0] bits (Common memory 4 setup time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
+
+

MEMWAIT4[7:0] bits (Common memory 4 wait time)

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_FEMPT   ((uint8_t)0x40)
+
+

FIFO empty

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_IFEN   ((uint8_t)0x20)
+
+

Interrupt Falling Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_IFS   ((uint8_t)0x04)
+
+

Interrupt Falling Edge status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_ILEN   ((uint8_t)0x10)
+
+

Interrupt Level detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_ILS   ((uint8_t)0x02)
+
+

Interrupt Level status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_IREN   ((uint8_t)0x08)
+
+

Interrupt Rising Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR2_IRS   ((uint8_t)0x01)
+
+

Interrupt Rising Edge status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_FEMPT   ((uint8_t)0x40)
+
+

FIFO empty

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_IFEN   ((uint8_t)0x20)
+
+

Interrupt Falling Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_IFS   ((uint8_t)0x04)
+
+

Interrupt Falling Edge status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_ILEN   ((uint8_t)0x10)
+
+

Interrupt Level detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_ILS   ((uint8_t)0x02)
+
+

Interrupt Level status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_IREN   ((uint8_t)0x08)
+
+

Interrupt Rising Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR3_IRS   ((uint8_t)0x01)
+
+

Interrupt Rising Edge status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_FEMPT   ((uint8_t)0x40)
+
+

FIFO empty

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_IFEN   ((uint8_t)0x20)
+
+

Interrupt Falling Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_IFS   ((uint8_t)0x04)
+
+

Interrupt Falling Edge status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_ILEN   ((uint8_t)0x10)
+
+

Interrupt Level detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_ILS   ((uint8_t)0x02)
+
+

Interrupt Level status

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_IREN   ((uint8_t)0x08)
+
+

Interrupt Rising Edge detection Enable bit

+ +
+
+ +
+
+ + + + +
#define FSMC_SR4_IRS   ((uint8_t)0x01)
+
+

Interrupt Rising Edge status

+ +
+
+ +
+
+ + + + +
#define I2C_CCR_CCR   ((uint16_t)0x0FFF)
+
+

Clock Control Register in Fast/Standard mode (Master mode)

+ +
+
+ +
+
+ + + + +
#define I2C_CCR_DUTY   ((uint16_t)0x4000)
+
+

Fast Mode Duty Cycle

+ +
+
+ +
+
+ + + + +
#define I2C_CCR_FS   ((uint16_t)0x8000)
+
+

I2C Master Mode Selection

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_ACK   ((uint16_t)0x0400)
+
+

Acknowledge Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_ALERT   ((uint16_t)0x2000)
+
+

SMBus Alert

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_ENARP   ((uint16_t)0x0010)
+
+

ARP Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_ENGC   ((uint16_t)0x0040)
+
+

General Call Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_ENPEC   ((uint16_t)0x0020)
+
+

PEC Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
+
+

Clock Stretching Disable (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_PE   ((uint16_t)0x0001)
+
+

Peripheral Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_PEC   ((uint16_t)0x1000)
+
+

Packet Error Checking

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_POS   ((uint16_t)0x0800)
+
+

Acknowledge/PEC Position (for data reception)

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
+
+

SMBus Type

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_SMBUS   ((uint16_t)0x0002)
+
+

SMBus Mode

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_START   ((uint16_t)0x0100)
+
+

Start Generation

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_STOP   ((uint16_t)0x0200)
+
+

Stop Generation

+ +
+
+ +
+
+ + + + +
#define I2C_CR1_SWRST   ((uint16_t)0x8000)
+
+

Software Reset

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_DMAEN   ((uint16_t)0x0800)
+
+

DMA Requests Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ   ((uint16_t)0x003F)
+
+

FREQ[5:0] bits (Peripheral Clock Frequency)

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
+
+

Buffer Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_ITERREN   ((uint16_t)0x0100)
+
+

Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
+
+

Event Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define I2C_CR2_LAST   ((uint16_t)0x1000)
+
+

DMA Last Transfer

+ +
+
+ +
+
+ + + + +
#define I2C_DR_DR   ((uint8_t)0xFF)
+
+

8-bit Data Register

+ +
+
+ +
+
+ + + + +
#define I2C_FLTR_ANOFF   ((uint8_t)0x10)
+
+

Analog Noise Filter OFF

+ +
+
+ +
+
+ + + + +
#define I2C_FLTR_DNF   ((uint8_t)0x0F)
+
+

Digital Noise Filter

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
+
+

Interface Address

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD5   ((uint16_t)0x0020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD6   ((uint16_t)0x0040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD7   ((uint16_t)0x0080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD8   ((uint16_t)0x0100)
+
+

Bit 8

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
+
+

Interface Address

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADD9   ((uint16_t)0x0200)
+
+

Bit 9

+ +
+
+ +
+
+ + + + +
#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
+
+

Addressing Mode (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_OAR2_ADD2   ((uint8_t)0xFE)
+
+

Interface address

+ +
+
+ +
+
+ + + + +
#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)
+
+

Dual addressing mode enable

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_ADD10   ((uint16_t)0x0008)
+
+

10-bit header sent (Master mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_ADDR   ((uint16_t)0x0002)
+
+

Address sent (master mode)/matched (slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_AF   ((uint16_t)0x0400)
+
+

Acknowledge Failure

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_ARLO   ((uint16_t)0x0200)
+
+

Arbitration Lost (master mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_BERR   ((uint16_t)0x0100)
+
+

Bus Error

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_BTF   ((uint16_t)0x0004)
+
+

Byte Transfer Finished

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_OVR   ((uint16_t)0x0800)
+
+

Overrun/Underrun

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_PECERR   ((uint16_t)0x1000)
+
+

PEC Error in reception

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_RXNE   ((uint16_t)0x0040)
+
+

Data Register not Empty (receivers)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_SB   ((uint16_t)0x0001)
+
+

Start Bit (Master mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)
+
+

SMBus Alert

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_STOPF   ((uint16_t)0x0010)
+
+

Stop detection (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
+
+

Timeout or Tlow Error

+ +
+
+ +
+
+ + + + +
#define I2C_SR1_TXE   ((uint16_t)0x0080)
+
+

Data Register Empty (transmitters)

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_BUSY   ((uint16_t)0x0002)
+
+

Bus Busy

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_DUALF   ((uint16_t)0x0080)
+
+

Dual Flag (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_GENCALL   ((uint16_t)0x0010)
+
+

General Call Address (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_MSL   ((uint16_t)0x0001)
+
+

Master/Slave

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_PEC   ((uint16_t)0xFF00)
+
+

Packet Error Checking Register

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
+
+

SMBus Device Default Address (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)
+
+

SMBus Host Header (Slave mode)

+ +
+
+ +
+
+ + + + +
#define I2C_SR2_TRA   ((uint16_t)0x0004)
+
+

Transmitter/Receiver

+ +
+
+ +
+
+ + + + +
#define I2C_TRISE_TRISE   ((uint8_t)0x3F)
+
+

Maximum Rise Time in Fast/Standard mode (Master mode)

+ +
+
+ +
+
+ + + + +
#define IWDG_KR_KEY   ((uint16_t)0xFFFF)
+
+

Key value (write only, read 0000h)

+ +
+
+ +
+
+ + + + +
#define IWDG_PR_PR   ((uint8_t)0x07)
+
+

PR[2:0] (Prescaler divider)

+ +
+
+ +
+
+ + + + +
#define IWDG_PR_PR_0   ((uint8_t)0x01)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define IWDG_PR_PR_1   ((uint8_t)0x02)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define IWDG_PR_PR_2   ((uint8_t)0x04)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define IWDG_RLR_RL   ((uint16_t)0x0FFF)
+
+

Watchdog counter reload value

+ +
+
+ +
+
+ + + + +
#define IWDG_SR_PVU   ((uint8_t)0x01)
+
+

Watchdog prescaler value update

+ +
+
+ +
+
+ + + + +
#define IWDG_SR_RVU   ((uint8_t)0x02)
+
+

Watchdog counter reload value update

+ +
+
+ +
+
+ + + + +
#define LTDC_AWCR_AAH   ((uint32_t)0x000007FF)
+
+

Accumulated Active heigh

+ +
+
+ +
+
+ + + + +
#define LTDC_AWCR_AAW   ((uint32_t)0x0FFF0000)
+
+

Accumulated Active Width

+ +
+
+ +
+
+ + + + +
#define LTDC_BCCR_BCBLUE   ((uint32_t)0x000000FF)
+
+

Background Blue value

+ +
+
+ +
+
+ + + + +
#define LTDC_BCCR_BCGREEN   ((uint32_t)0x0000FF00)
+
+

Background Green value

+ +
+
+ +
+
+ + + + +
#define LTDC_BCCR_BCRED   ((uint32_t)0x00FF0000)
+
+

Background Red value

+ +
+
+ +
+
+ + + + +
#define LTDC_BPCR_AHBP   ((uint32_t)0x0FFF0000)
+
+

Accumulated Horizontal Back Porch

+ +
+
+ +
+
+ + + + +
#define LTDC_BPCR_AVBP   ((uint32_t)0x000007FF)
+
+

Accumulated Vertical Back Porch

+ +
+
+ +
+
+ + + + +
#define LTDC_CDSR_HDES   ((uint32_t)0x00000002)
+
+

Horizontal Data Enable Status

+ +
+
+ +
+
+ + + + +
#define LTDC_CDSR_HSYNCS   ((uint32_t)0x00000008)
+
+

Horizontal Synchronization Status

+ +
+
+ +
+
+ + + + +
#define LTDC_CDSR_VDES   ((uint32_t)0x00000001)
+
+

Vertical Data Enable Status

+ +
+
+ +
+
+ + + + +
#define LTDC_CDSR_VSYNCS   ((uint32_t)0x00000004)
+
+

Vertical Synchronization Status

+ +
+
+ +
+
+ + + + +
#define LTDC_CPSR_CXPOS   ((uint32_t)0xFFFF0000)
+
+

Current X Position

+ +
+
+ +
+
+ + + + +
#define LTDC_CPSR_CYPOS   ((uint32_t)0x0000FFFF)
+
+

Current Y Position

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_DBW   ((uint32_t)0x00000070)
+
+

Dither Blue Width

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_DEPOL   ((uint32_t)0x20000000)
+
+

Data Enable Polarity

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_DGW   ((uint32_t)0x00000700)
+
+

Dither Green Width

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_DRW   ((uint32_t)0x00007000)
+
+

Dither Red Width

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_DTEN   ((uint32_t)0x00010000)
+
+

Dither Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_HSPOL   ((uint32_t)0x80000000)
+
+

Horizontal Synchronization Polarity

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_LTDCEN   ((uint32_t)0x00000001)
+
+

LCD-TFT controller enable bit

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_PCPOL   ((uint32_t)0x10000000)
+
+

Pixel Clock Polarity

+ +
+
+ +
+
+ + + + +
#define LTDC_GCR_VSPOL   ((uint32_t)0x40000000)
+
+

Vertical Synchronization Polarity

+ +
+
+ +
+
+ + + + +
#define LTDC_ICR_CFUIF   ((uint32_t)0x00000002)
+
+

Clears the FIFO Underrun Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ICR_CLIF   ((uint32_t)0x00000001)
+
+

Clears the Line Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ICR_CRRIF   ((uint32_t)0x00000008)
+
+

Clears Register Reload interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ICR_CTERRIF   ((uint32_t)0x00000004)
+
+

Clears the Transfer Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_IER_FUIE   ((uint32_t)0x00000002)
+
+

FIFO Underrun Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_IER_LIE   ((uint32_t)0x00000001)
+
+

Line Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_IER_RRIE   ((uint32_t)0x00000008)
+
+

Register Reload interrupt enable

+ +
+
+ +
+
+ + + + +
#define LTDC_IER_TERRIE   ((uint32_t)0x00000004)
+
+

Transfer Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_ISR_FUIF   ((uint32_t)0x00000002)
+
+

FIFO Underrun Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ISR_LIF   ((uint32_t)0x00000001)
+
+

Line Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ISR_RRIF   ((uint32_t)0x00000008)
+
+

Register Reload interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_ISR_TERRIF   ((uint32_t)0x00000004)
+
+

Transfer Error Interrupt Flag

+ +
+
+ +
+
+ + + + +
#define LTDC_LIPCR_LIPOS   ((uint32_t)0x000007FF)
+
+

Line Interrupt Position

+ +
+
+ +
+
+ + + + +
#define LTDC_LxBFCR_BF1   ((uint32_t)0x00000700)
+
+

Blending Factor 1

+ +
+
+ +
+
+ + + + +
#define LTDC_LxBFCR_BF2   ((uint32_t)0x00000007)
+
+

Blending Factor 2

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCACR_CONSTA   ((uint32_t)0x000000FF)
+
+

Constant Alpha

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCFBAR_CFBADD   ((uint32_t)0xFFFFFFFF)
+
+

Color Frame Buffer Start Address

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCFBLNR_CFBLNBR   ((uint32_t)0x000007FF)
+
+

Frame Buffer Line Number

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCFBLR_CFBLL   ((uint32_t)0x00001FFF)
+
+

Color Frame Buffer Line Length

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCFBLR_CFBP   ((uint32_t)0x1FFF0000)
+
+

Color Frame Buffer Pitch in bytes

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCKCR_CKBLUE   ((uint32_t)0x000000FF)
+
+

Color Key Blue value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCKCR_CKGREEN   ((uint32_t)0x0000FF00)
+
+

Color Key Green value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCKCR_CKRED   ((uint32_t)0x00FF0000)
+
+

Color Key Red value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCLUTWR_BLUE   ((uint32_t)0x000000FF)
+
+

Blue value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCLUTWR_CLUTADD   ((uint32_t)0xFF000000)
+
+

CLUT address

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCLUTWR_GREEN   ((uint32_t)0x0000FF00)
+
+

Green value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCLUTWR_RED   ((uint32_t)0x00FF0000)
+
+

Red value

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCR_CLUTEN   ((uint32_t)0x00000010)
+
+

Color Lockup Table Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCR_COLKEN   ((uint32_t)0x00000002)
+
+

Color Keying Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_LxCR_LEN   ((uint32_t)0x00000001)
+
+

Layer Enable

+ +
+
+ +
+
+ + + + +
#define LTDC_LxDCCR_DCALPHA   ((uint32_t)0xFF000000)
+
+

Default Color Alpha

+ +
+
+ +
+
+ + + + +
#define LTDC_LxDCCR_DCBLUE   ((uint32_t)0x000000FF)
+
+

Default Color Blue

+ +
+
+ +
+
+ + + + +
#define LTDC_LxDCCR_DCGREEN   ((uint32_t)0x0000FF00)
+
+

Default Color Green

+ +
+
+ +
+
+ + + + +
#define LTDC_LxDCCR_DCRED   ((uint32_t)0x00FF0000)
+
+

Default Color Red

+ +
+
+ +
+
+ + + + +
#define LTDC_LxPFCR_PF   ((uint32_t)0x00000007)
+
+

Pixel Format

+ +
+
+ +
+
+ + + + +
#define LTDC_LxWHPCR_WHSPPOS   ((uint32_t)0xFFFF0000)
+
+

Window Horizontal Stop Position

+ +
+
+ +
+
+ + + + +
#define LTDC_LxWHPCR_WHSTPOS   ((uint32_t)0x00000FFF)
+
+

Window Horizontal Start Position

+ +
+
+ +
+
+ + + + +
#define LTDC_LxWVPCR_WVSPPOS   ((uint32_t)0xFFFF0000)
+
+

Window Vertical Stop Position

+ +
+
+ +
+
+ + + + +
#define LTDC_LxWVPCR_WVSTPOS   ((uint32_t)0x00000FFF)
+
+

Window Vertical Start Position

+ +
+
+ +
+
+ + + + +
#define LTDC_SRCR_IMR   ((uint32_t)0x00000001)
+
+

Immediate Reload

+ +
+
+ +
+
+ + + + +
#define LTDC_SRCR_VBR   ((uint32_t)0x00000002)
+
+

Vertical Blanking Reload

+ +
+
+ +
+
+ + + + +
#define LTDC_SSCR_HSW   ((uint32_t)0x0FFF0000)
+
+

Horizontal Synchronization Width

+ +
+
+ +
+
+ + + + +
#define LTDC_SSCR_VSH   ((uint32_t)0x000007FF)
+
+

Vertical Synchronization Height

+ +
+
+ +
+
+ + + + +
#define LTDC_TWCR_TOTALH   ((uint32_t)0x000007FF)
+
+

Total Heigh

+ +
+
+ +
+
+ + + + +
#define LTDC_TWCR_TOTALW   ((uint32_t)0x0FFF0000)
+
+

Total Width

+ +
+
+ +
+
+ + + + +
#define PWR_CR_ADCDC1   ((uint32_t)0x00002000)
+
+

Refer to AN4073 on how to use this bit

+ +
+
+ +
+
+ + + + +
#define PWR_CR_CSBF   ((uint32_t)0x00000008)
+
+

Clear Standby Flag

+ +
+
+ +
+
+ + + + +
#define PWR_CR_CWUF   ((uint32_t)0x00000004)
+
+

Clear Wakeup Flag

+ +
+
+ +
+
+ + + + +
#define PWR_CR_DBP   ((uint32_t)0x00000100)
+
+

Disable Backup Domain write protection

+ +
+
+ +
+
+ + + + +
#define PWR_CR_FISSR   ((uint32_t)0x00200000)
+
+

Flash Interface Stop while System Run

+ +
+
+ +
+
+ + + + +
#define PWR_CR_FMSSR   ((uint32_t)0x00100000)
+
+

Flash Memory Sleep System Run

+ +
+
+ +
+
+ + + + +
#define PWR_CR_FPDS   ((uint32_t)0x00000200)
+
+

Flash power down in Stop mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_LPDS   ((uint32_t)0x00000001)
+
+

Low-Power Deepsleep

+ +
+
+ +
+
+ + + + +
#define PWR_CR_LPLVDS   ((uint32_t)0x00000400)
+
+

Low-power regulator Low Voltage in Deep Sleep mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_LPUDS   ((uint32_t)0x00000400)
+
+

Low-Power Regulator in Stop under-drive mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_MRLVDS   ((uint32_t)0x00000800)
+
+

Main regulator Low Voltage in Deep Sleep mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_MRUDS   ((uint32_t)0x00000800)
+
+

Main regulator in Stop under-drive mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_ODEN   ((uint32_t)0x00010000)
+
+

Over Drive enable

+ +
+
+ +
+
+ + + + +
#define PWR_CR_ODSWEN   ((uint32_t)0x00020000)
+
+

Over Drive switch enabled

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PDDS   ((uint32_t)0x00000002)
+
+

Power Down Deepsleep

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS   ((uint32_t)0x000000E0)
+
+

PLS[2:0] bits (PVD Level Selection)

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_2   ((uint32_t)0x00000080)
+
+

Bit 2 PVD level configuration

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV0   ((uint32_t)0x00000000)
+
+

PVD level 0

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV1   ((uint32_t)0x00000020)
+
+

PVD level 1

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV2   ((uint32_t)0x00000040)
+
+

PVD level 2

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV3   ((uint32_t)0x00000060)
+
+

PVD level 3

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV4   ((uint32_t)0x00000080)
+
+

PVD level 4

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV5   ((uint32_t)0x000000A0)
+
+

PVD level 5

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV6   ((uint32_t)0x000000C0)
+
+

PVD level 6

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PLS_LEV7   ((uint32_t)0x000000E0)
+
+

PVD level 7

+ +
+
+ +
+
+ + + + +
#define PWR_CR_PVDE   ((uint32_t)0x00000010)
+
+

Power Voltage Detector Enable

+ +
+
+ +
+
+ + + + +
#define PWR_CR_UDEN   ((uint32_t)0x000C0000)
+
+

Under Drive enable in stop mode

+ +
+
+ +
+
+ + + + +
#define PWR_CR_UDEN_0   ((uint32_t)0x00040000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define PWR_CR_UDEN_1   ((uint32_t)0x00080000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define PWR_CR_VOS   ((uint32_t)0x0000C000)
+
+

VOS[1:0] bits (Regulator voltage scaling output selection)

+ +
+
+ +
+
+ + + + +
#define PWR_CR_VOS_0   ((uint32_t)0x00004000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define PWR_CR_VOS_1   ((uint32_t)0x00008000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_BRE   ((uint32_t)0x00000200)
+
+

Backup regulator enable

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_BRR   ((uint32_t)0x00000008)
+
+

Backup regulator ready

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_EWUP   ((uint32_t)0x00000100)
+
+

Enable WKUP pin

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_ODRDY   ((uint32_t)0x00010000)
+
+

Over Drive generator ready

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_ODSWRDY   ((uint32_t)0x00020000)
+
+

Over Drive Switch ready

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_PVDO   ((uint32_t)0x00000004)
+
+

PVD Output

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_SBF   ((uint32_t)0x00000002)
+
+

Standby Flag

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_UDSWRDY   ((uint32_t)0x000C0000)
+
+

Under Drive ready

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_VOSRDY   ((uint32_t)0x00004000)
+
+

Regulator voltage scaling output selection ready

+ +
+
+ +
+
+ + + + +
#define PWR_CSR_WUF   ((uint32_t)0x00000001)
+
+

Wakeup Flag

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
+
+

HPRE[3:0] bits (AHB prescaler)

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
+
+

SYSCLK not divided

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
+
+

SYSCLK divided by 128

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
+
+

SYSCLK divided by 16

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
+
+

SYSCLK divided by 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
+
+

SYSCLK divided by 256

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
+
+

SYSCLK divided by 4

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
+
+

SYSCLK divided by 512 PPRE1 configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
+
+

SYSCLK divided by 64

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
+
+

SYSCLK divided by 8

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
+
+

PRE1[2:0] bits (APB1 prescaler)

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
+
+

HCLK not divided

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
+
+

HCLK divided by 16 PPRE2 configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
+
+

HCLK divided by 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
+
+

HCLK divided by 4

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
+
+

HCLK divided by 8

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
+
+

PRE2[2:0] bits (APB2 prescaler)

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
+
+

HCLK not divided

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)
+
+

HCLK divided by 16 RTCPRE configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
+
+

HCLK divided by 2

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
+
+

HCLK divided by 4

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
+
+

HCLK divided by 8

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
+
+

MCO1 configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW   ((uint32_t)0x00000003)
+
+

< SW configuration SW[1:0] bits (System clock Switch)

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
+
+

HSE selected as system clock

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
+
+

HSI selected as system clock

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
+
+

PLL selected as system clock SWS configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)
+
+

SWS[1:0] bits (System Clock Switch Status)

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
+
+

HSE oscillator used as system clock

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
+
+

HSI oscillator used as system clock

+ +
+
+ +
+
+ + + + +
#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
+
+

PLL used as system clock HPRE configuration

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCIN   ((uint32_t)0x00000003)
+
+

SYNCIN[1:0] bits (Synchronization Inputs)

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCIN_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCIN_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCOUT   ((uint32_t)0x00000030)
+
+

SYNCOUT[1:0] bits (Synchronization Outputs)

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCOUT_0   ((uint32_t)0x00000010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_GCR_SYNCOUT_1   ((uint32_t)0x00000020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CAFSDET   ((uint32_t)0x00000020)
+
+

Clear Anticipated frame synchronization detection

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CCNRDY   ((uint32_t)0x00000010)
+
+

Clear Codec not ready

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CFREQ   ((uint32_t)0x00000008)
+
+

Clear FIFO request

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CLFSDET   ((uint32_t)0x00000040)
+
+

Clear Late frame synchronization detection

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CMUTEDET   ((uint32_t)0x00000002)
+
+

Clear Mute detection

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_COVRUDR   ((uint32_t)0x00000001)
+
+

Clear Overrun underrun

+ +
+
+ +
+
+ + + + +
#define SAI_xCLRFR_CWCKCFG   ((uint32_t)0x00000004)
+
+

Clear Wrong Clock Configuration

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_CKSTR   ((uint32_t)0x00000200)
+
+

ClocK STRobing edge

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_DMAEN   ((uint32_t)0x00020000)
+
+

DMA enable

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_DS   ((uint32_t)0x000000E0)
+
+

DS[1:0] bits (Data Size)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_DS_0   ((uint32_t)0x00000020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_DS_1   ((uint32_t)0x00000040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_DS_2   ((uint32_t)0x00000080)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_LSBFIRST   ((uint32_t)0x00000100)
+
+

LSB First Configuration

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MCKDIV   ((uint32_t)0x00780000)
+
+

MCKDIV[3:0] (Master ClocK Divider)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MCKDIV_0   ((uint32_t)0x00080000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MCKDIV_1   ((uint32_t)0x00100000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MCKDIV_2   ((uint32_t)0x00200000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MCKDIV_3   ((uint32_t)0x00400000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MODE   ((uint32_t)0x00000003)
+
+

MODE[1:0] bits (Audio Block Mode)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MODE_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MODE_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_MONO   ((uint32_t)0x00001000)
+
+

Mono mode

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_NODIV   ((uint32_t)0x00080000)
+
+

No Divider Configuration

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_OUTDRIV   ((uint32_t)0x00002000)
+
+

Output Drive

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_PRTCFG   ((uint32_t)0x0000000C)
+
+

PRTCFG[1:0] bits (Protocol Configuration)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_PRTCFG_0   ((uint32_t)0x00000004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_PRTCFG_1   ((uint32_t)0x00000008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_SAIEN   ((uint32_t)0x00010000)
+
+

Audio Block enable

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_SYNCEN   ((uint32_t)0x00000C00)
+
+

SYNCEN[1:0](SYNChronization ENable)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_SYNCEN_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR1_SYNCEN_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_COMP   ((uint32_t)0x0000C000)
+
+

COMP[1:0] (Companding mode)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_COMP_0   ((uint32_t)0x00004000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_COMP_1   ((uint32_t)0x00008000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_CPL   ((uint32_t)0x00080000)
+
+

Complement Bit

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_FFLUSH   ((uint32_t)0x00000008)
+
+

Fifo FLUSH

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_FTH   ((uint32_t)0x00000003)
+
+

FTH[1:0](Fifo THreshold)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_FTH_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_FTH_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTE   ((uint32_t)0x00000020)
+
+

Mute mode

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT   ((uint32_t)0x00001F80)
+
+

MUTECNT[5:0] (MUTE counter)

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_0   ((uint32_t)0x00000080)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_1   ((uint32_t)0x00000100)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_2   ((uint32_t)0x00000200)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_3   ((uint32_t)0x00000400)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_4   ((uint32_t)0x00000800)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTECNT_5   ((uint32_t)0x00001000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_MUTEVAL   ((uint32_t)0x00000040)
+
+

Muate value

+ +
+
+ +
+
+ + + + +
#define SAI_xCR2_TRIS   ((uint32_t)0x00000010)
+
+

TRIState Management on data line

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL   ((uint32_t)0x000000FF)
+
+

FRL[1:0](Frame length)

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_5   ((uint32_t)0x00000020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_6   ((uint32_t)0x00000040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FRL_7   ((uint32_t)0x00000080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL   ((uint32_t)0x00007F00)
+
+

FRL[1:0] (Frame synchronization active level length)

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_4   ((uint32_t)0x00001000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_5   ((uint32_t)0x00002000)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSALL_6   ((uint32_t)0x00004000)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSDEF   ((uint32_t)0x00010000)
+
+

Frame Synchronization Definition

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSOFF   ((uint32_t)0x00040000)
+
+

Frame Synchronization OFFset

+ +
+
+ +
+
+ + + + +
#define SAI_xFRCR_FSPO   ((uint32_t)0x00020000)
+
+

Frame Synchronization POLarity

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_AFSDETIE   ((uint32_t)0x00000020)
+
+

Anticipated frame synchronization detection interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_CNRDYIE   ((uint32_t)0x00000010)
+
+

Codec not ready interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_FREQIE   ((uint32_t)0x00000008)
+
+

FIFO request interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_LFSDETIE   ((uint32_t)0x00000040)
+
+

Late frame synchronization detection interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_MUTEDETIE   ((uint32_t)0x00000002)
+
+

Mute detection interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_OVRUDRIE   ((uint32_t)0x00000001)
+
+

Overrun underrun interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xIMR_WCKCFGIE   ((uint32_t)0x00000004)
+
+

Wrong Clock Configuration interrupt enable

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF   ((uint32_t)0x0000001F)
+
+

FRL[4:0](First Bit Offset)

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF_3   ((uint32_t)0x00000008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_FBOFF_4   ((uint32_t)0x00000010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_NBSLOT   ((uint32_t)0x00000F00)
+
+

NBSLOT[3:0] (Number of Slot in audio Frame)

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_NBSLOT_0   ((uint32_t)0x00000100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_NBSLOT_1   ((uint32_t)0x00000200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_NBSLOT_2   ((uint32_t)0x00000400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_NBSLOT_3   ((uint32_t)0x00000800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_SLOTEN   ((uint32_t)0xFFFF0000)
+
+

SLOTEN[15:0] (Slot Enable)

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_SLOTSZ   ((uint32_t)0x000000C0)
+
+

SLOTSZ[1:0] (Slot size)

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_SLOTSZ_0   ((uint32_t)0x00000040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xSLOTR_SLOTSZ_1   ((uint32_t)0x00000080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_AFSDET   ((uint32_t)0x00000020)
+
+

Anticipated frame synchronization detection

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_CNRDY   ((uint32_t)0x00000010)
+
+

Codec not ready

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_FLVL   ((uint32_t)0x00070000)
+
+

FLVL[2:0] (FIFO Level Threshold)

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_FLVL_0   ((uint32_t)0x00010000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_FLVL_1   ((uint32_t)0x00020000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_FLVL_2   ((uint32_t)0x00030000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_FREQ   ((uint32_t)0x00000008)
+
+

FIFO request

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_LFSDET   ((uint32_t)0x00000040)
+
+

Late frame synchronization detection

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_MUTEDET   ((uint32_t)0x00000002)
+
+

Mute detection

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_OVRUDR   ((uint32_t)0x00000001)
+
+

Overrun underrun

+ +
+
+ +
+
+ + + + +
#define SAI_xSR_WCKCFG   ((uint32_t)0x00000004)
+
+

Wrong Clock Configuration

+ +
+
+ +
+
+ + + + +
#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
+
+

Command argument

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
+
+

Clock divider bypass enable bit

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
+
+

Clock divide factor

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
+
+

Clock enable bit

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
+
+

HW Flow Control enable

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
+
+

SDIO_CK dephasing selection bit

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
+
+

Power saving configuration bit

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
+
+

WIDBUS[1:0] bits (Wide bus mode enable bit)

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
+
+

CE-ATA command

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
+
+

Command Index

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
+
+

Command path state machine (CPSM) Enable bit

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
+
+

Enable CMD completion

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_NIEN   ((uint16_t)0x2000)
+
+

Not Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
+
+

SD I/O suspend command

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)
+
+

CPSM Waits for Interrupt Request

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
+
+

CPSM Waits for ends of data transfer (CmdPend internal signal)

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
+
+

WAITRESP[1:0] bits (Wait for response bits)

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
+
+

Data count value

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
+
+

DBLOCKSIZE[3:0] bits (Data block size)

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
+
+

DMA enabled bit

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
+
+

Data transfer direction selection

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
+
+

Data transfer enabled bit

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
+
+

Data transfer mode selection

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
+
+

Read wait mode

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
+
+

Read wait start

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
+
+

Read wait stop

+ +
+
+ +
+
+ + + + +
#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
+
+

SD I/O enable functions

+ +
+
+ +
+
+ + + + +
#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
+
+

Data length value

+ +
+
+ +
+
+ + + + +
#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
+
+

Data timeout period.

+ +
+
+ +
+
+ + + + +
#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
+
+

Receive and transmit FIFO data

+ +
+
+ +
+
+ + + + +
#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
+
+

Remaining number of words to be written to or read from the FIFO

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
+
+

CCRCFAIL flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
+
+

CEATAEND flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
+
+

CMDREND flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
+
+

CMDSENT flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
+
+

CTIMEOUT flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
+
+

DATAEND flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
+
+

DBCKEND flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
+
+

DCRCFAIL flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
+
+

DTIMEOUT flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
+
+

RXOVERR flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
+
+

SDIOIT flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
+
+

STBITERR flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
+
+

TXUNDERR flag clear bit

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
+
+

Command CRC Fail Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
+
+

CE-ATA command completion signal received Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
+
+

CCommand Acting Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
+
+

Command Response Received Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
+
+

Command Sent Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
+
+

Command TimeOut Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
+
+

Data End Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
+
+

Data Block End Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
+
+

Data CRC Fail Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
+
+

Data TimeOut Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
+
+

Data receive acting interrupt enabled

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
+
+

Data available in Rx FIFO interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
+
+

Rx FIFO Empty interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
+
+

Rx FIFO Full interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
+
+

Rx FIFO Half Full interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
+
+

Rx FIFO OverRun Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
+
+

SDIO Mode Interrupt Received interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
+
+

Start Bit Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
+
+

Data Transmit Acting Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
+
+

Data available in Tx FIFO interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
+
+

Tx FIFO Empty interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
+
+

Tx FIFO Full interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
+
+

Tx FIFO Half Empty interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
+
+

Tx FIFO UnderRun Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
+
+

PWRCTRL[1:0] bits (Power supply control bits)

+ +
+
+ +
+
+ + + + +
#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
+
+

Card Status

+ +
+
+ +
+
+ + + + +
#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
+
+

Card Status

+ +
+
+ +
+
+ + + + +
#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
+
+

Card Status

+ +
+
+ +
+
+ + + + +
#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
+
+

Card Status

+ +
+
+ +
+
+ + + + +
#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
+
+

Card Status

+ +
+
+ +
+
+ + + + +
#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
+
+

Response command index

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
+
+

Command response received (CRC check failed)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
+
+

CE-ATA command completion signal received for CMD61

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)
+
+

Command transfer in progress

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)
+
+

Command response received (CRC check passed)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
+
+

Command sent (no response required)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
+
+

Command response timeout

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)
+
+

Data end (data counter, SDIDCOUNT, is zero)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
+
+

Data block sent/received (CRC check passed)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
+
+

Data block sent/received (CRC check failed)

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
+
+

Data timeout

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXACT   ((uint32_t)0x00002000)
+
+

Data receive in progress

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
+
+

Data available in receive FIFO

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
+
+

Receive FIFO empty

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
+
+

Receive FIFO full

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
+
+

Receive FIFO Half Full: there are at least 8 words in the FIFO

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
+
+

Received FIFO overrun error

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
+
+

SDIO interrupt received

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)
+
+

Start bit not detected on all data signals in wide bus mode

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXACT   ((uint32_t)0x00001000)
+
+

Data transmit in progress

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
+
+

Data available in transmit FIFO

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
+
+

Transmit FIFO empty

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
+
+

Transmit FIFO full

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
+
+

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

+ +
+
+ +
+
+ + + + +
#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
+
+

Transmit FIFO underrun error

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
+
+

Bidirectional data mode enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)
+
+

Output enable in bidirectional mode

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BR   ((uint16_t)0x0038)
+
+

BR[2:0] bits (Baud Rate Control)

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BR_0   ((uint16_t)0x0008)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BR_1   ((uint16_t)0x0010)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_BR_2   ((uint16_t)0x0020)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_CPHA   ((uint16_t)0x0001)
+
+

Clock Phase

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_CPOL   ((uint16_t)0x0002)
+
+

Clock Polarity

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_CRCEN   ((uint16_t)0x2000)
+
+

Hardware CRC calculation enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
+
+

Transmit CRC next

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_DFF   ((uint16_t)0x0800)
+
+

Data Frame Format

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
+
+

Frame Format

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_MSTR   ((uint16_t)0x0004)
+
+

Master Selection

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_RXONLY   ((uint16_t)0x0400)
+
+

Receive only

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_SPE   ((uint16_t)0x0040)
+
+

SPI Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_SSI   ((uint16_t)0x0100)
+
+

Internal slave select

+ +
+
+ +
+
+ + + + +
#define SPI_CR1_SSM   ((uint16_t)0x0200)
+
+

Software slave management

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_ERRIE   ((uint8_t)0x20)
+
+

Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)
+
+

Rx Buffer DMA Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_RXNEIE   ((uint8_t)0x40)
+
+

RX buffer Not Empty Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_SSOE   ((uint8_t)0x04)
+
+

SS Output Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)
+
+

Tx Buffer DMA Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CR2_TXEIE   ((uint8_t)0x80)
+
+

Tx buffer Empty Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
+
+

CRC polynomial register

+ +
+
+ +
+
+ + + + +
#define SPI_DR_DR   ((uint16_t)0xFFFF)
+
+

Data Register

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
+
+

Channel length (number of bits per audio channel)

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
+
+

steady state clock polarity

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
+
+

DATLEN[1:0] bits (Data length to be transferred)

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
+
+

I2SCFG[1:0] bits (I2S configuration mode)

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
+
+

I2S Enable

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
+
+

I2S mode selection

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
+
+

I2SSTD[1:0] bits (I2S standard selection)

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
+
+

PCM frame synchronization

+ +
+
+ +
+
+ + + + +
#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
+
+

I2S Linear prescaler

+ +
+
+ +
+
+ + + + +
#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
+
+

Master Clock Output Enable

+ +
+
+ +
+
+ + + + +
#define SPI_I2SPR_ODD   ((uint16_t)0x0100)
+
+

Odd factor for the prescaler

+ +
+
+ +
+
+ + + + +
#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
+
+

Rx CRC Register

+ +
+
+ +
+
+ + + + +
#define SPI_SR_BSY   ((uint8_t)0x80)
+
+

Busy flag

+ +
+
+ +
+
+ + + + +
#define SPI_SR_CHSIDE   ((uint8_t)0x04)
+
+

Channel side

+ +
+
+ +
+
+ + + + +
#define SPI_SR_CRCERR   ((uint8_t)0x10)
+
+

CRC Error flag

+ +
+
+ +
+
+ + + + +
#define SPI_SR_MODF   ((uint8_t)0x20)
+
+

Mode fault

+ +
+
+ +
+
+ + + + +
#define SPI_SR_OVR   ((uint8_t)0x40)
+
+

Overrun flag

+ +
+
+ +
+
+ + + + +
#define SPI_SR_RXNE   ((uint8_t)0x01)
+
+

Receive buffer Not Empty

+ +
+
+ +
+
+ + + + +
#define SPI_SR_TXE   ((uint8_t)0x02)
+
+

Transmit buffer Empty

+ +
+
+ +
+
+ + + + +
#define SPI_SR_UDR   ((uint8_t)0x08)
+
+

Underrun flag

+ +
+
+ +
+
+ + + + +
#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
+
+

Tx CRC Register

+ +
+
+ +
+
+ + + + +
#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
+
+

Compensation cell ready flag

+ +
+
+ +
+
+ + + + +
#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
+
+

Compensation cell power-down

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
+
+

EXTI 0 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
+
+ +

EXTI0 configuration.

+

PA[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
+
+

PB[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
+
+

PC[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
+
+

PD[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
+
+

PE[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
+
+

PF[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
+
+

PG[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
+
+

PH[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
+
+

PI[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PJ   ((uint16_t)0x0009)
+
+

PJ[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI0_PK   ((uint16_t)0x000A)
+
+

PK[0] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
+
+

EXTI 1 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
+
+ +

EXTI1 configuration.

+

PA[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
+
+

PB[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
+
+

PC[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
+
+

PD[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
+
+

PE[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
+
+

PF[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
+
+

PG[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
+
+

PH[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
+
+

PI[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PJ   ((uint16_t)0x0090)
+
+

PJ[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI1_PK   ((uint16_t)0x00A0)
+
+

PK[1] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
+
+

EXTI 2 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
+
+ +

EXTI2 configuration.

+

PA[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
+
+

PB[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
+
+

PC[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
+
+

PD[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
+
+

PE[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
+
+

PF[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
+
+

PG[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
+
+

PH[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
+
+

PI[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PJ   ((uint16_t)0x0900)
+
+

PJ[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI2_PK   ((uint16_t)0x0A00)
+
+

PK[2] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
+
+

EXTI 3 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
+
+ +

EXTI3 configuration.

+

PA[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
+
+

PB[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
+
+

PC[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
+
+

PD[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
+
+

PE[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
+
+

PF[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
+
+

PG[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
+
+

PH[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
+
+

PI[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PJ   ((uint16_t)0x9000)
+
+

PJ[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR1_EXTI3_PK   ((uint16_t)0xA000)
+
+

PK[3] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
+
+

EXTI 4 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
+
+ +

EXTI4 configuration.

+

PA[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
+
+

PB[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
+
+

PC[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
+
+

PD[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
+
+

PE[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
+
+

PF[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
+
+

PG[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
+
+

PH[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
+
+

PI[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PJ   ((uint16_t)0x0009)
+
+

PJ[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI4_PK   ((uint16_t)0x000A)
+
+

PK[4] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
+
+

EXTI 5 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
+
+ +

EXTI5 configuration.

+

PA[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
+
+

PB[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
+
+

PC[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
+
+

PD[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
+
+

PE[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
+
+

PF[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
+
+

PG[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
+
+

PH[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
+
+

PI[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PJ   ((uint16_t)0x0090)
+
+

PJ[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI5_PK   ((uint16_t)0x00A0)
+
+

PK[5] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
+
+

EXTI 6 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
+
+ +

EXTI6 configuration.

+

PA[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
+
+

PB[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
+
+

PC[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
+
+

PD[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
+
+

PE[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
+
+

PF[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
+
+

PG[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
+
+

PH[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
+
+

PI[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PJ   ((uint16_t)0x0900)
+
+

PJ[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI6_PK   ((uint16_t)0x0A00)
+
+

PK[6] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
+
+

EXTI 7 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
+
+ +

EXTI7 configuration.

+

PA[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
+
+

PB[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
+
+

PC[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
+
+

PD[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
+
+

PE[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
+
+

PF[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
+
+

PG[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
+
+

PH[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
+
+

PI[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PJ   ((uint16_t)0x9000)
+
+

PJ[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR2_EXTI7_PK   ((uint16_t)0xA000)
+
+

PK[7] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
+
+

EXTI 10 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
+
+ +

EXTI10 configuration.

+

PA[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
+
+

PB[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
+
+

PC[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
+
+

PD[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
+
+

PE[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
+
+

PF[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
+
+

PG[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
+
+

PH[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
+
+

PI[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI10_PJ   ((uint16_t)0x0900)
+
+

PJ[10] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
+
+

EXTI 11 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
+
+ +

EXTI11 configuration.

+

PA[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
+
+

PB[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
+
+

PC[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
+
+

PD[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
+
+

PE[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
+
+

PF[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
+
+

PG[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
+
+

PH[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
+
+

PI[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI11_PJ   ((uint16_t)0x9000)
+
+

PJ[11] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
+
+

EXTI 8 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
+
+ +

EXTI8 configuration.

+

PA[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
+
+

PB[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
+
+

PC[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
+
+

PD[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
+
+

PE[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
+
+

PF[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
+
+

PG[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
+
+

PH[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
+
+

PI[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI8_PJ   ((uint16_t)0x0009)
+
+

PJ[8] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
+
+

EXTI 9 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
+
+ +

EXTI9 configuration.

+

PA[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
+
+

PB[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
+
+

PC[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
+
+

PD[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
+
+

PE[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
+
+

PF[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
+
+

PG[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
+
+

PH[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
+
+

PI[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR3_EXTI9_PJ   ((uint16_t)0x0090)
+
+

PJ[9] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
+
+

EXTI 12 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
+
+ +

EXTI12 configuration.

+

PA[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
+
+

PB[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
+
+

PC[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
+
+

PD[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
+
+

PE[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
+
+

PF[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
+
+

PG[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PH   ((uint16_t)0x0007)
+
+

PH[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PI   ((uint16_t)0x0008)
+
+

PI[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI12_PJ   ((uint16_t)0x0009)
+
+

PJ[12] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
+
+

EXTI 13 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
+
+ +

EXTI13 configuration.

+

PA[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
+
+

PB[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
+
+

PC[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
+
+

PD[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
+
+

PE[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
+
+

PF[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
+
+

PG[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PH   ((uint16_t)0x0070)
+
+

PH[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PI   ((uint16_t)0x0008)
+
+

PI[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI13_PJ   ((uint16_t)0x0009)
+
+

PJ[13] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
+
+

EXTI 14 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
+
+ +

EXTI14 configuration.

+

PA[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
+
+

PB[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
+
+

PC[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
+
+

PD[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
+
+

PE[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
+
+

PF[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
+
+

PG[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PH   ((uint16_t)0x0700)
+
+

PH[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PI   ((uint16_t)0x0800)
+
+

PI[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI14_PJ   ((uint16_t)0x0900)
+
+

PJ[14] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
+
+

EXTI 15 configuration

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
+
+ +

EXTI15 configuration.

+

PA[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
+
+

PB[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
+
+

PC[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
+
+

PD[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
+
+

PE[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
+
+

PF[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
+
+

PG[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PH   ((uint16_t)0x7000)
+
+

PH[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PI   ((uint16_t)0x8000)
+
+

PI[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_EXTICR4_EXTI15_PJ   ((uint16_t)0x9000)
+
+

PJ[15] pin

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_FB_MODE   ((uint32_t)0x00000100)
+
+

User Flash Bank mode

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000007)
+
+

SYSCFG_Memory Remap Config

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_MEM_MODE_2   ((uint32_t)0x00000004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_SWP_FMC   ((uint32_t)0x00000C00)
+
+

FMC memory mapping swap

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_SWP_FMC_0   ((uint32_t)0x00000400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define SYSCFG_MEMRMP_SWP_FMC_1   ((uint32_t)0x00000800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define SYSCFG_PMC_ADC1DC2   ((uint32_t)0x00010000)
+
+

Refer to AN4073 on how to use this bit

+ +
+
+ +
+
+ + + + +
#define SYSCFG_PMC_ADC2DC2   ((uint32_t)0x00020000)
+
+

Refer to AN4073 on how to use this bit

+ +
+
+ +
+
+ + + + +
#define SYSCFG_PMC_ADC3DC2   ((uint32_t)0x00040000)
+
+

Refer to AN4073 on how to use this bit

+ +
+
+ +
+
+ + + + +
#define SYSCFG_PMC_ADCxDC2   ((uint32_t)0x00070000)
+
+

Refer to AN4073 on how to use this bit

+ +
+
+ +
+
+ + + + +
#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)
+
+

Ethernet PHY interface selection

+ +
+
+ +
+
+ + + + +
#define TIM_ARR_ARR   ((uint16_t)0xFFFF)
+
+

actual auto-reload Value

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_AOE   ((uint16_t)0x4000)
+
+

Automatic Output enable

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_BKE   ((uint16_t)0x1000)
+
+

Break enable

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_BKP   ((uint16_t)0x2000)
+
+

Break Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG   ((uint16_t)0x00FF)
+
+

DTG[0:7] bits (Dead-Time Generator set-up)

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_LOCK   ((uint16_t)0x0300)
+
+

LOCK[1:0] bits (Lock Configuration)

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_MOE   ((uint16_t)0x8000)
+
+

Main Output enable

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_OSSI   ((uint16_t)0x0400)
+
+

Off-State Selection for Idle mode

+ +
+
+ +
+
+ + + + +
#define TIM_BDTR_OSSR   ((uint16_t)0x0800)
+
+

Off-State Selection for Run mode

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC1E   ((uint16_t)0x0001)
+
+

Capture/Compare 1 output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC1NE   ((uint16_t)0x0004)
+
+

Capture/Compare 1 Complementary output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC1NP   ((uint16_t)0x0008)
+
+

Capture/Compare 1 Complementary output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC1P   ((uint16_t)0x0002)
+
+

Capture/Compare 1 output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC2E   ((uint16_t)0x0010)
+
+

Capture/Compare 2 output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC2NE   ((uint16_t)0x0040)
+
+

Capture/Compare 2 Complementary output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC2NP   ((uint16_t)0x0080)
+
+

Capture/Compare 2 Complementary output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC2P   ((uint16_t)0x0020)
+
+

Capture/Compare 2 output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC3E   ((uint16_t)0x0100)
+
+

Capture/Compare 3 output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC3NE   ((uint16_t)0x0400)
+
+

Capture/Compare 3 Complementary output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC3NP   ((uint16_t)0x0800)
+
+

Capture/Compare 3 Complementary output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC3P   ((uint16_t)0x0200)
+
+

Capture/Compare 3 output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC4E   ((uint16_t)0x1000)
+
+

Capture/Compare 4 output enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC4NP   ((uint16_t)0x8000)
+
+

Capture/Compare 4 Complementary output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCER_CC4P   ((uint16_t)0x2000)
+
+

Capture/Compare 4 output Polarity

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)
+
+

CC1S[1:0] bits (Capture/Compare 1 Selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)
+
+

CC2S[1:0] bits (Capture/Compare 2 Selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
+
+

IC1F[3:0] bits (Input Capture 1 Filter)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
+
+

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)
+
+

IC2F[3:0] bits (Input Capture 2 Filter)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
+
+

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
+
+

Output Compare 1Clear Enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
+
+

Output Compare 1 Fast enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)
+
+

OC1M[2:0] bits (Output Compare 1 Mode)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
+
+

Output Compare 1 Preload enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
+
+

Output Compare 2 Clear Enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
+
+

Output Compare 2 Fast enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)
+
+

OC2M[2:0] bits (Output Compare 2 Mode)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
+
+

Output Compare 2 Preload enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)
+
+

CC3S[1:0] bits (Capture/Compare 3 Selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)
+
+

CC4S[1:0] bits (Capture/Compare 4 Selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
+
+

IC3F[3:0] bits (Input Capture 3 Filter)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
+
+

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)
+
+

IC4F[3:0] bits (Input Capture 4 Filter)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
+
+

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
+
+

Output Compare 3 Clear Enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
+
+

Output Compare 3 Fast enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)
+
+

OC3M[2:0] bits (Output Compare 3 Mode)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
+
+

Output Compare 3 Preload enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
+
+

Output Compare 4 Clear Enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
+
+

Output Compare 4 Fast enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)
+
+

OC4M[2:0] bits (Output Compare 4 Mode)

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
+
+

Output Compare 4 Preload enable

+ +
+
+ +
+
+ + + + +
#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
+
+

Capture/Compare 1 Value

+ +
+
+ +
+
+ + + + +
#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
+
+

Capture/Compare 2 Value

+ +
+
+ +
+
+ + + + +
#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
+
+

Capture/Compare 3 Value

+ +
+
+ +
+
+ + + + +
#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
+
+

Capture/Compare 4 Value

+ +
+
+ +
+
+ + + + +
#define TIM_CNT_CNT   ((uint16_t)0xFFFF)
+
+

Counter Value

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_ARPE   ((uint16_t)0x0080)
+
+

Auto-reload preload enable

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CEN   ((uint16_t)0x0001)
+
+

Counter enable

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CKD   ((uint16_t)0x0300)
+
+

CKD[1:0] bits (clock division)

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CKD_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CKD_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CMS   ((uint16_t)0x0060)
+
+

CMS[1:0] bits (Center-aligned mode selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CMS_0   ((uint16_t)0x0020)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_CMS_1   ((uint16_t)0x0040)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_DIR   ((uint16_t)0x0010)
+
+

Direction

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_OPM   ((uint16_t)0x0008)
+
+

One pulse mode

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_UDIS   ((uint16_t)0x0002)
+
+

Update disable

+ +
+
+ +
+
+ + + + +
#define TIM_CR1_URS   ((uint16_t)0x0004)
+
+

Update request source

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_CCDS   ((uint16_t)0x0008)
+
+

Capture/Compare DMA Selection

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_CCPC   ((uint16_t)0x0001)
+
+

Capture/Compare Preloaded Control

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_CCUS   ((uint16_t)0x0004)
+
+

Capture/Compare Control Update Selection

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_MMS   ((uint16_t)0x0070)
+
+

MMS[2:0] bits (Master Mode Selection)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_MMS_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_MMS_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_MMS_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS1   ((uint16_t)0x0100)
+
+

Output Idle state 1 (OC1 output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS1N   ((uint16_t)0x0200)
+
+

Output Idle state 1 (OC1N output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS2   ((uint16_t)0x0400)
+
+

Output Idle state 2 (OC2 output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS2N   ((uint16_t)0x0800)
+
+

Output Idle state 2 (OC2N output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS3   ((uint16_t)0x1000)
+
+

Output Idle state 3 (OC3 output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS3N   ((uint16_t)0x2000)
+
+

Output Idle state 3 (OC3N output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_OIS4   ((uint16_t)0x4000)
+
+

Output Idle state 4 (OC4 output)

+ +
+
+ +
+
+ + + + +
#define TIM_CR2_TI1S   ((uint16_t)0x0080)
+
+

TI1 Selection

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA   ((uint16_t)0x001F)
+
+

DBA[4:0] bits (DMA Base Address)

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA_2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA_3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBA_4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL   ((uint16_t)0x1F00)
+
+

DBL[4:0] bits (DMA Burst Length)

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL_2   ((uint16_t)0x0400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL_3   ((uint16_t)0x0800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_DCR_DBL_4   ((uint16_t)0x1000)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_BIE   ((uint16_t)0x0080)
+
+

Break interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC1DE   ((uint16_t)0x0200)
+
+

Capture/Compare 1 DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC1IE   ((uint16_t)0x0002)
+
+

Capture/Compare 1 interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC2DE   ((uint16_t)0x0400)
+
+

Capture/Compare 2 DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC2IE   ((uint16_t)0x0004)
+
+

Capture/Compare 2 interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC3DE   ((uint16_t)0x0800)
+
+

Capture/Compare 3 DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC3IE   ((uint16_t)0x0008)
+
+

Capture/Compare 3 interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC4DE   ((uint16_t)0x1000)
+
+

Capture/Compare 4 DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_CC4IE   ((uint16_t)0x0010)
+
+

Capture/Compare 4 interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_COMDE   ((uint16_t)0x2000)
+
+

COM DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_COMIE   ((uint16_t)0x0020)
+
+

COM interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_TDE   ((uint16_t)0x4000)
+
+

Trigger DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_TIE   ((uint16_t)0x0040)
+
+

Trigger interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_UDE   ((uint16_t)0x0100)
+
+

Update DMA request enable

+ +
+
+ +
+
+ + + + +
#define TIM_DIER_UIE   ((uint16_t)0x0001)
+
+

Update interrupt enable

+ +
+
+ +
+
+ + + + +
#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
+
+

DMA register for burst accesses

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_BG   ((uint8_t)0x80)
+
+

Break Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_CC1G   ((uint8_t)0x02)
+
+

Capture/Compare 1 Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_CC2G   ((uint8_t)0x04)
+
+

Capture/Compare 2 Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_CC3G   ((uint8_t)0x08)
+
+

Capture/Compare 3 Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_CC4G   ((uint8_t)0x10)
+
+

Capture/Compare 4 Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_COMG   ((uint8_t)0x20)
+
+

Capture/Compare Control Update Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_TG   ((uint8_t)0x40)
+
+

Trigger Generation

+ +
+
+ +
+
+ + + + +
#define TIM_EGR_UG   ((uint8_t)0x01)
+
+

Update Generation

+ +
+
+ +
+
+ + + + +
#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
+
+

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

+ +
+
+ +
+
+ + + + +
#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
+
+

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

+ +
+
+ +
+
+ + + + +
#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_PSC_PSC   ((uint16_t)0xFFFF)
+
+

Prescaler Value

+ +
+
+ +
+
+ + + + +
#define TIM_RCR_REP   ((uint8_t)0xFF)
+
+

Repetition Counter Value

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ECE   ((uint16_t)0x4000)
+
+

External clock enable

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETF   ((uint16_t)0x0F00)
+
+

ETF[3:0] bits (External trigger filter)

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETP   ((uint16_t)0x8000)
+
+

External trigger polarity

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETPS   ((uint16_t)0x3000)
+
+

ETPS[1:0] bits (External trigger prescaler)

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_MSM   ((uint16_t)0x0080)
+
+

Master/slave mode

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_SMS   ((uint16_t)0x0007)
+
+

SMS[2:0] bits (Slave mode selection)

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_TS   ((uint16_t)0x0070)
+
+

TS[2:0] bits (Trigger selection)

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_TS_0   ((uint16_t)0x0010)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_TS_1   ((uint16_t)0x0020)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define TIM_SMCR_TS_2   ((uint16_t)0x0040)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define TIM_SR_BIF   ((uint16_t)0x0080)
+
+

Break interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC1IF   ((uint16_t)0x0002)
+
+

Capture/Compare 1 interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC1OF   ((uint16_t)0x0200)
+
+

Capture/Compare 1 Overcapture Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC2IF   ((uint16_t)0x0004)
+
+

Capture/Compare 2 interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC2OF   ((uint16_t)0x0400)
+
+

Capture/Compare 2 Overcapture Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC3IF   ((uint16_t)0x0008)
+
+

Capture/Compare 3 interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC3OF   ((uint16_t)0x0800)
+
+

Capture/Compare 3 Overcapture Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC4IF   ((uint16_t)0x0010)
+
+

Capture/Compare 4 interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_CC4OF   ((uint16_t)0x1000)
+
+

Capture/Compare 4 Overcapture Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_COMIF   ((uint16_t)0x0020)
+
+

COM interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_TIF   ((uint16_t)0x0040)
+
+

Trigger interrupt Flag

+ +
+
+ +
+
+ + + + +
#define TIM_SR_UIF   ((uint16_t)0x0001)
+
+

Update interrupt Flag

+ +
+
+ +
+
+ + + + +
#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
+
+

Fraction of USARTDIV

+ +
+
+ +
+
+ + + + +
#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
+
+

Mantissa of USARTDIV

+ +
+
+ +
+
+ + + + +
#define USART_CR1_IDLEIE   ((uint16_t)0x0010)
+
+

IDLE Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_M   ((uint16_t)0x1000)
+
+

Word length

+ +
+
+ +
+
+ + + + +
#define USART_CR1_OVER8   ((uint16_t)0x8000)
+
+

USART Oversampling by 8 enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_PCE   ((uint16_t)0x0400)
+
+

Parity Control Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_PEIE   ((uint16_t)0x0100)
+
+

PE Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_PS   ((uint16_t)0x0200)
+
+

Parity Selection

+ +
+
+ +
+
+ + + + +
#define USART_CR1_RE   ((uint16_t)0x0004)
+
+

Receiver Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_RWU   ((uint16_t)0x0002)
+
+

Receiver wakeup

+ +
+
+ +
+
+ + + + +
#define USART_CR1_RXNEIE   ((uint16_t)0x0020)
+
+

RXNE Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_SBK   ((uint16_t)0x0001)
+
+

Send Break

+ +
+
+ +
+
+ + + + +
#define USART_CR1_TCIE   ((uint16_t)0x0040)
+
+

Transmission Complete Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_TE   ((uint16_t)0x0008)
+
+

Transmitter Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_TXEIE   ((uint16_t)0x0080)
+
+

PE Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_UE   ((uint16_t)0x2000)
+
+

USART Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR1_WAKE   ((uint16_t)0x0800)
+
+

Wakeup method

+ +
+
+ +
+
+ + + + +
#define USART_CR2_ADD   ((uint16_t)0x000F)
+
+

Address of the USART node

+ +
+
+ +
+
+ + + + +
#define USART_CR2_CLKEN   ((uint16_t)0x0800)
+
+

Clock Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR2_CPHA   ((uint16_t)0x0200)
+
+

Clock Phase

+ +
+
+ +
+
+ + + + +
#define USART_CR2_CPOL   ((uint16_t)0x0400)
+
+

Clock Polarity

+ +
+
+ +
+
+ + + + +
#define USART_CR2_LBCL   ((uint16_t)0x0100)
+
+

Last Bit Clock pulse

+ +
+
+ +
+
+ + + + +
#define USART_CR2_LBDIE   ((uint16_t)0x0040)
+
+

LIN Break Detection Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR2_LBDL   ((uint16_t)0x0020)
+
+

LIN Break Detection Length

+ +
+
+ +
+
+ + + + +
#define USART_CR2_LINEN   ((uint16_t)0x4000)
+
+

LIN mode enable

+ +
+
+ +
+
+ + + + +
#define USART_CR2_STOP   ((uint16_t)0x3000)
+
+

STOP[1:0] bits (STOP bits)

+ +
+
+ +
+
+ + + + +
#define USART_CR2_STOP_0   ((uint16_t)0x1000)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define USART_CR2_STOP_1   ((uint16_t)0x2000)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define USART_CR3_CTSE   ((uint16_t)0x0200)
+
+

CTS Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_CTSIE   ((uint16_t)0x0400)
+
+

CTS Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_DMAR   ((uint16_t)0x0040)
+
+

DMA Enable Receiver

+ +
+
+ +
+
+ + + + +
#define USART_CR3_DMAT   ((uint16_t)0x0080)
+
+

DMA Enable Transmitter

+ +
+
+ +
+
+ + + + +
#define USART_CR3_EIE   ((uint16_t)0x0001)
+
+

Error Interrupt Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_HDSEL   ((uint16_t)0x0008)
+
+

Half-Duplex Selection

+ +
+
+ +
+
+ + + + +
#define USART_CR3_IREN   ((uint16_t)0x0002)
+
+

IrDA mode Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_IRLP   ((uint16_t)0x0004)
+
+

IrDA Low-Power

+ +
+
+ +
+
+ + + + +
#define USART_CR3_NACK   ((uint16_t)0x0010)
+
+

Smartcard NACK enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_ONEBIT   ((uint16_t)0x0800)
+
+

USART One bit method enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_RTSE   ((uint16_t)0x0100)
+
+

RTS Enable

+ +
+
+ +
+
+ + + + +
#define USART_CR3_SCEN   ((uint16_t)0x0020)
+
+

Smartcard mode enable

+ +
+
+ +
+
+ + + + +
#define USART_DR_DR   ((uint16_t)0x01FF)
+
+

Data value

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_GT   ((uint16_t)0xFF00)
+
+

Guard time value

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC   ((uint16_t)0x00FF)
+
+

PSC[7:0] bits (Prescaler value)

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_5   ((uint16_t)0x0020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_6   ((uint16_t)0x0040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define USART_GTPR_PSC_7   ((uint16_t)0x0080)
+
+

Bit 7

+ +
+
+ +
+
+ + + + +
#define USART_SR_CTS   ((uint16_t)0x0200)
+
+

CTS Flag

+ +
+
+ +
+
+ + + + +
#define USART_SR_FE   ((uint16_t)0x0002)
+
+

Framing Error

+ +
+
+ +
+
+ + + + +
#define USART_SR_IDLE   ((uint16_t)0x0010)
+
+

IDLE line detected

+ +
+
+ +
+
+ + + + +
#define USART_SR_LBD   ((uint16_t)0x0100)
+
+

LIN Break Detection Flag

+ +
+
+ +
+
+ + + + +
#define USART_SR_NE   ((uint16_t)0x0004)
+
+

Noise Error Flag

+ +
+
+ +
+
+ + + + +
#define USART_SR_ORE   ((uint16_t)0x0008)
+
+

OverRun Error

+ +
+
+ +
+
+ + + + +
#define USART_SR_PE   ((uint16_t)0x0001)
+
+

Parity Error

+ +
+
+ +
+
+ + + + +
#define USART_SR_RXNE   ((uint16_t)0x0020)
+
+

Read Data Register Not Empty

+ +
+
+ +
+
+ + + + +
#define USART_SR_TC   ((uint16_t)0x0040)
+
+

Transmission Complete

+ +
+
+ +
+
+ + + + +
#define USART_SR_TXE   ((uint16_t)0x0080)
+
+

Transmit Data Register Empty

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_EWI   ((uint16_t)0x0200)
+
+

Early Wakeup Interrupt

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W   ((uint16_t)0x007F)
+
+

W[6:0] bits (7-bit window value)

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W0   ((uint16_t)0x0001)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W1   ((uint16_t)0x0002)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W2   ((uint16_t)0x0004)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W3   ((uint16_t)0x0008)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W4   ((uint16_t)0x0010)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W5   ((uint16_t)0x0020)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_W6   ((uint16_t)0x0040)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)
+
+

WDGTB[1:0] bits (Timer Base)

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T   ((uint8_t)0x7F)
+
+

T[6:0] bits (7-Bit counter (MSB to LSB))

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T0   ((uint8_t)0x01)
+
+

Bit 0

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T1   ((uint8_t)0x02)
+
+

Bit 1

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T2   ((uint8_t)0x04)
+
+

Bit 2

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T3   ((uint8_t)0x08)
+
+

Bit 3

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T4   ((uint8_t)0x10)
+
+

Bit 4

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T5   ((uint8_t)0x20)
+
+

Bit 5

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_T6   ((uint8_t)0x40)
+
+

Bit 6

+ +
+
+ +
+
+ + + + +
#define WWDG_CR_WDGA   ((uint8_t)0x80)
+
+

Activation bit

+ +
+
+ +
+
+ + + + +
#define WWDG_SR_EWIF   ((uint8_t)0x01)
+
+

Early Wakeup Interrupt Flag

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___peripheral___registers___bits___definition.map b/group___peripheral___registers___bits___definition.map new file mode 100644 index 0000000..a2f3a46 --- /dev/null +++ b/group___peripheral___registers___bits___definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___peripheral___registers___bits___definition.md5 b/group___peripheral___registers___bits___definition.md5 new file mode 100644 index 0000000..f92a484 --- /dev/null +++ b/group___peripheral___registers___bits___definition.md5 @@ -0,0 +1 @@ +9cccf9d9123881c317be82bd0b02fd1b \ No newline at end of file diff --git a/group___peripheral___registers___bits___definition.png b/group___peripheral___registers___bits___definition.png new file mode 100644 index 0000000..064dfa3 Binary files /dev/null and b/group___peripheral___registers___bits___definition.png differ diff --git a/group___peripheral__declaration.html b/group___peripheral__declaration.html new file mode 100644 index 0000000..19c2913 --- /dev/null +++ b/group___peripheral__declaration.html @@ -0,0 +1,400 @@ + + + + + + +discoverpixy: Peripheral_declaration + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Peripheral_declaration
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Peripheral_declaration:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM2   ((TIM_TypeDef *) TIM2_BASE)
 
+#define TIM3   ((TIM_TypeDef *) TIM3_BASE)
 
+#define TIM4   ((TIM_TypeDef *) TIM4_BASE)
 
+#define TIM5   ((TIM_TypeDef *) TIM5_BASE)
 
+#define TIM6   ((TIM_TypeDef *) TIM6_BASE)
 
+#define TIM7   ((TIM_TypeDef *) TIM7_BASE)
 
+#define TIM12   ((TIM_TypeDef *) TIM12_BASE)
 
+#define TIM13   ((TIM_TypeDef *) TIM13_BASE)
 
+#define TIM14   ((TIM_TypeDef *) TIM14_BASE)
 
+#define RTC   ((RTC_TypeDef *) RTC_BASE)
 
+#define WWDG   ((WWDG_TypeDef *) WWDG_BASE)
 
+#define IWDG   ((IWDG_TypeDef *) IWDG_BASE)
 
+#define I2S2ext   ((SPI_TypeDef *) I2S2ext_BASE)
 
+#define SPI2   ((SPI_TypeDef *) SPI2_BASE)
 
+#define SPI3   ((SPI_TypeDef *) SPI3_BASE)
 
+#define I2S3ext   ((SPI_TypeDef *) I2S3ext_BASE)
 
+#define USART2   ((USART_TypeDef *) USART2_BASE)
 
+#define USART3   ((USART_TypeDef *) USART3_BASE)
 
+#define UART4   ((USART_TypeDef *) UART4_BASE)
 
+#define UART5   ((USART_TypeDef *) UART5_BASE)
 
+#define I2C1   ((I2C_TypeDef *) I2C1_BASE)
 
+#define I2C2   ((I2C_TypeDef *) I2C2_BASE)
 
+#define I2C3   ((I2C_TypeDef *) I2C3_BASE)
 
+#define CAN1   ((CAN_TypeDef *) CAN1_BASE)
 
+#define CAN2   ((CAN_TypeDef *) CAN2_BASE)
 
+#define PWR   ((PWR_TypeDef *) PWR_BASE)
 
+#define DAC   ((DAC_TypeDef *) DAC_BASE)
 
+#define UART7   ((USART_TypeDef *) UART7_BASE)
 
+#define UART8   ((USART_TypeDef *) UART8_BASE)
 
+#define TIM1   ((TIM_TypeDef *) TIM1_BASE)
 
+#define TIM8   ((TIM_TypeDef *) TIM8_BASE)
 
+#define USART1   ((USART_TypeDef *) USART1_BASE)
 
+#define USART6   ((USART_TypeDef *) USART6_BASE)
 
+#define ADC   ((ADC_Common_TypeDef *) ADC_BASE)
 
+#define ADC1   ((ADC_TypeDef *) ADC1_BASE)
 
+#define ADC2   ((ADC_TypeDef *) ADC2_BASE)
 
+#define ADC3   ((ADC_TypeDef *) ADC3_BASE)
 
+#define SDIO   ((SDIO_TypeDef *) SDIO_BASE)
 
+#define SPI1   ((SPI_TypeDef *) SPI1_BASE)
 
+#define SPI4   ((SPI_TypeDef *) SPI4_BASE)
 
+#define SYSCFG   ((SYSCFG_TypeDef *) SYSCFG_BASE)
 
+#define EXTI   ((EXTI_TypeDef *) EXTI_BASE)
 
+#define TIM9   ((TIM_TypeDef *) TIM9_BASE)
 
+#define TIM10   ((TIM_TypeDef *) TIM10_BASE)
 
+#define TIM11   ((TIM_TypeDef *) TIM11_BASE)
 
+#define SPI5   ((SPI_TypeDef *) SPI5_BASE)
 
+#define SPI6   ((SPI_TypeDef *) SPI6_BASE)
 
+#define SAI1   ((SAI_TypeDef *) SAI1_BASE)
 
+#define SAI1_Block_A   ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
 
+#define SAI1_Block_B   ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
 
+#define LTDC   ((LTDC_TypeDef *)LTDC_BASE)
 
+#define LTDC_Layer1   ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
 
+#define LTDC_Layer2   ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
 
+#define GPIOA   ((GPIO_TypeDef *) GPIOA_BASE)
 
+#define GPIOB   ((GPIO_TypeDef *) GPIOB_BASE)
 
+#define GPIOC   ((GPIO_TypeDef *) GPIOC_BASE)
 
+#define GPIOD   ((GPIO_TypeDef *) GPIOD_BASE)
 
+#define GPIOE   ((GPIO_TypeDef *) GPIOE_BASE)
 
+#define GPIOF   ((GPIO_TypeDef *) GPIOF_BASE)
 
+#define GPIOG   ((GPIO_TypeDef *) GPIOG_BASE)
 
+#define GPIOH   ((GPIO_TypeDef *) GPIOH_BASE)
 
+#define GPIOI   ((GPIO_TypeDef *) GPIOI_BASE)
 
+#define GPIOJ   ((GPIO_TypeDef *) GPIOJ_BASE)
 
+#define GPIOK   ((GPIO_TypeDef *) GPIOK_BASE)
 
+#define CRC   ((CRC_TypeDef *) CRC_BASE)
 
+#define RCC   ((RCC_TypeDef *) RCC_BASE)
 
+#define FLASH   ((FLASH_TypeDef *) FLASH_R_BASE)
 
+#define DMA1   ((DMA_TypeDef *) DMA1_BASE)
 
+#define DMA1_Stream0   ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
 
+#define DMA1_Stream1   ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
 
+#define DMA1_Stream2   ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
 
+#define DMA1_Stream3   ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
 
+#define DMA1_Stream4   ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
 
+#define DMA1_Stream5   ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
 
+#define DMA1_Stream6   ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
 
+#define DMA1_Stream7   ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
 
+#define DMA2   ((DMA_TypeDef *) DMA2_BASE)
 
+#define DMA2_Stream0   ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
 
+#define DMA2_Stream1   ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
 
+#define DMA2_Stream2   ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
 
+#define DMA2_Stream3   ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
 
+#define DMA2_Stream4   ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
 
+#define DMA2_Stream5   ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
 
+#define DMA2_Stream6   ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
 
+#define DMA2_Stream7   ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
 
+#define ETH   ((ETH_TypeDef *) ETH_BASE)
 
+#define DMA2D   ((DMA2D_TypeDef *)DMA2D_BASE)
 
+#define DCMI   ((DCMI_TypeDef *) DCMI_BASE)
 
+#define CRYP   ((CRYP_TypeDef *) CRYP_BASE)
 
+#define HASH   ((HASH_TypeDef *) HASH_BASE)
 
+#define HASH_DIGEST   ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
 
+#define RNG   ((RNG_TypeDef *) RNG_BASE)
 
+#define FSMC_Bank1   ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
 
+#define FSMC_Bank1E   ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
 
+#define FSMC_Bank2   ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
 
+#define FSMC_Bank3   ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
 
+#define FSMC_Bank4   ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
 
+#define DBGMCU   ((DBGMCU_TypeDef *) DBGMCU_BASE)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___peripheral__declaration.map b/group___peripheral__declaration.map new file mode 100644 index 0000000..fbe96ec --- /dev/null +++ b/group___peripheral__declaration.map @@ -0,0 +1,3 @@ + + + diff --git a/group___peripheral__declaration.md5 b/group___peripheral__declaration.md5 new file mode 100644 index 0000000..764d18f --- /dev/null +++ b/group___peripheral__declaration.md5 @@ -0,0 +1 @@ +c26b5675d60c4329a5288198543813e4 \ No newline at end of file diff --git a/group___peripheral__declaration.png b/group___peripheral__declaration.png new file mode 100644 index 0000000..ee5c003 Binary files /dev/null and b/group___peripheral__declaration.png differ diff --git a/group___peripheral__memory__map.html b/group___peripheral__memory__map.html new file mode 100644 index 0000000..89e8579 --- /dev/null +++ b/group___peripheral__memory__map.html @@ -0,0 +1,713 @@ + + + + + + +discoverpixy: Peripheral_memory_map + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Peripheral_memory_map
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Peripheral_memory_map:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define FLASH_BASE   ((uint32_t)0x08000000)
 
#define CCMDATARAM_BASE   ((uint32_t)0x10000000)
 
#define SRAM1_BASE   ((uint32_t)0x20000000)
 
#define SRAM2_BASE   ((uint32_t)0x2001C000)
 
#define SRAM3_BASE   ((uint32_t)0x20020000)
 
#define PERIPH_BASE   ((uint32_t)0x40000000)
 
#define BKPSRAM_BASE   ((uint32_t)0x40024000)
 
#define FSMC_R_BASE   ((uint32_t)0xA0000000)
 
#define CCMDATARAM_BB_BASE   ((uint32_t)0x12000000)
 
#define SRAM1_BB_BASE   ((uint32_t)0x22000000)
 
#define SRAM2_BB_BASE   ((uint32_t)0x2201C000)
 
#define SRAM3_BB_BASE   ((uint32_t)0x22400000)
 
#define PERIPH_BB_BASE   ((uint32_t)0x42000000)
 
#define BKPSRAM_BB_BASE   ((uint32_t)0x42024000)
 
+#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
+#define APB1PERIPH_BASE   PERIPH_BASE
 
+#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000)
 
+#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000)
 
+#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)
 
+#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)
 
+#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)
 
+#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)
 
+#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)
 
+#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)
 
+#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)
 
+#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)
 
+#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)
 
+#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)
 
+#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)
 
+#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)
 
+#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400)
 
+#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)
 
+#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)
 
+#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000)
 
+#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)
 
+#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)
 
+#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)
 
+#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)
 
+#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)
 
+#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)
 
+#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00)
 
+#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)
 
+#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)
 
+#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)
 
+#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)
 
+#define UART7_BASE   (APB1PERIPH_BASE + 0x7800)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00)
 
+#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000)
 
+#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400)
 
+#define USART1_BASE   (APB2PERIPH_BASE + 0x1000)
 
+#define USART6_BASE   (APB2PERIPH_BASE + 0x1400)
 
+#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000)
 
+#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100)
 
+#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200)
 
+#define ADC_BASE   (APB2PERIPH_BASE + 0x2300)
 
+#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00)
 
+#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)
 
+#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400)
 
+#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800)
 
+#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00)
 
+#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000)
 
+#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400)
 
+#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800)
 
+#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000)
 
+#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400)
 
+#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800)
 
+#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004)
 
+#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024)
 
+#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800)
 
+#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104)
 
+#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000)
 
+#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400)
 
+#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800)
 
+#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00)
 
+#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000)
 
+#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400)
 
+#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800)
 
+#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00)
 
+#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000)
 
+#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400)
 
+#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800)
 
+#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000)
 
+#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800)
 
+#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00)
 
+#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000)
 
+#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010)
 
+#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028)
 
+#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040)
 
+#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058)
 
+#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070)
 
+#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088)
 
+#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0)
 
+#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8)
 
+#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400)
 
+#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010)
 
+#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028)
 
+#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040)
 
+#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058)
 
+#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070)
 
+#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088)
 
+#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0)
 
+#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8)
 
+#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000)
 
+#define ETH_MAC_BASE   (ETH_BASE)
 
+#define ETH_MMC_BASE   (ETH_BASE + 0x0100)
 
+#define ETH_PTP_BASE   (ETH_BASE + 0x0700)
 
+#define ETH_DMA_BASE   (ETH_BASE + 0x1000)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000)
 
+#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000)
 
+#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000)
 
+#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400)
 
+#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800)
 
+#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000)
 
+#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104)
 
+#define FSMC_Bank2_R_BASE   (FSMC_R_BASE + 0x0060)
 
+#define FSMC_Bank3_R_BASE   (FSMC_R_BASE + 0x0080)
 
+#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0)
 
+#define DBGMCU_BASE   ((uint32_t )0xE0042000)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000)
+
+

APB1 peripherals

+ +
+
+ +
+
+ + + + +
#define BKPSRAM_BASE   ((uint32_t)0x40024000)
+
+

Backup SRAM(4 KB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define BKPSRAM_BB_BASE   ((uint32_t)0x42024000)
+
+

Backup SRAM(4 KB) base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define CCMDATARAM_BASE   ((uint32_t)0x10000000)
+
+

CCM(core coupled memory) data RAM(64 KB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define CCMDATARAM_BB_BASE   ((uint32_t)0x12000000)
+
+

CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000)
+
+

AHB2 peripherals

+ +
+
+ +
+
+ + + + +
#define FLASH_BASE   ((uint32_t)0x08000000)
+
+

FLASH(up to 1 MB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define FSMC_R_BASE   ((uint32_t)0xA0000000)
+
+

FSMC registers base address

+ +
+
+ +
+
+ + + + +
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104)
+
+

AHB1 peripherals

+ +
+
+ +
+
+ + + + +
#define PERIPH_BASE   ((uint32_t)0x40000000)
+
+

Peripheral base address in the alias region

+ +
+
+ +
+
+ + + + +
#define PERIPH_BB_BASE   ((uint32_t)0x42000000)
+
+

Peripheral base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800)
+
+

FSMC Bankx registers base address

+ +
+
+ +
+
+ + + + +
#define SRAM1_BASE   ((uint32_t)0x20000000)
+
+

SRAM1(112 KB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define SRAM1_BB_BASE   ((uint32_t)0x22000000)
+
+

SRAM1(112 KB) base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define SRAM2_BASE   ((uint32_t)0x2001C000)
+
+

SRAM2(16 KB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define SRAM2_BB_BASE   ((uint32_t)0x2201C000)
+
+

SRAM2(16 KB) base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define SRAM3_BASE   ((uint32_t)0x20020000)
+
+

SRAM3(64 KB) base address in the alias region

+ +
+
+ +
+
+ + + + +
#define SRAM3_BB_BASE   ((uint32_t)0x22400000)
+
+

SRAM3(64 KB) base address in the bit-band region

+ +
+
+ +
+
+ + + + +
#define SRAM_BB_BASE   SRAM1_BB_BASE
+
+

Peripheral memory map

+ +
+
+ +
+
+ + + + +
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00)
+
+

APB2 peripherals

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___peripheral__memory__map.map b/group___peripheral__memory__map.map new file mode 100644 index 0000000..03b5c8f --- /dev/null +++ b/group___peripheral__memory__map.map @@ -0,0 +1,3 @@ + + + diff --git a/group___peripheral__memory__map.md5 b/group___peripheral__memory__map.md5 new file mode 100644 index 0000000..fac591f --- /dev/null +++ b/group___peripheral__memory__map.md5 @@ -0,0 +1 @@ +e1f5112ef215f093e1158378149df372 \ No newline at end of file diff --git a/group___peripheral__memory__map.png b/group___peripheral__memory__map.png new file mode 100644 index 0000000..84c27a5 Binary files /dev/null and b/group___peripheral__memory__map.png differ diff --git a/group___peripheral__registers__structures.html b/group___peripheral__registers__structures.html new file mode 100644 index 0000000..dd12247 --- /dev/null +++ b/group___peripheral__registers__structures.html @@ -0,0 +1,226 @@ + + + + + + +discoverpixy: Peripheral_registers_structures + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Classes
+
+
Peripheral_registers_structures
CMSIS » Stm32f4xx
+
+
+
+Collaboration diagram for Peripheral_registers_structures:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Classes

struct  ADC_TypeDef
 Analog to Digital Converter. More...
 
struct  ADC_Common_TypeDef
 
struct  CAN_TxMailBox_TypeDef
 Controller Area Network TxMailBox. More...
 
struct  CAN_FIFOMailBox_TypeDef
 Controller Area Network FIFOMailBox. More...
 
struct  CAN_FilterRegister_TypeDef
 Controller Area Network FilterRegister. More...
 
struct  CAN_TypeDef
 Controller Area Network. More...
 
struct  CRC_TypeDef
 CRC calculation unit. More...
 
struct  DAC_TypeDef
 Digital to Analog Converter. More...
 
struct  DBGMCU_TypeDef
 Debug MCU. More...
 
struct  DCMI_TypeDef
 DCMI. More...
 
struct  DMA_Stream_TypeDef
 DMA Controller. More...
 
struct  DMA_TypeDef
 
struct  DMA2D_TypeDef
 DMA2D Controller. More...
 
struct  ETH_TypeDef
 Ethernet MAC. More...
 
struct  EXTI_TypeDef
 External Interrupt/Event Controller. More...
 
struct  FLASH_TypeDef
 FLASH Registers. More...
 
struct  FSMC_Bank1_TypeDef
 Flexible Static Memory Controller. More...
 
struct  FSMC_Bank1E_TypeDef
 Flexible Static Memory Controller Bank1E. More...
 
struct  FSMC_Bank2_TypeDef
 Flexible Static Memory Controller Bank2. More...
 
struct  FSMC_Bank3_TypeDef
 Flexible Static Memory Controller Bank3. More...
 
struct  FSMC_Bank4_TypeDef
 Flexible Static Memory Controller Bank4. More...
 
struct  GPIO_TypeDef
 General Purpose I/O. More...
 
struct  SYSCFG_TypeDef
 System configuration controller. More...
 
struct  I2C_TypeDef
 Inter-integrated Circuit Interface. More...
 
struct  IWDG_TypeDef
 Independent WATCHDOG. More...
 
struct  LTDC_TypeDef
 LCD-TFT Display Controller. More...
 
struct  LTDC_Layer_TypeDef
 LCD-TFT Display layer x Controller. More...
 
struct  PWR_TypeDef
 Power Control. More...
 
struct  RCC_TypeDef
 Reset and Clock Control. More...
 
struct  RTC_TypeDef
 Real-Time Clock. More...
 
struct  SAI_TypeDef
 Serial Audio Interface. More...
 
struct  SAI_Block_TypeDef
 
struct  SDIO_TypeDef
 SD host Interface. More...
 
struct  SPI_TypeDef
 Serial Peripheral Interface. More...
 
struct  TIM_TypeDef
 TIM. More...
 
struct  USART_TypeDef
 Universal Synchronous Asynchronous Receiver Transmitter. More...
 
struct  WWDG_TypeDef
 Window WATCHDOG. More...
 
struct  CRYP_TypeDef
 Crypto Processor. More...
 
struct  HASH_TypeDef
 HASH. More...
 
struct  HASH_DIGEST_TypeDef
 HASH_DIGEST. More...
 
struct  RNG_TypeDef
 RNG. More...
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___peripheral__registers__structures.map b/group___peripheral__registers__structures.map new file mode 100644 index 0000000..512859e --- /dev/null +++ b/group___peripheral__registers__structures.map @@ -0,0 +1,3 @@ + + + diff --git a/group___peripheral__registers__structures.md5 b/group___peripheral__registers__structures.md5 new file mode 100644 index 0000000..4360584 --- /dev/null +++ b/group___peripheral__registers__structures.md5 @@ -0,0 +1 @@ +7d84d4cb181be09eadb6b7dbede0f61c \ No newline at end of file diff --git a/group___peripheral__registers__structures.png b/group___peripheral__registers__structures.png new file mode 100644 index 0000000..1d95cac Binary files /dev/null and b/group___peripheral__registers__structures.png differ diff --git a/group___power___mode__selection.html b/group___power___mode__selection.html new file mode 100644 index 0000000..bc4d83d --- /dev/null +++ b/group___power___mode__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Power_Mode_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
Power_Mode_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Power_Mode_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_LOWPOWERMODE_POWERDOWN   ((uint8_t)0x00)
 
+#define LIS302DL_LOWPOWERMODE_ACTIVE   ((uint8_t)0x40)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___power___mode__selection.map b/group___power___mode__selection.map new file mode 100644 index 0000000..daa1803 --- /dev/null +++ b/group___power___mode__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___power___mode__selection.md5 b/group___power___mode__selection.md5 new file mode 100644 index 0000000..b7e1077 --- /dev/null +++ b/group___power___mode__selection.md5 @@ -0,0 +1 @@ +ed68a3935b459cfafcf4f9ec7f5e808f \ No newline at end of file diff --git a/group___power___mode__selection.png b/group___power___mode__selection.png new file mode 100644 index 0000000..d84ecf1 Binary files /dev/null and b/group___power___mode__selection.png differ diff --git a/group___r_c_c.html b/group___r_c_c.html new file mode 100644 index 0000000..422f77f --- /dev/null +++ b/group___r_c_c.html @@ -0,0 +1,2831 @@ + + + + + + +discoverpixy: RCC + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
RCC
STM32F4xx_StdPeriph_Driver
+
+
+ +

RCC driver modules. +More...

+
+Collaboration diagram for RCC:
+
+
+ + +
+
+ + + + + + +

+Modules

 RCC_Exported_Constants
 
 RCC_Private_Functions
 
+ + + +

+Classes

struct  RCC_ClocksTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
 
+#define CR_OFFSET   (RCC_OFFSET + 0x00)
 
+#define HSION_BitNumber   0x00
 
+#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
 
+#define CSSON_BitNumber   0x13
 
+#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
 
+#define PLLON_BitNumber   0x18
 
+#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
 
+#define PLLI2SON_BitNumber   0x1A
 
+#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
 
+#define PLLSAION_BitNumber   0x1C
 
+#define CR_PLLSAION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
 
+#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
 
+#define I2SSRC_BitNumber   0x17
 
+#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
 
+#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
 
+#define RTCEN_BitNumber   0x0F
 
+#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
 
+#define BDRST_BitNumber   0x10
 
+#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
 
+#define CSR_OFFSET   (RCC_OFFSET + 0x74)
 
+#define LSION_BitNumber   0x00
 
+#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
 
+#define DCKCFGR_OFFSET   (RCC_OFFSET + 0x8C)
 
+#define TIMPRE_BitNumber   0x18
 
+#define DCKCFGR_TIMPRE_BB   (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
 
+#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)
 
+#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)
 
+#define FLAG_MASK   ((uint8_t)0x1F)
 
+#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
 
+#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
 
+#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
 
+#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state. More...
 
void RCC_HSEConfig (uint8_t RCC_HSE)
 Configures the External High Speed oscillator (HSE). More...
 
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up. More...
 
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value. More...
 
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI). More...
 
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE). More...
 
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI). More...
 
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 Configures the main PLL clock source, multiplication and division factors. More...
 
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the main PLL. More...
 
+void RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR)
 
void RCC_PLLI2SCmd (FunctionalState NewState)
 Enables or disables the PLLI2S. More...
 
void RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
 Configures the PLLSAI clock multiplication and division factors. More...
 
void RCC_PLLSAICmd (FunctionalState NewState)
 Enables or disables the PLLSAI. More...
 
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System. More...
 
void RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 Selects the clock source to output on MCO1 pin(PA8). More...
 
void RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 Selects the clock source to output on MCO2 pin(PC9). More...
 
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK). More...
 
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock. More...
 
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK). More...
 
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1). More...
 
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2). More...
 
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...
 
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
 Configures the SAI clock Divider coming from PLLI2S. More...
 
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
 Configures the SAI clock Divider coming from PLLSAI. More...
 
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
 Configures SAI1BlockA clock source selection. More...
 
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
 Configures SAI1BlockB clock source selection. More...
 
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
 Configures the LTDC clock Divider coming from PLLSAI. More...
 
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
 Configures the Timers clocks prescalers selection. More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_LSEModeConfig (uint8_t Mode)
 Configures the External Low Speed oscillator mode (LSE mode). More...
 
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts. More...
 
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not. More...
 
void RCC_ClearFlag (void)
 Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...
 
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not. More...
 
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC's interrupt pending bits. More...
 
+

Detailed Description

+

RCC driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
+
+ +

Adjusts the Internal High Speed oscillator (HSI) calibration value.

+
Note
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
+
Parameters
+ + +
HSICalibrationValuespecifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB1 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
    • +
  • RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
    • +
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
    • +
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB1 peripheral reset.

+
Parameters
+ + + +
RCC_AHB1Periphspecifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB2 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB2 peripheral reset.

+
Parameters
+ + + +
RCC_AHB2Periphspecifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB3 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB3 peripheral reset.

+
Parameters
+ + + +
RCC_AHB3Periphspecifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the Low Speed APB (APB1) peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases Low Speed APB (APB1) peripheral reset.

+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the High Speed APB (APB2) peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases High Speed APB (APB2) peripheral reset.

+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void RCC_BackupResetCmd (FunctionalState NewState)
+
+ +

Forces or releases the Backup domain reset.

+
Note
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
+
+The BKPSRAM is not affected by this reset.
+
Parameters
+ + +
NewStatenew state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_ClearFlag (void )
+
+ +

Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_ClearITPendingBit (uint8_t RCC_IT)
+
+ +

Clears the RCC's interrupt pending bits.

+
Parameters
+ + +
RCC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_IT_CSS: Clock Security System interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
+
+ +

Enables or disables the Clock Security System.

+
Note
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+
Parameters
+ + +
NewStatenew state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_DeInit (void )
+
+ +

Resets the RCC clock configuration to the default reset state.

+
Note
The default reset state of the clock configuration is given below:
    +
  • HSI ON and used as system clock source
    • +
  • HSE, PLL and PLLI2S OFF
    • +
  • AHB, APB1 and APB2 prescaler set to 1.
    • +
  • CSS, MCO1 and MCO2 OFF
    • +
  • All interrupts disabled
    • +
+
+
+This function doesn't modify the configuration of the
    +
  • Peripheral clocks
    • +
  • LSI, LSE and RTC clocks
    • +
+
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_GetClocksFreq (RCC_ClocksTypeDef * RCC_Clocks)
+
+ +

Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.

+
Note
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
+
+If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+
+If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+
+If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
+
+(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
+
+(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
+
+The result of this function could be not correct when using fractional value for HSE crystal.
+
Parameters
+ + +
RCC_Clockspointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
+
+
+
Note
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
+
+Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
+
+ +

Checks whether the specified RCC flag is set or not.

+
Parameters
+ + +
RCC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
    • +
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
    • +
  • RCC_FLAG_PLLRDY: main PLL clock ready
    • +
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
    • +
  • RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
    • +
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
    • +
  • RCC_FLAG_BORRST: POR/PDR or BOR reset
    • +
  • RCC_FLAG_PINRST: Pin reset
    • +
  • RCC_FLAG_PORRST: POR/PDR reset
    • +
  • RCC_FLAG_SFTRST: Software reset
    • +
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
    • +
  • RCC_FLAG_WWDGRST: Window Watchdog reset
    • +
  • RCC_FLAG_LPWRRST: Low Power reset
    • +
+
+
+
+
Return values
+ + +
Thenew state of RCC_FLAG (SET or RESET).
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
+
+ +

Checks whether the specified RCC interrupt has occurred or not.

+
Parameters
+ + +
RCC_ITspecifies the RCC interrupt source to check. This parameter can be one of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_IT_CSS: Clock Security System interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of RCC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t RCC_GetSYSCLKSource (void )
+
+ +

Returns the clock source used as system clock.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Theclock source used as system clock. The returned value can be one of the following:
    +
  • 0x00: HSI used as system clock
    • +
  • 0x04: HSE used as system clock
    • +
  • 0x08: PLL used as system clock
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
+
+ +

Configures the AHB clock (HCLK).

+
Note
Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
+
Parameters
+ + +
RCC_SYSCLKdefines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
    +
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
    • +
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
    • +
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
    • +
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
    • +
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
    • +
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
    • +
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
    • +
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
    • +
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HSEConfig (uint8_t RCC_HSE)
+
+ +

Configures the External High Speed oscillator (HSE).

+
Note
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
+
+HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
+
+The HSE is stopped by hardware when entering STOP and STANDBY modes.
+
+This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.
+
Parameters
+ + +
RCC_HSEspecifies the new state of the HSE. This parameter can be one of the following values:
    +
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
    • +
  • RCC_HSE_ON: turn ON the HSE oscillator
    • +
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HSICmd (FunctionalState NewState)
+
+ +

Enables or disables the Internal High Speed oscillator (HSI).

+
Note
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
+
+HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
+
+After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
+
Parameters
+ + +
NewStatenew state of the HSI. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
+
+ +

Configures the I2S clock source (I2SCLK).

+
Note
This function must be called before enabling the I2S APB clock.
+
Parameters
+ + +
RCC_I2SCLKSourcespecifies the I2S clock source. This parameter can be one of the following values:
    +
  • RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
    • +
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_ITConfig (uint8_t RCC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RCC interrupts.

+
Parameters
+ + + +
RCC_ITspecifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
+
NewStatenew state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSEConfig (uint8_t RCC_LSE)
+
+ +

Configures the External Low Speed oscillator (LSE).

+
Note
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
+
+After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
+
Parameters
+ + +
RCC_LSEspecifies the new state of the LSE. This parameter can be one of the following values:
    +
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
    • +
  • RCC_LSE_ON: turn ON the LSE oscillator
    • +
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSEModeConfig (uint8_t Mode)
+
+ +

Configures the External Low Speed oscillator mode (LSE mode).

+
Note
This mode is only available for STM32F411xx devices.
+
Parameters
+ + +
Modespecifies the LSE mode. This parameter can be one of the following values:
    +
  • RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
    • +
  • RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSICmd (FunctionalState NewState)
+
+ +

Enables or disables the Internal Low Speed oscillator (LSI).

+
Note
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
+
+LSI can not be disabled if the IWDG is running.
+
Parameters
+ + +
NewStatenew state of the LSI. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
+
+ +

Configures the LTDC clock Divider coming from PLLSAI.

+
Note
The LTDC peripheral is only available with STM32F429xx/439xx Devices.
+
+This function must be called before enabling the PLLSAI.
+
Parameters
+ + +
RCC_PLLSAIDivRspecifies the PLLSAI division factor for LTDC clock . This parameter must be a number between 2 and 16. LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_MCO1Config (uint32_t RCC_MCO1Source,
uint32_t RCC_MCO1Div 
)
+
+ +

Selects the clock source to output on MCO1 pin(PA8).

+
Note
PA8 should be configured in alternate function mode.
+
Parameters
+ + + +
RCC_MCO1Sourcespecifies the clock source to output. This parameter can be one of the following values:
    +
  • RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
    • +
  • RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
    • +
  • RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
    • +
  • RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
    • +
+
RCC_MCO1Divspecifies the MCO1 prescaler. This parameter can be one of the following values:
    +
  • RCC_MCO1Div_1: no division applied to MCO1 clock
    • +
  • RCC_MCO1Div_2: division by 2 applied to MCO1 clock
    • +
  • RCC_MCO1Div_3: division by 3 applied to MCO1 clock
    • +
  • RCC_MCO1Div_4: division by 4 applied to MCO1 clock
    • +
  • RCC_MCO1Div_5: division by 5 applied to MCO1 clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_MCO2Config (uint32_t RCC_MCO2Source,
uint32_t RCC_MCO2Div 
)
+
+ +

Selects the clock source to output on MCO2 pin(PC9).

+
Note
PC9 should be configured in alternate function mode.
+
Parameters
+ + + +
RCC_MCO2Sourcespecifies the clock source to output. This parameter can be one of the following values:
    +
  • RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
    • +
  • RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
    • +
  • RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
    • +
  • RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
    • +
+
RCC_MCO2Divspecifies the MCO2 prescaler. This parameter can be one of the following values:
    +
  • RCC_MCO2Div_1: no division applied to MCO2 clock
    • +
  • RCC_MCO2Div_2: division by 2 applied to MCO2 clock
    • +
  • RCC_MCO2Div_3: division by 3 applied to MCO2 clock
    • +
  • RCC_MCO2Div_4: division by 4 applied to MCO2 clock
    • +
  • RCC_MCO2Div_5: division by 5 applied to MCO2 clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PCLK1Config (uint32_t RCC_HCLK)
+
+ +

Configures the Low Speed APB clock (PCLK1).

+
Parameters
+ + +
RCC_HCLKdefines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
    +
  • RCC_HCLK_Div1: APB1 clock = HCLK
    • +
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
    • +
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
    • +
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
    • +
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PCLK2Config (uint32_t RCC_HCLK)
+
+ +

Configures the High Speed APB clock (PCLK2).

+
Parameters
+ + +
RCC_HCLKdefines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
    +
  • RCC_HCLK_Div1: APB2 clock = HCLK
    • +
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
    • +
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
    • +
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
    • +
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLCmd (FunctionalState NewState)
+
+ +

Enables or disables the main PLL.

+
Note
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
+
+The main PLL can not be disabled if it is used as system clock source
+
+The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the main PLL. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void RCC_PLLConfig (uint32_t RCC_PLLSource,
uint32_t PLLM,
uint32_t PLLN,
uint32_t PLLP,
uint32_t PLLQ 
)
+
+ +

Configures the main PLL clock source, multiplication and division factors.

+
Note
This function must be used only when the main PLL is disabled.
+
Parameters
+ + +
RCC_PLLSourcespecifies the PLL entry clock source. This parameter can be one of the following values:
    +
  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
    • +
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
    • +
+
+
+
+
Note
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+
Parameters
+ + +
PLLMspecifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.
+
+
+
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
+
Parameters
+ + +
PLLNspecifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192 and 432.
+
+
+
Note
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
+
Parameters
+ + +
PLLPspecifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
+
+
+
Note
You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.
+
Parameters
+ + +
PLLQspecifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15.
+
+
+
Note
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLI2SCmd (FunctionalState NewState)
+
+ +

Enables or disables the PLLI2S.

+
Note
The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLSAICmd (FunctionalState NewState)
+
+ +

Enables or disables the PLLSAI.

+
Note
This function can be used only for STM32F42xxx/43xxx devices
+
+The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RCC_PLLSAIConfig (uint32_t PLLSAIN,
uint32_t PLLSAIQ,
uint32_t PLLSAIR 
)
+
+ +

Configures the PLLSAI clock multiplication and division factors.

+
Note
This function can be used only for STM32F42xxx/43xxx devices
+
+This function must be used only when the PLLSAI is disabled.
+
+PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )
+
Parameters
+ + +
PLLSAINspecifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 192 and 432.
+
+
+
Note
You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
+
Parameters
+ + + +
PLLSAIQspecifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLSAIRspecifies the division factor for LTDC clock This parameter must be a number between 2 and 7.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_RTCCLKCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC clock.

+
Note
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
+
Parameters
+ + +
NewStatenew state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
+
+ +

Configures the RTC clock (RTCCLK).

+
Note
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
+
+Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
+
Parameters
+ + +
RCC_RTCCLKSourcespecifies the RTC clock source. This parameter can be one of the following values:
    +
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
    • +
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
    • +
  • RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
    • +
+
+
+
+
Note
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
+
+The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
+
+ +

Configures SAI1BlockA clock source selection.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
+
Parameters
+ + +
RCC_SAIBlockACLKSourcespecifies the SAI Block A clock source. This parameter can be one of the following values:
    +
  • RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block A clock
    • +
  • RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block A clock
    • +
  • RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
+
+ +

Configures SAI1BlockB clock source selection.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
+
Parameters
+ + +
RCC_SAIBlockBCLKSourcespecifies the SAI Block B clock source. This parameter can be one of the following values:
    +
  • RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block B clock
    • +
  • RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block B clock
    • +
  • RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block B clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
+
+ +

Configures the SAI clock Divider coming from PLLI2S.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling the PLLI2S.
+
Parameters
+ + +
RCC_PLLI2SDivQspecifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
+
+ +

Configures the SAI clock Divider coming from PLLSAI.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling the PLLSAI.
+
Parameters
+ + +
RCC_PLLSAIDivQspecifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
+
+ +

Configures the system clock (SYSCLK).

+
Note
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
+
+A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
+
Parameters
+ + +
RCC_SYSCLKSourcespecifies the clock source used as system clock. This parameter can be one of the following values:
    +
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
    • +
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
    • +
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
+
+ +

Configures the Timers clocks prescalers selection.

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
Parameters
+ + +
RCC_TIMCLKPrescaler: specifies the Timers clocks prescalers selection This parameter can be one of the following values:
    +
  • RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
    • +
+
    +
  • RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RCC_WaitForHSEStartUp (void )
+
+ +

Waits for HSE start-up.

+
Note
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: HSE oscillator is stable and ready to use
    • +
  • ERROR: HSE oscillator not yet ready
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c.map b/group___r_c_c.map new file mode 100644 index 0000000..36a6e57 --- /dev/null +++ b/group___r_c_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_c_c.md5 b/group___r_c_c.md5 new file mode 100644 index 0000000..c3f1bda --- /dev/null +++ b/group___r_c_c.md5 @@ -0,0 +1 @@ +ff6fa2c21378cd80fef74c30eea2e078 \ No newline at end of file diff --git a/group___r_c_c.png b/group___r_c_c.png new file mode 100644 index 0000000..b63266e Binary files /dev/null and b/group___r_c_c.png differ diff --git a/group___r_c_c___a_h_b1___peripherals.html b/group___r_c_c___a_h_b1___peripherals.html new file mode 100644 index 0000000..291fc12 --- /dev/null +++ b/group___r_c_c___a_h_b1___peripherals.html @@ -0,0 +1,196 @@ + + + + + + +discoverpixy: RCC_AHB1_Peripherals + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Macros
+
+
RCC_AHB1_Peripherals
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_AHB1_Peripherals:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_AHB1Periph_GPIOA   ((uint32_t)0x00000001)
 
+#define RCC_AHB1Periph_GPIOB   ((uint32_t)0x00000002)
 
+#define RCC_AHB1Periph_GPIOC   ((uint32_t)0x00000004)
 
+#define RCC_AHB1Periph_GPIOD   ((uint32_t)0x00000008)
 
+#define RCC_AHB1Periph_GPIOE   ((uint32_t)0x00000010)
 
+#define RCC_AHB1Periph_GPIOF   ((uint32_t)0x00000020)
 
+#define RCC_AHB1Periph_GPIOG   ((uint32_t)0x00000040)
 
+#define RCC_AHB1Periph_GPIOH   ((uint32_t)0x00000080)
 
+#define RCC_AHB1Periph_GPIOI   ((uint32_t)0x00000100)
 
+#define RCC_AHB1Periph_GPIOJ   ((uint32_t)0x00000200)
 
+#define RCC_AHB1Periph_GPIOK   ((uint32_t)0x00000400)
 
+#define RCC_AHB1Periph_CRC   ((uint32_t)0x00001000)
 
+#define RCC_AHB1Periph_FLITF   ((uint32_t)0x00008000)
 
+#define RCC_AHB1Periph_SRAM1   ((uint32_t)0x00010000)
 
+#define RCC_AHB1Periph_SRAM2   ((uint32_t)0x00020000)
 
+#define RCC_AHB1Periph_BKPSRAM   ((uint32_t)0x00040000)
 
+#define RCC_AHB1Periph_SRAM3   ((uint32_t)0x00080000)
 
+#define RCC_AHB1Periph_CCMDATARAMEN   ((uint32_t)0x00100000)
 
+#define RCC_AHB1Periph_DMA1   ((uint32_t)0x00200000)
 
+#define RCC_AHB1Periph_DMA2   ((uint32_t)0x00400000)
 
+#define RCC_AHB1Periph_DMA2D   ((uint32_t)0x00800000)
 
+#define RCC_AHB1Periph_ETH_MAC   ((uint32_t)0x02000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Tx   ((uint32_t)0x04000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Rx   ((uint32_t)0x08000000)
 
+#define RCC_AHB1Periph_ETH_MAC_PTP   ((uint32_t)0x10000000)
 
+#define RCC_AHB1Periph_OTG_HS   ((uint32_t)0x20000000)
 
+#define RCC_AHB1Periph_OTG_HS_ULPI   ((uint32_t)0x40000000)
 
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)   ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH)   ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH)   ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_h_b1___peripherals.map b/group___r_c_c___a_h_b1___peripherals.map new file mode 100644 index 0000000..3134c24 --- /dev/null +++ b/group___r_c_c___a_h_b1___peripherals.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_h_b1___peripherals.md5 b/group___r_c_c___a_h_b1___peripherals.md5 new file mode 100644 index 0000000..2663c94 --- /dev/null +++ b/group___r_c_c___a_h_b1___peripherals.md5 @@ -0,0 +1 @@ +611aa4cfa128c4e2d96d8ba7f7a9757e \ No newline at end of file diff --git a/group___r_c_c___a_h_b1___peripherals.png b/group___r_c_c___a_h_b1___peripherals.png new file mode 100644 index 0000000..619c35d Binary files /dev/null and b/group___r_c_c___a_h_b1___peripherals.png differ diff --git a/group___r_c_c___a_h_b2___peripherals.html b/group___r_c_c___a_h_b2___peripherals.html new file mode 100644 index 0000000..06c4b20 --- /dev/null +++ b/group___r_c_c___a_h_b2___peripherals.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: RCC_AHB2_Peripherals + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_AHB2_Peripherals
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_AHB2_Peripherals:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define RCC_AHB2Periph_DCMI   ((uint32_t)0x00000001)
 
+#define RCC_AHB2Periph_CRYP   ((uint32_t)0x00000010)
 
+#define RCC_AHB2Periph_HASH   ((uint32_t)0x00000020)
 
+#define RCC_AHB2Periph_RNG   ((uint32_t)0x00000040)
 
+#define RCC_AHB2Periph_OTG_FS   ((uint32_t)0x00000080)
 
+#define IS_RCC_AHB2_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_h_b2___peripherals.map b/group___r_c_c___a_h_b2___peripherals.map new file mode 100644 index 0000000..0560776 --- /dev/null +++ b/group___r_c_c___a_h_b2___peripherals.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_h_b2___peripherals.md5 b/group___r_c_c___a_h_b2___peripherals.md5 new file mode 100644 index 0000000..707f055 --- /dev/null +++ b/group___r_c_c___a_h_b2___peripherals.md5 @@ -0,0 +1 @@ +2af9d3fe599ec2fd49eab8b182c6e1d4 \ No newline at end of file diff --git a/group___r_c_c___a_h_b2___peripherals.png b/group___r_c_c___a_h_b2___peripherals.png new file mode 100644 index 0000000..f941ad4 Binary files /dev/null and b/group___r_c_c___a_h_b2___peripherals.png differ diff --git a/group___r_c_c___a_h_b3___peripherals.html b/group___r_c_c___a_h_b3___peripherals.html new file mode 100644 index 0000000..0c8cfa1 --- /dev/null +++ b/group___r_c_c___a_h_b3___peripherals.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: RCC_AHB3_Peripherals + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
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+ +
+ +
+
+Macros
+
+
RCC_AHB3_Peripherals
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_AHB3_Peripherals:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define RCC_AHB3Periph_FSMC   ((uint32_t)0x00000001)
 
+#define IS_RCC_AHB3_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_h_b3___peripherals.map b/group___r_c_c___a_h_b3___peripherals.map new file mode 100644 index 0000000..03d31ba --- /dev/null +++ b/group___r_c_c___a_h_b3___peripherals.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_h_b3___peripherals.md5 b/group___r_c_c___a_h_b3___peripherals.md5 new file mode 100644 index 0000000..6910239 --- /dev/null +++ b/group___r_c_c___a_h_b3___peripherals.md5 @@ -0,0 +1 @@ +24e65cac928df349257e215739f547e5 \ No newline at end of file diff --git a/group___r_c_c___a_h_b3___peripherals.png b/group___r_c_c___a_h_b3___peripherals.png new file mode 100644 index 0000000..97bbcf2 Binary files /dev/null and b/group___r_c_c___a_h_b3___peripherals.png differ diff --git a/group___r_c_c___a_h_b___clock___source.html b/group___r_c_c___a_h_b___clock___source.html new file mode 100644 index 0000000..7e456fb --- /dev/null +++ b/group___r_c_c___a_h_b___clock___source.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: RCC_AHB_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_AHB_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_AHB_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
 
+#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
 
+#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
 
+#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
 
+#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
 
+#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
 
+#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
 
+#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
 
+#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
 
#define IS_RCC_HCLK(HCLK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_HCLK( HCLK)
+
+Value:
(((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+
((HCLK) == RCC_SYSCLK_Div512))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_h_b___clock___source.map b/group___r_c_c___a_h_b___clock___source.map new file mode 100644 index 0000000..ceace24 --- /dev/null +++ b/group___r_c_c___a_h_b___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_h_b___clock___source.md5 b/group___r_c_c___a_h_b___clock___source.md5 new file mode 100644 index 0000000..fba4003 --- /dev/null +++ b/group___r_c_c___a_h_b___clock___source.md5 @@ -0,0 +1 @@ +d44cf8cad844b01d3e941ffbd8507941 \ No newline at end of file diff --git a/group___r_c_c___a_h_b___clock___source.png b/group___r_c_c___a_h_b___clock___source.png new file mode 100644 index 0000000..7abe311 Binary files /dev/null and b/group___r_c_c___a_h_b___clock___source.png differ diff --git a/group___r_c_c___a_p_b1___a_p_b2___clock___source.html b/group___r_c_c___a_p_b1___a_p_b2___clock___source.html new file mode 100644 index 0000000..7863b75 --- /dev/null +++ b/group___r_c_c___a_p_b1___a_p_b2___clock___source.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: RCC_APB1_APB2_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
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+Macros
+
+
RCC_APB1_APB2_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_APB1_APB2_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define RCC_HCLK_Div1   ((uint32_t)0x00000000)
 
+#define RCC_HCLK_Div2   ((uint32_t)0x00001000)
 
+#define RCC_HCLK_Div4   ((uint32_t)0x00001400)
 
+#define RCC_HCLK_Div8   ((uint32_t)0x00001800)
 
+#define RCC_HCLK_Div16   ((uint32_t)0x00001C00)
 
#define IS_RCC_PCLK(PCLK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_PCLK( PCLK)
+
+Value:
(((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+
((PCLK) == RCC_HCLK_Div16))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_p_b1___a_p_b2___clock___source.map b/group___r_c_c___a_p_b1___a_p_b2___clock___source.map new file mode 100644 index 0000000..22e6e6a --- /dev/null +++ b/group___r_c_c___a_p_b1___a_p_b2___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_p_b1___a_p_b2___clock___source.md5 b/group___r_c_c___a_p_b1___a_p_b2___clock___source.md5 new file mode 100644 index 0000000..b3df7d5 --- /dev/null +++ b/group___r_c_c___a_p_b1___a_p_b2___clock___source.md5 @@ -0,0 +1 @@ +e9f0e95a5fa349e8daed4120c223ad42 \ No newline at end of file diff --git a/group___r_c_c___a_p_b1___a_p_b2___clock___source.png b/group___r_c_c___a_p_b1___a_p_b2___clock___source.png new file mode 100644 index 0000000..b7f089e Binary files /dev/null and b/group___r_c_c___a_p_b1___a_p_b2___clock___source.png differ diff --git a/group___r_c_c___a_p_b1___peripherals.html b/group___r_c_c___a_p_b1___peripherals.html new file mode 100644 index 0000000..170c224 --- /dev/null +++ b/group___r_c_c___a_p_b1___peripherals.html @@ -0,0 +1,184 @@ + + + + + + +discoverpixy: RCC_APB1_Peripherals + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_APB1_Peripherals
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_APB1_Peripherals:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_APB1Periph_TIM2   ((uint32_t)0x00000001)
 
+#define RCC_APB1Periph_TIM3   ((uint32_t)0x00000002)
 
+#define RCC_APB1Periph_TIM4   ((uint32_t)0x00000004)
 
+#define RCC_APB1Periph_TIM5   ((uint32_t)0x00000008)
 
+#define RCC_APB1Periph_TIM6   ((uint32_t)0x00000010)
 
+#define RCC_APB1Periph_TIM7   ((uint32_t)0x00000020)
 
+#define RCC_APB1Periph_TIM12   ((uint32_t)0x00000040)
 
+#define RCC_APB1Periph_TIM13   ((uint32_t)0x00000080)
 
+#define RCC_APB1Periph_TIM14   ((uint32_t)0x00000100)
 
+#define RCC_APB1Periph_WWDG   ((uint32_t)0x00000800)
 
+#define RCC_APB1Periph_SPI2   ((uint32_t)0x00004000)
 
+#define RCC_APB1Periph_SPI3   ((uint32_t)0x00008000)
 
+#define RCC_APB1Periph_USART2   ((uint32_t)0x00020000)
 
+#define RCC_APB1Periph_USART3   ((uint32_t)0x00040000)
 
+#define RCC_APB1Periph_UART4   ((uint32_t)0x00080000)
 
+#define RCC_APB1Periph_UART5   ((uint32_t)0x00100000)
 
+#define RCC_APB1Periph_I2C1   ((uint32_t)0x00200000)
 
+#define RCC_APB1Periph_I2C2   ((uint32_t)0x00400000)
 
+#define RCC_APB1Periph_I2C3   ((uint32_t)0x00800000)
 
+#define RCC_APB1Periph_CAN1   ((uint32_t)0x02000000)
 
+#define RCC_APB1Periph_CAN2   ((uint32_t)0x04000000)
 
+#define RCC_APB1Periph_PWR   ((uint32_t)0x10000000)
 
+#define RCC_APB1Periph_DAC   ((uint32_t)0x20000000)
 
+#define RCC_APB1Periph_UART7   ((uint32_t)0x40000000)
 
+#define RCC_APB1Periph_UART8   ((uint32_t)0x80000000)
 
+#define IS_RCC_APB1_PERIPH(PERIPH)   ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_p_b1___peripherals.map b/group___r_c_c___a_p_b1___peripherals.map new file mode 100644 index 0000000..13a7582 --- /dev/null +++ b/group___r_c_c___a_p_b1___peripherals.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_p_b1___peripherals.md5 b/group___r_c_c___a_p_b1___peripherals.md5 new file mode 100644 index 0000000..fec8d49 --- /dev/null +++ b/group___r_c_c___a_p_b1___peripherals.md5 @@ -0,0 +1 @@ +e891cf995d3da8e713988e9a4a686fd5 \ No newline at end of file diff --git a/group___r_c_c___a_p_b1___peripherals.png b/group___r_c_c___a_p_b1___peripherals.png new file mode 100644 index 0000000..3fe0c12 Binary files /dev/null and b/group___r_c_c___a_p_b1___peripherals.png differ diff --git a/group___r_c_c___a_p_b2___peripherals.html b/group___r_c_c___a_p_b2___peripherals.html new file mode 100644 index 0000000..7e683ec --- /dev/null +++ b/group___r_c_c___a_p_b2___peripherals.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: RCC_APB2_Peripherals + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_APB2_Peripherals
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_APB2_Peripherals:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_APB2Periph_TIM1   ((uint32_t)0x00000001)
 
+#define RCC_APB2Periph_TIM8   ((uint32_t)0x00000002)
 
+#define RCC_APB2Periph_USART1   ((uint32_t)0x00000010)
 
+#define RCC_APB2Periph_USART6   ((uint32_t)0x00000020)
 
+#define RCC_APB2Periph_ADC   ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC1   ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC2   ((uint32_t)0x00000200)
 
+#define RCC_APB2Periph_ADC3   ((uint32_t)0x00000400)
 
+#define RCC_APB2Periph_SDIO   ((uint32_t)0x00000800)
 
+#define RCC_APB2Periph_SPI1   ((uint32_t)0x00001000)
 
+#define RCC_APB2Periph_SPI4   ((uint32_t)0x00002000)
 
+#define RCC_APB2Periph_SYSCFG   ((uint32_t)0x00004000)
 
+#define RCC_APB2Periph_TIM9   ((uint32_t)0x00010000)
 
+#define RCC_APB2Periph_TIM10   ((uint32_t)0x00020000)
 
+#define RCC_APB2Periph_TIM11   ((uint32_t)0x00040000)
 
+#define RCC_APB2Periph_SPI5   ((uint32_t)0x00100000)
 
+#define RCC_APB2Periph_SPI6   ((uint32_t)0x00200000)
 
+#define RCC_APB2Periph_SAI1   ((uint32_t)0x00400000)
 
+#define RCC_APB2Periph_LTDC   ((uint32_t)0x04000000)
 
+#define IS_RCC_APB2_PERIPH(PERIPH)   ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH)   ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___a_p_b2___peripherals.map b/group___r_c_c___a_p_b2___peripherals.map new file mode 100644 index 0000000..d712b97 --- /dev/null +++ b/group___r_c_c___a_p_b2___peripherals.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___a_p_b2___peripherals.md5 b/group___r_c_c___a_p_b2___peripherals.md5 new file mode 100644 index 0000000..6931b41 --- /dev/null +++ b/group___r_c_c___a_p_b2___peripherals.md5 @@ -0,0 +1 @@ +f0700dd8eee4bd116feb9e8fa2764914 \ No newline at end of file diff --git a/group___r_c_c___a_p_b2___peripherals.png b/group___r_c_c___a_p_b2___peripherals.png new file mode 100644 index 0000000..08988e1 Binary files /dev/null and b/group___r_c_c___a_p_b2___peripherals.png differ diff --git a/group___r_c_c___exported___constants.html b/group___r_c_c___exported___constants.html new file mode 100644 index 0000000..90e56d5 --- /dev/null +++ b/group___r_c_c___exported___constants.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: RCC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
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+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
RCC_Exported_Constants
STM32F4xx_StdPeriph_Driver » RCC
+
+
+
+Collaboration diagram for RCC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 RCC_HSE_configuration
 
 RCC_LSE_Dual_Mode_Selection
 
 RCC_PLL_Clock_Source
 
 RCC_System_Clock_Source
 
 RCC_AHB_Clock_Source
 
 RCC_APB1_APB2_Clock_Source
 
 RCC_Interrupt_Source
 
 RCC_LSE_Configuration
 
 RCC_RTC_Clock_Source
 
 RCC_I2S_Clock_Source
 
 RCC_SAI_BlockA_Clock_Source
 
 RCC_SAI_BlockB_Clock_Source
 
 RCC_TIM_PRescaler_Selection
 
 RCC_AHB1_Peripherals
 
 RCC_AHB2_Peripherals
 
 RCC_AHB3_Peripherals
 
 RCC_APB1_Peripherals
 
 RCC_APB2_Peripherals
 
 RCC_MCO1_Clock_Source_Prescaler
 
 RCC_MCO2_Clock_Source_Prescaler
 
 RCC_Flag
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___exported___constants.map b/group___r_c_c___exported___constants.map new file mode 100644 index 0000000..f8515d4 --- /dev/null +++ b/group___r_c_c___exported___constants.map @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___r_c_c___exported___constants.md5 b/group___r_c_c___exported___constants.md5 new file mode 100644 index 0000000..32016f6 --- /dev/null +++ b/group___r_c_c___exported___constants.md5 @@ -0,0 +1 @@ +f59e1cb66942faaabc3ad03f35a0a2ce \ No newline at end of file diff --git a/group___r_c_c___exported___constants.png b/group___r_c_c___exported___constants.png new file mode 100644 index 0000000..9e7dcd1 Binary files /dev/null and b/group___r_c_c___exported___constants.png differ diff --git a/group___r_c_c___flag.html b/group___r_c_c___flag.html new file mode 100644 index 0000000..df8ecfe --- /dev/null +++ b/group___r_c_c___flag.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: RCC_Flag + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_Flag
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_Flag:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_FLAG_HSIRDY   ((uint8_t)0x21)
 
+#define RCC_FLAG_HSERDY   ((uint8_t)0x31)
 
+#define RCC_FLAG_PLLRDY   ((uint8_t)0x39)
 
+#define RCC_FLAG_PLLI2SRDY   ((uint8_t)0x3B)
 
+#define RCC_FLAG_PLLSAIRDY   ((uint8_t)0x3D)
 
+#define RCC_FLAG_LSERDY   ((uint8_t)0x41)
 
+#define RCC_FLAG_LSIRDY   ((uint8_t)0x61)
 
+#define RCC_FLAG_BORRST   ((uint8_t)0x79)
 
+#define RCC_FLAG_PINRST   ((uint8_t)0x7A)
 
+#define RCC_FLAG_PORRST   ((uint8_t)0x7B)
 
+#define RCC_FLAG_SFTRST   ((uint8_t)0x7C)
 
+#define RCC_FLAG_IWDGRST   ((uint8_t)0x7D)
 
+#define RCC_FLAG_WWDGRST   ((uint8_t)0x7E)
 
+#define RCC_FLAG_LPWRRST   ((uint8_t)0x7F)
 
#define IS_RCC_FLAG(FLAG)
 
+#define IS_RCC_CALIBRATION_VALUE(VALUE)   ((VALUE) <= 0x1F)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_FLAG( FLAG)
+
+Value:
(((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
+
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
+
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___flag.map b/group___r_c_c___flag.map new file mode 100644 index 0000000..99822f2 --- /dev/null +++ b/group___r_c_c___flag.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___flag.md5 b/group___r_c_c___flag.md5 new file mode 100644 index 0000000..324f6c9 --- /dev/null +++ b/group___r_c_c___flag.md5 @@ -0,0 +1 @@ +bdf7176308bf64c1b817851c7943d197 \ No newline at end of file diff --git a/group___r_c_c___flag.png b/group___r_c_c___flag.png new file mode 100644 index 0000000..04cb9bf Binary files /dev/null and b/group___r_c_c___flag.png differ diff --git a/group___r_c_c___group1.html b/group___r_c_c___group1.html new file mode 100644 index 0000000..e271107 --- /dev/null +++ b/group___r_c_c___group1.html @@ -0,0 +1,856 @@ + + + + + + +discoverpixy: Internal and external clocks, PLL, CSS and MCO configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Internal and external clocks, PLL, CSS and MCO configuration functions
STM32F4xx_StdPeriph_Driver » RCC » RCC_Private_Functions
+
+
+ +

Internal and external clocks, PLL, CSS and MCO configuration functions. +More...

+
+Collaboration diagram for Internal and external clocks, PLL, CSS and MCO configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state. More...
 
void RCC_HSEConfig (uint8_t RCC_HSE)
 Configures the External High Speed oscillator (HSE). More...
 
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up. More...
 
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value. More...
 
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI). More...
 
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE). More...
 
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI). More...
 
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 Configures the main PLL clock source, multiplication and division factors. More...
 
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the main PLL. More...
 
void RCC_PLLI2SCmd (FunctionalState NewState)
 Enables or disables the PLLI2S. More...
 
void RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
 Configures the PLLSAI clock multiplication and division factors. More...
 
void RCC_PLLSAICmd (FunctionalState NewState)
 Enables or disables the PLLSAI. More...
 
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System. More...
 
void RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 Selects the clock source to output on MCO1 pin(PA8). More...
 
void RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 Selects the clock source to output on MCO2 pin(PC9). More...
 
+

Detailed Description

+

Internal and external clocks, PLL, CSS and MCO configuration functions.

+
 ===================================================================================
+ ##### Internal and  external clocks, PLL, CSS and MCO configuration functions #####
+ ===================================================================================  
+    [..]
+      This section provide functions allowing to configure the internal/external clocks,
+      PLLs, CSS and MCO pins.
+  
+      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+          the PLL as System clock source.
+
+      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+          clock source.
+
+      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+          through the PLL as System clock source. Can be used also as RTC clock source.
+
+      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+
+      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+        (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+      (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
+          high-quality audio performance on the I2S interface or SAI interface in case 
+          of STM32F429x/439x devices.
+     
+      (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI 
+          interface and LCD TFT controller available only for STM32F42xxx/43xxx devices.
+  
+      (#) CSS (Clock security system), once enable and if a HSE clock failure occurs 
+         (HSE used directly or through PLL as System clock source), the System clock
+         is automatically switched to HSI and an interrupt is generated if enabled. 
+         The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
+         exception vector.   
+
+      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+          clock (through a configurable prescaler) on PA8 pin.
+
+      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+          clock (through a configurable prescaler) on PC9 pin.

Function Documentation

+ +
+
+ + + + + + + + +
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
+
+ +

Adjusts the Internal High Speed oscillator (HSI) calibration value.

+
Note
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
+
Parameters
+ + +
HSICalibrationValuespecifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
+
+ +

Enables or disables the Clock Security System.

+
Note
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+
Parameters
+ + +
NewStatenew state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_DeInit (void )
+
+ +

Resets the RCC clock configuration to the default reset state.

+
Note
The default reset state of the clock configuration is given below:
    +
  • HSI ON and used as system clock source
    • +
  • HSE, PLL and PLLI2S OFF
    • +
  • AHB, APB1 and APB2 prescaler set to 1.
    • +
  • CSS, MCO1 and MCO2 OFF
    • +
  • All interrupts disabled
    • +
+
+
+This function doesn't modify the configuration of the
    +
  • Peripheral clocks
    • +
  • LSI, LSE and RTC clocks
    • +
+
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HSEConfig (uint8_t RCC_HSE)
+
+ +

Configures the External High Speed oscillator (HSE).

+
Note
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
+
+HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
+
+The HSE is stopped by hardware when entering STOP and STANDBY modes.
+
+This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function.
+
Parameters
+ + +
RCC_HSEspecifies the new state of the HSE. This parameter can be one of the following values:
    +
  • RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
    • +
  • RCC_HSE_ON: turn ON the HSE oscillator
    • +
  • RCC_HSE_Bypass: HSE oscillator bypassed with external clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HSICmd (FunctionalState NewState)
+
+ +

Enables or disables the Internal High Speed oscillator (HSI).

+
Note
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
+
+HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
+
+After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
+
Parameters
+ + +
NewStatenew state of the HSI. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSEConfig (uint8_t RCC_LSE)
+
+ +

Configures the External Low Speed oscillator (LSE).

+
Note
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
+
+After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
+
Parameters
+ + +
RCC_LSEspecifies the new state of the LSE. This parameter can be one of the following values:
    +
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
    • +
  • RCC_LSE_ON: turn ON the LSE oscillator
    • +
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSICmd (FunctionalState NewState)
+
+ +

Enables or disables the Internal Low Speed oscillator (LSI).

+
Note
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
+
+LSI can not be disabled if the IWDG is running.
+
Parameters
+ + +
NewStatenew state of the LSI. This parameter can be: ENABLE or DISABLE.
+
+
+
Note
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_MCO1Config (uint32_t RCC_MCO1Source,
uint32_t RCC_MCO1Div 
)
+
+ +

Selects the clock source to output on MCO1 pin(PA8).

+
Note
PA8 should be configured in alternate function mode.
+
Parameters
+ + + +
RCC_MCO1Sourcespecifies the clock source to output. This parameter can be one of the following values:
    +
  • RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
    • +
  • RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
    • +
  • RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
    • +
  • RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
    • +
+
RCC_MCO1Divspecifies the MCO1 prescaler. This parameter can be one of the following values:
    +
  • RCC_MCO1Div_1: no division applied to MCO1 clock
    • +
  • RCC_MCO1Div_2: division by 2 applied to MCO1 clock
    • +
  • RCC_MCO1Div_3: division by 3 applied to MCO1 clock
    • +
  • RCC_MCO1Div_4: division by 4 applied to MCO1 clock
    • +
  • RCC_MCO1Div_5: division by 5 applied to MCO1 clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_MCO2Config (uint32_t RCC_MCO2Source,
uint32_t RCC_MCO2Div 
)
+
+ +

Selects the clock source to output on MCO2 pin(PC9).

+
Note
PC9 should be configured in alternate function mode.
+
Parameters
+ + + +
RCC_MCO2Sourcespecifies the clock source to output. This parameter can be one of the following values:
    +
  • RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
    • +
  • RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
    • +
  • RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
    • +
  • RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
    • +
+
RCC_MCO2Divspecifies the MCO2 prescaler. This parameter can be one of the following values:
    +
  • RCC_MCO2Div_1: no division applied to MCO2 clock
    • +
  • RCC_MCO2Div_2: division by 2 applied to MCO2 clock
    • +
  • RCC_MCO2Div_3: division by 3 applied to MCO2 clock
    • +
  • RCC_MCO2Div_4: division by 4 applied to MCO2 clock
    • +
  • RCC_MCO2Div_5: division by 5 applied to MCO2 clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLCmd (FunctionalState NewState)
+
+ +

Enables or disables the main PLL.

+
Note
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
+
+The main PLL can not be disabled if it is used as system clock source
+
+The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the main PLL. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void RCC_PLLConfig (uint32_t RCC_PLLSource,
uint32_t PLLM,
uint32_t PLLN,
uint32_t PLLP,
uint32_t PLLQ 
)
+
+ +

Configures the main PLL clock source, multiplication and division factors.

+
Note
This function must be used only when the main PLL is disabled.
+
Parameters
+ + +
RCC_PLLSourcespecifies the PLL entry clock source. This parameter can be one of the following values:
    +
  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
    • +
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
    • +
+
+
+
+
Note
This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+
Parameters
+ + +
PLLMspecifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63.
+
+
+
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
+
Parameters
+ + +
PLLNspecifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192 and 432.
+
+
+
Note
You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
+
Parameters
+ + +
PLLPspecifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
+
+
+
Note
You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.
+
Parameters
+ + +
PLLQspecifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15.
+
+
+
Note
If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLI2SCmd (FunctionalState NewState)
+
+ +

Enables or disables the PLLI2S.

+
Note
The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PLLSAICmd (FunctionalState NewState)
+
+ +

Enables or disables the PLLSAI.

+
Note
This function can be used only for STM32F42xxx/43xxx devices
+
+The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
+
Parameters
+ + +
NewStatenew state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RCC_PLLSAIConfig (uint32_t PLLSAIN,
uint32_t PLLSAIQ,
uint32_t PLLSAIR 
)
+
+ +

Configures the PLLSAI clock multiplication and division factors.

+
Note
This function can be used only for STM32F42xxx/43xxx devices
+
+This function must be used only when the PLLSAI is disabled.
+
+PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )
+
Parameters
+ + +
PLLSAINspecifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 192 and 432.
+
+
+
Note
You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.
+
Parameters
+ + + +
PLLSAIQspecifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.
PLLSAIRspecifies the division factor for LTDC clock This parameter must be a number between 2 and 7.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RCC_WaitForHSEStartUp (void )
+
+ +

Waits for HSE start-up.

+
Note
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: HSE oscillator is stable and ready to use
    • +
  • ERROR: HSE oscillator not yet ready
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___group1.map b/group___r_c_c___group1.map new file mode 100644 index 0000000..ccddd57 --- /dev/null +++ b/group___r_c_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group1.md5 b/group___r_c_c___group1.md5 new file mode 100644 index 0000000..94ee247 --- /dev/null +++ b/group___r_c_c___group1.md5 @@ -0,0 +1 @@ +5634bf7c93ad80e796b87ea1847369f7 \ No newline at end of file diff --git a/group___r_c_c___group1.png b/group___r_c_c___group1.png new file mode 100644 index 0000000..6dad34d Binary files /dev/null and b/group___r_c_c___group1.png differ diff --git a/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.map b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.map new file mode 100644 index 0000000..ee1b68a --- /dev/null +++ b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.md5 b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.md5 new file mode 100644 index 0000000..7ef68e1 --- /dev/null +++ b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.md5 @@ -0,0 +1 @@ +19d3f21c6d5da73da1a8297722321a77 \ No newline at end of file diff --git a/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.png b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.png new file mode 100644 index 0000000..c9ae1aa Binary files /dev/null and b/group___r_c_c___group1_gae0f15692614dd048ee4110a056f001dc_cgraph.png differ diff --git a/group___r_c_c___group2.html b/group___r_c_c___group2.html new file mode 100644 index 0000000..ee6f483 --- /dev/null +++ b/group___r_c_c___group2.html @@ -0,0 +1,515 @@ + + + + + + +discoverpixy: System AHB and APB busses clocks configuration functions + + + + + + + + + + +
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+Functions
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System AHB and APB busses clocks configuration functions
STM32F4xx_StdPeriph_Driver » RCC » RCC_Private_Functions
+
+
+ +

System, AHB and APB busses clocks configuration functions. +More...

+
+Collaboration diagram for System AHB and APB busses clocks configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK). More...
 
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock. More...
 
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK). More...
 
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1). More...
 
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2). More...
 
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...
 
+

Detailed Description

+

System, AHB and APB busses clocks configuration functions.

+
 ===============================================================================
+      ##### System, AHB and APB busses clocks configuration functions #####
+ ===============================================================================  
+    [..]
+      This section provide functions allowing to configure the System, AHB, APB1 and 
+      APB2 busses clocks.
+  
+      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+          HSE and PLL.
+          The AHB clock (HCLK) is derived from System clock through configurable 
+          prescaler and used to clock the CPU, memory and peripherals mapped 
+          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
+          from AHB clock through configurable prescalers and used to clock 
+          the peripherals mapped on these busses. You can use 
+          "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
+
+      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
+        (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+             from an external clock mapped on the I2S_CKIN pin. 
+             You have to use RCC_I2SCLKConfig() function to configure this clock. 
+        (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+             divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
+             functions to configure this clock. 
+        (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+             to work correctly, while the SDIO require a frequency equal or lower than
+             to 48. This clock is derived of the main PLL through PLLQ divider.
+        (+@) IWDG clock which is always the LSI clock.
+       
+      (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency 
+         of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending 
+         on the device voltage range, the maximum frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |      NA        |154 < HCLK <= 168|140 < HCLK <= 160|
+ +---------------|----------------|----------------|-----------------|-----------------+ 
+      (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, 
+          PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum 
+          frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |8WS(9CPU cycle)|      NA        |      NA        |176 < HCLK <= 180|160 < HCLK <= 168|
+ +-------------------------------------------------------------------------------------+
+   
+      (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, 
+          PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum 
+          frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 22   |0 < HCLK <= 20   |
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44  |20 < HCLK <= 40  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66  |40 < HCLK <= 60  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|      NA        |72 < HCLK <= 84 |66 < HCLK <= 84  |60 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|      NA        |      NA        |      NA         |80 < HCLK <= 84  | 
+ +-------------------------------------------------------------------------------------+
+
+      (#) For STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, 
+          PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum 
+          frequency should be adapted accordingly:
+ +-------------------------------------------------------------------------------------+
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)|      NA        |96 < HCLK <= 100|72 < HCLK <= 90  |64 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|      NA        |       NA       |90 < HCLK <= 100 |80 < HCLK <= 96  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)|      NA        |       NA       |        NA       |96 < HCLK <= 100 |
+ +-------------------------------------------------------------------------------------+
+  
+      -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: 
+           (++) when VOS = '0', the maximum value of fHCLK = 144MHz. 
+           (++) when VOS = '1', the maximum value of fHCLK = 168MHz. 
+          [..] 
+          On STM32F42xxx/43xxx devices:
+           (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
+           (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
+           (++) when VOS[1:0] = '0x11', the maximum value of f  is 168MHz 
+          [..]  
+          On STM32F401x devices:
+           (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
+           (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
+          On STM32F411xE devices:
+           (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
+           (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
+           (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
+
+       You can use PWR_MainRegulatorModeConfig() function to control VOS bits.

Function Documentation

+ +
+
+ + + + + + + + +
void RCC_GetClocksFreq (RCC_ClocksTypeDef * RCC_Clocks)
+
+ +

Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.

+
Note
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
+
+If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+
+If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+
+If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
+
+(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
+
+(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
+
+The result of this function could be not correct when using fractional value for HSE crystal.
+
Parameters
+ + +
RCC_Clockspointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
+
+
+
Note
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
+
+Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint8_t RCC_GetSYSCLKSource (void )
+
+ +

Returns the clock source used as system clock.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Theclock source used as system clock. The returned value can be one of the following:
    +
  • 0x00: HSI used as system clock
    • +
  • 0x04: HSE used as system clock
    • +
  • 0x08: PLL used as system clock
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
+
+ +

Configures the AHB clock (HCLK).

+
Note
Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
+
Parameters
+ + +
RCC_SYSCLKdefines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
    +
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
    • +
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
    • +
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
    • +
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
    • +
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
    • +
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
    • +
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
    • +
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
    • +
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PCLK1Config (uint32_t RCC_HCLK)
+
+ +

Configures the Low Speed APB clock (PCLK1).

+
Parameters
+ + +
RCC_HCLKdefines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
    +
  • RCC_HCLK_Div1: APB1 clock = HCLK
    • +
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
    • +
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
    • +
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
    • +
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_PCLK2Config (uint32_t RCC_HCLK)
+
+ +

Configures the High Speed APB clock (PCLK2).

+
Parameters
+ + +
RCC_HCLKdefines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
    +
  • RCC_HCLK_Div1: APB2 clock = HCLK
    • +
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
    • +
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
    • +
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
    • +
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
+
+ +

Configures the system clock (SYSCLK).

+
Note
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
+
+A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
+
Parameters
+ + +
RCC_SYSCLKSourcespecifies the clock source used as system clock. This parameter can be one of the following values:
    +
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
    • +
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
    • +
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___group2.map b/group___r_c_c___group2.map new file mode 100644 index 0000000..f33fd2b --- /dev/null +++ b/group___r_c_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group2.md5 b/group___r_c_c___group2.md5 new file mode 100644 index 0000000..6185cdc --- /dev/null +++ b/group___r_c_c___group2.md5 @@ -0,0 +1 @@ +795031403f4b080dd98109645decc0f1 \ No newline at end of file diff --git a/group___r_c_c___group2.png b/group___r_c_c___group2.png new file mode 100644 index 0000000..0b8b2d1 Binary files /dev/null and b/group___r_c_c___group2.png differ diff --git a/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map new file mode 100644 index 0000000..f76737b --- /dev/null +++ b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 new file mode 100644 index 0000000..3fb1ed6 --- /dev/null +++ b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 @@ -0,0 +1 @@ +69e156d895f3de1061b4d5f8ba1b61af \ No newline at end of file diff --git a/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png new file mode 100644 index 0000000..510b5fb Binary files /dev/null and b/group___r_c_c___group2_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png differ diff --git a/group___r_c_c___group3.html b/group___r_c_c___group3.html new file mode 100644 index 0000000..a9da3c0 --- /dev/null +++ b/group___r_c_c___group3.html @@ -0,0 +1,1534 @@ + + + + + + +discoverpixy: Peripheral clocks configuration functions + + + + + + + + + + +
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+Functions
+
+
Peripheral clocks configuration functions
STM32F4xx_StdPeriph_Driver » RCC » RCC_Private_Functions
+
+
+ +

Peripheral clocks configuration functions. +More...

+
+Collaboration diagram for Peripheral clocks configuration functions:
+
+
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+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
 Configures the SAI clock Divider coming from PLLI2S. More...
 
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
 Configures the SAI clock Divider coming from PLLSAI. More...
 
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
 Configures SAI1BlockA clock source selection. More...
 
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
 Configures SAI1BlockB clock source selection. More...
 
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
 Configures the LTDC clock Divider coming from PLLSAI. More...
 
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
 Configures the Timers clocks prescalers selection. More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_LSEModeConfig (uint8_t Mode)
 Configures the External Low Speed oscillator mode (LSE mode). More...
 
+

Detailed Description

+

Peripheral clocks configuration functions.

+
 ===============================================================================
+              ##### Peripheral clocks configuration functions #####
+ ===============================================================================  
+    [..] This section provide functions allowing to configure the Peripheral clocks. 
+  
+      (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided 
+          by 2 to 31.
+     
+      (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
+          except internal SRAM, Flash and JTAG. Before to start using a peripheral 
+          you have to enable its interface clock. You can do this using 
+          RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
+
+      (#) To reset the peripherals configuration (to the default state after device reset)
+          you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
+          RCC_APB1PeriphResetCmd() functions.
+     
+      (#) To further reduce power consumption in SLEEP mode the peripheral clocks 
+          can be disabled prior to executing the WFI or WFE instructions. 
+          You can do this using RCC_AHBPeriphClockLPModeCmd(), 
+          RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB1 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
    • +
  • RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
    • +
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
    • +
  • RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
    • +
  • RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
  • RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB1 peripheral reset.

+
Parameters
+ + + +
RCC_AHB1Periphspecifies the AHB1 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_AHB1Periph_GPIOA: GPIOA clock
    • +
  • RCC_AHB1Periph_GPIOB: GPIOB clock
    • +
  • RCC_AHB1Periph_GPIOC: GPIOC clock
    • +
  • RCC_AHB1Periph_GPIOD: GPIOD clock
    • +
  • RCC_AHB1Periph_GPIOE: GPIOE clock
    • +
  • RCC_AHB1Periph_GPIOF: GPIOF clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOG: GPIOG clock
    • +
  • RCC_AHB1Periph_GPIOI: GPIOI clock
    • +
  • RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
    • +
  • RCC_AHB1Periph_CRC: CRC clock
    • +
  • RCC_AHB1Periph_DMA1: DMA1 clock
    • +
  • RCC_AHB1Periph_DMA2: DMA2 clock
    • +
  • RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
    • +
  • RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
    • +
  • RCC_AHB1Periph_OTG_HS: USB OTG HS clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB2 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB2 peripheral reset.

+
Parameters
+ + + +
RCC_AHB2Periphspecifies the AHB2 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_AHB2Periph_DCMI: DCMI clock
    • +
  • RCC_AHB2Periph_CRYP: CRYP clock
    • +
  • RCC_AHB2Periph_HASH: HASH clock
    • +
  • RCC_AHB2Periph_RNG: RNG clock
    • +
  • RCC_AHB2Periph_OTG_FS: USB OTG FS clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB3 peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_AHBPeriphspecifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases AHB3 peripheral reset.

+
Parameters
+ + + +
RCC_AHB3Periphspecifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the Low Speed APB (APB1) peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases Low Speed APB (APB1) peripheral reset.

+
Parameters
+ + + +
RCC_APB1Periphspecifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_APB1Periph_TIM2: TIM2 clock
    • +
  • RCC_APB1Periph_TIM3: TIM3 clock
    • +
  • RCC_APB1Periph_TIM4: TIM4 clock
    • +
  • RCC_APB1Periph_TIM5: TIM5 clock
    • +
  • RCC_APB1Periph_TIM6: TIM6 clock
    • +
  • RCC_APB1Periph_TIM7: TIM7 clock
    • +
  • RCC_APB1Periph_TIM12: TIM12 clock
    • +
  • RCC_APB1Periph_TIM13: TIM13 clock
    • +
  • RCC_APB1Periph_TIM14: TIM14 clock
    • +
  • RCC_APB1Periph_WWDG: WWDG clock
    • +
  • RCC_APB1Periph_SPI2: SPI2 clock
    • +
  • RCC_APB1Periph_SPI3: SPI3 clock
    • +
  • RCC_APB1Periph_USART2: USART2 clock
    • +
  • RCC_APB1Periph_USART3: USART3 clock
    • +
  • RCC_APB1Periph_UART4: UART4 clock
    • +
  • RCC_APB1Periph_UART5: UART5 clock
    • +
  • RCC_APB1Periph_I2C1: I2C1 clock
    • +
  • RCC_APB1Periph_I2C2: I2C2 clock
    • +
  • RCC_APB1Periph_I2C3: I2C3 clock
    • +
  • RCC_APB1Periph_CAN1: CAN1 clock
    • +
  • RCC_APB1Periph_CAN2: CAN2 clock
    • +
  • RCC_APB1Periph_PWR: PWR clock
    • +
  • RCC_APB1Periph_DAC: DAC clock
    • +
  • RCC_APB1Periph_UART7: UART7 clock
    • +
  • RCC_APB1Periph_UART8: UART8 clock
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the High Speed APB (APB2) peripheral clock.

+
Note
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

+
Note
Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
+
+After wakeup from SLEEP mode, the peripheral clock is enabled again.
+
+By default, all peripheral clocks are enabled during SLEEP mode.
+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph,
FunctionalState NewState 
)
+
+ +

Forces or releases High Speed APB (APB2) peripheral reset.

+
Parameters
+ + + +
RCC_APB2Periphspecifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
    +
  • RCC_APB2Periph_TIM1: TIM1 clock
    • +
  • RCC_APB2Periph_TIM8: TIM8 clock
    • +
  • RCC_APB2Periph_USART1: USART1 clock
    • +
  • RCC_APB2Periph_USART6: USART6 clock
    • +
  • RCC_APB2Periph_ADC1: ADC1 clock
    • +
  • RCC_APB2Periph_ADC2: ADC2 clock
    • +
  • RCC_APB2Periph_ADC3: ADC3 clock
    • +
  • RCC_APB2Periph_SDIO: SDIO clock
    • +
  • RCC_APB2Periph_SPI1: SPI1 clock
    • +
  • RCC_APB2Periph_SPI4: SPI4 clock
    • +
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
    • +
  • RCC_APB2Periph_TIM9: TIM9 clock
    • +
  • RCC_APB2Periph_TIM10: TIM10 clock
    • +
  • RCC_APB2Periph_TIM11: TIM11 clock
    • +
  • RCC_APB2Periph_SPI5: SPI5 clock
    • +
  • RCC_APB2Periph_SPI6: SPI6 clock
    • +
  • RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
    • +
  • RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
    • +
+
NewStatenew state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void RCC_BackupResetCmd (FunctionalState NewState)
+
+ +

Forces or releases the Backup domain reset.

+
Note
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
+
+The BKPSRAM is not affected by this reset.
+
Parameters
+ + +
NewStatenew state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
+
+ +

Configures the I2S clock source (I2SCLK).

+
Note
This function must be called before enabling the I2S APB clock.
+
Parameters
+ + +
RCC_I2SCLKSourcespecifies the I2S clock source. This parameter can be one of the following values:
    +
  • RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
    • +
  • RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LSEModeConfig (uint8_t Mode)
+
+ +

Configures the External Low Speed oscillator mode (LSE mode).

+
Note
This mode is only available for STM32F411xx devices.
+
Parameters
+ + +
Modespecifies the LSE mode. This parameter can be one of the following values:
    +
  • RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
    • +
  • RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
+
+ +

Configures the LTDC clock Divider coming from PLLSAI.

+
Note
The LTDC peripheral is only available with STM32F429xx/439xx Devices.
+
+This function must be called before enabling the PLLSAI.
+
Parameters
+ + +
RCC_PLLSAIDivRspecifies the PLLSAI division factor for LTDC clock . This parameter must be a number between 2 and 16. LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_RTCCLKCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC clock.

+
Note
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
+
Parameters
+ + +
NewStatenew state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
+
+ +

Configures the RTC clock (RTCCLK).

+
Note
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
+
+Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
+
Parameters
+ + +
RCC_RTCCLKSourcespecifies the RTC clock source. This parameter can be one of the following values:
    +
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
    • +
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
    • +
  • RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
    • +
+
+
+
+
Note
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
+
+The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
+
+ +

Configures SAI1BlockA clock source selection.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
+
Parameters
+ + +
RCC_SAIBlockACLKSourcespecifies the SAI Block A clock source. This parameter can be one of the following values:
    +
  • RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block A clock
    • +
  • RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block A clock
    • +
  • RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
+
+ +

Configures SAI1BlockB clock source selection.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling PLLSAI, PLLI2S and the SAI clock.
+
Parameters
+ + +
RCC_SAIBlockBCLKSourcespecifies the SAI Block B clock source. This parameter can be one of the following values:
    +
  • RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 Block B clock
    • +
  • RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 Block B clock
    • +
  • RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 Block B clock
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
+
+ +

Configures the SAI clock Divider coming from PLLI2S.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling the PLLI2S.
+
Parameters
+ + +
RCC_PLLI2SDivQspecifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
+
+ +

Configures the SAI clock Divider coming from PLLSAI.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
+This function must be called before enabling the PLLSAI.
+
Parameters
+ + +
RCC_PLLSAIDivQspecifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
+
+ +

Configures the Timers clocks prescalers selection.

+
Note
This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+
Parameters
+ + +
RCC_TIMCLKPrescaler: specifies the Timers clocks prescalers selection This parameter can be one of the following values:
    +
  • RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.
    • +
+
    +
  • RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___group3.map b/group___r_c_c___group3.map new file mode 100644 index 0000000..52ea950 --- /dev/null +++ b/group___r_c_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group3.md5 b/group___r_c_c___group3.md5 new file mode 100644 index 0000000..5263b5a --- /dev/null +++ b/group___r_c_c___group3.md5 @@ -0,0 +1 @@ +bba01355a2e5f92e827bf00e592784e2 \ No newline at end of file diff --git a/group___r_c_c___group3.png b/group___r_c_c___group3.png new file mode 100644 index 0000000..7d35590 Binary files /dev/null and b/group___r_c_c___group3.png differ diff --git a/group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph.map b/group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph.map new file mode 100644 index 0000000..45d9f7d --- /dev/null +++ b/group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph.md5 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discoverpixy +
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+ +
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+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » RCC » RCC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts. More...
 
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not. More...
 
void RCC_ClearFlag (void)
 Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...
 
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not. More...
 
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+                ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void RCC_ClearFlag (void )
+
+ +

Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RCC_ClearITPendingBit (uint8_t RCC_IT)
+
+ +

Clears the RCC's interrupt pending bits.

+
Parameters
+ + +
RCC_ITspecifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_IT_CSS: Clock Security System interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
+
+ +

Checks whether the specified RCC flag is set or not.

+
Parameters
+ + +
RCC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
    • +
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
    • +
  • RCC_FLAG_PLLRDY: main PLL clock ready
    • +
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
    • +
  • RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
    • +
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
    • +
  • RCC_FLAG_BORRST: POR/PDR or BOR reset
    • +
  • RCC_FLAG_PINRST: Pin reset
    • +
  • RCC_FLAG_PORRST: POR/PDR reset
    • +
  • RCC_FLAG_SFTRST: Software reset
    • +
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
    • +
  • RCC_FLAG_WWDGRST: Window Watchdog reset
    • +
  • RCC_FLAG_LPWRRST: Low Power reset
    • +
+
+
+
+
Return values
+ + +
Thenew state of RCC_FLAG (SET or RESET).
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
+
+ +

Checks whether the specified RCC interrupt has occurred or not.

+
Parameters
+ + +
RCC_ITspecifies the RCC interrupt source to check. This parameter can be one of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
  • RCC_IT_CSS: Clock Security System interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of RCC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RCC_ITConfig (uint8_t RCC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RCC interrupts.

+
Parameters
+ + + +
RCC_ITspecifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • RCC_IT_LSIRDY: LSI ready interrupt
    • +
  • RCC_IT_LSERDY: LSE ready interrupt
    • +
  • RCC_IT_HSIRDY: HSI ready interrupt
    • +
  • RCC_IT_HSERDY: HSE ready interrupt
    • +
  • RCC_IT_PLLRDY: main PLL ready interrupt
    • +
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
    • +
  • RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
    • +
+
NewStatenew state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___group4.map b/group___r_c_c___group4.map new file mode 100644 index 0000000..5504951 --- /dev/null +++ b/group___r_c_c___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group4.md5 b/group___r_c_c___group4.md5 new file mode 100644 index 0000000..b54e34f --- /dev/null +++ b/group___r_c_c___group4.md5 @@ -0,0 +1 @@ +e1e88b1b07921d655fa6542b6582facf \ No newline at end of file diff --git a/group___r_c_c___group4.png b/group___r_c_c___group4.png new file mode 100644 index 0000000..92e066e Binary files /dev/null and b/group___r_c_c___group4.png differ diff --git a/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.map b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.map new file mode 100644 index 0000000..4054673 --- /dev/null +++ b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 new file mode 100644 index 0000000..0d5d302 --- /dev/null +++ b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 @@ -0,0 +1 @@ +22767bb8bd39e9f3284dc08f555cce68 \ No newline at end of file diff --git a/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.png b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.png new file mode 100644 index 0000000..71d8f06 Binary files /dev/null and b/group___r_c_c___group4_ga2897bdc52f272031c44fb1f72205d295_icgraph.png differ diff --git a/group___r_c_c___h_s_e__configuration.html b/group___r_c_c___h_s_e__configuration.html new file mode 100644 index 0000000..71da19a --- /dev/null +++ b/group___r_c_c___h_s_e__configuration.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: RCC_HSE_configuration + + + + + + + + + + +
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discoverpixy +
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+Macros
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RCC_HSE_configuration
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_HSE_configuration:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RCC_HSE_OFF   ((uint8_t)0x00)
 
+#define RCC_HSE_ON   ((uint8_t)0x01)
 
+#define RCC_HSE_Bypass   ((uint8_t)0x05)
 
#define IS_RCC_HSE(HSE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_HSE( HSE)
+
+Value:
(((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+
((HSE) == RCC_HSE_Bypass))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___h_s_e__configuration.map b/group___r_c_c___h_s_e__configuration.map new file mode 100644 index 0000000..582ab1d --- /dev/null +++ b/group___r_c_c___h_s_e__configuration.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___h_s_e__configuration.md5 b/group___r_c_c___h_s_e__configuration.md5 new file mode 100644 index 0000000..6e4f32d --- /dev/null +++ b/group___r_c_c___h_s_e__configuration.md5 @@ -0,0 +1 @@ +1ebcc86ef96ed6bafe8f88a6aa4e3e9e \ No newline at end of file diff --git a/group___r_c_c___h_s_e__configuration.png b/group___r_c_c___h_s_e__configuration.png new file mode 100644 index 0000000..1d231d6 Binary files /dev/null and b/group___r_c_c___h_s_e__configuration.png differ diff --git a/group___r_c_c___i2_s___clock___source.html b/group___r_c_c___i2_s___clock___source.html new file mode 100644 index 0000000..d44d2c3 --- /dev/null +++ b/group___r_c_c___i2_s___clock___source.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: RCC_I2S_Clock_Source + + + + + + + + + + +
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discoverpixy +
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+Macros
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RCC_I2S_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
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+
+
+Collaboration diagram for RCC_I2S_Clock_Source:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RCC_I2S2CLKSource_PLLI2S   ((uint8_t)0x00)
 
+#define RCC_I2S2CLKSource_Ext   ((uint8_t)0x01)
 
+#define IS_RCC_I2SCLK_SOURCE(SOURCE)   (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___i2_s___clock___source.map b/group___r_c_c___i2_s___clock___source.map new file mode 100644 index 0000000..37d0cc9 --- /dev/null +++ b/group___r_c_c___i2_s___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___i2_s___clock___source.md5 b/group___r_c_c___i2_s___clock___source.md5 new file mode 100644 index 0000000..5e1db6e --- /dev/null +++ b/group___r_c_c___i2_s___clock___source.md5 @@ -0,0 +1 @@ +461797d435214bd0e95423a6558ff28e \ No newline at end of file diff --git a/group___r_c_c___i2_s___clock___source.png b/group___r_c_c___i2_s___clock___source.png new file mode 100644 index 0000000..d744157 Binary files /dev/null and b/group___r_c_c___i2_s___clock___source.png differ diff --git a/group___r_c_c___interrupt___source.html b/group___r_c_c___interrupt___source.html new file mode 100644 index 0000000..0999337 --- /dev/null +++ b/group___r_c_c___interrupt___source.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: RCC_Interrupt_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_Interrupt_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_Interrupt_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_IT_LSIRDY   ((uint8_t)0x01)
 
+#define RCC_IT_LSERDY   ((uint8_t)0x02)
 
+#define RCC_IT_HSIRDY   ((uint8_t)0x04)
 
+#define RCC_IT_HSERDY   ((uint8_t)0x08)
 
+#define RCC_IT_PLLRDY   ((uint8_t)0x10)
 
+#define RCC_IT_PLLI2SRDY   ((uint8_t)0x20)
 
+#define RCC_IT_PLLSAIRDY   ((uint8_t)0x40)
 
+#define RCC_IT_CSS   ((uint8_t)0x80)
 
+#define IS_RCC_IT(IT)   ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
 
#define IS_RCC_GET_IT(IT)
 
+#define IS_RCC_CLEAR_IT(IT)   ((IT) != 0x00)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_GET_IT( IT)
+
+Value:
(((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___interrupt___source.map b/group___r_c_c___interrupt___source.map new file mode 100644 index 0000000..8006235 --- /dev/null +++ b/group___r_c_c___interrupt___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___interrupt___source.md5 b/group___r_c_c___interrupt___source.md5 new file mode 100644 index 0000000..aca24ee --- /dev/null +++ b/group___r_c_c___interrupt___source.md5 @@ -0,0 +1 @@ +9f9482bd2737e3b6fc12f44a727ec142 \ No newline at end of file diff --git a/group___r_c_c___interrupt___source.png b/group___r_c_c___interrupt___source.png new file mode 100644 index 0000000..635827c Binary files /dev/null and b/group___r_c_c___interrupt___source.png differ diff --git a/group___r_c_c___l_s_e___configuration.html b/group___r_c_c___l_s_e___configuration.html new file mode 100644 index 0000000..c3276c0 --- /dev/null +++ b/group___r_c_c___l_s_e___configuration.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: RCC_LSE_Configuration + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_LSE_Configuration
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_LSE_Configuration:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RCC_LSE_OFF   ((uint8_t)0x00)
 
+#define RCC_LSE_ON   ((uint8_t)0x01)
 
+#define RCC_LSE_Bypass   ((uint8_t)0x04)
 
#define IS_RCC_LSE(LSE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_LSE( LSE)
+
+Value:
(((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+
((LSE) == RCC_LSE_Bypass))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___l_s_e___configuration.map b/group___r_c_c___l_s_e___configuration.map new file mode 100644 index 0000000..b7b3de3 --- /dev/null +++ b/group___r_c_c___l_s_e___configuration.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___l_s_e___configuration.md5 b/group___r_c_c___l_s_e___configuration.md5 new file mode 100644 index 0000000..0be2d27 --- /dev/null +++ b/group___r_c_c___l_s_e___configuration.md5 @@ -0,0 +1 @@ +28c2f7691a6d07cba95ed2d0b483c141 \ No newline at end of file diff --git a/group___r_c_c___l_s_e___configuration.png b/group___r_c_c___l_s_e___configuration.png new file mode 100644 index 0000000..42f03b7 Binary files /dev/null and b/group___r_c_c___l_s_e___configuration.png differ diff --git a/group___r_c_c___l_s_e___dual___mode___selection.html b/group___r_c_c___l_s_e___dual___mode___selection.html new file mode 100644 index 0000000..7f0338e --- /dev/null +++ b/group___r_c_c___l_s_e___dual___mode___selection.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RCC_LSE_Dual_Mode_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_LSE_Dual_Mode_Selection
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_LSE_Dual_Mode_Selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RCC_LSE_LOWPOWER_MODE   ((uint8_t)0x00)
 
+#define RCC_LSE_HIGHDRIVE_MODE   ((uint8_t)0x01)
 
#define IS_RCC_LSE_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_LSE_MODE( MODE)
+
+Value:
(((MODE) == RCC_LSE_LOWPOWER_MODE) || \
+
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___l_s_e___dual___mode___selection.map b/group___r_c_c___l_s_e___dual___mode___selection.map new file mode 100644 index 0000000..56294ba --- /dev/null +++ b/group___r_c_c___l_s_e___dual___mode___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___l_s_e___dual___mode___selection.md5 b/group___r_c_c___l_s_e___dual___mode___selection.md5 new file mode 100644 index 0000000..9ec44e0 --- /dev/null +++ b/group___r_c_c___l_s_e___dual___mode___selection.md5 @@ -0,0 +1 @@ +2ee8be0ca08105eef5538a9a4b9ff3a6 \ No newline at end of file diff --git a/group___r_c_c___l_s_e___dual___mode___selection.png b/group___r_c_c___l_s_e___dual___mode___selection.png new file mode 100644 index 0000000..cf729b7 Binary files /dev/null and b/group___r_c_c___l_s_e___dual___mode___selection.png differ diff --git a/group___r_c_c___m_c_o1___clock___source___prescaler.html b/group___r_c_c___m_c_o1___clock___source___prescaler.html new file mode 100644 index 0000000..e6322c3 --- /dev/null +++ b/group___r_c_c___m_c_o1___clock___source___prescaler.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: RCC_MCO1_Clock_Source_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_MCO1_Clock_Source_Prescaler
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_MCO1_Clock_Source_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_MCO1Source_HSI   ((uint32_t)0x00000000)
 
+#define RCC_MCO1Source_LSE   ((uint32_t)0x00200000)
 
+#define RCC_MCO1Source_HSE   ((uint32_t)0x00400000)
 
+#define RCC_MCO1Source_PLLCLK   ((uint32_t)0x00600000)
 
+#define RCC_MCO1Div_1   ((uint32_t)0x00000000)
 
+#define RCC_MCO1Div_2   ((uint32_t)0x04000000)
 
+#define RCC_MCO1Div_3   ((uint32_t)0x05000000)
 
+#define RCC_MCO1Div_4   ((uint32_t)0x06000000)
 
+#define RCC_MCO1Div_5   ((uint32_t)0x07000000)
 
#define IS_RCC_MCO1SOURCE(SOURCE)
 
#define IS_RCC_MCO1DIV(DIV)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_MCO1DIV( DIV)
+
+Value:
(((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
+
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
+
((DIV) == RCC_MCO1Div_5))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_RCC_MCO1SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
+
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___m_c_o1___clock___source___prescaler.map b/group___r_c_c___m_c_o1___clock___source___prescaler.map new file mode 100644 index 0000000..5ea6d09 --- /dev/null +++ b/group___r_c_c___m_c_o1___clock___source___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___m_c_o1___clock___source___prescaler.md5 b/group___r_c_c___m_c_o1___clock___source___prescaler.md5 new file mode 100644 index 0000000..0565af2 --- /dev/null +++ b/group___r_c_c___m_c_o1___clock___source___prescaler.md5 @@ -0,0 +1 @@ +443a8722cead3e4fad7a382aff0c9d72 \ No newline at end of file diff --git a/group___r_c_c___m_c_o1___clock___source___prescaler.png b/group___r_c_c___m_c_o1___clock___source___prescaler.png new file mode 100644 index 0000000..e97581c Binary files /dev/null and b/group___r_c_c___m_c_o1___clock___source___prescaler.png differ diff --git a/group___r_c_c___m_c_o2___clock___source___prescaler.html b/group___r_c_c___m_c_o2___clock___source___prescaler.html new file mode 100644 index 0000000..e712f03 --- /dev/null +++ b/group___r_c_c___m_c_o2___clock___source___prescaler.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: RCC_MCO2_Clock_Source_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_MCO2_Clock_Source_Prescaler
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_MCO2_Clock_Source_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_MCO2Source_SYSCLK   ((uint32_t)0x00000000)
 
+#define RCC_MCO2Source_PLLI2SCLK   ((uint32_t)0x40000000)
 
+#define RCC_MCO2Source_HSE   ((uint32_t)0x80000000)
 
+#define RCC_MCO2Source_PLLCLK   ((uint32_t)0xC0000000)
 
+#define RCC_MCO2Div_1   ((uint32_t)0x00000000)
 
+#define RCC_MCO2Div_2   ((uint32_t)0x20000000)
 
+#define RCC_MCO2Div_3   ((uint32_t)0x28000000)
 
+#define RCC_MCO2Div_4   ((uint32_t)0x30000000)
 
+#define RCC_MCO2Div_5   ((uint32_t)0x38000000)
 
#define IS_RCC_MCO2SOURCE(SOURCE)
 
#define IS_RCC_MCO2DIV(DIV)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_MCO2DIV( DIV)
+
+Value:
(((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
+
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
+
((DIV) == RCC_MCO2Div_5))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_RCC_MCO2SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
+
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___m_c_o2___clock___source___prescaler.map b/group___r_c_c___m_c_o2___clock___source___prescaler.map new file mode 100644 index 0000000..4a74127 --- /dev/null +++ b/group___r_c_c___m_c_o2___clock___source___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___m_c_o2___clock___source___prescaler.md5 b/group___r_c_c___m_c_o2___clock___source___prescaler.md5 new file mode 100644 index 0000000..ade39c3 --- /dev/null +++ b/group___r_c_c___m_c_o2___clock___source___prescaler.md5 @@ -0,0 +1 @@ +dc4b6d19bfd10d4fd3792f39e1da72ff \ No newline at end of file diff --git a/group___r_c_c___m_c_o2___clock___source___prescaler.png b/group___r_c_c___m_c_o2___clock___source___prescaler.png new file mode 100644 index 0000000..b815560 Binary files /dev/null and b/group___r_c_c___m_c_o2___clock___source___prescaler.png differ diff --git a/group___r_c_c___p_l_l___clock___source.html b/group___r_c_c___p_l_l___clock___source.html new file mode 100644 index 0000000..82d8618 --- /dev/null +++ b/group___r_c_c___p_l_l___clock___source.html @@ -0,0 +1,206 @@ + + + + + + +discoverpixy: RCC_PLL_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_PLL_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_PLL_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_PLLSource_HSI   ((uint32_t)0x00000000)
 
+#define RCC_PLLSource_HSE   ((uint32_t)0x00400000)
 
#define IS_RCC_PLL_SOURCE(SOURCE)
 
+#define IS_RCC_PLLM_VALUE(VALUE)   ((VALUE) <= 63)
 
+#define IS_RCC_PLLN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLP_VALUE(VALUE)   (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
 
+#define IS_RCC_PLLQ_VALUE(VALUE)   ((4 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLI2SN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLI2SR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
+#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((VALUE) <= 63)
 
+#define IS_RCC_PLLI2SQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLSAIN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLSAIQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLSAIR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
+#define RCC_PLLSAIDivR_Div2   ((uint32_t)0x00000000)
 
+#define RCC_PLLSAIDivR_Div4   ((uint32_t)0x00010000)
 
+#define RCC_PLLSAIDivR_Div8   ((uint32_t)0x00020000)
 
+#define RCC_PLLSAIDivR_Div16   ((uint32_t)0x00030000)
 
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_PLL_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_PLLSource_HSI) || \
+
((SOURCE) == RCC_PLLSource_HSE))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_RCC_PLLSAI_DIVR_VALUE( VALUE)
+
+Value:
(((VALUE) == RCC_PLLSAIDivR_Div2) ||\
+
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
+
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
+
((VALUE) == RCC_PLLSAIDivR_Div16))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___p_l_l___clock___source.map b/group___r_c_c___p_l_l___clock___source.map new file mode 100644 index 0000000..fb5c25b --- /dev/null +++ b/group___r_c_c___p_l_l___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___p_l_l___clock___source.md5 b/group___r_c_c___p_l_l___clock___source.md5 new file mode 100644 index 0000000..798f1cc --- /dev/null +++ b/group___r_c_c___p_l_l___clock___source.md5 @@ -0,0 +1 @@ +4fee9ee377295efd3da8f299c7566a95 \ No newline at end of file diff --git a/group___r_c_c___p_l_l___clock___source.png b/group___r_c_c___p_l_l___clock___source.png new file mode 100644 index 0000000..55396cc Binary files /dev/null and b/group___r_c_c___p_l_l___clock___source.png differ diff --git a/group___r_c_c___private___functions.html b/group___r_c_c___private___functions.html new file mode 100644 index 0000000..b114cd6 --- /dev/null +++ b/group___r_c_c___private___functions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: RCC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
RCC_Private_Functions
STM32F4xx_StdPeriph_Driver » RCC
+
+
+
+Collaboration diagram for RCC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 Internal and external clocks, PLL, CSS and MCO configuration functions
 Internal and external clocks, PLL, CSS and MCO configuration functions.
 
 System AHB and APB busses clocks configuration functions
 System, AHB and APB busses clocks configuration functions.
 
 Peripheral clocks configuration functions
 Peripheral clocks configuration functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___private___functions.map b/group___r_c_c___private___functions.map new file mode 100644 index 0000000..f63ecfd --- /dev/null +++ b/group___r_c_c___private___functions.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___r_c_c___private___functions.md5 b/group___r_c_c___private___functions.md5 new file mode 100644 index 0000000..5672660 --- /dev/null +++ b/group___r_c_c___private___functions.md5 @@ -0,0 +1 @@ +0d51bf997410bfa2614f395cfaab172f \ No newline at end of file diff --git a/group___r_c_c___private___functions.png b/group___r_c_c___private___functions.png new file mode 100644 index 0000000..44546d3 Binary files /dev/null and b/group___r_c_c___private___functions.png differ diff --git a/group___r_c_c___r_t_c___clock___source.html b/group___r_c_c___r_t_c___clock___source.html new file mode 100644 index 0000000..aeb442f --- /dev/null +++ b/group___r_c_c___r_t_c___clock___source.html @@ -0,0 +1,205 @@ + + + + + + +discoverpixy: RCC_RTC_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_RTC_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_RTC_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_RTCCLKSource_LSE   ((uint32_t)0x00000100)
 
+#define RCC_RTCCLKSource_LSI   ((uint32_t)0x00000200)
 
+#define RCC_RTCCLKSource_HSE_Div2   ((uint32_t)0x00020300)
 
+#define RCC_RTCCLKSource_HSE_Div3   ((uint32_t)0x00030300)
 
+#define RCC_RTCCLKSource_HSE_Div4   ((uint32_t)0x00040300)
 
+#define RCC_RTCCLKSource_HSE_Div5   ((uint32_t)0x00050300)
 
+#define RCC_RTCCLKSource_HSE_Div6   ((uint32_t)0x00060300)
 
+#define RCC_RTCCLKSource_HSE_Div7   ((uint32_t)0x00070300)
 
+#define RCC_RTCCLKSource_HSE_Div8   ((uint32_t)0x00080300)
 
+#define RCC_RTCCLKSource_HSE_Div9   ((uint32_t)0x00090300)
 
+#define RCC_RTCCLKSource_HSE_Div10   ((uint32_t)0x000A0300)
 
+#define RCC_RTCCLKSource_HSE_Div11   ((uint32_t)0x000B0300)
 
+#define RCC_RTCCLKSource_HSE_Div12   ((uint32_t)0x000C0300)
 
+#define RCC_RTCCLKSource_HSE_Div13   ((uint32_t)0x000D0300)
 
+#define RCC_RTCCLKSource_HSE_Div14   ((uint32_t)0x000E0300)
 
+#define RCC_RTCCLKSource_HSE_Div15   ((uint32_t)0x000F0300)
 
+#define RCC_RTCCLKSource_HSE_Div16   ((uint32_t)0x00100300)
 
+#define RCC_RTCCLKSource_HSE_Div17   ((uint32_t)0x00110300)
 
+#define RCC_RTCCLKSource_HSE_Div18   ((uint32_t)0x00120300)
 
+#define RCC_RTCCLKSource_HSE_Div19   ((uint32_t)0x00130300)
 
+#define RCC_RTCCLKSource_HSE_Div20   ((uint32_t)0x00140300)
 
+#define RCC_RTCCLKSource_HSE_Div21   ((uint32_t)0x00150300)
 
+#define RCC_RTCCLKSource_HSE_Div22   ((uint32_t)0x00160300)
 
+#define RCC_RTCCLKSource_HSE_Div23   ((uint32_t)0x00170300)
 
+#define RCC_RTCCLKSource_HSE_Div24   ((uint32_t)0x00180300)
 
+#define RCC_RTCCLKSource_HSE_Div25   ((uint32_t)0x00190300)
 
+#define RCC_RTCCLKSource_HSE_Div26   ((uint32_t)0x001A0300)
 
+#define RCC_RTCCLKSource_HSE_Div27   ((uint32_t)0x001B0300)
 
+#define RCC_RTCCLKSource_HSE_Div28   ((uint32_t)0x001C0300)
 
+#define RCC_RTCCLKSource_HSE_Div29   ((uint32_t)0x001D0300)
 
+#define RCC_RTCCLKSource_HSE_Div30   ((uint32_t)0x001E0300)
 
+#define RCC_RTCCLKSource_HSE_Div31   ((uint32_t)0x001F0300)
 
+#define IS_RCC_RTCCLK_SOURCE(SOURCE)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___r_t_c___clock___source.map b/group___r_c_c___r_t_c___clock___source.map new file mode 100644 index 0000000..aa5b16f --- /dev/null +++ b/group___r_c_c___r_t_c___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___r_t_c___clock___source.md5 b/group___r_c_c___r_t_c___clock___source.md5 new file mode 100644 index 0000000..beb34ed --- /dev/null +++ b/group___r_c_c___r_t_c___clock___source.md5 @@ -0,0 +1 @@ +82e797630cbda36e536ddcca0efb6946 \ No newline at end of file diff --git a/group___r_c_c___r_t_c___clock___source.png b/group___r_c_c___r_t_c___clock___source.png new file mode 100644 index 0000000..32f8ac5 Binary files /dev/null and b/group___r_c_c___r_t_c___clock___source.png differ diff --git a/group___r_c_c___s_a_i___block_a___clock___source.html b/group___r_c_c___s_a_i___block_a___clock___source.html new file mode 100644 index 0000000..87d4cbc --- /dev/null +++ b/group___r_c_c___s_a_i___block_a___clock___source.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: RCC_SAI_BlockA_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RCC_SAI_BlockA_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_SAI_BlockA_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RCC_SAIACLKSource_PLLSAI   ((uint32_t)0x00000000)
 
+#define RCC_SAIACLKSource_PLLI2S   ((uint32_t)0x00100000)
 
+#define RCC_SAIACLKSource_Ext   ((uint32_t)0x00200000)
 
#define IS_RCC_SAIACLK_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_SAIACLK_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
+
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
+
((SOURCE) == RCC_SAIACLKSource_Ext))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___s_a_i___block_a___clock___source.map b/group___r_c_c___s_a_i___block_a___clock___source.map new file mode 100644 index 0000000..0534cc8 --- /dev/null +++ b/group___r_c_c___s_a_i___block_a___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___s_a_i___block_a___clock___source.md5 b/group___r_c_c___s_a_i___block_a___clock___source.md5 new file mode 100644 index 0000000..6ae1ea8 --- /dev/null +++ b/group___r_c_c___s_a_i___block_a___clock___source.md5 @@ -0,0 +1 @@ +8efedb35bff8a3903fd217dc31964c9e \ No newline at end of file diff --git a/group___r_c_c___s_a_i___block_a___clock___source.png b/group___r_c_c___s_a_i___block_a___clock___source.png new file mode 100644 index 0000000..d1b6f90 Binary files /dev/null and b/group___r_c_c___s_a_i___block_a___clock___source.png differ diff --git a/group___r_c_c___s_a_i___block_b___clock___source.html b/group___r_c_c___s_a_i___block_b___clock___source.html new file mode 100644 index 0000000..e80a22a --- /dev/null +++ b/group___r_c_c___s_a_i___block_b___clock___source.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: RCC_SAI_BlockB_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
RCC_SAI_BlockB_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_SAI_BlockB_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RCC_SAIBCLKSource_PLLSAI   ((uint32_t)0x00000000)
 
+#define RCC_SAIBCLKSource_PLLI2S   ((uint32_t)0x00400000)
 
+#define RCC_SAIBCLKSource_Ext   ((uint32_t)0x00800000)
 
#define IS_RCC_SAIBCLK_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_SAIBCLK_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
+
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
+
((SOURCE) == RCC_SAIBCLKSource_Ext))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___s_a_i___block_b___clock___source.map b/group___r_c_c___s_a_i___block_b___clock___source.map new file mode 100644 index 0000000..46ba872 --- /dev/null +++ b/group___r_c_c___s_a_i___block_b___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___s_a_i___block_b___clock___source.md5 b/group___r_c_c___s_a_i___block_b___clock___source.md5 new file mode 100644 index 0000000..8777460 --- /dev/null +++ b/group___r_c_c___s_a_i___block_b___clock___source.md5 @@ -0,0 +1 @@ +9319217edef725a5fd95ec92a95cbe49 \ No newline at end of file diff --git a/group___r_c_c___s_a_i___block_b___clock___source.png b/group___r_c_c___s_a_i___block_b___clock___source.png new file mode 100644 index 0000000..2d31cd7 Binary files /dev/null and b/group___r_c_c___s_a_i___block_b___clock___source.png differ diff --git a/group___r_c_c___system___clock___source.html b/group___r_c_c___system___clock___source.html new file mode 100644 index 0000000..d185244 --- /dev/null +++ b/group___r_c_c___system___clock___source.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: RCC_System_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
RCC_System_Clock_Source
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_System_Clock_Source:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RCC_SYSCLKSource_HSI   ((uint32_t)0x00000000)
 
+#define RCC_SYSCLKSource_HSE   ((uint32_t)0x00000001)
 
+#define RCC_SYSCLKSource_PLLCLK   ((uint32_t)0x00000002)
 
#define IS_RCC_SYSCLK_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RCC_SYSCLK_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == RCC_SYSCLKSource_HSI) || \
+
((SOURCE) == RCC_SYSCLKSource_HSE) || \
+
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___system___clock___source.map b/group___r_c_c___system___clock___source.map new file mode 100644 index 0000000..2fddfb0 --- /dev/null +++ b/group___r_c_c___system___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___system___clock___source.md5 b/group___r_c_c___system___clock___source.md5 new file mode 100644 index 0000000..946c03a --- /dev/null +++ b/group___r_c_c___system___clock___source.md5 @@ -0,0 +1 @@ +5edd23f41fb7628805ef0773a53b4413 \ No newline at end of file diff --git a/group___r_c_c___system___clock___source.png b/group___r_c_c___system___clock___source.png new file mode 100644 index 0000000..acf256c Binary files /dev/null and b/group___r_c_c___system___clock___source.png differ diff --git a/group___r_c_c___t_i_m___p_rescaler___selection.html b/group___r_c_c___t_i_m___p_rescaler___selection.html new file mode 100644 index 0000000..0cbdc08 --- /dev/null +++ b/group___r_c_c___t_i_m___p_rescaler___selection.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: RCC_TIM_PRescaler_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
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+ +
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+Macros
+
+
RCC_TIM_PRescaler_Selection
STM32F4xx_StdPeriph_Driver » RCC » RCC_Exported_Constants
+
+
+
+Collaboration diagram for RCC_TIM_PRescaler_Selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RCC_TIMPrescDesactivated   ((uint8_t)0x00)
 
+#define RCC_TIMPrescActivated   ((uint8_t)0x01)
 
+#define IS_RCC_TIMCLK_PRESCALER(VALUE)   (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_c_c___t_i_m___p_rescaler___selection.map b/group___r_c_c___t_i_m___p_rescaler___selection.map new file mode 100644 index 0000000..027e792 --- /dev/null +++ b/group___r_c_c___t_i_m___p_rescaler___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c___t_i_m___p_rescaler___selection.md5 b/group___r_c_c___t_i_m___p_rescaler___selection.md5 new file mode 100644 index 0000000..9c0522b --- /dev/null +++ b/group___r_c_c___t_i_m___p_rescaler___selection.md5 @@ -0,0 +1 @@ +88b31533811b31acb21e5c01aab4ecbb \ No newline at end of file diff --git a/group___r_c_c___t_i_m___p_rescaler___selection.png b/group___r_c_c___t_i_m___p_rescaler___selection.png new file mode 100644 index 0000000..7d80d39 Binary files /dev/null and b/group___r_c_c___t_i_m___p_rescaler___selection.png differ diff --git a/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.map b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.map new file mode 100644 index 0000000..4054673 --- /dev/null +++ b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 new file mode 100644 index 0000000..0d5d302 --- /dev/null +++ b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.md5 @@ -0,0 +1 @@ +22767bb8bd39e9f3284dc08f555cce68 \ No newline at end of file diff --git a/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.png b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.png new file mode 100644 index 0000000..71d8f06 Binary files /dev/null and b/group___r_c_c_ga2897bdc52f272031c44fb1f72205d295_icgraph.png differ diff --git a/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map new file mode 100644 index 0000000..f76737b --- /dev/null +++ b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 new file mode 100644 index 0000000..3fb1ed6 --- /dev/null +++ b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.md5 @@ -0,0 +1 @@ +69e156d895f3de1061b4d5f8ba1b61af \ No newline at end of file diff --git a/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png new file mode 100644 index 0000000..510b5fb Binary files /dev/null and b/group___r_c_c_ga3e9944fd1ed734275222bbb3e3f29993_icgraph.png differ diff --git a/group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph.map b/group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph.map new file mode 100644 index 0000000..45d9f7d --- /dev/null +++ b/group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph.md5 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a/group___r_n_g.html b/group___r_n_g.html new file mode 100644 index 0000000..39710e1 --- /dev/null +++ b/group___r_n_g.html @@ -0,0 +1,423 @@ + + + + + + +discoverpixy: RNG + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Modules | +Functions
+
+
RNG
STM32F4xx_StdPeriph_Driver
+
+
+ +

RNG driver modules. +More...

+
+Collaboration diagram for RNG:
+
+
+ + +
+
+ + + + + + +

+Modules

 RNG_Exported_Constants
 
 RNG_Private_Functions
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RNG_DeInit (void)
 De-initializes the RNG peripheral registers to their default reset values. More...
 
void RNG_Cmd (FunctionalState NewState)
 Enables or disables the RNG peripheral. More...
 
uint32_t RNG_GetRandomNumber (void)
 Returns a 32-bit random number. More...
 
void RNG_ITConfig (FunctionalState NewState)
 Enables or disables the RNG interrupt. More...
 
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
 Checks whether the specified RNG flag is set or not. More...
 
void RNG_ClearFlag (uint8_t RNG_FLAG)
 Clears the RNG flags. More...
 
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
 Checks whether the specified RNG interrupt has occurred or not. More...
 
void RNG_ClearITPendingBit (uint8_t RNG_IT)
 Clears the RNG interrupt pending bit(s). More...
 
+

Detailed Description

+

RNG driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void RNG_ClearFlag (uint8_t RNG_FLAG)
+
+ +

Clears the RNG flags.

+
Parameters
+ + +
RNG_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • RNG_FLAG_CECS: Clock Error Current flag.
    • +
  • RNG_FLAG_SECS: Seed Error Current flag.
    • +
+
+
+
+
Note
RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. This flag is cleared only by reading the Random number data (using RNG_GetRandomNumber() function).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_ClearITPendingBit (uint8_t RNG_IT)
+
+ +

Clears the RNG interrupt pending bit(s).

+
Parameters
+ + +
RNG_ITspecifies the RNG interrupt pending bit(s) to clear. This parameter can be any combination of the following values:
    +
  • RNG_IT_CEI: Clock Error Interrupt.
    • +
  • RNG_IT_SEI: Seed Error Interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the RNG peripheral.

+
Parameters
+ + +
NewStatenew state of the RNG peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_DeInit (void )
+
+ +

De-initializes the RNG peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
+
+ +

Checks whether the specified RNG flag is set or not.

+
Parameters
+ + +
RNG_FLAGspecifies the RNG flag to check. This parameter can be one of the following values:
    +
  • RNG_FLAG_DRDY: Data Ready flag.
    • +
  • RNG_FLAG_CECS: Clock Error Current flag.
    • +
  • RNG_FLAG_SECS: Seed Error Current flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of RNG_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
+
+ +

Checks whether the specified RNG interrupt has occurred or not.

+
Parameters
+ + +
RNG_ITspecifies the RNG interrupt source to check. This parameter can be one of the following values:
    +
  • RNG_IT_CEI: Clock Error Interrupt.
    • +
  • RNG_IT_SEI: Seed Error Interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of RNG_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RNG_GetRandomNumber (void )
+
+ +

Returns a 32-bit random number.

+
Note
Before to call this function you have to wait till DRDY (data ready) flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
+
+Each time the the Random number data is read (using RNG_GetRandomNumber() function), the RNG_FLAG_DRDY flag is automatically cleared.
+
+In the case of a seed error, the generation of random numbers is interrupted for as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable and enable the RNG peripheral (using RNG_Cmd() function) to reinitialize and restart the RNG.
+
+In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User have to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) function) . The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
32-bitrandom number.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_ITConfig (FunctionalState NewState)
+
+ +

Enables or disables the RNG interrupt.

+
Note
The RNG provides 3 interrupt sources,
    +
  • Computed data is ready event (DRDY), and
    • +
  • Seed error Interrupt (SEI) and
    • +
  • Clock error Interrupt (CEI), all these interrupts sources are enabled by setting the IE bit in CR register. However, each interrupt have its specific status bit (see RNG_GetITStatus() function) and clear bit except the DRDY event (see RNG_ClearITPendingBit() function).
    • +
+
+
Parameters
+ + +
NewStatenew state of the RNG interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g.map b/group___r_n_g.map new file mode 100644 index 0000000..0862cf4 --- /dev/null +++ b/group___r_n_g.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_n_g.md5 b/group___r_n_g.md5 new file mode 100644 index 0000000..0932d50 --- /dev/null +++ b/group___r_n_g.md5 @@ -0,0 +1 @@ +8f8711c222b91862b32aee92020992c5 \ No newline at end of file diff --git a/group___r_n_g.png b/group___r_n_g.png new file mode 100644 index 0000000..7ebe88f Binary files /dev/null and b/group___r_n_g.png differ diff --git a/group___r_n_g___exported___constants.html b/group___r_n_g___exported___constants.html new file mode 100644 index 0000000..8a31c80 --- /dev/null +++ b/group___r_n_g___exported___constants.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: RNG_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
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+Modules
+
+
RNG_Exported_Constants
STM32F4xx_StdPeriph_Driver » RNG
+
+
+
+Collaboration diagram for RNG_Exported_Constants:
+
+
+ + +
+
+ + + + + + +

+Modules

 RNG_flags_definition
 
 RNG_interrupts_definition
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g___exported___constants.map b/group___r_n_g___exported___constants.map new file mode 100644 index 0000000..504dedc --- /dev/null +++ b/group___r_n_g___exported___constants.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_n_g___exported___constants.md5 b/group___r_n_g___exported___constants.md5 new file mode 100644 index 0000000..7c81e95 --- /dev/null +++ b/group___r_n_g___exported___constants.md5 @@ -0,0 +1 @@ +cd26b99a0ebb19c64a144ec9bc8ffe96 \ No newline at end of file diff --git a/group___r_n_g___exported___constants.png b/group___r_n_g___exported___constants.png new file mode 100644 index 0000000..1634bf3 Binary files /dev/null and b/group___r_n_g___exported___constants.png differ diff --git a/group___r_n_g___group1.html b/group___r_n_g___group1.html new file mode 100644 index 0000000..159f38e --- /dev/null +++ b/group___r_n_g___group1.html @@ -0,0 +1,191 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » RNG » RNG_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void RNG_DeInit (void)
 De-initializes the RNG peripheral registers to their default reset values. More...
 
void RNG_Cmd (FunctionalState NewState)
 Enables or disables the RNG peripheral. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================  
+ [..] This section provides functions allowing to 
+   (+) Initialize the RNG peripheral
+   (+) Enable or disable the RNG peripheral

Function Documentation

+ +
+
+ + + + + + + + +
void RNG_Cmd (FunctionalState NewState)
+
+ +

Enables or disables the RNG peripheral.

+
Parameters
+ + +
NewStatenew state of the RNG peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_DeInit (void )
+
+ +

De-initializes the RNG peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g___group1.map b/group___r_n_g___group1.map new file mode 100644 index 0000000..eaddf92 --- /dev/null +++ b/group___r_n_g___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g___group1.md5 b/group___r_n_g___group1.md5 new file mode 100644 index 0000000..43363f1 --- /dev/null +++ b/group___r_n_g___group1.md5 @@ -0,0 +1 @@ +d9dac0218d2b01bde076abe28b2c2ee1 \ No newline at end of file diff --git a/group___r_n_g___group1.png b/group___r_n_g___group1.png new file mode 100644 index 0000000..e73b72e Binary files /dev/null and b/group___r_n_g___group1.png differ diff --git a/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.map b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.map new file mode 100644 index 0000000..4976cc5 --- /dev/null +++ b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 new file mode 100644 index 0000000..fe703d5 --- /dev/null +++ b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 @@ -0,0 +1 @@ +f2f057734a7e0ab9fe5ab2a9e1a32112 \ No newline at end of file diff --git a/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.png b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.png new file mode 100644 index 0000000..c83569e Binary files /dev/null and b/group___r_n_g___group1_ga15ff5e649080076eebd51143b9ac4491_cgraph.png differ diff --git a/group___r_n_g___group2.html b/group___r_n_g___group2.html new file mode 100644 index 0000000..06cf065 --- /dev/null +++ b/group___r_n_g___group2.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: Get 32 bit Random number function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
Get 32 bit Random number function
STM32F4xx_StdPeriph_Driver » RNG » RNG_Private_Functions
+
+
+ +

Get 32 bit Random number function. +More...

+
+Collaboration diagram for Get 32 bit Random number function:
+
+
+ + +
+
+ + + + + +

+Functions

uint32_t RNG_GetRandomNumber (void)
 Returns a 32-bit random number. More...
 
+

Detailed Description

+

Get 32 bit Random number function.

+
 ===============================================================================
+                 ##### Get 32 bit Random number function #####
+ ===============================================================================  
+ [..] This section provides a function allowing to get the 32 bit Random number  
+  
+   (@)  Before to call this function you have to wait till DRDY flag is set,
+        using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t RNG_GetRandomNumber (void )
+
+ +

Returns a 32-bit random number.

+
Note
Before to call this function you have to wait till DRDY (data ready) flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
+
+Each time the the Random number data is read (using RNG_GetRandomNumber() function), the RNG_FLAG_DRDY flag is automatically cleared.
+
+In the case of a seed error, the generation of random numbers is interrupted for as long as the SECS bit is '1'. If a number is available in the RNG_DR register, it must not be used because it may not have enough entropy. In this case, it is recommended to clear the SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable and enable the RNG peripheral (using RNG_Cmd() function) to reinitialize and restart the RNG.
+
+In the case of a clock error, the RNG is no more able to generate random numbers because the PLL48CLK clock is not correct. User have to check that the clock controller is correctly configured to provide the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) function) . The clock error has no impact on the previously generated random numbers, and the RNG_DR register contents can be used.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
32-bitrandom number.
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g___group2.map b/group___r_n_g___group2.map new file mode 100644 index 0000000..34631bc --- /dev/null +++ b/group___r_n_g___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g___group2.md5 b/group___r_n_g___group2.md5 new file mode 100644 index 0000000..29bd80a --- /dev/null +++ b/group___r_n_g___group2.md5 @@ -0,0 +1 @@ +b776979116a4f77605c9cf80519e3826 \ No newline at end of file diff --git a/group___r_n_g___group2.png b/group___r_n_g___group2.png new file mode 100644 index 0000000..2be1aac Binary files /dev/null and b/group___r_n_g___group2.png differ diff --git a/group___r_n_g___group3.html b/group___r_n_g___group3.html new file mode 100644 index 0000000..b595b76 --- /dev/null +++ b/group___r_n_g___group3.html @@ -0,0 +1,356 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » RNG » RNG_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void RNG_ITConfig (FunctionalState NewState)
 Enables or disables the RNG interrupt. More...
 
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
 Checks whether the specified RNG flag is set or not. More...
 
void RNG_ClearFlag (uint8_t RNG_FLAG)
 Clears the RNG flags. More...
 
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
 Checks whether the specified RNG interrupt has occurred or not. More...
 
void RNG_ClearITPendingBit (uint8_t RNG_IT)
 Clears the RNG interrupt pending bit(s). More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+             ##### Interrupts and flags management functions #####
+ ===============================================================================  
+
+ [..] This section provides functions allowing to configure the RNG Interrupts and 
+      to get the status and clear flags and Interrupts pending bits.
+  
+ [..] The RNG provides 3 Interrupts sources and 3 Flags:
+  
+ *** Flags : ***
+ ===============
+ [..] 
+    (#) RNG_FLAG_DRDY :  In the case of the RNG_DR register contains valid 
+        random data. it is cleared by reading the valid data(using 
+        RNG_GetRandomNumber() function).
+
+    (#) RNG_FLAG_CECS : In the case of a seed error detection. 
+      
+    (#) RNG_FLAG_SECS : In the case of a clock error detection.
+              
+ *** Interrupts ***
+ ==================
+ [..] If enabled, an RNG interrupt is pending :
+    
+   (#) In the case of the RNG_DR register contains valid random data. 
+       This interrupt source is cleared once the RNG_DR register has been read 
+       (using RNG_GetRandomNumber() function) until a new valid value is 
+       computed; or 
+   (#) In the case of a seed error : One of the following faulty sequences has 
+       been detected:
+       (++) More than 64 consecutive bits at the same value (0 or 1)
+       (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
+       This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
+       function; or
+   (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) 
+       was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
+       cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
+       -@- note In this case, User have to check that the clock controller is 
+           correctly configured to provide the RNG clock. 
+
+ *** Managing the RNG controller events : ***
+ ============================================
+ [..] The user should identify which mode will be used in his application to manage 
+      the RNG controller events: Polling mode or Interrupt mode.
+  
+   (#) In the Polling Mode it is advised to use the following functions:
+       (++) RNG_GetFlagStatus() : to check if flags events occur. 
+       (++) RNG_ClearFlag()     : to clear the flags events.
+  
+       -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only 
+            by reading the Random number data.      
+  
+   (#)  In the Interrupt Mode it is advised to use the following functions:
+        (++) RNG_ITConfig()       : to enable or disable the interrupt source.
+        (++) RNG_GetITStatus()    : to check if Interrupt occurs.
+        (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit 
+             (corresponding Flag).

Function Documentation

+ +
+
+ + + + + + + + +
void RNG_ClearFlag (uint8_t RNG_FLAG)
+
+ +

Clears the RNG flags.

+
Parameters
+ + +
RNG_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • RNG_FLAG_CECS: Clock Error Current flag.
    • +
  • RNG_FLAG_SECS: Seed Error Current flag.
    • +
+
+
+
+
Note
RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. This flag is cleared only by reading the Random number data (using RNG_GetRandomNumber() function).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_ClearITPendingBit (uint8_t RNG_IT)
+
+ +

Clears the RNG interrupt pending bit(s).

+
Parameters
+ + +
RNG_ITspecifies the RNG interrupt pending bit(s) to clear. This parameter can be any combination of the following values:
    +
  • RNG_IT_CEI: Clock Error Interrupt.
    • +
  • RNG_IT_SEI: Seed Error Interrupt.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
+
+ +

Checks whether the specified RNG flag is set or not.

+
Parameters
+ + +
RNG_FLAGspecifies the RNG flag to check. This parameter can be one of the following values:
    +
  • RNG_FLAG_DRDY: Data Ready flag.
    • +
  • RNG_FLAG_CECS: Clock Error Current flag.
    • +
  • RNG_FLAG_SECS: Seed Error Current flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of RNG_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
+
+ +

Checks whether the specified RNG interrupt has occurred or not.

+
Parameters
+ + +
RNG_ITspecifies the RNG interrupt source to check. This parameter can be one of the following values:
    +
  • RNG_IT_CEI: Clock Error Interrupt.
    • +
  • RNG_IT_SEI: Seed Error Interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of RNG_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RNG_ITConfig (FunctionalState NewState)
+
+ +

Enables or disables the RNG interrupt.

+
Note
The RNG provides 3 interrupt sources,
    +
  • Computed data is ready event (DRDY), and
    • +
  • Seed error Interrupt (SEI) and
    • +
  • Clock error Interrupt (CEI), all these interrupts sources are enabled by setting the IE bit in CR register. However, each interrupt have its specific status bit (see RNG_GetITStatus() function) and clear bit except the DRDY event (see RNG_ClearITPendingBit() function).
    • +
+
+
Parameters
+ + +
NewStatenew state of the RNG interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g___group3.map b/group___r_n_g___group3.map new file mode 100644 index 0000000..7755997 --- /dev/null +++ b/group___r_n_g___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g___group3.md5 b/group___r_n_g___group3.md5 new file mode 100644 index 0000000..579dba6 --- /dev/null +++ b/group___r_n_g___group3.md5 @@ -0,0 +1 @@ +f14f9a91ab4f21d916185a2b067f328e \ No newline at end of file diff --git a/group___r_n_g___group3.png b/group___r_n_g___group3.png new file mode 100644 index 0000000..37bb1c4 Binary files /dev/null and b/group___r_n_g___group3.png differ diff --git a/group___r_n_g___private___functions.html b/group___r_n_g___private___functions.html new file mode 100644 index 0000000..f78d84c --- /dev/null +++ b/group___r_n_g___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: RNG_Private_Functions + + + + + + + + + + +
+
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discoverpixy +
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+Modules
+
+
RNG_Private_Functions
STM32F4xx_StdPeriph_Driver » RNG
+
+
+
+Collaboration diagram for RNG_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Get 32 bit Random number function
 Get 32 bit Random number function.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g___private___functions.map b/group___r_n_g___private___functions.map new file mode 100644 index 0000000..f21b6aa --- /dev/null +++ b/group___r_n_g___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___r_n_g___private___functions.md5 b/group___r_n_g___private___functions.md5 new file mode 100644 index 0000000..00c9f6f --- /dev/null +++ b/group___r_n_g___private___functions.md5 @@ -0,0 +1 @@ +46e2e2bf989d15c8c2d814136bd3a918 \ No newline at end of file diff --git a/group___r_n_g___private___functions.png b/group___r_n_g___private___functions.png new file mode 100644 index 0000000..b0acfc6 Binary files /dev/null and b/group___r_n_g___private___functions.png differ diff --git a/group___r_n_g__flags__definition.html b/group___r_n_g__flags__definition.html new file mode 100644 index 0000000..7af3c21 --- /dev/null +++ b/group___r_n_g__flags__definition.html @@ -0,0 +1,198 @@ + + + + + + +discoverpixy: RNG_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
RNG_flags_definition
STM32F4xx_StdPeriph_Driver » RNG » RNG_Exported_Constants
+
+
+
+Collaboration diagram for RNG_flags_definition:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define RNG_FLAG_DRDY   ((uint8_t)0x0001)
 
#define RNG_FLAG_CECS   ((uint8_t)0x0002)
 
#define RNG_FLAG_SECS   ((uint8_t)0x0004)
 
#define IS_RNG_GET_FLAG(RNG_FLAG)
 
#define IS_RNG_CLEAR_FLAG(RNG_FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RNG_CLEAR_FLAG( RNG_FLAG)
+
+Value:
(((RNG_FLAG) == RNG_FLAG_CECS) || \
+
((RNG_FLAG) == RNG_FLAG_SECS))
+
RNG_FLAG_SECS
#define RNG_FLAG_SECS
Definition: stm32f4xx_rng.h:60
+
RNG_FLAG_CECS
#define RNG_FLAG_CECS
Definition: stm32f4xx_rng.h:59
+
+
+
+ +
+
+ + + + + + + + +
#define IS_RNG_GET_FLAG( RNG_FLAG)
+
+Value:
(((RNG_FLAG) == RNG_FLAG_DRDY) || \
+
((RNG_FLAG) == RNG_FLAG_CECS) || \
+
((RNG_FLAG) == RNG_FLAG_SECS))
+
RNG_FLAG_SECS
#define RNG_FLAG_SECS
Definition: stm32f4xx_rng.h:60
+
RNG_FLAG_CECS
#define RNG_FLAG_CECS
Definition: stm32f4xx_rng.h:59
+
RNG_FLAG_DRDY
#define RNG_FLAG_DRDY
Definition: stm32f4xx_rng.h:58
+
+
+
+ +
+
+ + + + +
#define RNG_FLAG_CECS   ((uint8_t)0x0002)
+
+

Clock error current status

+ +
+
+ +
+
+ + + + +
#define RNG_FLAG_DRDY   ((uint8_t)0x0001)
+
+

Data ready

+ +
+
+ +
+
+ + + + +
#define RNG_FLAG_SECS   ((uint8_t)0x0004)
+
+

Seed error current status

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g__flags__definition.map b/group___r_n_g__flags__definition.map new file mode 100644 index 0000000..07d2600 --- /dev/null +++ b/group___r_n_g__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g__flags__definition.md5 b/group___r_n_g__flags__definition.md5 new file mode 100644 index 0000000..8d12f31 --- /dev/null +++ b/group___r_n_g__flags__definition.md5 @@ -0,0 +1 @@ +d5efb16aa504a933e5098be057f08967 \ No newline at end of file diff --git a/group___r_n_g__flags__definition.png b/group___r_n_g__flags__definition.png new file mode 100644 index 0000000..ec3a016 Binary files /dev/null and b/group___r_n_g__flags__definition.png differ diff --git a/group___r_n_g__interrupts__definition.html b/group___r_n_g__interrupts__definition.html new file mode 100644 index 0000000..03d1a83 --- /dev/null +++ b/group___r_n_g__interrupts__definition.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: RNG_interrupts_definition + + + + + + + + + + +
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RNG_interrupts_definition
STM32F4xx_StdPeriph_Driver » RNG » RNG_Exported_Constants
+
+
+
+Collaboration diagram for RNG_interrupts_definition:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define RNG_IT_CEI   ((uint8_t)0x20)
 
#define RNG_IT_SEI   ((uint8_t)0x40)
 
+#define IS_RNG_IT(IT)   ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
 
+#define IS_RNG_GET_IT(RNG_IT)   (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define RNG_IT_CEI   ((uint8_t)0x20)
+
+

Clock error interrupt

+ +
+
+ +
+
+ + + + +
#define RNG_IT_SEI   ((uint8_t)0x40)
+
+

Seed error interrupt

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_n_g__interrupts__definition.map b/group___r_n_g__interrupts__definition.map new file mode 100644 index 0000000..a93b1bc --- /dev/null +++ b/group___r_n_g__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g__interrupts__definition.md5 b/group___r_n_g__interrupts__definition.md5 new file mode 100644 index 0000000..6a4816f --- /dev/null +++ b/group___r_n_g__interrupts__definition.md5 @@ -0,0 +1 @@ +99a4543bfdb8bed23a55ee8955db49d0 \ No newline at end of file diff --git a/group___r_n_g__interrupts__definition.png b/group___r_n_g__interrupts__definition.png new file mode 100644 index 0000000..551d5c3 Binary files /dev/null and b/group___r_n_g__interrupts__definition.png differ diff --git a/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.map b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.map new file mode 100644 index 0000000..4976cc5 --- /dev/null +++ b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 new file mode 100644 index 0000000..fe703d5 --- /dev/null +++ b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.md5 @@ -0,0 +1 @@ +f2f057734a7e0ab9fe5ab2a9e1a32112 \ No newline at end of file diff --git a/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.png b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.png new file mode 100644 index 0000000..c83569e Binary files /dev/null and b/group___r_n_g_ga15ff5e649080076eebd51143b9ac4491_cgraph.png differ diff --git a/group___r_t_c.html b/group___r_t_c.html new file mode 100644 index 0000000..7a87065 --- /dev/null +++ b/group___r_t_c.html @@ -0,0 +1,2622 @@ + + + + + + +discoverpixy: RTC + + + + + + + + + + +
+
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+Modules | +Classes | +Macros | +Functions
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+
RTC
STM32F4xx_StdPeriph_Driver
+
+
+ +

RTC driver modules. +More...

+
+Collaboration diagram for RTC:
+
+
+ + +
+
+ + + + + + +

+Modules

 RTC_Exported_Constants
 
 RTC_Private_Functions
 
+ + + + + + + + + + + + + +

+Classes

struct  RTC_InitTypeDef
 RTC Init structures definition. More...
 
struct  RTC_TimeTypeDef
 RTC Time structure definition. More...
 
struct  RTC_DateTypeDef
 RTC Date structure definition. More...
 
struct  RTC_AlarmTypeDef
 RTC Alarm structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_TR_RESERVED_MASK   ((uint32_t)0x007F7F7F)
 
+#define RTC_DR_RESERVED_MASK   ((uint32_t)0x00FFFF3F)
 
+#define RTC_INIT_MASK   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_RSF_MASK   ((uint32_t)0xFFFFFF5F)
 
#define RTC_FLAGS_MASK
 
+#define INITMODE_TIMEOUT   ((uint32_t) 0x00010000)
 
+#define SYNCHRO_TIMEOUT   ((uint32_t) 0x00020000)
 
+#define RECALPF_TIMEOUT   ((uint32_t) 0x00020000)
 
+#define SHPF_TIMEOUT   ((uint32_t) 0x00001000)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_DeInit (void)
 Deinitializes the RTC registers to their default reset values. More...
 
ErrorStatus RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
 Initializes the RTC registers according to the specified parameters in RTC_InitStruct. More...
 
void RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
 Fills each RTC_InitStruct member with its default value. More...
 
void RTC_WriteProtectionCmd (FunctionalState NewState)
 Enables or disables the RTC registers write protection. More...
 
ErrorStatus RTC_EnterInitMode (void)
 Enters the RTC Initialization mode. More...
 
void RTC_ExitInitMode (void)
 Exits the RTC Initialization mode. More...
 
ErrorStatus RTC_WaitForSynchro (void)
 Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock. More...
 
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
 Enables or disables the RTC reference clock detection. More...
 
void RTC_BypassShadowCmd (FunctionalState NewState)
 Enables or Disables the Bypass Shadow feature. More...
 
ErrorStatus RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Set the RTC current time. More...
 
void RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
 Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec). More...
 
void RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Get the RTC current Time. More...
 
uint32_t RTC_GetSubSecond (void)
 Gets the RTC current Calendar Sub seconds value. More...
 
ErrorStatus RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Set the RTC current date. More...
 
void RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
 Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00). More...
 
void RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Get the RTC current date. More...
 
void RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Set the specified RTC Alarm. More...
 
void RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
 Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked). More...
 
void RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Get the RTC Alarm value and masks. More...
 
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
 Enables or disables the specified RTC Alarm. More...
 
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
 Configure the RTC AlarmA/B Sub seconds value and mask.*. More...
 
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
 Gets the RTC Alarm Sub seconds value. More...
 
void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
 Configures the RTC Wakeup clock source. More...
 
void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
 Configures the RTC Wakeup counter. More...
 
uint32_t RTC_GetWakeUpCounter (void)
 Returns the RTC WakeUp timer counter value. More...
 
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
 Enables or Disables the RTC WakeUp timer. More...
 
void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
 Adds or substract one hour from the current time. More...
 
uint32_t RTC_GetStoreOperation (void)
 Returns the RTC Day Light Saving stored operation. More...
 
void RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
 Configures the RTC output source (AFO_ALARM). More...
 
ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
 Configures the Coarse calibration parameters. More...
 
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
 Enables or disables the Coarse calibration process. More...
 
void RTC_CalibOutputCmd (FunctionalState NewState)
 Enables or disables the RTC clock to be output through the relative pin. More...
 
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
 Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). More...
 
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
 Configures the Smooth Calibration Settings. More...
 
void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
 Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge. More...
 
void RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
 Get the RTC TimeStamp value and masks. More...
 
uint32_t RTC_GetTimeStampSubSecond (void)
 Get the RTC timestamp Sub seconds value. More...
 
void RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
 Configures the select Tamper pin edge. More...
 
void RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
 Enables or Disables the Tamper detection. More...
 
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
 Configures the Tampers Filter. More...
 
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
 Configures the Tampers Sampling Frequency. More...
 
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
 Configures the Tampers Pins input Precharge Duration. More...
 
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
 Enables or Disables the TimeStamp on Tamper Detection Event. More...
 
void RTC_TamperPullUpCmd (FunctionalState NewState)
 Enables or Disables the Precharge of Tamper pin. More...
 
void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
 Writes a data in a specified RTC Backup data register. More...
 
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
 Reads data from the specified RTC Backup data Register. More...
 
void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
 Selects the RTC Tamper Pin. More...
 
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
 Selects the RTC TimeStamp Pin. More...
 
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
 Configures the RTC Output Pin mode. More...
 
ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
 Configures the Synchronization Shift Control Settings. More...
 
void RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
 Enables or disables the specified RTC interrupts. More...
 
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
 Checks whether the specified RTC flag is set or not. More...
 
void RTC_ClearFlag (uint32_t RTC_FLAG)
 Clears the RTC's pending flags. More...
 
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
 Checks whether the specified RTC interrupt has occurred or not. More...
 
void RTC_ClearITPendingBit (uint32_t RTC_IT)
 Clears the RTC's interrupt pending bits. More...
 
+

Detailed Description

+

RTC driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define RTC_FLAGS_MASK
+
+Value:
((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RTC Alarm.

+
Parameters
+ + + +
RTC_Alarmspecifies the alarm to be configured. This parameter can be any combination of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
NewStatenew state of the specified alarm. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Alarm is enabled/disabled
    • +
  • ERROR: RTC Alarm is not enabled/disabled
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_AlarmStructInit (RTC_AlarmTypeDef * RTC_AlarmStruct)
+
+ +

Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).

+
Parameters
+ + +
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm,
uint32_t RTC_AlarmSubSecondValue,
uint32_t RTC_AlarmSubSecondMask 
)
+
+ +

Configure the RTC AlarmA/B Sub seconds value and mask.*.

+
Note
This function is performed only when the Alarm is disabled.
+
Parameters
+ + + + +
RTC_Alarmspecifies the alarm to be configured. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmSubSecondValuespecifies the Sub seconds value. This parameter can be a value from 0 to 0x00007FFF.
RTC_AlarmSubSecondMaskspecifies the Sub seconds Mask. This parameter can be any combination of the following values:
    +
  • RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm.
    • +
  • RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared
    • +
  • RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared
    • +
  • RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match to activate alarm
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_BypassShadowCmd (FunctionalState NewState)
+
+ +

Enables or Disables the Bypass Shadow feature.

+
Note
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
+
Parameters
+ + +
NewStatenew state of the Bypass Shadow feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_CalibOutputCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC clock to be output through the relative pin.

+
Parameters
+ + +
NewStatenew state of the digital calibration Output. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
+
+ +

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

+
Parameters
+ + +
RTC_CalibOutput: Select the Calibration output Selection . This parameter can be one of the following values:
    +
  • RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
    • +
  • RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_ClearFlag (uint32_t RTC_FLAG)
+
+ +

Clears the RTC's pending flags.

+
Parameters
+ + +
RTC_FLAGspecifies the RTC flag to clear. This parameter can be any combination of the following values:
    +
  • RTC_FLAG_TAMP1F: Tamper 1 event flag
    • +
  • RTC_FLAG_TSOVF: Time Stamp Overflow flag
    • +
  • RTC_FLAG_TSF: Time Stamp event flag
    • +
  • RTC_FLAG_WUTF: WakeUp Timer flag
    • +
  • RTC_FLAG_ALRBF: Alarm B flag
    • +
  • RTC_FLAG_ALRAF: Alarm A flag
    • +
  • RTC_FLAG_RSF: Registers Synchronized flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_ClearITPendingBit (uint32_t RTC_IT)
+
+ +

Clears the RTC's interrupt pending bits.

+
Parameters
+ + +
RTC_ITspecifies the RTC interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt
    • +
  • RTC_IT_ALRB: Alarm B interrupt
    • +
  • RTC_IT_ALRA: Alarm A interrupt
    • +
  • RTC_IT_TAMP1: Tamper 1 event interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
+
+ +

Enables or disables the Coarse calibration process.

+
Parameters
+ + +
NewStatenew state of the Coarse calibration. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Coarse calibration are enabled/disabled
    • +
  • ERROR: RTC Coarse calibration are not enabled/disabled
    • +
+
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ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign,
uint32_t Value 
)
+
+ +

Configures the Coarse calibration parameters.

+
Parameters
+ + + +
RTC_CalibSignspecifies the sign of the coarse calibration value. This parameter can be one of the following values:
    +
  • RTC_CalibSign_Positive: The value sign is positive
    • +
  • RTC_CalibSign_Negative: The value sign is negative
    • +
+
Valuevalue of coarse calibration expressed in ppm (coded on 5 bits).
+
+
+
Note
This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
+
+This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Coarse calibration are initialized
    • +
  • ERROR: RTC Coarse calibration are not initialized
    • +
+
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void RTC_DateStructInit (RTC_DateTypeDef * RTC_DateStruct)
+
+ +

Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).

+
Parameters
+ + +
RTC_DateStructpointer to a RTC_DateTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving,
uint32_t RTC_StoreOperation 
)
+
+ +

Adds or substract one hour from the current time.

+
Parameters
+ + + +
RTC_DayLightSaveOperationthe value of hour adjustment. This parameter can be one of the following values:
    +
  • RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
    • +
  • RTC_DayLightSaving_ADD1H: Add one hour (summer time)
    • +
+
RTC_StoreOperationSpecifies the value to be written in the BCK bit in CR register to store the operation. This parameter can be one of the following values:
    +
  • RTC_StoreOperation_Reset: BCK Bit Reset
    • +
  • RTC_StoreOperation_Set: BCK Bit Set
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_DeInit (void )
+
+ +

Deinitializes the RTC registers to their default reset values.

+
Note
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are deinitialized
    • +
  • ERROR: RTC registers are not deinitialized
    • +
+
+
+
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ErrorStatus RTC_EnterInitMode (void )
+
+ +

Enters the RTC Initialization mode.

+
Note
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC is in Init mode
    • +
  • ERROR: RTC is not in Init mode
    • +
+
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void RTC_ExitInitMode (void )
+
+ +

Exits the RTC Initialization mode.

+
Note
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
+
+The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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void RTC_GetAlarm (uint32_t RTC_Format,
uint32_t RTC_Alarm,
RTC_AlarmTypeDef * RTC_AlarmStruct 
)
+
+ +

Get the RTC Alarm value and masks.

+
Parameters
+ + + + +
RTC_Formatspecifies the format of the output parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_Alarmspecifies the alarm to be read. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure that will contains the output alarm configuration values.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
+
+ +

Gets the RTC Alarm Sub seconds value.

+
Parameters
+ + + +
RTC_Alarmspecifies the alarm to be read. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
None
+
+
+
Return values
+ + +
RTCAlarm Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_GetDate (uint32_t RTC_Format,
RTC_DateTypeDef * RTC_DateStruct 
)
+
+ +

Get the RTC current date.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_DateStructpointer to a RTC_DateTypeDef structure that will contain the returned current date configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
+
+ +

Checks whether the specified RTC flag is set or not.

+
Parameters
+ + +
RTC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • RTC_FLAG_RECALPF: RECALPF event flag.
    • +
  • RTC_FLAG_TAMP1F: Tamper 1 event flag
    • +
  • RTC_FLAG_TSOVF: Time Stamp OverFlow flag
    • +
  • RTC_FLAG_TSF: Time Stamp event flag
    • +
  • RTC_FLAG_WUTF: WakeUp Timer flag
    • +
  • RTC_FLAG_ALRBF: Alarm B flag
    • +
  • RTC_FLAG_ALRAF: Alarm A flag
    • +
  • RTC_FLAG_INITF: Initialization mode flag
    • +
  • RTC_FLAG_RSF: Registers Synchronized flag
    • +
  • RTC_FLAG_INITS: Registers Configured flag
    • +
  • RTC_FLAG_SHPF: Shift operation pending flag.
    • +
  • RTC_FLAG_WUTWF: WakeUp Timer Write flag
    • +
  • RTC_FLAG_ALRBWF: Alarm B Write flag
    • +
  • RTC_FLAG_ALRAWF: Alarm A write flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of RTC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
+
+ +

Checks whether the specified RTC interrupt has occurred or not.

+
Parameters
+ + +
RTC_ITspecifies the RTC interrupt source to check. This parameter can be one of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt
    • +
  • RTC_IT_ALRB: Alarm B interrupt
    • +
  • RTC_IT_ALRA: Alarm A interrupt
    • +
  • RTC_IT_TAMP1: Tamper 1 event interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of RTC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetStoreOperation (void )
+
+ +

Returns the RTC Day Light Saving stored operation.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCDay Light Saving stored operation.
    +
  • RTC_StoreOperation_Reset
    • +
  • RTC_StoreOperation_Set
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetSubSecond (void )
+
+ +

Gets the RTC current Calendar Sub seconds value.

+
Note
This function freeze the Time and Date registers after reading the SSR register.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCcurrent Calendar Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_GetTime (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_TimeStruct 
)
+
+ +

Get the RTC current Time.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_TimeStructpointer to a RTC_TimeTypeDef structure that will contain the returned current time configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_GetTimeStamp (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_StampTimeStruct,
RTC_DateTypeDef * RTC_StampDateStruct 
)
+
+ +

Get the RTC TimeStamp value and masks.

+
Parameters
+ + + + +
RTC_Formatspecifies the format of the output parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_StampTimeStructpointer to a RTC_TimeTypeDef structure that will contains the TimeStamp time values.
RTC_StampDateStructpointer to a RTC_DateTypeDef structure that will contains the TimeStamp date values.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetTimeStampSubSecond (void )
+
+ +

Get the RTC timestamp Sub seconds value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCcurrent timestamp Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetWakeUpCounter (void )
+
+ +

Returns the RTC WakeUp timer counter value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheRTC WakeUp Counter value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_Init (RTC_InitTypeDef * RTC_InitStruct)
+
+ +

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

+
Parameters
+ + +
RTC_InitStructpointer to a RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
+
+
+
Note
The RTC Prescaler register is write protected and can be written in initialization mode only.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are initialized
    • +
  • ERROR: RTC registers are not initialized
    • +
+
+
+
+ +

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void RTC_ITConfig (uint32_t RTC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RTC interrupts.

+
Parameters
+ + + +
RTC_ITspecifies the RTC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt mask
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt mask
    • +
  • RTC_IT_ALRB: Alarm B interrupt mask
    • +
  • RTC_IT_ALRA: Alarm A interrupt mask
    • +
  • RTC_IT_TAMP: Tamper event interrupt mask
    • +
+
NewStatenew state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_OutputConfig (uint32_t RTC_Output,
uint32_t RTC_OutputPolarity 
)
+
+ +

Configures the RTC output source (AFO_ALARM).

+
Parameters
+ + + +
RTC_OutputSpecifies which signal will be routed to the RTC output. This parameter can be one of the following values:
    +
  • RTC_Output_Disable: No output selected
    • +
  • RTC_Output_AlarmA: signal of AlarmA mapped to output
    • +
  • RTC_Output_AlarmB: signal of AlarmB mapped to output
    • +
  • RTC_Output_WakeUp: signal of WakeUp mapped to output
    • +
+
RTC_OutputPolaritySpecifies the polarity of the output signal. This parameter can be one of the following:
    +
  • RTC_OutputPolarity_High: The output pin is high when the ALRAF/ALRBF/WUTF is high (depending on OSEL)
    • +
  • RTC_OutputPolarity_Low: The output pin is low when the ALRAF/ALRBF/WUTF is high (depending on OSEL)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
+
+ +

Configures the RTC Output Pin mode.

+
Parameters
+ + +
RTC_OutputTypespecifies the RTC Output (PC13) pin mode. This parameter can be one of the following values:
    +
  • RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in Open Drain mode.
    • +
  • RTC_OutputType_PushPull: RTC Output (PC13) is configured in Push Pull mode.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
+
+ +

Reads data from the specified RTC Backup data Register.

+
Parameters
+ + +
RTC_BKP_DRRTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC reference clock detection.

+
Parameters
+ + +
NewStatenew state of the RTC reference clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC reference clock detection is enabled
    • +
  • ERROR: RTC reference clock detection is disabled
    • +
+
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void RTC_SetAlarm (uint32_t RTC_Format,
uint32_t RTC_Alarm,
RTC_AlarmTypeDef * RTC_AlarmStruct 
)
+
+ +

Set the specified RTC Alarm.

+
Note
The Alarm register can only be written when the corresponding Alarm is disabled (Use the RTC_AlarmCmd(DISABLE)).
+
Parameters
+ + + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_Alarmspecifies the alarm to be configured. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SetDate (uint32_t RTC_Format,
RTC_DateTypeDef * RTC_DateStruct 
)
+
+ +

Set the RTC current date.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the entered parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_DateStructpointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Date register is configured
    • +
  • ERROR: RTC Date register is not configured
    • +
+
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ErrorStatus RTC_SetTime (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_TimeStruct 
)
+
+ +

Set the RTC current time.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the entered parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_TimeStructpointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Time register is configured
    • +
  • ERROR: RTC Time register is not configured
    • +
+
+
+
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void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
+
+ +

Configures the RTC Wakeup counter.

+
Note
The RTC WakeUp counter can only be written when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+
Parameters
+ + +
RTC_WakeUpCounterspecifies the WakeUp counter. This parameter can be a value from 0x0000 to 0xFFFF.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod,
uint32_t RTC_SmoothCalibPlusPulses,
uint32_t RTC_SmouthCalibMinusPulsesValue 
)
+
+ +

Configures the Smooth Calibration Settings.

+
Parameters
+ + + + +
RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. This parameter can be can be one of the following values:
    +
  • RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s.
    • +
  • RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s.
    • +
  • RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s.
    • +
+
RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. This parameter can be one of the following values:
    +
  • RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
    • +
  • RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
    • +
+
RTC_SmouthCalibMinusPulsesValueSelect the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Calib registers are configured
    • +
  • ERROR: RTC Calib registers are not configured
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_StructInit (RTC_InitTypeDef * RTC_InitStruct)
+
+ +

Fills each RTC_InitStruct member with its default value.

+
Parameters
+ + +
RTC_InitStructpointer to a RTC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S,
uint32_t RTC_ShiftSubFS 
)
+
+ +

Configures the Synchronization Shift Control Settings.

+
Note
When REFCKON is set, firmware must not write to Shift control register
+
Parameters
+ + + +
RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. This parameter can be one of the following values :
    +
  • RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
    • +
  • RTC_ShiftAdd1S_Reset: No effect.
    • +
+
RTC_ShiftSubFSSelect the number of Second Fractions to Substitute. This parameter can be one any value from 0 to 0x7FFF.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Shift registers are configured
    • +
  • ERROR: RTC Shift registers are not configured
    • +
+
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+
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void RTC_TamperCmd (uint32_t RTC_Tamper,
FunctionalState NewState 
)
+
+ +

Enables or Disables the Tamper detection.

+
Parameters
+ + + +
RTC_TamperSelected tamper pin. This parameter can be RTC_Tamper_1.
NewStatenew state of the tamper pin. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
+
+ +

Configures the Tampers Filter.

+
Parameters
+ + +
RTC_TamperFilterSpecifies the tampers filter. This parameter can be one of the following values:
    +
  • RTC_TamperFilter_Disable: Tamper filter is disabled.
    • +
  • RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive samples at the active level
    • +
  • RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive samples at the active level
    • +
  • RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive samples at the active level
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
+
+ +

Selects the RTC Tamper Pin.

+
Parameters
+ + +
RTC_TamperPinspecifies the RTC Tamper Pin. This parameter can be one of the following values:
    +
  • RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
    • +
  • RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
+
+ +

Configures the Tampers Pins input Precharge Duration.

+
Parameters
+ + +
RTC_TamperPrechargeDurationSpecifies the Tampers Pins input Precharge Duration. This parameter can be one of the following values:
    +
  • RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPullUpCmd (FunctionalState NewState)
+
+ +

Enables or Disables the Precharge of Tamper pin.

+
Parameters
+ + +
NewStatenew state of tamper pull up. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
+
+ +

Configures the Tampers Sampling Frequency.

+
Parameters
+ + +
RTC_TamperSamplingFreqSpecifies the tampers Sampling Frequency. This parameter can be one of the following values:
    +
  • RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled with a frequency = RTCCLK / 512
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled with a frequency = RTCCLK / 256
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_TamperTriggerConfig (uint32_t RTC_Tamper,
uint32_t RTC_TamperTrigger 
)
+
+ +

Configures the select Tamper pin edge.

+
Parameters
+ + + +
RTC_TamperSelected tamper pin. This parameter can be RTC_Tamper_1.
RTC_TamperTriggerSpecifies the trigger on the tamper pin that stimulates tamper event. This parameter can be one of the following values:
    +
  • RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge,
FunctionalState NewState 
)
+
+ +

Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.

+
Parameters
+ + + +
RTC_TimeStampEdgeSpecifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following:
    +
  • RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising edge of the related pin.
    • +
  • RTC_TimeStampEdge_Falling: the Time stamp event occurs on the falling edge of the related pin.
    • +
+
NewStatenew state of the TimeStamp. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
+
+ +

Enables or Disables the TimeStamp on Tamper Detection Event.

+
Note
The timestamp is valid even the TSE bit in tamper control register is reset.
+
Parameters
+ + +
NewStatenew state of the timestamp on tamper event. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
+
+ +

Selects the RTC TimeStamp Pin.

+
Parameters
+ + +
RTC_TimeStampPinspecifies the RTC TimeStamp Pin. This parameter can be one of the following values:
    +
  • RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
    • +
  • RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStructInit (RTC_TimeTypeDef * RTC_TimeStruct)
+
+ +

Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).

+
Parameters
+ + +
RTC_TimeStructpointer to a RTC_TimeTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_WaitForSynchro (void )
+
+ +

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

+
Note
The RTC Resynchronization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
+To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are synchronised
    • +
  • ERROR: RTC registers are not synchronised
    • +
+
+
+
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void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
+
+ +

Configures the RTC Wakeup clock source.

+
Note
The WakeUp Clock source can only be changed when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+
Parameters
+ + +
RTC_WakeUpClockWakeup Clock source. This parameter can be one of the following values:
    +
  • RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
    • +
  • RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
    • +
  • RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
    • +
  • RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
    • +
  • RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
    • +
  • RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
+
+ +

Enables or Disables the RTC WakeUp timer.

+
Parameters
+ + +
NewStatenew state of the WakeUp timer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR,
uint32_t Data 
)
+
+ +

Writes a data in a specified RTC Backup data register.

+
Parameters
+ + + +
RTC_BKP_DRRTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
DataData to be written in the specified RTC Backup data register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_WriteProtectionCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC registers write protection.

+
Note
All the RTC registers are write protected except for RTC_ISR[13:8], RTC_TAFCR and RTC_BKPxR.
+
+Writing a wrong key reactivates the write protection.
+
+The protection mechanism is not affected by system reset.
+
Parameters
+ + +
NewStatenew state of the write protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c.map b/group___r_t_c.map new file mode 100644 index 0000000..d9ffc16 --- /dev/null +++ b/group___r_t_c.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_t_c.md5 b/group___r_t_c.md5 new file mode 100644 index 0000000..07f4ed4 --- /dev/null +++ b/group___r_t_c.md5 @@ -0,0 +1 @@ +5a2a416d236a5b5c8c1302d114c44b9c \ No newline at end of file diff --git a/group___r_t_c.png b/group___r_t_c.png new file mode 100644 index 0000000..e13920c Binary files /dev/null and b/group___r_t_c.png differ diff --git a/group___r_t_c___a_m___p_m___definitions.html b/group___r_t_c___a_m___p_m___definitions.html new file mode 100644 index 0000000..7a0b505 --- /dev/null +++ b/group___r_t_c___a_m___p_m___definitions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: RTC_AM_PM_Definitions + + + + + + + + + + +
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RTC_AM_PM_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
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+Collaboration diagram for RTC_AM_PM_Definitions:
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+Macros

+#define RTC_H12_AM   ((uint8_t)0x00)
 
+#define RTC_H12_PM   ((uint8_t)0x40)
 
+#define IS_RTC_H12(PM)   (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___a_m___p_m___definitions.map b/group___r_t_c___a_m___p_m___definitions.map new file mode 100644 index 0000000..082d9c7 --- /dev/null +++ b/group___r_t_c___a_m___p_m___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___a_m___p_m___definitions.md5 b/group___r_t_c___a_m___p_m___definitions.md5 new file mode 100644 index 0000000..28f03c5 --- /dev/null +++ b/group___r_t_c___a_m___p_m___definitions.md5 @@ -0,0 +1 @@ +1f672054b6d13ea9ff2e04d803c9df86 \ No newline at end of file diff --git a/group___r_t_c___a_m___p_m___definitions.png b/group___r_t_c___a_m___p_m___definitions.png new file mode 100644 index 0000000..3eec7ab Binary files /dev/null and b/group___r_t_c___a_m___p_m___definitions.png differ diff --git a/group___r_t_c___add__1___second___parameter___definitions.html b/group___r_t_c___add__1___second___parameter___definitions.html new file mode 100644 index 0000000..dc6772c --- /dev/null +++ b/group___r_t_c___add__1___second___parameter___definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Add_1_Second_Parameter_Definitions + + + + + + + + + + +
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RTC_Add_1_Second_Parameter_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Add_1_Second_Parameter_Definitions:
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+
+ + +
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+ + + + + + + + +

+Macros

+#define RTC_ShiftAdd1S_Reset   ((uint32_t)0x00000000)
 
+#define RTC_ShiftAdd1S_Set   ((uint32_t)0x80000000)
 
#define IS_RTC_SHIFT_ADD1S(SEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_SHIFT_ADD1S( SEL)
+
+Value:
(((SEL) == RTC_ShiftAdd1S_Reset) || \
+
((SEL) == RTC_ShiftAdd1S_Set))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___add__1___second___parameter___definitions.map b/group___r_t_c___add__1___second___parameter___definitions.map new file mode 100644 index 0000000..56888ae --- /dev/null +++ b/group___r_t_c___add__1___second___parameter___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___add__1___second___parameter___definitions.md5 b/group___r_t_c___add__1___second___parameter___definitions.md5 new file mode 100644 index 0000000..14db904 --- /dev/null +++ b/group___r_t_c___add__1___second___parameter___definitions.md5 @@ -0,0 +1 @@ +d74475c497533eb362186f95e43ee3f9 \ No newline at end of file diff --git a/group___r_t_c___add__1___second___parameter___definitions.png b/group___r_t_c___add__1___second___parameter___definitions.png new file mode 100644 index 0000000..e39e658 Binary files /dev/null and b/group___r_t_c___add__1___second___parameter___definitions.png differ diff --git a/group___r_t_c___alarm___definitions.html b/group___r_t_c___alarm___definitions.html new file mode 100644 index 0000000..2ea73c6 --- /dev/null +++ b/group___r_t_c___alarm___definitions.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: RTC_Alarm_Definitions + + + + + + + + + + +
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+
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+Macros
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+
RTC_Alarm_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Alarm_Definitions:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE)   (((DATE) > 0) && ((DATE) <= 31))
 
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY( WEEKDAY)
+
+Value:
(((WEEKDAY) == RTC_Weekday_Monday) || \
+
((WEEKDAY) == RTC_Weekday_Tuesday) || \
+
((WEEKDAY) == RTC_Weekday_Wednesday) || \
+
((WEEKDAY) == RTC_Weekday_Thursday) || \
+
((WEEKDAY) == RTC_Weekday_Friday) || \
+
((WEEKDAY) == RTC_Weekday_Saturday) || \
+
((WEEKDAY) == RTC_Weekday_Sunday))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarm___definitions.map b/group___r_t_c___alarm___definitions.map new file mode 100644 index 0000000..77deab0 --- /dev/null +++ b/group___r_t_c___alarm___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarm___definitions.md5 b/group___r_t_c___alarm___definitions.md5 new file mode 100644 index 0000000..826a4b2 --- /dev/null +++ b/group___r_t_c___alarm___definitions.md5 @@ -0,0 +1 @@ +f9cb8d6c5ba48c150a2569baac28c213 \ No newline at end of file diff --git a/group___r_t_c___alarm___definitions.png b/group___r_t_c___alarm___definitions.png new file mode 100644 index 0000000..2fb389f Binary files /dev/null and b/group___r_t_c___alarm___definitions.png differ diff --git a/group___r_t_c___alarm___sub___seconds___masks___definitions.html b/group___r_t_c___alarm___sub___seconds___masks___definitions.html new file mode 100644 index 0000000..cbb02d5 --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___masks___definitions.html @@ -0,0 +1,397 @@ + + + + + + +discoverpixy: RTC_Alarm_Sub_Seconds_Masks_Definitions + + + + + + + + + + +
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RTC_Alarm_Sub_Seconds_Masks_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
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+
+
+Collaboration diagram for RTC_Alarm_Sub_Seconds_Masks_Definitions:
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define RTC_AlarmSubSecondMask_All   ((uint32_t)0x00000000)
 
#define RTC_AlarmSubSecondMask_SS14_1   ((uint32_t)0x01000000)
 
#define RTC_AlarmSubSecondMask_SS14_2   ((uint32_t)0x02000000)
 
#define RTC_AlarmSubSecondMask_SS14_3   ((uint32_t)0x03000000)
 
#define RTC_AlarmSubSecondMask_SS14_4   ((uint32_t)0x04000000)
 
#define RTC_AlarmSubSecondMask_SS14_5   ((uint32_t)0x05000000)
 
#define RTC_AlarmSubSecondMask_SS14_6   ((uint32_t)0x06000000)
 
#define RTC_AlarmSubSecondMask_SS14_7   ((uint32_t)0x07000000)
 
#define RTC_AlarmSubSecondMask_SS14_8   ((uint32_t)0x08000000)
 
#define RTC_AlarmSubSecondMask_SS14_9   ((uint32_t)0x09000000)
 
#define RTC_AlarmSubSecondMask_SS14_10   ((uint32_t)0x0A000000)
 
#define RTC_AlarmSubSecondMask_SS14_11   ((uint32_t)0x0B000000)
 
#define RTC_AlarmSubSecondMask_SS14_12   ((uint32_t)0x0C000000)
 
#define RTC_AlarmSubSecondMask_SS14_13   ((uint32_t)0x0D000000)
 
#define RTC_AlarmSubSecondMask_SS14   ((uint32_t)0x0E000000)
 
#define RTC_AlarmSubSecondMask_None   ((uint32_t)0x0F000000)
 
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_ALARM_SUB_SECOND_MASK( MASK)
+
+Value:
(((MASK) == RTC_AlarmSubSecondMask_All) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+
((MASK) == RTC_AlarmSubSecondMask_None))
+
RTC_AlarmSubSecondMask_SS14_5
#define RTC_AlarmSubSecondMask_SS14_5
Definition: stm32f4xx_rtc.h:317
+
RTC_AlarmSubSecondMask_SS14_1
#define RTC_AlarmSubSecondMask_SS14_1
Definition: stm32f4xx_rtc.h:305
+
RTC_AlarmSubSecondMask_SS14_8
#define RTC_AlarmSubSecondMask_SS14_8
Definition: stm32f4xx_rtc.h:326
+
RTC_AlarmSubSecondMask_SS14_9
#define RTC_AlarmSubSecondMask_SS14_9
Definition: stm32f4xx_rtc.h:329
+
RTC_AlarmSubSecondMask_SS14_10
#define RTC_AlarmSubSecondMask_SS14_10
Definition: stm32f4xx_rtc.h:332
+
RTC_AlarmSubSecondMask_SS14
#define RTC_AlarmSubSecondMask_SS14
Definition: stm32f4xx_rtc.h:344
+
RTC_AlarmSubSecondMask_SS14_7
#define RTC_AlarmSubSecondMask_SS14_7
Definition: stm32f4xx_rtc.h:323
+
RTC_AlarmSubSecondMask_SS14_2
#define RTC_AlarmSubSecondMask_SS14_2
Definition: stm32f4xx_rtc.h:308
+
RTC_AlarmSubSecondMask_SS14_6
#define RTC_AlarmSubSecondMask_SS14_6
Definition: stm32f4xx_rtc.h:320
+
RTC_AlarmSubSecondMask_SS14_12
#define RTC_AlarmSubSecondMask_SS14_12
Definition: stm32f4xx_rtc.h:338
+
RTC_AlarmSubSecondMask_All
#define RTC_AlarmSubSecondMask_All
Definition: stm32f4xx_rtc.h:300
+
RTC_AlarmSubSecondMask_SS14_11
#define RTC_AlarmSubSecondMask_SS14_11
Definition: stm32f4xx_rtc.h:335
+
RTC_AlarmSubSecondMask_SS14_13
#define RTC_AlarmSubSecondMask_SS14_13
Definition: stm32f4xx_rtc.h:341
+
RTC_AlarmSubSecondMask_SS14_4
#define RTC_AlarmSubSecondMask_SS14_4
Definition: stm32f4xx_rtc.h:314
+
RTC_AlarmSubSecondMask_None
#define RTC_AlarmSubSecondMask_None
Definition: stm32f4xx_rtc.h:347
+
RTC_AlarmSubSecondMask_SS14_3
#define RTC_AlarmSubSecondMask_SS14_3
Definition: stm32f4xx_rtc.h:311
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#define RTC_AlarmSubSecondMask_All   ((uint32_t)0x00000000)
+
+

All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_None   ((uint32_t)0x0F000000)
+
+

SS[14:0] are compared and must match to activate alarm.

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14   ((uint32_t)0x0E000000)
+
+

SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_1   ((uint32_t)0x01000000)
+
+

SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_10   ((uint32_t)0x0A000000)
+
+

SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_11   ((uint32_t)0x0B000000)
+
+

SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_12   ((uint32_t)0x0C000000)
+
+

SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_13   ((uint32_t)0x0D000000)
+
+

SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_2   ((uint32_t)0x02000000)
+
+

SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_3   ((uint32_t)0x03000000)
+
+

SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_4   ((uint32_t)0x04000000)
+
+

SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_5   ((uint32_t)0x05000000)
+
+

SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_6   ((uint32_t)0x06000000)
+
+

SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_7   ((uint32_t)0x07000000)
+
+

SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_8   ((uint32_t)0x08000000)
+
+

SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared

+ +
+
+ +
+
+ + + + +
#define RTC_AlarmSubSecondMask_SS14_9   ((uint32_t)0x09000000)
+
+

SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarm___sub___seconds___masks___definitions.map b/group___r_t_c___alarm___sub___seconds___masks___definitions.map new file mode 100644 index 0000000..477b778 --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___masks___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarm___sub___seconds___masks___definitions.md5 b/group___r_t_c___alarm___sub___seconds___masks___definitions.md5 new file mode 100644 index 0000000..af3b338 --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___masks___definitions.md5 @@ -0,0 +1 @@ +d83729efb062cb401fb789de74a82215 \ No newline at end of file diff --git a/group___r_t_c___alarm___sub___seconds___masks___definitions.png b/group___r_t_c___alarm___sub___seconds___masks___definitions.png new file mode 100644 index 0000000..c4166f4 Binary files /dev/null and b/group___r_t_c___alarm___sub___seconds___masks___definitions.png differ diff --git a/group___r_t_c___alarm___sub___seconds___value.html b/group___r_t_c___alarm___sub___seconds___value.html new file mode 100644 index 0000000..531a79c --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___value.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Alarm_Sub_Seconds_Value + + + + + + + + + + +
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+Macros
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RTC_Alarm_Sub_Seconds_Value
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Alarm_Sub_Seconds_Value:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE)   ((VALUE) <= 0x00007FFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarm___sub___seconds___value.map b/group___r_t_c___alarm___sub___seconds___value.map new file mode 100644 index 0000000..93d4c05 --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___value.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarm___sub___seconds___value.md5 b/group___r_t_c___alarm___sub___seconds___value.md5 new file mode 100644 index 0000000..a2a23d9 --- /dev/null +++ b/group___r_t_c___alarm___sub___seconds___value.md5 @@ -0,0 +1 @@ +c2d81db510760b8e1da8b7754bbcd910 \ No newline at end of file diff --git a/group___r_t_c___alarm___sub___seconds___value.png b/group___r_t_c___alarm___sub___seconds___value.png new file mode 100644 index 0000000..da3f20f Binary files /dev/null and b/group___r_t_c___alarm___sub___seconds___value.png differ diff --git a/group___r_t_c___alarm_date_week_day___definitions.html b/group___r_t_c___alarm_date_week_day___definitions.html new file mode 100644 index 0000000..4d60a98 --- /dev/null +++ b/group___r_t_c___alarm_date_week_day___definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_AlarmDateWeekDay_Definitions + + + + + + + + + + +
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RTC_AlarmDateWeekDay_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
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+
+
+Collaboration diagram for RTC_AlarmDateWeekDay_Definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_AlarmDateWeekDaySel_Date   ((uint32_t)0x00000000)
 
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
 
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL( SEL)
+
+Value:
(((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarm_date_week_day___definitions.map b/group___r_t_c___alarm_date_week_day___definitions.map new file mode 100644 index 0000000..994ed90 --- /dev/null +++ b/group___r_t_c___alarm_date_week_day___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarm_date_week_day___definitions.md5 b/group___r_t_c___alarm_date_week_day___definitions.md5 new file mode 100644 index 0000000..cf2f9b0 --- /dev/null +++ b/group___r_t_c___alarm_date_week_day___definitions.md5 @@ -0,0 +1 @@ +80cec4ff25d5a7ec710bda7c5ca7f2d3 \ No newline at end of file diff --git a/group___r_t_c___alarm_date_week_day___definitions.png b/group___r_t_c___alarm_date_week_day___definitions.png new file mode 100644 index 0000000..b099caa Binary files /dev/null and b/group___r_t_c___alarm_date_week_day___definitions.png differ diff --git a/group___r_t_c___alarm_mask___definitions.html b/group___r_t_c___alarm_mask___definitions.html new file mode 100644 index 0000000..8e771eb --- /dev/null +++ b/group___r_t_c___alarm_mask___definitions.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: RTC_AlarmMask_Definitions + + + + + + + + + + +
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RTC_AlarmMask_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_AlarmMask_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define RTC_AlarmMask_None   ((uint32_t)0x00000000)
 
+#define RTC_AlarmMask_DateWeekDay   ((uint32_t)0x80000000)
 
+#define RTC_AlarmMask_Hours   ((uint32_t)0x00800000)
 
+#define RTC_AlarmMask_Minutes   ((uint32_t)0x00008000)
 
+#define RTC_AlarmMask_Seconds   ((uint32_t)0x00000080)
 
+#define RTC_AlarmMask_All   ((uint32_t)0x80808080)
 
+#define IS_ALARM_MASK(MASK)   (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarm_mask___definitions.map b/group___r_t_c___alarm_mask___definitions.map new file mode 100644 index 0000000..bb0132d --- /dev/null +++ b/group___r_t_c___alarm_mask___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarm_mask___definitions.md5 b/group___r_t_c___alarm_mask___definitions.md5 new file mode 100644 index 0000000..a332cf8 --- /dev/null +++ b/group___r_t_c___alarm_mask___definitions.md5 @@ -0,0 +1 @@ +25a07d428b463345374a5bf1ff5e34de \ No newline at end of file diff --git a/group___r_t_c___alarm_mask___definitions.png b/group___r_t_c___alarm_mask___definitions.png new file mode 100644 index 0000000..37a0ec1 Binary files /dev/null and b/group___r_t_c___alarm_mask___definitions.png differ diff --git a/group___r_t_c___alarms___definitions.html b/group___r_t_c___alarms___definitions.html new file mode 100644 index 0000000..5d8e1ff --- /dev/null +++ b/group___r_t_c___alarms___definitions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: RTC_Alarms_Definitions + + + + + + + + + + +
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RTC_Alarms_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Alarms_Definitions:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RTC_Alarm_A   ((uint32_t)0x00000100)
 
+#define RTC_Alarm_B   ((uint32_t)0x00000200)
 
+#define IS_RTC_ALARM(ALARM)   (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
 
+#define IS_RTC_CMD_ALARM(ALARM)   (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___alarms___definitions.map b/group___r_t_c___alarms___definitions.map new file mode 100644 index 0000000..4624a59 --- /dev/null +++ b/group___r_t_c___alarms___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___alarms___definitions.md5 b/group___r_t_c___alarms___definitions.md5 new file mode 100644 index 0000000..e574221 --- /dev/null +++ b/group___r_t_c___alarms___definitions.md5 @@ -0,0 +1 @@ +96efea6c2d308a9c766613c42a0f781c \ No newline at end of file diff --git a/group___r_t_c___alarms___definitions.png b/group___r_t_c___alarms___definitions.png new file mode 100644 index 0000000..8ca73df Binary files /dev/null and b/group___r_t_c___alarms___definitions.png differ diff --git a/group___r_t_c___asynchronous___predivider.html b/group___r_t_c___asynchronous___predivider.html new file mode 100644 index 0000000..81d26e8 --- /dev/null +++ b/group___r_t_c___asynchronous___predivider.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Asynchronous_Predivider + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Asynchronous_Predivider
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Asynchronous_Predivider:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___asynchronous___predivider.map b/group___r_t_c___asynchronous___predivider.map new file mode 100644 index 0000000..8181d55 --- /dev/null +++ b/group___r_t_c___asynchronous___predivider.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___asynchronous___predivider.md5 b/group___r_t_c___asynchronous___predivider.md5 new file mode 100644 index 0000000..090bd08 --- /dev/null +++ b/group___r_t_c___asynchronous___predivider.md5 @@ -0,0 +1 @@ +f2e8b50f3b99d7ac9b3483364a69155c \ No newline at end of file diff --git a/group___r_t_c___asynchronous___predivider.png b/group___r_t_c___asynchronous___predivider.png new file mode 100644 index 0000000..3af8988 Binary files /dev/null and b/group___r_t_c___asynchronous___predivider.png differ diff --git a/group___r_t_c___backup___registers___definitions.html b/group___r_t_c___backup___registers___definitions.html new file mode 100644 index 0000000..a3e83fa --- /dev/null +++ b/group___r_t_c___backup___registers___definitions.html @@ -0,0 +1,205 @@ + + + + + + +discoverpixy: RTC_Backup_Registers_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Backup_Registers_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Backup_Registers_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_BKP_DR0   ((uint32_t)0x00000000)
 
+#define RTC_BKP_DR1   ((uint32_t)0x00000001)
 
+#define RTC_BKP_DR2   ((uint32_t)0x00000002)
 
+#define RTC_BKP_DR3   ((uint32_t)0x00000003)
 
+#define RTC_BKP_DR4   ((uint32_t)0x00000004)
 
+#define RTC_BKP_DR5   ((uint32_t)0x00000005)
 
+#define RTC_BKP_DR6   ((uint32_t)0x00000006)
 
+#define RTC_BKP_DR7   ((uint32_t)0x00000007)
 
+#define RTC_BKP_DR8   ((uint32_t)0x00000008)
 
+#define RTC_BKP_DR9   ((uint32_t)0x00000009)
 
+#define RTC_BKP_DR10   ((uint32_t)0x0000000A)
 
+#define RTC_BKP_DR11   ((uint32_t)0x0000000B)
 
+#define RTC_BKP_DR12   ((uint32_t)0x0000000C)
 
+#define RTC_BKP_DR13   ((uint32_t)0x0000000D)
 
+#define RTC_BKP_DR14   ((uint32_t)0x0000000E)
 
+#define RTC_BKP_DR15   ((uint32_t)0x0000000F)
 
+#define RTC_BKP_DR16   ((uint32_t)0x00000010)
 
+#define RTC_BKP_DR17   ((uint32_t)0x00000011)
 
+#define RTC_BKP_DR18   ((uint32_t)0x00000012)
 
+#define RTC_BKP_DR19   ((uint32_t)0x00000013)
 
#define IS_RTC_BKP(BKP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_BKP( BKP)
+
+Value:
(((BKP) == RTC_BKP_DR0) || \
+
((BKP) == RTC_BKP_DR1) || \
+
((BKP) == RTC_BKP_DR2) || \
+
((BKP) == RTC_BKP_DR3) || \
+
((BKP) == RTC_BKP_DR4) || \
+
((BKP) == RTC_BKP_DR5) || \
+
((BKP) == RTC_BKP_DR6) || \
+
((BKP) == RTC_BKP_DR7) || \
+
((BKP) == RTC_BKP_DR8) || \
+
((BKP) == RTC_BKP_DR9) || \
+
((BKP) == RTC_BKP_DR10) || \
+
((BKP) == RTC_BKP_DR11) || \
+
((BKP) == RTC_BKP_DR12) || \
+
((BKP) == RTC_BKP_DR13) || \
+
((BKP) == RTC_BKP_DR14) || \
+
((BKP) == RTC_BKP_DR15) || \
+
((BKP) == RTC_BKP_DR16) || \
+
((BKP) == RTC_BKP_DR17) || \
+
((BKP) == RTC_BKP_DR18) || \
+
((BKP) == RTC_BKP_DR19))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___backup___registers___definitions.map b/group___r_t_c___backup___registers___definitions.map new file mode 100644 index 0000000..1179aeb --- /dev/null +++ b/group___r_t_c___backup___registers___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___backup___registers___definitions.md5 b/group___r_t_c___backup___registers___definitions.md5 new file mode 100644 index 0000000..4728447 --- /dev/null +++ b/group___r_t_c___backup___registers___definitions.md5 @@ -0,0 +1 @@ +6d1bdf2491538af638da101e7d79c0e8 \ No newline at end of file diff --git a/group___r_t_c___backup___registers___definitions.png b/group___r_t_c___backup___registers___definitions.png new file mode 100644 index 0000000..76113ab Binary files /dev/null and b/group___r_t_c___backup___registers___definitions.png differ diff --git a/group___r_t_c___calib___output__selection___definitions.html b/group___r_t_c___calib___output__selection___definitions.html new file mode 100644 index 0000000..cfa244f --- /dev/null +++ b/group___r_t_c___calib___output__selection___definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Calib_Output_selection_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Calib_Output_selection_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Calib_Output_selection_Definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_CalibOutput_512Hz   ((uint32_t)0x00000000)
 
+#define RTC_CalibOutput_1Hz   ((uint32_t)0x00080000)
 
#define IS_RTC_CALIB_OUTPUT(OUTPUT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_CALIB_OUTPUT( OUTPUT)
+
+Value:
(((OUTPUT) == RTC_CalibOutput_512Hz) || \
+
((OUTPUT) == RTC_CalibOutput_1Hz))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___calib___output__selection___definitions.map b/group___r_t_c___calib___output__selection___definitions.map new file mode 100644 index 0000000..3557def --- /dev/null +++ b/group___r_t_c___calib___output__selection___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___calib___output__selection___definitions.md5 b/group___r_t_c___calib___output__selection___definitions.md5 new file mode 100644 index 0000000..e29acfe --- /dev/null +++ b/group___r_t_c___calib___output__selection___definitions.md5 @@ -0,0 +1 @@ +78321940068be3552ac2a73ac5d24dfe \ No newline at end of file diff --git a/group___r_t_c___calib___output__selection___definitions.png b/group___r_t_c___calib___output__selection___definitions.png new file mode 100644 index 0000000..8735d94 Binary files /dev/null and b/group___r_t_c___calib___output__selection___definitions.png differ diff --git a/group___r_t_c___day_light_saving___definitions.html b/group___r_t_c___day_light_saving___definitions.html new file mode 100644 index 0000000..ee6c445 --- /dev/null +++ b/group___r_t_c___day_light_saving___definitions.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: RTC_DayLightSaving_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_DayLightSaving_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_DayLightSaving_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
 
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
 
#define IS_RTC_DAYLIGHT_SAVING(SAVE)
 
+#define RTC_StoreOperation_Reset   ((uint32_t)0x00000000)
 
+#define RTC_StoreOperation_Set   ((uint32_t)0x00040000)
 
#define IS_RTC_STORE_OPERATION(OPERATION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_DAYLIGHT_SAVING( SAVE)
+
+Value:
(((SAVE) == RTC_DayLightSaving_SUB1H) || \
+
((SAVE) == RTC_DayLightSaving_ADD1H))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_RTC_STORE_OPERATION( OPERATION)
+
+Value:
(((OPERATION) == RTC_StoreOperation_Reset) || \
+
((OPERATION) == RTC_StoreOperation_Set))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___day_light_saving___definitions.map b/group___r_t_c___day_light_saving___definitions.map new file mode 100644 index 0000000..3eaf936 --- /dev/null +++ b/group___r_t_c___day_light_saving___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___day_light_saving___definitions.md5 b/group___r_t_c___day_light_saving___definitions.md5 new file mode 100644 index 0000000..ab20f8c --- /dev/null +++ b/group___r_t_c___day_light_saving___definitions.md5 @@ -0,0 +1 @@ +c167be9ccbe7971479180e00299bd4a9 \ No newline at end of file diff --git a/group___r_t_c___day_light_saving___definitions.png b/group___r_t_c___day_light_saving___definitions.png new file mode 100644 index 0000000..199f6e8 Binary files /dev/null and b/group___r_t_c___day_light_saving___definitions.png differ diff --git a/group___r_t_c___digital___calibration___definitions.html b/group___r_t_c___digital___calibration___definitions.html new file mode 100644 index 0000000..a261fe7 --- /dev/null +++ b/group___r_t_c___digital___calibration___definitions.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: RTC_Digital_Calibration_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Digital_Calibration_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Digital_Calibration_Definitions:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define RTC_CalibSign_Positive   ((uint32_t)0x00000000)
 
+#define RTC_CalibSign_Negative   ((uint32_t)0x00000080)
 
#define IS_RTC_CALIB_SIGN(SIGN)
 
+#define IS_RTC_CALIB_VALUE(VALUE)   ((VALUE) < 0x20)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_CALIB_SIGN( SIGN)
+
+Value:
(((SIGN) == RTC_CalibSign_Positive) || \
+
((SIGN) == RTC_CalibSign_Negative))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___digital___calibration___definitions.map b/group___r_t_c___digital___calibration___definitions.map new file mode 100644 index 0000000..4845242 --- /dev/null +++ b/group___r_t_c___digital___calibration___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___digital___calibration___definitions.md5 b/group___r_t_c___digital___calibration___definitions.md5 new file mode 100644 index 0000000..741b2b2 --- /dev/null +++ b/group___r_t_c___digital___calibration___definitions.md5 @@ -0,0 +1 @@ +3924517d1866d73161c0895efb4cf597 \ No newline at end of file diff --git a/group___r_t_c___digital___calibration___definitions.png b/group___r_t_c___digital___calibration___definitions.png new file mode 100644 index 0000000..c9847e8 Binary files /dev/null and b/group___r_t_c___digital___calibration___definitions.png differ diff --git a/group___r_t_c___exported___constants.html b/group___r_t_c___exported___constants.html new file mode 100644 index 0000000..a66f391 --- /dev/null +++ b/group___r_t_c___exported___constants.html @@ -0,0 +1,184 @@ + + + + + + +discoverpixy: RTC_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
RTC_Exported_Constants
STM32F4xx_StdPeriph_Driver » RTC
+
+
+
+Collaboration diagram for RTC_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 RTC_Hour_Formats
 
 RTC_Asynchronous_Predivider
 
 RTC_Synchronous_Predivider
 
 RTC_Time_Definitions
 
 RTC_AM_PM_Definitions
 
 RTC_Year_Date_Definitions
 
 RTC_Month_Date_Definitions
 
 RTC_WeekDay_Definitions
 
 RTC_Alarm_Definitions
 
 RTC_AlarmDateWeekDay_Definitions
 
 RTC_AlarmMask_Definitions
 
 RTC_Alarms_Definitions
 
 RTC_Alarm_Sub_Seconds_Masks_Definitions
 
 RTC_Alarm_Sub_Seconds_Value
 
 RTC_Wakeup_Timer_Definitions
 
 RTC_Time_Stamp_Edges_definitions
 
 RTC_Output_selection_Definitions
 
 RTC_Output_Polarity_Definitions
 
 RTC_Digital_Calibration_Definitions
 
 RTC_Calib_Output_selection_Definitions
 
 RTC_Smooth_calib_period_Definitions
 
 RTC_Smooth_calib_Plus_pulses_Definitions
 
 RTC_Smooth_calib_Minus_pulses_Definitions
 
 RTC_DayLightSaving_Definitions
 
 RTC_Tamper_Trigger_Definitions
 
 RTC_Tamper_Filter_Definitions
 
 RTC_Tamper_Sampling_Frequencies_Definitions
 
 RTC_Tamper_Pin_Precharge_Duration_Definitions
 
 RTC_Tamper_Pins_Definitions
 
 RTC_Tamper_Pin_Selection
 
 RTC_TimeStamp_Pin_Selection
 
 RTC_Output_Type_ALARM_OUT
 
 RTC_Add_1_Second_Parameter_Definitions
 
 RTC_Substract_Fraction_Of_Second_Value
 
 RTC_Backup_Registers_Definitions
 
 RTC_Input_parameter_format_definitions
 
 RTC_Flags_Definitions
 
 RTC_Interrupts_Definitions
 
 RTC_Legacy
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___exported___constants.map b/group___r_t_c___exported___constants.map new file mode 100644 index 0000000..8204994 --- /dev/null +++ b/group___r_t_c___exported___constants.map @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___r_t_c___exported___constants.md5 b/group___r_t_c___exported___constants.md5 new file mode 100644 index 0000000..b6a350d --- /dev/null +++ b/group___r_t_c___exported___constants.md5 @@ -0,0 +1 @@ +fd12aa0713e5404c3e2505d79aa2b8cc \ No newline at end of file diff --git a/group___r_t_c___exported___constants.png b/group___r_t_c___exported___constants.png new file mode 100644 index 0000000..cacd1cf Binary files /dev/null and b/group___r_t_c___exported___constants.png differ diff --git a/group___r_t_c___flags___definitions.html b/group___r_t_c___flags___definitions.html new file mode 100644 index 0000000..4bfcdbf --- /dev/null +++ b/group___r_t_c___flags___definitions.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: RTC_Flags_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Flags_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Flags_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_FLAG_RECALPF   ((uint32_t)0x00010000)
 
+#define RTC_FLAG_TAMP1F   ((uint32_t)0x00002000)
 
+#define RTC_FLAG_TSOVF   ((uint32_t)0x00001000)
 
+#define RTC_FLAG_TSF   ((uint32_t)0x00000800)
 
+#define RTC_FLAG_WUTF   ((uint32_t)0x00000400)
 
+#define RTC_FLAG_ALRBF   ((uint32_t)0x00000200)
 
+#define RTC_FLAG_ALRAF   ((uint32_t)0x00000100)
 
+#define RTC_FLAG_INITF   ((uint32_t)0x00000040)
 
+#define RTC_FLAG_RSF   ((uint32_t)0x00000020)
 
+#define RTC_FLAG_INITS   ((uint32_t)0x00000010)
 
+#define RTC_FLAG_SHPF   ((uint32_t)0x00000008)
 
+#define RTC_FLAG_WUTWF   ((uint32_t)0x00000004)
 
+#define RTC_FLAG_ALRBWF   ((uint32_t)0x00000002)
 
+#define RTC_FLAG_ALRAWF   ((uint32_t)0x00000001)
 
#define IS_RTC_GET_FLAG(FLAG)
 
+#define IS_RTC_CLEAR_FLAG(FLAG)   (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+
((FLAG) == RTC_FLAG_SHPF))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___flags___definitions.map b/group___r_t_c___flags___definitions.map new file mode 100644 index 0000000..04a6622 --- /dev/null +++ b/group___r_t_c___flags___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___flags___definitions.md5 b/group___r_t_c___flags___definitions.md5 new file mode 100644 index 0000000..92bb786 --- /dev/null +++ b/group___r_t_c___flags___definitions.md5 @@ -0,0 +1 @@ +fe55b96f4c9eee737562308049ca44d0 \ No newline at end of file diff --git a/group___r_t_c___flags___definitions.png b/group___r_t_c___flags___definitions.png new file mode 100644 index 0000000..236dbfb Binary files /dev/null and b/group___r_t_c___flags___definitions.png differ diff --git a/group___r_t_c___group1.html b/group___r_t_c___group1.html new file mode 100644 index 0000000..888feb3 --- /dev/null +++ b/group___r_t_c___group1.html @@ -0,0 +1,526 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_DeInit (void)
 Deinitializes the RTC registers to their default reset values. More...
 
ErrorStatus RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
 Initializes the RTC registers according to the specified parameters in RTC_InitStruct. More...
 
void RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
 Fills each RTC_InitStruct member with its default value. More...
 
void RTC_WriteProtectionCmd (FunctionalState NewState)
 Enables or disables the RTC registers write protection. More...
 
ErrorStatus RTC_EnterInitMode (void)
 Enters the RTC Initialization mode. More...
 
void RTC_ExitInitMode (void)
 Exits the RTC Initialization mode. More...
 
ErrorStatus RTC_WaitForSynchro (void)
 Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock. More...
 
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
 Enables or disables the RTC reference clock detection. More...
 
void RTC_BypassShadowCmd (FunctionalState NewState)
 Enables or Disables the Bypass Shadow feature. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+             ##### Initialization and Configuration functions #####
+ ===============================================================================
+ 
+ [..] This section provide functions allowing to initialize and configure the RTC
+      Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+      Write protection, enter and exit the RTC initialization mode, RTC registers
+      synchronization check and reference clock detection enable.
+  
+   (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
+       split into 2 programmable prescalers to minimize power consumption.
+       (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+       (++) When both prescalers are used, it is recommended to configure the 
+            asynchronous prescaler to a high value to minimize consumption.
+
+   (#) All RTC registers are Write protected. Writing to the RTC registers
+       is enabled by writing a key into the Write Protection register, RTC_WPR.
+
+   (#) To Configure the RTC Calendar, user application should enter initialization
+       mode. In this mode, the calendar counter is stopped and its value can be 
+       updated. When the initialization sequence is complete, the calendar restarts 
+       counting after 4 RTCCLK cycles.
+
+   (#) To read the calendar through the shadow registers after Calendar initialization,
+       calendar update or after wakeup from low power modes the software must first 
+       clear the RSF flag. The software must then wait until it is set again before 
+       reading the calendar, which means that the calendar registers have been 
+       correctly copied into the RTC_TR and RTC_DR shadow registers.
+       The RTC_WaitForSynchro() function implements the above software sequence 
+       (RSF clear and RSF check).

Function Documentation

+ +
+
+ + + + + + + + +
void RTC_BypassShadowCmd (FunctionalState NewState)
+
+ +

Enables or Disables the Bypass Shadow feature.

+
Note
When the Bypass Shadow is enabled the calendar value are taken directly from the Calendar counter.
+
Parameters
+ + +
NewStatenew state of the Bypass Shadow feature. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_DeInit (void )
+
+ +

Deinitializes the RTC registers to their default reset values.

+
Note
This function doesn't reset the RTC Clock source and RTC Backup Data registers.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are deinitialized
    • +
  • ERROR: RTC registers are not deinitialized
    • +
+
+
+
+ +

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+ +
+
+ + + + + + + + +
ErrorStatus RTC_EnterInitMode (void )
+
+ +

Enters the RTC Initialization mode.

+
Note
The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC is in Init mode
    • +
  • ERROR: RTC is not in Init mode
    • +
+
+
+
+ +

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+ +
+
+ +
+
+ + + + + + + + +
void RTC_ExitInitMode (void )
+
+ +

Exits the RTC Initialization mode.

+
Note
When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles.
+
+The RTC Initialization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + +
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+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_Init (RTC_InitTypeDef * RTC_InitStruct)
+
+ +

Initializes the RTC registers according to the specified parameters in RTC_InitStruct.

+
Parameters
+ + +
RTC_InitStructpointer to a RTC_InitTypeDef structure that contains the configuration information for the RTC peripheral.
+
+
+
Note
The RTC Prescaler register is write protected and can be written in initialization mode only.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are initialized
    • +
  • ERROR: RTC registers are not initialized
    • +
+
+
+
+ +

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+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC reference clock detection.

+
Parameters
+ + +
NewStatenew state of the RTC reference clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC reference clock detection is enabled
    • +
  • ERROR: RTC reference clock detection is disabled
    • +
+
+
+
+ +

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+ +
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+ +
+
+ + + + + + + + +
void RTC_StructInit (RTC_InitTypeDef * RTC_InitStruct)
+
+ +

Fills each RTC_InitStruct member with its default value.

+
Parameters
+ + +
RTC_InitStructpointer to a RTC_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_WaitForSynchro (void )
+
+ +

Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock.

+
Note
The RTC Resynchronization mode is write protected, use the RTC_WriteProtectionCmd(DISABLE) before calling this function.
+
+To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC registers are synchronised
    • +
  • ERROR: RTC registers are not synchronised
    • +
+
+
+
+ +

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+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void RTC_WriteProtectionCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC registers write protection.

+
Note
All the RTC registers are write protected except for RTC_ISR[13:8], RTC_TAFCR and RTC_BKPxR.
+
+Writing a wrong key reactivates the write protection.
+
+The protection mechanism is not affected by system reset.
+
Parameters
+ + +
NewStatenew state of the write protection. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group1.map b/group___r_t_c___group1.map new file mode 100644 index 0000000..db07372 --- /dev/null +++ b/group___r_t_c___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group1.md5 b/group___r_t_c___group1.md5 new file mode 100644 index 0000000..1b7217e --- /dev/null +++ b/group___r_t_c___group1.md5 @@ -0,0 +1 @@ +9563187e68b255ae411cc49988e32901 \ No newline at end of file diff --git a/group___r_t_c___group1.png b/group___r_t_c___group1.png new file mode 100644 index 0000000..5bdaefb Binary files /dev/null and b/group___r_t_c___group1.png differ diff --git a/group___r_t_c___group10.html b/group___r_t_c___group10.html new file mode 100644 index 0000000..d99b505 --- /dev/null +++ b/group___r_t_c___group10.html @@ -0,0 +1,190 @@ + + + + + + +discoverpixy: Backup Data Registers configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
+
+ + +
+ +
+ +
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+Functions
+
+
Backup Data Registers configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Backup Data Registers configuration functions. +More...

+
+Collaboration diagram for Backup Data Registers configuration functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
 Writes a data in a specified RTC Backup data register. More...
 
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
 Reads data from the specified RTC Backup data Register. More...
 
+

Detailed Description

+

Backup Data Registers configuration functions.

+
 ===============================================================================
+             ##### Backup Data Registers configuration functions ##### 
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
+
+ +

Reads data from the specified RTC Backup data Register.

+
Parameters
+ + +
RTC_BKP_DRRTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR,
uint32_t Data 
)
+
+ +

Writes a data in a specified RTC Backup data register.

+
Parameters
+ + + +
RTC_BKP_DRRTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to specify the register.
DataData to be written in the specified RTC Backup data register.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group10.map b/group___r_t_c___group10.map new file mode 100644 index 0000000..2f6087d --- /dev/null +++ b/group___r_t_c___group10.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group10.md5 b/group___r_t_c___group10.md5 new file mode 100644 index 0000000..f34784d --- /dev/null +++ b/group___r_t_c___group10.md5 @@ -0,0 +1 @@ +459e2686740b1bdc854141aceadffe9a \ No newline at end of file diff --git a/group___r_t_c___group10.png b/group___r_t_c___group10.png new file mode 100644 index 0000000..90befed Binary files /dev/null and b/group___r_t_c___group10.png differ diff --git a/group___r_t_c___group11.html b/group___r_t_c___group11.html new file mode 100644 index 0000000..05ca98b --- /dev/null +++ b/group___r_t_c___group11.html @@ -0,0 +1,224 @@ + + + + + + +discoverpixy: RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ +
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+ +
+
+Functions
+
+
RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions. +More...

+
+Collaboration diagram for RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
 Selects the RTC Tamper Pin. More...
 
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
 Selects the RTC TimeStamp Pin. More...
 
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
 Configures the RTC Output Pin mode. More...
 
+

Detailed Description

+

RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions.

+
 ==================================================================================================
+ ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### 
+ ==================================================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
+
+ +

Configures the RTC Output Pin mode.

+
Parameters
+ + +
RTC_OutputTypespecifies the RTC Output (PC13) pin mode. This parameter can be one of the following values:
    +
  • RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in Open Drain mode.
    • +
  • RTC_OutputType_PushPull: RTC Output (PC13) is configured in Push Pull mode.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
+
+ +

Selects the RTC Tamper Pin.

+
Parameters
+ + +
RTC_TamperPinspecifies the RTC Tamper Pin. This parameter can be one of the following values:
    +
  • RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
    • +
  • RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
+
+ +

Selects the RTC TimeStamp Pin.

+
Parameters
+ + +
RTC_TimeStampPinspecifies the RTC TimeStamp Pin. This parameter can be one of the following values:
    +
  • RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
    • +
  • RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group11.map b/group___r_t_c___group11.map new file mode 100644 index 0000000..5d8fb8b --- /dev/null +++ b/group___r_t_c___group11.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group11.md5 b/group___r_t_c___group11.md5 new file mode 100644 index 0000000..3532886 --- /dev/null +++ b/group___r_t_c___group11.md5 @@ -0,0 +1 @@ +519f37e016cede14f4c6f5483263b515 \ No newline at end of file diff --git a/group___r_t_c___group11.png b/group___r_t_c___group11.png new file mode 100644 index 0000000..555c621 Binary files /dev/null and b/group___r_t_c___group11.png differ diff --git a/group___r_t_c___group12.html b/group___r_t_c___group12.html new file mode 100644 index 0000000..658f111 --- /dev/null +++ b/group___r_t_c___group12.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: Shift control synchronisation functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Shift control synchronisation functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Shift control synchronisation functions. +More...

+
+Collaboration diagram for Shift control synchronisation functions:
+
+
+ + +
+
+ + + + + +

+Functions

ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
 Configures the Synchronization Shift Control Settings. More...
 
+

Detailed Description

+

Shift control synchronisation functions.

+
 ===============================================================================
+              ##### Shift control synchronisation functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S,
uint32_t RTC_ShiftSubFS 
)
+
+ +

Configures the Synchronization Shift Control Settings.

+
Note
When REFCKON is set, firmware must not write to Shift control register
+
Parameters
+ + + +
RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. This parameter can be one of the following values :
    +
  • RTC_ShiftAdd1S_Set : Add one second to the clock calendar.
    • +
  • RTC_ShiftAdd1S_Reset: No effect.
    • +
+
RTC_ShiftSubFSSelect the number of Second Fractions to Substitute. This parameter can be one any value from 0 to 0x7FFF.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Shift registers are configured
    • +
  • ERROR: RTC Shift registers are not configured
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group12.map b/group___r_t_c___group12.map new file mode 100644 index 0000000..ffdbc40 --- /dev/null +++ b/group___r_t_c___group12.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group12.md5 b/group___r_t_c___group12.md5 new file mode 100644 index 0000000..0013969 --- /dev/null +++ b/group___r_t_c___group12.md5 @@ -0,0 +1 @@ +99b0853a61e940dcf1726673a43f0e86 \ No newline at end of file diff --git a/group___r_t_c___group12.png b/group___r_t_c___group12.png new file mode 100644 index 0000000..7a09976 Binary files /dev/null and b/group___r_t_c___group12.png differ diff --git a/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.map b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.map new file mode 100644 index 0000000..4a654a4 --- /dev/null +++ b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.md5 b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.md5 new file mode 100644 index 0000000..3c6173a --- /dev/null +++ b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.md5 @@ -0,0 +1 @@ +5df286e73bdf47bdef80cc67ad23f7f2 \ No newline at end of file diff --git a/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.png b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.png new file mode 100644 index 0000000..69d9c01 Binary files /dev/null and b/group___r_t_c___group12_gaad434ed2a268f05662f0613e8e9717f3_cgraph.png differ diff --git a/group___r_t_c___group13.html b/group___r_t_c___group13.html new file mode 100644 index 0000000..669e56f --- /dev/null +++ b/group___r_t_c___group13.html @@ -0,0 +1,369 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
 Enables or disables the specified RTC interrupts. More...
 
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
 Checks whether the specified RTC flag is set or not. More...
 
void RTC_ClearFlag (uint32_t RTC_FLAG)
 Clears the RTC's pending flags. More...
 
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
 Checks whether the specified RTC interrupt has occurred or not. More...
 
void RTC_ClearITPendingBit (uint32_t RTC_IT)
 Clears the RTC's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================  
+ [..] All RTC interrupts are connected to the EXTI controller.
+ 
+   (+) To enable the RTC Alarm interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 17 in interrupt mode and select 
+            the rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
+            the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+
+   (+) To enable the RTC Wakeup interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 22 in interrupt mode and select the
+            rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the RTC to generate the RTC wakeup timer event using the 
+            RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() 
+            functions.
+
+   (+) To enable the RTC Tamper interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 21 in interrupt mode and select 
+            the rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
+            NVIC_Init() function.
+       (++) Configure the RTC to detect the RTC tamper event using the 
+            RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+   (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
+       (++) Configure and enable the EXTI Line 21 in interrupt mode and select the
+            rising edge sensitivity using the EXTI_Init() function.
+       (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the 
+            NVIC_Init() function.
+       (++) Configure the RTC to detect the RTC time stamp event using the 
+            RTC_TimeStampCmd() functions.

Function Documentation

+ +
+
+ + + + + + + + +
void RTC_ClearFlag (uint32_t RTC_FLAG)
+
+ +

Clears the RTC's pending flags.

+
Parameters
+ + +
RTC_FLAGspecifies the RTC flag to clear. This parameter can be any combination of the following values:
    +
  • RTC_FLAG_TAMP1F: Tamper 1 event flag
    • +
  • RTC_FLAG_TSOVF: Time Stamp Overflow flag
    • +
  • RTC_FLAG_TSF: Time Stamp event flag
    • +
  • RTC_FLAG_WUTF: WakeUp Timer flag
    • +
  • RTC_FLAG_ALRBF: Alarm B flag
    • +
  • RTC_FLAG_ALRAF: Alarm A flag
    • +
  • RTC_FLAG_RSF: Registers Synchronized flag
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_ClearITPendingBit (uint32_t RTC_IT)
+
+ +

Clears the RTC's interrupt pending bits.

+
Parameters
+ + +
RTC_ITspecifies the RTC interrupt pending bit to clear. This parameter can be any combination of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt
    • +
  • RTC_IT_ALRB: Alarm B interrupt
    • +
  • RTC_IT_ALRA: Alarm A interrupt
    • +
  • RTC_IT_TAMP1: Tamper 1 event interrupt
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
+
+ +

Checks whether the specified RTC flag is set or not.

+
Parameters
+ + +
RTC_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • RTC_FLAG_RECALPF: RECALPF event flag.
    • +
  • RTC_FLAG_TAMP1F: Tamper 1 event flag
    • +
  • RTC_FLAG_TSOVF: Time Stamp OverFlow flag
    • +
  • RTC_FLAG_TSF: Time Stamp event flag
    • +
  • RTC_FLAG_WUTF: WakeUp Timer flag
    • +
  • RTC_FLAG_ALRBF: Alarm B flag
    • +
  • RTC_FLAG_ALRAF: Alarm A flag
    • +
  • RTC_FLAG_INITF: Initialization mode flag
    • +
  • RTC_FLAG_RSF: Registers Synchronized flag
    • +
  • RTC_FLAG_INITS: Registers Configured flag
    • +
  • RTC_FLAG_SHPF: Shift operation pending flag.
    • +
  • RTC_FLAG_WUTWF: WakeUp Timer Write flag
    • +
  • RTC_FLAG_ALRBWF: Alarm B Write flag
    • +
  • RTC_FLAG_ALRAWF: Alarm A write flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of RTC_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
+
+ +

Checks whether the specified RTC interrupt has occurred or not.

+
Parameters
+ + +
RTC_ITspecifies the RTC interrupt source to check. This parameter can be one of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt
    • +
  • RTC_IT_ALRB: Alarm B interrupt
    • +
  • RTC_IT_ALRA: Alarm A interrupt
    • +
  • RTC_IT_TAMP1: Tamper 1 event interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of RTC_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_ITConfig (uint32_t RTC_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RTC interrupts.

+
Parameters
+ + + +
RTC_ITspecifies the RTC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • RTC_IT_TS: Time Stamp interrupt mask
    • +
  • RTC_IT_WUT: WakeUp Timer interrupt mask
    • +
  • RTC_IT_ALRB: Alarm B interrupt mask
    • +
  • RTC_IT_ALRA: Alarm A interrupt mask
    • +
  • RTC_IT_TAMP: Tamper event interrupt mask
    • +
+
NewStatenew state of the specified RTC interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group13.map b/group___r_t_c___group13.map new file mode 100644 index 0000000..2bb661b --- /dev/null +++ b/group___r_t_c___group13.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group13.md5 b/group___r_t_c___group13.md5 new file mode 100644 index 0000000..2cf754c --- /dev/null +++ b/group___r_t_c___group13.md5 @@ -0,0 +1 @@ +17b8cff8382a47aa879e4b49897016fb \ No newline at end of file diff --git a/group___r_t_c___group13.png b/group___r_t_c___group13.png new file mode 100644 index 0000000..5c8b054 Binary files /dev/null and b/group___r_t_c___group13.png differ diff --git a/group___r_t_c___group1_ga2938febeef6baf0d91cc066ca5caf095_icgraph.map b/group___r_t_c___group1_ga2938febeef6baf0d91cc066ca5caf095_icgraph.map new file mode 100644 index 0000000..0da39d7 --- /dev/null +++ b/group___r_t_c___group1_ga2938febeef6baf0d91cc066ca5caf095_icgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git 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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Time and Date configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Time and Date configuration functions. +More...

+
+Collaboration diagram for Time and Date configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Set the RTC current time. More...
 
void RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
 Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec). More...
 
void RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Get the RTC current Time. More...
 
uint32_t RTC_GetSubSecond (void)
 Gets the RTC current Calendar Sub seconds value. More...
 
ErrorStatus RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Set the RTC current date. More...
 
void RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
 Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00). More...
 
void RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Get the RTC current date. More...
 
+

Detailed Description

+

Time and Date configuration functions.

+
 ===============================================================================
+                 ##### Time and Date configuration functions #####
+ ===============================================================================  
+ 
+ [..] This section provide functions allowing to program and read the RTC Calendar
+      (Time and Date).

Function Documentation

+ +
+
+ + + + + + + + +
void RTC_DateStructInit (RTC_DateTypeDef * RTC_DateStruct)
+
+ +

Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).

+
Parameters
+ + +
RTC_DateStructpointer to a RTC_DateTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_GetDate (uint32_t RTC_Format,
RTC_DateTypeDef * RTC_DateStruct 
)
+
+ +

Get the RTC current date.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_DateStructpointer to a RTC_DateTypeDef structure that will contain the returned current date configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetSubSecond (void )
+
+ +

Gets the RTC current Calendar Sub seconds value.

+
Note
This function freeze the Time and Date registers after reading the SSR register.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCcurrent Calendar Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_GetTime (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_TimeStruct 
)
+
+ +

Get the RTC current Time.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_TimeStructpointer to a RTC_TimeTypeDef structure that will contain the returned current time configuration.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SetDate (uint32_t RTC_Format,
RTC_DateTypeDef * RTC_DateStruct 
)
+
+ +

Set the RTC current date.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the entered parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_DateStructpointer to a RTC_DateTypeDef structure that contains the date configuration information for the RTC.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Date register is configured
    • +
  • ERROR: RTC Date register is not configured
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SetTime (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_TimeStruct 
)
+
+ +

Set the RTC current time.

+
Parameters
+ + + +
RTC_Formatspecifies the format of the entered parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_TimeStructpointer to a RTC_TimeTypeDef structure that contains the time configuration information for the RTC.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Time register is configured
    • +
  • ERROR: RTC Time register is not configured
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStructInit (RTC_TimeTypeDef * RTC_TimeStruct)
+
+ +

Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec).

+
Parameters
+ + +
RTC_TimeStructpointer to a RTC_TimeTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group2.map b/group___r_t_c___group2.map new file mode 100644 index 0000000..e9c4dda --- /dev/null +++ b/group___r_t_c___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group2.md5 b/group___r_t_c___group2.md5 new file mode 100644 index 0000000..433bf53 --- /dev/null +++ b/group___r_t_c___group2.md5 @@ -0,0 +1 @@ +d8bc0bb418ed8f8b27c8c1962aac4f68 \ No newline at end of file diff --git a/group___r_t_c___group2.png b/group___r_t_c___group2.png new file mode 100644 index 0000000..f29f6da Binary files /dev/null and b/group___r_t_c___group2.png differ diff --git a/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.map b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.map new file mode 100644 index 0000000..da8515b --- /dev/null +++ b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.md5 b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.md5 new file mode 100644 index 0000000..38704b6 --- /dev/null +++ b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.md5 @@ -0,0 +1 @@ +bb55b469f6699c9b00b7f4de4d0d463e \ No newline at end of file diff --git a/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.png b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.png new file mode 100644 index 0000000..4dfb542 Binary files /dev/null and b/group___r_t_c___group2_ga69d08538147f3d89c818dcfabf50e362_cgraph.png differ diff --git a/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.map b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.map new file mode 100644 index 0000000..b90b69a --- /dev/null +++ b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.md5 b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.md5 new file mode 100644 index 0000000..d46eef6 --- /dev/null +++ b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.md5 @@ -0,0 +1 @@ +1881ff44ec1293c2103653989f02bfab \ No newline at end of file diff --git a/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.png b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.png new file mode 100644 index 0000000..dc02a40 Binary files /dev/null and b/group___r_t_c___group2_ga9f9df80cfa82f7a4dd9f4d0cf2ffb3a6_cgraph.png differ diff --git a/group___r_t_c___group3.html b/group___r_t_c___group3.html new file mode 100644 index 0000000..dc5a51d --- /dev/null +++ b/group___r_t_c___group3.html @@ -0,0 +1,431 @@ + + + + + + +discoverpixy: Alarms configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Alarms configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Alarms (Alarm A and Alarm B) configuration functions. +More...

+
+Collaboration diagram for Alarms configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Set the specified RTC Alarm. More...
 
void RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
 Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked). More...
 
void RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Get the RTC Alarm value and masks. More...
 
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
 Enables or disables the specified RTC Alarm. More...
 
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
 Configure the RTC AlarmA/B Sub seconds value and mask.*. More...
 
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
 Gets the RTC Alarm Sub seconds value. More...
 
+

Detailed Description

+

Alarms (Alarm A and Alarm B) configuration functions.

+
 ===============================================================================
+         ##### Alarms A and B configuration functions #####
+ ===============================================================================  
+ 
+ [..] This section provide functions allowing to program and read the RTC Alarms.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified RTC Alarm.

+
Parameters
+ + + +
RTC_Alarmspecifies the alarm to be configured. This parameter can be any combination of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
NewStatenew state of the specified alarm. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Alarm is enabled/disabled
    • +
  • ERROR: RTC Alarm is not enabled/disabled
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_AlarmStructInit (RTC_AlarmTypeDef * RTC_AlarmStruct)
+
+ +

Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked).

+
Parameters
+ + +
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm,
uint32_t RTC_AlarmSubSecondValue,
uint32_t RTC_AlarmSubSecondMask 
)
+
+ +

Configure the RTC AlarmA/B Sub seconds value and mask.*.

+
Note
This function is performed only when the Alarm is disabled.
+
Parameters
+ + + + +
RTC_Alarmspecifies the alarm to be configured. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmSubSecondValuespecifies the Sub seconds value. This parameter can be a value from 0 to 0x00007FFF.
RTC_AlarmSubSecondMaskspecifies the Sub seconds Mask. This parameter can be any combination of the following values:
    +
  • RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm.
    • +
  • RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared
    • +
  • RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared
    • +
  • RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared
    • +
  • RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match to activate alarm
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_GetAlarm (uint32_t RTC_Format,
uint32_t RTC_Alarm,
RTC_AlarmTypeDef * RTC_AlarmStruct 
)
+
+ +

Get the RTC Alarm value and masks.

+
Parameters
+ + + + +
RTC_Formatspecifies the format of the output parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_Alarmspecifies the alarm to be read. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure that will contains the output alarm configuration values.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
+
+ +

Gets the RTC Alarm Sub seconds value.

+
Parameters
+ + + +
RTC_Alarmspecifies the alarm to be read. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
None
+
+
+
Return values
+ + +
RTCAlarm Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_SetAlarm (uint32_t RTC_Format,
uint32_t RTC_Alarm,
RTC_AlarmTypeDef * RTC_AlarmStruct 
)
+
+ +

Set the specified RTC Alarm.

+
Note
The Alarm register can only be written when the corresponding Alarm is disabled (Use the RTC_AlarmCmd(DISABLE)).
+
Parameters
+ + + + +
RTC_Formatspecifies the format of the returned parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_Alarmspecifies the alarm to be configured. This parameter can be one of the following values:
    +
  • RTC_Alarm_A: to select Alarm A
    • +
  • RTC_Alarm_B: to select Alarm B
    • +
+
RTC_AlarmStructpointer to a RTC_AlarmTypeDef structure that contains the alarm configuration parameters.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group3.map b/group___r_t_c___group3.map new file mode 100644 index 0000000..7c39c6e --- /dev/null +++ b/group___r_t_c___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group3.md5 b/group___r_t_c___group3.md5 new file mode 100644 index 0000000..6098219 --- /dev/null +++ b/group___r_t_c___group3.md5 @@ -0,0 +1 @@ +3d2b0d61cfa358680e02706547ff4a72 \ No newline at end of file diff --git a/group___r_t_c___group3.png b/group___r_t_c___group3.png new file mode 100644 index 0000000..ec27f37 Binary files /dev/null and b/group___r_t_c___group3.png differ diff --git a/group___r_t_c___group4.html b/group___r_t_c___group4.html new file mode 100644 index 0000000..6e7061e --- /dev/null +++ b/group___r_t_c___group4.html @@ -0,0 +1,257 @@ + + + + + + +discoverpixy: WakeUp Timer configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
WakeUp Timer configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

WakeUp Timer configuration functions. +More...

+
+Collaboration diagram for WakeUp Timer configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
 Configures the RTC Wakeup clock source. More...
 
void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
 Configures the RTC Wakeup counter. More...
 
uint32_t RTC_GetWakeUpCounter (void)
 Returns the RTC WakeUp timer counter value. More...
 
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
 Enables or Disables the RTC WakeUp timer. More...
 
+

Detailed Description

+

WakeUp Timer configuration functions.

+
 ===============================================================================
+                 ##### WakeUp Timer configuration functions #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to program and read the RTC WakeUp.

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t RTC_GetWakeUpCounter (void )
+
+ +

Returns the RTC WakeUp timer counter value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
TheRTC WakeUp Counter value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
+
+ +

Configures the RTC Wakeup counter.

+
Note
The RTC WakeUp counter can only be written when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+
Parameters
+ + +
RTC_WakeUpCounterspecifies the WakeUp counter. This parameter can be a value from 0x0000 to 0xFFFF.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
+
+ +

Configures the RTC Wakeup clock source.

+
Note
The WakeUp Clock source can only be changed when the RTC WakeUp is disabled (Use the RTC_WakeUpCmd(DISABLE)).
+
Parameters
+ + +
RTC_WakeUpClockWakeup Clock source. This parameter can be one of the following values:
    +
  • RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
    • +
  • RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
    • +
  • RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
    • +
  • RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
    • +
  • RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
    • +
  • RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
+
+ +

Enables or Disables the RTC WakeUp timer.

+
Parameters
+ + +
NewStatenew state of the WakeUp timer. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group4.map b/group___r_t_c___group4.map new file mode 100644 index 0000000..3d5c594 --- /dev/null +++ b/group___r_t_c___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group4.md5 b/group___r_t_c___group4.md5 new file mode 100644 index 0000000..f13778c --- /dev/null +++ b/group___r_t_c___group4.md5 @@ -0,0 +1 @@ +d28159b48b34db3e89d2990b5aeb77b1 \ No newline at end of file diff --git a/group___r_t_c___group4.png b/group___r_t_c___group4.png new file mode 100644 index 0000000..576dec3 Binary files /dev/null and b/group___r_t_c___group4.png differ diff --git a/group___r_t_c___group5.html b/group___r_t_c___group5.html new file mode 100644 index 0000000..53fd471 --- /dev/null +++ b/group___r_t_c___group5.html @@ -0,0 +1,204 @@ + + + + + + +discoverpixy: Daylight Saving configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Daylight Saving configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Daylight Saving configuration functions. +More...

+
+Collaboration diagram for Daylight Saving configuration functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
 Adds or substract one hour from the current time. More...
 
uint32_t RTC_GetStoreOperation (void)
 Returns the RTC Day Light Saving stored operation. More...
 
+

Detailed Description

+

Daylight Saving configuration functions.

+
 ===============================================================================
+              ##### Daylight Saving configuration functions #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to configure the RTC DayLight Saving.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving,
uint32_t RTC_StoreOperation 
)
+
+ +

Adds or substract one hour from the current time.

+
Parameters
+ + + +
RTC_DayLightSaveOperationthe value of hour adjustment. This parameter can be one of the following values:
    +
  • RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
    • +
  • RTC_DayLightSaving_ADD1H: Add one hour (summer time)
    • +
+
RTC_StoreOperationSpecifies the value to be written in the BCK bit in CR register to store the operation. This parameter can be one of the following values:
    +
  • RTC_StoreOperation_Reset: BCK Bit Reset
    • +
  • RTC_StoreOperation_Set: BCK Bit Set
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetStoreOperation (void )
+
+ +

Returns the RTC Day Light Saving stored operation.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCDay Light Saving stored operation.
    +
  • RTC_StoreOperation_Reset
    • +
  • RTC_StoreOperation_Set
    • +
+
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group5.map b/group___r_t_c___group5.map new file mode 100644 index 0000000..2fbe62e --- /dev/null +++ b/group___r_t_c___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group5.md5 b/group___r_t_c___group5.md5 new file mode 100644 index 0000000..189583f --- /dev/null +++ b/group___r_t_c___group5.md5 @@ -0,0 +1 @@ +c39ec900964dbd0128d538a01764db80 \ No newline at end of file diff --git a/group___r_t_c___group5.png b/group___r_t_c___group5.png new file mode 100644 index 0000000..b2819d4 Binary files /dev/null and b/group___r_t_c___group5.png differ diff --git a/group___r_t_c___group6.html b/group___r_t_c___group6.html new file mode 100644 index 0000000..5159da7 --- /dev/null +++ b/group___r_t_c___group6.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: Output pin Configuration function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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+ +
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+Functions
+
+
Output pin Configuration function
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Output pin Configuration function. +More...

+
+Collaboration diagram for Output pin Configuration function:
+
+
+ + +
+
+ + + + + +

+Functions

void RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
 Configures the RTC output source (AFO_ALARM). More...
 
+

Detailed Description

+

Output pin Configuration function.

+
 ===============================================================================
+                 ##### Output pin Configuration function #####
+ ===============================================================================  
+
+ [..] This section provide functions allowing to configure the RTC Output source.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_OutputConfig (uint32_t RTC_Output,
uint32_t RTC_OutputPolarity 
)
+
+ +

Configures the RTC output source (AFO_ALARM).

+
Parameters
+ + + +
RTC_OutputSpecifies which signal will be routed to the RTC output. This parameter can be one of the following values:
    +
  • RTC_Output_Disable: No output selected
    • +
  • RTC_Output_AlarmA: signal of AlarmA mapped to output
    • +
  • RTC_Output_AlarmB: signal of AlarmB mapped to output
    • +
  • RTC_Output_WakeUp: signal of WakeUp mapped to output
    • +
+
RTC_OutputPolaritySpecifies the polarity of the output signal. This parameter can be one of the following:
    +
  • RTC_OutputPolarity_High: The output pin is high when the ALRAF/ALRBF/WUTF is high (depending on OSEL)
    • +
  • RTC_OutputPolarity_Low: The output pin is low when the ALRAF/ALRBF/WUTF is high (depending on OSEL)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group6.map b/group___r_t_c___group6.map new file mode 100644 index 0000000..1a48808 --- /dev/null +++ b/group___r_t_c___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group6.md5 b/group___r_t_c___group6.md5 new file mode 100644 index 0000000..ffa0b20 --- /dev/null +++ b/group___r_t_c___group6.md5 @@ -0,0 +1 @@ +c557c4fe365dcd28f7d04e0cfdb55727 \ No newline at end of file diff --git a/group___r_t_c___group6.png b/group___r_t_c___group6.png new file mode 100644 index 0000000..83117db Binary files /dev/null and b/group___r_t_c___group6.png differ diff --git a/group___r_t_c___group7.html b/group___r_t_c___group7.html new file mode 100644 index 0000000..a1fbfe0 --- /dev/null +++ b/group___r_t_c___group7.html @@ -0,0 +1,357 @@ + + + + + + +discoverpixy: Digital Calibration configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Digital Calibration configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Coarse Calibration configuration functions. +More...

+
+Collaboration diagram for Digital Calibration configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
 Configures the Coarse calibration parameters. More...
 
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
 Enables or disables the Coarse calibration process. More...
 
void RTC_CalibOutputCmd (FunctionalState NewState)
 Enables or disables the RTC clock to be output through the relative pin. More...
 
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
 Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). More...
 
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
 Configures the Smooth Calibration Settings. More...
 
+

Detailed Description

+

Coarse Calibration configuration functions.

+
 ===============================================================================
+              ##### Digital Calibration configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void RTC_CalibOutputCmd (FunctionalState NewState)
+
+ +

Enables or disables the RTC clock to be output through the relative pin.

+
Parameters
+ + +
NewStatenew state of the digital calibration Output. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
+
+ +

Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).

+
Parameters
+ + +
RTC_CalibOutput: Select the Calibration output Selection . This parameter can be one of the following values:
    +
  • RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
    • +
  • RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
+
+ +

Enables or disables the Coarse calibration process.

+
Parameters
+ + +
NewStatenew state of the Coarse calibration. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Coarse calibration are enabled/disabled
    • +
  • ERROR: RTC Coarse calibration are not enabled/disabled
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign,
uint32_t Value 
)
+
+ +

Configures the Coarse calibration parameters.

+
Parameters
+ + + +
RTC_CalibSignspecifies the sign of the coarse calibration value. This parameter can be one of the following values:
    +
  • RTC_CalibSign_Positive: The value sign is positive
    • +
  • RTC_CalibSign_Negative: The value sign is negative
    • +
+
Valuevalue of coarse calibration expressed in ppm (coded on 5 bits).
+
+
+
Note
This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
+
+This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Coarse calibration are initialized
    • +
  • ERROR: RTC Coarse calibration are not initialized
    • +
+
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod,
uint32_t RTC_SmoothCalibPlusPulses,
uint32_t RTC_SmouthCalibMinusPulsesValue 
)
+
+ +

Configures the Smooth Calibration Settings.

+
Parameters
+ + + + +
RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. This parameter can be can be one of the following values:
    +
  • RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s.
    • +
  • RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s.
    • +
  • RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s.
    • +
+
RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. This parameter can be one of the following values:
    +
  • RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
    • +
  • RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
    • +
+
RTC_SmouthCalibMinusPulsesValueSelect the value of CALM[8:0] bits. This parameter can be one any value from 0 to 0x000001FF.
+
+
+
Return values
+ + +
AnErrorStatus enumeration value:
    +
  • SUCCESS: RTC Calib registers are configured
    • +
  • ERROR: RTC Calib registers are not configured
    • +
+
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group7.map b/group___r_t_c___group7.map new file mode 100644 index 0000000..e62db52 --- /dev/null +++ b/group___r_t_c___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group7.md5 b/group___r_t_c___group7.md5 new file mode 100644 index 0000000..5ff5e15 --- /dev/null +++ b/group___r_t_c___group7.md5 @@ -0,0 +1 @@ +aa95899100115a8e10782889f7f9a738 \ No newline at end of file diff --git a/group___r_t_c___group7.png b/group___r_t_c___group7.png new file mode 100644 index 0000000..45fb718 Binary files /dev/null and b/group___r_t_c___group7.png differ diff --git a/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.map b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.map new file mode 100644 index 0000000..2210dfa --- /dev/null +++ b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.md5 b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.md5 new file mode 100644 index 0000000..d7d4dc7 --- /dev/null +++ b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.md5 @@ -0,0 +1 @@ +d7848ed5a7b2cea80f8417e7cdda4b66 \ No newline at end of file diff --git a/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.png b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.png new file mode 100644 index 0000000..4faa195 Binary files /dev/null and b/group___r_t_c___group7_ga008ae7173b2befe876f5e76686bc9089_cgraph.png differ diff --git a/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.map b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.map new file mode 100644 index 0000000..838657d --- /dev/null +++ b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.md5 b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.md5 new file mode 100644 index 0000000..b6db69e --- /dev/null +++ b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.md5 @@ -0,0 +1 @@ +f2b50bc1a41e724a16c4a9793606d526 \ No newline at end of file diff --git a/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.png b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.png new file mode 100644 index 0000000..2711077 Binary files /dev/null and b/group___r_t_c___group7_gaa3bb10170a2c70ac9ce3e41c611bdd43_cgraph.png differ diff --git a/group___r_t_c___group8.html b/group___r_t_c___group8.html new file mode 100644 index 0000000..80bcd70 --- /dev/null +++ b/group___r_t_c___group8.html @@ -0,0 +1,249 @@ + + + + + + +discoverpixy: TimeStamp configuration functions + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Functions
+
+
TimeStamp configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

TimeStamp configuration functions. +More...

+
+Collaboration diagram for TimeStamp configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
 Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge. More...
 
void RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
 Get the RTC TimeStamp value and masks. More...
 
uint32_t RTC_GetTimeStampSubSecond (void)
 Get the RTC timestamp Sub seconds value. More...
 
+

Detailed Description

+

TimeStamp configuration functions.

+
 ===============================================================================
+                 ##### TimeStamp configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void RTC_GetTimeStamp (uint32_t RTC_Format,
RTC_TimeTypeDef * RTC_StampTimeStruct,
RTC_DateTypeDef * RTC_StampDateStruct 
)
+
+ +

Get the RTC TimeStamp value and masks.

+
Parameters
+ + + + +
RTC_Formatspecifies the format of the output parameters. This parameter can be one of the following values:
    +
  • RTC_Format_BIN: Binary data format
    • +
  • RTC_Format_BCD: BCD data format
    • +
+
RTC_StampTimeStructpointer to a RTC_TimeTypeDef structure that will contains the TimeStamp time values.
RTC_StampDateStructpointer to a RTC_DateTypeDef structure that will contains the TimeStamp date values.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t RTC_GetTimeStampSubSecond (void )
+
+ +

Get the RTC timestamp Sub seconds value.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
RTCcurrent timestamp Sub seconds value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge,
FunctionalState NewState 
)
+
+ +

Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge.

+
Parameters
+ + + +
RTC_TimeStampEdgeSpecifies the pin edge on which the TimeStamp is activated. This parameter can be one of the following:
    +
  • RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising edge of the related pin.
    • +
  • RTC_TimeStampEdge_Falling: the Time stamp event occurs on the falling edge of the related pin.
    • +
+
NewStatenew state of the TimeStamp. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group8.map b/group___r_t_c___group8.map new file mode 100644 index 0000000..6fa164d --- /dev/null +++ b/group___r_t_c___group8.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group8.md5 b/group___r_t_c___group8.md5 new file mode 100644 index 0000000..16b5f64 --- /dev/null +++ b/group___r_t_c___group8.md5 @@ -0,0 +1 @@ +b7f4bb41f2966bfca069add6e7ef80cd \ No newline at end of file diff --git a/group___r_t_c___group8.png b/group___r_t_c___group8.png new file mode 100644 index 0000000..8cc135a Binary files /dev/null and b/group___r_t_c___group8.png differ diff --git a/group___r_t_c___group9.html b/group___r_t_c___group9.html new file mode 100644 index 0000000..8690c6d --- /dev/null +++ b/group___r_t_c___group9.html @@ -0,0 +1,395 @@ + + + + + + +discoverpixy: Tampers configuration functions + + + + + + + + + + +
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+Functions
+
+
Tampers configuration functions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Private_Functions
+
+
+ +

Tampers configuration functions. +More...

+
+Collaboration diagram for Tampers configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
 Configures the select Tamper pin edge. More...
 
void RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
 Enables or Disables the Tamper detection. More...
 
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
 Configures the Tampers Filter. More...
 
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
 Configures the Tampers Sampling Frequency. More...
 
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
 Configures the Tampers Pins input Precharge Duration. More...
 
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
 Enables or Disables the TimeStamp on Tamper Detection Event. More...
 
void RTC_TamperPullUpCmd (FunctionalState NewState)
 Enables or Disables the Precharge of Tamper pin. More...
 
+

Detailed Description

+

Tampers configuration functions.

+
 ===============================================================================
+                 ##### Tampers configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_TamperCmd (uint32_t RTC_Tamper,
FunctionalState NewState 
)
+
+ +

Enables or Disables the Tamper detection.

+
Parameters
+ + + +
RTC_TamperSelected tamper pin. This parameter can be RTC_Tamper_1.
NewStatenew state of the tamper pin. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
+
+ +

Configures the Tampers Filter.

+
Parameters
+ + +
RTC_TamperFilterSpecifies the tampers filter. This parameter can be one of the following values:
    +
  • RTC_TamperFilter_Disable: Tamper filter is disabled.
    • +
  • RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive samples at the active level
    • +
  • RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive samples at the active level
    • +
  • RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive samples at the active level
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
+
+ +

Configures the Tampers Pins input Precharge Duration.

+
Parameters
+ + +
RTC_TamperPrechargeDurationSpecifies the Tampers Pins input Precharge Duration. This parameter can be one of the following values:
    +
  • RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle
    • +
  • RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperPullUpCmd (FunctionalState NewState)
+
+ +

Enables or Disables the Precharge of Tamper pin.

+
Parameters
+ + +
NewStatenew state of tamper pull up. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
+
+ +

Configures the Tampers Sampling Frequency.

+
Parameters
+ + +
RTC_TamperSamplingFreqSpecifies the tampers Sampling Frequency. This parameter can be one of the following values:
    +
  • RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled with a frequency = RTCCLK / 512
    • +
  • RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled with a frequency = RTCCLK / 256
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void RTC_TamperTriggerConfig (uint32_t RTC_Tamper,
uint32_t RTC_TamperTrigger 
)
+
+ +

Configures the select Tamper pin edge.

+
Parameters
+ + + +
RTC_TamperSelected tamper pin. This parameter can be RTC_Tamper_1.
RTC_TamperTriggerSpecifies the trigger on the tamper pin that stimulates tamper event. This parameter can be one of the following values:
    +
  • RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
    • +
  • RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
+
+ +

Enables or Disables the TimeStamp on Tamper Detection Event.

+
Note
The timestamp is valid even the TSE bit in tamper control register is reset.
+
Parameters
+ + +
NewStatenew state of the timestamp on tamper event. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___group9.map b/group___r_t_c___group9.map new file mode 100644 index 0000000..455b5a1 --- /dev/null +++ b/group___r_t_c___group9.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___group9.md5 b/group___r_t_c___group9.md5 new file mode 100644 index 0000000..03b3b2f --- /dev/null +++ b/group___r_t_c___group9.md5 @@ -0,0 +1 @@ +f84549ca2785577c7551fec30f3c916a \ No newline at end of file diff --git a/group___r_t_c___group9.png b/group___r_t_c___group9.png new file mode 100644 index 0000000..acb05d8 Binary files /dev/null and b/group___r_t_c___group9.png differ diff --git a/group___r_t_c___hour___formats.html b/group___r_t_c___hour___formats.html new file mode 100644 index 0000000..2c03f08 --- /dev/null +++ b/group___r_t_c___hour___formats.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Hour_Formats + + + + + + + + + + +
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discoverpixy +
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+Macros
+
+
RTC_Hour_Formats
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Hour_Formats:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_HourFormat_24   ((uint32_t)0x00000000)
 
+#define RTC_HourFormat_12   ((uint32_t)0x00000040)
 
#define IS_RTC_HOUR_FORMAT(FORMAT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_HOUR_FORMAT( FORMAT)
+
+Value:
(((FORMAT) == RTC_HourFormat_12) || \
+
((FORMAT) == RTC_HourFormat_24))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___hour___formats.map b/group___r_t_c___hour___formats.map new file mode 100644 index 0000000..cd29af5 --- /dev/null +++ b/group___r_t_c___hour___formats.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___hour___formats.md5 b/group___r_t_c___hour___formats.md5 new file mode 100644 index 0000000..f5a7a18 --- /dev/null +++ b/group___r_t_c___hour___formats.md5 @@ -0,0 +1 @@ +6443885625d4c3c5d226e9199c3b2f19 \ No newline at end of file diff --git a/group___r_t_c___hour___formats.png b/group___r_t_c___hour___formats.png new file mode 100644 index 0000000..13b327b Binary files /dev/null and b/group___r_t_c___hour___formats.png differ diff --git a/group___r_t_c___input__parameter__format__definitions.html b/group___r_t_c___input__parameter__format__definitions.html new file mode 100644 index 0000000..4dfd3a1 --- /dev/null +++ b/group___r_t_c___input__parameter__format__definitions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: RTC_Input_parameter_format_definitions + + + + + + + + + + +
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+ + + + + + +
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discoverpixy +
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+Macros
+
+
RTC_Input_parameter_format_definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Input_parameter_format_definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_Format_BIN   ((uint32_t)0x000000000)
 
+#define RTC_Format_BCD   ((uint32_t)0x000000001)
 
+#define IS_RTC_FORMAT(FORMAT)   (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___input__parameter__format__definitions.map b/group___r_t_c___input__parameter__format__definitions.map new file mode 100644 index 0000000..490ce96 --- /dev/null +++ b/group___r_t_c___input__parameter__format__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___input__parameter__format__definitions.md5 b/group___r_t_c___input__parameter__format__definitions.md5 new file mode 100644 index 0000000..c6c63c4 --- /dev/null +++ b/group___r_t_c___input__parameter__format__definitions.md5 @@ -0,0 +1 @@ +37e581b8f5ccb4e3e94ea40cab63a8d4 \ No newline at end of file diff --git a/group___r_t_c___input__parameter__format__definitions.png b/group___r_t_c___input__parameter__format__definitions.png new file mode 100644 index 0000000..5891b3d Binary files /dev/null and b/group___r_t_c___input__parameter__format__definitions.png differ diff --git a/group___r_t_c___interrupts___definitions.html b/group___r_t_c___interrupts___definitions.html new file mode 100644 index 0000000..217d5e8 --- /dev/null +++ b/group___r_t_c___interrupts___definitions.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: RTC_Interrupts_Definitions + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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RTC_Interrupts_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Interrupts_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_IT_TS   ((uint32_t)0x00008000)
 
+#define RTC_IT_WUT   ((uint32_t)0x00004000)
 
+#define RTC_IT_ALRB   ((uint32_t)0x00002000)
 
+#define RTC_IT_ALRA   ((uint32_t)0x00001000)
 
+#define RTC_IT_TAMP   ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
 
+#define RTC_IT_TAMP1   ((uint32_t)0x00020000)
 
+#define IS_RTC_CONFIG_IT(IT)   (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
 
#define IS_RTC_GET_IT(IT)
 
+#define IS_RTC_CLEAR_IT(IT)   (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_GET_IT( IT)
+
+Value:
(((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+
((IT) == RTC_IT_TAMP1))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___interrupts___definitions.map b/group___r_t_c___interrupts___definitions.map new file mode 100644 index 0000000..0ee35ab --- /dev/null +++ b/group___r_t_c___interrupts___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___interrupts___definitions.md5 b/group___r_t_c___interrupts___definitions.md5 new file mode 100644 index 0000000..6a56f79 --- /dev/null +++ b/group___r_t_c___interrupts___definitions.md5 @@ -0,0 +1 @@ +04815159212d4ff450015d430a33024f \ No newline at end of file diff --git a/group___r_t_c___interrupts___definitions.png b/group___r_t_c___interrupts___definitions.png new file mode 100644 index 0000000..59a1c16 Binary files /dev/null and b/group___r_t_c___interrupts___definitions.png differ diff --git a/group___r_t_c___legacy.html b/group___r_t_c___legacy.html new file mode 100644 index 0000000..cd0fc56 --- /dev/null +++ b/group___r_t_c___legacy.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: RTC_Legacy + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Legacy
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Legacy:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define RTC_DigitalCalibConfig   RTC_CoarseCalibConfig
 
+#define RTC_DigitalCalibCmd   RTC_CoarseCalibCmd
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___legacy.map b/group___r_t_c___legacy.map new file mode 100644 index 0000000..f632b90 --- /dev/null +++ b/group___r_t_c___legacy.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___legacy.md5 b/group___r_t_c___legacy.md5 new file mode 100644 index 0000000..3ba50b3 --- /dev/null +++ b/group___r_t_c___legacy.md5 @@ -0,0 +1 @@ +28cc0ee651f5652371edb31403a4c3dd \ No newline at end of file diff --git a/group___r_t_c___legacy.png b/group___r_t_c___legacy.png new file mode 100644 index 0000000..037eda9 Binary files /dev/null and b/group___r_t_c___legacy.png differ diff --git a/group___r_t_c___month___date___definitions.html b/group___r_t_c___month___date___definitions.html new file mode 100644 index 0000000..a72e067 --- /dev/null +++ b/group___r_t_c___month___date___definitions.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: RTC_Month_Date_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Month_Date_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Month_Date_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_Month_January   ((uint8_t)0x01)
 
+#define RTC_Month_February   ((uint8_t)0x02)
 
+#define RTC_Month_March   ((uint8_t)0x03)
 
+#define RTC_Month_April   ((uint8_t)0x04)
 
+#define RTC_Month_May   ((uint8_t)0x05)
 
+#define RTC_Month_June   ((uint8_t)0x06)
 
+#define RTC_Month_July   ((uint8_t)0x07)
 
+#define RTC_Month_August   ((uint8_t)0x08)
 
+#define RTC_Month_September   ((uint8_t)0x09)
 
+#define RTC_Month_October   ((uint8_t)0x10)
 
+#define RTC_Month_November   ((uint8_t)0x11)
 
+#define RTC_Month_December   ((uint8_t)0x12)
 
+#define IS_RTC_MONTH(MONTH)   (((MONTH) >= 1) && ((MONTH) <= 12))
 
+#define IS_RTC_DATE(DATE)   (((DATE) >= 1) && ((DATE) <= 31))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___month___date___definitions.map b/group___r_t_c___month___date___definitions.map new file mode 100644 index 0000000..0c4dbf7 --- /dev/null +++ b/group___r_t_c___month___date___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___month___date___definitions.md5 b/group___r_t_c___month___date___definitions.md5 new file mode 100644 index 0000000..22da284 --- /dev/null +++ b/group___r_t_c___month___date___definitions.md5 @@ -0,0 +1 @@ +c3e55710cf6337792e782bb690f0fea2 \ No newline at end of file diff --git a/group___r_t_c___month___date___definitions.png b/group___r_t_c___month___date___definitions.png new file mode 100644 index 0000000..c68c5ac Binary files /dev/null and b/group___r_t_c___month___date___definitions.png differ diff --git a/group___r_t_c___output___polarity___definitions.html b/group___r_t_c___output___polarity___definitions.html new file mode 100644 index 0000000..e82da1e --- /dev/null +++ b/group___r_t_c___output___polarity___definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Output_Polarity_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Output_Polarity_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Output_Polarity_Definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_OutputPolarity_High   ((uint32_t)0x00000000)
 
+#define RTC_OutputPolarity_Low   ((uint32_t)0x00100000)
 
#define IS_RTC_OUTPUT_POL(POL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_OUTPUT_POL( POL)
+
+Value:
(((POL) == RTC_OutputPolarity_High) || \
+
((POL) == RTC_OutputPolarity_Low))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___output___polarity___definitions.map b/group___r_t_c___output___polarity___definitions.map new file mode 100644 index 0000000..08cddb7 --- /dev/null +++ b/group___r_t_c___output___polarity___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___output___polarity___definitions.md5 b/group___r_t_c___output___polarity___definitions.md5 new file mode 100644 index 0000000..ff1172e --- /dev/null +++ b/group___r_t_c___output___polarity___definitions.md5 @@ -0,0 +1 @@ +04d9ee76969ac4c9eeee35d40a0216d3 \ No newline at end of file diff --git a/group___r_t_c___output___polarity___definitions.png b/group___r_t_c___output___polarity___definitions.png new file mode 100644 index 0000000..86b1777 Binary files /dev/null and b/group___r_t_c___output___polarity___definitions.png differ diff --git a/group___r_t_c___output___type___a_l_a_r_m___o_u_t.html b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.html new file mode 100644 index 0000000..da287f9 --- /dev/null +++ b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Output_Type_ALARM_OUT + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
RTC_Output_Type_ALARM_OUT
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Output_Type_ALARM_OUT:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_OutputType_OpenDrain   ((uint32_t)0x00000000)
 
+#define RTC_OutputType_PushPull   ((uint32_t)0x00040000)
 
#define IS_RTC_OUTPUT_TYPE(TYPE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_OUTPUT_TYPE( TYPE)
+
+Value:
(((TYPE) == RTC_OutputType_OpenDrain) || \
+
((TYPE) == RTC_OutputType_PushPull))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___output___type___a_l_a_r_m___o_u_t.map b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.map new file mode 100644 index 0000000..5a9569b --- /dev/null +++ b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___output___type___a_l_a_r_m___o_u_t.md5 b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.md5 new file mode 100644 index 0000000..571267d --- /dev/null +++ b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.md5 @@ -0,0 +1 @@ +22d5c4976830b7456c304db6c78dda3f \ No newline at end of file diff --git a/group___r_t_c___output___type___a_l_a_r_m___o_u_t.png b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.png new file mode 100644 index 0000000..de7bb79 Binary files /dev/null and b/group___r_t_c___output___type___a_l_a_r_m___o_u_t.png differ diff --git a/group___r_t_c___output__selection___definitions.html b/group___r_t_c___output__selection___definitions.html new file mode 100644 index 0000000..363d0ca --- /dev/null +++ b/group___r_t_c___output__selection___definitions.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: RTC_Output_selection_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Output_selection_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Output_selection_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define RTC_Output_Disable   ((uint32_t)0x00000000)
 
+#define RTC_Output_AlarmA   ((uint32_t)0x00200000)
 
+#define RTC_Output_AlarmB   ((uint32_t)0x00400000)
 
+#define RTC_Output_WakeUp   ((uint32_t)0x00600000)
 
#define IS_RTC_OUTPUT(OUTPUT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_OUTPUT( OUTPUT)
+
+Value:
(((OUTPUT) == RTC_Output_Disable) || \
+
((OUTPUT) == RTC_Output_AlarmA) || \
+
((OUTPUT) == RTC_Output_AlarmB) || \
+
((OUTPUT) == RTC_Output_WakeUp))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___output__selection___definitions.map b/group___r_t_c___output__selection___definitions.map new file mode 100644 index 0000000..12d907c --- /dev/null +++ b/group___r_t_c___output__selection___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___output__selection___definitions.md5 b/group___r_t_c___output__selection___definitions.md5 new file mode 100644 index 0000000..b56cba9 --- /dev/null +++ b/group___r_t_c___output__selection___definitions.md5 @@ -0,0 +1 @@ +a054ef6f18ed941a70ace20205ca67b4 \ No newline at end of file diff --git a/group___r_t_c___output__selection___definitions.png b/group___r_t_c___output__selection___definitions.png new file mode 100644 index 0000000..73ec188 Binary files /dev/null and b/group___r_t_c___output__selection___definitions.png differ diff --git a/group___r_t_c___private___functions.html b/group___r_t_c___private___functions.html new file mode 100644 index 0000000..3208da0 --- /dev/null +++ b/group___r_t_c___private___functions.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: RTC_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
RTC_Private_Functions
STM32F4xx_StdPeriph_Driver » RTC
+
+
+
+Collaboration diagram for RTC_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Time and Date configuration functions
 Time and Date configuration functions.
 
 Alarms configuration functions
 Alarms (Alarm A and Alarm B) configuration functions.
 
 WakeUp Timer configuration functions
 WakeUp Timer configuration functions.
 
 Daylight Saving configuration functions
 Daylight Saving configuration functions.
 
 Output pin Configuration function
 Output pin Configuration function.
 
 Digital Calibration configuration functions
 Coarse Calibration configuration functions.
 
 TimeStamp configuration functions
 TimeStamp configuration functions.
 
 Tampers configuration functions
 Tampers configuration functions.
 
 Backup Data Registers configuration functions
 Backup Data Registers configuration functions.
 
 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions.
 
 Shift control synchronisation functions
 Shift control synchronisation functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___private___functions.map b/group___r_t_c___private___functions.map new file mode 100644 index 0000000..3307e28 --- /dev/null +++ b/group___r_t_c___private___functions.map @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/group___r_t_c___private___functions.md5 b/group___r_t_c___private___functions.md5 new file mode 100644 index 0000000..4253903 --- /dev/null +++ b/group___r_t_c___private___functions.md5 @@ -0,0 +1 @@ +845aedf956b7acccf0a7817ef3f56c24 \ No newline at end of file diff --git a/group___r_t_c___private___functions.png b/group___r_t_c___private___functions.png new file mode 100644 index 0000000..230e9a9 Binary files /dev/null and b/group___r_t_c___private___functions.png differ diff --git a/group___r_t_c___smooth__calib___minus__pulses___definitions.html b/group___r_t_c___smooth__calib___minus__pulses___definitions.html new file mode 100644 index 0000000..b176500 --- /dev/null +++ b/group___r_t_c___smooth__calib___minus__pulses___definitions.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Smooth_calib_Minus_pulses_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Smooth_calib_Minus_pulses_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Smooth_calib_Minus_pulses_Definitions:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE)   ((VALUE) <= 0x000001FF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___smooth__calib___minus__pulses___definitions.map b/group___r_t_c___smooth__calib___minus__pulses___definitions.map new file mode 100644 index 0000000..abd637a --- /dev/null +++ b/group___r_t_c___smooth__calib___minus__pulses___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___smooth__calib___minus__pulses___definitions.md5 b/group___r_t_c___smooth__calib___minus__pulses___definitions.md5 new file mode 100644 index 0000000..5830179 --- /dev/null +++ b/group___r_t_c___smooth__calib___minus__pulses___definitions.md5 @@ -0,0 +1 @@ +f5183b0a625c71b3cc68c677072159c4 \ No newline at end of file diff --git a/group___r_t_c___smooth__calib___minus__pulses___definitions.png b/group___r_t_c___smooth__calib___minus__pulses___definitions.png new file mode 100644 index 0000000..5563733 Binary files /dev/null and b/group___r_t_c___smooth__calib___minus__pulses___definitions.png differ diff --git a/group___r_t_c___smooth__calib___plus__pulses___definitions.html b/group___r_t_c___smooth__calib___plus__pulses___definitions.html new file mode 100644 index 0000000..22f9cc4 --- /dev/null +++ b/group___r_t_c___smooth__calib___plus__pulses___definitions.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: RTC_Smooth_calib_Plus_pulses_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
RTC_Smooth_calib_Plus_pulses_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Smooth_calib_Plus_pulses_Definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define RTC_SmoothCalibPlusPulses_Set   ((uint32_t)0x00008000)
 
#define RTC_SmoothCalibPlusPulses_Reset   ((uint32_t)0x00000000)
 
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_SMOOTH_CALIB_PLUS( PLUS)
+
+Value:
(((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
RTC_SmoothCalibPlusPulses_Reset
#define RTC_SmoothCalibPlusPulses_Reset
Definition: stm32f4xx_rtc.h:492
+
RTC_SmoothCalibPlusPulses_Set
#define RTC_SmoothCalibPlusPulses_Set
Definition: stm32f4xx_rtc.h:487
+
+
+
+ +
+
+ + + + +
#define RTC_SmoothCalibPlusPulses_Reset   ((uint32_t)0x00000000)
+
+

The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0].

+ +
+
+ +
+
+ + + + +
#define RTC_SmoothCalibPlusPulses_Set   ((uint32_t)0x00008000)
+
+

The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0]. with Y = 512, 256, 128 when X = 32, 16, 8

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___smooth__calib___plus__pulses___definitions.map b/group___r_t_c___smooth__calib___plus__pulses___definitions.map new file mode 100644 index 0000000..ba03fb3 --- /dev/null +++ b/group___r_t_c___smooth__calib___plus__pulses___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___smooth__calib___plus__pulses___definitions.md5 b/group___r_t_c___smooth__calib___plus__pulses___definitions.md5 new file mode 100644 index 0000000..19acdfa --- /dev/null +++ b/group___r_t_c___smooth__calib___plus__pulses___definitions.md5 @@ -0,0 +1 @@ +4e14571fb01ef88df2ef1b20901505b3 \ No newline at end of file diff --git a/group___r_t_c___smooth__calib___plus__pulses___definitions.png b/group___r_t_c___smooth__calib___plus__pulses___definitions.png new file mode 100644 index 0000000..cb8d533 Binary files /dev/null and b/group___r_t_c___smooth__calib___plus__pulses___definitions.png differ diff --git a/group___r_t_c___smooth__calib__period___definitions.html b/group___r_t_c___smooth__calib__period___definitions.html new file mode 100644 index 0000000..4b1db42 --- /dev/null +++ b/group___r_t_c___smooth__calib__period___definitions.html @@ -0,0 +1,176 @@ + + + + + + +discoverpixy: RTC_Smooth_calib_period_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
RTC_Smooth_calib_period_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Smooth_calib_period_Definitions:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000)
 
#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000)
 
#define RTC_SmoothCalibPeriod_8sec   ((uint32_t)0x00004000)
 
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_SMOOTH_CALIB_PERIOD( PERIOD)
+
+Value:
(((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
RTC_SmoothCalibPeriod_8sec
#define RTC_SmoothCalibPeriod_8sec
Definition: stm32f4xx_rtc.h:473
+
RTC_SmoothCalibPeriod_16sec
#define RTC_SmoothCalibPeriod_16sec
Definition: stm32f4xx_rtc.h:470
+
RTC_SmoothCalibPeriod_32sec
#define RTC_SmoothCalibPeriod_32sec
Definition: stm32f4xx_rtc.h:467
+
+
+
+ +
+
+ + + + +
#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000)
+
+

if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds

+ +
+
+ +
+
+ + + + +
#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000)
+
+

if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds

+ +
+
+ +
+
+ + + + +
#define RTC_SmoothCalibPeriod_8sec   ((uint32_t)0x00004000)
+
+

if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___smooth__calib__period___definitions.map b/group___r_t_c___smooth__calib__period___definitions.map new file mode 100644 index 0000000..005e26d --- /dev/null +++ b/group___r_t_c___smooth__calib__period___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___smooth__calib__period___definitions.md5 b/group___r_t_c___smooth__calib__period___definitions.md5 new file mode 100644 index 0000000..5655f03 --- /dev/null +++ b/group___r_t_c___smooth__calib__period___definitions.md5 @@ -0,0 +1 @@ +e1bf8f7c98343128355c086531fd4a37 \ No newline at end of file diff --git a/group___r_t_c___smooth__calib__period___definitions.png b/group___r_t_c___smooth__calib__period___definitions.png new file mode 100644 index 0000000..49d7b3d Binary files /dev/null and b/group___r_t_c___smooth__calib__period___definitions.png differ diff --git a/group___r_t_c___substract___fraction___of___second___value.html b/group___r_t_c___substract___fraction___of___second___value.html new file mode 100644 index 0000000..51845ef --- /dev/null +++ b/group___r_t_c___substract___fraction___of___second___value.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Substract_Fraction_Of_Second_Value + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
RTC_Substract_Fraction_Of_Second_Value
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Substract_Fraction_Of_Second_Value:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_SHIFT_SUBFS(FS)   ((FS) <= 0x00007FFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___substract___fraction___of___second___value.map b/group___r_t_c___substract___fraction___of___second___value.map new file mode 100644 index 0000000..f00c09b --- /dev/null +++ b/group___r_t_c___substract___fraction___of___second___value.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___substract___fraction___of___second___value.md5 b/group___r_t_c___substract___fraction___of___second___value.md5 new file mode 100644 index 0000000..c7cb1a3 --- /dev/null +++ b/group___r_t_c___substract___fraction___of___second___value.md5 @@ -0,0 +1 @@ +cda63f6a90210bbee4420052202b4780 \ No newline at end of file diff --git a/group___r_t_c___substract___fraction___of___second___value.png b/group___r_t_c___substract___fraction___of___second___value.png new file mode 100644 index 0000000..89e6d20 Binary files /dev/null and b/group___r_t_c___substract___fraction___of___second___value.png differ diff --git a/group___r_t_c___synchronous___predivider.html b/group___r_t_c___synchronous___predivider.html new file mode 100644 index 0000000..8cb1a12 --- /dev/null +++ b/group___r_t_c___synchronous___predivider.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Synchronous_Predivider + + + + + + + + + + +
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+Macros
+
+
RTC_Synchronous_Predivider
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Synchronous_Predivider:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_SYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___synchronous___predivider.map b/group___r_t_c___synchronous___predivider.map new file mode 100644 index 0000000..2d23779 --- /dev/null +++ b/group___r_t_c___synchronous___predivider.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___synchronous___predivider.md5 b/group___r_t_c___synchronous___predivider.md5 new file mode 100644 index 0000000..5aae4be --- /dev/null +++ b/group___r_t_c___synchronous___predivider.md5 @@ -0,0 +1 @@ +d3a547c6a5cec45fdc6344d9e240af7b \ No newline at end of file diff --git a/group___r_t_c___synchronous___predivider.png b/group___r_t_c___synchronous___predivider.png new file mode 100644 index 0000000..b113113 Binary files /dev/null and b/group___r_t_c___synchronous___predivider.png differ diff --git a/group___r_t_c___tamper___filter___definitions.html b/group___r_t_c___tamper___filter___definitions.html new file mode 100644 index 0000000..5ccb6c4 --- /dev/null +++ b/group___r_t_c___tamper___filter___definitions.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: RTC_Tamper_Filter_Definitions + + + + + + + + + + +
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+ + + + + + +
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+Macros
+
+
RTC_Tamper_Filter_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Filter_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000)
 
#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800)
 
#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000)
 
#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800)
 
#define IS_RTC_TAMPER_FILTER(FILTER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TAMPER_FILTER( FILTER)
+
+Value:
(((FILTER) == RTC_TamperFilter_Disable) || \
+
((FILTER) == RTC_TamperFilter_2Sample) || \
+
((FILTER) == RTC_TamperFilter_4Sample) || \
+
((FILTER) == RTC_TamperFilter_8Sample))
+
RTC_TamperFilter_8Sample
#define RTC_TamperFilter_8Sample
Definition: stm32f4xx_rtc.h:554
+
RTC_TamperFilter_2Sample
#define RTC_TamperFilter_2Sample
Definition: stm32f4xx_rtc.h:548
+
RTC_TamperFilter_4Sample
#define RTC_TamperFilter_4Sample
Definition: stm32f4xx_rtc.h:551
+
RTC_TamperFilter_Disable
#define RTC_TamperFilter_Disable
Definition: stm32f4xx_rtc.h:546
+
+
+
+ +
+
+ + + + +
#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800)
+
+

Tamper is activated after 2 consecutive samples at the active level

+ +
+
+ +
+
+ + + + +
#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000)
+
+

Tamper is activated after 4 consecutive samples at the active level

+ +
+
+ +
+
+ + + + +
#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800)
+
+

Tamper is activated after 8 consecutive samples at the active leve.

+ +
+
+ +
+
+ + + + +
#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000)
+
+

Tamper filter is disabled

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___filter___definitions.map b/group___r_t_c___tamper___filter___definitions.map new file mode 100644 index 0000000..cf5706e --- /dev/null +++ b/group___r_t_c___tamper___filter___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___filter___definitions.md5 b/group___r_t_c___tamper___filter___definitions.md5 new file mode 100644 index 0000000..f081ee0 --- /dev/null +++ b/group___r_t_c___tamper___filter___definitions.md5 @@ -0,0 +1 @@ +0829c24115596b71986d432eed94b092 \ No newline at end of file diff --git a/group___r_t_c___tamper___filter___definitions.png b/group___r_t_c___tamper___filter___definitions.png new file mode 100644 index 0000000..54299a4 Binary files /dev/null and b/group___r_t_c___tamper___filter___definitions.png differ diff --git a/group___r_t_c___tamper___pin___precharge___duration___definitions.html b/group___r_t_c___tamper___pin___precharge___duration___definitions.html new file mode 100644 index 0000000..01c55f7 --- /dev/null +++ b/group___r_t_c___tamper___pin___precharge___duration___definitions.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: RTC_Tamper_Pin_Precharge_Duration_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+Macros
+
+
RTC_Tamper_Pin_Precharge_Duration_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Pin_Precharge_Duration_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define RTC_TamperPrechargeDuration_1RTCCLK   ((uint32_t)0x00000000)
 
#define RTC_TamperPrechargeDuration_2RTCCLK   ((uint32_t)0x00002000)
 
#define RTC_TamperPrechargeDuration_4RTCCLK   ((uint32_t)0x00004000)
 
#define RTC_TamperPrechargeDuration_8RTCCLK   ((uint32_t)0x00006000)
 
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TAMPER_PRECHARGE_DURATION( DURATION)
+
+Value:
(((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+
RTC_TamperPrechargeDuration_4RTCCLK
#define RTC_TamperPrechargeDuration_4RTCCLK
Definition: stm32f4xx_rtc.h:614
+
RTC_TamperPrechargeDuration_1RTCCLK
#define RTC_TamperPrechargeDuration_1RTCCLK
Definition: stm32f4xx_rtc.h:608
+
RTC_TamperPrechargeDuration_2RTCCLK
#define RTC_TamperPrechargeDuration_2RTCCLK
Definition: stm32f4xx_rtc.h:611
+
RTC_TamperPrechargeDuration_8RTCCLK
#define RTC_TamperPrechargeDuration_8RTCCLK
Definition: stm32f4xx_rtc.h:617
+
+
+
+ +
+
+ + + + +
#define RTC_TamperPrechargeDuration_1RTCCLK   ((uint32_t)0x00000000)
+
+

Tamper pins are pre-charged before sampling during 1 RTCCLK cycle

+ +
+
+ +
+
+ + + + +
#define RTC_TamperPrechargeDuration_2RTCCLK   ((uint32_t)0x00002000)
+
+

Tamper pins are pre-charged before sampling during 2 RTCCLK cycles

+ +
+
+ +
+
+ + + + +
#define RTC_TamperPrechargeDuration_4RTCCLK   ((uint32_t)0x00004000)
+
+

Tamper pins are pre-charged before sampling during 4 RTCCLK cycles

+ +
+
+ +
+
+ + + + +
#define RTC_TamperPrechargeDuration_8RTCCLK   ((uint32_t)0x00006000)
+
+

Tamper pins are pre-charged before sampling during 8 RTCCLK cycles

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___pin___precharge___duration___definitions.map b/group___r_t_c___tamper___pin___precharge___duration___definitions.map new file mode 100644 index 0000000..d6e458a --- /dev/null +++ b/group___r_t_c___tamper___pin___precharge___duration___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___pin___precharge___duration___definitions.md5 b/group___r_t_c___tamper___pin___precharge___duration___definitions.md5 new file mode 100644 index 0000000..1a6e0e8 --- /dev/null +++ b/group___r_t_c___tamper___pin___precharge___duration___definitions.md5 @@ -0,0 +1 @@ +9c19503ae1ce1a9d2fa6f6b0f0967142 \ No newline at end of file diff --git a/group___r_t_c___tamper___pin___precharge___duration___definitions.png b/group___r_t_c___tamper___pin___precharge___duration___definitions.png new file mode 100644 index 0000000..1a5ece3 Binary files /dev/null and b/group___r_t_c___tamper___pin___precharge___duration___definitions.png differ diff --git a/group___r_t_c___tamper___pin___selection.html b/group___r_t_c___tamper___pin___selection.html new file mode 100644 index 0000000..9c5bcde --- /dev/null +++ b/group___r_t_c___tamper___pin___selection.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Tamper_Pin_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+Macros
+
+
RTC_Tamper_Pin_Selection
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Pin_Selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_TamperPin_PC13   ((uint32_t)0x00000000)
 
+#define RTC_TamperPin_PI8   ((uint32_t)0x00010000)
 
#define IS_RTC_TAMPER_PIN(PIN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TAMPER_PIN( PIN)
+
+Value:
(((PIN) == RTC_TamperPin_PC13) || \
+
((PIN) == RTC_TamperPin_PI8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___pin___selection.map b/group___r_t_c___tamper___pin___selection.map new file mode 100644 index 0000000..5d9a032 --- /dev/null +++ b/group___r_t_c___tamper___pin___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___pin___selection.md5 b/group___r_t_c___tamper___pin___selection.md5 new file mode 100644 index 0000000..a410770 --- /dev/null +++ b/group___r_t_c___tamper___pin___selection.md5 @@ -0,0 +1 @@ +2318784becf43dabc1a84a76011cb78f \ No newline at end of file diff --git a/group___r_t_c___tamper___pin___selection.png b/group___r_t_c___tamper___pin___selection.png new file mode 100644 index 0000000..d463a02 Binary files /dev/null and b/group___r_t_c___tamper___pin___selection.png differ diff --git a/group___r_t_c___tamper___pins___definitions.html b/group___r_t_c___tamper___pins___definitions.html new file mode 100644 index 0000000..60d9143 --- /dev/null +++ b/group___r_t_c___tamper___pins___definitions.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: RTC_Tamper_Pins_Definitions + + + + + + + + + + +
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+Macros
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+
RTC_Tamper_Pins_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Pins_Definitions:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define RTC_Tamper_1   RTC_TAFCR_TAMP1E
 
+#define IS_RTC_TAMPER(TAMPER)   (((TAMPER) == RTC_Tamper_1))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___pins___definitions.map b/group___r_t_c___tamper___pins___definitions.map new file mode 100644 index 0000000..e2ea4bb --- /dev/null +++ b/group___r_t_c___tamper___pins___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___pins___definitions.md5 b/group___r_t_c___tamper___pins___definitions.md5 new file mode 100644 index 0000000..75836e4 --- /dev/null +++ b/group___r_t_c___tamper___pins___definitions.md5 @@ -0,0 +1 @@ +ee42b109a4c7114a6bd222b189d4d20a \ No newline at end of file diff --git a/group___r_t_c___tamper___pins___definitions.png b/group___r_t_c___tamper___pins___definitions.png new file mode 100644 index 0000000..07a8f1f Binary files /dev/null and b/group___r_t_c___tamper___pins___definitions.png differ diff --git a/group___r_t_c___tamper___sampling___frequencies___definitions.html b/group___r_t_c___tamper___sampling___frequencies___definitions.html new file mode 100644 index 0000000..37558b4 --- /dev/null +++ b/group___r_t_c___tamper___sampling___frequencies___definitions.html @@ -0,0 +1,261 @@ + + + + + + +discoverpixy: RTC_Tamper_Sampling_Frequencies_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
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+Macros
+
+
RTC_Tamper_Sampling_Frequencies_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Sampling_Frequencies_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define RTC_TamperSamplingFreq_RTCCLK_Div32768   ((uint32_t)0x00000000)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div16384   ((uint32_t)0x000000100)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700)
 
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TAMPER_SAMPLING_FREQ( FREQ)
+
+Value:
(((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
RTC_TamperSamplingFreq_RTCCLK_Div4096
#define RTC_TamperSamplingFreq_RTCCLK_Div4096
Definition: stm32f4xx_rtc.h:577
+
RTC_TamperSamplingFreq_RTCCLK_Div1024
#define RTC_TamperSamplingFreq_RTCCLK_Div1024
Definition: stm32f4xx_rtc.h:583
+
RTC_TamperSamplingFreq_RTCCLK_Div16384
#define RTC_TamperSamplingFreq_RTCCLK_Div16384
Definition: stm32f4xx_rtc.h:571
+
RTC_TamperSamplingFreq_RTCCLK_Div8192
#define RTC_TamperSamplingFreq_RTCCLK_Div8192
Definition: stm32f4xx_rtc.h:574
+
RTC_TamperSamplingFreq_RTCCLK_Div32768
#define RTC_TamperSamplingFreq_RTCCLK_Div32768
Definition: stm32f4xx_rtc.h:568
+
RTC_TamperSamplingFreq_RTCCLK_Div512
#define RTC_TamperSamplingFreq_RTCCLK_Div512
Definition: stm32f4xx_rtc.h:586
+
RTC_TamperSamplingFreq_RTCCLK_Div256
#define RTC_TamperSamplingFreq_RTCCLK_Div256
Definition: stm32f4xx_rtc.h:589
+
RTC_TamperSamplingFreq_RTCCLK_Div2048
#define RTC_TamperSamplingFreq_RTCCLK_Div2048
Definition: stm32f4xx_rtc.h:580
+
+
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div16384   ((uint32_t)0x000000100)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 256

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div32768   ((uint32_t)0x00000000)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 512

+ +
+
+ +
+
+ + + + +
#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200)
+
+

Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___sampling___frequencies___definitions.map b/group___r_t_c___tamper___sampling___frequencies___definitions.map new file mode 100644 index 0000000..1ded155 --- /dev/null +++ b/group___r_t_c___tamper___sampling___frequencies___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___sampling___frequencies___definitions.md5 b/group___r_t_c___tamper___sampling___frequencies___definitions.md5 new file mode 100644 index 0000000..17b5866 --- /dev/null +++ b/group___r_t_c___tamper___sampling___frequencies___definitions.md5 @@ -0,0 +1 @@ +cda9e556e5af913b49bdf21eb4487be7 \ No newline at end of file diff --git a/group___r_t_c___tamper___sampling___frequencies___definitions.png b/group___r_t_c___tamper___sampling___frequencies___definitions.png new file mode 100644 index 0000000..0289ace Binary files /dev/null and b/group___r_t_c___tamper___sampling___frequencies___definitions.png differ diff --git a/group___r_t_c___tamper___trigger___definitions.html b/group___r_t_c___tamper___trigger___definitions.html new file mode 100644 index 0000000..8caf032 --- /dev/null +++ b/group___r_t_c___tamper___trigger___definitions.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: RTC_Tamper_Trigger_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
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+ +
+ +
+
+Macros
+
+
RTC_Tamper_Trigger_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Tamper_Trigger_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define RTC_TamperTrigger_RisingEdge   ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_FallingEdge   ((uint32_t)0x00000001)
 
+#define RTC_TamperTrigger_LowLevel   ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_HighLevel   ((uint32_t)0x00000001)
 
#define IS_RTC_TAMPER_TRIGGER(TRIGGER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TAMPER_TRIGGER( TRIGGER)
+
+Value:
(((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+
((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___tamper___trigger___definitions.map b/group___r_t_c___tamper___trigger___definitions.map new file mode 100644 index 0000000..8a3ae99 --- /dev/null +++ b/group___r_t_c___tamper___trigger___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___tamper___trigger___definitions.md5 b/group___r_t_c___tamper___trigger___definitions.md5 new file mode 100644 index 0000000..5ec928a --- /dev/null +++ b/group___r_t_c___tamper___trigger___definitions.md5 @@ -0,0 +1 @@ +ae878677b4d3d4ab078102a13a146f86 \ No newline at end of file diff --git a/group___r_t_c___tamper___trigger___definitions.png b/group___r_t_c___tamper___trigger___definitions.png new file mode 100644 index 0000000..629eaae Binary files /dev/null and b/group___r_t_c___tamper___trigger___definitions.png differ diff --git a/group___r_t_c___time___definitions.html b/group___r_t_c___time___definitions.html new file mode 100644 index 0000000..89de5f1 --- /dev/null +++ b/group___r_t_c___time___definitions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: RTC_Time_Definitions + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+Macros
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+
RTC_Time_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Time_Definitions:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define IS_RTC_HOUR12(HOUR)   (((HOUR) > 0) && ((HOUR) <= 12))
 
+#define IS_RTC_HOUR24(HOUR)   ((HOUR) <= 23)
 
+#define IS_RTC_MINUTES(MINUTES)   ((MINUTES) <= 59)
 
+#define IS_RTC_SECONDS(SECONDS)   ((SECONDS) <= 59)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___time___definitions.map b/group___r_t_c___time___definitions.map new file mode 100644 index 0000000..61e764f --- /dev/null +++ b/group___r_t_c___time___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___time___definitions.md5 b/group___r_t_c___time___definitions.md5 new file mode 100644 index 0000000..70d9601 --- /dev/null +++ b/group___r_t_c___time___definitions.md5 @@ -0,0 +1 @@ +2c17149a3c5857c2dc9d6d5170574017 \ No newline at end of file diff --git a/group___r_t_c___time___definitions.png b/group___r_t_c___time___definitions.png new file mode 100644 index 0000000..e198e20 Binary files /dev/null and b/group___r_t_c___time___definitions.png differ diff --git a/group___r_t_c___time___stamp___edges__definitions.html b/group___r_t_c___time___stamp___edges__definitions.html new file mode 100644 index 0000000..94e3838 --- /dev/null +++ b/group___r_t_c___time___stamp___edges__definitions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_Time_Stamp_Edges_definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ +
+ +
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+Macros
+
+
RTC_Time_Stamp_Edges_definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Time_Stamp_Edges_definitions:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_TimeStampEdge_Rising   ((uint32_t)0x00000000)
 
+#define RTC_TimeStampEdge_Falling   ((uint32_t)0x00000008)
 
#define IS_RTC_TIMESTAMP_EDGE(EDGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TIMESTAMP_EDGE( EDGE)
+
+Value:
(((EDGE) == RTC_TimeStampEdge_Rising) || \
+
((EDGE) == RTC_TimeStampEdge_Falling))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___time___stamp___edges__definitions.map b/group___r_t_c___time___stamp___edges__definitions.map new file mode 100644 index 0000000..d08295c --- /dev/null +++ b/group___r_t_c___time___stamp___edges__definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___time___stamp___edges__definitions.md5 b/group___r_t_c___time___stamp___edges__definitions.md5 new file mode 100644 index 0000000..85175ed --- /dev/null +++ b/group___r_t_c___time___stamp___edges__definitions.md5 @@ -0,0 +1 @@ +e24c7fb969aff05858fb11010726919e \ No newline at end of file diff --git a/group___r_t_c___time___stamp___edges__definitions.png b/group___r_t_c___time___stamp___edges__definitions.png new file mode 100644 index 0000000..358dd4a Binary files /dev/null and b/group___r_t_c___time___stamp___edges__definitions.png differ diff --git a/group___r_t_c___time_stamp___pin___selection.html b/group___r_t_c___time_stamp___pin___selection.html new file mode 100644 index 0000000..323ca51 --- /dev/null +++ b/group___r_t_c___time_stamp___pin___selection.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: RTC_TimeStamp_Pin_Selection + + + + + + + + + + +
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+Macros
+
+
RTC_TimeStamp_Pin_Selection
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_TimeStamp_Pin_Selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define RTC_TimeStampPin_PC13   ((uint32_t)0x00000000)
 
+#define RTC_TimeStampPin_PI8   ((uint32_t)0x00020000)
 
#define IS_RTC_TIMESTAMP_PIN(PIN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_TIMESTAMP_PIN( PIN)
+
+Value:
(((PIN) == RTC_TimeStampPin_PC13) || \
+
((PIN) == RTC_TimeStampPin_PI8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___time_stamp___pin___selection.map b/group___r_t_c___time_stamp___pin___selection.map new file mode 100644 index 0000000..558999b --- /dev/null +++ b/group___r_t_c___time_stamp___pin___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___time_stamp___pin___selection.md5 b/group___r_t_c___time_stamp___pin___selection.md5 new file mode 100644 index 0000000..38629a3 --- /dev/null +++ b/group___r_t_c___time_stamp___pin___selection.md5 @@ -0,0 +1 @@ +4bcab64db920226bbf13a5889c895757 \ No newline at end of file diff --git a/group___r_t_c___time_stamp___pin___selection.png b/group___r_t_c___time_stamp___pin___selection.png new file mode 100644 index 0000000..ed7352f Binary files /dev/null and b/group___r_t_c___time_stamp___pin___selection.png differ diff --git a/group___r_t_c___wakeup___timer___definitions.html b/group___r_t_c___wakeup___timer___definitions.html new file mode 100644 index 0000000..48430c4 --- /dev/null +++ b/group___r_t_c___wakeup___timer___definitions.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: RTC_Wakeup_Timer_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
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+ + +
+ +
+ +
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+Macros
+
+
RTC_Wakeup_Timer_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Wakeup_Timer_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_WakeUpClock_RTCCLK_Div16   ((uint32_t)0x00000000)
 
+#define RTC_WakeUpClock_RTCCLK_Div8   ((uint32_t)0x00000001)
 
+#define RTC_WakeUpClock_RTCCLK_Div4   ((uint32_t)0x00000002)
 
+#define RTC_WakeUpClock_RTCCLK_Div2   ((uint32_t)0x00000003)
 
+#define RTC_WakeUpClock_CK_SPRE_16bits   ((uint32_t)0x00000004)
 
+#define RTC_WakeUpClock_CK_SPRE_17bits   ((uint32_t)0x00000006)
 
#define IS_RTC_WAKEUP_CLOCK(CLOCK)
 
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)   ((COUNTER) <= 0xFFFF)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_WAKEUP_CLOCK( CLOCK)
+
+Value:
(((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___wakeup___timer___definitions.map b/group___r_t_c___wakeup___timer___definitions.map new file mode 100644 index 0000000..4d03e50 --- /dev/null +++ b/group___r_t_c___wakeup___timer___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___wakeup___timer___definitions.md5 b/group___r_t_c___wakeup___timer___definitions.md5 new file mode 100644 index 0000000..11a6977 --- /dev/null +++ b/group___r_t_c___wakeup___timer___definitions.md5 @@ -0,0 +1 @@ +4366d824b070597ba81e2d51e026ffc9 \ No newline at end of file diff --git a/group___r_t_c___wakeup___timer___definitions.png b/group___r_t_c___wakeup___timer___definitions.png new file mode 100644 index 0000000..32ca995 Binary files /dev/null and b/group___r_t_c___wakeup___timer___definitions.png differ diff --git a/group___r_t_c___week_day___definitions.html b/group___r_t_c___week_day___definitions.html new file mode 100644 index 0000000..9a0396a --- /dev/null +++ b/group___r_t_c___week_day___definitions.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: RTC_WeekDay_Definitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
RTC_WeekDay_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_WeekDay_Definitions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_Weekday_Monday   ((uint8_t)0x01)
 
+#define RTC_Weekday_Tuesday   ((uint8_t)0x02)
 
+#define RTC_Weekday_Wednesday   ((uint8_t)0x03)
 
+#define RTC_Weekday_Thursday   ((uint8_t)0x04)
 
+#define RTC_Weekday_Friday   ((uint8_t)0x05)
 
+#define RTC_Weekday_Saturday   ((uint8_t)0x06)
 
+#define RTC_Weekday_Sunday   ((uint8_t)0x07)
 
#define IS_RTC_WEEKDAY(WEEKDAY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_RTC_WEEKDAY( WEEKDAY)
+
+Value:
(((WEEKDAY) == RTC_Weekday_Monday) || \
+
((WEEKDAY) == RTC_Weekday_Tuesday) || \
+
((WEEKDAY) == RTC_Weekday_Wednesday) || \
+
((WEEKDAY) == RTC_Weekday_Thursday) || \
+
((WEEKDAY) == RTC_Weekday_Friday) || \
+
((WEEKDAY) == RTC_Weekday_Saturday) || \
+
((WEEKDAY) == RTC_Weekday_Sunday))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___week_day___definitions.map b/group___r_t_c___week_day___definitions.map new file mode 100644 index 0000000..842c6f6 --- /dev/null +++ b/group___r_t_c___week_day___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___week_day___definitions.md5 b/group___r_t_c___week_day___definitions.md5 new file mode 100644 index 0000000..882c4fb --- /dev/null +++ b/group___r_t_c___week_day___definitions.md5 @@ -0,0 +1 @@ +0929cb8b9ff70f2c27ca465f9c6703d9 \ No newline at end of file diff --git a/group___r_t_c___week_day___definitions.png b/group___r_t_c___week_day___definitions.png new file mode 100644 index 0000000..793ef2f Binary files /dev/null and b/group___r_t_c___week_day___definitions.png differ diff --git a/group___r_t_c___year___date___definitions.html b/group___r_t_c___year___date___definitions.html new file mode 100644 index 0000000..e6725b7 --- /dev/null +++ b/group___r_t_c___year___date___definitions.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: RTC_Year_Date_Definitions + + + + + + + + + + +
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discoverpixy +
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+ +
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+Macros
+
+
RTC_Year_Date_Definitions
STM32F4xx_StdPeriph_Driver » RTC » RTC_Exported_Constants
+
+
+
+Collaboration diagram for RTC_Year_Date_Definitions:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_RTC_YEAR(YEAR)   ((YEAR) <= 99)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___r_t_c___year___date___definitions.map b/group___r_t_c___year___date___definitions.map new file mode 100644 index 0000000..f24e40d --- /dev/null +++ b/group___r_t_c___year___date___definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___r_t_c___year___date___definitions.md5 b/group___r_t_c___year___date___definitions.md5 new file mode 100644 index 0000000..cb8bb27 --- /dev/null +++ b/group___r_t_c___year___date___definitions.md5 @@ -0,0 +1 @@ +d112d7ef7574e982c40b6531e9d96a80 \ No newline at end of file diff --git a/group___r_t_c___year___date___definitions.png b/group___r_t_c___year___date___definitions.png new file mode 100644 index 0000000..18774af Binary files /dev/null and b/group___r_t_c___year___date___definitions.png differ diff --git a/group___r_t_c_ga008ae7173b2befe876f5e76686bc9089_cgraph.map b/group___r_t_c_ga008ae7173b2befe876f5e76686bc9089_cgraph.map new file mode 100644 index 0000000..2210dfa --- /dev/null +++ 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b/group___s_a_i.html @@ -0,0 +1,1269 @@ + + + + + + +discoverpixy: SAI + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+Modules | +Classes | +Macros | +Functions
+
+
SAI
STM32F4xx_StdPeriph_Driver
+
+
+ +

SAI driver modules. +More...

+
+Collaboration diagram for SAI:
+
+
+ + +
+
+ + + + + + +

+Modules

 SAI_Exported_Constants
 
 SAI_Private_Functions
 
+ + + + + + + + + + +

+Classes

struct  SAI_InitTypeDef
 SAI Block Init structure definition. More...
 
struct  SAI_FrameInitTypeDef
 SAI Block Frame Init structure definition. More...
 
struct  SAI_SlotInitTypeDef
 SAI Block Slot Init Structure definition. More...
 
+ + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint32_t)0xFF07C010)
 
+#define FRCR_CLEAR_MASK   ((uint32_t)0xFFF88000)
 
+#define SLOTR_CLEAR_MASK   ((uint32_t)0x0000F020)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SAI_DeInit (SAI_TypeDef *SAIx)
 Deinitialize the SAIx peripheral registers to their default reset values. More...
 
void SAI_Init (SAI_Block_TypeDef *SAI_Block_x, SAI_InitTypeDef *SAI_InitStruct)
 Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct. More...
 
void SAI_FrameInit (SAI_Block_TypeDef *SAI_Block_x, SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct. More...
 
void SAI_SlotInit (SAI_Block_TypeDef *SAI_Block_x, SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct. More...
 
void SAI_StructInit (SAI_InitTypeDef *SAI_InitStruct)
 Fills each SAI_InitStruct member with its default value. More...
 
void SAI_FrameStructInit (SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Fills each SAI_FrameInitStruct member with its default value. More...
 
void SAI_SlotStructInit (SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Fills each SAI_SlotInitStruct member with its default value. More...
 
void SAI_Cmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the specified SAI Block peripheral. More...
 
void SAI_MonoModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_Mono_StreoMode)
 Configures the mono mode for the selected SAI block. More...
 
void SAI_TRIStateConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_TRIState)
 Configures the TRIState managment on data line for the selected SAI block. More...
 
void SAI_CompandingModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_CompandingMode)
 Configures the companding mode for the selected SAI block. More...
 
void SAI_MuteModeCmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_MuteValueConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteValue)
 Configure the mute value for the selected SAI block. More...
 
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteCounter)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_FlushFIFO (SAI_Block_TypeDef *SAI_Block_x)
 Reinitialize the FIFO pointer. More...
 
void SAI_SendData (SAI_Block_TypeDef *SAI_Block_x, uint32_t Data)
 Transmits a Data through the SAI block x peripheral. More...
 
uint32_t SAI_ReceiveData (SAI_Block_TypeDef *SAI_Block_x)
 Returns the most recent received data by the SAI block x peripheral. More...
 
void SAI_DMACmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the SAI Block x DMA interface. More...
 
void SAI_ITConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
 Enables or disables the specified SAI Block interrupts. More...
 
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Checks whether the specified SAI block x flag is set or not. More...
 
void SAI_ClearFlag (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Clears the specified SAI Block x flag. More...
 
ITStatus SAI_GetITStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Checks whether the specified SAI Block x interrupt has occurred or not. More...
 
void SAI_ClearITPendingBit (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Clears the SAI Block x interrupt pending bit. More...
 
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the status of EN bit for the specified SAI Block x. More...
 
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the current SAI Block x FIFO filled level. More...
 
+

Detailed Description

+

SAI driver modules.

+

Function Documentation

+ +
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void SAI_ClearFlag (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_FLAG 
)
+
+ +

Clears the specified SAI Block x flag.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FLAGspecifies the SAI block flag to check. This parameter can be one of the following values:
    +
  • SAI_FLAG_MUTEDET: MUTE detection flag.
    • +
  • SAI_FLAG_OVRUDR: overrun/underrun flag.
    • +
  • SAI_FLAG_WCKCFG: wrong clock configuration flag.
    • +
  • SAI_FLAG_CNRDY: codec not ready flag.
    • +
  • SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
    • +
  • SAI_FLAG_LFSDET: late frame synchronization detection flag.
    • +
+
+
+
+
Note
FREQ (FIFO Request) flag is cleared :
    +
  • When the audio block is transmitter and the FIFO is full or the FIFO has one data (one buffer mode) depending the bit FTH in the SAI_xCR2 register.
    • +
  • When the audio block is receiver and the FIFO is not empty
    • +
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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void SAI_ClearITPendingBit (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT 
)
+
+ +

Clears the SAI Block x interrupt pending bit.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI Block interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • SAI_IT_MUTEDET: MUTE detection interrupt.
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt.
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt.
    • +
  • SAI_IT_CNRDY: codec not ready interrupt.
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt.
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt.
    • +
+
+
+
+
Note
FREQ (FIFO Request) flag is cleared :
    +
  • When the audio block is transmitter and the FIFO is full or the FIFO has one data (one buffer mode) depending the bit FTH in the SAI_xCR2 register.
    • +
  • When the audio block is receiver and the FIFO is not empty
    • +
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_Cmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SAI Block peripheral.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the SAI_Block_x peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_CompandingModeConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_CompandingMode 
)
+
+ +

Configures the companding mode for the selected SAI block.

+
Note
The data expansion or data compression are determined by the state of SAI block selected (transmitter or receiver).
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_CompandingModespecifies the SAI block companding mode. This parameter can be one of the following values:
    +
  • SAI_NoCompanding : no companding algorithm set
    • +
  • SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation)
    • +
  • SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation)
    • +
  • SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation)
    • +
  • SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
void SAI_DeInit (SAI_TypeDef * SAIx)
+
+ +

Deinitialize the SAIx peripheral registers to their default reset values.

+
Parameters
+ + +
SAIxTo select the SAIx peripheral, where x can be the different instances
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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void SAI_DMACmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the SAI Block x DMA interface.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the selected SAI block DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
void SAI_FlushFIFO (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Reinitialize the FIFO pointer.

+
Note
The FIFO pointers can be reinitialized at anytime The data present into the FIFO, if it is not empty, will be lost.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the selected SAI TI communication mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_FrameInit (SAI_Block_TypeDef * SAI_Block_x,
SAI_FrameInitTypeDef * SAI_FrameInitStruct 
)
+
+ +

Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct.

+
Note
this function has no meaning if the AC'97 or SPDIF audio protocol are selected.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FrameInitStructpointer to an SAI_FrameInitTypeDef structure that contains the configuration of audio frame for a specified SAI Block
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_FrameStructInit (SAI_FrameInitTypeDef * SAI_FrameInitStruct)
+
+ +

Fills each SAI_FrameInitStruct member with its default value.

+
Parameters
+ + +
SAI_FrameInitStructpointer to a SAI_FrameInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the status of EN bit for the specified SAI Block x.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Note
After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing, the current frame will be transferred and the block will be effectively disabled only at the end of audio frame.
+
Return values
+ + +
Currentstate of the DMAy Streamx (ENABLE or DISABLE).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the current SAI Block x FIFO filled level.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Return values
+ + +
TheFIFO filling state.
    +
  • SAI_FIFOStatus_Empty: when FIFO is empty
    • +
  • SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
    • +
  • SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
    • +
  • SAI_FIFOStatus_HalfFull: if more than 1 half-full.
    • +
  • SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
    • +
  • SAI_FIFOStatus_Full: when FIFO is full
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_FLAG 
)
+
+ +

Checks whether the specified SAI block x flag is set or not.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FLAGspecifies the SAI block flag to check. This parameter can be one of the following values:
    +
  • SAI_FLAG_FREQ: FIFO Request flag.
    • +
  • SAI_FLAG_MUTEDET: MUTE detection flag.
    • +
  • SAI_FLAG_OVRUDR: overrun/underrun flag.
    • +
  • SAI_FLAG_WCKCFG: wrong clock configuration flag.
    • +
  • SAI_FLAG_CNRDY: codec not ready flag.
    • +
  • SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
    • +
  • SAI_FLAG_LFSDET: late frame synchronization detection flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SAI_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus SAI_GetITStatus (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT 
)
+
+ +

Checks whether the specified SAI Block x interrupt has occurred or not.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SAI_IT_FREQ: FIFO Request interrupt
    • +
  • SAI_IT_MUTEDET: MUTE detection interrupt
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt
    • +
  • SAI_IT_CNRDY: codec not ready interrupt
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of SAI_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_Init (SAI_Block_TypeDef * SAI_Block_x,
SAI_InitTypeDef * SAI_InitStruct 
)
+
+ +

Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct.

+
Note
SAI clock is generated from a specific output of the PLLSAI or a specific output of the PLLI2S or from an alternate function bypassing the PLL I2S.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_InitStructpointer to a SAI_InitTypeDef structure that contains the configuration information for the specified SAI Block peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_ITConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SAI Block interrupts.

+
Parameters
+ + + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SAI_IT_FREQ: FIFO Request interrupt mask
    • +
  • SAI_IT_MUTEDET: MUTE detection interrupt mask
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt mask
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt mask
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt mask
    • +
  • SAI_IT_CNRDY: codec not ready interrupt mask
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt mask
    • +
+
NewStatenew state of the specified SAI interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MonoModeConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_Mono_StreoMode 
)
+
+ +

Configures the mono mode for the selected SAI block.

+
Note
This function has a meaning only when the number of slot is equal to 2.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MonoModespecifies the SAI block mono mode. This parameter can be one of the following values:
    +
  • SAI_MonoMode : Set mono audio mode
    • +
  • SAI_StreoMode : Set streo audio mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_MuteCounter 
)
+
+ +

Enables or disables the Mute mode for the selected SAI block.

+
Note
This function has a meaning only when the audio block is Receiver
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MuteCounterspecifies the SAI block mute value. This parameter can be a number between 0 and 63.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteModeCmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the Mute mode for the selected SAI block.

+
Note
This function has a meaning only when the audio block is transmitter
+
+Mute mode is applied for an entire frame for all the valid slot It becomes active at the end of an audio frame when set somewhere in a frame. Mute mode exit occurs at the end of the frame in which the bit MUTE has been set.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the SAIx block. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteValueConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_MuteValue 
)
+
+ +

Configure the mute value for the selected SAI block.

+
Note
This function has a meaning only when the audio block is transmitter
+
+the configuration last value sent during mute mode has only a meaning when the number of slot is lower or equal to 2 and if the MUTE bit is set.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MuteValuespecifies the SAI block mute value. This parameter can be one of the following values:
    +
  • SAI_ZeroValue : bit value 0 is sent during Mute Mode
    • +
  • SAI_LastSentValue : Last value is sent during Mute Mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SAI_ReceiveData (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the most recent received data by the SAI block x peripheral.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_SendData (SAI_Block_TypeDef * SAI_Block_x,
uint32_t Data 
)
+
+ +

Transmits a Data through the SAI block x peripheral.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
DataData to be transmitted.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_SlotInit (SAI_Block_TypeDef * SAI_Block_x,
SAI_SlotInitTypeDef * SAI_SlotInitStruct 
)
+
+ +

Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct.

+
Note
this function has no meaning if the AC'97 or SPDIF audio protocol are selected.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_SlotInitStructpointer to an SAI_SlotInitTypeDef structure that contains the configuration of audio slot for a specified SAI Block
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_SlotStructInit (SAI_SlotInitTypeDef * SAI_SlotInitStruct)
+
+ +

Fills each SAI_SlotInitStruct member with its default value.

+
Parameters
+ + +
SAI_SlotInitStructpointer to a SAI_SlotInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_StructInit (SAI_InitTypeDef * SAI_InitStruct)
+
+ +

Fills each SAI_InitStruct member with its default value.

+
Parameters
+ + +
SAI_InitStructpointer to a SAI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TRIStateConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_TRIState 
)
+
+ +

Configures the TRIState managment on data line for the selected SAI block.

+
Note
This function has a meaning only when the SAI block is configured in transmitter
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_TRIStatespecifies the SAI block TRIState management. This parameter can be one of the following values:
    +
  • SAI_Output_NotReleased : SD output line is still drived by the SAI.
    • +
  • SAI_Output_Released : SD output line is released (HI-Z)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i.map b/group___s_a_i.map new file mode 100644 index 0000000..fb4130c --- /dev/null +++ b/group___s_a_i.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___s_a_i.md5 b/group___s_a_i.md5 new file mode 100644 index 0000000..5c2eeed --- /dev/null +++ b/group___s_a_i.md5 @@ -0,0 +1 @@ +a039404dd32012ccca2ea65168b7e8de \ No newline at end of file diff --git a/group___s_a_i.png b/group___s_a_i.png new file mode 100644 index 0000000..96eef47 Binary files /dev/null and b/group___s_a_i.png differ diff --git a/group___s_a_i___block___active___frame_length.html b/group___s_a_i___block___active___frame_length.html new file mode 100644 index 0000000..42f8201 --- /dev/null +++ b/group___s_a_i___block___active___frame_length.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Active_FrameLength + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Active_FrameLength
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Active_FrameLength:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH)   ((1 <= (LENGTH)) && ((LENGTH) <= 128))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___active___frame_length.map b/group___s_a_i___block___active___frame_length.map new file mode 100644 index 0000000..f8d8ba1 --- /dev/null +++ b/group___s_a_i___block___active___frame_length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___active___frame_length.md5 b/group___s_a_i___block___active___frame_length.md5 new file mode 100644 index 0000000..02a7c11 --- /dev/null +++ b/group___s_a_i___block___active___frame_length.md5 @@ -0,0 +1 @@ +e8b2c50b4245af8767048c7f8f9ea5b0 \ No newline at end of file diff --git a/group___s_a_i___block___active___frame_length.png b/group___s_a_i___block___active___frame_length.png new file mode 100644 index 0000000..fcf6a15 Binary files /dev/null and b/group___s_a_i___block___active___frame_length.png differ diff --git a/group___s_a_i___block___clock___strobing.html b/group___s_a_i___block___clock___strobing.html new file mode 100644 index 0000000..274fe71 --- /dev/null +++ b/group___s_a_i___block___clock___strobing.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_Clock_Strobing + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Clock_Strobing
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Clock_Strobing:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_ClockStrobing_FallingEdge   ((uint32_t)0x00000000)
 
+#define SAI_ClockStrobing_RisingEdge   ((uint32_t)SAI_xCR1_CKSTR)
 
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_CLOCK_STROBING( CLOCK)
+
+Value:
(((CLOCK) == SAI_ClockStrobing_FallingEdge) || \
+
((CLOCK) == SAI_ClockStrobing_RisingEdge))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___clock___strobing.map b/group___s_a_i___block___clock___strobing.map new file mode 100644 index 0000000..8ae2ba4 --- /dev/null +++ b/group___s_a_i___block___clock___strobing.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___clock___strobing.md5 b/group___s_a_i___block___clock___strobing.md5 new file mode 100644 index 0000000..cf6d7b4 --- /dev/null +++ b/group___s_a_i___block___clock___strobing.md5 @@ -0,0 +1 @@ +e3a9feeee650ebaf61d63f4a92183431 \ No newline at end of file diff --git a/group___s_a_i___block___clock___strobing.png b/group___s_a_i___block___clock___strobing.png new file mode 100644 index 0000000..7c683e7 Binary files /dev/null and b/group___s_a_i___block___clock___strobing.png differ diff --git a/group___s_a_i___block___companding___mode.html b/group___s_a_i___block___companding___mode.html new file mode 100644 index 0000000..7595849 --- /dev/null +++ b/group___s_a_i___block___companding___mode.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: SAI_Block_Companding_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Companding_Mode
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Companding_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define SAI_NoCompanding   ((uint32_t)0x00000000)
 
+#define SAI_ULaw_1CPL_Companding   ((uint32_t)0x00008000)
 
+#define SAI_ALaw_1CPL_Companding   ((uint32_t)0x0000C000)
 
+#define SAI_ULaw_2CPL_Companding   ((uint32_t)0x0000A000)
 
+#define SAI_ALaw_2CPL_Companding   ((uint32_t)0x0000E000)
 
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_COMPANDING_MODE( MODE)
+
+Value:
(((MODE) == SAI_NoCompanding) || \
+
((MODE) == SAI_ULaw_1CPL_Companding) || \
+
((MODE) == SAI_ALaw_1CPL_Companding) || \
+
((MODE) == SAI_ULaw_2CPL_Companding) || \
+
((MODE) == SAI_ALaw_2CPL_Companding))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___companding___mode.map b/group___s_a_i___block___companding___mode.map new file mode 100644 index 0000000..6048ef1 --- /dev/null +++ b/group___s_a_i___block___companding___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___companding___mode.md5 b/group___s_a_i___block___companding___mode.md5 new file mode 100644 index 0000000..4c18840 --- /dev/null +++ b/group___s_a_i___block___companding___mode.md5 @@ -0,0 +1 @@ +07bc29ab6c86f0d2ee435f4d8ea92f7c \ No newline at end of file diff --git a/group___s_a_i___block___companding___mode.png b/group___s_a_i___block___companding___mode.png new file mode 100644 index 0000000..9f79316 Binary files /dev/null and b/group___s_a_i___block___companding___mode.png differ diff --git a/group___s_a_i___block___data___size.html b/group___s_a_i___block___data___size.html new file mode 100644 index 0000000..8449e1e --- /dev/null +++ b/group___s_a_i___block___data___size.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: SAI_Block_Data_Size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Data_Size
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Data_Size:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define SAI_DataSize_8b   ((uint32_t)0x00000040)
 
+#define SAI_DataSize_10b   ((uint32_t)0x00000060)
 
+#define SAI_DataSize_16b   ((uint32_t)0x00000080)
 
+#define SAI_DataSize_20b   ((uint32_t)0x000000A0)
 
+#define SAI_DataSize_24b   ((uint32_t)0x000000C0)
 
+#define SAI_DataSize_32b   ((uint32_t)0x000000E0)
 
#define IS_SAI_BLOCK_DATASIZE(DATASIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_DATASIZE( DATASIZE)
+
+Value:
(((DATASIZE) == SAI_DataSize_8b) || \
+
((DATASIZE) == SAI_DataSize_10b) || \
+
((DATASIZE) == SAI_DataSize_16b) || \
+
((DATASIZE) == SAI_DataSize_20b) || \
+
((DATASIZE) == SAI_DataSize_24b) || \
+
((DATASIZE) == SAI_DataSize_32b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___data___size.map b/group___s_a_i___block___data___size.map new file mode 100644 index 0000000..59fd873 --- /dev/null +++ b/group___s_a_i___block___data___size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___data___size.md5 b/group___s_a_i___block___data___size.md5 new file mode 100644 index 0000000..1dcca2f --- /dev/null +++ b/group___s_a_i___block___data___size.md5 @@ -0,0 +1 @@ +13bbb2a1ac55d310fd656de4c99605d1 \ No newline at end of file diff --git a/group___s_a_i___block___data___size.png b/group___s_a_i___block___data___size.png new file mode 100644 index 0000000..5659633 Binary files /dev/null and b/group___s_a_i___block___data___size.png differ diff --git a/group___s_a_i___block___f_s___definition.html b/group___s_a_i___block___f_s___definition.html new file mode 100644 index 0000000..7a7a608 --- /dev/null +++ b/group___s_a_i___block___f_s___definition.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_FS_Definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_FS_Definition
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_FS_Definition:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_FS_StartFrame   ((uint32_t)0x00000000)
 
+#define I2S_FS_ChannelIdentification   ((uint32_t)SAI_xFRCR_FSDEF)
 
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FS_DEFINITION( DEFINITION)
+
+Value:
(((DEFINITION) == SAI_FS_StartFrame) || \
+
((DEFINITION) == I2S_FS_ChannelIdentification))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___f_s___definition.map b/group___s_a_i___block___f_s___definition.map new file mode 100644 index 0000000..fb5cac5 --- /dev/null +++ b/group___s_a_i___block___f_s___definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___f_s___definition.md5 b/group___s_a_i___block___f_s___definition.md5 new file mode 100644 index 0000000..ba4f9cd --- /dev/null +++ b/group___s_a_i___block___f_s___definition.md5 @@ -0,0 +1 @@ +19e6bc614736b3696a97efbb1929be4e \ No newline at end of file diff --git a/group___s_a_i___block___f_s___definition.png b/group___s_a_i___block___f_s___definition.png new file mode 100644 index 0000000..c985f89 Binary files /dev/null and b/group___s_a_i___block___f_s___definition.png differ diff --git a/group___s_a_i___block___f_s___offset.html b/group___s_a_i___block___f_s___offset.html new file mode 100644 index 0000000..6682d76 --- /dev/null +++ b/group___s_a_i___block___f_s___offset.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_FS_Offset + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_FS_Offset
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_FS_Offset:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_FS_FirstBit   ((uint32_t)0x00000000)
 
+#define SAI_FS_BeforeFirstBit   ((uint32_t)SAI_xFRCR_FSOFF)
 
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FS_OFFSET( OFFSET)
+
+Value:
(((OFFSET) == SAI_FS_FirstBit) || \
+
((OFFSET) == SAI_FS_BeforeFirstBit))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___f_s___offset.map b/group___s_a_i___block___f_s___offset.map new file mode 100644 index 0000000..b39b28b --- /dev/null +++ b/group___s_a_i___block___f_s___offset.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___f_s___offset.md5 b/group___s_a_i___block___f_s___offset.md5 new file mode 100644 index 0000000..5714694 --- /dev/null +++ b/group___s_a_i___block___f_s___offset.md5 @@ -0,0 +1 @@ +6f3baf950dce5348bb806ee95b6c3d39 \ No newline at end of file diff --git a/group___s_a_i___block___f_s___offset.png b/group___s_a_i___block___f_s___offset.png new file mode 100644 index 0000000..8e20dab Binary files /dev/null and b/group___s_a_i___block___f_s___offset.png differ diff --git a/group___s_a_i___block___f_s___polarity.html b/group___s_a_i___block___f_s___polarity.html new file mode 100644 index 0000000..c2bc72c --- /dev/null +++ b/group___s_a_i___block___f_s___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_FS_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_FS_Polarity
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_FS_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_FS_ActiveLow   ((uint32_t)0x00000000)
 
+#define SAI_FS_ActiveHigh   ((uint32_t)SAI_xFRCR_FSPO)
 
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FS_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == SAI_FS_ActiveLow) || \
+
((POLARITY) == SAI_FS_ActiveHigh))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___f_s___polarity.map b/group___s_a_i___block___f_s___polarity.map new file mode 100644 index 0000000..f228fdc --- /dev/null +++ b/group___s_a_i___block___f_s___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___f_s___polarity.md5 b/group___s_a_i___block___f_s___polarity.md5 new file mode 100644 index 0000000..8b9a5fb --- /dev/null +++ b/group___s_a_i___block___f_s___polarity.md5 @@ -0,0 +1 @@ +9d4138fcf892f39f9d5a1c0f9f9df931 \ No newline at end of file diff --git a/group___s_a_i___block___f_s___polarity.png b/group___s_a_i___block___f_s___polarity.png new file mode 100644 index 0000000..8db42d4 Binary files /dev/null and b/group___s_a_i___block___f_s___polarity.png differ diff --git a/group___s_a_i___block___fifo___status___level.html b/group___s_a_i___block___fifo___status___level.html new file mode 100644 index 0000000..60c5b45 --- /dev/null +++ b/group___s_a_i___block___fifo___status___level.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: SAI_Block_Fifo_Status_Level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Fifo_Status_Level
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Fifo_Status_Level:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define SAI_FIFOStatus_Empty   ((uint32_t)0x00000000)
 
+#define SAI_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00010000)
 
+#define SAI_FIFOStatus_1QuarterFull   ((uint32_t)0x00020000)
 
+#define SAI_FIFOStatus_HalfFull   ((uint32_t)0x00030000)
 
+#define SAI_FIFOStatus_3QuartersFull   ((uint32_t)0x00040000)
 
+#define SAI_FIFOStatus_Full   ((uint32_t)0x00050000)
 
#define IS_SAI_BLOCK_FIFO_STATUS(STATUS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FIFO_STATUS( STATUS)
+
+Value:
(((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
+
((STATUS) == SAI_FIFOStatus_HalfFull) || \
+
((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
+
((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
+
((STATUS) == SAI_FIFOStatus_Full) || \
+
((STATUS) == SAI_FIFOStatus_Empty))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___fifo___status___level.map b/group___s_a_i___block___fifo___status___level.map new file mode 100644 index 0000000..bf3df44 --- /dev/null +++ b/group___s_a_i___block___fifo___status___level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___fifo___status___level.md5 b/group___s_a_i___block___fifo___status___level.md5 new file mode 100644 index 0000000..2fa7f08 --- /dev/null +++ b/group___s_a_i___block___fifo___status___level.md5 @@ -0,0 +1 @@ +45c17c21ea435bc368523cc598525dbf \ No newline at end of file diff --git a/group___s_a_i___block___fifo___status___level.png b/group___s_a_i___block___fifo___status___level.png new file mode 100644 index 0000000..8f5dad5 Binary files /dev/null and b/group___s_a_i___block___fifo___status___level.png differ diff --git a/group___s_a_i___block___fifo___threshold.html b/group___s_a_i___block___fifo___threshold.html new file mode 100644 index 0000000..8acba4e --- /dev/null +++ b/group___s_a_i___block___fifo___threshold.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: SAI_Block_Fifo_Threshold + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Fifo_Threshold
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Fifo_Threshold:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define SAI_Threshold_FIFOEmpty   ((uint32_t)0x00000000)
 
+#define SAI_FIFOThreshold_1QuarterFull   ((uint32_t)0x00000001)
 
+#define SAI_FIFOThreshold_HalfFull   ((uint32_t)0x00000002)
 
+#define SAI_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000003)
 
+#define SAI_FIFOThreshold_Full   ((uint32_t)0x00000004)
 
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FIFO_THRESHOLD( THRESHOLD)
+
+Value:
(((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \
+
((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \
+
((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \
+
((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \
+
((THRESHOLD) == SAI_FIFOThreshold_Full))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___fifo___threshold.map b/group___s_a_i___block___fifo___threshold.map new file mode 100644 index 0000000..e86655f --- /dev/null +++ b/group___s_a_i___block___fifo___threshold.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___fifo___threshold.md5 b/group___s_a_i___block___fifo___threshold.md5 new file mode 100644 index 0000000..3933fc3 --- /dev/null +++ b/group___s_a_i___block___fifo___threshold.md5 @@ -0,0 +1 @@ +f5d0b743fc7fd3c2f25413fb75b27e8a \ No newline at end of file diff --git a/group___s_a_i___block___fifo___threshold.png b/group___s_a_i___block___fifo___threshold.png new file mode 100644 index 0000000..668995e Binary files /dev/null and b/group___s_a_i___block___fifo___threshold.png differ diff --git a/group___s_a_i___block___flags___definition.html b/group___s_a_i___block___flags___definition.html new file mode 100644 index 0000000..ab961ea --- /dev/null +++ b/group___s_a_i___block___flags___definition.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: SAI_Block_Flags_Definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Flags_Definition
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Flags_Definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SAI_FLAG_OVRUDR   ((uint32_t)SAI_xSR_OVRUDR)
 
+#define SAI_FLAG_MUTEDET   ((uint32_t)SAI_xSR_MUTEDET)
 
+#define SAI_FLAG_WCKCFG   ((uint32_t)SAI_xSR_WCKCFG)
 
+#define SAI_FLAG_FREQ   ((uint32_t)SAI_xSR_FREQ)
 
+#define SAI_FLAG_CNRDY   ((uint32_t)SAI_xSR_CNRDY)
 
+#define SAI_FLAG_AFSDET   ((uint32_t)SAI_xSR_AFSDET)
 
+#define SAI_FLAG_LFSDET   ((uint32_t)SAI_xSR_LFSDET)
 
#define IS_SAI_BLOCK_GET_FLAG(FLAG)
 
#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_CLEAR_FLAG( FLAG)
+
+Value:
(((FLAG) == SAI_FLAG_OVRUDR) || \
+
((FLAG) == SAI_FLAG_MUTEDET) || \
+
((FLAG) == SAI_FLAG_WCKCFG) || \
+
((FLAG) == SAI_FLAG_FREQ) || \
+
((FLAG) == SAI_FLAG_CNRDY) || \
+
((FLAG) == SAI_FLAG_AFSDET) || \
+
((FLAG) == SAI_FLAG_LFSDET))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == SAI_FLAG_OVRUDR) || \
+
((FLAG) == SAI_FLAG_MUTEDET) || \
+
((FLAG) == SAI_FLAG_WCKCFG) || \
+
((FLAG) == SAI_FLAG_FREQ) || \
+
((FLAG) == SAI_FLAG_CNRDY) || \
+
((FLAG) == SAI_FLAG_AFSDET) || \
+
((FLAG) == SAI_FLAG_LFSDET))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___flags___definition.map b/group___s_a_i___block___flags___definition.map new file mode 100644 index 0000000..48e3726 --- /dev/null +++ b/group___s_a_i___block___flags___definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___flags___definition.md5 b/group___s_a_i___block___flags___definition.md5 new file mode 100644 index 0000000..99b390b --- /dev/null +++ b/group___s_a_i___block___flags___definition.md5 @@ -0,0 +1 @@ +3e6f7b08b78f771e46b520310221f37e \ No newline at end of file diff --git a/group___s_a_i___block___flags___definition.png b/group___s_a_i___block___flags___definition.png new file mode 100644 index 0000000..50fe9f4 Binary files /dev/null and b/group___s_a_i___block___flags___definition.png differ diff --git a/group___s_a_i___block___frame___length.html b/group___s_a_i___block___frame___length.html new file mode 100644 index 0000000..28f5880 --- /dev/null +++ b/group___s_a_i___block___frame___length.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Frame_Length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Frame_Length
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Frame_Length:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH)   ((8 <= (LENGTH)) && ((LENGTH) <= 256))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___frame___length.map b/group___s_a_i___block___frame___length.map new file mode 100644 index 0000000..f98167e --- /dev/null +++ b/group___s_a_i___block___frame___length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___frame___length.md5 b/group___s_a_i___block___frame___length.md5 new file mode 100644 index 0000000..d6bde4d --- /dev/null +++ b/group___s_a_i___block___frame___length.md5 @@ -0,0 +1 @@ +e7b9a6686bd5eea9da8b8905394451f2 \ No newline at end of file diff --git a/group___s_a_i___block___frame___length.png b/group___s_a_i___block___frame___length.png new file mode 100644 index 0000000..b122438 Binary files /dev/null and b/group___s_a_i___block___frame___length.png differ diff --git a/group___s_a_i___block___interrupts___definition.html b/group___s_a_i___block___interrupts___definition.html new file mode 100644 index 0000000..871bb3a --- /dev/null +++ b/group___s_a_i___block___interrupts___definition.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: SAI_Block_Interrupts_Definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Interrupts_Definition
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Interrupts_Definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define SAI_IT_OVRUDR   ((uint32_t)SAI_xIMR_OVRUDRIE)
 
+#define SAI_IT_MUTEDET   ((uint32_t)SAI_xIMR_MUTEDETIE)
 
+#define SAI_IT_WCKCFG   ((uint32_t)SAI_xIMR_WCKCFGIE)
 
+#define SAI_IT_FREQ   ((uint32_t)SAI_xIMR_FREQIE)
 
+#define SAI_IT_CNRDY   ((uint32_t)SAI_xIMR_CNRDYIE)
 
+#define SAI_IT_AFSDET   ((uint32_t)SAI_xIMR_AFSDETIE)
 
+#define SAI_IT_LFSDET   ((uint32_t)SAI_xIMR_LFSDETIE)
 
#define IS_SAI_BLOCK_CONFIG_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_CONFIG_IT( IT)
+
+Value:
(((IT) == SAI_IT_OVRUDR) || \
+
((IT) == SAI_IT_MUTEDET) || \
+
((IT) == SAI_IT_WCKCFG) || \
+
((IT) == SAI_IT_FREQ) || \
+
((IT) == SAI_IT_CNRDY) || \
+
((IT) == SAI_IT_AFSDET) || \
+
((IT) == SAI_IT_LFSDET))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___interrupts___definition.map b/group___s_a_i___block___interrupts___definition.map new file mode 100644 index 0000000..4ee044b --- /dev/null +++ b/group___s_a_i___block___interrupts___definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___interrupts___definition.md5 b/group___s_a_i___block___interrupts___definition.md5 new file mode 100644 index 0000000..81dc3d5 --- /dev/null +++ b/group___s_a_i___block___interrupts___definition.md5 @@ -0,0 +1 @@ +9840a3fa4ce6127e7a647d4095d8ed94 \ No newline at end of file diff --git a/group___s_a_i___block___interrupts___definition.png b/group___s_a_i___block___interrupts___definition.png new file mode 100644 index 0000000..cbff6fa Binary files /dev/null and b/group___s_a_i___block___interrupts___definition.png differ diff --git a/group___s_a_i___block___m_s_b___l_s_b__transmission.html b/group___s_a_i___block___m_s_b___l_s_b__transmission.html new file mode 100644 index 0000000..1448915 --- /dev/null +++ b/group___s_a_i___block___m_s_b___l_s_b__transmission.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_MSB_LSB_transmission + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
SAI_Block_MSB_LSB_transmission
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_MSB_LSB_transmission:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_FirstBit_MSB   ((uint32_t)0x00000000)
 
+#define SAI_FirstBit_LSB   ((uint32_t)SAI_xCR1_LSBFIRST)
 
#define IS_SAI_BLOCK_FIRST_BIT(BIT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_FIRST_BIT( BIT)
+
+Value:
(((BIT) == SAI_FirstBit_MSB) || \
+
((BIT) == SAI_FirstBit_LSB))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___m_s_b___l_s_b__transmission.map b/group___s_a_i___block___m_s_b___l_s_b__transmission.map new file mode 100644 index 0000000..a14a10d --- /dev/null +++ b/group___s_a_i___block___m_s_b___l_s_b__transmission.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___m_s_b___l_s_b__transmission.md5 b/group___s_a_i___block___m_s_b___l_s_b__transmission.md5 new file mode 100644 index 0000000..aa0a4cd --- /dev/null +++ b/group___s_a_i___block___m_s_b___l_s_b__transmission.md5 @@ -0,0 +1 @@ +bab30b9c3c4f1159be5d0b988ea1753b \ No newline at end of file diff --git a/group___s_a_i___block___m_s_b___l_s_b__transmission.png b/group___s_a_i___block___m_s_b___l_s_b__transmission.png new file mode 100644 index 0000000..84889f4 Binary files /dev/null and b/group___s_a_i___block___m_s_b___l_s_b__transmission.png differ diff --git a/group___s_a_i___block___master___divider.html b/group___s_a_i___block___master___divider.html new file mode 100644 index 0000000..0eac760 --- /dev/null +++ b/group___s_a_i___block___master___divider.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Master_Divider + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Master_Divider
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Master_Divider:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER)   ((DIVIDER) <= 15)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___master___divider.map b/group___s_a_i___block___master___divider.map new file mode 100644 index 0000000..8fffe91 --- /dev/null +++ b/group___s_a_i___block___master___divider.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___master___divider.md5 b/group___s_a_i___block___master___divider.md5 new file mode 100644 index 0000000..ce27c84 --- /dev/null +++ b/group___s_a_i___block___master___divider.md5 @@ -0,0 +1 @@ +5d2da261d9a629bdd981f577a75dbb4c \ No newline at end of file diff --git a/group___s_a_i___block___master___divider.png b/group___s_a_i___block___master___divider.png new file mode 100644 index 0000000..825d102 Binary files /dev/null and b/group___s_a_i___block___master___divider.png differ diff --git a/group___s_a_i___block___mode.html b/group___s_a_i___block___mode.html new file mode 100644 index 0000000..23ee3c2 --- /dev/null +++ b/group___s_a_i___block___mode.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: SAI_Block_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Mode
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define SAI_Mode_MasterTx   ((uint32_t)0x00000000)
 
+#define SAI_Mode_MasterRx   ((uint32_t)0x00000001)
 
+#define SAI_Mode_SlaveTx   ((uint32_t)0x00000002)
 
+#define SAI_Mode_SlaveRx   ((uint32_t)0x00000003)
 
#define IS_SAI_BLOCK_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_MODE( MODE)
+
+Value:
(((MODE) == SAI_Mode_MasterTx) || \
+
((MODE) == SAI_Mode_MasterRx) || \
+
((MODE) == SAI_Mode_SlaveTx) || \
+
((MODE) == SAI_Mode_SlaveRx))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___mode.map b/group___s_a_i___block___mode.map new file mode 100644 index 0000000..788daa3 --- /dev/null +++ b/group___s_a_i___block___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___mode.md5 b/group___s_a_i___block___mode.md5 new file mode 100644 index 0000000..db2bad6 --- /dev/null +++ b/group___s_a_i___block___mode.md5 @@ -0,0 +1 @@ +56817d9cd28d33440a2ba4954d8b643c \ No newline at end of file diff --git a/group___s_a_i___block___mode.png b/group___s_a_i___block___mode.png new file mode 100644 index 0000000..702616e Binary files /dev/null and b/group___s_a_i___block___mode.png differ diff --git a/group___s_a_i___block___mute___frame___counter.html b/group___s_a_i___block___mute___frame___counter.html new file mode 100644 index 0000000..16fe490 --- /dev/null +++ b/group___s_a_i___block___mute___frame___counter.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Mute_Frame_Counter + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Mute_Frame_Counter
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Mute_Frame_Counter:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER)   ((COUNTER) <= 63)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___mute___frame___counter.map b/group___s_a_i___block___mute___frame___counter.map new file mode 100644 index 0000000..937b0cf --- /dev/null +++ b/group___s_a_i___block___mute___frame___counter.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___mute___frame___counter.md5 b/group___s_a_i___block___mute___frame___counter.md5 new file mode 100644 index 0000000..2681c38 --- /dev/null +++ b/group___s_a_i___block___mute___frame___counter.md5 @@ -0,0 +1 @@ +9016467e19b55d9e20a686040f90c312 \ No newline at end of file diff --git a/group___s_a_i___block___mute___frame___counter.png b/group___s_a_i___block___mute___frame___counter.png new file mode 100644 index 0000000..89033e8 Binary files /dev/null and b/group___s_a_i___block___mute___frame___counter.png differ diff --git a/group___s_a_i___block___mute___value.html b/group___s_a_i___block___mute___value.html new file mode 100644 index 0000000..bb8ad5b --- /dev/null +++ b/group___s_a_i___block___mute___value.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_Mute_Value + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Mute_Value
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Mute_Value:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_ZeroValue   ((uint32_t)0x00000000)
 
+#define SAI_LastSentValue   ((uint32_t)SAI_xCR2_MUTEVAL)
 
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_MUTE_VALUE( VALUE)
+
+Value:
(((VALUE) == SAI_ZeroValue) || \
+
((VALUE) == SAI_LastSentValue))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___mute___value.map b/group___s_a_i___block___mute___value.map new file mode 100644 index 0000000..59dfd17 --- /dev/null +++ b/group___s_a_i___block___mute___value.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___mute___value.md5 b/group___s_a_i___block___mute___value.md5 new file mode 100644 index 0000000..d40290f --- /dev/null +++ b/group___s_a_i___block___mute___value.md5 @@ -0,0 +1 @@ +61fb0229c99b58c4abfd4bf77702a950 \ No newline at end of file diff --git a/group___s_a_i___block___mute___value.png b/group___s_a_i___block___mute___value.png new file mode 100644 index 0000000..212dcf7 Binary files /dev/null and b/group___s_a_i___block___mute___value.png differ diff --git a/group___s_a_i___block___no_divider.html b/group___s_a_i___block___no_divider.html new file mode 100644 index 0000000..4fad316 --- /dev/null +++ b/group___s_a_i___block___no_divider.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_NoDivider + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_NoDivider
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_NoDivider:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_MasterDivider_Enabled   ((uint32_t)0x00000000)
 
+#define SAI_MasterDivider_Disabled   ((uint32_t)SAI_xCR1_NODIV)
 
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_NODIVIDER( NODIVIDER)
+
+Value:
(((NODIVIDER) == SAI_MasterDivider_Enabled) || \
+
((NODIVIDER) == SAI_MasterDivider_Disabled))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___no_divider.map b/group___s_a_i___block___no_divider.map new file mode 100644 index 0000000..aba6e44 --- /dev/null +++ b/group___s_a_i___block___no_divider.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___no_divider.md5 b/group___s_a_i___block___no_divider.md5 new file mode 100644 index 0000000..2ae123a --- /dev/null +++ b/group___s_a_i___block___no_divider.md5 @@ -0,0 +1 @@ +a60b0f0394476a63bc1a1bd101fb453c \ No newline at end of file diff --git a/group___s_a_i___block___no_divider.png b/group___s_a_i___block___no_divider.png new file mode 100644 index 0000000..95fd6d5 Binary files /dev/null and b/group___s_a_i___block___no_divider.png differ diff --git a/group___s_a_i___block___output___drive.html b/group___s_a_i___block___output___drive.html new file mode 100644 index 0000000..3aa5f75 --- /dev/null +++ b/group___s_a_i___block___output___drive.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_Output_Drive + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Output_Drive
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Output_Drive:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_OutputDrive_Disabled   ((uint32_t)0x00000000)
 
+#define SAI_OutputDrive_Enabled   ((uint32_t)SAI_xCR1_OUTDRIV)
 
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_OUTPUT_DRIVE( DRIVE)
+
+Value:
(((DRIVE) == SAI_OutputDrive_Disabled) || \
+
((DRIVE) == SAI_OutputDrive_Enabled))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___output___drive.map b/group___s_a_i___block___output___drive.map new file mode 100644 index 0000000..7ce843e --- /dev/null +++ b/group___s_a_i___block___output___drive.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___output___drive.md5 b/group___s_a_i___block___output___drive.md5 new file mode 100644 index 0000000..3af9665 --- /dev/null +++ b/group___s_a_i___block___output___drive.md5 @@ -0,0 +1 @@ +4a7d4f26655beb2ddec77515b640192e \ No newline at end of file diff --git a/group___s_a_i___block___output___drive.png b/group___s_a_i___block___output___drive.png new file mode 100644 index 0000000..2e57690 Binary files /dev/null and b/group___s_a_i___block___output___drive.png differ diff --git a/group___s_a_i___block___protocol.html b/group___s_a_i___block___protocol.html new file mode 100644 index 0000000..d26d580 --- /dev/null +++ b/group___s_a_i___block___protocol.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: SAI_Block_Protocol + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Protocol
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Protocol:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define SAI_Free_Protocol   ((uint32_t)0x00000000)
 
+#define SAI_SPDIF_Protocol   ((uint32_t)SAI_xCR1_PRTCFG_0)
 
+#define SAI_AC97_Protocol   ((uint32_t)SAI_xCR1_PRTCFG_1)
 
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_PROTOCOL( PROTOCOL)
+
+Value:
(((PROTOCOL) == SAI_Free_Protocol) || \
+
((PROTOCOL) == SAI_SPDIF_Protocol) || \
+
((PROTOCOL) == SAI_AC97_Protocol))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___protocol.map b/group___s_a_i___block___protocol.map new file mode 100644 index 0000000..66ae8ed --- /dev/null +++ b/group___s_a_i___block___protocol.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___protocol.md5 b/group___s_a_i___block___protocol.md5 new file mode 100644 index 0000000..060c1ff --- /dev/null +++ b/group___s_a_i___block___protocol.md5 @@ -0,0 +1 @@ +53f31916fe21d08b5f7e5c8ec6ae4866 \ No newline at end of file diff --git a/group___s_a_i___block___protocol.png b/group___s_a_i___block___protocol.png new file mode 100644 index 0000000..853d411 Binary files /dev/null and b/group___s_a_i___block___protocol.png differ diff --git a/group___s_a_i___block___slot___active.html b/group___s_a_i___block___slot___active.html new file mode 100644 index 0000000..9222ccf --- /dev/null +++ b/group___s_a_i___block___slot___active.html @@ -0,0 +1,163 @@ + + + + + + +discoverpixy: SAI_Block_Slot_Active + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Slot_Active
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Slot_Active:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SAI_Slot_NotActive   ((uint32_t)0x00000000)
 
+#define SAI_SlotActive_0   ((uint32_t)0x00010000)
 
+#define SAI_SlotActive_1   ((uint32_t)0x00020000)
 
+#define SAI_SlotActive_2   ((uint32_t)0x00040000)
 
+#define SAI_SlotActive_3   ((uint32_t)0x00080000)
 
+#define SAI_SlotActive_4   ((uint32_t)0x00100000)
 
+#define SAI_SlotActive_5   ((uint32_t)0x00200000)
 
+#define SAI_SlotActive_6   ((uint32_t)0x00400000)
 
+#define SAI_SlotActive_7   ((uint32_t)0x00800000)
 
+#define SAI_SlotActive_8   ((uint32_t)0x01000000)
 
+#define SAI_SlotActive_9   ((uint32_t)0x02000000)
 
+#define SAI_SlotActive_10   ((uint32_t)0x04000000)
 
+#define SAI_SlotActive_11   ((uint32_t)0x08000000)
 
+#define SAI_SlotActive_12   ((uint32_t)0x10000000)
 
+#define SAI_SlotActive_13   ((uint32_t)0x20000000)
 
+#define SAI_SlotActive_14   ((uint32_t)0x40000000)
 
+#define SAI_SlotActive_15   ((uint32_t)0x80000000)
 
+#define SAI_SlotActive_ALL   ((uint32_t)0xFFFF0000)
 
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)   ((ACTIVE) != 0)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___slot___active.map b/group___s_a_i___block___slot___active.map new file mode 100644 index 0000000..a951a4c --- /dev/null +++ b/group___s_a_i___block___slot___active.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___slot___active.md5 b/group___s_a_i___block___slot___active.md5 new file mode 100644 index 0000000..255dc68 --- /dev/null +++ b/group___s_a_i___block___slot___active.md5 @@ -0,0 +1 @@ +57d5b0284ec8e29bfcabd6fef90fea15 \ No newline at end of file diff --git a/group___s_a_i___block___slot___active.png b/group___s_a_i___block___slot___active.png new file mode 100644 index 0000000..2e47e90 Binary files /dev/null and b/group___s_a_i___block___slot___active.png differ diff --git a/group___s_a_i___block___slot___first_bit___offset.html b/group___s_a_i___block___slot___first_bit___offset.html new file mode 100644 index 0000000..144080e --- /dev/null +++ b/group___s_a_i___block___slot___first_bit___offset.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Slot_FirstBit_Offset + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Slot_FirstBit_Offset
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Slot_FirstBit_Offset:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET)   ((OFFSET) <= 24)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___slot___first_bit___offset.map b/group___s_a_i___block___slot___first_bit___offset.map new file mode 100644 index 0000000..136b544 --- /dev/null +++ b/group___s_a_i___block___slot___first_bit___offset.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___slot___first_bit___offset.md5 b/group___s_a_i___block___slot___first_bit___offset.md5 new file mode 100644 index 0000000..620e97c --- /dev/null +++ b/group___s_a_i___block___slot___first_bit___offset.md5 @@ -0,0 +1 @@ +90e2e3ca1c4f17433283d192be8c333f \ No newline at end of file diff --git a/group___s_a_i___block___slot___first_bit___offset.png b/group___s_a_i___block___slot___first_bit___offset.png new file mode 100644 index 0000000..1185276 Binary files /dev/null and b/group___s_a_i___block___slot___first_bit___offset.png differ diff --git a/group___s_a_i___block___slot___number.html b/group___s_a_i___block___slot___number.html new file mode 100644 index 0000000..00d72b8 --- /dev/null +++ b/group___s_a_i___block___slot___number.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SAI_Block_Slot_Number + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Slot_Number
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Slot_Number:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER)   ((1 <= (NUMBER)) && ((NUMBER) <= 16))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___slot___number.map b/group___s_a_i___block___slot___number.map new file mode 100644 index 0000000..99297ef --- /dev/null +++ b/group___s_a_i___block___slot___number.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___slot___number.md5 b/group___s_a_i___block___slot___number.md5 new file mode 100644 index 0000000..83b111f --- /dev/null +++ b/group___s_a_i___block___slot___number.md5 @@ -0,0 +1 @@ +2fdf5c80591d17bfe5a6ef79a4cdfb24 \ No newline at end of file diff --git a/group___s_a_i___block___slot___number.png b/group___s_a_i___block___slot___number.png new file mode 100644 index 0000000..170b7a2 Binary files /dev/null and b/group___s_a_i___block___slot___number.png differ diff --git a/group___s_a_i___block___slot___size.html b/group___s_a_i___block___slot___size.html new file mode 100644 index 0000000..aabc0a5 --- /dev/null +++ b/group___s_a_i___block___slot___size.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: SAI_Block_Slot_Size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Slot_Size
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Slot_Size:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define SAI_SlotSize_DataSize   ((uint32_t)0x00000000)
 
+#define SAI_SlotSize_16b   ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
 
+#define SAI_SlotSize_32b   ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
 
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_SLOT_SIZE( SIZE)
+
+Value:
(((SIZE) == SAI_SlotSize_DataSize) || \
+
((SIZE) == SAI_SlotSize_16b) || \
+
((SIZE) == SAI_SlotSize_32b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___slot___size.map b/group___s_a_i___block___slot___size.map new file mode 100644 index 0000000..286eaba --- /dev/null +++ b/group___s_a_i___block___slot___size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___slot___size.md5 b/group___s_a_i___block___slot___size.md5 new file mode 100644 index 0000000..ab8ac88 --- /dev/null +++ b/group___s_a_i___block___slot___size.md5 @@ -0,0 +1 @@ +3214d62821e357aba53f2527d11c21e9 \ No newline at end of file diff --git a/group___s_a_i___block___slot___size.png b/group___s_a_i___block___slot___size.png new file mode 100644 index 0000000..74b48cf Binary files /dev/null and b/group___s_a_i___block___slot___size.png differ diff --git a/group___s_a_i___block___synchronization.html b/group___s_a_i___block___synchronization.html new file mode 100644 index 0000000..6c4de43 --- /dev/null +++ b/group___s_a_i___block___synchronization.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Block_Synchronization + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Block_Synchronization
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Block_Synchronization:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_Asynchronous   ((uint32_t)0x00000000)
 
+#define SAI_Synchronous   ((uint32_t)SAI_xCR1_SYNCEN_0)
 
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_SYNCHRO( SYNCHRO)
+
+Value:
(((SYNCHRO) == SAI_Synchronous) || \
+
((SYNCHRO) == SAI_Asynchronous))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___block___synchronization.map b/group___s_a_i___block___synchronization.map new file mode 100644 index 0000000..79d764b --- /dev/null +++ b/group___s_a_i___block___synchronization.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___block___synchronization.md5 b/group___s_a_i___block___synchronization.md5 new file mode 100644 index 0000000..b907c42 --- /dev/null +++ b/group___s_a_i___block___synchronization.md5 @@ -0,0 +1 @@ +8068f672512399db03593626c2a5d1c6 \ No newline at end of file diff --git a/group___s_a_i___block___synchronization.png b/group___s_a_i___block___synchronization.png new file mode 100644 index 0000000..1b380b5 Binary files /dev/null and b/group___s_a_i___block___synchronization.png differ diff --git a/group___s_a_i___exported___constants.html b/group___s_a_i___exported___constants.html new file mode 100644 index 0000000..fdfaa27 --- /dev/null +++ b/group___s_a_i___exported___constants.html @@ -0,0 +1,188 @@ + + + + + + +discoverpixy: SAI_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
SAI_Exported_Constants
STM32F4xx_StdPeriph_Driver » SAI
+
+
+
+Collaboration diagram for SAI_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 SAI_Block_Mode
 
 SAI_Block_Protocol
 
 SAI_Block_Data_Size
 
 SAI_Block_MSB_LSB_transmission
 
 SAI_Block_Clock_Strobing
 
 SAI_Block_Synchronization
 
 SAI_Block_Output_Drive
 
 SAI_Block_NoDivider
 
 SAI_Block_Master_Divider
 
 SAI_Block_Frame_Length
 
 SAI_Block_Active_FrameLength
 
 SAI_Block_FS_Definition
 
 SAI_Block_FS_Polarity
 
 SAI_Block_FS_Offset
 
 SAI_Block_Slot_FirstBit_Offset
 
 SAI_Block_Slot_Size
 
 SAI_Block_Slot_Number
 
 SAI_Block_Slot_Active
 
 SAI_Mono_Streo_Mode
 
 SAI_TRIState_Management
 
 SAI_Block_Fifo_Threshold
 
 SAI_Block_Companding_Mode
 
 SAI_Block_Mute_Value
 
 SAI_Block_Mute_Frame_Counter
 
 SAI_Block_Interrupts_Definition
 
 SAI_Block_Flags_Definition
 
 SAI_Block_Fifo_Status_Level
 
+ + + + + +

+Macros

+#define IS_SAI_PERIPH(PERIPH)   ((PERIPH) == SAI1)
 
#define IS_SAI_BLOCK_PERIPH(PERIPH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == SAI1_Block_A) || \
+
((PERIPH) == SAI1_Block_B))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___exported___constants.map b/group___s_a_i___exported___constants.map new file mode 100644 index 0000000..bbcf806 --- /dev/null +++ b/group___s_a_i___exported___constants.map @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___s_a_i___exported___constants.md5 b/group___s_a_i___exported___constants.md5 new file mode 100644 index 0000000..3e43a2c --- /dev/null +++ b/group___s_a_i___exported___constants.md5 @@ -0,0 +1 @@ +e87d19b9d4380b40939b0a83d8a55353 \ No newline at end of file diff --git a/group___s_a_i___exported___constants.png b/group___s_a_i___exported___constants.png new file mode 100644 index 0000000..628aa2e Binary files /dev/null and b/group___s_a_i___exported___constants.png differ diff --git a/group___s_a_i___group1.html b/group___s_a_i___group1.html new file mode 100644 index 0000000..a56712f --- /dev/null +++ b/group___s_a_i___group1.html @@ -0,0 +1,770 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » SAI » SAI_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SAI_DeInit (SAI_TypeDef *SAIx)
 Deinitialize the SAIx peripheral registers to their default reset values. More...
 
void SAI_Init (SAI_Block_TypeDef *SAI_Block_x, SAI_InitTypeDef *SAI_InitStruct)
 Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct. More...
 
void SAI_FrameInit (SAI_Block_TypeDef *SAI_Block_x, SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct. More...
 
void SAI_SlotInit (SAI_Block_TypeDef *SAI_Block_x, SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct. More...
 
void SAI_StructInit (SAI_InitTypeDef *SAI_InitStruct)
 Fills each SAI_InitStruct member with its default value. More...
 
void SAI_FrameStructInit (SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Fills each SAI_FrameInitStruct member with its default value. More...
 
void SAI_SlotStructInit (SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Fills each SAI_SlotInitStruct member with its default value. More...
 
void SAI_Cmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the specified SAI Block peripheral. More...
 
void SAI_MonoModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_Mono_StreoMode)
 Configures the mono mode for the selected SAI block. More...
 
void SAI_TRIStateConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_TRIState)
 Configures the TRIState managment on data line for the selected SAI block. More...
 
void SAI_CompandingModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_CompandingMode)
 Configures the companding mode for the selected SAI block. More...
 
void SAI_MuteModeCmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_MuteValueConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteValue)
 Configure the mute value for the selected SAI block. More...
 
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteCounter)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_FlushFIFO (SAI_Block_TypeDef *SAI_Block_x)
 Reinitialize the FIFO pointer. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+  [..]
+  This section provides a set of functions allowing to initialize the SAI Audio 
+  Block Mode, Audio Protocol, Data size, Synchronization between audio block, 
+  Master clock Divider, Fifo threshold, Frame configuration, slot configuration,
+  Tristate mode, Companding mode and Mute mode.  
+  [..] 
+  The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block
+  configuration procedures for Master mode and Slave mode (details for these procedures 
+  are available in reference manual(RM0090).

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_Cmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SAI Block peripheral.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the SAI_Block_x peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_CompandingModeConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_CompandingMode 
)
+
+ +

Configures the companding mode for the selected SAI block.

+
Note
The data expansion or data compression are determined by the state of SAI block selected (transmitter or receiver).
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_CompandingModespecifies the SAI block companding mode. This parameter can be one of the following values:
    +
  • SAI_NoCompanding : no companding algorithm set
    • +
  • SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation)
    • +
  • SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation)
    • +
  • SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation)
    • +
  • SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_DeInit (SAI_TypeDef * SAIx)
+
+ +

Deinitialize the SAIx peripheral registers to their default reset values.

+
Parameters
+ + +
SAIxTo select the SAIx peripheral, where x can be the different instances
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void SAI_FlushFIFO (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Reinitialize the FIFO pointer.

+
Note
The FIFO pointers can be reinitialized at anytime The data present into the FIFO, if it is not empty, will be lost.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the selected SAI TI communication mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_FrameInit (SAI_Block_TypeDef * SAI_Block_x,
SAI_FrameInitTypeDef * SAI_FrameInitStruct 
)
+
+ +

Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct.

+
Note
this function has no meaning if the AC'97 or SPDIF audio protocol are selected.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FrameInitStructpointer to an SAI_FrameInitTypeDef structure that contains the configuration of audio frame for a specified SAI Block
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_FrameStructInit (SAI_FrameInitTypeDef * SAI_FrameInitStruct)
+
+ +

Fills each SAI_FrameInitStruct member with its default value.

+
Parameters
+ + +
SAI_FrameInitStructpointer to a SAI_FrameInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_Init (SAI_Block_TypeDef * SAI_Block_x,
SAI_InitTypeDef * SAI_InitStruct 
)
+
+ +

Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct.

+
Note
SAI clock is generated from a specific output of the PLLSAI or a specific output of the PLLI2S or from an alternate function bypassing the PLL I2S.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_InitStructpointer to a SAI_InitTypeDef structure that contains the configuration information for the specified SAI Block peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MonoModeConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_Mono_StreoMode 
)
+
+ +

Configures the mono mode for the selected SAI block.

+
Note
This function has a meaning only when the number of slot is equal to 2.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MonoModespecifies the SAI block mono mode. This parameter can be one of the following values:
    +
  • SAI_MonoMode : Set mono audio mode
    • +
  • SAI_StreoMode : Set streo audio mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_MuteCounter 
)
+
+ +

Enables or disables the Mute mode for the selected SAI block.

+
Note
This function has a meaning only when the audio block is Receiver
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MuteCounterspecifies the SAI block mute value. This parameter can be a number between 0 and 63.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteModeCmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the Mute mode for the selected SAI block.

+
Note
This function has a meaning only when the audio block is transmitter
+
+Mute mode is applied for an entire frame for all the valid slot It becomes active at the end of an audio frame when set somewhere in a frame. Mute mode exit occurs at the end of the frame in which the bit MUTE has been set.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the SAIx block. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_MuteValueConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_MuteValue 
)
+
+ +

Configure the mute value for the selected SAI block.

+
Note
This function has a meaning only when the audio block is transmitter
+
+the configuration last value sent during mute mode has only a meaning when the number of slot is lower or equal to 2 and if the MUTE bit is set.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_MuteValuespecifies the SAI block mute value. This parameter can be one of the following values:
    +
  • SAI_ZeroValue : bit value 0 is sent during Mute Mode
    • +
  • SAI_LastSentValue : Last value is sent during Mute Mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_SlotInit (SAI_Block_TypeDef * SAI_Block_x,
SAI_SlotInitTypeDef * SAI_SlotInitStruct 
)
+
+ +

Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct.

+
Note
this function has no meaning if the AC'97 or SPDIF audio protocol are selected.
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_SlotInitStructpointer to an SAI_SlotInitTypeDef structure that contains the configuration of audio slot for a specified SAI Block
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_SlotStructInit (SAI_SlotInitTypeDef * SAI_SlotInitStruct)
+
+ +

Fills each SAI_SlotInitStruct member with its default value.

+
Parameters
+ + +
SAI_SlotInitStructpointer to a SAI_SlotInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SAI_StructInit (SAI_InitTypeDef * SAI_InitStruct)
+
+ +

Fills each SAI_InitStruct member with its default value.

+
Parameters
+ + +
SAI_InitStructpointer to a SAI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_TRIStateConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_TRIState 
)
+
+ +

Configures the TRIState managment on data line for the selected SAI block.

+
Note
This function has a meaning only when the SAI block is configured in transmitter
+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_TRIStatespecifies the SAI block TRIState management. This parameter can be one of the following values:
    +
  • SAI_Output_NotReleased : SD output line is still drived by the SAI.
    • +
  • SAI_Output_Released : SD output line is released (HI-Z)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___group1.map b/group___s_a_i___group1.map new file mode 100644 index 0000000..d910666 --- /dev/null +++ b/group___s_a_i___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___group1.md5 b/group___s_a_i___group1.md5 new file mode 100644 index 0000000..8238657 --- /dev/null +++ b/group___s_a_i___group1.md5 @@ -0,0 +1 @@ +08b6d2c3ecc2562c80ab8d0a42d6e93d \ No newline at end of file diff --git a/group___s_a_i___group1.png b/group___s_a_i___group1.png new file mode 100644 index 0000000..ec12544 Binary files /dev/null and b/group___s_a_i___group1.png differ diff --git a/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map new file mode 100644 index 0000000..0f2ad40 --- /dev/null +++ b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 new file mode 100644 index 0000000..240364a --- /dev/null +++ b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 @@ -0,0 +1 @@ +be41093f65d5057d152724dee17a8939 \ No newline at end of file diff --git a/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png new file mode 100644 index 0000000..12f83a0 Binary files /dev/null and b/group___s_a_i___group1_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png differ diff --git a/group___s_a_i___group2.html b/group___s_a_i___group2.html new file mode 100644 index 0000000..5f6e137 --- /dev/null +++ b/group___s_a_i___group2.html @@ -0,0 +1,201 @@ + + + + + + +discoverpixy: Data transfers functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Data transfers functions
STM32F4xx_StdPeriph_Driver » SAI » SAI_Private_Functions
+
+
+ +

Data transfers functions. +More...

+
+Collaboration diagram for Data transfers functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

uint32_t SAI_ReceiveData (SAI_Block_TypeDef *SAI_Block_x)
 Returns the most recent received data by the SAI block x peripheral. More...
 
void SAI_SendData (SAI_Block_TypeDef *SAI_Block_x, uint32_t Data)
 Transmits a Data through the SAI block x peripheral. More...
 
+

Detailed Description

+

Data transfers functions.

+
 ===============================================================================
+                       ##### Data transfers functions #####
+ ===============================================================================  
+  [..]
+  This section provides a set of functions allowing to manage the SAI data transfers.
+  [..]
+  In reception, data are received and then stored into an internal FIFO while 
+  In transmission, data are first stored into an internal FIFO before being 
+  transmitted.
+  [..]
+  The read access of the SAI_xDR register can be done using the SAI_ReceiveData()
+  function and returns the Rx buffered value. Whereas a write access to the SAI_DR 
+  can be done using SAI_SendData() function and stores the written data into 
+  Tx buffer.

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t SAI_ReceiveData (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the most recent received data by the SAI block x peripheral.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_SendData (SAI_Block_TypeDef * SAI_Block_x,
uint32_t Data 
)
+
+ +

Transmits a Data through the SAI block x peripheral.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
DataData to be transmitted.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___group2.map b/group___s_a_i___group2.map new file mode 100644 index 0000000..f1394d4 --- /dev/null +++ b/group___s_a_i___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___group2.md5 b/group___s_a_i___group2.md5 new file mode 100644 index 0000000..d3db681 --- /dev/null +++ b/group___s_a_i___group2.md5 @@ -0,0 +1 @@ +414f79186d40b6d3e24b01bec7cd0f5f \ No newline at end of file diff --git a/group___s_a_i___group2.png b/group___s_a_i___group2.png new file mode 100644 index 0000000..946f535 Binary files /dev/null and b/group___s_a_i___group2.png differ diff --git a/group___s_a_i___group3.html b/group___s_a_i___group3.html new file mode 100644 index 0000000..4a49399 --- /dev/null +++ b/group___s_a_i___group3.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: DMA transfers management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DMA transfers management functions
STM32F4xx_StdPeriph_Driver » SAI » SAI_Private_Functions
+
+
+ +

DMA transfers management functions. +More...

+
+Collaboration diagram for DMA transfers management functions:
+
+
+ + +
+
+ + + + + +

+Functions

void SAI_DMACmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the SAI Block x DMA interface. More...
 
+

Detailed Description

+

DMA transfers management functions.

+
 ===============================================================================
+                  ##### DMA transfers management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_DMACmd (SAI_Block_TypeDef * SAI_Block_x,
FunctionalState NewState 
)
+
+ +

Enables or disables the SAI Block x DMA interface.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
NewStatenew state of the selected SAI block DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___group3.map b/group___s_a_i___group3.map new file mode 100644 index 0000000..07cae8f --- /dev/null +++ b/group___s_a_i___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___group3.md5 b/group___s_a_i___group3.md5 new file mode 100644 index 0000000..4941f50 --- /dev/null +++ b/group___s_a_i___group3.md5 @@ -0,0 +1 @@ +22bd2a4ec0af1b557680caaea693c3ef \ No newline at end of file diff --git a/group___s_a_i___group3.png b/group___s_a_i___group3.png new file mode 100644 index 0000000..6601f7e Binary files /dev/null and b/group___s_a_i___group3.png differ diff --git a/group___s_a_i___group4.html b/group___s_a_i___group4.html new file mode 100644 index 0000000..96785ef --- /dev/null +++ b/group___s_a_i___group4.html @@ -0,0 +1,560 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » SAI » SAI_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SAI_ITConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
 Enables or disables the specified SAI Block interrupts. More...
 
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Checks whether the specified SAI block x flag is set or not. More...
 
void SAI_ClearFlag (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Clears the specified SAI Block x flag. More...
 
ITStatus SAI_GetITStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Checks whether the specified SAI Block x interrupt has occurred or not. More...
 
void SAI_ClearITPendingBit (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Clears the SAI Block x interrupt pending bit. More...
 
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the status of EN bit for the specified SAI Block x. More...
 
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the current SAI Block x FIFO filled level. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+  [..]
+  This section provides a set of functions allowing to configure the SAI Interrupts 
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  *** Polling Mode ***
+  ====================
+  [..]
+  In Polling Mode, the SAI communication can be managed by 7 flags:
+     (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read.
+     (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected
+     (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur
+     (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame 
+                          synchronisation (FS) earlier than expected
+     (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame 
+                          synchronisation (FS) later than expected              
+     (#) SAI_FLAG_CNRDY : to indicate if  the codec is not ready to communicate during 
+                         the reception of the TAG 0 (slot0) of the AC97 audio frame 
+     (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode 
+                         error occurs.
+  [..]
+  In this Mode it is advised to use the following functions:
+     (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
+     (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
+
+  *** Interrupt Mode ***
+  ======================
+  [..]
+  In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources
+  and 7 pending bits: 
+  (+) Pending Bits:
+     (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read.
+     (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected.
+     (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur.
+     (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame 
+                          synchronisation (FS) earlier than expected.
+     (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame 
+                          synchronisation (FS) later than expected.              
+     (##) SAI_IT_CNRDY : to indicate if  the codec is not ready to communicate during 
+                         the reception of the TAG 0 (slot0) of the AC97 audio frame. 
+     (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode 
+                         error occurs.
+
+  (+) Interrupt Source:
+     (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request.
+     (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected.
+     (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error.
+     (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization
+                          detection interrupt.
+     (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization
+                          detection interrupt.             
+     (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt
+     (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration
+                         interrupt.
+  [..]                     
+  In this Mode it is advised to use the following functions:
+     (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
+     (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
+     (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
+
+  *** DMA Mode ***
+  ================
+  [..]
+  In DMA Mode, each SAI audio block has an independent DMA interface in order to 
+  read or to write into the SAI_xDR register (to hit the internal FIFO). 
+  There is one DMA channel by audio block following basic DMA request/acknowledge 
+  protocol.
+  [..]
+  In this Mode it is advised to use the following function:
+    (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
+  [..]
+  This section provides also functions allowing to
+   (+) Check the SAI Block enable status
+   (+)Check the FIFO status 
+   
+  *** SAI Block Enable status ***
+  ===============================
+  [..]
+  After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block 
+  is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing
+  the current frame will be transferred and the block will be effectively disabled only at 
+  the end of audio frame. 
+  To monitor this state it is possible to use the following function:
+    (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); 
+ 
+  *** SAI Block FIFO status ***
+  =============================
+  [..]
+  It is possible to monitor the FIFO status when a transfer is ongoing using the following 
+  function:
+    (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_ClearFlag (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_FLAG 
)
+
+ +

Clears the specified SAI Block x flag.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FLAGspecifies the SAI block flag to check. This parameter can be one of the following values:
    +
  • SAI_FLAG_MUTEDET: MUTE detection flag.
    • +
  • SAI_FLAG_OVRUDR: overrun/underrun flag.
    • +
  • SAI_FLAG_WCKCFG: wrong clock configuration flag.
    • +
  • SAI_FLAG_CNRDY: codec not ready flag.
    • +
  • SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
    • +
  • SAI_FLAG_LFSDET: late frame synchronization detection flag.
    • +
+
+
+
+
Note
FREQ (FIFO Request) flag is cleared :
    +
  • When the audio block is transmitter and the FIFO is full or the FIFO has one data (one buffer mode) depending the bit FTH in the SAI_xCR2 register.
    • +
  • When the audio block is receiver and the FIFO is not empty
    • +
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SAI_ClearITPendingBit (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT 
)
+
+ +

Clears the SAI Block x interrupt pending bit.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI Block interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • SAI_IT_MUTEDET: MUTE detection interrupt.
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt.
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt.
    • +
  • SAI_IT_CNRDY: codec not ready interrupt.
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt.
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt.
    • +
+
+
+
+
Note
FREQ (FIFO Request) flag is cleared :
    +
  • When the audio block is transmitter and the FIFO is full or the FIFO has one data (one buffer mode) depending the bit FTH in the SAI_xCR2 register.
    • +
  • When the audio block is receiver and the FIFO is not empty
    • +
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the status of EN bit for the specified SAI Block x.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Note
After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing, the current frame will be transferred and the block will be effectively disabled only at the end of audio frame.
+
Return values
+ + +
Currentstate of the DMAy Streamx (ENABLE or DISABLE).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef * SAI_Block_x)
+
+ +

Returns the current SAI Block x FIFO filled level.

+
Parameters
+ + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
+
+
+
Return values
+ + +
TheFIFO filling state.
    +
  • SAI_FIFOStatus_Empty: when FIFO is empty
    • +
  • SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.
    • +
  • SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
    • +
  • SAI_FIFOStatus_HalfFull: if more than 1 half-full.
    • +
  • SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
    • +
  • SAI_FIFOStatus_Full: when FIFO is full
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_FLAG 
)
+
+ +

Checks whether the specified SAI block x flag is set or not.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_FLAGspecifies the SAI block flag to check. This parameter can be one of the following values:
    +
  • SAI_FLAG_FREQ: FIFO Request flag.
    • +
  • SAI_FLAG_MUTEDET: MUTE detection flag.
    • +
  • SAI_FLAG_OVRUDR: overrun/underrun flag.
    • +
  • SAI_FLAG_WCKCFG: wrong clock configuration flag.
    • +
  • SAI_FLAG_CNRDY: codec not ready flag.
    • +
  • SAI_FLAG_AFSDET: anticipated frame synchronization detection flag.
    • +
  • SAI_FLAG_LFSDET: late frame synchronization detection flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SAI_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus SAI_GetITStatus (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT 
)
+
+ +

Checks whether the specified SAI Block x interrupt has occurred or not.

+
Parameters
+ + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SAI_IT_FREQ: FIFO Request interrupt
    • +
  • SAI_IT_MUTEDET: MUTE detection interrupt
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt
    • +
  • SAI_IT_CNRDY: codec not ready interrupt
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of SAI_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SAI_ITConfig (SAI_Block_TypeDef * SAI_Block_x,
uint32_t SAI_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SAI Block interrupts.

+
Parameters
+ + + + +
SAI_Block_xwhere x can be A or B to select the SAI Block peripheral.
SAI_ITspecifies the SAI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SAI_IT_FREQ: FIFO Request interrupt mask
    • +
  • SAI_IT_MUTEDET: MUTE detection interrupt mask
    • +
  • SAI_IT_OVRUDR: overrun/underrun interrupt mask
    • +
  • SAI_IT_AFSDET: anticipated frame synchronization detection interrupt mask
    • +
  • SAI_IT_LFSDET: late frame synchronization detection interrupt mask
    • +
  • SAI_IT_CNRDY: codec not ready interrupt mask
    • +
  • SAI_IT_WCKCFG: wrong clock configuration interrupt mask
    • +
+
NewStatenew state of the specified SAI interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___group4.map b/group___s_a_i___group4.map new file mode 100644 index 0000000..bafbc1f --- /dev/null +++ b/group___s_a_i___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___group4.md5 b/group___s_a_i___group4.md5 new file mode 100644 index 0000000..003167d --- /dev/null +++ b/group___s_a_i___group4.md5 @@ -0,0 +1 @@ +86c63735ab5d0ea2ca54ef8c7d83fb9e \ No newline at end of file diff --git a/group___s_a_i___group4.png b/group___s_a_i___group4.png new file mode 100644 index 0000000..8c5ea3a Binary files /dev/null and b/group___s_a_i___group4.png differ diff --git a/group___s_a_i___mono___streo___mode.html b/group___s_a_i___mono___streo___mode.html new file mode 100644 index 0000000..802eadc --- /dev/null +++ b/group___s_a_i___mono___streo___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_Mono_Streo_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_Mono_Streo_Mode
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_Mono_Streo_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_MonoMode   ((uint32_t)SAI_xCR1_MONO)
 
+#define SAI_StreoMode   ((uint32_t)0x00000000)
 
#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_MONO_STREO_MODE( MODE)
+
+Value:
(((MODE) == SAI_MonoMode) ||\
+
((MODE) == SAI_StreoMode))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___mono___streo___mode.map b/group___s_a_i___mono___streo___mode.map new file mode 100644 index 0000000..fd679a8 --- /dev/null +++ b/group___s_a_i___mono___streo___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___mono___streo___mode.md5 b/group___s_a_i___mono___streo___mode.md5 new file mode 100644 index 0000000..f195800 --- /dev/null +++ b/group___s_a_i___mono___streo___mode.md5 @@ -0,0 +1 @@ +ded886a274700985157f8ee2d4817e06 \ No newline at end of file diff --git a/group___s_a_i___mono___streo___mode.png b/group___s_a_i___mono___streo___mode.png new file mode 100644 index 0000000..44c2eb6 Binary files /dev/null and b/group___s_a_i___mono___streo___mode.png differ diff --git a/group___s_a_i___private___functions.html b/group___s_a_i___private___functions.html new file mode 100644 index 0000000..8741379 --- /dev/null +++ b/group___s_a_i___private___functions.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: SAI_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
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+ +
+
+Modules
+
+
SAI_Private_Functions
STM32F4xx_StdPeriph_Driver » SAI
+
+
+
+Collaboration diagram for SAI_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Data transfers functions
 Data transfers functions.
 
 DMA transfers management functions
 DMA transfers management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___private___functions.map b/group___s_a_i___private___functions.map new file mode 100644 index 0000000..bf2fe0b --- /dev/null +++ b/group___s_a_i___private___functions.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___s_a_i___private___functions.md5 b/group___s_a_i___private___functions.md5 new file mode 100644 index 0000000..df3b943 --- /dev/null +++ b/group___s_a_i___private___functions.md5 @@ -0,0 +1 @@ +ef1dbdb5444f3fbd13398d8a8d5e9e71 \ No newline at end of file diff --git a/group___s_a_i___private___functions.png b/group___s_a_i___private___functions.png new file mode 100644 index 0000000..fdc91cc Binary files /dev/null and b/group___s_a_i___private___functions.png differ diff --git a/group___s_a_i___t_r_i_state___management.html b/group___s_a_i___t_r_i_state___management.html new file mode 100644 index 0000000..fcca33a --- /dev/null +++ b/group___s_a_i___t_r_i_state___management.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SAI_TRIState_Management + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SAI_TRIState_Management
STM32F4xx_StdPeriph_Driver » SAI » SAI_Exported_Constants
+
+
+
+Collaboration diagram for SAI_TRIState_Management:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SAI_Output_NotReleased   ((uint32_t)0x00000000)
 
+#define SAI_Output_Released   ((uint32_t)SAI_xCR2_TRIS)
 
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT( STATE)
+
+Value:
(((STATE) == SAI_Output_NotReleased) ||\
+
((STATE) == SAI_Output_Released))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_a_i___t_r_i_state___management.map b/group___s_a_i___t_r_i_state___management.map new file mode 100644 index 0000000..813f960 --- /dev/null +++ b/group___s_a_i___t_r_i_state___management.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i___t_r_i_state___management.md5 b/group___s_a_i___t_r_i_state___management.md5 new file mode 100644 index 0000000..60a2547 --- /dev/null +++ b/group___s_a_i___t_r_i_state___management.md5 @@ -0,0 +1 @@ +d6e6644f362cc4780860abdff34c71c7 \ No newline at end of file diff --git a/group___s_a_i___t_r_i_state___management.png b/group___s_a_i___t_r_i_state___management.png new file mode 100644 index 0000000..44a58a1 Binary files /dev/null and b/group___s_a_i___t_r_i_state___management.png differ diff --git a/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map new file mode 100644 index 0000000..0f2ad40 --- /dev/null +++ b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 new file mode 100644 index 0000000..240364a --- /dev/null +++ b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.md5 @@ -0,0 +1 @@ +be41093f65d5057d152724dee17a8939 \ No newline at end of file diff --git a/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png new file mode 100644 index 0000000..12f83a0 Binary files /dev/null and b/group___s_a_i_gadcef52be2d2792a70f67b6e7872b334e_cgraph.png differ diff --git a/group___s_d_i_o.html b/group___s_d_i_o.html new file mode 100644 index 0000000..86b840f --- /dev/null +++ b/group___s_d_i_o.html @@ -0,0 +1,1356 @@ + + + + + + +discoverpixy: SDIO + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
SDIO
STM32F4xx_StdPeriph_Driver
+
+
+ +

SDIO driver modules. +More...

+
+Collaboration diagram for SDIO:
+
+
+ + +
+
+ + + + + + +

+Modules

 SDIO_Exported_Constants
 
 SDIO_Private_Functions
 
+ + + + + + + +

+Classes

struct  SDIO_InitTypeDef
 
struct  SDIO_CmdInitTypeDef
 
struct  SDIO_DataInitTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_OFFSET   (SDIO_BASE - PERIPH_BASE)
 
+#define CLKCR_OFFSET   (SDIO_OFFSET + 0x04)
 
+#define CLKEN_BitNumber   0x08
 
+#define CLKCR_CLKEN_BB   (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
 
+#define CMD_OFFSET   (SDIO_OFFSET + 0x0C)
 
+#define SDIOSUSPEND_BitNumber   0x0B
 
+#define CMD_SDIOSUSPEND_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
 
+#define ENCMDCOMPL_BitNumber   0x0C
 
+#define CMD_ENCMDCOMPL_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
 
+#define NIEN_BitNumber   0x0D
 
+#define CMD_NIEN_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
 
+#define ATACMD_BitNumber   0x0E
 
+#define CMD_ATACMD_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 
+#define DCTRL_OFFSET   (SDIO_OFFSET + 0x2C)
 
+#define DMAEN_BitNumber   0x03
 
+#define DCTRL_DMAEN_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 
+#define RWSTART_BitNumber   0x08
 
+#define DCTRL_RWSTART_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
 
+#define RWSTOP_BitNumber   0x09
 
+#define DCTRL_RWSTOP_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 
+#define RWMOD_BitNumber   0x0A
 
+#define DCTRL_RWMOD_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
 
+#define SDIOEN_BitNumber   0x0B
 
+#define DCTRL_SDIOEN_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
 
+#define CLKCR_CLEAR_MASK   ((uint32_t)0xFFFF8100)
 
+#define PWR_PWRCTRL_MASK   ((uint32_t)0xFFFFFFFC)
 
+#define DCTRL_CLEAR_MASK   ((uint32_t)0xFFFFFF08)
 
+#define CMD_CLEAR_MASK   ((uint32_t)0xFFFFF800)
 
+#define SDIO_RESP_ADDR   ((uint32_t)(SDIO_BASE + 0x14))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SDIO_DeInit (void)
 Deinitializes the SDIO peripheral registers to their default reset values. More...
 
void SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
 Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. More...
 
void SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
 Fills each SDIO_InitStruct member with its default value. More...
 
void SDIO_ClockCmd (FunctionalState NewState)
 Enables or disables the SDIO Clock. More...
 
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
 Sets the power status of the controller. More...
 
uint32_t SDIO_GetPowerState (void)
 Gets the power status of the controller. More...
 
void SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command. More...
 
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Fills each SDIO_CmdInitStruct member with its default value. More...
 
uint8_t SDIO_GetCommandResponse (void)
 Returns command index of last command for which response received. More...
 
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
 Returns response received from the card for the last command. More...
 
void SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. More...
 
void SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Fills each SDIO_DataInitStruct member with its default value. More...
 
uint32_t SDIO_GetDataCounter (void)
 Returns number of remaining data bytes to be transferred. More...
 
uint32_t SDIO_ReadData (void)
 Read one data word from Rx FIFO. More...
 
void SDIO_WriteData (uint32_t Data)
 Write one data word to Tx FIFO. More...
 
uint32_t SDIO_GetFIFOCount (void)
 Returns the number of words left to be written to or read from FIFO. More...
 
void SDIO_StartSDIOReadWait (FunctionalState NewState)
 Starts the SD I/O Read Wait operation. More...
 
void SDIO_StopSDIOReadWait (FunctionalState NewState)
 Stops the SD I/O Read Wait operation. More...
 
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
 Sets one of the two options of inserting read wait interval. More...
 
void SDIO_SetSDIOOperation (FunctionalState NewState)
 Enables or disables the SD I/O Mode Operation. More...
 
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
 Enables or disables the SD I/O Mode suspend command sending. More...
 
void SDIO_CommandCompletionCmd (FunctionalState NewState)
 Enables or disables the command completion signal. More...
 
void SDIO_CEATAITCmd (FunctionalState NewState)
 Enables or disables the CE-ATA interrupt. More...
 
void SDIO_SendCEATACmd (FunctionalState NewState)
 Sends CE-ATA command (CMD61). More...
 
void SDIO_DMACmd (FunctionalState NewState)
 Enables or disables the SDIO DMA request. More...
 
void SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
 Enables or disables the SDIO interrupts. More...
 
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
 Checks whether the specified SDIO flag is set or not. More...
 
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
 Clears the SDIO's pending flags. More...
 
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
 Checks whether the specified SDIO interrupt has occurred or not. More...
 
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
 Clears the SDIO's interrupt pending bits. More...
 
+

Detailed Description

+

SDIO driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_CEATAITCmd (FunctionalState NewState)
+
+ +

Enables or disables the CE-ATA interrupt.

+
Parameters
+ + +
NewStatenew state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
+
+ +

Clears the SDIO's pending flags.

+
Parameters
+ + +
SDIO_FLAGspecifies the flag to clear. This parameter can be one or a combination of the following values:
    +
  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
    • +
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
    • +
  • SDIO_FLAG_CTIMEOUT: Command response timeout
    • +
  • SDIO_FLAG_DTIMEOUT: Data timeout
    • +
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
    • +
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
    • +
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
    • +
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
    • +
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
    • +
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
    • +
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
    • +
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
    • +
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
+
+ +

Clears the SDIO's interrupt pending bits.

+
Parameters
+ + +
SDIO_ITspecifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_ClockCmd (FunctionalState NewState)
+
+ +

Enables or disables the SDIO Clock.

+
Parameters
+ + +
NewStatenew state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef * SDIO_CmdInitStruct)
+
+ +

Fills each SDIO_CmdInitStruct member with its default value.

+
Parameters
+ + +
SDIO_CmdInitStructpointer to an SDIO_CmdInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_CommandCompletionCmd (FunctionalState NewState)
+
+ +

Enables or disables the command completion signal.

+
Parameters
+ + +
NewStatenew state of command completion signal. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DataConfig (SDIO_DataInitTypeDef * SDIO_DataInitStruct)
+
+ +

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

+
Parameters
+ + +
SDIO_DataInitStruct: pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DataStructInit (SDIO_DataInitTypeDef * SDIO_DataInitStruct)
+
+ +

Fills each SDIO_DataInitStruct member with its default value.

+
Parameters
+ + +
SDIO_DataInitStructpointer to an SDIO_DataInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DeInit (void )
+
+ +

Deinitializes the SDIO peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DMACmd (FunctionalState NewState)
+
+ +

Enables or disables the SDIO DMA request.

+
Parameters
+ + +
NewStatenew state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t SDIO_GetCommandResponse (void )
+
+ +

Returns command index of last command for which response received.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Returnsthe command index of the last command response received.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetDataCounter (void )
+
+ +

Returns number of remaining data bytes to be transferred.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Numberof remaining data bytes to be transferred
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetFIFOCount (void )
+
+ +

Returns the number of words left to be written to or read from FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Remainingnumber of words.
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
+
+ +

Checks whether the specified SDIO flag is set or not.

+
Parameters
+ + +
SDIO_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
    • +
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
    • +
  • SDIO_FLAG_CTIMEOUT: Command response timeout
    • +
  • SDIO_FLAG_DTIMEOUT: Data timeout
    • +
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
    • +
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
    • +
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
    • +
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
    • +
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
    • +
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
    • +
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
    • +
  • SDIO_FLAG_CMDACT: Command transfer in progress
    • +
  • SDIO_FLAG_TXACT: Data transmit in progress
    • +
  • SDIO_FLAG_RXACT: Data receive in progress
    • +
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
    • +
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
    • +
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full
    • +
  • SDIO_FLAG_RXFIFOF: Receive FIFO full
    • +
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty
    • +
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty
    • +
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO
    • +
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO
    • +
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
    • +
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
Thenew state of SDIO_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
+
+ +

Checks whether the specified SDIO interrupt has occurred or not.

+
Parameters
+ + +
SDIO_ITspecifies the SDIO interrupt source to check. This parameter can be one of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
    • +
  • SDIO_IT_TXACT: Data transmit in progress interrupt
    • +
  • SDIO_IT_RXACT: Data receive in progress interrupt
    • +
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
    • +
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
    • +
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
    • +
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
    • +
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
    • +
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
    • +
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
    • +
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of SDIO_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetPowerState (void )
+
+ +

Gets the power status of the controller.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Powerstatus of the controller. The returned value can be one of the following values:
    +
  • 0x00: Power OFF
    • +
  • 0x02: Power UP
    • +
  • 0x03: Power ON
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
+
+ +

Returns response received from the card for the last command.

+
Parameters
+ + +
SDIO_RESPSpecifies the SDIO response register. This parameter can be one of the following values:
    +
  • SDIO_RESP1: Response Register 1
    • +
  • SDIO_RESP2: Response Register 2
    • +
  • SDIO_RESP3: Response Register 3
    • +
  • SDIO_RESP4: Response Register 4
    • +
+
+
+
+
Return values
+ + +
TheCorresponding response register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_Init (SDIO_InitTypeDef * SDIO_InitStruct)
+
+ +

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

+
Parameters
+ + +
SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SDIO_ITConfig (uint32_t SDIO_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the SDIO interrupts.

+
Parameters
+ + + +
SDIO_ITspecifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
    • +
  • SDIO_IT_TXACT: Data transmit in progress interrupt
    • +
  • SDIO_IT_RXACT: Data receive in progress interrupt
    • +
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
    • +
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
    • +
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
    • +
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
    • +
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
    • +
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
    • +
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
    • +
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
    • +
+
NewStatenew state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_ReadData (void )
+
+ +

Read one data word from Rx FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Datareceived
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SendCEATACmd (FunctionalState NewState)
+
+ +

Sends CE-ATA command (CMD61).

+
Parameters
+ + +
NewStatenew state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SendCommand (SDIO_CmdInitTypeDef * SDIO_CmdInitStruct)
+
+ +

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

+
Parameters
+ + +
SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
+
+ +

Enables or disables the SD I/O Mode suspend command sending.

+
Parameters
+ + +
NewStatenew state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
+
+ +

Sets the power status of the controller.

+
Parameters
+ + +
SDIO_PowerStatenew state of the Power state. This parameter can be one of the following values:
    +
  • SDIO_PowerState_OFF: SDIO Power OFF
    • +
  • SDIO_PowerState_ON: SDIO Power ON
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetSDIOOperation (FunctionalState NewState)
+
+ +

Enables or disables the SD I/O Mode Operation.

+
Parameters
+ + +
NewStatenew state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
+
+ +

Sets one of the two options of inserting read wait interval.

+
Parameters
+ + +
SDIO_ReadWaitModeSD I/O Read Wait operation mode. This parameter can be:
    +
  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
    • +
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StartSDIOReadWait (FunctionalState NewState)
+
+ +

Starts the SD I/O Read Wait operation.

+
Parameters
+ + +
NewStatenew state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StopSDIOReadWait (FunctionalState NewState)
+
+ +

Stops the SD I/O Read Wait operation.

+
Parameters
+ + +
NewStatenew state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StructInit (SDIO_InitTypeDef * SDIO_InitStruct)
+
+ +

Fills each SDIO_InitStruct member with its default value.

+
Parameters
+ + +
SDIO_InitStructpointer to an SDIO_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_WriteData (uint32_t Data)
+
+ +

Write one data word to Tx FIFO.

+
Parameters
+ + +
Data32-bit data word to write.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o.map b/group___s_d_i_o.map new file mode 100644 index 0000000..5ece813 --- /dev/null +++ b/group___s_d_i_o.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___s_d_i_o.md5 b/group___s_d_i_o.md5 new file mode 100644 index 0000000..e57f7f6 --- /dev/null +++ b/group___s_d_i_o.md5 @@ -0,0 +1 @@ +2fcf829034b2271240ec08be85e2652f \ No newline at end of file diff --git a/group___s_d_i_o.png b/group___s_d_i_o.png new file mode 100644 index 0000000..bccb973 Binary files /dev/null and b/group___s_d_i_o.png differ diff --git a/group___s_d_i_o___bus___wide.html b/group___s_d_i_o___bus___wide.html new file mode 100644 index 0000000..fb2d28b --- /dev/null +++ b/group___s_d_i_o___bus___wide.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: SDIO_Bus_Wide + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Bus_Wide
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Bus_Wide:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define SDIO_BusWide_1b   ((uint32_t)0x00000000)
 
+#define SDIO_BusWide_4b   ((uint32_t)0x00000800)
 
+#define SDIO_BusWide_8b   ((uint32_t)0x00001000)
 
#define IS_SDIO_BUS_WIDE(WIDE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_BUS_WIDE( WIDE)
+
+Value:
(((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+
((WIDE) == SDIO_BusWide_8b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___bus___wide.map b/group___s_d_i_o___bus___wide.map new file mode 100644 index 0000000..f26d0ce --- /dev/null +++ b/group___s_d_i_o___bus___wide.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___bus___wide.md5 b/group___s_d_i_o___bus___wide.md5 new file mode 100644 index 0000000..8f34472 --- /dev/null +++ b/group___s_d_i_o___bus___wide.md5 @@ -0,0 +1 @@ +bc3e176b3b50ba093bc1a6bcbfe52122 \ No newline at end of file diff --git a/group___s_d_i_o___bus___wide.png b/group___s_d_i_o___bus___wide.png new file mode 100644 index 0000000..95ba39d Binary files /dev/null and b/group___s_d_i_o___bus___wide.png differ diff --git a/group___s_d_i_o___c_p_s_m___state.html b/group___s_d_i_o___c_p_s_m___state.html new file mode 100644 index 0000000..4c738d2 --- /dev/null +++ b/group___s_d_i_o___c_p_s_m___state.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: SDIO_CPSM_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_CPSM_State
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_CPSM_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_CPSM_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_CPSM_Enable   ((uint32_t)0x00000400)
 
+#define IS_SDIO_CPSM(CPSM)   (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___c_p_s_m___state.map b/group___s_d_i_o___c_p_s_m___state.map new file mode 100644 index 0000000..33ae423 --- /dev/null +++ b/group___s_d_i_o___c_p_s_m___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___c_p_s_m___state.md5 b/group___s_d_i_o___c_p_s_m___state.md5 new file mode 100644 index 0000000..ea3914b --- /dev/null +++ b/group___s_d_i_o___c_p_s_m___state.md5 @@ -0,0 +1 @@ +8a3d6c2d19be8559823643b0de58e8b2 \ No newline at end of file diff --git a/group___s_d_i_o___c_p_s_m___state.png b/group___s_d_i_o___c_p_s_m___state.png new file mode 100644 index 0000000..9824d09 Binary files /dev/null and b/group___s_d_i_o___c_p_s_m___state.png differ diff --git a/group___s_d_i_o___clock___bypass.html b/group___s_d_i_o___clock___bypass.html new file mode 100644 index 0000000..64e247f --- /dev/null +++ b/group___s_d_i_o___clock___bypass.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Clock_Bypass + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Clock_Bypass
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Clock_Bypass:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_ClockBypass_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_ClockBypass_Enable   ((uint32_t)0x00000400)
 
#define IS_SDIO_CLOCK_BYPASS(BYPASS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_CLOCK_BYPASS( BYPASS)
+
+Value:
(((BYPASS) == SDIO_ClockBypass_Disable) || \
+
((BYPASS) == SDIO_ClockBypass_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___clock___bypass.map b/group___s_d_i_o___clock___bypass.map new file mode 100644 index 0000000..af15a00 --- /dev/null +++ b/group___s_d_i_o___clock___bypass.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___clock___bypass.md5 b/group___s_d_i_o___clock___bypass.md5 new file mode 100644 index 0000000..acb2db0 --- /dev/null +++ b/group___s_d_i_o___clock___bypass.md5 @@ -0,0 +1 @@ +7c9d5b554a61669461b28dabf3878f91 \ No newline at end of file diff --git a/group___s_d_i_o___clock___bypass.png b/group___s_d_i_o___clock___bypass.png new file mode 100644 index 0000000..d51c7d2 Binary files /dev/null and b/group___s_d_i_o___clock___bypass.png differ diff --git a/group___s_d_i_o___clock___edge.html b/group___s_d_i_o___clock___edge.html new file mode 100644 index 0000000..2a3e4d2 --- /dev/null +++ b/group___s_d_i_o___clock___edge.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Clock_Edge + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Clock_Edge
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Clock_Edge:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_ClockEdge_Rising   ((uint32_t)0x00000000)
 
+#define SDIO_ClockEdge_Falling   ((uint32_t)0x00002000)
 
#define IS_SDIO_CLOCK_EDGE(EDGE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_CLOCK_EDGE( EDGE)
+
+Value:
(((EDGE) == SDIO_ClockEdge_Rising) || \
+
((EDGE) == SDIO_ClockEdge_Falling))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___clock___edge.map b/group___s_d_i_o___clock___edge.map new file mode 100644 index 0000000..1b1068a --- /dev/null +++ b/group___s_d_i_o___clock___edge.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___clock___edge.md5 b/group___s_d_i_o___clock___edge.md5 new file mode 100644 index 0000000..6c8ccb5 --- /dev/null +++ b/group___s_d_i_o___clock___edge.md5 @@ -0,0 +1 @@ +d42edfd95a98696b3916407fc7320264 \ No newline at end of file diff --git a/group___s_d_i_o___clock___edge.png b/group___s_d_i_o___clock___edge.png new file mode 100644 index 0000000..9cecc42 Binary files /dev/null and b/group___s_d_i_o___clock___edge.png differ diff --git a/group___s_d_i_o___clock___power___save.html b/group___s_d_i_o___clock___power___save.html new file mode 100644 index 0000000..de36f5d --- /dev/null +++ b/group___s_d_i_o___clock___power___save.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Clock_Power_Save + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Clock_Power_Save
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Clock_Power_Save:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_ClockPowerSave_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_ClockPowerSave_Enable   ((uint32_t)0x00000200)
 
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_CLOCK_POWER_SAVE( SAVE)
+
+Value:
(((SAVE) == SDIO_ClockPowerSave_Disable) || \
+
((SAVE) == SDIO_ClockPowerSave_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___clock___power___save.map b/group___s_d_i_o___clock___power___save.map new file mode 100644 index 0000000..5c448e8 --- /dev/null +++ b/group___s_d_i_o___clock___power___save.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___clock___power___save.md5 b/group___s_d_i_o___clock___power___save.md5 new file mode 100644 index 0000000..6d6338a --- /dev/null +++ b/group___s_d_i_o___clock___power___save.md5 @@ -0,0 +1 @@ +298d220e97af71ef9b7d70509ecb5ef2 \ No newline at end of file diff --git a/group___s_d_i_o___clock___power___save.png b/group___s_d_i_o___clock___power___save.png new file mode 100644 index 0000000..b094421 Binary files /dev/null and b/group___s_d_i_o___clock___power___save.png differ diff --git a/group___s_d_i_o___command___index.html b/group___s_d_i_o___command___index.html new file mode 100644 index 0000000..e62d972 --- /dev/null +++ b/group___s_d_i_o___command___index.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SDIO_Command_Index + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Command_Index
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Command_Index:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SDIO_CMD_INDEX(INDEX)   ((INDEX) < 0x40)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___command___index.map b/group___s_d_i_o___command___index.map new file mode 100644 index 0000000..7963f9e --- /dev/null +++ b/group___s_d_i_o___command___index.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___command___index.md5 b/group___s_d_i_o___command___index.md5 new file mode 100644 index 0000000..e942c95 --- /dev/null +++ b/group___s_d_i_o___command___index.md5 @@ -0,0 +1 @@ +ce26c05e09e8cc139471e50ace533bae \ No newline at end of file diff --git a/group___s_d_i_o___command___index.png b/group___s_d_i_o___command___index.png new file mode 100644 index 0000000..1fc37d7 Binary files /dev/null and b/group___s_d_i_o___command___index.png differ diff --git a/group___s_d_i_o___d_p_s_m___state.html b/group___s_d_i_o___d_p_s_m___state.html new file mode 100644 index 0000000..f09873b --- /dev/null +++ b/group___s_d_i_o___d_p_s_m___state.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: SDIO_DPSM_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_DPSM_State
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_DPSM_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_DPSM_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_DPSM_Enable   ((uint32_t)0x00000001)
 
+#define IS_SDIO_DPSM(DPSM)   (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___d_p_s_m___state.map b/group___s_d_i_o___d_p_s_m___state.map new file mode 100644 index 0000000..947a283 --- /dev/null +++ b/group___s_d_i_o___d_p_s_m___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___d_p_s_m___state.md5 b/group___s_d_i_o___d_p_s_m___state.md5 new file mode 100644 index 0000000..7a91c7a --- /dev/null +++ b/group___s_d_i_o___d_p_s_m___state.md5 @@ -0,0 +1 @@ +8e31d3b5e389695e49a358055d0a8ee2 \ No newline at end of file diff --git a/group___s_d_i_o___d_p_s_m___state.png b/group___s_d_i_o___d_p_s_m___state.png new file mode 100644 index 0000000..fbced32 Binary files /dev/null and b/group___s_d_i_o___d_p_s_m___state.png differ diff --git a/group___s_d_i_o___data___block___size.html b/group___s_d_i_o___data___block___size.html new file mode 100644 index 0000000..6be075d --- /dev/null +++ b/group___s_d_i_o___data___block___size.html @@ -0,0 +1,185 @@ + + + + + + +discoverpixy: SDIO_Data_Block_Size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Data_Block_Size
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Data_Block_Size:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_DataBlockSize_1b   ((uint32_t)0x00000000)
 
+#define SDIO_DataBlockSize_2b   ((uint32_t)0x00000010)
 
+#define SDIO_DataBlockSize_4b   ((uint32_t)0x00000020)
 
+#define SDIO_DataBlockSize_8b   ((uint32_t)0x00000030)
 
+#define SDIO_DataBlockSize_16b   ((uint32_t)0x00000040)
 
+#define SDIO_DataBlockSize_32b   ((uint32_t)0x00000050)
 
+#define SDIO_DataBlockSize_64b   ((uint32_t)0x00000060)
 
+#define SDIO_DataBlockSize_128b   ((uint32_t)0x00000070)
 
+#define SDIO_DataBlockSize_256b   ((uint32_t)0x00000080)
 
+#define SDIO_DataBlockSize_512b   ((uint32_t)0x00000090)
 
+#define SDIO_DataBlockSize_1024b   ((uint32_t)0x000000A0)
 
+#define SDIO_DataBlockSize_2048b   ((uint32_t)0x000000B0)
 
+#define SDIO_DataBlockSize_4096b   ((uint32_t)0x000000C0)
 
+#define SDIO_DataBlockSize_8192b   ((uint32_t)0x000000D0)
 
+#define SDIO_DataBlockSize_16384b   ((uint32_t)0x000000E0)
 
#define IS_SDIO_BLOCK_SIZE(SIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_BLOCK_SIZE( SIZE)
+
+Value:
(((SIZE) == SDIO_DataBlockSize_1b) || \
+
((SIZE) == SDIO_DataBlockSize_2b) || \
+
((SIZE) == SDIO_DataBlockSize_4b) || \
+
((SIZE) == SDIO_DataBlockSize_8b) || \
+
((SIZE) == SDIO_DataBlockSize_16b) || \
+
((SIZE) == SDIO_DataBlockSize_32b) || \
+
((SIZE) == SDIO_DataBlockSize_64b) || \
+
((SIZE) == SDIO_DataBlockSize_128b) || \
+
((SIZE) == SDIO_DataBlockSize_256b) || \
+
((SIZE) == SDIO_DataBlockSize_512b) || \
+
((SIZE) == SDIO_DataBlockSize_1024b) || \
+
((SIZE) == SDIO_DataBlockSize_2048b) || \
+
((SIZE) == SDIO_DataBlockSize_4096b) || \
+
((SIZE) == SDIO_DataBlockSize_8192b) || \
+
((SIZE) == SDIO_DataBlockSize_16384b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___data___block___size.map b/group___s_d_i_o___data___block___size.map new file mode 100644 index 0000000..9e151c9 --- /dev/null +++ b/group___s_d_i_o___data___block___size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___data___block___size.md5 b/group___s_d_i_o___data___block___size.md5 new file mode 100644 index 0000000..0df7e75 --- /dev/null +++ b/group___s_d_i_o___data___block___size.md5 @@ -0,0 +1 @@ +2a9f10386141f4bfcda6bcb85e958261 \ No newline at end of file diff --git a/group___s_d_i_o___data___block___size.png b/group___s_d_i_o___data___block___size.png new file mode 100644 index 0000000..c94aa52 Binary files /dev/null and b/group___s_d_i_o___data___block___size.png differ diff --git a/group___s_d_i_o___data___length.html b/group___s_d_i_o___data___length.html new file mode 100644 index 0000000..054288b --- /dev/null +++ b/group___s_d_i_o___data___length.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SDIO_Data_Length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Data_Length
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Data_Length:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SDIO_DATA_LENGTH(LENGTH)   ((LENGTH) <= 0x01FFFFFF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___data___length.map b/group___s_d_i_o___data___length.map new file mode 100644 index 0000000..6be640e --- /dev/null +++ b/group___s_d_i_o___data___length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___data___length.md5 b/group___s_d_i_o___data___length.md5 new file mode 100644 index 0000000..245df3c --- /dev/null +++ b/group___s_d_i_o___data___length.md5 @@ -0,0 +1 @@ +dc785241153412436e20146b6fef3e6b \ No newline at end of file diff --git a/group___s_d_i_o___data___length.png b/group___s_d_i_o___data___length.png new file mode 100644 index 0000000..939ab03 Binary files /dev/null and b/group___s_d_i_o___data___length.png differ diff --git a/group___s_d_i_o___exported___constants.html b/group___s_d_i_o___exported___constants.html new file mode 100644 index 0000000..eb0fbba --- /dev/null +++ b/group___s_d_i_o___exported___constants.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: SDIO_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
SDIO_Exported_Constants
STM32F4xx_StdPeriph_Driver » SDIO
+
+
+
+Collaboration diagram for SDIO_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 SDIO_Clock_Edge
 
 SDIO_Clock_Bypass
 
 SDIO_Clock_Power_Save
 
 SDIO_Bus_Wide
 
 SDIO_Hardware_Flow_Control
 
 SDIO_Power_State
 
 SDIO_Interrupt_sources
 
 SDIO_Command_Index
 
 SDIO_Response_Type
 
 SDIO_Wait_Interrupt_State
 
 SDIO_CPSM_State
 
 SDIO_Response_Registers
 
 SDIO_Data_Length
 
 SDIO_Data_Block_Size
 
 SDIO_Transfer_Direction
 
 SDIO_Transfer_Type
 
 SDIO_DPSM_State
 
 SDIO_Flags
 
 SDIO_Read_Wait_Mode
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___exported___constants.map b/group___s_d_i_o___exported___constants.map new file mode 100644 index 0000000..08ee96c --- /dev/null +++ b/group___s_d_i_o___exported___constants.map @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___s_d_i_o___exported___constants.md5 b/group___s_d_i_o___exported___constants.md5 new file mode 100644 index 0000000..9b18aba --- /dev/null +++ b/group___s_d_i_o___exported___constants.md5 @@ -0,0 +1 @@ +266af5d286d2570e4454723eb4b32e42 \ No newline at end of file diff --git a/group___s_d_i_o___exported___constants.png b/group___s_d_i_o___exported___constants.png new file mode 100644 index 0000000..b13e66f Binary files /dev/null and b/group___s_d_i_o___exported___constants.png differ diff --git a/group___s_d_i_o___flags.html b/group___s_d_i_o___flags.html new file mode 100644 index 0000000..708060f --- /dev/null +++ b/group___s_d_i_o___flags.html @@ -0,0 +1,269 @@ + + + + + + +discoverpixy: SDIO_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Flags
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_FLAG_CCRCFAIL   ((uint32_t)0x00000001)
 
+#define SDIO_FLAG_DCRCFAIL   ((uint32_t)0x00000002)
 
+#define SDIO_FLAG_CTIMEOUT   ((uint32_t)0x00000004)
 
+#define SDIO_FLAG_DTIMEOUT   ((uint32_t)0x00000008)
 
+#define SDIO_FLAG_TXUNDERR   ((uint32_t)0x00000010)
 
+#define SDIO_FLAG_RXOVERR   ((uint32_t)0x00000020)
 
+#define SDIO_FLAG_CMDREND   ((uint32_t)0x00000040)
 
+#define SDIO_FLAG_CMDSENT   ((uint32_t)0x00000080)
 
+#define SDIO_FLAG_DATAEND   ((uint32_t)0x00000100)
 
+#define SDIO_FLAG_STBITERR   ((uint32_t)0x00000200)
 
+#define SDIO_FLAG_DBCKEND   ((uint32_t)0x00000400)
 
+#define SDIO_FLAG_CMDACT   ((uint32_t)0x00000800)
 
+#define SDIO_FLAG_TXACT   ((uint32_t)0x00001000)
 
+#define SDIO_FLAG_RXACT   ((uint32_t)0x00002000)
 
+#define SDIO_FLAG_TXFIFOHE   ((uint32_t)0x00004000)
 
+#define SDIO_FLAG_RXFIFOHF   ((uint32_t)0x00008000)
 
+#define SDIO_FLAG_TXFIFOF   ((uint32_t)0x00010000)
 
+#define SDIO_FLAG_RXFIFOF   ((uint32_t)0x00020000)
 
+#define SDIO_FLAG_TXFIFOE   ((uint32_t)0x00040000)
 
+#define SDIO_FLAG_RXFIFOE   ((uint32_t)0x00080000)
 
+#define SDIO_FLAG_TXDAVL   ((uint32_t)0x00100000)
 
+#define SDIO_FLAG_RXDAVL   ((uint32_t)0x00200000)
 
+#define SDIO_FLAG_SDIOIT   ((uint32_t)0x00400000)
 
+#define SDIO_FLAG_CEATAEND   ((uint32_t)0x00800000)
 
#define IS_SDIO_FLAG(FLAG)
 
+#define IS_SDIO_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
 
#define IS_SDIO_GET_IT(IT)
 
+#define IS_SDIO_CLEAR_IT(IT)   ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_FLAG( FLAG)
+
+Value:
(((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+
((FLAG) == SDIO_FLAG_TXUNDERR) || \
+
((FLAG) == SDIO_FLAG_RXOVERR) || \
+
((FLAG) == SDIO_FLAG_CMDREND) || \
+
((FLAG) == SDIO_FLAG_CMDSENT) || \
+
((FLAG) == SDIO_FLAG_DATAEND) || \
+
((FLAG) == SDIO_FLAG_STBITERR) || \
+
((FLAG) == SDIO_FLAG_DBCKEND) || \
+
((FLAG) == SDIO_FLAG_CMDACT) || \
+
((FLAG) == SDIO_FLAG_TXACT) || \
+
((FLAG) == SDIO_FLAG_RXACT) || \
+
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+
((FLAG) == SDIO_FLAG_TXFIFOF) || \
+
((FLAG) == SDIO_FLAG_RXFIFOF) || \
+
((FLAG) == SDIO_FLAG_TXFIFOE) || \
+
((FLAG) == SDIO_FLAG_RXFIFOE) || \
+
((FLAG) == SDIO_FLAG_TXDAVL) || \
+
((FLAG) == SDIO_FLAG_RXDAVL) || \
+
((FLAG) == SDIO_FLAG_SDIOIT) || \
+
((FLAG) == SDIO_FLAG_CEATAEND))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SDIO_GET_IT( IT)
+
+Value:
(((IT) == SDIO_IT_CCRCFAIL) || \
+
((IT) == SDIO_IT_DCRCFAIL) || \
+
((IT) == SDIO_IT_CTIMEOUT) || \
+
((IT) == SDIO_IT_DTIMEOUT) || \
+
((IT) == SDIO_IT_TXUNDERR) || \
+
((IT) == SDIO_IT_RXOVERR) || \
+
((IT) == SDIO_IT_CMDREND) || \
+
((IT) == SDIO_IT_CMDSENT) || \
+
((IT) == SDIO_IT_DATAEND) || \
+
((IT) == SDIO_IT_STBITERR) || \
+
((IT) == SDIO_IT_DBCKEND) || \
+
((IT) == SDIO_IT_CMDACT) || \
+
((IT) == SDIO_IT_TXACT) || \
+
((IT) == SDIO_IT_RXACT) || \
+
((IT) == SDIO_IT_TXFIFOHE) || \
+
((IT) == SDIO_IT_RXFIFOHF) || \
+
((IT) == SDIO_IT_TXFIFOF) || \
+
((IT) == SDIO_IT_RXFIFOF) || \
+
((IT) == SDIO_IT_TXFIFOE) || \
+
((IT) == SDIO_IT_RXFIFOE) || \
+
((IT) == SDIO_IT_TXDAVL) || \
+
((IT) == SDIO_IT_RXDAVL) || \
+
((IT) == SDIO_IT_SDIOIT) || \
+
((IT) == SDIO_IT_CEATAEND))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___flags.map b/group___s_d_i_o___flags.map new file mode 100644 index 0000000..1df0466 --- /dev/null +++ b/group___s_d_i_o___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___flags.md5 b/group___s_d_i_o___flags.md5 new file mode 100644 index 0000000..344ae63 --- /dev/null +++ b/group___s_d_i_o___flags.md5 @@ -0,0 +1 @@ +621778fcc891d16aa4691878c30f5b20 \ No newline at end of file diff --git a/group___s_d_i_o___flags.png b/group___s_d_i_o___flags.png new file mode 100644 index 0000000..abecde4 Binary files /dev/null and b/group___s_d_i_o___flags.png differ diff --git a/group___s_d_i_o___group1.html b/group___s_d_i_o___group1.html new file mode 100644 index 0000000..dfec33b --- /dev/null +++ b/group___s_d_i_o___group1.html @@ -0,0 +1,329 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void SDIO_DeInit (void)
 Deinitializes the SDIO peripheral registers to their default reset values. More...
 
void SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
 Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. More...
 
void SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
 Fills each SDIO_InitStruct member with its default value. More...
 
void SDIO_ClockCmd (FunctionalState NewState)
 Enables or disables the SDIO Clock. More...
 
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
 Sets the power status of the controller. More...
 
uint32_t SDIO_GetPowerState (void)
 Gets the power status of the controller. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_ClockCmd (FunctionalState NewState)
+
+ +

Enables or disables the SDIO Clock.

+
Parameters
+ + +
NewStatenew state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DeInit (void )
+
+ +

Deinitializes the SDIO peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetPowerState (void )
+
+ +

Gets the power status of the controller.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Powerstatus of the controller. The returned value can be one of the following values:
    +
  • 0x00: Power OFF
    • +
  • 0x02: Power UP
    • +
  • 0x03: Power ON
    • +
+
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_Init (SDIO_InitTypeDef * SDIO_InitStruct)
+
+ +

Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.

+
Parameters
+ + +
SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure that contains the configuration information for the SDIO peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
+
+ +

Sets the power status of the controller.

+
Parameters
+ + +
SDIO_PowerStatenew state of the Power state. This parameter can be one of the following values:
    +
  • SDIO_PowerState_OFF: SDIO Power OFF
    • +
  • SDIO_PowerState_ON: SDIO Power ON
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StructInit (SDIO_InitTypeDef * SDIO_InitStruct)
+
+ +

Fills each SDIO_InitStruct member with its default value.

+
Parameters
+ + +
SDIO_InitStructpointer to an SDIO_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group1.map b/group___s_d_i_o___group1.map new file mode 100644 index 0000000..1acaaaa --- /dev/null +++ b/group___s_d_i_o___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group1.md5 b/group___s_d_i_o___group1.md5 new file mode 100644 index 0000000..299cbc8 --- /dev/null +++ b/group___s_d_i_o___group1.md5 @@ -0,0 +1 @@ +1c7c733bbd1b081aa57e3648a555eddb \ No newline at end of file diff --git a/group___s_d_i_o___group1.png b/group___s_d_i_o___group1.png new file mode 100644 index 0000000..6bc48ad Binary files /dev/null and b/group___s_d_i_o___group1.png differ diff --git a/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map new file mode 100644 index 0000000..2ea5cd3 --- /dev/null +++ b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 new file mode 100644 index 0000000..5a6d9a4 --- /dev/null +++ b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 @@ -0,0 +1 @@ +0f400270d7801e4011b207ded75efd6d \ No newline at end of file diff --git a/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png new file mode 100644 index 0000000..edc4ea5 Binary files /dev/null and b/group___s_d_i_o___group1_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png differ diff --git a/group___s_d_i_o___group2.html b/group___s_d_i_o___group2.html new file mode 100644 index 0000000..9954fac --- /dev/null +++ b/group___s_d_i_o___group2.html @@ -0,0 +1,254 @@ + + + + + + +discoverpixy: Command path state machine (CPSM) management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Command path state machine (CPSM) management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

Command path state machine (CPSM) management functions. +More...

+
+Collaboration diagram for Command path state machine (CPSM) management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command. More...
 
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Fills each SDIO_CmdInitStruct member with its default value. More...
 
uint8_t SDIO_GetCommandResponse (void)
 Returns command index of last command for which response received. More...
 
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
 Returns response received from the card for the last command. More...
 
+

Detailed Description

+

Command path state machine (CPSM) management functions.

+
 ===============================================================================
+        ##### Command path state machine (CPSM) management functions #####
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the Command path 
+  state machine (CPSM).

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef * SDIO_CmdInitStruct)
+
+ +

Fills each SDIO_CmdInitStruct member with its default value.

+
Parameters
+ + +
SDIO_CmdInitStructpointer to an SDIO_CmdInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint8_t SDIO_GetCommandResponse (void )
+
+ +

Returns command index of last command for which response received.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Returnsthe command index of the last command response received.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
+
+ +

Returns response received from the card for the last command.

+
Parameters
+ + +
SDIO_RESPSpecifies the SDIO response register. This parameter can be one of the following values:
    +
  • SDIO_RESP1: Response Register 1
    • +
  • SDIO_RESP2: Response Register 2
    • +
  • SDIO_RESP3: Response Register 3
    • +
  • SDIO_RESP4: Response Register 4
    • +
+
+
+
+
Return values
+ + +
TheCorresponding response register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SendCommand (SDIO_CmdInitTypeDef * SDIO_CmdInitStruct)
+
+ +

Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command.

+
Parameters
+ + +
SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains the configuration information for the SDIO command.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group2.map b/group___s_d_i_o___group2.map new file mode 100644 index 0000000..3eb3264 --- /dev/null +++ b/group___s_d_i_o___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group2.md5 b/group___s_d_i_o___group2.md5 new file mode 100644 index 0000000..8ca37eb --- /dev/null +++ b/group___s_d_i_o___group2.md5 @@ -0,0 +1 @@ +032f8412199aa2687a49ebeb05de0bd4 \ No newline at end of file diff --git a/group___s_d_i_o___group2.png b/group___s_d_i_o___group2.png new file mode 100644 index 0000000..f1118f6 Binary files /dev/null and b/group___s_d_i_o___group2.png differ diff --git a/group___s_d_i_o___group3.html b/group___s_d_i_o___group3.html new file mode 100644 index 0000000..6d43539 --- /dev/null +++ b/group___s_d_i_o___group3.html @@ -0,0 +1,314 @@ + + + + + + +discoverpixy: Data path state machine (DPSM) management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Data path state machine (DPSM) management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

Data path state machine (DPSM) management functions. +More...

+
+Collaboration diagram for Data path state machine (DPSM) management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Functions

void SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. More...
 
void SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Fills each SDIO_DataInitStruct member with its default value. More...
 
uint32_t SDIO_GetDataCounter (void)
 Returns number of remaining data bytes to be transferred. More...
 
uint32_t SDIO_ReadData (void)
 Read one data word from Rx FIFO. More...
 
void SDIO_WriteData (uint32_t Data)
 Write one data word to Tx FIFO. More...
 
uint32_t SDIO_GetFIFOCount (void)
 Returns the number of words left to be written to or read from FIFO. More...
 
+

Detailed Description

+

Data path state machine (DPSM) management functions.

+
 ===============================================================================
+         ##### Data path state machine (DPSM) management functions #####
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the Data path 
+  state machine (DPSM).

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_DataConfig (SDIO_DataInitTypeDef * SDIO_DataInitStruct)
+
+ +

Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.

+
Parameters
+ + +
SDIO_DataInitStruct: pointer to a SDIO_DataInitTypeDef structure that contains the configuration information for the SDIO command.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_DataStructInit (SDIO_DataInitTypeDef * SDIO_DataInitStruct)
+
+ +

Fills each SDIO_DataInitStruct member with its default value.

+
Parameters
+ + +
SDIO_DataInitStructpointer to an SDIO_DataInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetDataCounter (void )
+
+ +

Returns number of remaining data bytes to be transferred.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Numberof remaining data bytes to be transferred
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_GetFIFOCount (void )
+
+ +

Returns the number of words left to be written to or read from FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Remainingnumber of words.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t SDIO_ReadData (void )
+
+ +

Read one data word from Rx FIFO.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Datareceived
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_WriteData (uint32_t Data)
+
+ +

Write one data word to Tx FIFO.

+
Parameters
+ + +
Data32-bit data word to write.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group3.map b/group___s_d_i_o___group3.map new file mode 100644 index 0000000..b4d1204 --- /dev/null +++ b/group___s_d_i_o___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group3.md5 b/group___s_d_i_o___group3.md5 new file mode 100644 index 0000000..b28197f --- /dev/null +++ b/group___s_d_i_o___group3.md5 @@ -0,0 +1 @@ +e3adaa204060b3aaea1cbadcfa494568 \ No newline at end of file diff --git a/group___s_d_i_o___group3.png b/group___s_d_i_o___group3.png new file mode 100644 index 0000000..5e6f0cb Binary files /dev/null and b/group___s_d_i_o___group3.png differ diff --git a/group___s_d_i_o___group4.html b/group___s_d_i_o___group4.html new file mode 100644 index 0000000..03d5cb8 --- /dev/null +++ b/group___s_d_i_o___group4.html @@ -0,0 +1,284 @@ + + + + + + +discoverpixy: SDIO IO Cards mode management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
SDIO IO Cards mode management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

SDIO IO Cards mode management functions. +More...

+
+Collaboration diagram for SDIO IO Cards mode management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void SDIO_StartSDIOReadWait (FunctionalState NewState)
 Starts the SD I/O Read Wait operation. More...
 
void SDIO_StopSDIOReadWait (FunctionalState NewState)
 Stops the SD I/O Read Wait operation. More...
 
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
 Sets one of the two options of inserting read wait interval. More...
 
void SDIO_SetSDIOOperation (FunctionalState NewState)
 Enables or disables the SD I/O Mode Operation. More...
 
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
 Enables or disables the SD I/O Mode suspend command sending. More...
 
+

Detailed Description

+

SDIO IO Cards mode management functions.

+
 ===============================================================================
+               ##### SDIO IO Cards mode management functions #####
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the SDIO IO Cards.

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
+
+ +

Enables or disables the SD I/O Mode suspend command sending.

+
Parameters
+ + +
NewStatenew state of the SD I/O Mode suspend command. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetSDIOOperation (FunctionalState NewState)
+
+ +

Enables or disables the SD I/O Mode Operation.

+
Parameters
+ + +
NewStatenew state of SDIO specific operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
+
+ +

Sets one of the two options of inserting read wait interval.

+
Parameters
+ + +
SDIO_ReadWaitModeSD I/O Read Wait operation mode. This parameter can be:
    +
  • SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
    • +
  • SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StartSDIOReadWait (FunctionalState NewState)
+
+ +

Starts the SD I/O Read Wait operation.

+
Parameters
+ + +
NewStatenew state of the Start SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_StopSDIOReadWait (FunctionalState NewState)
+
+ +

Stops the SD I/O Read Wait operation.

+
Parameters
+ + +
NewStatenew state of the Stop SDIO Read Wait operation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group4.map b/group___s_d_i_o___group4.map new file mode 100644 index 0000000..3f2884b --- /dev/null +++ b/group___s_d_i_o___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group4.md5 b/group___s_d_i_o___group4.md5 new file mode 100644 index 0000000..2d20a92 --- /dev/null +++ b/group___s_d_i_o___group4.md5 @@ -0,0 +1 @@ +87ae35ccacd5de38d86aed739eb5db7d \ No newline at end of file diff --git a/group___s_d_i_o___group4.png b/group___s_d_i_o___group4.png new file mode 100644 index 0000000..21601db Binary files /dev/null and b/group___s_d_i_o___group4.png differ diff --git a/group___s_d_i_o___group5.html b/group___s_d_i_o___group5.html new file mode 100644 index 0000000..659bfe2 --- /dev/null +++ b/group___s_d_i_o___group5.html @@ -0,0 +1,214 @@ + + + + + + +discoverpixy: CE-ATA mode management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Functions
+
+
CE-ATA mode management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

CE-ATA mode management functions. +More...

+
+Collaboration diagram for CE-ATA mode management functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void SDIO_CommandCompletionCmd (FunctionalState NewState)
 Enables or disables the command completion signal. More...
 
void SDIO_CEATAITCmd (FunctionalState NewState)
 Enables or disables the CE-ATA interrupt. More...
 
void SDIO_SendCEATACmd (FunctionalState NewState)
 Sends CE-ATA command (CMD61). More...
 
+

Detailed Description

+

CE-ATA mode management functions.

+
 ===============================================================================
+                  ##### CE-ATA mode management functions #####
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the CE-ATA card.

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_CEATAITCmd (FunctionalState NewState)
+
+ +

Enables or disables the CE-ATA interrupt.

+
Parameters
+ + +
NewStatenew state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_CommandCompletionCmd (FunctionalState NewState)
+
+ +

Enables or disables the command completion signal.

+
Parameters
+ + +
NewStatenew state of command completion signal. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_SendCEATACmd (FunctionalState NewState)
+
+ +

Sends CE-ATA command (CMD61).

+
Parameters
+ + +
NewStatenew state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group5.map b/group___s_d_i_o___group5.map new file mode 100644 index 0000000..1902d27 --- /dev/null +++ b/group___s_d_i_o___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group5.md5 b/group___s_d_i_o___group5.md5 new file mode 100644 index 0000000..750be29 --- /dev/null +++ b/group___s_d_i_o___group5.md5 @@ -0,0 +1 @@ +b5908c5cf748af488497456486850eeb \ No newline at end of file diff --git a/group___s_d_i_o___group5.png b/group___s_d_i_o___group5.png new file mode 100644 index 0000000..f287399 Binary files /dev/null and b/group___s_d_i_o___group5.png differ diff --git a/group___s_d_i_o___group6.html b/group___s_d_i_o___group6.html new file mode 100644 index 0000000..eec0eba --- /dev/null +++ b/group___s_d_i_o___group6.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: DMA transfers management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DMA transfers management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

DMA transfers management functions. +More...

+
+Collaboration diagram for DMA transfers management functions:
+
+
+ + +
+
+ + + + + +

+Functions

void SDIO_DMACmd (FunctionalState NewState)
 Enables or disables the SDIO DMA request. More...
 
+

Detailed Description

+

DMA transfers management functions.

+
 ===============================================================================
+                  ##### DMA transfers management functions #####
+ ===============================================================================  
+
+  This section provide functions allowing to program SDIO DMA transfer.

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_DMACmd (FunctionalState NewState)
+
+ +

Enables or disables the SDIO DMA request.

+
Parameters
+ + +
NewStatenew state of the selected SDIO DMA request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group6.map b/group___s_d_i_o___group6.map new file mode 100644 index 0000000..3d4f9d1 --- /dev/null +++ b/group___s_d_i_o___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group6.md5 b/group___s_d_i_o___group6.md5 new file mode 100644 index 0000000..66db4e2 --- /dev/null +++ b/group___s_d_i_o___group6.md5 @@ -0,0 +1 @@ +eca2ac2bc0d4a3ecd8eb71f8107e9411 \ No newline at end of file diff --git a/group___s_d_i_o___group6.png b/group___s_d_i_o___group6.png new file mode 100644 index 0000000..43d32b5 Binary files /dev/null and b/group___s_d_i_o___group6.png differ diff --git a/group___s_d_i_o___group7.html b/group___s_d_i_o___group7.html new file mode 100644 index 0000000..03c6a2a --- /dev/null +++ b/group___s_d_i_o___group7.html @@ -0,0 +1,396 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
 Enables or disables the SDIO interrupts. More...
 
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
 Checks whether the specified SDIO flag is set or not. More...
 
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
 Clears the SDIO's pending flags. More...
 
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
 Checks whether the specified SDIO interrupt has occurred or not. More...
 
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
 Clears the SDIO's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+              ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
+
+ +

Clears the SDIO's pending flags.

+
Parameters
+ + +
SDIO_FLAGspecifies the flag to clear. This parameter can be one or a combination of the following values:
    +
  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
    • +
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
    • +
  • SDIO_FLAG_CTIMEOUT: Command response timeout
    • +
  • SDIO_FLAG_DTIMEOUT: Data timeout
    • +
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
    • +
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
    • +
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
    • +
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
    • +
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
    • +
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
    • +
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
    • +
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
    • +
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
+
+ +

Clears the SDIO's interrupt pending bits.

+
Parameters
+ + +
SDIO_ITspecifies the interrupt pending bit to clear. This parameter can be one or a combination of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
+
+ +

Checks whether the specified SDIO flag is set or not.

+
Parameters
+ + +
SDIO_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
    • +
  • SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
    • +
  • SDIO_FLAG_CTIMEOUT: Command response timeout
    • +
  • SDIO_FLAG_DTIMEOUT: Data timeout
    • +
  • SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
    • +
  • SDIO_FLAG_RXOVERR: Received FIFO overrun error
    • +
  • SDIO_FLAG_CMDREND: Command response received (CRC check passed)
    • +
  • SDIO_FLAG_CMDSENT: Command sent (no response required)
    • +
  • SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
    • +
  • SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
    • +
  • SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
    • +
  • SDIO_FLAG_CMDACT: Command transfer in progress
    • +
  • SDIO_FLAG_TXACT: Data transmit in progress
    • +
  • SDIO_FLAG_RXACT: Data receive in progress
    • +
  • SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
    • +
  • SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
    • +
  • SDIO_FLAG_TXFIFOF: Transmit FIFO full
    • +
  • SDIO_FLAG_RXFIFOF: Receive FIFO full
    • +
  • SDIO_FLAG_TXFIFOE: Transmit FIFO empty
    • +
  • SDIO_FLAG_RXFIFOE: Receive FIFO empty
    • +
  • SDIO_FLAG_TXDAVL: Data available in transmit FIFO
    • +
  • SDIO_FLAG_RXDAVL: Data available in receive FIFO
    • +
  • SDIO_FLAG_SDIOIT: SD I/O interrupt received
    • +
  • SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
    • +
+
+
+
+
Return values
+ + +
Thenew state of SDIO_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
+
+ +

Checks whether the specified SDIO interrupt has occurred or not.

+
Parameters
+ + +
SDIO_ITspecifies the SDIO interrupt source to check. This parameter can be one of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
    • +
  • SDIO_IT_TXACT: Data transmit in progress interrupt
    • +
  • SDIO_IT_RXACT: Data receive in progress interrupt
    • +
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
    • +
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
    • +
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
    • +
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
    • +
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
    • +
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
    • +
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
    • +
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of SDIO_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SDIO_ITConfig (uint32_t SDIO_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the SDIO interrupts.

+
Parameters
+ + + +
SDIO_ITspecifies the SDIO interrupt sources to be enabled or disabled. This parameter can be one or a combination of the following values:
    +
  • SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
    • +
  • SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
    • +
  • SDIO_IT_CTIMEOUT: Command response timeout interrupt
    • +
  • SDIO_IT_DTIMEOUT: Data timeout interrupt
    • +
  • SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
    • +
  • SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
    • +
  • SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDSENT: Command sent (no response required) interrupt
    • +
  • SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
    • +
  • SDIO_IT_STBITERR: Start bit not detected on all data signals in wide bus mode interrupt
    • +
  • SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
    • +
  • SDIO_IT_CMDACT: Command transfer in progress interrupt
    • +
  • SDIO_IT_TXACT: Data transmit in progress interrupt
    • +
  • SDIO_IT_RXACT: Data receive in progress interrupt
    • +
  • SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
    • +
  • SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
    • +
  • SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
    • +
  • SDIO_IT_RXFIFOF: Receive FIFO full interrupt
    • +
  • SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
    • +
  • SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
    • +
  • SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
    • +
  • SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
    • +
  • SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
    • +
  • SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
    • +
+
NewStatenew state of the specified SDIO interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___group7.map b/group___s_d_i_o___group7.map new file mode 100644 index 0000000..033c15e --- /dev/null +++ b/group___s_d_i_o___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___group7.md5 b/group___s_d_i_o___group7.md5 new file mode 100644 index 0000000..391faaa --- /dev/null +++ b/group___s_d_i_o___group7.md5 @@ -0,0 +1 @@ +544d2fc2c136f8889d8bf5820047d626 \ No newline at end of file diff --git a/group___s_d_i_o___group7.png b/group___s_d_i_o___group7.png new file mode 100644 index 0000000..faeab06 Binary files /dev/null and b/group___s_d_i_o___group7.png differ diff --git a/group___s_d_i_o___hardware___flow___control.html b/group___s_d_i_o___hardware___flow___control.html new file mode 100644 index 0000000..185c14a --- /dev/null +++ b/group___s_d_i_o___hardware___flow___control.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Hardware_Flow_Control + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Hardware_Flow_Control
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Hardware_Flow_Control:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_HardwareFlowControl_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_HardwareFlowControl_Enable   ((uint32_t)0x00004000)
 
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_HARDWARE_FLOW_CONTROL( CONTROL)
+
+Value:
(((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+
((CONTROL) == SDIO_HardwareFlowControl_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___hardware___flow___control.map b/group___s_d_i_o___hardware___flow___control.map new file mode 100644 index 0000000..194feb8 --- /dev/null +++ b/group___s_d_i_o___hardware___flow___control.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___hardware___flow___control.md5 b/group___s_d_i_o___hardware___flow___control.md5 new file mode 100644 index 0000000..9bc8ec1 --- /dev/null +++ b/group___s_d_i_o___hardware___flow___control.md5 @@ -0,0 +1 @@ +41928786ca9906b83484086bf8e1f5c1 \ No newline at end of file diff --git a/group___s_d_i_o___hardware___flow___control.png b/group___s_d_i_o___hardware___flow___control.png new file mode 100644 index 0000000..db16eda Binary files /dev/null and b/group___s_d_i_o___hardware___flow___control.png differ diff --git a/group___s_d_i_o___interrupt__sources.html b/group___s_d_i_o___interrupt__sources.html new file mode 100644 index 0000000..7720df6 --- /dev/null +++ b/group___s_d_i_o___interrupt__sources.html @@ -0,0 +1,181 @@ + + + + + + +discoverpixy: SDIO_Interrupt_sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Interrupt_sources
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Interrupt_sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_IT_CCRCFAIL   ((uint32_t)0x00000001)
 
+#define SDIO_IT_DCRCFAIL   ((uint32_t)0x00000002)
 
+#define SDIO_IT_CTIMEOUT   ((uint32_t)0x00000004)
 
+#define SDIO_IT_DTIMEOUT   ((uint32_t)0x00000008)
 
+#define SDIO_IT_TXUNDERR   ((uint32_t)0x00000010)
 
+#define SDIO_IT_RXOVERR   ((uint32_t)0x00000020)
 
+#define SDIO_IT_CMDREND   ((uint32_t)0x00000040)
 
+#define SDIO_IT_CMDSENT   ((uint32_t)0x00000080)
 
+#define SDIO_IT_DATAEND   ((uint32_t)0x00000100)
 
+#define SDIO_IT_STBITERR   ((uint32_t)0x00000200)
 
+#define SDIO_IT_DBCKEND   ((uint32_t)0x00000400)
 
+#define SDIO_IT_CMDACT   ((uint32_t)0x00000800)
 
+#define SDIO_IT_TXACT   ((uint32_t)0x00001000)
 
+#define SDIO_IT_RXACT   ((uint32_t)0x00002000)
 
+#define SDIO_IT_TXFIFOHE   ((uint32_t)0x00004000)
 
+#define SDIO_IT_RXFIFOHF   ((uint32_t)0x00008000)
 
+#define SDIO_IT_TXFIFOF   ((uint32_t)0x00010000)
 
+#define SDIO_IT_RXFIFOF   ((uint32_t)0x00020000)
 
+#define SDIO_IT_TXFIFOE   ((uint32_t)0x00040000)
 
+#define SDIO_IT_RXFIFOE   ((uint32_t)0x00080000)
 
+#define SDIO_IT_TXDAVL   ((uint32_t)0x00100000)
 
+#define SDIO_IT_RXDAVL   ((uint32_t)0x00200000)
 
+#define SDIO_IT_SDIOIT   ((uint32_t)0x00400000)
 
+#define SDIO_IT_CEATAEND   ((uint32_t)0x00800000)
 
+#define IS_SDIO_IT(IT)   ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___interrupt__sources.map b/group___s_d_i_o___interrupt__sources.map new file mode 100644 index 0000000..088680b --- /dev/null +++ b/group___s_d_i_o___interrupt__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___interrupt__sources.md5 b/group___s_d_i_o___interrupt__sources.md5 new file mode 100644 index 0000000..9b72703 --- /dev/null +++ b/group___s_d_i_o___interrupt__sources.md5 @@ -0,0 +1 @@ +210f20eb01da8c8db7d4a014c5336a3b \ No newline at end of file diff --git a/group___s_d_i_o___interrupt__sources.png b/group___s_d_i_o___interrupt__sources.png new file mode 100644 index 0000000..3eee78c Binary files /dev/null and b/group___s_d_i_o___interrupt__sources.png differ diff --git a/group___s_d_i_o___power___state.html b/group___s_d_i_o___power___state.html new file mode 100644 index 0000000..bebc779 --- /dev/null +++ b/group___s_d_i_o___power___state.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: SDIO_Power_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Power_State
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Power_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_PowerState_OFF   ((uint32_t)0x00000000)
 
+#define SDIO_PowerState_ON   ((uint32_t)0x00000003)
 
+#define IS_SDIO_POWER_STATE(STATE)   (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___power___state.map b/group___s_d_i_o___power___state.map new file mode 100644 index 0000000..b368e65 --- /dev/null +++ b/group___s_d_i_o___power___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___power___state.md5 b/group___s_d_i_o___power___state.md5 new file mode 100644 index 0000000..8ec7a06 --- /dev/null +++ b/group___s_d_i_o___power___state.md5 @@ -0,0 +1 @@ +29c33dda631ce994e0481f5dad8a3ec4 \ No newline at end of file diff --git a/group___s_d_i_o___power___state.png b/group___s_d_i_o___power___state.png new file mode 100644 index 0000000..f6b19e8 Binary files /dev/null and b/group___s_d_i_o___power___state.png differ diff --git a/group___s_d_i_o___private___functions.html b/group___s_d_i_o___private___functions.html new file mode 100644 index 0000000..f0d8634 --- /dev/null +++ b/group___s_d_i_o___private___functions.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: SDIO_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
SDIO_Private_Functions
STM32F4xx_StdPeriph_Driver » SDIO
+
+
+
+Collaboration diagram for SDIO_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Command path state machine (CPSM) management functions
 Command path state machine (CPSM) management functions.
 
 Data path state machine (DPSM) management functions
 Data path state machine (DPSM) management functions.
 
 SDIO IO Cards mode management functions
 SDIO IO Cards mode management functions.
 
 CE-ATA mode management functions
 CE-ATA mode management functions.
 
 DMA transfers management functions
 DMA transfers management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___private___functions.map b/group___s_d_i_o___private___functions.map new file mode 100644 index 0000000..2e924c0 --- /dev/null +++ b/group___s_d_i_o___private___functions.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___s_d_i_o___private___functions.md5 b/group___s_d_i_o___private___functions.md5 new file mode 100644 index 0000000..0a54010 --- /dev/null +++ b/group___s_d_i_o___private___functions.md5 @@ -0,0 +1 @@ +79d417ed67579182cecbf3b79c49583b \ No newline at end of file diff --git a/group___s_d_i_o___private___functions.png b/group___s_d_i_o___private___functions.png new file mode 100644 index 0000000..21be7d0 Binary files /dev/null and b/group___s_d_i_o___private___functions.png differ diff --git a/group___s_d_i_o___read___wait___mode.html b/group___s_d_i_o___read___wait___mode.html new file mode 100644 index 0000000..66d612a --- /dev/null +++ b/group___s_d_i_o___read___wait___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Read_Wait_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
SDIO_Read_Wait_Mode
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Read_Wait_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_ReadWaitMode_DATA2   ((uint32_t)0x00000000)
 
+#define SDIO_ReadWaitMode_CLK   ((uint32_t)0x00000001)
 
#define IS_SDIO_READWAIT_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_READWAIT_MODE( MODE)
+
+Value:
(((MODE) == SDIO_ReadWaitMode_CLK) || \
+
((MODE) == SDIO_ReadWaitMode_DATA2))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___read___wait___mode.map b/group___s_d_i_o___read___wait___mode.map new file mode 100644 index 0000000..36341c0 --- /dev/null +++ b/group___s_d_i_o___read___wait___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___read___wait___mode.md5 b/group___s_d_i_o___read___wait___mode.md5 new file mode 100644 index 0000000..9e8bfe2 --- /dev/null +++ b/group___s_d_i_o___read___wait___mode.md5 @@ -0,0 +1 @@ +02b1dec81bb4c623dfacd268f35bd8ce \ No newline at end of file diff --git a/group___s_d_i_o___read___wait___mode.png b/group___s_d_i_o___read___wait___mode.png new file mode 100644 index 0000000..cdc7013 Binary files /dev/null and b/group___s_d_i_o___read___wait___mode.png differ diff --git a/group___s_d_i_o___response___registers.html b/group___s_d_i_o___response___registers.html new file mode 100644 index 0000000..d21fe8b --- /dev/null +++ b/group___s_d_i_o___response___registers.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: SDIO_Response_Registers + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
SDIO_Response_Registers
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Response_Registers:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define SDIO_RESP1   ((uint32_t)0x00000000)
 
+#define SDIO_RESP2   ((uint32_t)0x00000004)
 
+#define SDIO_RESP3   ((uint32_t)0x00000008)
 
+#define SDIO_RESP4   ((uint32_t)0x0000000C)
 
#define IS_SDIO_RESP(RESP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_RESP( RESP)
+
+Value:
(((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___response___registers.map b/group___s_d_i_o___response___registers.map new file mode 100644 index 0000000..fabce54 --- /dev/null +++ b/group___s_d_i_o___response___registers.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___response___registers.md5 b/group___s_d_i_o___response___registers.md5 new file mode 100644 index 0000000..89dc7c7 --- /dev/null +++ b/group___s_d_i_o___response___registers.md5 @@ -0,0 +1 @@ +fe90d2b14492e8f694cbb11e3bcd29cd \ No newline at end of file diff --git a/group___s_d_i_o___response___registers.png b/group___s_d_i_o___response___registers.png new file mode 100644 index 0000000..17e854a Binary files /dev/null and b/group___s_d_i_o___response___registers.png differ diff --git a/group___s_d_i_o___response___type.html b/group___s_d_i_o___response___type.html new file mode 100644 index 0000000..b0e8725 --- /dev/null +++ b/group___s_d_i_o___response___type.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: SDIO_Response_Type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Response_Type
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Response_Type:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define SDIO_Response_No   ((uint32_t)0x00000000)
 
+#define SDIO_Response_Short   ((uint32_t)0x00000040)
 
+#define SDIO_Response_Long   ((uint32_t)0x000000C0)
 
#define IS_SDIO_RESPONSE(RESPONSE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_RESPONSE( RESPONSE)
+
+Value:
(((RESPONSE) == SDIO_Response_No) || \
+
((RESPONSE) == SDIO_Response_Short) || \
+
((RESPONSE) == SDIO_Response_Long))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___response___type.map b/group___s_d_i_o___response___type.map new file mode 100644 index 0000000..fbd3a0d --- /dev/null +++ b/group___s_d_i_o___response___type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___response___type.md5 b/group___s_d_i_o___response___type.md5 new file mode 100644 index 0000000..c95f36d --- /dev/null +++ b/group___s_d_i_o___response___type.md5 @@ -0,0 +1 @@ +d8a3520fc6be20d75b33e2811dfd1376 \ No newline at end of file diff --git a/group___s_d_i_o___response___type.png b/group___s_d_i_o___response___type.png new file mode 100644 index 0000000..c837652 Binary files /dev/null and b/group___s_d_i_o___response___type.png differ diff --git a/group___s_d_i_o___transfer___direction.html b/group___s_d_i_o___transfer___direction.html new file mode 100644 index 0000000..34bb191 --- /dev/null +++ b/group___s_d_i_o___transfer___direction.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Transfer_Direction + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Transfer_Direction
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Transfer_Direction:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_TransferDir_ToCard   ((uint32_t)0x00000000)
 
+#define SDIO_TransferDir_ToSDIO   ((uint32_t)0x00000002)
 
#define IS_SDIO_TRANSFER_DIR(DIR)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_TRANSFER_DIR( DIR)
+
+Value:
(((DIR) == SDIO_TransferDir_ToCard) || \
+
((DIR) == SDIO_TransferDir_ToSDIO))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___transfer___direction.map b/group___s_d_i_o___transfer___direction.map new file mode 100644 index 0000000..76fe29a --- /dev/null +++ b/group___s_d_i_o___transfer___direction.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___transfer___direction.md5 b/group___s_d_i_o___transfer___direction.md5 new file mode 100644 index 0000000..fa31359 --- /dev/null +++ b/group___s_d_i_o___transfer___direction.md5 @@ -0,0 +1 @@ +fd298882a6d454126a51bb1d235a59fe \ No newline at end of file diff --git a/group___s_d_i_o___transfer___direction.png b/group___s_d_i_o___transfer___direction.png new file mode 100644 index 0000000..c134beb Binary files /dev/null and b/group___s_d_i_o___transfer___direction.png differ diff --git a/group___s_d_i_o___transfer___type.html b/group___s_d_i_o___transfer___type.html new file mode 100644 index 0000000..c6d2c3a --- /dev/null +++ b/group___s_d_i_o___transfer___type.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SDIO_Transfer_Type + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Transfer_Type
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Transfer_Type:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SDIO_TransferMode_Block   ((uint32_t)0x00000000)
 
+#define SDIO_TransferMode_Stream   ((uint32_t)0x00000004)
 
#define IS_SDIO_TRANSFER_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_TRANSFER_MODE( MODE)
+
+Value:
(((MODE) == SDIO_TransferMode_Stream) || \
+
((MODE) == SDIO_TransferMode_Block))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___transfer___type.map b/group___s_d_i_o___transfer___type.map new file mode 100644 index 0000000..4fc866b --- /dev/null +++ b/group___s_d_i_o___transfer___type.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___transfer___type.md5 b/group___s_d_i_o___transfer___type.md5 new file mode 100644 index 0000000..febdfc9 --- /dev/null +++ b/group___s_d_i_o___transfer___type.md5 @@ -0,0 +1 @@ +47af7c5221b953e4047aa455436f0c14 \ No newline at end of file diff --git a/group___s_d_i_o___transfer___type.png b/group___s_d_i_o___transfer___type.png new file mode 100644 index 0000000..d9bd2af Binary files /dev/null and b/group___s_d_i_o___transfer___type.png differ diff --git a/group___s_d_i_o___wait___interrupt___state.html b/group___s_d_i_o___wait___interrupt___state.html new file mode 100644 index 0000000..b7a7eef --- /dev/null +++ b/group___s_d_i_o___wait___interrupt___state.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: SDIO_Wait_Interrupt_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SDIO_Wait_Interrupt_State
STM32F4xx_StdPeriph_Driver » SDIO » SDIO_Exported_Constants
+
+
+
+Collaboration diagram for SDIO_Wait_Interrupt_State:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define SDIO_Wait_No   ((uint32_t)0x00000000)
 
#define SDIO_Wait_IT   ((uint32_t)0x00000100)
 
#define SDIO_Wait_Pend   ((uint32_t)0x00000200)
 
#define IS_SDIO_WAIT(WAIT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SDIO_WAIT( WAIT)
+
+Value:
(((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+
((WAIT) == SDIO_Wait_Pend))
+
SDIO_Wait_No
#define SDIO_Wait_No
Definition: stm32f4xx_sdio.h:256
+
SDIO_Wait_Pend
#define SDIO_Wait_Pend
Definition: stm32f4xx_sdio.h:258
+
SDIO_Wait_IT
#define SDIO_Wait_IT
Definition: stm32f4xx_sdio.h:257
+
+
+
+ +
+
+ + + + +
#define SDIO_Wait_IT   ((uint32_t)0x00000100)
+
+

SDIO Wait Interrupt Request

+ +
+
+ +
+
+ + + + +
#define SDIO_Wait_No   ((uint32_t)0x00000000)
+
+

SDIO No Wait, TimeOut is enabled

+ +
+
+ +
+
+ + + + +
#define SDIO_Wait_Pend   ((uint32_t)0x00000200)
+
+

SDIO Wait End of transfer

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_d_i_o___wait___interrupt___state.map b/group___s_d_i_o___wait___interrupt___state.map new file mode 100644 index 0000000..bf572b6 --- /dev/null +++ b/group___s_d_i_o___wait___interrupt___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o___wait___interrupt___state.md5 b/group___s_d_i_o___wait___interrupt___state.md5 new file mode 100644 index 0000000..b792524 --- /dev/null +++ b/group___s_d_i_o___wait___interrupt___state.md5 @@ -0,0 +1 @@ +2cb2ee5d0cc1cda7ca6ab04d3a9e8faf \ No newline at end of file diff --git a/group___s_d_i_o___wait___interrupt___state.png b/group___s_d_i_o___wait___interrupt___state.png new file mode 100644 index 0000000..7f66c7c Binary files /dev/null and b/group___s_d_i_o___wait___interrupt___state.png differ diff --git a/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map new file mode 100644 index 0000000..2ea5cd3 --- /dev/null +++ b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 new file mode 100644 index 0000000..5a6d9a4 --- /dev/null +++ b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.md5 @@ -0,0 +1 @@ +0f400270d7801e4011b207ded75efd6d \ No newline at end of file diff --git a/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png new file mode 100644 index 0000000..edc4ea5 Binary files /dev/null and b/group___s_d_i_o_gac359d2c6c67a2590f8f9b720c0e4ff1b_cgraph.png differ diff --git a/group___s_p_i.html b/group___s_p_i.html new file mode 100644 index 0000000..2f6c4e3 --- /dev/null +++ b/group___s_p_i.html @@ -0,0 +1,1279 @@ + + + + + + +discoverpixy: SPI + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Classes | +Macros | +Functions
+
+
SPI
STM32F4xx_StdPeriph_Driver
+
+
+ +

SPI driver modules. +More...

+
+Collaboration diagram for SPI:
+
+
+ + +
+
+ + + + + + +

+Modules

 SPI_Exported_Constants
 
 SPI_Private_Functions
 
+ + + + + + + +

+Classes

struct  SPI_InitTypeDef
 SPI Init structure definition. More...
 
struct  I2S_InitTypeDef
 I2S Init structure definition. More...
 
+ + + + + + + + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint16_t)0x3040)
 
+#define I2SCFGR_CLEAR_MASK   ((uint16_t)0xF040)
 
+#define PLLCFGR_PPLR_MASK   ((uint32_t)0x70000000)
 
+#define PLLCFGR_PPLN_MASK   ((uint32_t)0x00007FC0)
 
+#define SPI_CR2_FRF   ((uint16_t)0x0010)
 
+#define SPI_SR_TIFRFE   ((uint16_t)0x0100)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SPI_I2S_DeInit (SPI_TypeDef *SPIx)
 De-initialize the SPIx peripheral registers to their default reset values. More...
 
void SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct. More...
 
void I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
 Fills each SPI_InitStruct member with its default value. More...
 
void I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
 Fills each I2S_InitStruct member with its default value. More...
 
void SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral. More...
 
void I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral (in I2S mode). More...
 
void SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
 Configures the data size for the selected SPI. More...
 
void SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
 Selects the data transfer direction in bidirectional mode for the specified SPI. More...
 
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
 Configures internally by software the NSS pin for the selected SPI. More...
 
void SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SS output for the selected SPI. More...
 
void SPI_TIModeCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void I2S_FullDuplexConfig (SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
 Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
 Transmits a Data through the SPIx/I2Sx peripheral. More...
 
uint16_t SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
 Returns the most recent received data by the SPIx/I2Sx peripheral. More...
 
void SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the CRC value calculation of the transferred bytes. More...
 
void SPI_TransmitCRC (SPI_TypeDef *SPIx)
 Transmit the SPIx CRC value. More...
 
uint16_t SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
 Returns the transmit or the receive CRC register value for the specified SPI. More...
 
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
 Returns the CRC Polynomial register value for the specified SPI. More...
 
void SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
 Enables or disables the specified SPI/I2S interrupts. More...
 
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Checks whether the specified SPIx/I2Sx flag is set or not. More...
 
void SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Clears the SPIx CRC Error (CRCERR) flag. More...
 
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Checks whether the specified SPIx/I2Sx interrupt has occurred or not. More...
 
void SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Clears the SPIx CRC Error (CRCERR) interrupt pending bit. More...
 
+

Detailed Description

+

SPI driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_Cmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI peripheral (in I2S mode).

+
Parameters
+ + + +
SPIxwhere x can be 2 or 3 to select the SPI peripheral (or I2Sxext for full duplex mode).
NewStatenew state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_FullDuplexConfig (SPI_TypeDef * I2Sxext,
I2S_InitTypeDef * I2S_InitStruct 
)
+
+ +

Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct.

+
Parameters
+ + + +
I2Sxextwhere x can be 2 or 3 to select the I2S peripheral extension block.
I2S_InitStructpointer to an I2S_InitTypeDef structure that contains the configuration information for the specified I2S peripheral extension.
+
+
+
Note
The structure pointed by I2S_InitStruct parameter should be the same used for the master I2S peripheral. In this case, if the master is configured as transmitter, the slave will be receiver and vice versa. Or you can force a different mode by modifying the field I2S_Mode to the value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
+
+The I2S full duplex extension can be configured in slave mode only.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_Init (SPI_TypeDef * SPIx,
I2S_InitTypeDef * I2S_InitStruct 
)
+
+ +

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

+
Parameters
+ + + +
SPIxwhere x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStructpointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
+
+
+
Note
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead.
+
+if an external clock is used as source clock for the I2S, then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set to the value of the the source clock frequency (in Hz).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2S_StructInit (I2S_InitTypeDef * I2S_InitStruct)
+
+ +

Fills each I2S_InitStruct member with its default value.

+
Parameters
+ + +
I2S_InitStructpointer to a I2S_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_BiDirectionalLineConfig (SPI_TypeDef * SPIx,
uint16_t SPI_Direction 
)
+
+ +

Selects the data transfer direction in bidirectional mode for the specified SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_Directionspecifies the data transfer direction in bidirectional mode. This parameter can be one of the following values:
    +
  • SPI_Direction_Tx: Selects Tx transmission direction
    • +
  • SPI_Direction_Rx: Selects Rx receive direction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_CalculateCRC (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the CRC value calculation of the transferred bytes.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_Cmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI peripheral.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_DataSizeConfig (SPI_TypeDef * SPIx,
uint16_t SPI_DataSize 
)
+
+ +

Configures the data size for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_DataSizespecifies the SPI data size. This parameter can be one of the following values:
    +
  • SPI_DataSize_16b: Set data frame format to 16bit
    • +
  • SPI_DataSize_8b: Set data frame format to 8bit
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t SPI_GetCRC (SPI_TypeDef * SPIx,
uint8_t SPI_CRC 
)
+
+ +

Returns the transmit or the receive CRC register value for the specified SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_CRCspecifies the CRC register to be read. This parameter can be one of the following values:
    +
  • SPI_CRC_Tx: Selects Tx CRC register
    • +
  • SPI_CRC_Rx: Selects Rx CRC register
    • +
+
+
+
+
Return values
+ + +
Theselected CRC register value..
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef * SPIx)
+
+ +

Returns the CRC Polynomial register value for the specified SPI.

+
Parameters
+ + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+
+
+
Return values
+ + +
TheCRC Polynomial register value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_ClearFlag (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_FLAG 
)
+
+ +

Clears the SPIx CRC Error (CRCERR) flag.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_FLAGspecifies the SPI flag to clear. This function clears only CRCERR flag.
    +
  • SPI_FLAG_CRCERR: CRC Error flag.
    • +
+
+
+
+
Note
OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+
+UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+
+MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_ClearITPendingBit (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT 
)
+
+ +

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.
    +
  • SPI_IT_CRCERR: CRC Error interrupt.
    • +
+
+
+
+
Note
OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+
+UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+
+MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_I2S_DeInit (SPI_TypeDef * SPIx)
+
+ +

De-initialize the SPIx peripheral registers to their default reset values.

+
Parameters
+ + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode.
+
+
+
Note
The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized when the relative I2S peripheral is de-initialized (the extended block's clock is managed by the I2S peripheral clock).
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SPI_I2S_DMACmd (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the SPIx/I2Sx DMA interface.

+
Parameters
+ + + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_DMAReqspecifies the SPI DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
    • +
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
    • +
+
NewStatenew state of the selected SPI DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_FLAG 
)
+
+ +

Checks whether the specified SPIx/I2Sx flag is set or not.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_FLAGspecifies the SPI flag to check. This parameter can be one of the following values:
    +
  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
    • +
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
    • +
  • SPI_I2S_FLAG_BSY: Busy flag.
    • +
  • SPI_I2S_FLAG_OVR: Overrun flag.
    • +
  • SPI_FLAG_MODF: Mode Fault flag.
    • +
  • SPI_FLAG_CRCERR: CRC Error flag.
    • +
  • SPI_I2S_FLAG_TIFRFE: Format Error.
    • +
  • I2S_FLAG_UDR: Underrun Error flag.
    • +
  • I2S_FLAG_CHSIDE: Channel Side flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SPI_I2S_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT 
)
+
+ +

Checks whether the specified SPIx/I2Sx interrupt has occurred or not.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt source to check. This parameter can be one of the following values:
    +
  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
    • +
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
    • +
  • SPI_I2S_IT_OVR: Overrun interrupt.
    • +
  • SPI_IT_MODF: Mode Fault interrupt.
    • +
  • SPI_IT_CRCERR: CRC Error interrupt.
    • +
  • I2S_IT_UDR: Underrun interrupt.
    • +
  • SPI_I2S_IT_TIFRFE: Format Error interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SPI_I2S_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SPI_I2S_ITConfig (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI/I2S interrupts.

+
Parameters
+ + + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
    • +
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
    • +
  • SPI_I2S_IT_ERR: Error interrupt mask
    • +
+
NewStatenew state of the specified SPI interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t SPI_I2S_ReceiveData (SPI_TypeDef * SPIx)
+
+ +

Returns the most recent received data by the SPIx/I2Sx peripheral.

+
Parameters
+ + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_SendData (SPI_TypeDef * SPIx,
uint16_t Data 
)
+
+ +

Transmits a Data through the SPIx/I2Sx peripheral.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
DataData to be transmitted.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_Init (SPI_TypeDef * SPIx,
SPI_InitTypeDef * SPI_InitStruct 
)
+
+ +

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_InitStructpointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef * SPIx,
uint16_t SPI_NSSInternalSoft 
)
+
+ +

Configures internally by software the NSS pin for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_NSSInternalSoftspecifies the SPI NSS internal state. This parameter can be one of the following values:
    +
  • SPI_NSSInternalSoft_Set: Set NSS pin internally
    • +
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_SSOutputCmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the SS output for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_StructInit (SPI_InitTypeDef * SPI_InitStruct)
+
+ +

Fills each SPI_InitStruct member with its default value.

+
Parameters
+ + +
SPI_InitStructpointer to a SPI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_TIModeCmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the SPIx/I2Sx DMA interface.

+
Note
This function can be called only after the SPI_Init() function has been called.
+
+When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA are not taken into consideration and are configured by hardware respectively to the TI mode requirements.
+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6
NewStatenew state of the selected SPI TI communication mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_TransmitCRC (SPI_TypeDef * SPIx)
+
+ +

Transmit the SPIx CRC value.

+
Parameters
+ + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i.map b/group___s_p_i.map new file mode 100644 index 0000000..d1169c1 --- /dev/null +++ b/group___s_p_i.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___s_p_i.md5 b/group___s_p_i.md5 new file mode 100644 index 0000000..8175e21 --- /dev/null +++ b/group___s_p_i.md5 @@ -0,0 +1 @@ +a28fe5d9c21049233a273d7475078024 \ No newline at end of file diff --git a/group___s_p_i.png b/group___s_p_i.png new file mode 100644 index 0000000..16146ab Binary files /dev/null and b/group___s_p_i.png differ diff --git a/group___s_p_i___baud_rate___prescaler.html b/group___s_p_i___baud_rate___prescaler.html new file mode 100644 index 0000000..85a26ed --- /dev/null +++ b/group___s_p_i___baud_rate___prescaler.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: SPI_BaudRate_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_BaudRate_Prescaler
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_BaudRate_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SPI_BaudRatePrescaler_2   ((uint16_t)0x0000)
 
+#define SPI_BaudRatePrescaler_4   ((uint16_t)0x0008)
 
+#define SPI_BaudRatePrescaler_8   ((uint16_t)0x0010)
 
+#define SPI_BaudRatePrescaler_16   ((uint16_t)0x0018)
 
+#define SPI_BaudRatePrescaler_32   ((uint16_t)0x0020)
 
+#define SPI_BaudRatePrescaler_64   ((uint16_t)0x0028)
 
+#define SPI_BaudRatePrescaler_128   ((uint16_t)0x0030)
 
+#define SPI_BaudRatePrescaler_256   ((uint16_t)0x0038)
 
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_BAUDRATE_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+
((PRESCALER) == SPI_BaudRatePrescaler_256))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___baud_rate___prescaler.map b/group___s_p_i___baud_rate___prescaler.map new file mode 100644 index 0000000..076bbfb --- /dev/null +++ b/group___s_p_i___baud_rate___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___baud_rate___prescaler.md5 b/group___s_p_i___baud_rate___prescaler.md5 new file mode 100644 index 0000000..8d94018 --- /dev/null +++ b/group___s_p_i___baud_rate___prescaler.md5 @@ -0,0 +1 @@ +695cd50329aad18af85350ae79d28abd \ No newline at end of file diff --git a/group___s_p_i___baud_rate___prescaler.png b/group___s_p_i___baud_rate___prescaler.png new file mode 100644 index 0000000..57dc555 Binary files /dev/null and b/group___s_p_i___baud_rate___prescaler.png differ diff --git a/group___s_p_i___c_r_c___transmit___receive.html b/group___s_p_i___c_r_c___transmit___receive.html new file mode 100644 index 0000000..48d05a7 --- /dev/null +++ b/group___s_p_i___c_r_c___transmit___receive.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: SPI_CRC_Transmit_Receive + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_CRC_Transmit_Receive
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_CRC_Transmit_Receive:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_CRC_Tx   ((uint8_t)0x00)
 
+#define SPI_CRC_Rx   ((uint8_t)0x01)
 
+#define IS_SPI_CRC(CRC)   (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___c_r_c___transmit___receive.map b/group___s_p_i___c_r_c___transmit___receive.map new file mode 100644 index 0000000..3b557cf --- /dev/null +++ b/group___s_p_i___c_r_c___transmit___receive.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___c_r_c___transmit___receive.md5 b/group___s_p_i___c_r_c___transmit___receive.md5 new file mode 100644 index 0000000..7fa9fb1 --- /dev/null +++ b/group___s_p_i___c_r_c___transmit___receive.md5 @@ -0,0 +1 @@ +ca02728e67f6f9c9a13bd0649df5f5ea \ No newline at end of file diff --git a/group___s_p_i___c_r_c___transmit___receive.png b/group___s_p_i___c_r_c___transmit___receive.png new file mode 100644 index 0000000..ec4ca3e Binary files /dev/null and b/group___s_p_i___c_r_c___transmit___receive.png differ diff --git a/group___s_p_i___c_r_c__polynomial.html b/group___s_p_i___c_r_c__polynomial.html new file mode 100644 index 0000000..3c25b36 --- /dev/null +++ b/group___s_p_i___c_r_c__polynomial.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: SPI_CRC_polynomial + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_CRC_polynomial
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_CRC_polynomial:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)   ((POLYNOMIAL) >= 0x1)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___c_r_c__polynomial.map b/group___s_p_i___c_r_c__polynomial.map new file mode 100644 index 0000000..9b91ef4 --- /dev/null +++ b/group___s_p_i___c_r_c__polynomial.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___c_r_c__polynomial.md5 b/group___s_p_i___c_r_c__polynomial.md5 new file mode 100644 index 0000000..45a1086 --- /dev/null +++ b/group___s_p_i___c_r_c__polynomial.md5 @@ -0,0 +1 @@ +100e26efea15011884b9099adfd96945 \ No newline at end of file diff --git a/group___s_p_i___c_r_c__polynomial.png b/group___s_p_i___c_r_c__polynomial.png new file mode 100644 index 0000000..3261370 Binary files /dev/null and b/group___s_p_i___c_r_c__polynomial.png differ diff --git a/group___s_p_i___clock___phase.html b/group___s_p_i___clock___phase.html new file mode 100644 index 0000000..1b7272a --- /dev/null +++ b/group___s_p_i___clock___phase.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_Clock_Phase + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_Clock_Phase
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_Clock_Phase:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_CPHA_1Edge   ((uint16_t)0x0000)
 
+#define SPI_CPHA_2Edge   ((uint16_t)0x0001)
 
#define IS_SPI_CPHA(CPHA)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_CPHA( CPHA)
+
+Value:
(((CPHA) == SPI_CPHA_1Edge) || \
+
((CPHA) == SPI_CPHA_2Edge))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___clock___phase.map b/group___s_p_i___clock___phase.map new file mode 100644 index 0000000..dc08abf --- /dev/null +++ b/group___s_p_i___clock___phase.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___clock___phase.md5 b/group___s_p_i___clock___phase.md5 new file mode 100644 index 0000000..1df8913 --- /dev/null +++ b/group___s_p_i___clock___phase.md5 @@ -0,0 +1 @@ +048aa593d655ba6880c39b530ecc7f9c \ No newline at end of file diff --git a/group___s_p_i___clock___phase.png b/group___s_p_i___clock___phase.png new file mode 100644 index 0000000..8a4beb4 Binary files /dev/null and b/group___s_p_i___clock___phase.png differ diff --git a/group___s_p_i___clock___polarity.html b/group___s_p_i___clock___polarity.html new file mode 100644 index 0000000..31a8b70 --- /dev/null +++ b/group___s_p_i___clock___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_Clock_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_Clock_Polarity
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_Clock_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_CPOL_Low   ((uint16_t)0x0000)
 
+#define SPI_CPOL_High   ((uint16_t)0x0002)
 
#define IS_SPI_CPOL(CPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_CPOL( CPOL)
+
+Value:
(((CPOL) == SPI_CPOL_Low) || \
+
((CPOL) == SPI_CPOL_High))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___clock___polarity.map b/group___s_p_i___clock___polarity.map new file mode 100644 index 0000000..65efb6d --- /dev/null +++ b/group___s_p_i___clock___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___clock___polarity.md5 b/group___s_p_i___clock___polarity.md5 new file mode 100644 index 0000000..ddb8f73 --- /dev/null +++ b/group___s_p_i___clock___polarity.md5 @@ -0,0 +1 @@ +bd29e5c50bcb3a78438642ad27827228 \ No newline at end of file diff --git a/group___s_p_i___clock___polarity.png b/group___s_p_i___clock___polarity.png new file mode 100644 index 0000000..abc913e Binary files /dev/null and b/group___s_p_i___clock___polarity.png differ diff --git a/group___s_p_i___exported___constants.html b/group___s_p_i___exported___constants.html new file mode 100644 index 0000000..f0437c0 --- /dev/null +++ b/group___s_p_i___exported___constants.html @@ -0,0 +1,267 @@ + + + + + + +discoverpixy: SPI_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
SPI_Exported_Constants
STM32F4xx_StdPeriph_Driver » SPI
+
+
+
+Collaboration diagram for SPI_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 SPI_data_direction
 
 SPI_mode
 
 SPI_data_size
 
 SPI_Clock_Polarity
 
 SPI_Clock_Phase
 
 SPI_Slave_Select_management
 
 SPI_BaudRate_Prescaler
 
 SPI_MSB_LSB_transmission
 
 SPI_I2S_Mode
 
 SPI_I2S_Standard
 
 SPI_I2S_Data_Format
 
 SPI_I2S_MCLK_Output
 
 SPI_I2S_Audio_Frequency
 
 SPI_I2S_Clock_Polarity
 
 SPI_I2S_DMA_transfer_requests
 
 SPI_NSS_internal_software_management
 
 SPI_CRC_Transmit_Receive
 
 SPI_direction_transmit_receive
 
 SPI_I2S_interrupts_definition
 
 SPI_I2S_flags_definition
 
 SPI_CRC_polynomial
 
 SPI_I2S_Legacy
 
+ + + + + + + + + + + +

+Macros

#define IS_SPI_ALL_PERIPH(PERIPH)
 
#define IS_SPI_ALL_PERIPH_EXT(PERIPH)
 
#define IS_SPI_23_PERIPH(PERIPH)
 
#define IS_SPI_23_PERIPH_EXT(PERIPH)
 
#define IS_I2S_EXT_PERIPH(PERIPH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_EXT_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == I2S2ext) || \
+
((PERIPH) == I2S3ext))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SPI_23_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == SPI2) || \
+
((PERIPH) == SPI3))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SPI_23_PERIPH_EXT( PERIPH)
+
+Value:
(((PERIPH) == SPI2) || \
+
((PERIPH) == SPI3) || \
+
((PERIPH) == I2S2ext) || \
+
((PERIPH) == I2S3ext))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SPI_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == SPI1) || \
+
((PERIPH) == SPI2) || \
+
((PERIPH) == SPI3) || \
+
((PERIPH) == SPI4) || \
+
((PERIPH) == SPI5) || \
+
((PERIPH) == SPI6))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SPI_ALL_PERIPH_EXT( PERIPH)
+
+Value:
(((PERIPH) == SPI1) || \
+
((PERIPH) == SPI2) || \
+
((PERIPH) == SPI3) || \
+
((PERIPH) == SPI4) || \
+
((PERIPH) == SPI5) || \
+
((PERIPH) == SPI6) || \
+
((PERIPH) == I2S2ext) || \
+
((PERIPH) == I2S3ext))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___exported___constants.map b/group___s_p_i___exported___constants.map new file mode 100644 index 0000000..59488a6 --- /dev/null +++ b/group___s_p_i___exported___constants.map @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___s_p_i___exported___constants.md5 b/group___s_p_i___exported___constants.md5 new file mode 100644 index 0000000..407ed6f --- /dev/null +++ b/group___s_p_i___exported___constants.md5 @@ -0,0 +1 @@ +1112b9aa05ce4c4760f26a36dfa49950 \ No newline at end of file diff --git a/group___s_p_i___exported___constants.png b/group___s_p_i___exported___constants.png new file mode 100644 index 0000000..e9d51da Binary files /dev/null and b/group___s_p_i___exported___constants.png differ diff --git a/group___s_p_i___group1.html b/group___s_p_i___group1.html new file mode 100644 index 0000000..050083a --- /dev/null +++ b/group___s_p_i___group1.html @@ -0,0 +1,690 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » SPI » SPI_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SPI_I2S_DeInit (SPI_TypeDef *SPIx)
 De-initialize the SPIx peripheral registers to their default reset values. More...
 
void SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct. More...
 
void I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
 Fills each SPI_InitStruct member with its default value. More...
 
void I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
 Fills each I2S_InitStruct member with its default value. More...
 
void SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral. More...
 
void I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral (in I2S mode). More...
 
void SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
 Configures the data size for the selected SPI. More...
 
void SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
 Selects the data transfer direction in bidirectional mode for the specified SPI. More...
 
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
 Configures internally by software the NSS pin for the selected SPI. More...
 
void SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SS output for the selected SPI. More...
 
void SPI_TIModeCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void I2S_FullDuplexConfig (SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
 Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+             ##### Initialization and Configuration functions ##### 
+ ===============================================================================  
+ [..] This section provides a set of functions allowing to initialize the SPI 
+      Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS 
+      Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+  
+ [..] The SPI_Init() function follows the SPI configuration procedures for Master 
+      mode and Slave mode (details for these procedures are available in reference 
+      manual (RM0090)).

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_Cmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI peripheral (in I2S mode).

+
Parameters
+ + + +
SPIxwhere x can be 2 or 3 to select the SPI peripheral (or I2Sxext for full duplex mode).
NewStatenew state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_FullDuplexConfig (SPI_TypeDef * I2Sxext,
I2S_InitTypeDef * I2S_InitStruct 
)
+
+ +

Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct.

+
Parameters
+ + + +
I2Sxextwhere x can be 2 or 3 to select the I2S peripheral extension block.
I2S_InitStructpointer to an I2S_InitTypeDef structure that contains the configuration information for the specified I2S peripheral extension.
+
+
+
Note
The structure pointed by I2S_InitStruct parameter should be the same used for the master I2S peripheral. In this case, if the master is configured as transmitter, the slave will be receiver and vice versa. Or you can force a different mode by modifying the field I2S_Mode to the value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
+
+The I2S full duplex extension can be configured in slave mode only.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void I2S_Init (SPI_TypeDef * SPIx,
I2S_InitTypeDef * I2S_InitStruct 
)
+
+ +

Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.

+
Parameters
+ + + +
SPIxwhere x can be 2 or 3 to select the SPI peripheral (configured in I2S mode).
I2S_InitStructpointer to an I2S_InitTypeDef structure that contains the configuration information for the specified SPI peripheral configured in I2S mode.
+
+
+
Note
The function calculates the optimal prescaler needed to obtain the most accurate audio frequency (depending on the I2S clock source, the PLL values and the product configuration). But in case the prescaler value is greater than 511, the default value (0x02) will be configured instead.
+
+if an external clock is used as source clock for the I2S, then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set to the value of the the source clock frequency (in Hz).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void I2S_StructInit (I2S_InitTypeDef * I2S_InitStruct)
+
+ +

Fills each I2S_InitStruct member with its default value.

+
Parameters
+ + +
I2S_InitStructpointer to a I2S_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_BiDirectionalLineConfig (SPI_TypeDef * SPIx,
uint16_t SPI_Direction 
)
+
+ +

Selects the data transfer direction in bidirectional mode for the specified SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_Directionspecifies the data transfer direction in bidirectional mode. This parameter can be one of the following values:
    +
  • SPI_Direction_Tx: Selects Tx transmission direction
    • +
  • SPI_Direction_Rx: Selects Rx receive direction
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_Cmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI peripheral.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_DataSizeConfig (SPI_TypeDef * SPIx,
uint16_t SPI_DataSize 
)
+
+ +

Configures the data size for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_DataSizespecifies the SPI data size. This parameter can be one of the following values:
    +
  • SPI_DataSize_16b: Set data frame format to 16bit
    • +
  • SPI_DataSize_8b: Set data frame format to 8bit
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_I2S_DeInit (SPI_TypeDef * SPIx)
+
+ +

De-initialize the SPIx peripheral registers to their default reset values.

+
Parameters
+ + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode.
+
+
+
Note
The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized when the relative I2S peripheral is de-initialized (the extended block's clock is managed by the I2S peripheral clock).
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_Init (SPI_TypeDef * SPIx,
SPI_InitTypeDef * SPI_InitStruct 
)
+
+ +

Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_InitStructpointer to a SPI_InitTypeDef structure that contains the configuration information for the specified SPI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef * SPIx,
uint16_t SPI_NSSInternalSoft 
)
+
+ +

Configures internally by software the NSS pin for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_NSSInternalSoftspecifies the SPI NSS internal state. This parameter can be one of the following values:
    +
  • SPI_NSSInternalSoft_Set: Set NSS pin internally
    • +
  • SPI_NSSInternalSoft_Reset: Reset NSS pin internally
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_SSOutputCmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the SS output for the selected SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx SS output. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_StructInit (SPI_InitTypeDef * SPI_InitStruct)
+
+ +

Fills each SPI_InitStruct member with its default value.

+
Parameters
+ + +
SPI_InitStructpointer to a SPI_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_TIModeCmd (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the SPIx/I2Sx DMA interface.

+
Note
This function can be called only after the SPI_Init() function has been called.
+
+When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA are not taken into consideration and are configured by hardware respectively to the TI mode requirements.
+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6
NewStatenew state of the selected SPI TI communication mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___group1.map b/group___s_p_i___group1.map new file mode 100644 index 0000000..5f57472 --- /dev/null +++ b/group___s_p_i___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___group1.md5 b/group___s_p_i___group1.md5 new file mode 100644 index 0000000..ba4fa31 --- /dev/null +++ b/group___s_p_i___group1.md5 @@ -0,0 +1 @@ +4985107b284e03e8da11ca56d3d83365 \ No newline at end of file diff --git a/group___s_p_i___group1.png b/group___s_p_i___group1.png new file mode 100644 index 0000000..2f897ce Binary files /dev/null and b/group___s_p_i___group1.png differ diff --git a/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.map b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.map new file mode 100644 index 0000000..e76c0ac --- /dev/null +++ b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.md5 b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.md5 new file mode 100644 index 0000000..4663e97 --- /dev/null +++ b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.md5 @@ -0,0 +1 @@ +bfb083ab89116dd5f0651595ba8e4cd4 \ No newline at end of file diff --git a/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.png b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.png new file mode 100644 index 0000000..412626c Binary files /dev/null and b/group___s_p_i___group1_gabe36880945fa56785283a9c0092124cc_cgraph.png differ diff --git a/group___s_p_i___group2.html b/group___s_p_i___group2.html new file mode 100644 index 0000000..d69666e --- /dev/null +++ b/group___s_p_i___group2.html @@ -0,0 +1,200 @@ + + + + + + +discoverpixy: Data transfers functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Data transfers functions
STM32F4xx_StdPeriph_Driver » SPI » SPI_Private_Functions
+
+
+ +

Data transfers functions. +More...

+
+Collaboration diagram for Data transfers functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

uint16_t SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
 Returns the most recent received data by the SPIx/I2Sx peripheral. More...
 
void SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
 Transmits a Data through the SPIx/I2Sx peripheral. More...
 
+

Detailed Description

+

Data transfers functions.

+
 ===============================================================================
+                      ##### Data transfers functions #####
+ ===============================================================================  
+
+ [..] This section provides a set of functions allowing to manage the SPI data 
+      transfers. In reception, data are received and then stored into an internal 
+      Rx buffer while. In transmission, data are first stored into an internal Tx 
+      buffer before being transmitted.
+
+ [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
+      function and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+      can be done using SPI_I2S_SendData() function and stores the written data into 
+      Tx buffer.

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t SPI_I2S_ReceiveData (SPI_TypeDef * SPIx)
+
+ +

Returns the most recent received data by the SPIx/I2Sx peripheral.

+
Parameters
+ + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
+
+
+
Return values
+ + +
Thevalue of the received data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_SendData (SPI_TypeDef * SPIx,
uint16_t Data 
)
+
+ +

Transmits a Data through the SPIx/I2Sx peripheral.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
DataData to be transmitted.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___group2.map b/group___s_p_i___group2.map new file mode 100644 index 0000000..8138f06 --- /dev/null +++ b/group___s_p_i___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___group2.md5 b/group___s_p_i___group2.md5 new file mode 100644 index 0000000..20576f8 --- /dev/null +++ b/group___s_p_i___group2.md5 @@ -0,0 +1 @@ +5b58cd99305983d850806fd90102563a \ No newline at end of file diff --git a/group___s_p_i___group2.png b/group___s_p_i___group2.png new file mode 100644 index 0000000..65705f2 Binary files /dev/null and b/group___s_p_i___group2.png differ diff --git a/group___s_p_i___group3.html b/group___s_p_i___group3.html new file mode 100644 index 0000000..879e212 --- /dev/null +++ b/group___s_p_i___group3.html @@ -0,0 +1,329 @@ + + + + + + +discoverpixy: Hardware CRC Calculation functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Hardware CRC Calculation functions
STM32F4xx_StdPeriph_Driver » SPI » SPI_Private_Functions
+
+
+ +

Hardware CRC Calculation functions. +More...

+
+Collaboration diagram for Hardware CRC Calculation functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the CRC value calculation of the transferred bytes. More...
 
void SPI_TransmitCRC (SPI_TypeDef *SPIx)
 Transmit the SPIx CRC value. More...
 
uint16_t SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
 Returns the transmit or the receive CRC register value for the specified SPI. More...
 
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
 Returns the CRC Polynomial register value for the specified SPI. More...
 
+

Detailed Description

+

Hardware CRC Calculation functions.

+
 ===============================================================================
+                 ##### Hardware CRC Calculation functions #####
+ ===============================================================================  
+
+ [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
+      calculation
+
+ [..] SPI communication using CRC is possible through the following procedure:
+   (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+       Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+       function.
+   (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
+   (#) Enable the SPI using the SPI_Cmd() function
+   (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
+       SPI_TransmitCRC() function to indicate that after transmission of the last 
+       data, the CRC should be transmitted.
+   (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+        bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+        value. 
+        If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+        can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+
+ [..]
+   (@) It is advised not to read the calculated CRC values during the communication.
+
+   (@) When the SPI is in slave mode, be careful to enable CRC calculation only 
+       when the clock is stable, that is, when the clock is in the steady state. 
+       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+       to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+       the value of the SPE bit.
+
+   (@) With high bitrate frequencies, be careful when transmitting the CRC.
+       As the number of used CPU cycles has to be as low as possible in the CRC 
+       transfer phase, it is forbidden to call software functions in the CRC 
+       transmission sequence to avoid errors in the last data and CRC reception. 
+       In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+       of the last data.
+
+   (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+       degradation of the SPI speed performance due to CPU accesses impacting the 
+       SPI bandwidth.
+
+   (@) When the STM32F4xx is configured as slave and the NSS hardware mode is 
+       used, the NSS pin needs to be kept low between the data phase and the CRC 
+       phase.
+
+   (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
+       calculation takes place even if a high level is applied on the NSS pin. 
+       This may happen for example in case of a multi-slave environment where the 
+       communication master addresses slaves alternately.
+
+   (@) Between a slave de-selection (high level on NSS) and a new slave selection 
+       (low level on NSS), the CRC value should be cleared on both master and slave
+       sides in order to resynchronize the master and slave for their respective 
+       CRC calculation.
+
+   (@) To clear the CRC, follow the procedure below:
+       (#@) Disable SPI using the SPI_Cmd() function
+       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
+       (#@) Enable SPI using the SPI_Cmd() function.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_CalculateCRC (SPI_TypeDef * SPIx,
FunctionalState NewState 
)
+
+ +

Enables or disables the CRC value calculation of the transferred bytes.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
NewStatenew state of the SPIx CRC value calculation. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t SPI_GetCRC (SPI_TypeDef * SPIx,
uint8_t SPI_CRC 
)
+
+ +

Returns the transmit or the receive CRC register value for the specified SPI.

+
Parameters
+ + + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
SPI_CRCspecifies the CRC register to be read. This parameter can be one of the following values:
    +
  • SPI_CRC_Tx: Selects Tx CRC register
    • +
  • SPI_CRC_Rx: Selects Rx CRC register
    • +
+
+
+
+
Return values
+ + +
Theselected CRC register value..
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef * SPIx)
+
+ +

Returns the CRC Polynomial register value for the specified SPI.

+
Parameters
+ + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+
+
+
Return values
+ + +
TheCRC Polynomial register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SPI_TransmitCRC (SPI_TypeDef * SPIx)
+
+ +

Transmit the SPIx CRC value.

+
Parameters
+ + +
SPIxwhere x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___group3.map b/group___s_p_i___group3.map new file mode 100644 index 0000000..476871d --- /dev/null +++ b/group___s_p_i___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___group3.md5 b/group___s_p_i___group3.md5 new file mode 100644 index 0000000..3637f36 --- /dev/null +++ b/group___s_p_i___group3.md5 @@ -0,0 +1 @@ +274bff93647eb4fb730241810e48a460 \ No newline at end of file diff --git a/group___s_p_i___group3.png b/group___s_p_i___group3.png new file mode 100644 index 0000000..d038b75 Binary files /dev/null and b/group___s_p_i___group3.png differ diff --git a/group___s_p_i___group4.html b/group___s_p_i___group4.html new file mode 100644 index 0000000..c771c90 --- /dev/null +++ b/group___s_p_i___group4.html @@ -0,0 +1,168 @@ + + + + + + +discoverpixy: DMA transfers management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DMA transfers management functions
STM32F4xx_StdPeriph_Driver » SPI » SPI_Private_Functions
+
+
+ +

DMA transfers management functions. +More...

+
+Collaboration diagram for DMA transfers management functions:
+
+
+ + +
+
+ + + + + +

+Functions

void SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
+

Detailed Description

+

DMA transfers management functions.

+
 ===============================================================================
+                   ##### DMA transfers management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SPI_I2S_DMACmd (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the SPIx/I2Sx DMA interface.

+
Parameters
+ + + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_DMAReqspecifies the SPI DMA transfer request to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
    • +
  • SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
    • +
+
NewStatenew state of the selected SPI DMA transfer request. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___group4.map b/group___s_p_i___group4.map new file mode 100644 index 0000000..0a3a8f1 --- /dev/null +++ b/group___s_p_i___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___group4.md5 b/group___s_p_i___group4.md5 new file mode 100644 index 0000000..0bc4fe1 --- /dev/null +++ b/group___s_p_i___group4.md5 @@ -0,0 +1 @@ +9c5fef19b52023c5941df6ea7cf621d9 \ No newline at end of file diff --git a/group___s_p_i___group4.png b/group___s_p_i___group4.png new file mode 100644 index 0000000..f3a3a0d Binary files /dev/null and b/group___s_p_i___group4.png differ diff --git a/group___s_p_i___group5.html b/group___s_p_i___group5.html new file mode 100644 index 0000000..a1d0ea3 --- /dev/null +++ b/group___s_p_i___group5.html @@ -0,0 +1,441 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » SPI » SPI_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
 Enables or disables the specified SPI/I2S interrupts. More...
 
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Checks whether the specified SPIx/I2Sx flag is set or not. More...
 
void SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Clears the SPIx CRC Error (CRCERR) flag. More...
 
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Checks whether the specified SPIx/I2Sx interrupt has occurred or not. More...
 
void SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Clears the SPIx CRC Error (CRCERR) interrupt pending bit. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+ 
+ [..] This section provides a set of functions allowing to configure the SPI Interrupts 
+      sources and check or clear the flags or pending bits status.
+      The user should identify which mode will be used in his application to manage 
+      the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+ *** Polling Mode ***
+ ====================
+[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+  (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
+  (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
+  (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+  (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
+  (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
+  (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
+  (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
+  (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
+  (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
+
+  (@) Do not use the BSY flag to handle each data transmission or reception. It is
+      better to use the TXE and RXNE flags instead.
+
+ [..] In this Mode it is advised to use the following functions:
+   (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+   (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+ *** Interrupt Mode ***
+ ======================
+ [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
+      and 7 pending bits: 
+   (+) Pending Bits:
+       (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
+       (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
+       (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)            
+       (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
+       (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
+       (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
+       (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
+
+   (+) Interrupt Source:
+       (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+            interrupt.  
+       (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+            empty interrupt.
+       (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+
+ [..] In this Mode it is advised to use the following functions:
+   (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+   (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+   (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+ *** DMA Mode ***
+ ================
+ [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
+   (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+   (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+
+ [..] In this Mode it is advised to use the following function:
+   (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState 
+       NewState);

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_ClearFlag (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_FLAG 
)
+
+ +

Clears the SPIx CRC Error (CRCERR) flag.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_FLAGspecifies the SPI flag to clear. This function clears only CRCERR flag.
    +
  • SPI_FLAG_CRCERR: CRC Error flag.
    • +
+
+
+
+
Note
OVR (OverRun error) flag is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+
+UDR (UnderRun error) flag is cleared by a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+
+MODF (Mode Fault) flag is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SPI_I2S_ClearITPendingBit (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT 
)
+
+ +

Clears the SPIx CRC Error (CRCERR) interrupt pending bit.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt pending bit to clear. This function clears only CRCERR interrupt pending bit.
    +
  • SPI_IT_CRCERR: CRC Error interrupt.
    • +
+
+
+
+
Note
OVR (OverRun Error) interrupt pending bit is cleared by software sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+
+UDR (UnderRun Error) interrupt pending bit is cleared by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+
+MODF (Mode Fault) interrupt pending bit is cleared by software sequence: a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef * SPIx,
uint16_t SPI_I2S_FLAG 
)
+
+ +

Checks whether the specified SPIx/I2Sx flag is set or not.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_FLAGspecifies the SPI flag to check. This parameter can be one of the following values:
    +
  • SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
    • +
  • SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
    • +
  • SPI_I2S_FLAG_BSY: Busy flag.
    • +
  • SPI_I2S_FLAG_OVR: Overrun flag.
    • +
  • SPI_FLAG_MODF: Mode Fault flag.
    • +
  • SPI_FLAG_CRCERR: CRC Error flag.
    • +
  • SPI_I2S_FLAG_TIFRFE: Format Error.
    • +
  • I2S_FLAG_UDR: Underrun Error flag.
    • +
  • I2S_FLAG_CHSIDE: Channel Side flag.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SPI_I2S_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT 
)
+
+ +

Checks whether the specified SPIx/I2Sx interrupt has occurred or not.

+
Parameters
+ + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt source to check. This parameter can be one of the following values:
    +
  • SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
    • +
  • SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
    • +
  • SPI_I2S_IT_OVR: Overrun interrupt.
    • +
  • SPI_IT_MODF: Mode Fault interrupt.
    • +
  • SPI_IT_CRCERR: CRC Error interrupt.
    • +
  • I2S_IT_UDR: Underrun interrupt.
    • +
  • SPI_I2S_IT_TIFRFE: Format Error interrupt.
    • +
+
+
+
+
Return values
+ + +
Thenew state of SPI_I2S_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void SPI_I2S_ITConfig (SPI_TypeDef * SPIx,
uint8_t SPI_I2S_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified SPI/I2S interrupts.

+
Parameters
+ + + + +
SPIxTo select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
SPI_I2S_ITspecifies the SPI interrupt source to be enabled or disabled. This parameter can be one of the following values:
    +
  • SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
    • +
  • SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
    • +
  • SPI_I2S_IT_ERR: Error interrupt mask
    • +
+
NewStatenew state of the specified SPI interrupt. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___group5.map b/group___s_p_i___group5.map new file mode 100644 index 0000000..c5d8030 --- /dev/null +++ b/group___s_p_i___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___group5.md5 b/group___s_p_i___group5.md5 new file mode 100644 index 0000000..2902019 --- /dev/null +++ b/group___s_p_i___group5.md5 @@ -0,0 +1 @@ +000a89bc5cfa5188368f227133acd0b1 \ No newline at end of file diff --git a/group___s_p_i___group5.png b/group___s_p_i___group5.png new file mode 100644 index 0000000..9ae060f Binary files /dev/null and b/group___s_p_i___group5.png differ diff --git a/group___s_p_i___i2_s___audio___frequency.html b/group___s_p_i___i2_s___audio___frequency.html new file mode 100644 index 0000000..0b583a1 --- /dev/null +++ b/group___s_p_i___i2_s___audio___frequency.html @@ -0,0 +1,158 @@ + + + + + + +discoverpixy: SPI_I2S_Audio_Frequency + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Audio_Frequency
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Audio_Frequency:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define I2S_AudioFreq_192k   ((uint32_t)192000)
 
+#define I2S_AudioFreq_96k   ((uint32_t)96000)
 
+#define I2S_AudioFreq_48k   ((uint32_t)48000)
 
+#define I2S_AudioFreq_44k   ((uint32_t)44100)
 
+#define I2S_AudioFreq_32k   ((uint32_t)32000)
 
+#define I2S_AudioFreq_22k   ((uint32_t)22050)
 
+#define I2S_AudioFreq_16k   ((uint32_t)16000)
 
+#define I2S_AudioFreq_11k   ((uint32_t)11025)
 
+#define I2S_AudioFreq_8k   ((uint32_t)8000)
 
+#define I2S_AudioFreq_Default   ((uint32_t)2)
 
#define IS_I2S_AUDIO_FREQ(FREQ)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_AUDIO_FREQ( FREQ)
+
+Value:
((((FREQ) >= I2S_AudioFreq_8k) && \
+
((FREQ) <= I2S_AudioFreq_192k)) || \
+
((FREQ) == I2S_AudioFreq_Default))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___audio___frequency.map b/group___s_p_i___i2_s___audio___frequency.map new file mode 100644 index 0000000..57fcc6a --- /dev/null +++ b/group___s_p_i___i2_s___audio___frequency.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___audio___frequency.md5 b/group___s_p_i___i2_s___audio___frequency.md5 new file mode 100644 index 0000000..2b813f3 --- /dev/null +++ b/group___s_p_i___i2_s___audio___frequency.md5 @@ -0,0 +1 @@ +989198b7dc05869ff76ae2b473a7b33d \ No newline at end of file diff --git a/group___s_p_i___i2_s___audio___frequency.png b/group___s_p_i___i2_s___audio___frequency.png new file mode 100644 index 0000000..e3b81d0 Binary files /dev/null and b/group___s_p_i___i2_s___audio___frequency.png differ diff --git a/group___s_p_i___i2_s___clock___polarity.html b/group___s_p_i___i2_s___clock___polarity.html new file mode 100644 index 0000000..c2bb478 --- /dev/null +++ b/group___s_p_i___i2_s___clock___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_I2S_Clock_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Clock_Polarity
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Clock_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2S_CPOL_Low   ((uint16_t)0x0000)
 
+#define I2S_CPOL_High   ((uint16_t)0x0008)
 
#define IS_I2S_CPOL(CPOL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_CPOL( CPOL)
+
+Value:
(((CPOL) == I2S_CPOL_Low) || \
+
((CPOL) == I2S_CPOL_High))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___clock___polarity.map b/group___s_p_i___i2_s___clock___polarity.map new file mode 100644 index 0000000..9d79cf8 --- /dev/null +++ b/group___s_p_i___i2_s___clock___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___clock___polarity.md5 b/group___s_p_i___i2_s___clock___polarity.md5 new file mode 100644 index 0000000..1b5b262 --- /dev/null +++ b/group___s_p_i___i2_s___clock___polarity.md5 @@ -0,0 +1 @@ +2c1aea23ba9a34330569cf6d31ffc37b \ No newline at end of file diff --git a/group___s_p_i___i2_s___clock___polarity.png b/group___s_p_i___i2_s___clock___polarity.png new file mode 100644 index 0000000..ec2e1ce Binary files /dev/null and b/group___s_p_i___i2_s___clock___polarity.png differ diff --git a/group___s_p_i___i2_s___d_m_a__transfer__requests.html b/group___s_p_i___i2_s___d_m_a__transfer__requests.html new file mode 100644 index 0000000..364edbe --- /dev/null +++ b/group___s_p_i___i2_s___d_m_a__transfer__requests.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: SPI_I2S_DMA_transfer_requests + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_DMA_transfer_requests
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_DMA_transfer_requests:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_I2S_DMAReq_Tx   ((uint16_t)0x0002)
 
+#define SPI_I2S_DMAReq_Rx   ((uint16_t)0x0001)
 
+#define IS_SPI_I2S_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___d_m_a__transfer__requests.map b/group___s_p_i___i2_s___d_m_a__transfer__requests.map new file mode 100644 index 0000000..4ea8f5f --- /dev/null +++ b/group___s_p_i___i2_s___d_m_a__transfer__requests.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___d_m_a__transfer__requests.md5 b/group___s_p_i___i2_s___d_m_a__transfer__requests.md5 new file mode 100644 index 0000000..5e0850e --- /dev/null +++ b/group___s_p_i___i2_s___d_m_a__transfer__requests.md5 @@ -0,0 +1 @@ +ac8bbc6b7e74a7a8c34edbd1bb4c5d01 \ No newline at end of file diff --git a/group___s_p_i___i2_s___d_m_a__transfer__requests.png b/group___s_p_i___i2_s___d_m_a__transfer__requests.png new file mode 100644 index 0000000..90fe5e2 Binary files /dev/null and b/group___s_p_i___i2_s___d_m_a__transfer__requests.png differ diff --git a/group___s_p_i___i2_s___data___format.html b/group___s_p_i___i2_s___data___format.html new file mode 100644 index 0000000..1646864 --- /dev/null +++ b/group___s_p_i___i2_s___data___format.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: SPI_I2S_Data_Format + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Data_Format
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Data_Format:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define I2S_DataFormat_16b   ((uint16_t)0x0000)
 
+#define I2S_DataFormat_16bextended   ((uint16_t)0x0001)
 
+#define I2S_DataFormat_24b   ((uint16_t)0x0003)
 
+#define I2S_DataFormat_32b   ((uint16_t)0x0005)
 
#define IS_I2S_DATA_FORMAT(FORMAT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_DATA_FORMAT( FORMAT)
+
+Value:
(((FORMAT) == I2S_DataFormat_16b) || \
+
((FORMAT) == I2S_DataFormat_16bextended) || \
+
((FORMAT) == I2S_DataFormat_24b) || \
+
((FORMAT) == I2S_DataFormat_32b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___data___format.map b/group___s_p_i___i2_s___data___format.map new file mode 100644 index 0000000..ce37204 --- /dev/null +++ b/group___s_p_i___i2_s___data___format.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___data___format.md5 b/group___s_p_i___i2_s___data___format.md5 new file mode 100644 index 0000000..c36d03b --- /dev/null +++ b/group___s_p_i___i2_s___data___format.md5 @@ -0,0 +1 @@ +7942b91b40b3c8e9c025f1bee598300b \ No newline at end of file diff --git a/group___s_p_i___i2_s___data___format.png b/group___s_p_i___i2_s___data___format.png new file mode 100644 index 0000000..17843ce Binary files /dev/null and b/group___s_p_i___i2_s___data___format.png differ diff --git a/group___s_p_i___i2_s___legacy.html b/group___s_p_i___i2_s___legacy.html new file mode 100644 index 0000000..8e9a11d --- /dev/null +++ b/group___s_p_i___i2_s___legacy.html @@ -0,0 +1,163 @@ + + + + + + +discoverpixy: SPI_I2S_Legacy + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Legacy
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Legacy:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SPI_DMAReq_Tx   SPI_I2S_DMAReq_Tx
 
+#define SPI_DMAReq_Rx   SPI_I2S_DMAReq_Rx
 
+#define SPI_IT_TXE   SPI_I2S_IT_TXE
 
+#define SPI_IT_RXNE   SPI_I2S_IT_RXNE
 
+#define SPI_IT_ERR   SPI_I2S_IT_ERR
 
+#define SPI_IT_OVR   SPI_I2S_IT_OVR
 
+#define SPI_FLAG_RXNE   SPI_I2S_FLAG_RXNE
 
+#define SPI_FLAG_TXE   SPI_I2S_FLAG_TXE
 
+#define SPI_FLAG_OVR   SPI_I2S_FLAG_OVR
 
+#define SPI_FLAG_BSY   SPI_I2S_FLAG_BSY
 
+#define SPI_DeInit   SPI_I2S_DeInit
 
+#define SPI_ITConfig   SPI_I2S_ITConfig
 
+#define SPI_DMACmd   SPI_I2S_DMACmd
 
+#define SPI_SendData   SPI_I2S_SendData
 
+#define SPI_ReceiveData   SPI_I2S_ReceiveData
 
+#define SPI_GetFlagStatus   SPI_I2S_GetFlagStatus
 
+#define SPI_ClearFlag   SPI_I2S_ClearFlag
 
+#define SPI_GetITStatus   SPI_I2S_GetITStatus
 
+#define SPI_ClearITPendingBit   SPI_I2S_ClearITPendingBit
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___legacy.map b/group___s_p_i___i2_s___legacy.map new file mode 100644 index 0000000..95b880a --- /dev/null +++ b/group___s_p_i___i2_s___legacy.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___legacy.md5 b/group___s_p_i___i2_s___legacy.md5 new file mode 100644 index 0000000..c624213 --- /dev/null +++ b/group___s_p_i___i2_s___legacy.md5 @@ -0,0 +1 @@ +bf5370b6a19923c16ef34f00720c605c \ No newline at end of file diff --git a/group___s_p_i___i2_s___legacy.png b/group___s_p_i___i2_s___legacy.png new file mode 100644 index 0000000..ee9e84c Binary files /dev/null and b/group___s_p_i___i2_s___legacy.png differ diff --git a/group___s_p_i___i2_s___m_c_l_k___output.html b/group___s_p_i___i2_s___m_c_l_k___output.html new file mode 100644 index 0000000..00ca695 --- /dev/null +++ b/group___s_p_i___i2_s___m_c_l_k___output.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_I2S_MCLK_Output + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_MCLK_Output
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_MCLK_Output:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define I2S_MCLKOutput_Enable   ((uint16_t)0x0200)
 
+#define I2S_MCLKOutput_Disable   ((uint16_t)0x0000)
 
#define IS_I2S_MCLK_OUTPUT(OUTPUT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_MCLK_OUTPUT( OUTPUT)
+
+Value:
(((OUTPUT) == I2S_MCLKOutput_Enable) || \
+
((OUTPUT) == I2S_MCLKOutput_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___m_c_l_k___output.map b/group___s_p_i___i2_s___m_c_l_k___output.map new file mode 100644 index 0000000..b30fbc3 --- /dev/null +++ b/group___s_p_i___i2_s___m_c_l_k___output.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___m_c_l_k___output.md5 b/group___s_p_i___i2_s___m_c_l_k___output.md5 new file mode 100644 index 0000000..02dc041 --- /dev/null +++ b/group___s_p_i___i2_s___m_c_l_k___output.md5 @@ -0,0 +1 @@ +0d3d2c709ef418f2ea4a3f7c0b6d2e31 \ No newline at end of file diff --git a/group___s_p_i___i2_s___m_c_l_k___output.png b/group___s_p_i___i2_s___m_c_l_k___output.png new file mode 100644 index 0000000..2bfab99 Binary files /dev/null and b/group___s_p_i___i2_s___m_c_l_k___output.png differ diff --git a/group___s_p_i___i2_s___mode.html b/group___s_p_i___i2_s___mode.html new file mode 100644 index 0000000..7870ea4 --- /dev/null +++ b/group___s_p_i___i2_s___mode.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: SPI_I2S_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Mode
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define I2S_Mode_SlaveTx   ((uint16_t)0x0000)
 
+#define I2S_Mode_SlaveRx   ((uint16_t)0x0100)
 
+#define I2S_Mode_MasterTx   ((uint16_t)0x0200)
 
+#define I2S_Mode_MasterRx   ((uint16_t)0x0300)
 
#define IS_I2S_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_MODE( MODE)
+
+Value:
(((MODE) == I2S_Mode_SlaveTx) || \
+
((MODE) == I2S_Mode_SlaveRx) || \
+
((MODE) == I2S_Mode_MasterTx)|| \
+
((MODE) == I2S_Mode_MasterRx))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___mode.map b/group___s_p_i___i2_s___mode.map new file mode 100644 index 0000000..1985d40 --- /dev/null +++ b/group___s_p_i___i2_s___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___mode.md5 b/group___s_p_i___i2_s___mode.md5 new file mode 100644 index 0000000..a47948d --- /dev/null +++ b/group___s_p_i___i2_s___mode.md5 @@ -0,0 +1 @@ +ebf90f13ef3647bf8c84288c206c5493 \ No newline at end of file diff --git a/group___s_p_i___i2_s___mode.png b/group___s_p_i___i2_s___mode.png new file mode 100644 index 0000000..4fb591b Binary files /dev/null and b/group___s_p_i___i2_s___mode.png differ diff --git a/group___s_p_i___i2_s___standard.html b/group___s_p_i___i2_s___standard.html new file mode 100644 index 0000000..feffe08 --- /dev/null +++ b/group___s_p_i___i2_s___standard.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: SPI_I2S_Standard + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_Standard
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_Standard:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define I2S_Standard_Phillips   ((uint16_t)0x0000)
 
+#define I2S_Standard_MSB   ((uint16_t)0x0010)
 
+#define I2S_Standard_LSB   ((uint16_t)0x0020)
 
+#define I2S_Standard_PCMShort   ((uint16_t)0x0030)
 
+#define I2S_Standard_PCMLong   ((uint16_t)0x00B0)
 
#define IS_I2S_STANDARD(STANDARD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_I2S_STANDARD( STANDARD)
+
+Value:
(((STANDARD) == I2S_Standard_Phillips) || \
+
((STANDARD) == I2S_Standard_MSB) || \
+
((STANDARD) == I2S_Standard_LSB) || \
+
((STANDARD) == I2S_Standard_PCMShort) || \
+
((STANDARD) == I2S_Standard_PCMLong))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s___standard.map b/group___s_p_i___i2_s___standard.map new file mode 100644 index 0000000..e81f1f6 --- /dev/null +++ b/group___s_p_i___i2_s___standard.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s___standard.md5 b/group___s_p_i___i2_s___standard.md5 new file mode 100644 index 0000000..98923dc --- /dev/null +++ b/group___s_p_i___i2_s___standard.md5 @@ -0,0 +1 @@ +57aad7801d1070f9c8b061f041809e82 \ No newline at end of file diff --git a/group___s_p_i___i2_s___standard.png b/group___s_p_i___i2_s___standard.png new file mode 100644 index 0000000..bd80649 Binary files /dev/null and b/group___s_p_i___i2_s___standard.png differ diff --git a/group___s_p_i___i2_s__flags__definition.html b/group___s_p_i___i2_s__flags__definition.html new file mode 100644 index 0000000..8ffad16 --- /dev/null +++ b/group___s_p_i___i2_s__flags__definition.html @@ -0,0 +1,160 @@ + + + + + + +discoverpixy: SPI_I2S_flags_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_flags_definition
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_flags_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SPI_I2S_FLAG_RXNE   ((uint16_t)0x0001)
 
+#define SPI_I2S_FLAG_TXE   ((uint16_t)0x0002)
 
+#define I2S_FLAG_CHSIDE   ((uint16_t)0x0004)
 
+#define I2S_FLAG_UDR   ((uint16_t)0x0008)
 
+#define SPI_FLAG_CRCERR   ((uint16_t)0x0010)
 
+#define SPI_FLAG_MODF   ((uint16_t)0x0020)
 
+#define SPI_I2S_FLAG_OVR   ((uint16_t)0x0040)
 
+#define SPI_I2S_FLAG_BSY   ((uint16_t)0x0080)
 
+#define SPI_I2S_FLAG_TIFRFE   ((uint16_t)0x0100)
 
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG)   (((FLAG) == SPI_FLAG_CRCERR))
 
#define IS_SPI_I2S_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_I2S_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+
((FLAG) == SPI_I2S_FLAG_TIFRFE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s__flags__definition.map b/group___s_p_i___i2_s__flags__definition.map new file mode 100644 index 0000000..d51ff5e --- /dev/null +++ b/group___s_p_i___i2_s__flags__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s__flags__definition.md5 b/group___s_p_i___i2_s__flags__definition.md5 new file mode 100644 index 0000000..522b2c9 --- /dev/null +++ b/group___s_p_i___i2_s__flags__definition.md5 @@ -0,0 +1 @@ +1a9e73578f1376ea37d046d82ca8b9d4 \ No newline at end of file diff --git a/group___s_p_i___i2_s__flags__definition.png b/group___s_p_i___i2_s__flags__definition.png new file mode 100644 index 0000000..230779d Binary files /dev/null and b/group___s_p_i___i2_s__flags__definition.png differ diff --git a/group___s_p_i___i2_s__interrupts__definition.html b/group___s_p_i___i2_s__interrupts__definition.html new file mode 100644 index 0000000..4cb7b33 --- /dev/null +++ b/group___s_p_i___i2_s__interrupts__definition.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: SPI_I2S_interrupts_definition + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_I2S_interrupts_definition
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_I2S_interrupts_definition:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SPI_I2S_IT_TXE   ((uint8_t)0x71)
 
+#define SPI_I2S_IT_RXNE   ((uint8_t)0x60)
 
+#define SPI_I2S_IT_ERR   ((uint8_t)0x50)
 
+#define I2S_IT_UDR   ((uint8_t)0x53)
 
+#define SPI_I2S_IT_TIFRFE   ((uint8_t)0x58)
 
#define IS_SPI_I2S_CONFIG_IT(IT)
 
+#define SPI_I2S_IT_OVR   ((uint8_t)0x56)
 
+#define SPI_IT_MODF   ((uint8_t)0x55)
 
+#define SPI_IT_CRCERR   ((uint8_t)0x54)
 
+#define IS_SPI_I2S_CLEAR_IT(IT)   (((IT) == SPI_IT_CRCERR))
 
#define IS_SPI_I2S_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_I2S_CONFIG_IT( IT)
+
+Value:
(((IT) == SPI_I2S_IT_TXE) || \
+
((IT) == SPI_I2S_IT_RXNE) || \
+
((IT) == SPI_I2S_IT_ERR))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_SPI_I2S_GET_IT( IT)
+
+Value:
(((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
+
((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
+
((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
+
((IT) == SPI_I2S_IT_TIFRFE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___i2_s__interrupts__definition.map b/group___s_p_i___i2_s__interrupts__definition.map new file mode 100644 index 0000000..01172c8 --- /dev/null +++ b/group___s_p_i___i2_s__interrupts__definition.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___i2_s__interrupts__definition.md5 b/group___s_p_i___i2_s__interrupts__definition.md5 new file mode 100644 index 0000000..b18bf8e --- /dev/null +++ b/group___s_p_i___i2_s__interrupts__definition.md5 @@ -0,0 +1 @@ +f20c64c7baa326b840b7286d9a41122c \ No newline at end of file diff --git a/group___s_p_i___i2_s__interrupts__definition.png b/group___s_p_i___i2_s__interrupts__definition.png new file mode 100644 index 0000000..45f7bf0 Binary files /dev/null and b/group___s_p_i___i2_s__interrupts__definition.png differ diff --git a/group___s_p_i___m_s_b___l_s_b__transmission.html b/group___s_p_i___m_s_b___l_s_b__transmission.html new file mode 100644 index 0000000..5be93a6 --- /dev/null +++ b/group___s_p_i___m_s_b___l_s_b__transmission.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_MSB_LSB_transmission + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_MSB_LSB_transmission
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_MSB_LSB_transmission:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_FirstBit_MSB   ((uint16_t)0x0000)
 
+#define SPI_FirstBit_LSB   ((uint16_t)0x0080)
 
#define IS_SPI_FIRST_BIT(BIT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_FIRST_BIT( BIT)
+
+Value:
(((BIT) == SPI_FirstBit_MSB) || \
+
((BIT) == SPI_FirstBit_LSB))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___m_s_b___l_s_b__transmission.map b/group___s_p_i___m_s_b___l_s_b__transmission.map new file mode 100644 index 0000000..dea9ed4 --- /dev/null +++ b/group___s_p_i___m_s_b___l_s_b__transmission.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___m_s_b___l_s_b__transmission.md5 b/group___s_p_i___m_s_b___l_s_b__transmission.md5 new file mode 100644 index 0000000..ad7e20a --- /dev/null +++ b/group___s_p_i___m_s_b___l_s_b__transmission.md5 @@ -0,0 +1 @@ +2f22ff4067d0dc15e0b90d3bc70e8a33 \ No newline at end of file diff --git a/group___s_p_i___m_s_b___l_s_b__transmission.png b/group___s_p_i___m_s_b___l_s_b__transmission.png new file mode 100644 index 0000000..8f57661 Binary files /dev/null and b/group___s_p_i___m_s_b___l_s_b__transmission.png differ diff --git a/group___s_p_i___n_s_s__internal__software__management.html b/group___s_p_i___n_s_s__internal__software__management.html new file mode 100644 index 0000000..43c99fb --- /dev/null +++ b/group___s_p_i___n_s_s__internal__software__management.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_NSS_internal_software_management + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_NSS_internal_software_management
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_NSS_internal_software_management:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_NSSInternalSoft_Set   ((uint16_t)0x0100)
 
+#define SPI_NSSInternalSoft_Reset   ((uint16_t)0xFEFF)
 
#define IS_SPI_NSS_INTERNAL(INTERNAL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_NSS_INTERNAL( INTERNAL)
+
+Value:
(((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+
((INTERNAL) == SPI_NSSInternalSoft_Reset))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___n_s_s__internal__software__management.map b/group___s_p_i___n_s_s__internal__software__management.map new file mode 100644 index 0000000..99a92c4 --- /dev/null +++ b/group___s_p_i___n_s_s__internal__software__management.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___n_s_s__internal__software__management.md5 b/group___s_p_i___n_s_s__internal__software__management.md5 new file mode 100644 index 0000000..5cc27f1 --- /dev/null +++ b/group___s_p_i___n_s_s__internal__software__management.md5 @@ -0,0 +1 @@ +e2ec9a92b56bcc963f853de5d9812ed9 \ No newline at end of file diff --git a/group___s_p_i___n_s_s__internal__software__management.png b/group___s_p_i___n_s_s__internal__software__management.png new file mode 100644 index 0000000..a905266 Binary files /dev/null and b/group___s_p_i___n_s_s__internal__software__management.png differ diff --git a/group___s_p_i___private___functions.html b/group___s_p_i___private___functions.html new file mode 100644 index 0000000..ea5fadf --- /dev/null +++ b/group___s_p_i___private___functions.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: SPI_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
SPI_Private_Functions
STM32F4xx_StdPeriph_Driver » SPI
+
+
+
+Collaboration diagram for SPI_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Data transfers functions
 Data transfers functions.
 
 Hardware CRC Calculation functions
 Hardware CRC Calculation functions.
 
 DMA transfers management functions
 DMA transfers management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___private___functions.map b/group___s_p_i___private___functions.map new file mode 100644 index 0000000..8bc622d --- /dev/null +++ b/group___s_p_i___private___functions.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___s_p_i___private___functions.md5 b/group___s_p_i___private___functions.md5 new file mode 100644 index 0000000..b399395 --- /dev/null +++ b/group___s_p_i___private___functions.md5 @@ -0,0 +1 @@ +8613d867b6a4e93ffdb1a8697b62c158 \ No newline at end of file diff --git a/group___s_p_i___private___functions.png b/group___s_p_i___private___functions.png new file mode 100644 index 0000000..c6e71bb Binary files /dev/null and b/group___s_p_i___private___functions.png differ diff --git a/group___s_p_i___serial___interface___mode__selection.html b/group___s_p_i___serial___interface___mode__selection.html new file mode 100644 index 0000000..f4a64ff --- /dev/null +++ b/group___s_p_i___serial___interface___mode__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: SPI_Serial_Interface_Mode_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_Serial_Interface_Mode_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for SPI_Serial_Interface_Mode_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_SERIALINTERFACE_4WIRE   ((uint8_t)0x00)
 
+#define LIS302DL_SERIALINTERFACE_3WIRE   ((uint8_t)0x80)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___serial___interface___mode__selection.map b/group___s_p_i___serial___interface___mode__selection.map new file mode 100644 index 0000000..e2110bc --- /dev/null +++ b/group___s_p_i___serial___interface___mode__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___serial___interface___mode__selection.md5 b/group___s_p_i___serial___interface___mode__selection.md5 new file mode 100644 index 0000000..8438ca8 --- /dev/null +++ b/group___s_p_i___serial___interface___mode__selection.md5 @@ -0,0 +1 @@ +31e52472f8321196548edcbdbf822ba3 \ No newline at end of file diff --git a/group___s_p_i___serial___interface___mode__selection.png b/group___s_p_i___serial___interface___mode__selection.png new file mode 100644 index 0000000..38c4e60 Binary files /dev/null and b/group___s_p_i___serial___interface___mode__selection.png differ diff --git a/group___s_p_i___slave___select__management.html b/group___s_p_i___slave___select__management.html new file mode 100644 index 0000000..5d28a76 --- /dev/null +++ b/group___s_p_i___slave___select__management.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_Slave_Select_management + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_Slave_Select_management
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_Slave_Select_management:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_NSS_Soft   ((uint16_t)0x0200)
 
+#define SPI_NSS_Hard   ((uint16_t)0x0000)
 
#define IS_SPI_NSS(NSS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_NSS( NSS)
+
+Value:
(((NSS) == SPI_NSS_Soft) || \
+
((NSS) == SPI_NSS_Hard))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i___slave___select__management.map b/group___s_p_i___slave___select__management.map new file mode 100644 index 0000000..8bb2e59 --- /dev/null +++ b/group___s_p_i___slave___select__management.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i___slave___select__management.md5 b/group___s_p_i___slave___select__management.md5 new file mode 100644 index 0000000..f85a924 --- /dev/null +++ b/group___s_p_i___slave___select__management.md5 @@ -0,0 +1 @@ +12d59f6418b8c3fb2ba2af809f458db5 \ No newline at end of file diff --git a/group___s_p_i___slave___select__management.png b/group___s_p_i___slave___select__management.png new file mode 100644 index 0000000..9a7f2ac Binary files /dev/null and b/group___s_p_i___slave___select__management.png differ diff --git a/group___s_p_i__data__direction.html b/group___s_p_i__data__direction.html new file mode 100644 index 0000000..70f639e --- /dev/null +++ b/group___s_p_i__data__direction.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: SPI_data_direction + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_data_direction
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_data_direction:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define SPI_Direction_2Lines_FullDuplex   ((uint16_t)0x0000)
 
+#define SPI_Direction_2Lines_RxOnly   ((uint16_t)0x0400)
 
+#define SPI_Direction_1Line_Rx   ((uint16_t)0x8000)
 
+#define SPI_Direction_1Line_Tx   ((uint16_t)0xC000)
 
#define IS_SPI_DIRECTION_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_DIRECTION_MODE( MODE)
+
+Value:
(((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+
((MODE) == SPI_Direction_2Lines_RxOnly) || \
+
((MODE) == SPI_Direction_1Line_Rx) || \
+
((MODE) == SPI_Direction_1Line_Tx))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i__data__direction.map b/group___s_p_i__data__direction.map new file mode 100644 index 0000000..cc33e27 --- /dev/null +++ b/group___s_p_i__data__direction.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i__data__direction.md5 b/group___s_p_i__data__direction.md5 new file mode 100644 index 0000000..0eb985f --- /dev/null +++ b/group___s_p_i__data__direction.md5 @@ -0,0 +1 @@ +a9468133d58fd59017e6ad1db056f31c \ No newline at end of file diff --git a/group___s_p_i__data__direction.png b/group___s_p_i__data__direction.png new file mode 100644 index 0000000..f393da7 Binary files /dev/null and b/group___s_p_i__data__direction.png differ diff --git a/group___s_p_i__data__size.html b/group___s_p_i__data__size.html new file mode 100644 index 0000000..ebe08b5 --- /dev/null +++ b/group___s_p_i__data__size.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_data_size + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_data_size
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_data_size:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_DataSize_16b   ((uint16_t)0x0800)
 
+#define SPI_DataSize_8b   ((uint16_t)0x0000)
 
#define IS_SPI_DATASIZE(DATASIZE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_DATASIZE( DATASIZE)
+
+Value:
(((DATASIZE) == SPI_DataSize_16b) || \
+
((DATASIZE) == SPI_DataSize_8b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i__data__size.map b/group___s_p_i__data__size.map new file mode 100644 index 0000000..17fd2cd --- /dev/null +++ b/group___s_p_i__data__size.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i__data__size.md5 b/group___s_p_i__data__size.md5 new file mode 100644 index 0000000..28cc9c7 --- /dev/null +++ b/group___s_p_i__data__size.md5 @@ -0,0 +1 @@ +43e04897798f9eb6406949fa13ba3f2b \ No newline at end of file diff --git a/group___s_p_i__data__size.png b/group___s_p_i__data__size.png new file mode 100644 index 0000000..e53e777 Binary files /dev/null and b/group___s_p_i__data__size.png differ diff --git a/group___s_p_i__direction__transmit__receive.html b/group___s_p_i__direction__transmit__receive.html new file mode 100644 index 0000000..13d5955 --- /dev/null +++ b/group___s_p_i__direction__transmit__receive.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_direction_transmit_receive + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_direction_transmit_receive
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_direction_transmit_receive:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_Direction_Rx   ((uint16_t)0xBFFF)
 
+#define SPI_Direction_Tx   ((uint16_t)0x4000)
 
#define IS_SPI_DIRECTION(DIRECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_DIRECTION( DIRECTION)
+
+Value:
(((DIRECTION) == SPI_Direction_Rx) || \
+
((DIRECTION) == SPI_Direction_Tx))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i__direction__transmit__receive.map b/group___s_p_i__direction__transmit__receive.map new file mode 100644 index 0000000..a5df57e --- /dev/null +++ b/group___s_p_i__direction__transmit__receive.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i__direction__transmit__receive.md5 b/group___s_p_i__direction__transmit__receive.md5 new file mode 100644 index 0000000..507d430 --- /dev/null +++ b/group___s_p_i__direction__transmit__receive.md5 @@ -0,0 +1 @@ +6203aa5a56422f31977c1057cfbce160 \ No newline at end of file diff --git a/group___s_p_i__direction__transmit__receive.png b/group___s_p_i__direction__transmit__receive.png new file mode 100644 index 0000000..bc58b7c Binary files /dev/null and b/group___s_p_i__direction__transmit__receive.png differ diff --git a/group___s_p_i__mode.html b/group___s_p_i__mode.html new file mode 100644 index 0000000..f0a5827 --- /dev/null +++ b/group___s_p_i__mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SPI_mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SPI_mode
STM32F4xx_StdPeriph_Driver » SPI » SPI_Exported_Constants
+
+
+
+Collaboration diagram for SPI_mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SPI_Mode_Master   ((uint16_t)0x0104)
 
+#define SPI_Mode_Slave   ((uint16_t)0x0000)
 
#define IS_SPI_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SPI_MODE( MODE)
+
+Value:
(((MODE) == SPI_Mode_Master) || \
+
((MODE) == SPI_Mode_Slave))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_p_i__mode.map b/group___s_p_i__mode.map new file mode 100644 index 0000000..8414585 --- /dev/null +++ b/group___s_p_i__mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_p_i__mode.md5 b/group___s_p_i__mode.md5 new file mode 100644 index 0000000..3945c27 --- /dev/null +++ b/group___s_p_i__mode.md5 @@ -0,0 +1 @@ +e8a46cb9e38b5d0a9393f850baf895c2 \ No newline at end of file diff --git a/group___s_p_i__mode.png b/group___s_p_i__mode.png new file mode 100644 index 0000000..4f59bf7 Binary files /dev/null and b/group___s_p_i__mode.png differ diff --git a/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.map b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.map new file mode 100644 index 0000000..e76c0ac --- /dev/null +++ b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.md5 b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.md5 new file mode 100644 index 0000000..4663e97 --- /dev/null +++ b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.md5 @@ -0,0 +1 @@ +bfb083ab89116dd5f0651595ba8e4cd4 \ No newline at end of file diff --git a/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.png b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.png new file mode 100644 index 0000000..412626c Binary files /dev/null and b/group___s_p_i_gabe36880945fa56785283a9c0092124cc_cgraph.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.html new file mode 100644 index 0000000..6e49436 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY + + + + + + + + + + +
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Utilities
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+Modules

 STM32F4_DISCOVERY_LOW_LEVEL
 This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics.
 
 STM32F4_DISCOVERY_LIS302DL
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.map new file mode 100644 index 0000000..253edba --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.md5 new file mode 100644 index 0000000..8df61a6 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.md5 @@ -0,0 +1 @@ +47a147c5f2b5c0c7cab3bf4a4aa201d0 \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.png new file mode 100644 index 0000000..2804286 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.html new file mode 100644 index 0000000..5fc2394 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL + + + + + + + + + + +
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STM32F4_DISCOVERY_LIS302DL
Utilities » STM32F4_DISCOVERY
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL:
+
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+Modules

 STM32F4_DISCOVERY_LIS302DL_Exported_Types
 
 STM32F4_DISCOVERY_LIS302DL_Exported_Constants
 
 STM32F4_DISCOVERY_LIS302DL_Exported_Macros
 
 STM32F4_DISCOVERY_LIS302DL_Exported_Functions
 
 STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions
 
 STM32F4_DISCOVERY_LIS302DL_Private_Defines
 
 STM32F4_DISCOVERY_LIS302DL_Private_Macros
 
 STM32F4_DISCOVERY_LIS302DL_Private_Variables
 
 STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes
 
 STM32F4_DISCOVERY_LIS302DL_Private_Functions
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.map new file mode 100644 index 0000000..010ba7e --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.md5 new file mode 100644 index 0000000..91bced0 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.md5 @@ -0,0 +1 @@ +1878aa949a5f26a62c5b51ce29b75ae4 \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.png new file mode 100644 index 0000000..ca61e51 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.html new file mode 100644 index 0000000..e7cc645 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.html @@ -0,0 +1,320 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Exported_Constants + + + + + + + + + + +
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STM32F4_DISCOVERY_LIS302DL_Exported_Constants
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Exported_Constants:
+
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+ + +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Data_Rate_selection
 
 Power_Mode_selection
 
 Full_Scale_selection
 
 Self_Test_selection
 
 Direction_XYZ_selection
 
 SPI_Serial_Interface_Mode_selection
 
 Boot_Mode_selection
 
 Filtered_Data_Selection_Mode_selection
 
 High_Pass_Filter_Interrupt_selection
 
 High_Pass_Filter_selection
 
 Latch_Interrupt_Request_selection
 
 Click_Interrupt_XYZ_selection
 
 Double_Click_Interrupt_XYZ_selection
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LIS302DL_FLAG_TIMEOUT   ((uint32_t)0x1000)
 
+#define LIS302DL_SPI   SPI1
 LIS302DL SPI Interface pins.
 
+#define LIS302DL_SPI_CLK   RCC_APB2Periph_SPI1
 
+#define LIS302DL_SPI_SCK_PIN   GPIO_Pin_5 /* PA.05 */
 
+#define LIS302DL_SPI_SCK_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_SCK_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_SCK_SOURCE   GPIO_PinSource5
 
+#define LIS302DL_SPI_SCK_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_MISO_PIN   GPIO_Pin_6 /* PA.6 */
 
+#define LIS302DL_SPI_MISO_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_MISO_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_MISO_SOURCE   GPIO_PinSource6
 
+#define LIS302DL_SPI_MISO_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_MOSI_PIN   GPIO_Pin_7 /* PA.7 */
 
+#define LIS302DL_SPI_MOSI_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_MOSI_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_MOSI_SOURCE   GPIO_PinSource7
 
+#define LIS302DL_SPI_MOSI_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_CS_PIN   GPIO_Pin_3 /* PE.03 */
 
+#define LIS302DL_SPI_CS_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_CS_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT1_PIN   GPIO_Pin_0 /* PE.00 */
 
+#define LIS302DL_SPI_INT1_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_INT1_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT1_EXTI_LINE   EXTI_Line0
 
+#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOE
 
+#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE   EXTI_PinSource0
 
+#define LIS302DL_SPI_INT1_EXTI_IRQn   EXTI0_IRQn
 
+#define LIS302DL_SPI_INT2_PIN   GPIO_Pin_1 /* PE.01 */
 
+#define LIS302DL_SPI_INT2_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_INT2_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT2_EXTI_LINE   EXTI_Line1
 
+#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOE
 
+#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE   EXTI_PinSource1
 
+#define LIS302DL_SPI_INT2_EXTI_IRQn   EXTI1_IRQn
 
+#define LIS302DL_WHO_AM_I_ADDR   0x0F
 
+#define LIS302DL_CTRL_REG1_ADDR   0x20
 
+#define LIS302DL_CTRL_REG2_ADDR   0x21
 
+#define LIS302DL_CTRL_REG3_ADDR   0x22
 
+#define LIS302DL_HP_FILTER_RESET_REG_ADDR   0x23
 
+#define LIS302DL_STATUS_REG_ADDR   0x27
 
+#define LIS302DL_OUT_X_ADDR   0x29
 
+#define LIS302DL_OUT_Y_ADDR   0x2B
 
+#define LIS302DL_OUT_Z_ADDR   0x2D
 
+#define LIS302DL_FF_WU_CFG1_REG_ADDR   0x30
 
+#define LIS302DL_FF_WU_SRC1_REG_ADDR   0x31
 
+#define LIS302DL_FF_WU_THS1_REG_ADDR   0x32
 
+#define LIS302DL_FF_WU_DURATION1_REG_ADDR   0x33
 
+#define LIS302DL_FF_WU_CFG2_REG_ADDR   0x34
 
+#define LIS302DL_FF_WU_SRC2_REG_ADDR   0x35
 
+#define LIS302DL_FF_WU_THS2_REG_ADDR   0x36
 
+#define LIS302DL_FF_WU_DURATION2_REG_ADDR   0x37
 
+#define LIS302DL_CLICK_CFG_REG_ADDR   0x38
 
+#define LIS302DL_CLICK_SRC_REG_ADDR   0x39
 
+#define LIS302DL_CLICK_THSY_X_REG_ADDR   0x3B
 
+#define LIS302DL_CLICK_THSZ_REG_ADDR   0x3C
 
+#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR   0x3D
 
+#define LIS302DL_CLICK_LATENCY_REG_ADDR   0x3E
 
+#define LIS302DL_CLICK_WINDOW_REG_ADDR   0x3F
 
+#define LIS302DL_SENSITIVITY_2_3G   18 /* 18 mg/digit*/
 
+#define LIS302DL_SENSITIVITY_9_2G   72 /* 72 mg/digit*/
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.map new file mode 100644 index 0000000..5f2db9d --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.map @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.md5 new file mode 100644 index 0000000..7f946d7 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.md5 @@ -0,0 +1 @@ +e9cf2e3fde68d8011677bc2bbe3ed7fe \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.png new file mode 100644 index 0000000..db11ae6 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___constants.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___functions.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___functions.html new file mode 100644 index 0000000..6996d48 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___functions.html @@ -0,0 +1,578 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Exported_Functions + + + + + + + + + + +
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+Functions
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STM32F4_DISCOVERY_LIS302DL_Exported_Functions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Exported_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LIS302DL_Init (LIS302DL_InitTypeDef *LIS302DL_InitStruct)
 Set LIS302DL Initialization. More...
 
void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct)
 Set LIS302DL Interrupt configuration. More...
 
void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
 Set LIS302DL Internal High Pass Filter configuration. More...
 
void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
 Change the lowpower mode for LIS302DL. More...
 
void LIS302DL_FullScaleCmd (uint8_t FS_value)
 Change the Full Scale of LIS302DL. More...
 
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
 Data Rate command. More...
 
void LIS302DL_RebootCmd (void)
 Reboot memory content of LIS302DL. More...
 
void LIS302DL_ReadACC (int32_t *out)
 Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) More...
 
void LIS302DL_Write (uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
 Writes one byte to the LIS302DL. More...
 
void LIS302DL_Read (uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
 Reads a block of data from the LIS302DL. More...
 
+uint32_t LIS302DL_TIMEOUT_UserCallback (void)
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
+
+ +

Data Rate command.

+
Parameters
+ + +
DataRateValueData rate value This parameter can be one of the following values:
    +
  • LIS302DL_DATARATE_100: 100 Hz output data rate
    • +
  • LIS302DL_DATARATE_400: 400 Hz output data rate
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef * LIS302DL_FilterConfigStruct)
+
+ +

Set LIS302DL Internal High Pass Filter configuration.

+
Parameters
+ + +
LIS302DL_Filter_ConfigTypeDefpointer to a LIS302DL_FilterConfig_TypeDef structure that contains the configuration setting for the LIS302DL Filter.
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_FullScaleCmd (uint8_t FS_value)
+
+ +

Change the Full Scale of LIS302DL.

+
Parameters
+ + +
FS_valuenew full scale value. This parameter can be one of the following values:
    +
  • LIS302DL_FULLSCALE_2_3: +-2.3g
    • +
  • LIS302DL_FULLSCALE_9_2: +-9.2g
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_Init (LIS302DL_InitTypeDef * LIS302DL_InitStruct)
+
+ +

Set LIS302DL Initialization.

+
Parameters
+ + +
LIS302DL_Config_Structpointer to a LIS302DL_Config_TypeDef structure that contains the configuration setting for the LIS302DL.
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef * LIS302DL_IntConfigStruct)
+
+ +

Set LIS302DL Interrupt configuration.

+
Parameters
+ + +
LIS302DL_InterruptConfig_TypeDefpointer to a LIS302DL_InterruptConfig_TypeDef structure that contains the configuration setting for the LIS302DL Interrupt.
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
+
+ +

Change the lowpower mode for LIS302DL.

+
Parameters
+ + +
LowPowerModenew state for the lowpower mode. This parameter can be one of the following values:
    +
  • LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode
    • +
  • LIS302DL_LOWPOWERMODE_ACTIVE: Active mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_Read (uint8_t * pBuffer,
uint8_t ReadAddr,
uint16_t NumByteToRead 
)
+
+ +

Reads a block of data from the LIS302DL.

+
Parameters
+ + + + +
pBuffer: pointer to the buffer that receives the data read from the LIS302DL.
ReadAddr: LIS302DL's internal address to read from.
NumByteToRead: number of bytes to read from the LIS302DL.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ +
+
+ + + + + + + + +
void LIS302DL_ReadACC (int32_t * out)
+
+ +

Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation)

+
Parameters
+ + +
s16buffer to store data
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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+

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+ + + + + + + + +
void LIS302DL_RebootCmd (void )
+
+ +

Reboot memory content of LIS302DL.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
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+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void LIS302DL_Write (uint8_t * pBuffer,
uint8_t WriteAddr,
uint16_t NumByteToWrite 
)
+
+ +

Writes one byte to the LIS302DL.

+
Parameters
+ + + + +
pBuffer: pointer to the buffer containing the data to be written to the LIS302DL.
WriteAddr: LIS302DL's internal address to write to.
NumByteToWriteNumber of bytes to write.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LIS302DL_Exported_Macros
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
+
+
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Exported_Macros:
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+ + +
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+ + + + + + +

+Macros

+#define LIS302DL_CS_LOW()   GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
 
+#define LIS302DL_CS_HIGH()   GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.map new file mode 100644 index 0000000..87f705e --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.md5 new file mode 100644 index 0000000..e808d3b --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.md5 @@ -0,0 +1 @@ +0f583f01a3f9e28712d093820e69dc6b \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.png new file mode 100644 index 0000000..e61e381 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___macros.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.html new file mode 100644 index 0000000..10f4667 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Exported_Types + + + + + + + + + + +
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STM32F4_DISCOVERY_LIS302DL_Exported_Types
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Exported_Types:
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+ + + + + + + + +

+Classes

struct  LIS302DL_InitTypeDef
 
struct  LIS302DL_FilterConfigTypeDef
 
struct  LIS302DL_InterruptConfigTypeDef
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.map new file mode 100644 index 0000000..95d617a --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.md5 new file mode 100644 index 0000000..cec4a5a --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.md5 @@ -0,0 +1 @@ +6b85d4ef34eba9aeb30d2bb7bc9ac3de \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.png new file mode 100644 index 0000000..643bbf2 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___exported___types.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.html new file mode 100644 index 0000000..163e368 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Private_Defines + + + + + + + + + + +
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+Macros | +Variables
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STM32F4_DISCOVERY_LIS302DL_Private_Defines
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_Defines:
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+ + +
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+ + + + + + + + +

+Macros

+#define READWRITE_CMD   ((uint8_t)0x80)
 
+#define MULTIPLEBYTE_CMD   ((uint8_t)0x40)
 
+#define DUMMY_BYTE   ((uint8_t)0x00)
 
+ + + +

+Variables

+__IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.map new file mode 100644 index 0000000..46ca38f --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.md5 new file mode 100644 index 0000000..ae3c76e --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.md5 @@ -0,0 +1 @@ +71eb900a358e05e9885064b3ee72552d \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.png new file mode 100644 index 0000000..91e8618 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___defines.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.html new file mode 100644 index 0000000..9b57536 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes + + + + + + + + + + +
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STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.map new file mode 100644 index 0000000..7e2798a --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.md5 new file mode 100644 index 0000000..e4153c9 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.md5 @@ -0,0 +1 @@ +9e44ba9dfca6be56acfcb87e3c0d1a49 \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.png new file mode 100644 index 0000000..25fa220 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___function_prototypes.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___functions.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___functions.html new file mode 100644 index 0000000..b1c26c8 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_i_s302_d_l___private___functions.html @@ -0,0 +1,575 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LIS302DL_Private_Functions + + + + + + + + + + +
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STM32F4_DISCOVERY_LIS302DL_Private_Functions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
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+
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_Functions:
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+Functions

void LIS302DL_Init (LIS302DL_InitTypeDef *LIS302DL_InitStruct)
 Set LIS302DL Initialization. More...
 
void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
 Set LIS302DL Internal High Pass Filter configuration. More...
 
void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct)
 Set LIS302DL Interrupt configuration. More...
 
void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
 Change the lowpower mode for LIS302DL. More...
 
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
 Data Rate command. More...
 
void LIS302DL_FullScaleCmd (uint8_t FS_value)
 Change the Full Scale of LIS302DL. More...
 
void LIS302DL_RebootCmd (void)
 Reboot memory content of LIS302DL. More...
 
void LIS302DL_Write (uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
 Writes one byte to the LIS302DL. More...
 
void LIS302DL_Read (uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
 Reads a block of data from the LIS302DL. More...
 
void LIS302DL_ReadACC (int32_t *out)
 Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
+
+ +

Data Rate command.

+
Parameters
+ + +
DataRateValueData rate value This parameter can be one of the following values:
    +
  • LIS302DL_DATARATE_100: 100 Hz output data rate
    • +
  • LIS302DL_DATARATE_400: 400 Hz output data rate
    • +
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+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef * LIS302DL_FilterConfigStruct)
+
+ +

Set LIS302DL Internal High Pass Filter configuration.

+
Parameters
+ + +
LIS302DL_Filter_ConfigTypeDefpointer to a LIS302DL_FilterConfig_TypeDef structure that contains the configuration setting for the LIS302DL Filter.
+
+
+
Return values
+ + +
None
+
+
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void LIS302DL_FullScaleCmd (uint8_t FS_value)
+
+ +

Change the Full Scale of LIS302DL.

+
Parameters
+ + +
FS_valuenew full scale value. This parameter can be one of the following values:
    +
  • LIS302DL_FULLSCALE_2_3: +-2.3g
    • +
  • LIS302DL_FULLSCALE_9_2: +-9.2g
    • +
+
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+
Return values
+ + +
None
+
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void LIS302DL_Init (LIS302DL_InitTypeDef * LIS302DL_InitStruct)
+
+ +

Set LIS302DL Initialization.

+
Parameters
+ + +
LIS302DL_Config_Structpointer to a LIS302DL_Config_TypeDef structure that contains the configuration setting for the LIS302DL.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef * LIS302DL_IntConfigStruct)
+
+ +

Set LIS302DL Interrupt configuration.

+
Parameters
+ + +
LIS302DL_InterruptConfig_TypeDefpointer to a LIS302DL_InterruptConfig_TypeDef structure that contains the configuration setting for the LIS302DL Interrupt.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
+
+ +

Change the lowpower mode for LIS302DL.

+
Parameters
+ + +
LowPowerModenew state for the lowpower mode. This parameter can be one of the following values:
    +
  • LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode
    • +
  • LIS302DL_LOWPOWERMODE_ACTIVE: Active mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_Read (uint8_t * pBuffer,
uint8_t ReadAddr,
uint16_t NumByteToRead 
)
+
+ +

Reads a block of data from the LIS302DL.

+
Parameters
+ + + + +
pBuffer: pointer to the buffer that receives the data read from the LIS302DL.
ReadAddr: LIS302DL's internal address to read from.
NumByteToRead: number of bytes to read from the LIS302DL.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + +
void LIS302DL_ReadACC (int32_t * out)
+
+ +

Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation)

+
Parameters
+ + +
s16buffer to store data
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_RebootCmd (void )
+
+ +

Reboot memory content of LIS302DL.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

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void LIS302DL_Write (uint8_t * pBuffer,
uint8_t WriteAddr,
uint16_t NumByteToWrite 
)
+
+ +

Writes one byte to the LIS302DL.

+
Parameters
+ + + + +
pBuffer: pointer to the buffer containing the data to be written to the LIS302DL.
WriteAddr: LIS302DL's internal address to write to.
NumByteToWriteNumber of bytes to write.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
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+ +
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+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LIS302DL_Private_Macros
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_Macros:
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STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions:
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STM32F4_DISCOVERY_LIS302DL_Private_Variables
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL
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+Collaboration diagram for STM32F4_DISCOVERY_LIS302DL_Private_Variables:
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STM32F4_DISCOVERY_LOW_LEVEL
Utilities » STM32F4_DISCOVERY
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+ +

This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics. +More...

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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL:
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+Modules

 STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
 
 STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes
 
 STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions
 
+

Detailed Description

+

This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics.

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.map new file mode 100644 index 0000000..2a41260 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.md5 new file mode 100644 index 0000000..c8f81b7 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.md5 @@ -0,0 +1 @@ +ae3f689e7db1cf308bed0ca7af4d00ce \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.png new file mode 100644 index 0000000..ff6d854 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___b_u_t_t_o_n.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___b_u_t_t_o_n.html new file mode 100644 index 0000000..bd9994f --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___b_u_t_t_o_n.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LOW_LEVEL_BUTTON + + + + + + + + + + +
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STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL » STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_BUTTON:
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+Macros

+#define BUTTONn   1
 
+#define USER_BUTTON_PIN   GPIO_Pin_0
 Wakeup push-button.
 
+#define USER_BUTTON_GPIO_PORT   GPIOA
 
+#define USER_BUTTON_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define USER_BUTTON_EXTI_LINE   EXTI_Line0
 
+#define USER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOA
 
+#define USER_BUTTON_EXTI_PIN_SOURCE   EXTI_PinSource0
 
+#define USER_BUTTON_EXTI_IRQn   EXTI0_IRQn
 
+

Detailed Description

+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants:
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+Modules

 STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
 
 STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
 
 STM32F4_DISCOVERY_LOW_LEVEL_LED
 
 STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.map new file mode 100644 index 0000000..4dcbc05 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.md5 new file mode 100644 index 0000000..5ccb508 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.md5 @@ -0,0 +1 @@ +49097221fc0ac7da7399fcab5d96e185 \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.png new file mode 100644 index 0000000..1d083b2 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___constants.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___functions.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___functions.html new file mode 100644 index 0000000..cc4b67e --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___exported___functions.html @@ -0,0 +1,371 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions + + + + + + + + + + +
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STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL » STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
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+Functions

void STM_EVAL_LEDInit (Led_TypeDef Led)
 Configures LED GPIO. More...
 
void STM_EVAL_LEDOn (Led_TypeDef Led)
 Turns selected LED On. More...
 
void STM_EVAL_LEDOff (Led_TypeDef Led)
 Turns selected LED Off. More...
 
void STM_EVAL_LEDToggle (Led_TypeDef Led)
 Toggles the selected LED. More...
 
void STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
 Configures Button GPIO and EXTI Line. More...
 
uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
 Returns the selected Button state. More...
 
+

Detailed Description

+

Function Documentation

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+ + + + + + + + +
void STM_EVAL_LEDInit (Led_TypeDef Led)
+
+ +

Configures LED GPIO.

+
Parameters
+ + +
LedSpecifies the Led to be configured. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
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Return values
+ + +
None
+
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void STM_EVAL_LEDOff (Led_TypeDef Led)
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+ +

Turns selected LED Off.

+
Parameters
+ + +
LedSpecifies the Led to be set off. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
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+
+
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Return values
+ + +
None
+
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+ +
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void STM_EVAL_LEDOn (Led_TypeDef Led)
+
+ +

Turns selected LED On.

+
Parameters
+ + +
LedSpecifies the Led to be set on. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
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+ +
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void STM_EVAL_LEDToggle (Led_TypeDef Led)
+
+ +

Toggles the selected LED.

+
Parameters
+ + +
LedSpecifies the Led to be toggled. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
+
+
+
+
Return values
+ + +
None
+
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+ +
+
+ +
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+ + + + + + + + +
uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
+
+ +

Returns the selected Button state.

+
Parameters
+ + +
ButtonSpecifies the Button to be checked. This parameter should be: BUTTON_USER
+
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Return values
+ + +
TheButton GPIO pin value.
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void STM_EVAL_PBInit (Button_TypeDef Button,
ButtonMode_TypeDef Button_Mode 
)
+
+ +

Configures Button GPIO and EXTI Line.

+
Parameters
+ + + +
ButtonSpecifies the Button to be configured. This parameter should be: BUTTON_USER
Button_ModeSpecifies Button mode. This parameter can be one of following parameters:
    +
  • BUTTON_MODE_GPIO: Button will be used as simple IO
    • +
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
    • +
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Return values
+ + +
None
+
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL » STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types:
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+Enumerations

enum  Led_TypeDef { LED4 = 0, +LED3 = 1, +LED5 = 2, +LED6 = 3 + }
 
enum  Button_TypeDef { BUTTON_USER = 0 + }
 
enum  ButtonMode_TypeDef { BUTTON_MODE_GPIO = 0, +BUTTON_MODE_EXTI = 1 + }
 
+

Detailed Description

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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Macros
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STM32F4_DISCOVERY_LOW_LEVEL_LED
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL » STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_LED:
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+Macros

+#define LEDn   4
 
+#define LED4_PIN   GPIO_Pin_12
 
+#define LED4_GPIO_PORT   GPIOD
 
+#define LED4_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED3_PIN   GPIO_Pin_13
 
+#define LED3_GPIO_PORT   GPIOD
 
+#define LED3_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED5_PIN   GPIO_Pin_14
 
+#define LED5_GPIO_PORT   GPIOD
 
+#define LED5_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED6_PIN   GPIO_Pin_15
 
+#define LED6_GPIO_PORT   GPIOD
 
+#define LED6_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+

Detailed Description

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes:
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Functions
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STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Functions

void STM_EVAL_LEDInit (Led_TypeDef Led)
 Configures LED GPIO. More...
 
void STM_EVAL_LEDOn (Led_TypeDef Led)
 Turns selected LED On. More...
 
void STM_EVAL_LEDOff (Led_TypeDef Led)
 Turns selected LED Off. More...
 
void STM_EVAL_LEDToggle (Led_TypeDef Led)
 Toggles the selected LED. More...
 
void STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
 Configures Button GPIO and EXTI Line. More...
 
uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
 Returns the selected Button state. More...
 
+

Detailed Description

+

Function Documentation

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+ + + + + + + + +
void STM_EVAL_LEDInit (Led_TypeDef Led)
+
+ +

Configures LED GPIO.

+
Parameters
+ + +
LedSpecifies the Led to be configured. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
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Return values
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None
+
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void STM_EVAL_LEDOff (Led_TypeDef Led)
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+ +

Turns selected LED Off.

+
Parameters
+ + +
LedSpecifies the Led to be set off. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
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Return values
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None
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void STM_EVAL_LEDOn (Led_TypeDef Led)
+
+ +

Turns selected LED On.

+
Parameters
+ + +
LedSpecifies the Led to be set on. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
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Return values
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None
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void STM_EVAL_LEDToggle (Led_TypeDef Led)
+
+ +

Toggles the selected LED.

+
Parameters
+ + +
LedSpecifies the Led to be toggled. This parameter can be one of following parameters:
    +
  • LED4
    • +
  • LED3
    • +
  • LED5
    • +
  • LED6
    • +
+
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Return values
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None
+
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uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
+
+ +

Returns the selected Button state.

+
Parameters
+ + +
ButtonSpecifies the Button to be checked. This parameter should be: BUTTON_USER
+
+
+
Return values
+ + +
TheButton GPIO pin value.
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void STM_EVAL_PBInit (Button_TypeDef Button,
ButtonMode_TypeDef Button_Mode 
)
+
+ +

Configures Button GPIO and EXTI Line.

+
Parameters
+ + + +
ButtonSpecifies the Button to be configured. This parameter should be: BUTTON_USER
Button_ModeSpecifies Button mode. This parameter can be one of following parameters:
    +
  • BUTTON_MODE_GPIO: Button will be used as simple IO
    • +
  • BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt generation capability
    • +
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Return values
+ + +
None
+
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
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+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros:
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.map new file mode 100644 index 0000000..4a69417 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.md5 new file mode 100644 index 0000000..14babe1 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.md5 @@ -0,0 +1 @@ +04f3fedcdd1fbf4be8040e9a90af95c4 \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.png new file mode 100644 index 0000000..0a2030f Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___macros.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.html new file mode 100644 index 0000000..5d05c05 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions + + + + + + + + + + +
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STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.map new file mode 100644 index 0000000..a4c4a7f --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.md5 new file mode 100644 index 0000000..4a82631 --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.md5 @@ -0,0 +1 @@ +d21fdedfa359ce366de288282fcf97ed \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.png new file mode 100644 index 0000000..9ca68e1 Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___types_definitions.png differ diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.html b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.html new file mode 100644 index 0000000..aaf194a --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables + + + + + + + + + + +
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discoverpixy +
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+Variables
+
+
STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LOW_LEVEL
+
+
+
+Collaboration diagram for STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables:
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+Variables

GPIO_TypeDef * GPIO_PORT [LEDn]
 
const uint16_t GPIO_PIN [LEDn]
 
const uint32_t GPIO_CLK [LEDn]
 
+GPIO_TypeDef * BUTTON_PORT [BUTTONn] = {USER_BUTTON_GPIO_PORT }
 
+const uint16_t BUTTON_PIN [BUTTONn] = {USER_BUTTON_PIN }
 
+const uint32_t BUTTON_CLK [BUTTONn] = {USER_BUTTON_GPIO_CLK }
 
+const uint16_t BUTTON_EXTI_LINE [BUTTONn] = {USER_BUTTON_EXTI_LINE }
 
+const uint8_t BUTTON_PORT_SOURCE [BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE}
 
+const uint8_t BUTTON_PIN_SOURCE [BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE }
 
+const uint8_t BUTTON_IRQn [BUTTONn] = {USER_BUTTON_EXTI_IRQn }
 
+NVIC_InitTypeDef NVIC_InitStructure
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
const uint32_t GPIO_CLK[LEDn]
+
+Initial value:
= {LED4_GPIO_CLK, LED3_GPIO_CLK, LED5_GPIO_CLK,
+
LED6_GPIO_CLK}
+
+
+
+ +
+
+ + + + +
const uint16_t GPIO_PIN[LEDn]
+
+Initial value:
= {LED4_PIN, LED3_PIN, LED5_PIN,
+
LED6_PIN}
+
+
+
+ +
+
+ + + + +
GPIO_TypeDef* GPIO_PORT[LEDn]
+
+Initial value:
= {LED4_GPIO_PORT, LED3_GPIO_PORT, LED5_GPIO_PORT,
+
LED6_GPIO_PORT}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.map b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.map new file mode 100644 index 0000000..873160f --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.md5 b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.md5 new file mode 100644 index 0000000..0b4f66f --- /dev/null +++ b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.md5 @@ -0,0 +1 @@ +be68633a7dd4066d75901d9c4d965d4c \ No newline at end of file diff --git a/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.png b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.png new file mode 100644 index 0000000..25bcd8c Binary files /dev/null and b/group___s_t_m32_f4___d_i_s_c_o_v_e_r_y___l_o_w___l_e_v_e_l___private___variables.png differ diff --git a/group___s_t_m32_f4xx___std_periph___driver.html b/group___s_t_m32_f4xx___std_periph___driver.html new file mode 100644 index 0000000..5224277 --- /dev/null +++ b/group___s_t_m32_f4xx___std_periph___driver.html @@ -0,0 +1,229 @@ + + + + + + +discoverpixy: STM32F4xx_StdPeriph_Driver + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
STM32F4xx_StdPeriph_Driver
+
+
+
+Collaboration diagram for STM32F4xx_StdPeriph_Driver:
+
+
+ + +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 LTDC_SYNC
 
 LTDC_HSPolarity
 
 LTDC_VSPolarity
 
 LTDC_DEPolarity
 
 LTDC_PCPolarity
 
 LTDC_Reload
 
 LTDC_Back_Color
 
 LTDC_Position
 
 LTDC_LIPosition
 
 LTDC_CurrentStatus
 
 LTDC_Interrupts
 
 LTDC_Flag
 
 LTDC_Pixelformat
 
 LTDC_BlendingFactor1
 
 LTDC_BlendingFactor2
 
 LTDC_LAYER_Config
 
 LTDC_colorkeying_Config
 
 LTDC_CLUT_Config
 
 MISC
 MISC driver modules.
 
 ADC
 ADC driver modules.
 
 CAN
 CAN driver modules.
 
 CRC
 CRC driver modules.
 
 CRYP
 CRYP driver modules.
 
 DAC
 DAC driver modules.
 
 DBGMCU
 DBGMCU driver modules.
 
 DCMI
 DCMI driver modules.
 
 DMA
 DMA driver modules.
 
 DMA2D
 DMA2D driver modules.
 
 EXTI
 EXTI driver modules.
 
 RAMFUNC
 FLASH driver modules.
 
 FSMC
 FSMC driver modules.
 
 GPIO
 GPIO driver modules.
 
 HASH
 HASH driver modules.
 
 I2C
 I2C driver modules.
 
 IWDG
 IWDG driver modules.
 
 LTDC
 LTDC driver modules.
 
 PWR
 PWR driver modules.
 
 RCC
 RCC driver modules.
 
 RNG
 RNG driver modules.
 
 RTC
 RTC driver modules.
 
 SAI
 SAI driver modules.
 
 SDIO
 SDIO driver modules.
 
 SPI
 SPI driver modules.
 
 SYSCFG
 SYSCFG driver modules.
 
 TIM
 TIM driver modules.
 
 USART
 USART driver modules.
 
 WWDG
 WWDG driver modules.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___std_periph___driver.map b/group___s_t_m32_f4xx___std_periph___driver.map new file mode 100644 index 0000000..78a10c0 --- /dev/null +++ b/group___s_t_m32_f4xx___std_periph___driver.map @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___s_t_m32_f4xx___std_periph___driver.md5 b/group___s_t_m32_f4xx___std_periph___driver.md5 new file mode 100644 index 0000000..0c29e07 --- /dev/null +++ b/group___s_t_m32_f4xx___std_periph___driver.md5 @@ -0,0 +1 @@ +f09c46a6ab015f8b17107edd6d80287f \ No newline at end of file diff --git a/group___s_t_m32_f4xx___std_periph___driver.png b/group___s_t_m32_f4xx___std_periph___driver.png new file mode 100644 index 0000000..814e1b7 Binary files /dev/null and b/group___s_t_m32_f4xx___std_periph___driver.png differ diff --git a/group___s_t_m32_f4xx___system___exported___constants.html b/group___s_t_m32_f4xx___system___exported___constants.html new file mode 100644 index 0000000..a44821a --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___constants.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: STM32F4xx_System_Exported_Constants + + + + + + + + + + +
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STM32F4xx_System_Exported_Constants
CMSIS » Stm32f4xx_system
+
+
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+Collaboration diagram for STM32F4xx_System_Exported_Constants:
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+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___exported___constants.map b/group___s_t_m32_f4xx___system___exported___constants.map new file mode 100644 index 0000000..b6bfc34 --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___constants.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___exported___constants.md5 b/group___s_t_m32_f4xx___system___exported___constants.md5 new file mode 100644 index 0000000..19353bc --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___constants.md5 @@ -0,0 +1 @@ +f5ba1dd27ea714a89d24b0faf920fe4c \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___exported___constants.png b/group___s_t_m32_f4xx___system___exported___constants.png new file mode 100644 index 0000000..0a7469e Binary files /dev/null and b/group___s_t_m32_f4xx___system___exported___constants.png differ diff --git a/group___s_t_m32_f4xx___system___exported___functions.html b/group___s_t_m32_f4xx___system___exported___functions.html new file mode 100644 index 0000000..102bdcb --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___functions.html @@ -0,0 +1,186 @@ + + + + + + +discoverpixy: STM32F4xx_System_Exported_Functions + + + + + + + + + + +
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STM32F4xx_System_Exported_Functions
CMSIS » Stm32f4xx_system
+
+
+
+Collaboration diagram for STM32F4xx_System_Exported_Functions:
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+Functions

void SystemInit (void)
 Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. More...
 
void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+ +

Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

+
Note
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
+
+- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
+
    +
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
    • +
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
    • +
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
    • +
+

(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

+

(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

+
    +
  • The result of this function could be not correct when using fractional value for HSE crystal.
    • +
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+ +

Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___exported___functions.map b/group___s_t_m32_f4xx___system___exported___functions.map new file mode 100644 index 0000000..4b58826 --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___exported___functions.md5 b/group___s_t_m32_f4xx___system___exported___functions.md5 new file mode 100644 index 0000000..e46adc7 --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___functions.md5 @@ -0,0 +1 @@ +941a6808ff262b39c059e1dcfc3472e2 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___exported___functions.png b/group___s_t_m32_f4xx___system___exported___functions.png new file mode 100644 index 0000000..cbd017e Binary files /dev/null and b/group___s_t_m32_f4xx___system___exported___functions.png differ diff --git a/group___s_t_m32_f4xx___system___exported___macros.html b/group___s_t_m32_f4xx___system___exported___macros.html new file mode 100644 index 0000000..26efafa --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: STM32F4xx_System_Exported_Macros + + + + + + + + + + +
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STM32F4xx_System_Exported_Macros
CMSIS » Stm32f4xx_system
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+Collaboration diagram for STM32F4xx_System_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___exported___macros.map b/group___s_t_m32_f4xx___system___exported___macros.map new file mode 100644 index 0000000..31d1de6 --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___exported___macros.md5 b/group___s_t_m32_f4xx___system___exported___macros.md5 new file mode 100644 index 0000000..417c40f --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported___macros.md5 @@ -0,0 +1 @@ +d4d72cf843f9cde2f2acc16dc8060c49 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___exported___macros.png b/group___s_t_m32_f4xx___system___exported___macros.png new file mode 100644 index 0000000..8622b59 Binary files /dev/null and b/group___s_t_m32_f4xx___system___exported___macros.png differ diff --git a/group___s_t_m32_f4xx___system___exported__types.html b/group___s_t_m32_f4xx___system___exported__types.html new file mode 100644 index 0000000..9e140fc --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported__types.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: STM32F4xx_System_Exported_types + + + + + + + + + + +
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STM32F4xx_System_Exported_types
CMSIS » Stm32f4xx_system
+
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+Collaboration diagram for STM32F4xx_System_Exported_types:
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+Variables

uint32_t SystemCoreClock
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
uint32_t SystemCoreClock
+
+

System Clock Frequency (Core Clock)

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___exported__types.map b/group___s_t_m32_f4xx___system___exported__types.map new file mode 100644 index 0000000..d5261b4 --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported__types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___exported__types.md5 b/group___s_t_m32_f4xx___system___exported__types.md5 new file mode 100644 index 0000000..0768adf --- /dev/null +++ b/group___s_t_m32_f4xx___system___exported__types.md5 @@ -0,0 +1 @@ +9f035a1b116ec801de85aeb9eddb9df5 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___exported__types.png b/group___s_t_m32_f4xx___system___exported__types.png new file mode 100644 index 0000000..8eb22c3 Binary files /dev/null and b/group___s_t_m32_f4xx___system___exported__types.png differ diff --git a/group___s_t_m32_f4xx___system___includes.html b/group___s_t_m32_f4xx___system___includes.html new file mode 100644 index 0000000..6098792 --- /dev/null +++ b/group___s_t_m32_f4xx___system___includes.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: STM32F4xx_System_Includes + + + + + + + + + + +
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STM32F4xx_System_Includes
CMSIS » Stm32f4xx_system
+
+
+ +

Define to prevent recursive inclusion. +More...

+
+Collaboration diagram for STM32F4xx_System_Includes:
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Define to prevent recursive inclusion.

+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4xx_System_Private_Defines
CMSIS » Stm32f4xx_system
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+Collaboration diagram for STM32F4xx_System_Private_Defines:
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+Macros

#define VECT_TAB_OFFSET   0x00
 
+#define PLL_M   8
 
+#define PLL_N   336
 
+#define PLL_P   2
 
+#define PLL_Q   7
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define VECT_TAB_OFFSET   0x00
+
+

< Uncomment the following line if you need to use external SRAM mounted on STM324xG_EVAL board as data memory

+

< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. Vector Table base offset field. This value must be a multiple of 0x200.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___private___defines.map b/group___s_t_m32_f4xx___system___private___defines.map new file mode 100644 index 0000000..2af9c3e --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___private___defines.md5 b/group___s_t_m32_f4xx___system___private___defines.md5 new file mode 100644 index 0000000..a6ccbb6 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___defines.md5 @@ -0,0 +1 @@ +0e46eef3ac4792cd4609e1f957a97e07 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___private___defines.png b/group___s_t_m32_f4xx___system___private___defines.png new file mode 100644 index 0000000..35c2104 Binary files /dev/null and b/group___s_t_m32_f4xx___system___private___defines.png differ diff --git a/group___s_t_m32_f4xx___system___private___function_prototypes.html b/group___s_t_m32_f4xx___system___private___function_prototypes.html new file mode 100644 index 0000000..2fec4ce --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: STM32F4xx_System_Private_FunctionPrototypes + + + + + + + + + + +
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STM32F4xx_System_Private_FunctionPrototypes
CMSIS » Stm32f4xx_system
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+Collaboration diagram for STM32F4xx_System_Private_FunctionPrototypes:
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Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4xx_System_Private_Functions
CMSIS » Stm32f4xx_system
+
+
+
+Collaboration diagram for STM32F4xx_System_Private_Functions:
+
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+ + + + + + + + +

+Functions

void SystemInit (void)
 Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. More...
 
void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+ +

Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

+
Note
Each time the core clock (HCLK) changes, this function must be called to update SystemCoreClock variable value. Otherwise, any configuration based on this variable will be incorrect.
+
+- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
+
    +
  • If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
    • +
  • If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
    • +
  • If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
    • +
+

(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

+

(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

+
    +
  • The result of this function could be not correct when using fractional value for HSE crystal.
    • +
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+ +

Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
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STM32F4xx_System_Private_Includes
CMSIS » Stm32f4xx_system
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STM32F4xx_System_Private_Macros
CMSIS » Stm32f4xx_system
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STM32F4xx_System_Private_TypesDefinitions
CMSIS » Stm32f4xx_system
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+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___private___types_definitions.map b/group___s_t_m32_f4xx___system___private___types_definitions.map new file mode 100644 index 0000000..a4a33e8 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___private___types_definitions.md5 b/group___s_t_m32_f4xx___system___private___types_definitions.md5 new file mode 100644 index 0000000..cf9b358 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___types_definitions.md5 @@ -0,0 +1 @@ +0868e5c7eddff499e17cf6ad5c5b6688 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___private___types_definitions.png b/group___s_t_m32_f4xx___system___private___types_definitions.png new file mode 100644 index 0000000..3b29d4e Binary files /dev/null and b/group___s_t_m32_f4xx___system___private___types_definitions.png differ diff --git a/group___s_t_m32_f4xx___system___private___variables.html b/group___s_t_m32_f4xx___system___private___variables.html new file mode 100644 index 0000000..e63aa08 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___variables.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: STM32F4xx_System_Private_Variables + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
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+Variables
+
+
STM32F4xx_System_Private_Variables
CMSIS » Stm32f4xx_system
+
+
+
+Collaboration diagram for STM32F4xx_System_Private_Variables:
+
+
+ + +
+
+ + + + + + +

+Variables

+uint32_t SystemCoreClock = 168000000
 
+__I uint8_t AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_t_m32_f4xx___system___private___variables.map b/group___s_t_m32_f4xx___system___private___variables.map new file mode 100644 index 0000000..a19cd74 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_t_m32_f4xx___system___private___variables.md5 b/group___s_t_m32_f4xx___system___private___variables.md5 new file mode 100644 index 0000000..3988e53 --- /dev/null +++ b/group___s_t_m32_f4xx___system___private___variables.md5 @@ -0,0 +1 @@ +333d7a4912761cebb498f2a88f07ad01 \ No newline at end of file diff --git a/group___s_t_m32_f4xx___system___private___variables.png b/group___s_t_m32_f4xx___system___private___variables.png new file mode 100644 index 0000000..12bfd9c Binary files /dev/null and b/group___s_t_m32_f4xx___system___private___variables.png differ diff --git a/group___s_y_s_c_f_g.html b/group___s_y_s_c_f_g.html new file mode 100644 index 0000000..9b8f7ca --- /dev/null +++ b/group___s_y_s_c_f_g.html @@ -0,0 +1,435 @@ + + + + + + +discoverpixy: SYSCFG + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+ + +
+ +
+ +
+
+Modules | +Macros | +Functions
+
+
SYSCFG
STM32F4xx_StdPeriph_Driver
+
+
+ +

SYSCFG driver modules. +More...

+
+Collaboration diagram for SYSCFG:
+
+
+ + +
+
+ + + + + + +

+Modules

 SYSCFG_Exported_Constants
 
 SYSCFG_Private_Functions
 
+ + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SYSCFG_OFFSET   (SYSCFG_BASE - PERIPH_BASE)
 
+#define MEMRMP_OFFSET   SYSCFG_OFFSET
 
+#define UFB_MODE_BitNumber   ((uint8_t)0x8)
 
+#define UFB_MODE_BB   (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
 
+#define PMC_OFFSET   (SYSCFG_OFFSET + 0x04)
 
+#define MII_RMII_SEL_BitNumber   ((uint8_t)0x17)
 
+#define PMC_MII_RMII_SEL_BB   (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
 
+#define CMPCR_OFFSET   (SYSCFG_OFFSET + 0x20)
 
+#define CMP_PD_BitNumber   ((uint8_t)0x00)
 
+#define CMPCR_CMP_PD_BB   (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SYSCFG_DeInit (void)
 Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values. More...
 
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
 Changes the mapping of the specified pin. More...
 
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
 Enables or disables the Interal FLASH Bank Swapping. More...
 
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 Selects the GPIO pin used as EXTI Line. More...
 
void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
 Selects the ETHERNET media interface. More...
 
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
 Enables or disables the I/O Compensation Cell. More...
 
FlagStatus SYSCFG_GetCompensationCellStatus (void)
 Checks whether the I/O Compensation Cell ready flag is set or not. More...
 
+

Detailed Description

+

SYSCFG driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
+
+ +

Enables or disables the I/O Compensation Cell.

+
Note
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
+
Parameters
+ + +
NewStatenew state of the I/O Compensation Cell. This parameter can be one of the following values:
    +
  • ENABLE: I/O compensation cell enabled
    • +
  • DISABLE: I/O compensation cell power-down mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_DeInit (void )
+
+ +

Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
+
+ +

Selects the ETHERNET media interface.

+
Parameters
+ + +
SYSCFG_ETH_MediaInterfacespecifies the Media Interface mode. This parameter can be one of the following values:
    +
  • SYSCFG_ETH_MediaInterface_MII: MII mode selected
    • +
  • SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx,
uint8_t EXTI_PinSourcex 
)
+
+ +

Selects the GPIO pin used as EXTI Line.

+
Parameters
+ + + +
EXTI_PortSourceGPIOx: selects the GPIO port to be used as source for EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) for STM32401xx devices.
EXTI_PinSourcexspecifies the EXTI line to be configured. This parameter can be EXTI_PinSourcex where x can be (0..15, except for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can be (0..7) for STM32F42xxx/43xxx devices.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
FlagStatus SYSCFG_GetCompensationCellStatus (void )
+
+ +

Checks whether the I/O Compensation Cell ready flag is set or not.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thenew state of the I/O Compensation Cell ready flag (SET or RESET)
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
+
+ +

Changes the mapping of the specified pin.

+
Parameters
+ + +
SYSCFG_Memoryselects the memory remapping. This parameter can be one of the following values:
    +
  • SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
    • +
  • SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
    • +
  • SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
+
+ +

Enables or disables the Interal FLASH Bank Swapping.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
NewStatenew state of Interal FLASH Bank swapping. This parameter can be one of the following values:
    +
  • ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
    • +
  • DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g.map b/group___s_y_s_c_f_g.map new file mode 100644 index 0000000..caea8c1 --- /dev/null +++ b/group___s_y_s_c_f_g.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___s_y_s_c_f_g.md5 b/group___s_y_s_c_f_g.md5 new file mode 100644 index 0000000..819540d --- /dev/null +++ b/group___s_y_s_c_f_g.md5 @@ -0,0 +1 @@ +ad923f6c0ae9a23f6ebd56fc1595fce2 \ No newline at end of file diff --git a/group___s_y_s_c_f_g.png b/group___s_y_s_c_f_g.png new file mode 100644 index 0000000..2c762ba Binary files /dev/null and b/group___s_y_s_c_f_g.png differ diff --git a/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.html b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.html new file mode 100644 index 0000000..70bc123 --- /dev/null +++ b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: SYSCFG_ETHERNET_Media_Interface + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SYSCFG_ETHERNET_Media_Interface
STM32F4xx_StdPeriph_Driver » SYSCFG » SYSCFG_Exported_Constants
+
+
+
+Collaboration diagram for SYSCFG_ETHERNET_Media_Interface:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define SYSCFG_ETH_MediaInterface_MII   ((uint32_t)0x00000000)
 
+#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)
 
#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SYSCFG_ETH_MEDIA_INTERFACE( INTERFACE)
+
+Value:
(((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
+
((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.map b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.map new file mode 100644 index 0000000..e888a2d --- /dev/null +++ b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.md5 b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.md5 new file mode 100644 index 0000000..ef07499 --- /dev/null +++ b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.md5 @@ -0,0 +1 @@ +0aa971e3f4cf0d2ccf8647b42710f472 \ No newline at end of file diff --git a/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.png b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.png new file mode 100644 index 0000000..3f88ec6 Binary files /dev/null and b/group___s_y_s_c_f_g___e_t_h_e_r_n_e_t___media___interface.png differ diff --git a/group___s_y_s_c_f_g___e_x_t_i___pin___sources.html b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.html new file mode 100644 index 0000000..fbd6c6d --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: SYSCFG_EXTI_Pin_Sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SYSCFG_EXTI_Pin_Sources
STM32F4xx_StdPeriph_Driver » SYSCFG » SYSCFG_Exported_Constants
+
+
+
+Collaboration diagram for SYSCFG_EXTI_Pin_Sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define EXTI_PinSource0   ((uint8_t)0x00)
 
+#define EXTI_PinSource1   ((uint8_t)0x01)
 
+#define EXTI_PinSource2   ((uint8_t)0x02)
 
+#define EXTI_PinSource3   ((uint8_t)0x03)
 
+#define EXTI_PinSource4   ((uint8_t)0x04)
 
+#define EXTI_PinSource5   ((uint8_t)0x05)
 
+#define EXTI_PinSource6   ((uint8_t)0x06)
 
+#define EXTI_PinSource7   ((uint8_t)0x07)
 
+#define EXTI_PinSource8   ((uint8_t)0x08)
 
+#define EXTI_PinSource9   ((uint8_t)0x09)
 
+#define EXTI_PinSource10   ((uint8_t)0x0A)
 
+#define EXTI_PinSource11   ((uint8_t)0x0B)
 
+#define EXTI_PinSource12   ((uint8_t)0x0C)
 
+#define EXTI_PinSource13   ((uint8_t)0x0D)
 
+#define EXTI_PinSource14   ((uint8_t)0x0E)
 
+#define EXTI_PinSource15   ((uint8_t)0x0F)
 
#define IS_EXTI_PIN_SOURCE(PINSOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_EXTI_PIN_SOURCE( PINSOURCE)
+
+Value:
(((PINSOURCE) == EXTI_PinSource0) || \
+
((PINSOURCE) == EXTI_PinSource1) || \
+
((PINSOURCE) == EXTI_PinSource2) || \
+
((PINSOURCE) == EXTI_PinSource3) || \
+
((PINSOURCE) == EXTI_PinSource4) || \
+
((PINSOURCE) == EXTI_PinSource5) || \
+
((PINSOURCE) == EXTI_PinSource6) || \
+
((PINSOURCE) == EXTI_PinSource7) || \
+
((PINSOURCE) == EXTI_PinSource8) || \
+
((PINSOURCE) == EXTI_PinSource9) || \
+
((PINSOURCE) == EXTI_PinSource10) || \
+
((PINSOURCE) == EXTI_PinSource11) || \
+
((PINSOURCE) == EXTI_PinSource12) || \
+
((PINSOURCE) == EXTI_PinSource13) || \
+
((PINSOURCE) == EXTI_PinSource14) || \
+
((PINSOURCE) == EXTI_PinSource15))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___e_x_t_i___pin___sources.map b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.map new file mode 100644 index 0000000..84e68c6 --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_y_s_c_f_g___e_x_t_i___pin___sources.md5 b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.md5 new file mode 100644 index 0000000..6925321 --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.md5 @@ -0,0 +1 @@ +2b65283a9d2d727319fb16ca5d7affe6 \ No newline at end of file diff --git a/group___s_y_s_c_f_g___e_x_t_i___pin___sources.png b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.png new file mode 100644 index 0000000..be5c382 Binary files /dev/null and b/group___s_y_s_c_f_g___e_x_t_i___pin___sources.png differ diff --git a/group___s_y_s_c_f_g___e_x_t_i___port___sources.html b/group___s_y_s_c_f_g___e_x_t_i___port___sources.html new file mode 100644 index 0000000..41d8803 --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___port___sources.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: SYSCFG_EXTI_Port_Sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
SYSCFG_EXTI_Port_Sources
STM32F4xx_StdPeriph_Driver » SYSCFG » SYSCFG_Exported_Constants
+
+
+
+Collaboration diagram for SYSCFG_EXTI_Port_Sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define EXTI_PortSourceGPIOA   ((uint8_t)0x00)
 
+#define EXTI_PortSourceGPIOB   ((uint8_t)0x01)
 
+#define EXTI_PortSourceGPIOC   ((uint8_t)0x02)
 
+#define EXTI_PortSourceGPIOD   ((uint8_t)0x03)
 
+#define EXTI_PortSourceGPIOE   ((uint8_t)0x04)
 
+#define EXTI_PortSourceGPIOF   ((uint8_t)0x05)
 
+#define EXTI_PortSourceGPIOG   ((uint8_t)0x06)
 
+#define EXTI_PortSourceGPIOH   ((uint8_t)0x07)
 
+#define EXTI_PortSourceGPIOI   ((uint8_t)0x08)
 
+#define EXTI_PortSourceGPIOJ   ((uint8_t)0x09)
 
+#define EXTI_PortSourceGPIOK   ((uint8_t)0x0A)
 
#define IS_EXTI_PORT_SOURCE(PORTSOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_EXTI_PORT_SOURCE( PORTSOURCE)
+
+Value:
(((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
+
((PORTSOURCE) == EXTI_PortSourceGPIOK))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___e_x_t_i___port___sources.map b/group___s_y_s_c_f_g___e_x_t_i___port___sources.map new file mode 100644 index 0000000..88d87d7 --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___port___sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_y_s_c_f_g___e_x_t_i___port___sources.md5 b/group___s_y_s_c_f_g___e_x_t_i___port___sources.md5 new file mode 100644 index 0000000..8dbd760 --- /dev/null +++ b/group___s_y_s_c_f_g___e_x_t_i___port___sources.md5 @@ -0,0 +1 @@ +7e0cf81bd562195d7a22aaeec0413eef \ No newline at end of file diff --git a/group___s_y_s_c_f_g___e_x_t_i___port___sources.png b/group___s_y_s_c_f_g___e_x_t_i___port___sources.png new file mode 100644 index 0000000..9e351ba Binary files /dev/null and b/group___s_y_s_c_f_g___e_x_t_i___port___sources.png differ diff --git a/group___s_y_s_c_f_g___exported___constants.html b/group___s_y_s_c_f_g___exported___constants.html new file mode 100644 index 0000000..e0bcecf --- /dev/null +++ b/group___s_y_s_c_f_g___exported___constants.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: SYSCFG_Exported_Constants + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+ + +
+ +
+ +
+
+Modules
+
+
SYSCFG_Exported_Constants
STM32F4xx_StdPeriph_Driver » SYSCFG
+
+
+
+Collaboration diagram for SYSCFG_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + +

+Modules

 SYSCFG_EXTI_Port_Sources
 
 SYSCFG_EXTI_Pin_Sources
 
 SYSCFG_Memory_Remap_Config
 
 SYSCFG_ETHERNET_Media_Interface
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___exported___constants.map b/group___s_y_s_c_f_g___exported___constants.map new file mode 100644 index 0000000..a590ba2 --- /dev/null +++ b/group___s_y_s_c_f_g___exported___constants.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/group___s_y_s_c_f_g___exported___constants.md5 b/group___s_y_s_c_f_g___exported___constants.md5 new file mode 100644 index 0000000..29edfb6 --- /dev/null +++ b/group___s_y_s_c_f_g___exported___constants.md5 @@ -0,0 +1 @@ +95b1ec7a94bea8dc550c29d718f84c42 \ No newline at end of file diff --git a/group___s_y_s_c_f_g___exported___constants.png b/group___s_y_s_c_f_g___exported___constants.png new file mode 100644 index 0000000..7583aac Binary files /dev/null and b/group___s_y_s_c_f_g___exported___constants.png differ diff --git a/group___s_y_s_c_f_g___memory___remap___config.html b/group___s_y_s_c_f_g___memory___remap___config.html new file mode 100644 index 0000000..ce140c8 --- /dev/null +++ b/group___s_y_s_c_f_g___memory___remap___config.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: SYSCFG_Memory_Remap_Config + + + + + + + + + + +
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discoverpixy +
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+ + +
+ +
+ +
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+Macros
+
+
SYSCFG_Memory_Remap_Config
STM32F4xx_StdPeriph_Driver » SYSCFG » SYSCFG_Exported_Constants
+
+
+
+Collaboration diagram for SYSCFG_Memory_Remap_Config:
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+ + +
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+ + + + + + + + + + + + + + +

+Macros

+#define SYSCFG_MemoryRemap_Flash   ((uint8_t)0x00)
 
+#define SYSCFG_MemoryRemap_SystemFlash   ((uint8_t)0x01)
 
+#define SYSCFG_MemoryRemap_SRAM   ((uint8_t)0x03)
 
+#define SYSCFG_MemoryRemap_SDRAM   ((uint8_t)0x04)
 
+#define SYSCFG_MemoryRemap_FSMC   ((uint8_t)0x02)
 
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_SYSCFG_MEMORY_REMAP_CONFING( REMAP)
+
+Value:
(((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+
((REMAP) == SYSCFG_MemoryRemap_FSMC))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___memory___remap___config.map b/group___s_y_s_c_f_g___memory___remap___config.map new file mode 100644 index 0000000..f04832c --- /dev/null +++ b/group___s_y_s_c_f_g___memory___remap___config.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_y_s_c_f_g___memory___remap___config.md5 b/group___s_y_s_c_f_g___memory___remap___config.md5 new file mode 100644 index 0000000..5e8df4b --- /dev/null +++ b/group___s_y_s_c_f_g___memory___remap___config.md5 @@ -0,0 +1 @@ +3de78c990cd86215a1ef51a5e36df8c4 \ No newline at end of file diff --git a/group___s_y_s_c_f_g___memory___remap___config.png b/group___s_y_s_c_f_g___memory___remap___config.png new file mode 100644 index 0000000..5ee87df Binary files /dev/null and b/group___s_y_s_c_f_g___memory___remap___config.png differ diff --git a/group___s_y_s_c_f_g___private___functions.html b/group___s_y_s_c_f_g___private___functions.html new file mode 100644 index 0000000..b15df30 --- /dev/null +++ b/group___s_y_s_c_f_g___private___functions.html @@ -0,0 +1,389 @@ + + + + + + +discoverpixy: SYSCFG_Private_Functions + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
SYSCFG_Private_Functions
STM32F4xx_StdPeriph_Driver » SYSCFG
+
+
+
+Collaboration diagram for SYSCFG_Private_Functions:
+
+
+ + +
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+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SYSCFG_DeInit (void)
 Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values. More...
 
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
 Changes the mapping of the specified pin. More...
 
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
 Enables or disables the Interal FLASH Bank Swapping. More...
 
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 Selects the GPIO pin used as EXTI Line. More...
 
void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
 Selects the ETHERNET media interface. More...
 
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
 Enables or disables the I/O Compensation Cell. More...
 
FlagStatus SYSCFG_GetCompensationCellStatus (void)
 Checks whether the I/O Compensation Cell ready flag is set or not. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
+
+ +

Enables or disables the I/O Compensation Cell.

+
Note
The I/O compensation cell can be used only when the device supply voltage ranges from 2.4 to 3.6 V.
+
Parameters
+ + +
NewStatenew state of the I/O Compensation Cell. This parameter can be one of the following values:
    +
  • ENABLE: I/O compensation cell enabled
    • +
  • DISABLE: I/O compensation cell power-down mode
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_DeInit (void )
+
+ +

Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
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+

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void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
+
+ +

Selects the ETHERNET media interface.

+
Parameters
+ + +
SYSCFG_ETH_MediaInterfacespecifies the Media Interface mode. This parameter can be one of the following values:
    +
  • SYSCFG_ETH_MediaInterface_MII: MII mode selected
    • +
  • SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx,
uint8_t EXTI_PinSourcex 
)
+
+ +

Selects the GPIO pin used as EXTI Line.

+
Parameters
+ + + +
EXTI_PortSourceGPIOx: selects the GPIO port to be used as source for EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) for STM32401xx devices.
EXTI_PinSourcexspecifies the EXTI line to be configured. This parameter can be EXTI_PinSourcex where x can be (0..15, except for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can be (0..7) for STM32F42xxx/43xxx devices.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
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+ + + + + + + + +
FlagStatus SYSCFG_GetCompensationCellStatus (void )
+
+ +

Checks whether the I/O Compensation Cell ready flag is set or not.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thenew state of the I/O Compensation Cell ready flag (SET or RESET)
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
+
+ +

Changes the mapping of the specified pin.

+
Parameters
+ + +
SYSCFG_Memoryselects the memory remapping. This parameter can be one of the following values:
    +
  • SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
    • +
  • SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
    • +
  • SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
    • +
  • SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
+
+ +

Enables or disables the Interal FLASH Bank Swapping.

+
Note
This function can be used only for STM32F42xxx/43xxx devices.
+
Parameters
+ + +
NewStatenew state of Interal FLASH Bank swapping. This parameter can be one of the following values:
    +
  • ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
    • +
  • DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___s_y_s_c_f_g___private___functions.map b/group___s_y_s_c_f_g___private___functions.map new file mode 100644 index 0000000..43647ca --- /dev/null +++ b/group___s_y_s_c_f_g___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___s_y_s_c_f_g___private___functions.md5 b/group___s_y_s_c_f_g___private___functions.md5 new file mode 100644 index 0000000..b13c891 --- /dev/null +++ b/group___s_y_s_c_f_g___private___functions.md5 @@ -0,0 +1 @@ +2584dc46e32fc51aded53fc1dcb64135 \ No newline at end of file diff --git a/group___s_y_s_c_f_g___private___functions.png b/group___s_y_s_c_f_g___private___functions.png new file mode 100644 index 0000000..ab6fa96 Binary files /dev/null and b/group___s_y_s_c_f_g___private___functions.png differ diff --git a/group___s_y_s_c_f_g___private___functions_gaf2f9faa2df9a59a68ae17fae23bc478e_cgraph.map b/group___s_y_s_c_f_g___private___functions_gaf2f9faa2df9a59a68ae17fae23bc478e_cgraph.map new file mode 100644 index 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b/group___s_y_s_c_f_g_gafedab1f64cef720aeafeafd409ba6ae7_icgraph.png differ diff --git a/group___selection___protection___mode.html b/group___selection___protection___mode.html new file mode 100644 index 0000000..68667f1 --- /dev/null +++ b/group___selection___protection___mode.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: Selection_Protection_Mode + + + + + + + + + + +
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+
discoverpixy +
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+Macros
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+
Selection_Protection_Mode
STM32F4xx_StdPeriph_Driver » RAMFUNC » FLASH_Exported_Constants
+
+
+
+Collaboration diagram for Selection_Protection_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define OB_PcROP_Disable   ((uint8_t)0x00)
 
#define OB_PcROP_Enable   ((uint8_t)0x80)
 
+#define IS_OB_PCROP_SELECT(PCROP)   (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define OB_PcROP_Disable   ((uint8_t)0x00)
+
+

Disabled PcROP, nWPRi bits used for Write Protection on sector i

+ +
+
+ +
+
+ + + + +
#define OB_PcROP_Enable   ((uint8_t)0x80)
+
+

Enable PcROP, nWPRi bits used for PCRoP Protection on sector i

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___selection___protection___mode.map b/group___selection___protection___mode.map new file mode 100644 index 0000000..4e4ffed --- /dev/null +++ b/group___selection___protection___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___selection___protection___mode.md5 b/group___selection___protection___mode.md5 new file mode 100644 index 0000000..a36d525 --- /dev/null +++ b/group___selection___protection___mode.md5 @@ -0,0 +1 @@ +f6b8a762778695f16930bf51b08b07c7 \ No newline at end of file diff --git a/group___selection___protection___mode.png b/group___selection___protection___mode.png new file mode 100644 index 0000000..1361c0f Binary files /dev/null and b/group___selection___protection___mode.png differ diff --git a/group___self___test__selection.html b/group___self___test__selection.html new file mode 100644 index 0000000..66cf281 --- /dev/null +++ b/group___self___test__selection.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: Self_Test_selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
Self_Test_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Self_Test_selection:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define LIS302DL_SELFTEST_NORMAL   ((uint8_t)0x00)
 
+#define LIS302DL_SELFTEST_P   ((uint8_t)0x10)
 
+#define LIS302DL_SELFTEST_M   ((uint8_t)0x08)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Modules | +Classes | +Macros | +Functions
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+
TIM
STM32F4xx_StdPeriph_Driver
+
+
+ +

TIM driver modules. +More...

+
+Collaboration diagram for TIM:
+
+
+ + +
+
+ + + + + + +

+Modules

 TIM_Exported_constants
 
 TIM_Private_Functions
 
+ + + + + + + + + + + + + +

+Classes

struct  TIM_TimeBaseInitTypeDef
 TIM Time Base Init structure definition. More...
 
struct  TIM_OCInitTypeDef
 TIM Output Compare Init structure definition. More...
 
struct  TIM_ICInitTypeDef
 TIM Input Capture Init structure definition. More...
 
struct  TIM_BDTRInitTypeDef
 BDTR structure definition. More...
 
+ + + + + + + + + + + + + +

+Macros

+#define SMCR_ETR_MASK   ((uint16_t)0x00FF)
 
+#define CCMR_OFFSET   ((uint16_t)0x0018)
 
+#define CCER_CCE_SET   ((uint16_t)0x0001)
 
+#define CCER_CCNE_SET   ((uint16_t)0x0004)
 
+#define CCMR_OC13M_MASK   ((uint16_t)0xFF8F)
 
+#define CCMR_OC24M_MASK   ((uint16_t)0x8FFF)
 
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+Functions

void TIM_DeInit (TIM_TypeDef *TIMx)
 Deinitializes the TIMx peripheral registers to their default reset values. More...
 
void TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct. More...
 
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Fills each TIM_TimeBaseInitStruct member with its default value. More...
 
void TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
 Configures the TIMx Prescaler. More...
 
void TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
 Specifies the TIMx Counter Mode to be used. More...
 
void TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
 Sets the TIMx Counter Register value. More...
 
void TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
 Sets the TIMx Autoreload Register value. More...
 
uint32_t TIM_GetCounter (TIM_TypeDef *TIMx)
 Gets the TIMx Counter value. More...
 
uint16_t TIM_GetPrescaler (TIM_TypeDef *TIMx)
 Gets the TIMx Prescaler value. More...
 
void TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or Disables the TIMx Update event. More...
 
void TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
 Configures the TIMx Update Request Interrupt source. More...
 
void TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables TIMx peripheral Preload register on ARR. More...
 
void TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
 Selects the TIMx's One Pulse Mode. More...
 
void TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
 Sets the TIMx Clock Division value. More...
 
void TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the specified TIM peripheral. More...
 
void TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
 Fills each TIM_OCInitStruct member with its default value. More...
 
void TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
 Selects the TIM Output Compare Mode. More...
 
void TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
 Sets the TIMx Capture Compare1 Register value. More...
 
void TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
 Sets the TIMx Capture Compare2 Register value. More...
 
void TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
 Sets the TIMx Capture Compare3 Register value. More...
 
void TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
 Sets the TIMx Capture Compare4 Register value. More...
 
void TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 1 waveform to active or inactive level. More...
 
void TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 2 waveform to active or inactive level. More...
 
void TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 3 waveform to active or inactive level. More...
 
void TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 4 waveform to active or inactive level. More...
 
void TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR1. More...
 
void TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR2. More...
 
void TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR3. More...
 
void TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR4. More...
 
void TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 1 Fast feature. More...
 
void TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 2 Fast feature. More...
 
void TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 3 Fast feature. More...
 
void TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 4 Fast feature. More...
 
void TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF1 signal on an external event. More...
 
void TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF2 signal on an external event. More...
 
void TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF3 signal on an external event. More...
 
void TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF4 signal on an external event. More...
 
void TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 1 polarity. More...
 
void TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 1N polarity. More...
 
void TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 2 polarity. More...
 
void TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 2N polarity. More...
 
void TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 3 polarity. More...
 
void TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 3N polarity. More...
 
void TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 4 polarity. More...
 
void TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
 Enables or disables the TIM Capture Compare Channel x. More...
 
void TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
 Enables or disables the TIM Capture Compare Channel xN. More...
 
void TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct. More...
 
void TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
 Fills each TIM_ICInitStruct member with its default value. More...
 
void TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal. More...
 
uint32_t TIM_GetCapture1 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 1 value. More...
 
uint32_t TIM_GetCapture2 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 2 value. More...
 
uint32_t TIM_GetCapture3 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 3 value. More...
 
uint32_t TIM_GetCapture4 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 4 value. More...
 
void TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 1 prescaler. More...
 
void TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 2 prescaler. More...
 
void TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 3 prescaler. More...
 
void TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 4 prescaler. More...
 
void TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). More...
 
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Fills each TIM_BDTRInitStruct member with its default value. More...
 
void TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIM peripheral Main Outputs. More...
 
void TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIM peripheral Commutation event. More...
 
void TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
 Sets or Resets the TIM peripheral Capture Compare Preload Control bit. More...
 
void TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
 Enables or disables the specified TIM interrupts. More...
 
void TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
 Configures the TIMx event to be generate by software. More...
 
FlagStatus TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Checks whether the specified TIM flag is set or not. More...
 
void TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Clears the TIMx's pending flags. More...
 
ITStatus TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Checks whether the TIM interrupt has occurred or not. More...
 
void TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Clears the TIMx's interrupt pending bits. More...
 
void TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
 Configures the TIMx's DMA interface. More...
 
void TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
 Enables or disables the TIMx's DMA Requests. More...
 
void TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIMx peripheral Capture Compare DMA source. More...
 
void TIM_InternalClockConfig (TIM_TypeDef *TIMx)
 Configures the TIMx internal Clock. More...
 
void TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Configures the TIMx Internal Trigger as External Clock. More...
 
void TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
 Configures the TIMx Trigger as External Clock. More...
 
void TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode1. More...
 
void TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode2. More...
 
void TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Selects the Input Trigger source. More...
 
void TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
 Selects the TIMx Trigger Output Mode. More...
 
void TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
 Selects the TIMx Slave Mode. More...
 
void TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
 Sets or Resets the TIMx Master/Slave Mode. More...
 
void TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the TIMx External Trigger (ETR). More...
 
void TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
 Configures the TIMx Encoder Interface. More...
 
void TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIMx's Hall sensor interface. More...
 
void TIM_RemapConfig (TIM_TypeDef *TIMx, uint16_t TIM_Remap)
 Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. More...
 
+

Detailed Description

+

TIM driver modules.

+

Function Documentation

+ +
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void TIM_ARRPreloadConfig (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables TIMx peripheral Preload register on ARR.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
NewStatenew state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
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+
+ +
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+ +
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+ + + + + + + + + + + + + + + + + + +
void TIM_BDTRConfig (TIM_TypeDef * TIMx,
TIM_BDTRInitTypeDef * TIM_BDTRInitStruct 
)
+
+ +

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM
TIM_BDTRInitStructpointer to a TIM_BDTRInitTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
+
+
+
Return values
+ + +
None
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+ +
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+ +
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+ + + + + + + + +
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef * TIM_BDTRInitStruct)
+
+ +

Fills each TIM_BDTRInitStruct member with its default value.

+
Parameters
+ + +
TIM_BDTRInitStructpointer to a TIM_BDTRInitTypeDef structure which will be initialized.
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+
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Return values
+ + +
None
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void TIM_CCPreloadControl (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Sets or Resets the TIM peripheral Capture Compare Preload Control bit.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral
NewStatenew state of the Capture Compare Preload Control bit This parameter can be: ENABLE or DISABLE.
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Return values
+ + +
None
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void TIM_CCxCmd (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_CCx 
)
+
+ +

Enables or disables the TIM Capture Compare Channel x.

+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
  • TIM_Channel_4: TIM Channel 4
    • +
+
TIM_CCxspecifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
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Return values
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None
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void TIM_CCxNCmd (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_CCxN 
)
+
+ +

Enables or disables the TIM Capture Compare Channel xN.

+
Parameters
+ + + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
+
TIM_CCxNspecifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
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Return values
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None
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void TIM_ClearFlag (TIM_TypeDef * TIMx,
uint16_t TIM_FLAG 
)
+
+ +

Clears the TIMx's pending flags.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_FLAGspecifies the flag bit to clear. This parameter can be any combination of the following values:
    +
  • TIM_FLAG_Update: TIM update Flag
    • +
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
    • +
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
    • +
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
    • +
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
    • +
  • TIM_FLAG_COM: TIM Commutation Flag
    • +
  • TIM_FLAG_Trigger: TIM Trigger Flag
    • +
  • TIM_FLAG_Break: TIM Break Flag
    • +
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
    • +
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
    • +
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
    • +
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
    • +
+
+
+
+
Note
TIM6 and TIM7 can have only one update flag.
+
+TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
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Return values
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None
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void TIM_ClearITPendingBit (TIM_TypeDef * TIMx,
uint16_t TIM_IT 
)
+
+ +

Clears the TIMx's interrupt pending bits.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_ITspecifies the pending bit to clear. This parameter can be any combination of the following values:
    +
  • TIM_IT_Update: TIM1 update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
TIM6 and TIM7 can generate only an update interrupt.
+
+TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
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Return values
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None
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void TIM_ClearOC1Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF1 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
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Return values
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None
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void TIM_ClearOC2Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF2 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
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Return values
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None
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void TIM_ClearOC3Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF3 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
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+ +
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void TIM_ClearOC4Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF4 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_Cmd (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified TIM peripheral.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIMx peripheral.
NewStatenew state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_CounterModeConfig (TIM_TypeDef * TIMx,
uint16_t TIM_CounterMode 
)
+
+ +

Specifies the TIMx Counter Mode to be used.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_CounterModespecifies the Counter Mode to be used This parameter can be one of the following values:
    +
  • TIM_CounterMode_Up: TIM Up Counting Mode
    • +
  • TIM_CounterMode_Down: TIM Down Counting Mode
    • +
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
    • +
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
    • +
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_CtrlPWMOutputs (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIM peripheral Main Outputs.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral.
NewStatenew state of the TIM peripheral Main Outputs. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_DeInit (TIM_TypeDef * TIMx)
+
+ +

Deinitializes the TIMx peripheral registers to their default reset values.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + +
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+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_DMACmd (TIM_TypeDef * TIMx,
uint16_t TIM_DMASource,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIMx's DMA Requests.

+
Parameters
+ + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
TIM_DMASourcespecifies the DMA Request sources. This parameter can be any combination of the following values:
    +
  • TIM_DMA_Update: TIM update Interrupt source
    • +
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
    • +
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
    • +
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
    • +
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
    • +
  • TIM_DMA_COM: TIM Commutation DMA source
    • +
  • TIM_DMA_Trigger: TIM Trigger DMA source
    • +
+
NewStatenew state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_DMAConfig (TIM_TypeDef * TIMx,
uint16_t TIM_DMABase,
uint16_t TIM_DMABurstLength 
)
+
+ +

Configures the TIMx's DMA interface.

+
Parameters
+ + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_DMABaseDMA Base address. This parameter can be one of the following values:
    +
  • TIM_DMABase_CR1
    • +
  • TIM_DMABase_CR2
    • +
  • TIM_DMABase_SMCR
    • +
  • TIM_DMABase_DIER
    • +
  • TIM1_DMABase_SR
    • +
  • TIM_DMABase_EGR
    • +
  • TIM_DMABase_CCMR1
    • +
  • TIM_DMABase_CCMR2
    • +
  • TIM_DMABase_CCER
    • +
  • TIM_DMABase_CNT
    • +
  • TIM_DMABase_PSC
    • +
  • TIM_DMABase_ARR
    • +
  • TIM_DMABase_RCR
    • +
  • TIM_DMABase_CCR1
    • +
  • TIM_DMABase_CCR2
    • +
  • TIM_DMABase_CCR3
    • +
  • TIM_DMABase_CCR4
    • +
  • TIM_DMABase_BDTR
    • +
  • TIM_DMABase_DCR
    • +
+
TIM_DMABurstLengthDMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_EncoderInterfaceConfig (TIM_TypeDef * TIMx,
uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity,
uint16_t TIM_IC2Polarity 
)
+
+ +

Configures the TIMx Encoder Interface.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_EncoderModespecifies the TIMx Encoder Mode. This parameter can be one of the following values:
    +
  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
    • +
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
    • +
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
    • +
+
TIM_IC1Polarityspecifies the IC1 Polarity This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Falling: IC Falling edge.
    • +
  • TIM_ICPolarity_Rising: IC Rising edge.
    • +
+
TIM_IC2Polarityspecifies the IC2 Polarity This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Falling: IC Falling edge.
    • +
  • TIM_ICPolarity_Rising: IC Rising edge.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_ETRClockMode1Config (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the External clock Mode1.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_ETRClockMode2Config (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the External clock Mode2.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_ETRConfig (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the TIMx External Trigger (ETR).

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC1Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 1 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC1REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC2Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 2 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC2REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC3Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 3 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC3REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC4Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 4 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC4REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_GenerateEvent (TIM_TypeDef * TIMx,
uint16_t TIM_EventSource 
)
+
+ +

Configures the TIMx event to be generate by software.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_EventSourcespecifies the event source. This parameter can be one or more of the following values:
    +
  • TIM_EventSource_Update: Timer update Event source
    • +
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source
    • +
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source
    • +
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source
    • +
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source
    • +
  • TIM_EventSource_COM: Timer COM event source
    • +
  • TIM_EventSource_Trigger: Timer Trigger Event source
    • +
  • TIM_EventSource_Break: Timer Break event source
    • +
+
+
+
+
Note
TIM6 and TIM7 can only generate an update event.
+
+TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture1 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 1 value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 1 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture2 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 2 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 2 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture3 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 3 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 3 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture4 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 4 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 4 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCounter (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Counter value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
CounterRegister value
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus TIM_GetFlagStatus (TIM_TypeDef * TIMx,
uint16_t TIM_FLAG 
)
+
+ +

Checks whether the specified TIM flag is set or not.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • TIM_FLAG_Update: TIM update Flag
    • +
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
    • +
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
    • +
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
    • +
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
    • +
  • TIM_FLAG_COM: TIM Commutation Flag
    • +
  • TIM_FLAG_Trigger: TIM Trigger Flag
    • +
  • TIM_FLAG_Break: TIM Break Flag
    • +
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
    • +
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
    • +
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
    • +
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
    • +
+
+
+
+
Note
TIM6 and TIM7 can have only one update flag.
+
+TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
Thenew state of TIM_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus TIM_GetITStatus (TIM_TypeDef * TIMx,
uint16_t TIM_IT 
)
+
+ +

Checks whether the TIM interrupt has occurred or not.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_ITspecifies the TIM interrupt source to check. This parameter can be one of the following values:
    +
  • TIM_IT_Update: TIM update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
TIM6 and TIM7 can generate only an update interrupt.
+
+TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
Thenew state of the TIM_IT(SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t TIM_GetPrescaler (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Prescaler value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
PrescalerRegister value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ICInit (TIM_TypeDef * TIMx,
TIM_ICInitTypeDef * TIM_ICInitStruct 
)
+
+ +

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void TIM_ICStructInit (TIM_ICInitTypeDef * TIM_ICInitStruct)
+
+ +

Fills each TIM_ICInitStruct member with its default value.

+
Parameters
+ + +
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_InternalClockConfig (TIM_TypeDef * TIMx)
+
+ +

Configures the TIMx internal Clock.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_ITConfig (TIM_TypeDef * TIMx,
uint16_t TIM_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified TIM interrupts.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIMx peripheral.
TIM_ITspecifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • TIM_IT_Update: TIM update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
+
+For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
+
+For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can be used: TIM_IT_Update or TIM_IT_CC1
+
+TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
+
Parameters
+ + +
NewStatenew state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ITRxExternalClockConfig (TIM_TypeDef * TIMx,
uint16_t TIM_InputTriggerSource 
)
+
+ +

Configures the TIMx Internal Trigger as External Clock.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_InputTriggerSourceTrigger source. This parameter can be one of the following values:
    +
  • TIM_TS_ITR0: Internal Trigger 0
    • +
  • TIM_TS_ITR1: Internal Trigger 1
    • +
  • TIM_TS_ITR2: Internal Trigger 2
    • +
  • TIM_TS_ITR3: Internal Trigger 3
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 1 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 1N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC1N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 1 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCPolarityspecifies the OC1 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR1.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 2 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 2N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC2N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 2 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC2 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR2.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 3 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 3N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC3N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 3 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC3 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR3.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 4 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 4 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC4 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR4.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_OCStructInit (TIM_OCInitTypeDef * TIM_OCInitStruct)
+
+ +

Fills each TIM_OCInitStruct member with its default value.

+
Parameters
+ + +
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_PrescalerConfig (TIM_TypeDef * TIMx,
uint16_t Prescaler,
uint16_t TIM_PSCReloadMode 
)
+
+ +

Configures the TIMx Prescaler.

+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Prescalerspecifies the Prescaler Register value
TIM_PSCReloadModespecifies the TIM Prescaler Reload mode This parameter can be one of the following values:
    +
  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
    • +
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_PWMIConfig (TIM_TypeDef * TIMx,
TIM_ICInitTypeDef * TIM_ICInitStruct 
)
+
+ +

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM peripheral.
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_RemapConfig (TIM_TypeDef * TIMx,
uint16_t TIM_Remap 
)
+
+ +

Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.

+
Parameters
+ + + +
TIMxwhere x can be 2, 5 or 11 to select the TIM peripheral.
TIM_Remapspecifies the TIM input remapping source. This parameter can be one of the following values:
    +
  • TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
    • +
  • TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
    • +
  • TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
    • +
  • TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
    • +
  • TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
    • +
  • TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
    • +
  • TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
    • +
  • TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
    • +
  • TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
    • +
  • TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock (HSE divided by a programmable prescaler)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectCCDMA (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Selects the TIMx peripheral Capture Compare DMA source.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
NewStatenew state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectCOM (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Selects the TIM peripheral Commutation event.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral
NewStatenew state of the Commutation event. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectHallSensor (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIMx's Hall sensor interface.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
NewStatenew state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectInputTrigger (TIM_TypeDef * TIMx,
uint16_t TIM_InputTriggerSource 
)
+
+ +

Selects the Input Trigger source.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the TIM peripheral.
TIM_InputTriggerSourceThe Input Trigger source. This parameter can be one of the following values:
    +
  • TIM_TS_ITR0: Internal Trigger 0
    • +
  • TIM_TS_ITR1: Internal Trigger 1
    • +
  • TIM_TS_ITR2: Internal Trigger 2
    • +
  • TIM_TS_ITR3: Internal Trigger 3
    • +
  • TIM_TS_TI1F_ED: TI1 Edge Detector
    • +
  • TIM_TS_TI1FP1: Filtered Timer Input 1
    • +
  • TIM_TS_TI2FP2: Filtered Timer Input 2
    • +
  • TIM_TS_ETRF: External Trigger input
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectMasterSlaveMode (TIM_TypeDef * TIMx,
uint16_t TIM_MasterSlaveMode 
)
+
+ +

Sets or Resets the TIMx Master/Slave Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_MasterSlaveModespecifies the Timer Master Slave Mode. This parameter can be one of the following values:
    +
  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO)
    • +
  • TIM_MasterSlaveMode_Disable: No action
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_SelectOCxM (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_OCMode 
)
+
+ +

Selects the TIM Output Compare Mode.

+
Note
This function disables the selected channel before changing the Output Compare Mode. If needed, user has to enable this channel using TIM_CCxCmd() and TIM_CCxNCmd() functions.
+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
  • TIM_Channel_4: TIM Channel 4
    • +
+
TIM_OCModespecifies the TIM Output Compare Mode. This parameter can be one of the following values:
    +
  • TIM_OCMode_Timing
    • +
  • TIM_OCMode_Active
    • +
  • TIM_OCMode_Toggle
    • +
  • TIM_OCMode_PWM1
    • +
  • TIM_OCMode_PWM2
    • +
  • TIM_ForcedAction_Active
    • +
  • TIM_ForcedAction_InActive
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectOnePulseMode (TIM_TypeDef * TIMx,
uint16_t TIM_OPMode 
)
+
+ +

Selects the TIMx's One Pulse Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_OPModespecifies the OPM Mode to be used. This parameter can be one of the following values:
    +
  • TIM_OPMode_Single
    • +
  • TIM_OPMode_Repetitive
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectOutputTrigger (TIM_TypeDef * TIMx,
uint16_t TIM_TRGOSource 
)
+
+ +

Selects the TIMx Trigger Output Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
TIM_TRGOSourcespecifies the Trigger Output source. This parameter can be one of the following values:
+
+
+
    +
  • For all TIMx
      +
    • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
      • +
    +
    • +
  • For all TIMx except TIM6 and TIM7
      +
    • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs(TRGO)
      • +
    • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
      • +
    +
    Return values
    + + +
    None
    +
    +
    +
    • +
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectSlaveMode (TIM_TypeDef * TIMx,
uint16_t TIM_SlaveMode 
)
+
+ +

Selects the TIMx Slave Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_SlaveModespecifies the Timer Slave Mode. This parameter can be one of the following values:
    +
  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize the counter and triggers an update of the registers
    • +
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
    • +
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
    • +
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetAutoreload (TIM_TypeDef * TIMx,
uint32_t Autoreload 
)
+
+ +

Sets the TIMx Autoreload Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Autoreloadspecifies the Autoreload register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetClockDivision (TIM_TypeDef * TIMx,
uint16_t TIM_CKD 
)
+
+ +

Sets the TIMx Clock Division value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_CKDspecifies the clock division value. This parameter can be one of the following value:
    +
  • TIM_CKD_DIV1: TDTS = Tck_tim
    • +
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim
    • +
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare1 (TIM_TypeDef * TIMx,
uint32_t Compare1 
)
+
+ +

Sets the TIMx Capture Compare1 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
Compare1specifies the Capture Compare1 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare2 (TIM_TypeDef * TIMx,
uint32_t Compare2 
)
+
+ +

Sets the TIMx Capture Compare2 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
Compare2specifies the Capture Compare2 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare3 (TIM_TypeDef * TIMx,
uint32_t Compare3 
)
+
+ +

Sets the TIMx Capture Compare3 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare3specifies the Capture Compare3 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare4 (TIM_TypeDef * TIMx,
uint32_t Compare4 
)
+
+ +

Sets the TIMx Capture Compare4 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare4specifies the Capture Compare4 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCounter (TIM_TypeDef * TIMx,
uint32_t Counter 
)
+
+ +

Sets the TIMx Counter Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Counterspecifies the Counter register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC1Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 1 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture1 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC2Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 2 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture2 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC3Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 3 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture3 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC4Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 4 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_TimeBaseInit (TIM_TypeDef * TIMx,
TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct 
)
+
+ +

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_TimeBaseInitStructpointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct)
+
+ +

Fills each TIM_TimeBaseInitStruct member with its default value.

+
Parameters
+ + +
TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_TIxExternalClockConfig (TIM_TypeDef * TIMx,
uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity,
uint16_t ICFilter 
)
+
+ +

Configures the TIMx Trigger as External Clock.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the TIM peripheral.
TIM_TIxExternalCLKSourceTrigger source. This parameter can be one of the following values:
    +
  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
    • +
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
    • +
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
    • +
+
TIM_ICPolarityspecifies the TIx Polarity. This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Rising
    • +
  • TIM_ICPolarity_Falling
    • +
+
ICFilterspecifies the filter value. This parameter must be a value between 0x0 and 0xF.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_UpdateDisableConfig (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or Disables the TIMx Update event.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
NewStatenew state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_UpdateRequestConfig (TIM_TypeDef * TIMx,
uint16_t TIM_UpdateSource 
)
+
+ +

Configures the TIMx Update Request Interrupt source.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_UpdateSourcespecifies the Update source. This parameter can be one of the following values:
    +
  • TIM_UpdateSource_Global: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
    • +
  • TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m.map b/group___t_i_m.map new file mode 100644 index 0000000..b4b7782 --- /dev/null +++ b/group___t_i_m.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___t_i_m.md5 b/group___t_i_m.md5 new file mode 100644 index 0000000..ddc1416 --- /dev/null +++ b/group___t_i_m.md5 @@ -0,0 +1 @@ +89632d5977eacc41aa9f573f4a7a19ed \ No newline at end of file diff --git a/group___t_i_m.png b/group___t_i_m.png new file mode 100644 index 0000000..3e442b4 Binary files /dev/null and b/group___t_i_m.png differ diff --git a/group___t_i_m___a_o_e___bit___set___reset.html b/group___t_i_m___a_o_e___bit___set___reset.html new file mode 100644 index 0000000..fe719c4 --- /dev/null +++ b/group___t_i_m___a_o_e___bit___set___reset.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_AOE_Bit_Set_Reset + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_AOE_Bit_Set_Reset
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_AOE_Bit_Set_Reset:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_AutomaticOutput_Enable   ((uint16_t)0x4000)
 
+#define TIM_AutomaticOutput_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_AUTOMATIC_OUTPUT_STATE( STATE)
+
+Value:
(((STATE) == TIM_AutomaticOutput_Enable) || \
+
((STATE) == TIM_AutomaticOutput_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___a_o_e___bit___set___reset.map b/group___t_i_m___a_o_e___bit___set___reset.map new file mode 100644 index 0000000..05ae850 --- /dev/null +++ b/group___t_i_m___a_o_e___bit___set___reset.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___a_o_e___bit___set___reset.md5 b/group___t_i_m___a_o_e___bit___set___reset.md5 new file mode 100644 index 0000000..fb7fee7 --- /dev/null +++ b/group___t_i_m___a_o_e___bit___set___reset.md5 @@ -0,0 +1 @@ +fd7fd2d2696a059b5b7bea93d50fcb8f \ No newline at end of file diff --git a/group___t_i_m___a_o_e___bit___set___reset.png b/group___t_i_m___a_o_e___bit___set___reset.png new file mode 100644 index 0000000..5c80639 Binary files /dev/null and b/group___t_i_m___a_o_e___bit___set___reset.png differ diff --git a/group___t_i_m___break___input__enable__disable.html b/group___t_i_m___break___input__enable__disable.html new file mode 100644 index 0000000..e60c78c --- /dev/null +++ b/group___t_i_m___break___input__enable__disable.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Break_Input_enable_disable + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Break_Input_enable_disable
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Break_Input_enable_disable:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_Break_Enable   ((uint16_t)0x1000)
 
+#define TIM_Break_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_BREAK_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_BREAK_STATE( STATE)
+
+Value:
(((STATE) == TIM_Break_Enable) || \
+
((STATE) == TIM_Break_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___break___input__enable__disable.map b/group___t_i_m___break___input__enable__disable.map new file mode 100644 index 0000000..7281dff --- /dev/null +++ b/group___t_i_m___break___input__enable__disable.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___break___input__enable__disable.md5 b/group___t_i_m___break___input__enable__disable.md5 new file mode 100644 index 0000000..08d54e0 --- /dev/null +++ b/group___t_i_m___break___input__enable__disable.md5 @@ -0,0 +1 @@ +d97c1f121d85dfa57f2f1d836b1120c8 \ No newline at end of file diff --git a/group___t_i_m___break___input__enable__disable.png b/group___t_i_m___break___input__enable__disable.png new file mode 100644 index 0000000..2584c2c Binary files /dev/null and b/group___t_i_m___break___input__enable__disable.png differ diff --git a/group___t_i_m___break___polarity.html b/group___t_i_m___break___polarity.html new file mode 100644 index 0000000..736c0ac --- /dev/null +++ b/group___t_i_m___break___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Break_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Break_Polarity
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Break_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_BreakPolarity_Low   ((uint16_t)0x0000)
 
+#define TIM_BreakPolarity_High   ((uint16_t)0x2000)
 
#define IS_TIM_BREAK_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_BREAK_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == TIM_BreakPolarity_Low) || \
+
((POLARITY) == TIM_BreakPolarity_High))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___break___polarity.map b/group___t_i_m___break___polarity.map new file mode 100644 index 0000000..e10690b --- /dev/null +++ b/group___t_i_m___break___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___break___polarity.md5 b/group___t_i_m___break___polarity.md5 new file mode 100644 index 0000000..6f18c3f --- /dev/null +++ b/group___t_i_m___break___polarity.md5 @@ -0,0 +1 @@ +c82c2ef48571956a89e3b96ff9dbb33e \ No newline at end of file diff --git a/group___t_i_m___break___polarity.png b/group___t_i_m___break___polarity.png new file mode 100644 index 0000000..ed52167 Binary files /dev/null and b/group___t_i_m___break___polarity.png differ diff --git a/group___t_i_m___capture___compare___n___state.html b/group___t_i_m___capture___compare___n___state.html new file mode 100644 index 0000000..9b7622f --- /dev/null +++ b/group___t_i_m___capture___compare___n___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Capture_Compare_N_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Capture_Compare_N_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Capture_Compare_N_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_CCxN_Enable   ((uint16_t)0x0004)
 
+#define TIM_CCxN_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_CCXN(CCXN)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_CCXN( CCXN)
+
+Value:
(((CCXN) == TIM_CCxN_Enable) || \
+
((CCXN) == TIM_CCxN_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___capture___compare___n___state.map b/group___t_i_m___capture___compare___n___state.map new file mode 100644 index 0000000..ac80480 --- /dev/null +++ b/group___t_i_m___capture___compare___n___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___capture___compare___n___state.md5 b/group___t_i_m___capture___compare___n___state.md5 new file mode 100644 index 0000000..38cd05f --- /dev/null +++ b/group___t_i_m___capture___compare___n___state.md5 @@ -0,0 +1 @@ +71b710a0198365c6451b1802f8226287 \ No newline at end of file diff --git a/group___t_i_m___capture___compare___n___state.png b/group___t_i_m___capture___compare___n___state.png new file mode 100644 index 0000000..a5e6fd1 Binary files /dev/null and b/group___t_i_m___capture___compare___n___state.png differ diff --git a/group___t_i_m___capture___compare___state.html b/group___t_i_m___capture___compare___state.html new file mode 100644 index 0000000..d2a597e --- /dev/null +++ b/group___t_i_m___capture___compare___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Capture_Compare_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Capture_Compare_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Capture_Compare_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_CCx_Enable   ((uint16_t)0x0001)
 
+#define TIM_CCx_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_CCX(CCX)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_CCX( CCX)
+
+Value:
(((CCX) == TIM_CCx_Enable) || \
+
((CCX) == TIM_CCx_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___capture___compare___state.map b/group___t_i_m___capture___compare___state.map new file mode 100644 index 0000000..7f0ad51 --- /dev/null +++ b/group___t_i_m___capture___compare___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___capture___compare___state.md5 b/group___t_i_m___capture___compare___state.md5 new file mode 100644 index 0000000..701eb74 --- /dev/null +++ b/group___t_i_m___capture___compare___state.md5 @@ -0,0 +1 @@ +652757e277feb0394b2c9944f3e20913 \ No newline at end of file diff --git a/group___t_i_m___capture___compare___state.png b/group___t_i_m___capture___compare___state.png new file mode 100644 index 0000000..97605ae Binary files /dev/null and b/group___t_i_m___capture___compare___state.png differ diff --git a/group___t_i_m___channel.html b/group___t_i_m___channel.html new file mode 100644 index 0000000..87d6439 --- /dev/null +++ b/group___t_i_m___channel.html @@ -0,0 +1,182 @@ + + + + + + +discoverpixy: TIM_Channel + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Channel
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Channel:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define TIM_Channel_1   ((uint16_t)0x0000)
 
+#define TIM_Channel_2   ((uint16_t)0x0004)
 
+#define TIM_Channel_3   ((uint16_t)0x0008)
 
+#define TIM_Channel_4   ((uint16_t)0x000C)
 
#define IS_TIM_CHANNEL(CHANNEL)
 
#define IS_TIM_PWMI_CHANNEL(CHANNEL)
 
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == TIM_Channel_1) || \
+
((CHANNEL) == TIM_Channel_2) || \
+
((CHANNEL) == TIM_Channel_3) || \
+
((CHANNEL) == TIM_Channel_4))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_COMPLEMENTARY_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == TIM_Channel_1) || \
+
((CHANNEL) == TIM_Channel_2) || \
+
((CHANNEL) == TIM_Channel_3))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_PWMI_CHANNEL( CHANNEL)
+
+Value:
(((CHANNEL) == TIM_Channel_1) || \
+
((CHANNEL) == TIM_Channel_2))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___channel.map b/group___t_i_m___channel.map new file mode 100644 index 0000000..0fe0fe2 --- /dev/null +++ b/group___t_i_m___channel.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___channel.md5 b/group___t_i_m___channel.md5 new file mode 100644 index 0000000..ee67750 --- /dev/null +++ b/group___t_i_m___channel.md5 @@ -0,0 +1 @@ +a1a1ec7c99387f2018054c8ef4de0ccc \ No newline at end of file diff --git a/group___t_i_m___channel.png b/group___t_i_m___channel.png new file mode 100644 index 0000000..4801202 Binary files /dev/null and b/group___t_i_m___channel.png differ diff --git a/group___t_i_m___clock___division___c_k_d.html b/group___t_i_m___clock___division___c_k_d.html new file mode 100644 index 0000000..b1566c2 --- /dev/null +++ b/group___t_i_m___clock___division___c_k_d.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: TIM_Clock_Division_CKD + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Clock_Division_CKD
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Clock_Division_CKD:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define TIM_CKD_DIV1   ((uint16_t)0x0000)
 
+#define TIM_CKD_DIV2   ((uint16_t)0x0100)
 
+#define TIM_CKD_DIV4   ((uint16_t)0x0200)
 
#define IS_TIM_CKD_DIV(DIV)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_CKD_DIV( DIV)
+
+Value:
(((DIV) == TIM_CKD_DIV1) || \
+
((DIV) == TIM_CKD_DIV2) || \
+
((DIV) == TIM_CKD_DIV4))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___clock___division___c_k_d.map b/group___t_i_m___clock___division___c_k_d.map new file mode 100644 index 0000000..c1f66c1 --- /dev/null +++ b/group___t_i_m___clock___division___c_k_d.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___clock___division___c_k_d.md5 b/group___t_i_m___clock___division___c_k_d.md5 new file mode 100644 index 0000000..59c0760 --- /dev/null +++ b/group___t_i_m___clock___division___c_k_d.md5 @@ -0,0 +1 @@ +80e349bfb9630d1a2c86556d552f8c9f \ No newline at end of file diff --git a/group___t_i_m___clock___division___c_k_d.png b/group___t_i_m___clock___division___c_k_d.png new file mode 100644 index 0000000..28fe95d Binary files /dev/null and b/group___t_i_m___clock___division___c_k_d.png differ diff --git a/group___t_i_m___counter___mode.html b/group___t_i_m___counter___mode.html new file mode 100644 index 0000000..f2ca322 --- /dev/null +++ b/group___t_i_m___counter___mode.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: TIM_Counter_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Counter_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Counter_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define TIM_CounterMode_Up   ((uint16_t)0x0000)
 
+#define TIM_CounterMode_Down   ((uint16_t)0x0010)
 
+#define TIM_CounterMode_CenterAligned1   ((uint16_t)0x0020)
 
+#define TIM_CounterMode_CenterAligned2   ((uint16_t)0x0040)
 
+#define TIM_CounterMode_CenterAligned3   ((uint16_t)0x0060)
 
#define IS_TIM_COUNTER_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_COUNTER_MODE( MODE)
+
+Value:
(((MODE) == TIM_CounterMode_Up) || \
+
((MODE) == TIM_CounterMode_Down) || \
+
((MODE) == TIM_CounterMode_CenterAligned1) || \
+
((MODE) == TIM_CounterMode_CenterAligned2) || \
+
((MODE) == TIM_CounterMode_CenterAligned3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___counter___mode.map b/group___t_i_m___counter___mode.map new file mode 100644 index 0000000..4bfeb6f --- /dev/null +++ b/group___t_i_m___counter___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___counter___mode.md5 b/group___t_i_m___counter___mode.md5 new file mode 100644 index 0000000..a6c9646 --- /dev/null +++ b/group___t_i_m___counter___mode.md5 @@ -0,0 +1 @@ +6c0502e17692cc8038b089bd3e4ca21c \ No newline at end of file diff --git a/group___t_i_m___counter___mode.png b/group___t_i_m___counter___mode.png new file mode 100644 index 0000000..f03e79a Binary files /dev/null and b/group___t_i_m___counter___mode.png differ diff --git a/group___t_i_m___d_m_a___base__address.html b/group___t_i_m___d_m_a___base__address.html new file mode 100644 index 0000000..aca5e9a --- /dev/null +++ b/group___t_i_m___d_m_a___base__address.html @@ -0,0 +1,205 @@ + + + + + + +discoverpixy: TIM_DMA_Base_address + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_DMA_Base_address
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_DMA_Base_address:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_DMABase_CR1   ((uint16_t)0x0000)
 
+#define TIM_DMABase_CR2   ((uint16_t)0x0001)
 
+#define TIM_DMABase_SMCR   ((uint16_t)0x0002)
 
+#define TIM_DMABase_DIER   ((uint16_t)0x0003)
 
+#define TIM_DMABase_SR   ((uint16_t)0x0004)
 
+#define TIM_DMABase_EGR   ((uint16_t)0x0005)
 
+#define TIM_DMABase_CCMR1   ((uint16_t)0x0006)
 
+#define TIM_DMABase_CCMR2   ((uint16_t)0x0007)
 
+#define TIM_DMABase_CCER   ((uint16_t)0x0008)
 
+#define TIM_DMABase_CNT   ((uint16_t)0x0009)
 
+#define TIM_DMABase_PSC   ((uint16_t)0x000A)
 
+#define TIM_DMABase_ARR   ((uint16_t)0x000B)
 
+#define TIM_DMABase_RCR   ((uint16_t)0x000C)
 
+#define TIM_DMABase_CCR1   ((uint16_t)0x000D)
 
+#define TIM_DMABase_CCR2   ((uint16_t)0x000E)
 
+#define TIM_DMABase_CCR3   ((uint16_t)0x000F)
 
+#define TIM_DMABase_CCR4   ((uint16_t)0x0010)
 
+#define TIM_DMABase_BDTR   ((uint16_t)0x0011)
 
+#define TIM_DMABase_DCR   ((uint16_t)0x0012)
 
+#define TIM_DMABase_OR   ((uint16_t)0x0013)
 
#define IS_TIM_DMA_BASE(BASE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_DMA_BASE( BASE)
+
+Value:
(((BASE) == TIM_DMABase_CR1) || \
+
((BASE) == TIM_DMABase_CR2) || \
+
((BASE) == TIM_DMABase_SMCR) || \
+
((BASE) == TIM_DMABase_DIER) || \
+
((BASE) == TIM_DMABase_SR) || \
+
((BASE) == TIM_DMABase_EGR) || \
+
((BASE) == TIM_DMABase_CCMR1) || \
+
((BASE) == TIM_DMABase_CCMR2) || \
+
((BASE) == TIM_DMABase_CCER) || \
+
((BASE) == TIM_DMABase_CNT) || \
+
((BASE) == TIM_DMABase_PSC) || \
+
((BASE) == TIM_DMABase_ARR) || \
+
((BASE) == TIM_DMABase_RCR) || \
+
((BASE) == TIM_DMABase_CCR1) || \
+
((BASE) == TIM_DMABase_CCR2) || \
+
((BASE) == TIM_DMABase_CCR3) || \
+
((BASE) == TIM_DMABase_CCR4) || \
+
((BASE) == TIM_DMABase_BDTR) || \
+
((BASE) == TIM_DMABase_DCR) || \
+
((BASE) == TIM_DMABase_OR))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___d_m_a___base__address.map b/group___t_i_m___d_m_a___base__address.map new file mode 100644 index 0000000..d29b24d --- /dev/null +++ b/group___t_i_m___d_m_a___base__address.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___d_m_a___base__address.md5 b/group___t_i_m___d_m_a___base__address.md5 new file mode 100644 index 0000000..7f9697a --- /dev/null +++ b/group___t_i_m___d_m_a___base__address.md5 @@ -0,0 +1 @@ +924f032c53ec9df87a435f4759898a5f \ No newline at end of file diff --git a/group___t_i_m___d_m_a___base__address.png b/group___t_i_m___d_m_a___base__address.png new file mode 100644 index 0000000..c4c39ff Binary files /dev/null and b/group___t_i_m___d_m_a___base__address.png differ diff --git a/group___t_i_m___d_m_a___burst___length.html b/group___t_i_m___d_m_a___burst___length.html new file mode 100644 index 0000000..9e2577d --- /dev/null +++ b/group___t_i_m___d_m_a___burst___length.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: TIM_DMA_Burst_Length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_DMA_Burst_Length
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_DMA_Burst_Length:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_DMABurstLength_1Transfer   ((uint16_t)0x0000)
 
+#define TIM_DMABurstLength_2Transfers   ((uint16_t)0x0100)
 
+#define TIM_DMABurstLength_3Transfers   ((uint16_t)0x0200)
 
+#define TIM_DMABurstLength_4Transfers   ((uint16_t)0x0300)
 
+#define TIM_DMABurstLength_5Transfers   ((uint16_t)0x0400)
 
+#define TIM_DMABurstLength_6Transfers   ((uint16_t)0x0500)
 
+#define TIM_DMABurstLength_7Transfers   ((uint16_t)0x0600)
 
+#define TIM_DMABurstLength_8Transfers   ((uint16_t)0x0700)
 
+#define TIM_DMABurstLength_9Transfers   ((uint16_t)0x0800)
 
+#define TIM_DMABurstLength_10Transfers   ((uint16_t)0x0900)
 
+#define TIM_DMABurstLength_11Transfers   ((uint16_t)0x0A00)
 
+#define TIM_DMABurstLength_12Transfers   ((uint16_t)0x0B00)
 
+#define TIM_DMABurstLength_13Transfers   ((uint16_t)0x0C00)
 
+#define TIM_DMABurstLength_14Transfers   ((uint16_t)0x0D00)
 
+#define TIM_DMABurstLength_15Transfers   ((uint16_t)0x0E00)
 
+#define TIM_DMABurstLength_16Transfers   ((uint16_t)0x0F00)
 
+#define TIM_DMABurstLength_17Transfers   ((uint16_t)0x1000)
 
+#define TIM_DMABurstLength_18Transfers   ((uint16_t)0x1100)
 
#define IS_TIM_DMA_LENGTH(LENGTH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_DMA_LENGTH( LENGTH)
+
+Value:
(((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+
((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+
((LENGTH) == TIM_DMABurstLength_18Transfers))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___d_m_a___burst___length.map b/group___t_i_m___d_m_a___burst___length.map new file mode 100644 index 0000000..1d91620 --- /dev/null +++ b/group___t_i_m___d_m_a___burst___length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___d_m_a___burst___length.md5 b/group___t_i_m___d_m_a___burst___length.md5 new file mode 100644 index 0000000..217ea1e --- /dev/null +++ b/group___t_i_m___d_m_a___burst___length.md5 @@ -0,0 +1 @@ +6ee46fae1c88b6aff64fbe117852833b \ No newline at end of file diff --git a/group___t_i_m___d_m_a___burst___length.png b/group___t_i_m___d_m_a___burst___length.png new file mode 100644 index 0000000..4cc4ac9 Binary files /dev/null and b/group___t_i_m___d_m_a___burst___length.png differ diff --git a/group___t_i_m___d_m_a__sources.html b/group___t_i_m___d_m_a__sources.html new file mode 100644 index 0000000..2fefe89 --- /dev/null +++ b/group___t_i_m___d_m_a__sources.html @@ -0,0 +1,130 @@ + + + + + + +discoverpixy: TIM_DMA_sources + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_DMA_sources
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_DMA_sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_DMA_Update   ((uint16_t)0x0100)
 
+#define TIM_DMA_CC1   ((uint16_t)0x0200)
 
+#define TIM_DMA_CC2   ((uint16_t)0x0400)
 
+#define TIM_DMA_CC3   ((uint16_t)0x0800)
 
+#define TIM_DMA_CC4   ((uint16_t)0x1000)
 
+#define TIM_DMA_COM   ((uint16_t)0x2000)
 
+#define TIM_DMA_Trigger   ((uint16_t)0x4000)
 
+#define IS_TIM_DMA_SOURCE(SOURCE)   ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___d_m_a__sources.map b/group___t_i_m___d_m_a__sources.map new file mode 100644 index 0000000..8bdb188 --- /dev/null +++ b/group___t_i_m___d_m_a__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___d_m_a__sources.md5 b/group___t_i_m___d_m_a__sources.md5 new file mode 100644 index 0000000..8fd2d3d --- /dev/null +++ b/group___t_i_m___d_m_a__sources.md5 @@ -0,0 +1 @@ +c329cf176984a57014bb909b7a0bda11 \ No newline at end of file diff --git a/group___t_i_m___d_m_a__sources.png b/group___t_i_m___d_m_a__sources.png new file mode 100644 index 0000000..66f2ebf Binary files /dev/null and b/group___t_i_m___d_m_a__sources.png differ diff --git a/group___t_i_m___encoder___mode.html b/group___t_i_m___encoder___mode.html new file mode 100644 index 0000000..54799e6 --- /dev/null +++ b/group___t_i_m___encoder___mode.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: TIM_Encoder_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Encoder_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Encoder_Mode:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define TIM_EncoderMode_TI1   ((uint16_t)0x0001)
 
+#define TIM_EncoderMode_TI2   ((uint16_t)0x0002)
 
+#define TIM_EncoderMode_TI12   ((uint16_t)0x0003)
 
#define IS_TIM_ENCODER_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_ENCODER_MODE( MODE)
+
+Value:
(((MODE) == TIM_EncoderMode_TI1) || \
+
((MODE) == TIM_EncoderMode_TI2) || \
+
((MODE) == TIM_EncoderMode_TI12))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___encoder___mode.map b/group___t_i_m___encoder___mode.map new file mode 100644 index 0000000..93c9b34 --- /dev/null +++ b/group___t_i_m___encoder___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___encoder___mode.md5 b/group___t_i_m___encoder___mode.md5 new file mode 100644 index 0000000..caac306 --- /dev/null +++ b/group___t_i_m___encoder___mode.md5 @@ -0,0 +1 @@ +f7a41d345adc94749a7c03111905edce \ No newline at end of file diff --git a/group___t_i_m___encoder___mode.png b/group___t_i_m___encoder___mode.png new file mode 100644 index 0000000..a102c9a Binary files /dev/null and b/group___t_i_m___encoder___mode.png differ diff --git a/group___t_i_m___event___source.html b/group___t_i_m___event___source.html new file mode 100644 index 0000000..1416b30 --- /dev/null +++ b/group___t_i_m___event___source.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Event_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Event_Source
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Event_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_EventSource_Update   ((uint16_t)0x0001)
 
+#define TIM_EventSource_CC1   ((uint16_t)0x0002)
 
+#define TIM_EventSource_CC2   ((uint16_t)0x0004)
 
+#define TIM_EventSource_CC3   ((uint16_t)0x0008)
 
+#define TIM_EventSource_CC4   ((uint16_t)0x0010)
 
+#define TIM_EventSource_COM   ((uint16_t)0x0020)
 
+#define TIM_EventSource_Trigger   ((uint16_t)0x0040)
 
+#define TIM_EventSource_Break   ((uint16_t)0x0080)
 
+#define IS_TIM_EVENT_SOURCE(SOURCE)   ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___event___source.map b/group___t_i_m___event___source.map new file mode 100644 index 0000000..432237f --- /dev/null +++ b/group___t_i_m___event___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___event___source.md5 b/group___t_i_m___event___source.md5 new file mode 100644 index 0000000..d6fce66 --- /dev/null +++ b/group___t_i_m___event___source.md5 @@ -0,0 +1 @@ +557cedab19af384ebabf9299b1fb61a2 \ No newline at end of file diff --git a/group___t_i_m___event___source.png b/group___t_i_m___event___source.png new file mode 100644 index 0000000..fa6a81e Binary files /dev/null and b/group___t_i_m___event___source.png differ diff --git a/group___t_i_m___exported__constants.html b/group___t_i_m___exported__constants.html new file mode 100644 index 0000000..c0f7275 --- /dev/null +++ b/group___t_i_m___exported__constants.html @@ -0,0 +1,382 @@ + + + + + + +discoverpixy: TIM_Exported_constants + + + + + + + + + + +
+
+ + + + + + +
+
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+Modules | +Macros
+
+
TIM_Exported_constants
STM32F4xx_StdPeriph_Driver » TIM
+
+
+
+Collaboration diagram for TIM_Exported_constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 TIM_Output_Compare_and_PWM_modes
 
 TIM_One_Pulse_Mode
 
 TIM_Channel
 
 TIM_Clock_Division_CKD
 
 TIM_Counter_Mode
 
 TIM_Output_Compare_Polarity
 
 TIM_Output_Compare_N_Polarity
 
 TIM_Output_Compare_State
 
 TIM_Output_Compare_N_State
 
 TIM_Capture_Compare_State
 
 TIM_Capture_Compare_N_State
 
 TIM_Break_Input_enable_disable
 
 TIM_Break_Polarity
 
 TIM_AOE_Bit_Set_Reset
 
 TIM_Lock_level
 
 TIM_OSSI_Off_State_Selection_for_Idle_mode_state
 
 TIM_OSSR_Off_State_Selection_for_Run_mode_state
 
 TIM_Output_Compare_Idle_State
 
 TIM_Output_Compare_N_Idle_State
 
 TIM_Input_Capture_Polarity
 
 TIM_Input_Capture_Selection
 
 TIM_Input_Capture_Prescaler
 
 TIM_interrupt_sources
 
 TIM_DMA_Base_address
 
 TIM_DMA_Burst_Length
 
 TIM_DMA_sources
 
 TIM_External_Trigger_Prescaler
 
 TIM_Internal_Trigger_Selection
 
 TIM_TIx_External_Clock_Source
 
 TIM_External_Trigger_Polarity
 
 TIM_Prescaler_Reload_Mode
 
 TIM_Forced_Action
 
 TIM_Encoder_Mode
 
 TIM_Event_Source
 
 TIM_Update_Source
 
 TIM_Output_Compare_Preload_State
 
 TIM_Output_Compare_Fast_State
 
 TIM_Output_Compare_Clear_State
 
 TIM_Trigger_Output_Source
 
 TIM_Slave_Mode
 
 TIM_Master_Slave_Mode
 
 TIM_Remap
 
 TIM_Flags
 
 TIM_Input_Capture_Filer_Value
 
 TIM_External_Trigger_Filter
 
 TIM_Legacy
 
+ + + + + + + + + + + + + + + +

+Macros

#define IS_TIM_ALL_PERIPH(PERIPH)
 
#define IS_TIM_LIST1_PERIPH(PERIPH)
 
#define IS_TIM_LIST2_PERIPH(PERIPH)
 
#define IS_TIM_LIST3_PERIPH(PERIPH)
 
#define IS_TIM_LIST4_PERIPH(PERIPH)
 
#define IS_TIM_LIST5_PERIPH(PERIPH)
 
#define IS_TIM_LIST6_PERIPH(TIMx)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM2) || \
+
((PERIPH) == TIM3) || \
+
((PERIPH) == TIM4) || \
+
((PERIPH) == TIM5) || \
+
((PERIPH) == TIM6) || \
+
((PERIPH) == TIM7) || \
+
((PERIPH) == TIM8) || \
+
((PERIPH) == TIM9) || \
+
((PERIPH) == TIM10) || \
+
((PERIPH) == TIM11) || \
+
((PERIPH) == TIM12) || \
+
(((PERIPH) == TIM13) || \
+
((PERIPH) == TIM14)))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST1_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM2) || \
+
((PERIPH) == TIM3) || \
+
((PERIPH) == TIM4) || \
+
((PERIPH) == TIM5) || \
+
((PERIPH) == TIM8) || \
+
((PERIPH) == TIM9) || \
+
((PERIPH) == TIM10) || \
+
((PERIPH) == TIM11) || \
+
((PERIPH) == TIM12) || \
+
((PERIPH) == TIM13) || \
+
((PERIPH) == TIM14))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST2_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM2) || \
+
((PERIPH) == TIM3) || \
+
((PERIPH) == TIM4) || \
+
((PERIPH) == TIM5) || \
+
((PERIPH) == TIM8) || \
+
((PERIPH) == TIM9) || \
+
((PERIPH) == TIM12))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST3_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM2) || \
+
((PERIPH) == TIM3) || \
+
((PERIPH) == TIM4) || \
+
((PERIPH) == TIM5) || \
+
((PERIPH) == TIM8))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST4_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM8))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST5_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == TIM1) || \
+
((PERIPH) == TIM2) || \
+
((PERIPH) == TIM3) || \
+
((PERIPH) == TIM4) || \
+
((PERIPH) == TIM5) || \
+
((PERIPH) == TIM6) || \
+
((PERIPH) == TIM7) || \
+
((PERIPH) == TIM8))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_LIST6_PERIPH( TIMx)
+
+Value:
(((TIMx) == TIM2) || \
+
((TIMx) == TIM5) || \
+
((TIMx) == TIM11))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___exported__constants.map b/group___t_i_m___exported__constants.map new file mode 100644 index 0000000..e623d0a --- /dev/null +++ b/group___t_i_m___exported__constants.map @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/group___t_i_m___exported__constants.md5 b/group___t_i_m___exported__constants.md5 new file mode 100644 index 0000000..cb24dbc --- /dev/null +++ b/group___t_i_m___exported__constants.md5 @@ -0,0 +1 @@ +f3189280735a3816eefc4f25825f6214 \ No newline at end of file diff --git a/group___t_i_m___exported__constants.png b/group___t_i_m___exported__constants.png new file mode 100644 index 0000000..4a39aea Binary files /dev/null and b/group___t_i_m___exported__constants.png differ diff --git a/group___t_i_m___external___trigger___filter.html b/group___t_i_m___external___trigger___filter.html new file mode 100644 index 0000000..90f37b6 --- /dev/null +++ b/group___t_i_m___external___trigger___filter.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: TIM_External_Trigger_Filter + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_External_Trigger_Filter
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_External_Trigger_Filter:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_TIM_EXT_FILTER(EXTFILTER)   ((EXTFILTER) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___external___trigger___filter.map b/group___t_i_m___external___trigger___filter.map new file mode 100644 index 0000000..35af242 --- /dev/null +++ b/group___t_i_m___external___trigger___filter.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___external___trigger___filter.md5 b/group___t_i_m___external___trigger___filter.md5 new file mode 100644 index 0000000..16c6ace --- /dev/null +++ b/group___t_i_m___external___trigger___filter.md5 @@ -0,0 +1 @@ +edafe3246c04fe3a26d4806146780d36 \ No newline at end of file diff --git a/group___t_i_m___external___trigger___filter.png b/group___t_i_m___external___trigger___filter.png new file mode 100644 index 0000000..57ba916 Binary files /dev/null and b/group___t_i_m___external___trigger___filter.png differ diff --git a/group___t_i_m___external___trigger___polarity.html b/group___t_i_m___external___trigger___polarity.html new file mode 100644 index 0000000..5b47c94 --- /dev/null +++ b/group___t_i_m___external___trigger___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_External_Trigger_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros
+
+
TIM_External_Trigger_Polarity
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_External_Trigger_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_ExtTRGPolarity_Inverted   ((uint16_t)0x8000)
 
+#define TIM_ExtTRGPolarity_NonInverted   ((uint16_t)0x0000)
 
#define IS_TIM_EXT_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_EXT_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___external___trigger___polarity.map b/group___t_i_m___external___trigger___polarity.map new file mode 100644 index 0000000..fc6f5a9 --- /dev/null +++ b/group___t_i_m___external___trigger___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___external___trigger___polarity.md5 b/group___t_i_m___external___trigger___polarity.md5 new file mode 100644 index 0000000..cdb39cf --- /dev/null +++ b/group___t_i_m___external___trigger___polarity.md5 @@ -0,0 +1 @@ +e0c86f1a774f4faf86219707fb8ad7e4 \ No newline at end of file diff --git a/group___t_i_m___external___trigger___polarity.png b/group___t_i_m___external___trigger___polarity.png new file mode 100644 index 0000000..d99935f Binary files /dev/null and b/group___t_i_m___external___trigger___polarity.png differ diff --git a/group___t_i_m___external___trigger___prescaler.html b/group___t_i_m___external___trigger___prescaler.html new file mode 100644 index 0000000..d7b80ba --- /dev/null +++ b/group___t_i_m___external___trigger___prescaler.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: TIM_External_Trigger_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_External_Trigger_Prescaler
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_External_Trigger_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define TIM_ExtTRGPSC_OFF   ((uint16_t)0x0000)
 
+#define TIM_ExtTRGPSC_DIV2   ((uint16_t)0x1000)
 
+#define TIM_ExtTRGPSC_DIV4   ((uint16_t)0x2000)
 
+#define TIM_ExtTRGPSC_DIV8   ((uint16_t)0x3000)
 
#define IS_TIM_EXT_PRESCALER(PRESCALER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_EXT_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___external___trigger___prescaler.map b/group___t_i_m___external___trigger___prescaler.map new file mode 100644 index 0000000..f21f12b --- /dev/null +++ b/group___t_i_m___external___trigger___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___external___trigger___prescaler.md5 b/group___t_i_m___external___trigger___prescaler.md5 new file mode 100644 index 0000000..824f10d --- /dev/null +++ b/group___t_i_m___external___trigger___prescaler.md5 @@ -0,0 +1 @@ +9c1256297b0430a5eb3f2b8a2bd781f2 \ No newline at end of file diff --git a/group___t_i_m___external___trigger___prescaler.png b/group___t_i_m___external___trigger___prescaler.png new file mode 100644 index 0000000..afb1ab7 Binary files /dev/null and b/group___t_i_m___external___trigger___prescaler.png differ diff --git a/group___t_i_m___flags.html b/group___t_i_m___flags.html new file mode 100644 index 0000000..2b1b150 --- /dev/null +++ b/group___t_i_m___flags.html @@ -0,0 +1,173 @@ + + + + + + +discoverpixy: TIM_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Flags
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_FLAG_Update   ((uint16_t)0x0001)
 
+#define TIM_FLAG_CC1   ((uint16_t)0x0002)
 
+#define TIM_FLAG_CC2   ((uint16_t)0x0004)
 
+#define TIM_FLAG_CC3   ((uint16_t)0x0008)
 
+#define TIM_FLAG_CC4   ((uint16_t)0x0010)
 
+#define TIM_FLAG_COM   ((uint16_t)0x0020)
 
+#define TIM_FLAG_Trigger   ((uint16_t)0x0040)
 
+#define TIM_FLAG_Break   ((uint16_t)0x0080)
 
+#define TIM_FLAG_CC1OF   ((uint16_t)0x0200)
 
+#define TIM_FLAG_CC2OF   ((uint16_t)0x0400)
 
+#define TIM_FLAG_CC3OF   ((uint16_t)0x0800)
 
+#define TIM_FLAG_CC4OF   ((uint16_t)0x1000)
 
#define IS_TIM_GET_FLAG(FLAG)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_GET_FLAG( FLAG)
+
+Value:
(((FLAG) == TIM_FLAG_Update) || \
+
((FLAG) == TIM_FLAG_CC1) || \
+
((FLAG) == TIM_FLAG_CC2) || \
+
((FLAG) == TIM_FLAG_CC3) || \
+
((FLAG) == TIM_FLAG_CC4) || \
+
((FLAG) == TIM_FLAG_COM) || \
+
((FLAG) == TIM_FLAG_Trigger) || \
+
((FLAG) == TIM_FLAG_Break) || \
+
((FLAG) == TIM_FLAG_CC1OF) || \
+
((FLAG) == TIM_FLAG_CC2OF) || \
+
((FLAG) == TIM_FLAG_CC3OF) || \
+
((FLAG) == TIM_FLAG_CC4OF))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___flags.map b/group___t_i_m___flags.map new file mode 100644 index 0000000..3516c56 --- /dev/null +++ b/group___t_i_m___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___flags.md5 b/group___t_i_m___flags.md5 new file mode 100644 index 0000000..7813e2d --- /dev/null +++ b/group___t_i_m___flags.md5 @@ -0,0 +1 @@ +7d461737f23cb5d603b58e98d4311f0a \ No newline at end of file diff --git a/group___t_i_m___flags.png b/group___t_i_m___flags.png new file mode 100644 index 0000000..3980648 Binary files /dev/null and b/group___t_i_m___flags.png differ diff --git a/group___t_i_m___forced___action.html b/group___t_i_m___forced___action.html new file mode 100644 index 0000000..e1d2dee --- /dev/null +++ b/group___t_i_m___forced___action.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Forced_Action + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Forced_Action
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Forced_Action:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_ForcedAction_Active   ((uint16_t)0x0050)
 
+#define TIM_ForcedAction_InActive   ((uint16_t)0x0040)
 
#define IS_TIM_FORCED_ACTION(ACTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_FORCED_ACTION( ACTION)
+
+Value:
(((ACTION) == TIM_ForcedAction_Active) || \
+
((ACTION) == TIM_ForcedAction_InActive))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___forced___action.map b/group___t_i_m___forced___action.map new file mode 100644 index 0000000..f6b5d1b --- /dev/null +++ b/group___t_i_m___forced___action.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___forced___action.md5 b/group___t_i_m___forced___action.md5 new file mode 100644 index 0000000..8a3bcd1 --- /dev/null +++ b/group___t_i_m___forced___action.md5 @@ -0,0 +1 @@ +8c5094bc6a4775ada49bd363fd0425ee \ No newline at end of file diff --git a/group___t_i_m___forced___action.png b/group___t_i_m___forced___action.png new file mode 100644 index 0000000..0b95595 Binary files /dev/null and b/group___t_i_m___forced___action.png differ diff --git a/group___t_i_m___group1.html b/group___t_i_m___group1.html new file mode 100644 index 0000000..755d6a1 --- /dev/null +++ b/group___t_i_m___group1.html @@ -0,0 +1,791 @@ + + + + + + +discoverpixy: TimeBase management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
TimeBase management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

TimeBase management functions. +More...

+
+Collaboration diagram for TimeBase management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_DeInit (TIM_TypeDef *TIMx)
 Deinitializes the TIMx peripheral registers to their default reset values. More...
 
void TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct. More...
 
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Fills each TIM_TimeBaseInitStruct member with its default value. More...
 
void TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
 Configures the TIMx Prescaler. More...
 
void TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
 Specifies the TIMx Counter Mode to be used. More...
 
void TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
 Sets the TIMx Counter Register value. More...
 
void TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
 Sets the TIMx Autoreload Register value. More...
 
uint32_t TIM_GetCounter (TIM_TypeDef *TIMx)
 Gets the TIMx Counter value. More...
 
uint16_t TIM_GetPrescaler (TIM_TypeDef *TIMx)
 Gets the TIMx Prescaler value. More...
 
void TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or Disables the TIMx Update event. More...
 
void TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
 Configures the TIMx Update Request Interrupt source. More...
 
void TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables TIMx peripheral Preload register on ARR. More...
 
void TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
 Selects the TIMx's One Pulse Mode. More...
 
void TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
 Sets the TIMx Clock Division value. More...
 
void TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the specified TIM peripheral. More...
 
+

Detailed Description

+

TimeBase management functions.

+
 ===============================================================================
+                     ##### TimeBase management functions #####
+ ===============================================================================  
+  
+     
+            ##### TIM Driver: how to use it in Timing(Time base) Mode #####
+ ===============================================================================
+    [..] 
+    To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+      (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+                    
+      (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
+       
+      (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
+          with the corresponding configuration
+          
+      (#) Enable the NVIC if you need to generate the update interrupt. 
+          
+      (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) 
+       
+      (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+             
+       -@- All other functions can be used separately to modify, if needed,
+           a specific feature of the Timer.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ARRPreloadConfig (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables TIMx peripheral Preload register on ARR.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
NewStatenew state of the TIMx peripheral Preload register This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_Cmd (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified TIM peripheral.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIMx peripheral.
NewStatenew state of the TIMx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_CounterModeConfig (TIM_TypeDef * TIMx,
uint16_t TIM_CounterMode 
)
+
+ +

Specifies the TIMx Counter Mode to be used.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_CounterModespecifies the Counter Mode to be used This parameter can be one of the following values:
    +
  • TIM_CounterMode_Up: TIM Up Counting Mode
    • +
  • TIM_CounterMode_Down: TIM Down Counting Mode
    • +
  • TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
    • +
  • TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
    • +
  • TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_DeInit (TIM_TypeDef * TIMx)
+
+ +

Deinitializes the TIMx peripheral registers to their default reset values.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCounter (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Counter value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
CounterRegister value
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t TIM_GetPrescaler (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Prescaler value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
+
+
+
Return values
+ + +
PrescalerRegister value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_PrescalerConfig (TIM_TypeDef * TIMx,
uint16_t Prescaler,
uint16_t TIM_PSCReloadMode 
)
+
+ +

Configures the TIMx Prescaler.

+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Prescalerspecifies the Prescaler Register value
TIM_PSCReloadModespecifies the TIM Prescaler Reload mode This parameter can be one of the following values:
    +
  • TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
    • +
  • TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectOnePulseMode (TIM_TypeDef * TIMx,
uint16_t TIM_OPMode 
)
+
+ +

Selects the TIMx's One Pulse Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_OPModespecifies the OPM Mode to be used. This parameter can be one of the following values:
    +
  • TIM_OPMode_Single
    • +
  • TIM_OPMode_Repetitive
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetAutoreload (TIM_TypeDef * TIMx,
uint32_t Autoreload 
)
+
+ +

Sets the TIMx Autoreload Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Autoreloadspecifies the Autoreload register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetClockDivision (TIM_TypeDef * TIMx,
uint16_t TIM_CKD 
)
+
+ +

Sets the TIMx Clock Division value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_CKDspecifies the clock division value. This parameter can be one of the following value:
    +
  • TIM_CKD_DIV1: TDTS = Tck_tim
    • +
  • TIM_CKD_DIV2: TDTS = 2*Tck_tim
    • +
  • TIM_CKD_DIV4: TDTS = 4*Tck_tim
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCounter (TIM_TypeDef * TIMx,
uint32_t Counter 
)
+
+ +

Sets the TIMx Counter Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
Counterspecifies the Counter register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_TimeBaseInit (TIM_TypeDef * TIMx,
TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct 
)
+
+ +

Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_TimeBaseInitStructpointer to a TIM_TimeBaseInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef * TIM_TimeBaseInitStruct)
+
+ +

Fills each TIM_TimeBaseInitStruct member with its default value.

+
Parameters
+ + +
TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_UpdateDisableConfig (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or Disables the TIMx Update event.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
NewStatenew state of the TIMx UDIS bit This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_UpdateRequestConfig (TIM_TypeDef * TIMx,
uint16_t TIM_UpdateSource 
)
+
+ +

Configures the TIMx Update Request Interrupt source.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_UpdateSourcespecifies the Update source. This parameter can be one of the following values:
    +
  • TIM_UpdateSource_Global: Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.
    • +
  • TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group1.map b/group___t_i_m___group1.map new file mode 100644 index 0000000..669377e --- /dev/null +++ b/group___t_i_m___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group1.md5 b/group___t_i_m___group1.md5 new file mode 100644 index 0000000..db717fb --- /dev/null +++ b/group___t_i_m___group1.md5 @@ -0,0 +1 @@ +07905053407f6aa0cf15ff6007dd31f0 \ No newline at end of file diff --git a/group___t_i_m___group1.png b/group___t_i_m___group1.png new file mode 100644 index 0000000..752f19f Binary files /dev/null and b/group___t_i_m___group1.png differ diff --git a/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.map b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.map new file mode 100644 index 0000000..07cedee --- /dev/null +++ b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.md5 b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.md5 new file mode 100644 index 0000000..87f000d --- /dev/null +++ b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.md5 @@ -0,0 +1 @@ +16d5c77ba96bba74c6762ea675be25d5 \ No newline at end of file diff --git a/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.png b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.png new file mode 100644 index 0000000..ed72cd2 Binary files /dev/null and b/group___t_i_m___group1_ga1659cc0ce503ac151568e0c7c02b1ba5_cgraph.png differ diff --git a/group___t_i_m___group2.html b/group___t_i_m___group2.html new file mode 100644 index 0000000..d75abae --- /dev/null +++ b/group___t_i_m___group2.html @@ -0,0 +1,1822 @@ + + + + + + +discoverpixy: Output Compare management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Functions
+
+
Output Compare management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Output Compare management functions. +More...

+
+Collaboration diagram for Output Compare management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
 Fills each TIM_OCInitStruct member with its default value. More...
 
void TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
 Selects the TIM Output Compare Mode. More...
 
void TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
 Sets the TIMx Capture Compare1 Register value. More...
 
void TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
 Sets the TIMx Capture Compare2 Register value. More...
 
void TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
 Sets the TIMx Capture Compare3 Register value. More...
 
void TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
 Sets the TIMx Capture Compare4 Register value. More...
 
void TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 1 waveform to active or inactive level. More...
 
void TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 2 waveform to active or inactive level. More...
 
void TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 3 waveform to active or inactive level. More...
 
void TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 4 waveform to active or inactive level. More...
 
void TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR1. More...
 
void TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR2. More...
 
void TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR3. More...
 
void TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR4. More...
 
void TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 1 Fast feature. More...
 
void TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 2 Fast feature. More...
 
void TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 3 Fast feature. More...
 
void TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 4 Fast feature. More...
 
void TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF1 signal on an external event. More...
 
void TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF2 signal on an external event. More...
 
void TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF3 signal on an external event. More...
 
void TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF4 signal on an external event. More...
 
void TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 1 polarity. More...
 
void TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 1N polarity. More...
 
void TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 2 polarity. More...
 
void TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 2N polarity. More...
 
void TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 3 polarity. More...
 
void TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 3N polarity. More...
 
void TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 4 polarity. More...
 
void TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
 Enables or disables the TIM Capture Compare Channel x. More...
 
void TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
 Enables or disables the TIM Capture Compare Channel xN. More...
 
+

Detailed Description

+

Output Compare management functions.

+
 ===============================================================================
+              ##### Output Compare management functions #####
+ ===============================================================================  
+   
+      
+        ##### TIM Driver: how to use it in Output Compare Mode #####
+ ===============================================================================
+    [..] 
+    To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+      (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 
+          function
+       
+      (#) Configure the TIM pins by configuring the corresponding GPIO pins
+       
+      (#) Configure the Time base unit as described in the first part of this driver, 
+        (++) if needed, else the Timer will run with the default configuration:
+            Autoreload value = 0xFFFF
+        (++) Prescaler value = 0x0000
+        (++) Counter mode = Up counting
+        (++) Clock Division = TIM_CKD_DIV1
+          
+      (#) Fill the TIM_OCInitStruct with the desired parameters including:
+        (++) The TIM Output Compare mode: TIM_OCMode
+        (++) TIM Output State: TIM_OutputState
+        (++) TIM Pulse value: TIM_Pulse
+        (++) TIM Output Compare Polarity : TIM_OCPolarity
+       
+      (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired 
+          channel with the corresponding configuration
+       
+      (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+       
+      -@- All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+          
+      -@- In case of PWM mode, this function is mandatory:
+          TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 
+              
+      -@- If the corresponding interrupt or DMA request are needed, the user should:
+        (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 
+        (+@) Enable the corresponding interrupt (or DMA request) using the function 
+             TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_CCxCmd (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_CCx 
)
+
+ +

Enables or disables the TIM Capture Compare Channel x.

+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
  • TIM_Channel_4: TIM Channel 4
    • +
+
TIM_CCxspecifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_CCxNCmd (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_CCxN 
)
+
+ +

Enables or disables the TIM Capture Compare Channel xN.

+
Parameters
+ + + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
+
TIM_CCxNspecifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearOC1Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF1 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearOC2Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF2 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearOC3Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF3 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearOC4Ref (TIM_TypeDef * TIMx,
uint16_t TIM_OCClear 
)
+
+ +

Clears or safeguards the OCREF4 signal on an external event.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCClearnew state of the Output Compare Clear Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCClear_Enable: TIM Output clear enable
    • +
  • TIM_OCClear_Disable: TIM Output clear disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC1Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 1 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC1REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC1REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC2Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 2 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC2REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC2REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC3Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 3 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC3REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC3REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ForcedOC4Config (TIM_TypeDef * TIMx,
uint16_t TIM_ForcedAction 
)
+
+ +

Forces the TIMx output 4 waveform to active or inactive level.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ForcedActionspecifies the forced Action to be set to the output waveform. This parameter can be one of the following values:
    +
  • TIM_ForcedAction_Active: Force active level on OC4REF
    • +
  • TIM_ForcedAction_InActive: Force inactive level on OC4REF.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 1 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 1N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC1N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 1 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCPolarityspecifies the OC1 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC1PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR1.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 2 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 2N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC2N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 2 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC2 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC2PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR2.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 3 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3NPolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCNPolarity 
)
+
+ +

Configures the TIMx Channel 3N polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM peripheral.
TIM_OCNPolarityspecifies the OC3N Polarity This parameter can be one of the following values:
    +
  • TIM_OCNPolarity_High: Output Compare active high
    • +
  • TIM_OCNPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 3 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC3 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC3PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR3.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4FastConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCFast 
)
+
+ +

Configures the TIMx Output Compare 4 Fast feature.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCFastnew state of the Output Compare Fast Enable Bit. This parameter can be one of the following values:
    +
  • TIM_OCFast_Enable: TIM output compare fast enable
    • +
  • TIM_OCFast_Disable: TIM output compare fast disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4Init (TIM_TypeDef * TIMx,
TIM_OCInitTypeDef * TIM_OCInitStruct 
)
+
+ +

Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4PolarityConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPolarity 
)
+
+ +

Configures the TIMx channel 4 polarity.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPolarityspecifies the OC4 Polarity This parameter can be one of the following values:
    +
  • TIM_OCPolarity_High: Output Compare active high
    • +
  • TIM_OCPolarity_Low: Output Compare active low
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_OC4PreloadConfig (TIM_TypeDef * TIMx,
uint16_t TIM_OCPreload 
)
+
+ +

Enables or disables the TIMx peripheral Preload register on CCR4.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_OCPreloadnew state of the TIMx peripheral Preload register This parameter can be one of the following values:
    +
  • TIM_OCPreload_Enable
    • +
  • TIM_OCPreload_Disable
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_OCStructInit (TIM_OCInitTypeDef * TIM_OCInitStruct)
+
+ +

Fills each TIM_OCInitStruct member with its default value.

+
Parameters
+ + +
TIM_OCInitStructpointer to a TIM_OCInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_SelectOCxM (TIM_TypeDef * TIMx,
uint16_t TIM_Channel,
uint16_t TIM_OCMode 
)
+
+ +

Selects the TIM Output Compare Mode.

+
Note
This function disables the selected channel before changing the Output Compare Mode. If needed, user has to enable this channel using TIM_CCxCmd() and TIM_CCxNCmd() functions.
+
Parameters
+ + + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_Channelspecifies the TIM Channel This parameter can be one of the following values:
    +
  • TIM_Channel_1: TIM Channel 1
    • +
  • TIM_Channel_2: TIM Channel 2
    • +
  • TIM_Channel_3: TIM Channel 3
    • +
  • TIM_Channel_4: TIM Channel 4
    • +
+
TIM_OCModespecifies the TIM Output Compare Mode. This parameter can be one of the following values:
    +
  • TIM_OCMode_Timing
    • +
  • TIM_OCMode_Active
    • +
  • TIM_OCMode_Toggle
    • +
  • TIM_OCMode_PWM1
    • +
  • TIM_OCMode_PWM2
    • +
  • TIM_ForcedAction_Active
    • +
  • TIM_ForcedAction_InActive
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare1 (TIM_TypeDef * TIMx,
uint32_t Compare1 
)
+
+ +

Sets the TIMx Capture Compare1 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
Compare1specifies the Capture Compare1 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare2 (TIM_TypeDef * TIMx,
uint32_t Compare2 
)
+
+ +

Sets the TIMx Capture Compare2 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
Compare2specifies the Capture Compare2 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare3 (TIM_TypeDef * TIMx,
uint32_t Compare3 
)
+
+ +

Sets the TIMx Capture Compare3 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare3specifies the Capture Compare3 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetCompare4 (TIM_TypeDef * TIMx,
uint32_t Compare4 
)
+
+ +

Sets the TIMx Capture Compare4 Register value.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
Compare4specifies the Capture Compare4 register new value.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group2.map b/group___t_i_m___group2.map new file mode 100644 index 0000000..c0be541 --- /dev/null +++ b/group___t_i_m___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group2.md5 b/group___t_i_m___group2.md5 new file mode 100644 index 0000000..53d966b --- /dev/null +++ b/group___t_i_m___group2.md5 @@ -0,0 +1 @@ +737191c2477d29a73566b37a3645eb9e \ No newline at end of file diff --git a/group___t_i_m___group2.png b/group___t_i_m___group2.png new file mode 100644 index 0000000..60b686b Binary files /dev/null and b/group___t_i_m___group2.png differ diff --git a/group___t_i_m___group3.html b/group___t_i_m___group3.html new file mode 100644 index 0000000..186d803 --- /dev/null +++ b/group___t_i_m___group3.html @@ -0,0 +1,663 @@ + + + + + + +discoverpixy: Input Capture management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Input Capture management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Input Capture management functions. +More...

+
+Collaboration diagram for Input Capture management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct. More...
 
void TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
 Fills each TIM_ICInitStruct member with its default value. More...
 
void TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal. More...
 
uint32_t TIM_GetCapture1 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 1 value. More...
 
uint32_t TIM_GetCapture2 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 2 value. More...
 
uint32_t TIM_GetCapture3 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 3 value. More...
 
uint32_t TIM_GetCapture4 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 4 value. More...
 
void TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 1 prescaler. More...
 
void TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 2 prescaler. More...
 
void TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 3 prescaler. More...
 
void TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 4 prescaler. More...
 
+

Detailed Description

+

Input Capture management functions.

+
 ===============================================================================
+                  ##### Input Capture management functions #####
+ ===============================================================================  
+         
+            ##### TIM Driver: how to use it in Input Capture Mode #####
+ ===============================================================================
+    [..]    
+    To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+      (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 
+          function
+       
+      (#) Configure the TIM pins by configuring the corresponding GPIO pins
+       
+      (#) Configure the Time base unit as described in the first part of this driver,
+          if needed, else the Timer will run with the default configuration:
+        (++) Autoreload value = 0xFFFF
+        (++) Prescaler value = 0x0000
+        (++) Counter mode = Up counting
+        (++) Clock Division = TIM_CKD_DIV1
+          
+      (#) Fill the TIM_ICInitStruct with the desired parameters including:
+        (++) TIM Channel: TIM_Channel
+        (++) TIM Input Capture polarity: TIM_ICPolarity
+        (++) TIM Input Capture selection: TIM_ICSelection
+        (++) TIM Input Capture Prescaler: TIM_ICPrescaler
+        (++) TIM Input CApture filter value: TIM_ICFilter
+       
+      (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel 
+          with the corresponding configuration and to measure only frequency 
+          or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) 
+          to configure the desired channels with the corresponding configuration 
+          and to measure the frequency and the duty cycle of the input signal
+          
+      (#) Enable the NVIC or the DMA to read the measured frequency. 
+          
+      (#) Enable the corresponding interrupt (or DMA request) to read the Captured 
+          value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) 
+          (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 
+       
+      (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+       
+      (#) Use TIM_GetCapturex(TIMx); to read the captured value.
+       
+      -@- All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer.

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture1 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 1 value.

+
Parameters
+ + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 1 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture2 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 2 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 2 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture3 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 3 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 3 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TIM_GetCapture4 (TIM_TypeDef * TIMx)
+
+ +

Gets the TIMx Input Capture 4 value.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+
+
+
Return values
+ + +
CaptureCompare 4 Register value.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ICInit (TIM_TypeDef * TIMx,
TIM_ICInitTypeDef * TIM_ICInitStruct 
)
+
+ +

Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

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+

+ +
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+ +
+
+ + + + + + + + +
void TIM_ICStructInit (TIM_ICInitTypeDef * TIM_ICInitStruct)
+
+ +

Fills each TIM_ICInitStruct member with its default value.

+
Parameters
+ + +
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_PWMIConfig (TIM_TypeDef * TIMx,
TIM_ICInitTypeDef * TIM_ICInitStruct 
)
+
+ +

Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM peripheral.
TIM_ICInitStructpointer to a TIM_ICInitTypeDef structure that contains the configuration information for the specified TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

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void TIM_SetIC1Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 1 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture1 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC2Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 2 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture2 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC3Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 3 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture3 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SetIC4Prescaler (TIM_TypeDef * TIMx,
uint16_t TIM_ICPSC 
)
+
+ +

Sets the TIMx Input Capture 4 prescaler.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ICPSCspecifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
    +
  • TIM_ICPSC_DIV1: no prescaler
    • +
  • TIM_ICPSC_DIV2: capture is done once every 2 events
    • +
  • TIM_ICPSC_DIV4: capture is done once every 4 events
    • +
  • TIM_ICPSC_DIV8: capture is done once every 8 events
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
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+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group3.map b/group___t_i_m___group3.map new file mode 100644 index 0000000..7e01853 --- /dev/null +++ b/group___t_i_m___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group3.md5 b/group___t_i_m___group3.md5 new file mode 100644 index 0000000..8d8825f --- /dev/null +++ b/group___t_i_m___group3.md5 @@ -0,0 +1 @@ +7f24bb24ee6da06c670d2011fa8bd555 \ No newline at end of file diff --git a/group___t_i_m___group3.png b/group___t_i_m___group3.png new file mode 100644 index 0000000..eadd669 Binary files /dev/null and b/group___t_i_m___group3.png differ diff --git a/group___t_i_m___group3_ga0f2c784271356d6b64b8c0da64dbdbc2_icgraph.map b/group___t_i_m___group3_ga0f2c784271356d6b64b8c0da64dbdbc2_icgraph.map new file mode 100644 index 0000000..3497dc2 --- /dev/null +++ b/group___t_i_m___group3_ga0f2c784271356d6b64b8c0da64dbdbc2_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group3_ga0f2c784271356d6b64b8c0da64dbdbc2_icgraph.md5 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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Advanced-control timers (TIM1 and TIM8) specific features
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Advanced-control timers (TIM1 and TIM8) specific features. +More...

+
+Collaboration diagram for Advanced-control timers (TIM1 and TIM8) specific features:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). More...
 
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Fills each TIM_BDTRInitStruct member with its default value. More...
 
void TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIM peripheral Main Outputs. More...
 
void TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIM peripheral Commutation event. More...
 
void TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
 Sets or Resets the TIM peripheral Capture Compare Preload Control bit. More...
 
+

Detailed Description

+

Advanced-control timers (TIM1 and TIM8) specific features.

+
 ===============================================================================
+      ##### Advanced-control timers (TIM1 and TIM8) specific features #####
+ ===============================================================================  
+        
+             ##### TIM Driver: how to use the Break feature #####
+ ===============================================================================
+    [..] 
+    After configuring the Timer channel(s) in the appropriate Output Compare mode: 
+                         
+      (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+          Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
+          AOE(automatic output enable).
+               
+      (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+          
+      (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
+          
+      (#) Once the break even occurs, the Timer's output signals are put in reset
+          state or in a known state (according to the configuration made in
+          TIM_BDTRConfig() function).

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_BDTRConfig (TIM_TypeDef * TIMx,
TIM_BDTRInitTypeDef * TIM_BDTRInitStruct 
)
+
+ +

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIM
TIM_BDTRInitStructpointer to a TIM_BDTRInitTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef * TIM_BDTRInitStruct)
+
+ +

Fills each TIM_BDTRInitStruct member with its default value.

+
Parameters
+ + +
TIM_BDTRInitStructpointer to a TIM_BDTRInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_CCPreloadControl (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Sets or Resets the TIM peripheral Capture Compare Preload Control bit.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral
NewStatenew state of the Capture Compare Preload Control bit This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_CtrlPWMOutputs (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIM peripheral Main Outputs.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral.
NewStatenew state of the TIM peripheral Main Outputs. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectCOM (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Selects the TIM peripheral Commutation event.

+
Parameters
+ + + +
TIMxwhere x can be 1 or 8 to select the TIMx peripheral
NewStatenew state of the Commutation event. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group4.map b/group___t_i_m___group4.map new file mode 100644 index 0000000..df3ef70 --- /dev/null +++ b/group___t_i_m___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group4.md5 b/group___t_i_m___group4.md5 new file mode 100644 index 0000000..54f29d2 --- /dev/null +++ b/group___t_i_m___group4.md5 @@ -0,0 +1 @@ +64e36a4709d8ce51373554cc8ca8bd71 \ No newline at end of file diff --git a/group___t_i_m___group4.png b/group___t_i_m___group4.png new file mode 100644 index 0000000..d524190 Binary files /dev/null and b/group___t_i_m___group4.png differ diff --git a/group___t_i_m___group5.html b/group___t_i_m___group5.html new file mode 100644 index 0000000..584ee5c --- /dev/null +++ b/group___t_i_m___group5.html @@ -0,0 +1,655 @@ + + + + + + +discoverpixy: Interrupts DMA and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts DMA and flags management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Interrupts, DMA and flags management functions. +More...

+
+Collaboration diagram for Interrupts DMA and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
 Enables or disables the specified TIM interrupts. More...
 
void TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
 Configures the TIMx event to be generate by software. More...
 
FlagStatus TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Checks whether the specified TIM flag is set or not. More...
 
void TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Clears the TIMx's pending flags. More...
 
ITStatus TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Checks whether the TIM interrupt has occurred or not. More...
 
void TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Clears the TIMx's interrupt pending bits. More...
 
void TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
 Configures the TIMx's DMA interface. More...
 
void TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
 Enables or disables the TIMx's DMA Requests. More...
 
void TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIMx peripheral Capture Compare DMA source. More...
 
+

Detailed Description

+

Interrupts, DMA and flags management functions.

+
 ===============================================================================
+          ##### Interrupts, DMA and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearFlag (TIM_TypeDef * TIMx,
uint16_t TIM_FLAG 
)
+
+ +

Clears the TIMx's pending flags.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_FLAGspecifies the flag bit to clear. This parameter can be any combination of the following values:
    +
  • TIM_FLAG_Update: TIM update Flag
    • +
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
    • +
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
    • +
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
    • +
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
    • +
  • TIM_FLAG_COM: TIM Commutation Flag
    • +
  • TIM_FLAG_Trigger: TIM Trigger Flag
    • +
  • TIM_FLAG_Break: TIM Break Flag
    • +
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
    • +
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
    • +
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
    • +
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
    • +
+
+
+
+
Note
TIM6 and TIM7 can have only one update flag.
+
+TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_ClearITPendingBit (TIM_TypeDef * TIMx,
uint16_t TIM_IT 
)
+
+ +

Clears the TIMx's interrupt pending bits.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_ITspecifies the pending bit to clear. This parameter can be any combination of the following values:
    +
  • TIM_IT_Update: TIM1 update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
TIM6 and TIM7 can generate only an update interrupt.
+
+TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_DMACmd (TIM_TypeDef * TIMx,
uint16_t TIM_DMASource,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIMx's DMA Requests.

+
Parameters
+ + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
TIM_DMASourcespecifies the DMA Request sources. This parameter can be any combination of the following values:
    +
  • TIM_DMA_Update: TIM update Interrupt source
    • +
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
    • +
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
    • +
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
    • +
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
    • +
  • TIM_DMA_COM: TIM Commutation DMA source
    • +
  • TIM_DMA_Trigger: TIM Trigger DMA source
    • +
+
NewStatenew state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_DMAConfig (TIM_TypeDef * TIMx,
uint16_t TIM_DMABase,
uint16_t TIM_DMABurstLength 
)
+
+ +

Configures the TIMx's DMA interface.

+
Parameters
+ + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_DMABaseDMA Base address. This parameter can be one of the following values:
    +
  • TIM_DMABase_CR1
    • +
  • TIM_DMABase_CR2
    • +
  • TIM_DMABase_SMCR
    • +
  • TIM_DMABase_DIER
    • +
  • TIM1_DMABase_SR
    • +
  • TIM_DMABase_EGR
    • +
  • TIM_DMABase_CCMR1
    • +
  • TIM_DMABase_CCMR2
    • +
  • TIM_DMABase_CCER
    • +
  • TIM_DMABase_CNT
    • +
  • TIM_DMABase_PSC
    • +
  • TIM_DMABase_ARR
    • +
  • TIM_DMABase_RCR
    • +
  • TIM_DMABase_CCR1
    • +
  • TIM_DMABase_CCR2
    • +
  • TIM_DMABase_CCR3
    • +
  • TIM_DMABase_CCR4
    • +
  • TIM_DMABase_BDTR
    • +
  • TIM_DMABase_DCR
    • +
+
TIM_DMABurstLengthDMA Burst length. This parameter can be one value between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_GenerateEvent (TIM_TypeDef * TIMx,
uint16_t TIM_EventSource 
)
+
+ +

Configures the TIMx event to be generate by software.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_EventSourcespecifies the event source. This parameter can be one or more of the following values:
    +
  • TIM_EventSource_Update: Timer update Event source
    • +
  • TIM_EventSource_CC1: Timer Capture Compare 1 Event source
    • +
  • TIM_EventSource_CC2: Timer Capture Compare 2 Event source
    • +
  • TIM_EventSource_CC3: Timer Capture Compare 3 Event source
    • +
  • TIM_EventSource_CC4: Timer Capture Compare 4 Event source
    • +
  • TIM_EventSource_COM: Timer COM event source
    • +
  • TIM_EventSource_Trigger: Timer Trigger Event source
    • +
  • TIM_EventSource_Break: Timer Break event source
    • +
+
+
+
+
Note
TIM6 and TIM7 can only generate an update event.
+
+TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus TIM_GetFlagStatus (TIM_TypeDef * TIMx,
uint16_t TIM_FLAG 
)
+
+ +

Checks whether the specified TIM flag is set or not.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • TIM_FLAG_Update: TIM update Flag
    • +
  • TIM_FLAG_CC1: TIM Capture Compare 1 Flag
    • +
  • TIM_FLAG_CC2: TIM Capture Compare 2 Flag
    • +
  • TIM_FLAG_CC3: TIM Capture Compare 3 Flag
    • +
  • TIM_FLAG_CC4: TIM Capture Compare 4 Flag
    • +
  • TIM_FLAG_COM: TIM Commutation Flag
    • +
  • TIM_FLAG_Trigger: TIM Trigger Flag
    • +
  • TIM_FLAG_Break: TIM Break Flag
    • +
  • TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
    • +
  • TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
    • +
  • TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
    • +
  • TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
    • +
+
+
+
+
Note
TIM6 and TIM7 can have only one update flag.
+
+TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
Thenew state of TIM_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus TIM_GetITStatus (TIM_TypeDef * TIMx,
uint16_t TIM_IT 
)
+
+ +

Checks whether the TIM interrupt has occurred or not.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIM peripheral.
TIM_ITspecifies the TIM interrupt source to check. This parameter can be one of the following values:
    +
  • TIM_IT_Update: TIM update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
TIM6 and TIM7 can generate only an update interrupt.
+
+TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+
Return values
+ + +
Thenew state of the TIM_IT(SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_ITConfig (TIM_TypeDef * TIMx,
uint16_t TIM_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified TIM interrupts.

+
Parameters
+ + + +
TIMxwhere x can be 1 to 14 to select the TIMx peripheral.
TIM_ITspecifies the TIM interrupts sources to be enabled or disabled. This parameter can be any combination of the following values:
    +
  • TIM_IT_Update: TIM update Interrupt source
    • +
  • TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
    • +
  • TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
    • +
  • TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
    • +
  • TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
    • +
  • TIM_IT_COM: TIM Commutation Interrupt source
    • +
  • TIM_IT_Trigger: TIM Trigger Interrupt source
    • +
  • TIM_IT_Break: TIM Break Interrupt source
    • +
+
+
+
+
Note
For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
+
+For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
+
+For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can be used: TIM_IT_Update or TIM_IT_CC1
+
+TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
+
Parameters
+ + +
NewStatenew state of the TIM interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_SelectCCDMA (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Selects the TIMx peripheral Capture Compare DMA source.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
NewStatenew state of the Capture Compare DMA source This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group5.map b/group___t_i_m___group5.map new file mode 100644 index 0000000..26bccf0 --- /dev/null +++ b/group___t_i_m___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group5.md5 b/group___t_i_m___group5.md5 new file mode 100644 index 0000000..b1d27b0 --- /dev/null +++ b/group___t_i_m___group5.md5 @@ -0,0 +1 @@ +f8377a1521f55bf8e1e0a6fe248c4cdd \ No newline at end of file diff --git a/group___t_i_m___group5.png b/group___t_i_m___group5.png new file mode 100644 index 0000000..57912aa Binary files /dev/null and b/group___t_i_m___group5.png differ diff --git a/group___t_i_m___group6.html b/group___t_i_m___group6.html new file mode 100644 index 0000000..0a4d815 --- /dev/null +++ b/group___t_i_m___group6.html @@ -0,0 +1,435 @@ + + + + + + +discoverpixy: Clocks management functions + + + + + + + + + + +
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+
discoverpixy +
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+ + +
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+ +
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+Functions
+
+
Clocks management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Clocks management functions. +More...

+
+Collaboration diagram for Clocks management functions:
+
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+ + + + + + + + + + + + + + + + + +

+Functions

void TIM_InternalClockConfig (TIM_TypeDef *TIMx)
 Configures the TIMx internal Clock. More...
 
void TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Configures the TIMx Internal Trigger as External Clock. More...
 
void TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
 Configures the TIMx Trigger as External Clock. More...
 
void TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode1. More...
 
void TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode2. More...
 
+

Detailed Description

+

Clocks management functions.

+
 ===============================================================================
+                  ##### Clocks management functions #####
+ ===============================================================================

Function Documentation

+ +
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void TIM_ETRClockMode1Config (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the External clock Mode1.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
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void TIM_ETRClockMode2Config (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the External clock Mode2.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
+ +

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void TIM_InternalClockConfig (TIM_TypeDef * TIMx)
+
+ +

Configures the TIMx internal Clock.

+
Parameters
+ + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
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void TIM_ITRxExternalClockConfig (TIM_TypeDef * TIMx,
uint16_t TIM_InputTriggerSource 
)
+
+ +

Configures the TIMx Internal Trigger as External Clock.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_InputTriggerSourceTrigger source. This parameter can be one of the following values:
    +
  • TIM_TS_ITR0: Internal Trigger 0
    • +
  • TIM_TS_ITR1: Internal Trigger 1
    • +
  • TIM_TS_ITR2: Internal Trigger 2
    • +
  • TIM_TS_ITR3: Internal Trigger 3
    • +
+
+
+
+
Return values
+ + +
None
+
+
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void TIM_TIxExternalClockConfig (TIM_TypeDef * TIMx,
uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity,
uint16_t ICFilter 
)
+
+ +

Configures the TIMx Trigger as External Clock.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the TIM peripheral.
TIM_TIxExternalCLKSourceTrigger source. This parameter can be one of the following values:
    +
  • TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
    • +
  • TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
    • +
  • TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
    • +
+
TIM_ICPolarityspecifies the TIx Polarity. This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Rising
    • +
  • TIM_ICPolarity_Falling
    • +
+
ICFilterspecifies the filter value. This parameter must be a value between 0x0 and 0xF.
+
+
+
Return values
+ + +
None
+
+
+ +

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group6.map b/group___t_i_m___group6.map new file mode 100644 index 0000000..dac013c --- /dev/null +++ b/group___t_i_m___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group6.md5 b/group___t_i_m___group6.md5 new file mode 100644 index 0000000..1f85caa --- /dev/null +++ b/group___t_i_m___group6.md5 @@ -0,0 +1 @@ +1442ee4723634ad68d1242ed8db96da2 \ No newline at end of file diff --git a/group___t_i_m___group6.png b/group___t_i_m___group6.png new file mode 100644 index 0000000..a8b4932 Binary files /dev/null and b/group___t_i_m___group6.png differ diff --git a/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map new file mode 100644 index 0000000..2c438eb --- /dev/null +++ b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.md5 b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.md5 new file mode 100644 index 0000000..f52c05d --- /dev/null +++ b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.md5 @@ -0,0 +1 @@ +9d2f8816579c7a43e62e530946ed040b \ No newline at end of file diff --git a/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.png b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.png new file mode 100644 index 0000000..c457648 Binary files /dev/null and b/group___t_i_m___group6_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.png differ diff --git a/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.map b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.map new file mode 100644 index 0000000..a3feae1 --- /dev/null +++ b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.md5 b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.md5 new file mode 100644 index 0000000..d80a51a --- /dev/null +++ b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.md5 @@ -0,0 +1 @@ +1d690aeed52c57b1ca29c671b40af788 \ No newline at end of file diff --git a/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.png b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.png new file mode 100644 index 0000000..987c6d6 Binary files /dev/null and b/group___t_i_m___group6_ga47c05638b93aabcd641dbc8859e1b2df_cgraph.png differ diff --git a/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.map b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.map new file mode 100644 index 0000000..952ac1e --- /dev/null +++ b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.md5 b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.md5 new file mode 100644 index 0000000..c74835f --- /dev/null +++ b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.md5 @@ -0,0 +1 @@ +2aee61973306ed0c5007d639d84e7bf2 \ No newline at end of file diff --git a/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.png b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.png new file mode 100644 index 0000000..f0efb09 Binary files /dev/null and b/group___t_i_m___group6_gabef227d21d9e121e6a4ec5ab6223f5a9_cgraph.png differ diff --git a/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.map b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.map new file mode 100644 index 0000000..0baee4f --- /dev/null +++ b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.md5 b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.md5 new file mode 100644 index 0000000..5c158a2 --- /dev/null +++ b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.md5 @@ -0,0 +1 @@ +ae9a066c8f088096e23e1993d1733eaf \ No newline at end of file diff --git a/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.png b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.png new file mode 100644 index 0000000..f638e67 Binary files /dev/null and b/group___t_i_m___group6_gaf460e7d9c9969044e364130e209937fc_cgraph.png differ diff --git a/group___t_i_m___group7.html b/group___t_i_m___group7.html new file mode 100644 index 0000000..8a945b3 --- /dev/null +++ b/group___t_i_m___group7.html @@ -0,0 +1,435 @@ + + + + + + +discoverpixy: Synchronization management functions + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
Synchronization management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Synchronization management functions. +More...

+
+Collaboration diagram for Synchronization management functions:
+
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+ + +
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+ + + + + + + + + + + + + + + + + +

+Functions

void TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Selects the Input Trigger source. More...
 
void TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
 Selects the TIMx Trigger Output Mode. More...
 
void TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
 Selects the TIMx Slave Mode. More...
 
void TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
 Sets or Resets the TIMx Master/Slave Mode. More...
 
void TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the TIMx External Trigger (ETR). More...
 
+

Detailed Description

+

Synchronization management functions.

+
 ===============================================================================
+                ##### Synchronization management functions #####
+ ===============================================================================  
+                         
+          ##### TIM Driver: how to use it in synchronization Mode #####
+ ===============================================================================
+    [..] 
+    
+    *** Case of two/several Timers ***
+    ==================================
+    [..]
+      (#) Configure the Master Timers using the following functions:
+        (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 
+        (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);  
+      (#) Configure the Slave Timers using the following functions: 
+        (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+        (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+          
+    *** Case of Timers and external trigger(ETR pin) ***
+    ====================================================
+    [..]           
+      (#) Configure the External trigger using this function:
+        (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                               uint16_t ExtTRGFilter);
+      (#) Configure the Slave Timers using the following functions: 
+        (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+        (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);

Function Documentation

+ +
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void TIM_ETRConfig (TIM_TypeDef * TIMx,
uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter 
)
+
+ +

Configures the TIMx External Trigger (ETR).

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
TIM_ExtTRGPrescalerThe external Trigger Prescaler. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
    • +
  • TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
    • +
  • TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
    • +
  • TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
    • +
+
TIM_ExtTRGPolarityThe external Trigger Polarity. This parameter can be one of the following values:
    +
  • TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
    • +
  • TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
    • +
+
ExtTRGFilterExternal Trigger Filter. This parameter must be a value between 0x00 and 0x0F
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the caller graph for this function:
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void TIM_SelectInputTrigger (TIM_TypeDef * TIMx,
uint16_t TIM_InputTriggerSource 
)
+
+ +

Selects the Input Trigger source.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the TIM peripheral.
TIM_InputTriggerSourceThe Input Trigger source. This parameter can be one of the following values:
    +
  • TIM_TS_ITR0: Internal Trigger 0
    • +
  • TIM_TS_ITR1: Internal Trigger 1
    • +
  • TIM_TS_ITR2: Internal Trigger 2
    • +
  • TIM_TS_ITR3: Internal Trigger 3
    • +
  • TIM_TS_TI1F_ED: TI1 Edge Detector
    • +
  • TIM_TS_TI1FP1: Filtered Timer Input 1
    • +
  • TIM_TS_TI2FP2: Filtered Timer Input 2
    • +
  • TIM_TS_ETRF: External Trigger input
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +

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void TIM_SelectMasterSlaveMode (TIM_TypeDef * TIMx,
uint16_t TIM_MasterSlaveMode 
)
+
+ +

Sets or Resets the TIMx Master/Slave Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_MasterSlaveModespecifies the Timer Master Slave Mode. This parameter can be one of the following values:
    +
  • TIM_MasterSlaveMode_Enable: synchronization between the current timer and its slaves (through TRGO)
    • +
  • TIM_MasterSlaveMode_Disable: No action
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
void TIM_SelectOutputTrigger (TIM_TypeDef * TIMx,
uint16_t TIM_TRGOSource 
)
+
+ +

Selects the TIMx Trigger Output Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
TIM_TRGOSourcespecifies the Trigger Output source. This parameter can be one of the following values:
+
+
+
    +
  • For all TIMx
      +
    • TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
      • +
    +
    • +
  • For all TIMx except TIM6 and TIM7
      +
    • TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag is to be set, as soon as a capture or compare match occurs(TRGO)
      • +
    • TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
      • +
    • TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
      • +
    +
    Return values
    + + +
    None
    +
    +
    +
    • +
+ +
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void TIM_SelectSlaveMode (TIM_TypeDef * TIMx,
uint16_t TIM_SlaveMode 
)
+
+ +

Selects the TIMx Slave Mode.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_SlaveModespecifies the Timer Slave Mode. This parameter can be one of the following values:
    +
  • TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize the counter and triggers an update of the registers
    • +
  • TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
    • +
  • TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
    • +
  • TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group7.map b/group___t_i_m___group7.map new file mode 100644 index 0000000..b15e380 --- /dev/null +++ b/group___t_i_m___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group7.md5 b/group___t_i_m___group7.md5 new file mode 100644 index 0000000..eccbfe8 --- /dev/null +++ b/group___t_i_m___group7.md5 @@ -0,0 +1 @@ +4843fecb860337635e132a6949bcd893 \ No newline at end of file diff --git a/group___t_i_m___group7.png b/group___t_i_m___group7.png new file mode 100644 index 0000000..d076dd0 Binary files /dev/null and b/group___t_i_m___group7.png differ diff --git a/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.map b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.map new file mode 100644 index 0000000..3780339 --- /dev/null +++ b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.md5 b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.md5 new file mode 100644 index 0000000..e39d36f --- /dev/null +++ b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.md5 @@ -0,0 +1 @@ +2364bf1b68eb7a693fa2337a1b7b4ff0 \ No newline at end of file diff --git a/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.png b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.png new file mode 100644 index 0000000..4b3f418 Binary files /dev/null and b/group___t_i_m___group7_ga4252583c6ae8a73d6fc66f7e951dbc35_icgraph.png differ diff --git a/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.map b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.map new file mode 100644 index 0000000..0c022fb --- /dev/null +++ b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.md5 b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.md5 new file mode 100644 index 0000000..03beadf --- /dev/null +++ b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.md5 @@ -0,0 +1 @@ +2c081d5a7487a87805d0e866806a7d77 \ No newline at end of file diff --git a/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.png b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.png new file mode 100644 index 0000000..0a4677c Binary files /dev/null and b/group___t_i_m___group7_ga8bdde400b7a30f3e747fe8e4962c0abe_icgraph.png differ diff --git a/group___t_i_m___group8.html b/group___t_i_m___group8.html new file mode 100644 index 0000000..47b7597 --- /dev/null +++ b/group___t_i_m___group8.html @@ -0,0 +1,228 @@ + + + + + + +discoverpixy: Specific interface management functions + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
Specific interface management functions
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Specific interface management functions. +More...

+
+Collaboration diagram for Specific interface management functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
 Configures the TIMx Encoder Interface. More...
 
void TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIMx's Hall sensor interface. More...
 
+

Detailed Description

+

Specific interface management functions.

+
 ===============================================================================
+            ##### Specific interface management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void TIM_EncoderInterfaceConfig (TIM_TypeDef * TIMx,
uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity,
uint16_t TIM_IC2Polarity 
)
+
+ +

Configures the TIMx Encoder Interface.

+
Parameters
+ + + + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
TIM_EncoderModespecifies the TIMx Encoder Mode. This parameter can be one of the following values:
    +
  • TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
    • +
  • TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
    • +
  • TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
    • +
+
TIM_IC1Polarityspecifies the IC1 Polarity This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Falling: IC Falling edge.
    • +
  • TIM_ICPolarity_Rising: IC Rising edge.
    • +
+
TIM_IC2Polarityspecifies the IC2 Polarity This parameter can be one of the following values:
    +
  • TIM_ICPolarity_Falling: IC Falling edge.
    • +
  • TIM_ICPolarity_Rising: IC Rising edge.
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
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+ +
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void TIM_SelectHallSensor (TIM_TypeDef * TIMx,
FunctionalState NewState 
)
+
+ +

Enables or disables the TIMx's Hall sensor interface.

+
Parameters
+ + + +
TIMxwhere x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
NewStatenew state of the TIMx Hall sensor interface. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group8.map b/group___t_i_m___group8.map new file mode 100644 index 0000000..666b174 --- /dev/null +++ b/group___t_i_m___group8.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group8.md5 b/group___t_i_m___group8.md5 new file mode 100644 index 0000000..e9f9082 --- /dev/null +++ b/group___t_i_m___group8.md5 @@ -0,0 +1 @@ +5c7d5b994d297748f7123c78fab017d0 \ No newline at end of file diff --git a/group___t_i_m___group8.png b/group___t_i_m___group8.png new file mode 100644 index 0000000..c214355 Binary files /dev/null and b/group___t_i_m___group8.png differ diff --git a/group___t_i_m___group9.html b/group___t_i_m___group9.html new file mode 100644 index 0000000..4e3a5ad --- /dev/null +++ b/group___t_i_m___group9.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: Specific remapping management function + + + + + + + + + + +
+
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discoverpixy +
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+Functions
+
+
Specific remapping management function
STM32F4xx_StdPeriph_Driver » TIM » TIM_Private_Functions
+
+
+ +

Specific remapping management function. +More...

+
+Collaboration diagram for Specific remapping management function:
+
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+ + +
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+ + + + + +

+Functions

void TIM_RemapConfig (TIM_TypeDef *TIMx, uint16_t TIM_Remap)
 Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. More...
 
+

Detailed Description

+

Specific remapping management function.

+
 ===============================================================================
+              ##### Specific remapping management function #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void TIM_RemapConfig (TIM_TypeDef * TIMx,
uint16_t TIM_Remap 
)
+
+ +

Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.

+
Parameters
+ + + +
TIMxwhere x can be 2, 5 or 11 to select the TIM peripheral.
TIM_Remapspecifies the TIM input remapping source. This parameter can be one of the following values:
    +
  • TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
    • +
  • TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
    • +
  • TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
    • +
  • TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
    • +
  • TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
    • +
  • TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
    • +
  • TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
    • +
  • TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
    • +
  • TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
    • +
  • TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock (HSE divided by a programmable prescaler)
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___group9.map b/group___t_i_m___group9.map new file mode 100644 index 0000000..f5b0b2b --- /dev/null +++ b/group___t_i_m___group9.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___group9.md5 b/group___t_i_m___group9.md5 new file mode 100644 index 0000000..ffba3ad --- /dev/null +++ b/group___t_i_m___group9.md5 @@ -0,0 +1 @@ +05b6bb5ee0e823367f1540ad045b0590 \ No newline at end of file diff --git a/group___t_i_m___group9.png b/group___t_i_m___group9.png new file mode 100644 index 0000000..e6ec0a5 Binary files /dev/null and b/group___t_i_m___group9.png differ diff --git a/group___t_i_m___input___capture___filer___value.html b/group___t_i_m___input___capture___filer___value.html new file mode 100644 index 0000000..24f0c05 --- /dev/null +++ b/group___t_i_m___input___capture___filer___value.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: TIM_Input_Capture_Filer_Value + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Input_Capture_Filer_Value
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Input_Capture_Filer_Value:
+
+
+ + +
+
+ + + + +

+Macros

+#define IS_TIM_IC_FILTER(ICFILTER)   ((ICFILTER) <= 0xF)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___input___capture___filer___value.map b/group___t_i_m___input___capture___filer___value.map new file mode 100644 index 0000000..6068db0 --- /dev/null +++ b/group___t_i_m___input___capture___filer___value.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___input___capture___filer___value.md5 b/group___t_i_m___input___capture___filer___value.md5 new file mode 100644 index 0000000..de4e75b --- /dev/null +++ b/group___t_i_m___input___capture___filer___value.md5 @@ -0,0 +1 @@ +5168eeb3870ae60a93cbbd50d2ffcd18 \ No newline at end of file diff --git a/group___t_i_m___input___capture___filer___value.png b/group___t_i_m___input___capture___filer___value.png new file mode 100644 index 0000000..b4114d2 Binary files /dev/null and b/group___t_i_m___input___capture___filer___value.png differ diff --git a/group___t_i_m___input___capture___polarity.html b/group___t_i_m___input___capture___polarity.html new file mode 100644 index 0000000..23ecc40 --- /dev/null +++ b/group___t_i_m___input___capture___polarity.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: TIM_Input_Capture_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Input_Capture_Polarity
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Input_Capture_Polarity:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define TIM_ICPolarity_Rising   ((uint16_t)0x0000)
 
+#define TIM_ICPolarity_Falling   ((uint16_t)0x0002)
 
+#define TIM_ICPolarity_BothEdge   ((uint16_t)0x000A)
 
#define IS_TIM_IC_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_IC_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == TIM_ICPolarity_Rising) || \
+
((POLARITY) == TIM_ICPolarity_Falling)|| \
+
((POLARITY) == TIM_ICPolarity_BothEdge))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___input___capture___polarity.map b/group___t_i_m___input___capture___polarity.map new file mode 100644 index 0000000..dc07694 --- /dev/null +++ b/group___t_i_m___input___capture___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___input___capture___polarity.md5 b/group___t_i_m___input___capture___polarity.md5 new file mode 100644 index 0000000..07828cd --- /dev/null +++ b/group___t_i_m___input___capture___polarity.md5 @@ -0,0 +1 @@ +f8ebcd894abcf7ed1bfc714e7e8bd7c7 \ No newline at end of file diff --git a/group___t_i_m___input___capture___polarity.png b/group___t_i_m___input___capture___polarity.png new file mode 100644 index 0000000..b88651d Binary files /dev/null and b/group___t_i_m___input___capture___polarity.png differ diff --git a/group___t_i_m___input___capture___prescaler.html b/group___t_i_m___input___capture___prescaler.html new file mode 100644 index 0000000..391aee7 --- /dev/null +++ b/group___t_i_m___input___capture___prescaler.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: TIM_Input_Capture_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Input_Capture_Prescaler
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Input_Capture_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

#define TIM_ICPSC_DIV1   ((uint16_t)0x0000)
 
#define TIM_ICPSC_DIV2   ((uint16_t)0x0004)
 
#define TIM_ICPSC_DIV4   ((uint16_t)0x0008)
 
#define TIM_ICPSC_DIV8   ((uint16_t)0x000C)
 
#define IS_TIM_IC_PRESCALER(PRESCALER)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_IC_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
+
((PRESCALER) == TIM_ICPSC_DIV2) || \
+
((PRESCALER) == TIM_ICPSC_DIV4) || \
+
((PRESCALER) == TIM_ICPSC_DIV8))
+
TIM_ICPSC_DIV8
#define TIM_ICPSC_DIV8
Definition: stm32f4xx_tim.h:542
+
TIM_ICPSC_DIV1
#define TIM_ICPSC_DIV1
Definition: stm32f4xx_tim.h:539
+
TIM_ICPSC_DIV4
#define TIM_ICPSC_DIV4
Definition: stm32f4xx_tim.h:541
+
TIM_ICPSC_DIV2
#define TIM_ICPSC_DIV2
Definition: stm32f4xx_tim.h:540
+
+
+
+ +
+
+ + + + +
#define TIM_ICPSC_DIV1   ((uint16_t)0x0000)
+
+

Capture performed each time an edge is detected on the capture input.

+ +
+
+ +
+
+ + + + +
#define TIM_ICPSC_DIV2   ((uint16_t)0x0004)
+
+

Capture performed once every 2 events.

+ +
+
+ +
+
+ + + + +
#define TIM_ICPSC_DIV4   ((uint16_t)0x0008)
+
+

Capture performed once every 4 events.

+ +
+
+ +
+
+ + + + +
#define TIM_ICPSC_DIV8   ((uint16_t)0x000C)
+
+

Capture performed once every 8 events.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___input___capture___prescaler.map b/group___t_i_m___input___capture___prescaler.map new file mode 100644 index 0000000..c5c4579 --- /dev/null +++ b/group___t_i_m___input___capture___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___input___capture___prescaler.md5 b/group___t_i_m___input___capture___prescaler.md5 new file mode 100644 index 0000000..e3925b9 --- /dev/null +++ b/group___t_i_m___input___capture___prescaler.md5 @@ -0,0 +1 @@ +c6578fd99d8c3150daa135db73a55a3e \ No newline at end of file diff --git a/group___t_i_m___input___capture___prescaler.png b/group___t_i_m___input___capture___prescaler.png new file mode 100644 index 0000000..82d30c7 Binary files /dev/null and b/group___t_i_m___input___capture___prescaler.png differ diff --git a/group___t_i_m___input___capture___selection.html b/group___t_i_m___input___capture___selection.html new file mode 100644 index 0000000..4f96bbc --- /dev/null +++ b/group___t_i_m___input___capture___selection.html @@ -0,0 +1,176 @@ + + + + + + +discoverpixy: TIM_Input_Capture_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Input_Capture_Selection
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Input_Capture_Selection:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

#define TIM_ICSelection_DirectTI   ((uint16_t)0x0001)
 
#define TIM_ICSelection_IndirectTI   ((uint16_t)0x0002)
 
#define TIM_ICSelection_TRC   ((uint16_t)0x0003)
 
#define IS_TIM_IC_SELECTION(SELECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_IC_SELECTION( SELECTION)
+
+Value:
(((SELECTION) == TIM_ICSelection_DirectTI) || \
+
((SELECTION) == TIM_ICSelection_IndirectTI) || \
+
((SELECTION) == TIM_ICSelection_TRC))
+
TIM_ICSelection_IndirectTI
#define TIM_ICSelection_IndirectTI
Definition: stm32f4xx_tim.h:524
+
TIM_ICSelection_TRC
#define TIM_ICSelection_TRC
Definition: stm32f4xx_tim.h:527
+
TIM_ICSelection_DirectTI
#define TIM_ICSelection_DirectTI
Definition: stm32f4xx_tim.h:521
+
+
+
+ +
+
+ + + + +
#define TIM_ICSelection_DirectTI   ((uint16_t)0x0001)
+
+

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

+ +
+
+ +
+
+ + + + +
#define TIM_ICSelection_IndirectTI   ((uint16_t)0x0002)
+
+

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively.

+ +
+
+ +
+
+ + + + +
#define TIM_ICSelection_TRC   ((uint16_t)0x0003)
+
+

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___input___capture___selection.map b/group___t_i_m___input___capture___selection.map new file mode 100644 index 0000000..23c5063 --- /dev/null +++ b/group___t_i_m___input___capture___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___input___capture___selection.md5 b/group___t_i_m___input___capture___selection.md5 new file mode 100644 index 0000000..a0790c1 --- /dev/null +++ b/group___t_i_m___input___capture___selection.md5 @@ -0,0 +1 @@ +ec6f66c41039619359e071a85a05ada6 \ No newline at end of file diff --git a/group___t_i_m___input___capture___selection.png b/group___t_i_m___input___capture___selection.png new file mode 100644 index 0000000..20a4a1d Binary files /dev/null and b/group___t_i_m___input___capture___selection.png differ diff --git a/group___t_i_m___internal___trigger___selection.html b/group___t_i_m___internal___trigger___selection.html new file mode 100644 index 0000000..676fc85 --- /dev/null +++ b/group___t_i_m___internal___trigger___selection.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: TIM_Internal_Trigger_Selection + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Internal_Trigger_Selection
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Internal_Trigger_Selection:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_TS_ITR0   ((uint16_t)0x0000)
 
+#define TIM_TS_ITR1   ((uint16_t)0x0010)
 
+#define TIM_TS_ITR2   ((uint16_t)0x0020)
 
+#define TIM_TS_ITR3   ((uint16_t)0x0030)
 
+#define TIM_TS_TI1F_ED   ((uint16_t)0x0040)
 
+#define TIM_TS_TI1FP1   ((uint16_t)0x0050)
 
+#define TIM_TS_TI2FP2   ((uint16_t)0x0060)
 
+#define TIM_TS_ETRF   ((uint16_t)0x0070)
 
#define IS_TIM_TRIGGER_SELECTION(SELECTION)
 
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_INTERNAL_TRIGGER_SELECTION( SELECTION)
+
+Value:
(((SELECTION) == TIM_TS_ITR0) || \
+
((SELECTION) == TIM_TS_ITR1) || \
+
((SELECTION) == TIM_TS_ITR2) || \
+
((SELECTION) == TIM_TS_ITR3))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_TRIGGER_SELECTION( SELECTION)
+
+Value:
(((SELECTION) == TIM_TS_ITR0) || \
+
((SELECTION) == TIM_TS_ITR1) || \
+
((SELECTION) == TIM_TS_ITR2) || \
+
((SELECTION) == TIM_TS_ITR3) || \
+
((SELECTION) == TIM_TS_TI1F_ED) || \
+
((SELECTION) == TIM_TS_TI1FP1) || \
+
((SELECTION) == TIM_TS_TI2FP2) || \
+
((SELECTION) == TIM_TS_ETRF))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___internal___trigger___selection.map b/group___t_i_m___internal___trigger___selection.map new file mode 100644 index 0000000..c5c9d90 --- /dev/null +++ b/group___t_i_m___internal___trigger___selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___internal___trigger___selection.md5 b/group___t_i_m___internal___trigger___selection.md5 new file mode 100644 index 0000000..33cd5df --- /dev/null +++ b/group___t_i_m___internal___trigger___selection.md5 @@ -0,0 +1 @@ +8ec2bf156b2a344018264935ce4235ab \ No newline at end of file diff --git a/group___t_i_m___internal___trigger___selection.png b/group___t_i_m___internal___trigger___selection.png new file mode 100644 index 0000000..0281d30 Binary files /dev/null and b/group___t_i_m___internal___trigger___selection.png differ diff --git a/group___t_i_m___legacy.html b/group___t_i_m___legacy.html new file mode 100644 index 0000000..6a017f4 --- /dev/null +++ b/group___t_i_m___legacy.html @@ -0,0 +1,160 @@ + + + + + + +discoverpixy: TIM_Legacy + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
TIM_Legacy
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Legacy:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_DMABurstLength_1Byte   TIM_DMABurstLength_1Transfer
 
+#define TIM_DMABurstLength_2Bytes   TIM_DMABurstLength_2Transfers
 
+#define TIM_DMABurstLength_3Bytes   TIM_DMABurstLength_3Transfers
 
+#define TIM_DMABurstLength_4Bytes   TIM_DMABurstLength_4Transfers
 
+#define TIM_DMABurstLength_5Bytes   TIM_DMABurstLength_5Transfers
 
+#define TIM_DMABurstLength_6Bytes   TIM_DMABurstLength_6Transfers
 
+#define TIM_DMABurstLength_7Bytes   TIM_DMABurstLength_7Transfers
 
+#define TIM_DMABurstLength_8Bytes   TIM_DMABurstLength_8Transfers
 
+#define TIM_DMABurstLength_9Bytes   TIM_DMABurstLength_9Transfers
 
+#define TIM_DMABurstLength_10Bytes   TIM_DMABurstLength_10Transfers
 
+#define TIM_DMABurstLength_11Bytes   TIM_DMABurstLength_11Transfers
 
+#define TIM_DMABurstLength_12Bytes   TIM_DMABurstLength_12Transfers
 
+#define TIM_DMABurstLength_13Bytes   TIM_DMABurstLength_13Transfers
 
+#define TIM_DMABurstLength_14Bytes   TIM_DMABurstLength_14Transfers
 
+#define TIM_DMABurstLength_15Bytes   TIM_DMABurstLength_15Transfers
 
+#define TIM_DMABurstLength_16Bytes   TIM_DMABurstLength_16Transfers
 
+#define TIM_DMABurstLength_17Bytes   TIM_DMABurstLength_17Transfers
 
+#define TIM_DMABurstLength_18Bytes   TIM_DMABurstLength_18Transfers
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___legacy.map b/group___t_i_m___legacy.map new file mode 100644 index 0000000..ed2cf94 --- /dev/null +++ b/group___t_i_m___legacy.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___legacy.md5 b/group___t_i_m___legacy.md5 new file mode 100644 index 0000000..a554f46 --- /dev/null +++ b/group___t_i_m___legacy.md5 @@ -0,0 +1 @@ +3219b00ad60949c1caaa2f835ea58ba6 \ No newline at end of file diff --git a/group___t_i_m___legacy.png b/group___t_i_m___legacy.png new file mode 100644 index 0000000..876c5b9 Binary files /dev/null and b/group___t_i_m___legacy.png differ diff --git a/group___t_i_m___lock__level.html b/group___t_i_m___lock__level.html new file mode 100644 index 0000000..9ee5054 --- /dev/null +++ b/group___t_i_m___lock__level.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: TIM_Lock_level + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
TIM_Lock_level
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Lock_level:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define TIM_LOCKLevel_OFF   ((uint16_t)0x0000)
 
+#define TIM_LOCKLevel_1   ((uint16_t)0x0100)
 
+#define TIM_LOCKLevel_2   ((uint16_t)0x0200)
 
+#define TIM_LOCKLevel_3   ((uint16_t)0x0300)
 
#define IS_TIM_LOCK_LEVEL(LEVEL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_LOCK_LEVEL( LEVEL)
+
+Value:
(((LEVEL) == TIM_LOCKLevel_OFF) || \
+
((LEVEL) == TIM_LOCKLevel_1) || \
+
((LEVEL) == TIM_LOCKLevel_2) || \
+
((LEVEL) == TIM_LOCKLevel_3))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___lock__level.map b/group___t_i_m___lock__level.map new file mode 100644 index 0000000..14f51a1 --- /dev/null +++ b/group___t_i_m___lock__level.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___lock__level.md5 b/group___t_i_m___lock__level.md5 new file mode 100644 index 0000000..5748170 --- /dev/null +++ b/group___t_i_m___lock__level.md5 @@ -0,0 +1 @@ +45abd112c31e76249fdb4b4e2e2552cd \ No newline at end of file diff --git a/group___t_i_m___lock__level.png b/group___t_i_m___lock__level.png new file mode 100644 index 0000000..5738845 Binary files /dev/null and b/group___t_i_m___lock__level.png differ diff --git a/group___t_i_m___master___slave___mode.html b/group___t_i_m___master___slave___mode.html new file mode 100644 index 0000000..0662bd0 --- /dev/null +++ b/group___t_i_m___master___slave___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Master_Slave_Mode + + + + + + + + + + +
+
+ + + + + + +
+
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+ +
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+ +
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+Macros
+
+
TIM_Master_Slave_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Master_Slave_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_MasterSlaveMode_Enable   ((uint16_t)0x0080)
 
+#define TIM_MasterSlaveMode_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_MSM_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_MSM_STATE( STATE)
+
+Value:
(((STATE) == TIM_MasterSlaveMode_Enable) || \
+
((STATE) == TIM_MasterSlaveMode_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___master___slave___mode.map b/group___t_i_m___master___slave___mode.map new file mode 100644 index 0000000..6d859dd --- /dev/null +++ b/group___t_i_m___master___slave___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___master___slave___mode.md5 b/group___t_i_m___master___slave___mode.md5 new file mode 100644 index 0000000..eb127cb --- /dev/null +++ b/group___t_i_m___master___slave___mode.md5 @@ -0,0 +1 @@ +0c1dbcf385b32538c086f6fb6110d4c3 \ No newline at end of file diff --git a/group___t_i_m___master___slave___mode.png b/group___t_i_m___master___slave___mode.png new file mode 100644 index 0000000..aac6826 Binary files /dev/null and b/group___t_i_m___master___slave___mode.png differ diff --git a/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.html b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.html new file mode 100644 index 0000000..54c3ca5 --- /dev/null +++ b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_OSSI_Off_State_Selection_for_Idle_mode_state + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_OSSI_Off_State_Selection_for_Idle_mode_state
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_OSSI_Off_State_Selection_for_Idle_mode_state:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OSSIState_Enable   ((uint16_t)0x0400)
 
+#define TIM_OSSIState_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OSSI_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OSSI_STATE( STATE)
+
+Value:
(((STATE) == TIM_OSSIState_Enable) || \
+
((STATE) == TIM_OSSIState_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.map b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.map new file mode 100644 index 0000000..87c47ce --- /dev/null +++ b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.md5 b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.md5 new file mode 100644 index 0000000..0d7f033 --- /dev/null +++ b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.md5 @@ -0,0 +1 @@ +cf90ead28698f13727e9ef33851eb7bf \ No newline at end of file diff --git a/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.png b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.png new file mode 100644 index 0000000..f31ac7d Binary files /dev/null and b/group___t_i_m___o_s_s_i___off___state___selection__for___idle__mode__state.png differ diff --git a/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.html b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.html new file mode 100644 index 0000000..6780343 --- /dev/null +++ b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_OSSR_Off_State_Selection_for_Run_mode_state + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_OSSR_Off_State_Selection_for_Run_mode_state
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_OSSR_Off_State_Selection_for_Run_mode_state:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OSSRState_Enable   ((uint16_t)0x0800)
 
+#define TIM_OSSRState_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OSSR_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OSSR_STATE( STATE)
+
+Value:
(((STATE) == TIM_OSSRState_Enable) || \
+
((STATE) == TIM_OSSRState_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.map b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.map new file mode 100644 index 0000000..66a1185 --- /dev/null +++ b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.md5 b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.md5 new file mode 100644 index 0000000..7092b06 --- /dev/null +++ b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.md5 @@ -0,0 +1 @@ +d9e80f2f7183fba3311a299a993f5f9b \ No newline at end of file diff --git a/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.png b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.png new file mode 100644 index 0000000..f9edf70 Binary files /dev/null and b/group___t_i_m___o_s_s_r___off___state___selection__for___run__mode__state.png differ diff --git a/group___t_i_m___one___pulse___mode.html b/group___t_i_m___one___pulse___mode.html new file mode 100644 index 0000000..ae4e891 --- /dev/null +++ b/group___t_i_m___one___pulse___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_One_Pulse_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_One_Pulse_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_One_Pulse_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OPMode_Single   ((uint16_t)0x0008)
 
+#define TIM_OPMode_Repetitive   ((uint16_t)0x0000)
 
#define IS_TIM_OPM_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OPM_MODE( MODE)
+
+Value:
(((MODE) == TIM_OPMode_Single) || \
+
((MODE) == TIM_OPMode_Repetitive))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___one___pulse___mode.map b/group___t_i_m___one___pulse___mode.map new file mode 100644 index 0000000..139b6dd --- /dev/null +++ b/group___t_i_m___one___pulse___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___one___pulse___mode.md5 b/group___t_i_m___one___pulse___mode.md5 new file mode 100644 index 0000000..970384e --- /dev/null +++ b/group___t_i_m___one___pulse___mode.md5 @@ -0,0 +1 @@ +315a65b1198aca83155a815f29d6548c \ No newline at end of file diff --git a/group___t_i_m___one___pulse___mode.png b/group___t_i_m___one___pulse___mode.png new file mode 100644 index 0000000..0ec416d Binary files /dev/null and b/group___t_i_m___one___pulse___mode.png differ diff --git a/group___t_i_m___output___compare___clear___state.html b/group___t_i_m___output___compare___clear___state.html new file mode 100644 index 0000000..3bdf497 --- /dev/null +++ b/group___t_i_m___output___compare___clear___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_Clear_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_Clear_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_Clear_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCClear_Enable   ((uint16_t)0x0080)
 
+#define TIM_OCClear_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCCLEAR_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCCLEAR_STATE( STATE)
+
+Value:
(((STATE) == TIM_OCClear_Enable) || \
+
((STATE) == TIM_OCClear_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___clear___state.map b/group___t_i_m___output___compare___clear___state.map new file mode 100644 index 0000000..6ea30fe --- /dev/null +++ b/group___t_i_m___output___compare___clear___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___clear___state.md5 b/group___t_i_m___output___compare___clear___state.md5 new file mode 100644 index 0000000..2c4c1b4 --- /dev/null +++ b/group___t_i_m___output___compare___clear___state.md5 @@ -0,0 +1 @@ +f6c3d25adbbf0377b6ec2054eb9722b9 \ No newline at end of file diff --git a/group___t_i_m___output___compare___clear___state.png b/group___t_i_m___output___compare___clear___state.png new file mode 100644 index 0000000..65ccddc Binary files /dev/null and b/group___t_i_m___output___compare___clear___state.png differ diff --git a/group___t_i_m___output___compare___fast___state.html b/group___t_i_m___output___compare___fast___state.html new file mode 100644 index 0000000..176b2a2 --- /dev/null +++ b/group___t_i_m___output___compare___fast___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_Fast_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_Fast_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_Fast_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCFast_Enable   ((uint16_t)0x0004)
 
+#define TIM_OCFast_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCFAST_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCFAST_STATE( STATE)
+
+Value:
(((STATE) == TIM_OCFast_Enable) || \
+
((STATE) == TIM_OCFast_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___fast___state.map b/group___t_i_m___output___compare___fast___state.map new file mode 100644 index 0000000..7053c5f --- /dev/null +++ b/group___t_i_m___output___compare___fast___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___fast___state.md5 b/group___t_i_m___output___compare___fast___state.md5 new file mode 100644 index 0000000..ef7a703 --- /dev/null +++ b/group___t_i_m___output___compare___fast___state.md5 @@ -0,0 +1 @@ +e41ae65f2005a0494e328e500e23c602 \ No newline at end of file diff --git a/group___t_i_m___output___compare___fast___state.png b/group___t_i_m___output___compare___fast___state.png new file mode 100644 index 0000000..05264d7 Binary files /dev/null and b/group___t_i_m___output___compare___fast___state.png differ diff --git a/group___t_i_m___output___compare___idle___state.html b/group___t_i_m___output___compare___idle___state.html new file mode 100644 index 0000000..c3fe547 --- /dev/null +++ b/group___t_i_m___output___compare___idle___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_Idle_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_Idle_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_Idle_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCIdleState_Set   ((uint16_t)0x0100)
 
+#define TIM_OCIdleState_Reset   ((uint16_t)0x0000)
 
#define IS_TIM_OCIDLE_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCIDLE_STATE( STATE)
+
+Value:
(((STATE) == TIM_OCIdleState_Set) || \
+
((STATE) == TIM_OCIdleState_Reset))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___idle___state.map b/group___t_i_m___output___compare___idle___state.map new file mode 100644 index 0000000..7831220 --- /dev/null +++ b/group___t_i_m___output___compare___idle___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___idle___state.md5 b/group___t_i_m___output___compare___idle___state.md5 new file mode 100644 index 0000000..ec603cd --- /dev/null +++ b/group___t_i_m___output___compare___idle___state.md5 @@ -0,0 +1 @@ +abdd915b669494b381b8b490a1d9fd02 \ No newline at end of file diff --git a/group___t_i_m___output___compare___idle___state.png b/group___t_i_m___output___compare___idle___state.png new file mode 100644 index 0000000..2850e29 Binary files /dev/null and b/group___t_i_m___output___compare___idle___state.png differ diff --git a/group___t_i_m___output___compare___n___idle___state.html b/group___t_i_m___output___compare___n___idle___state.html new file mode 100644 index 0000000..8812e5a --- /dev/null +++ b/group___t_i_m___output___compare___n___idle___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_N_Idle_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_N_Idle_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_N_Idle_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCNIdleState_Set   ((uint16_t)0x0200)
 
+#define TIM_OCNIdleState_Reset   ((uint16_t)0x0000)
 
#define IS_TIM_OCNIDLE_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCNIDLE_STATE( STATE)
+
+Value:
(((STATE) == TIM_OCNIdleState_Set) || \
+
((STATE) == TIM_OCNIdleState_Reset))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___n___idle___state.map b/group___t_i_m___output___compare___n___idle___state.map new file mode 100644 index 0000000..bca5fc8 --- /dev/null +++ b/group___t_i_m___output___compare___n___idle___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___n___idle___state.md5 b/group___t_i_m___output___compare___n___idle___state.md5 new file mode 100644 index 0000000..6e55763 --- /dev/null +++ b/group___t_i_m___output___compare___n___idle___state.md5 @@ -0,0 +1 @@ +3316fd8f15551307d6b65554988c707b \ No newline at end of file diff --git a/group___t_i_m___output___compare___n___idle___state.png b/group___t_i_m___output___compare___n___idle___state.png new file mode 100644 index 0000000..3e3a4cf Binary files /dev/null and b/group___t_i_m___output___compare___n___idle___state.png differ diff --git a/group___t_i_m___output___compare___n___polarity.html b/group___t_i_m___output___compare___n___polarity.html new file mode 100644 index 0000000..f63f801 --- /dev/null +++ b/group___t_i_m___output___compare___n___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_N_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_N_Polarity
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_N_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCNPolarity_High   ((uint16_t)0x0000)
 
+#define TIM_OCNPolarity_Low   ((uint16_t)0x0008)
 
#define IS_TIM_OCN_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCN_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == TIM_OCNPolarity_High) || \
+
((POLARITY) == TIM_OCNPolarity_Low))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___n___polarity.map b/group___t_i_m___output___compare___n___polarity.map new file mode 100644 index 0000000..b874410 --- /dev/null +++ b/group___t_i_m___output___compare___n___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___n___polarity.md5 b/group___t_i_m___output___compare___n___polarity.md5 new file mode 100644 index 0000000..761bd48 --- /dev/null +++ b/group___t_i_m___output___compare___n___polarity.md5 @@ -0,0 +1 @@ +f4ed07c3493a4f4ecc5c2db9ba6f88a6 \ No newline at end of file diff --git a/group___t_i_m___output___compare___n___polarity.png b/group___t_i_m___output___compare___n___polarity.png new file mode 100644 index 0000000..c1727b8 Binary files /dev/null and b/group___t_i_m___output___compare___n___polarity.png differ diff --git a/group___t_i_m___output___compare___n___state.html b/group___t_i_m___output___compare___n___state.html new file mode 100644 index 0000000..7e2b977 --- /dev/null +++ b/group___t_i_m___output___compare___n___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_N_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_N_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_N_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OutputNState_Disable   ((uint16_t)0x0000)
 
+#define TIM_OutputNState_Enable   ((uint16_t)0x0004)
 
#define IS_TIM_OUTPUTN_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OUTPUTN_STATE( STATE)
+
+Value:
(((STATE) == TIM_OutputNState_Disable) || \
+
((STATE) == TIM_OutputNState_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___n___state.map b/group___t_i_m___output___compare___n___state.map new file mode 100644 index 0000000..d2f94ab --- /dev/null +++ b/group___t_i_m___output___compare___n___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___n___state.md5 b/group___t_i_m___output___compare___n___state.md5 new file mode 100644 index 0000000..b52c7ac --- /dev/null +++ b/group___t_i_m___output___compare___n___state.md5 @@ -0,0 +1 @@ +5a3f0b0d309d3ac2e3f856fb8e9b15f6 \ No newline at end of file diff --git a/group___t_i_m___output___compare___n___state.png b/group___t_i_m___output___compare___n___state.png new file mode 100644 index 0000000..ab4c472 Binary files /dev/null and b/group___t_i_m___output___compare___n___state.png differ diff --git a/group___t_i_m___output___compare___polarity.html b/group___t_i_m___output___compare___polarity.html new file mode 100644 index 0000000..130eef4 --- /dev/null +++ b/group___t_i_m___output___compare___polarity.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_Polarity
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCPolarity_High   ((uint16_t)0x0000)
 
+#define TIM_OCPolarity_Low   ((uint16_t)0x0002)
 
#define IS_TIM_OC_POLARITY(POLARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OC_POLARITY( POLARITY)
+
+Value:
(((POLARITY) == TIM_OCPolarity_High) || \
+
((POLARITY) == TIM_OCPolarity_Low))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___polarity.map b/group___t_i_m___output___compare___polarity.map new file mode 100644 index 0000000..c615fb1 --- /dev/null +++ b/group___t_i_m___output___compare___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___polarity.md5 b/group___t_i_m___output___compare___polarity.md5 new file mode 100644 index 0000000..e38c4a5 --- /dev/null +++ b/group___t_i_m___output___compare___polarity.md5 @@ -0,0 +1 @@ +a129fc17ede2b929e3946b9810f46585 \ No newline at end of file diff --git a/group___t_i_m___output___compare___polarity.png b/group___t_i_m___output___compare___polarity.png new file mode 100644 index 0000000..20cbbbc Binary files /dev/null and b/group___t_i_m___output___compare___polarity.png differ diff --git a/group___t_i_m___output___compare___preload___state.html b/group___t_i_m___output___compare___preload___state.html new file mode 100644 index 0000000..3b5deb2 --- /dev/null +++ b/group___t_i_m___output___compare___preload___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_Preload_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_Preload_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_Preload_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OCPreload_Enable   ((uint16_t)0x0008)
 
+#define TIM_OCPreload_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCPRELOAD_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OCPRELOAD_STATE( STATE)
+
+Value:
(((STATE) == TIM_OCPreload_Enable) || \
+
((STATE) == TIM_OCPreload_Disable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___preload___state.map b/group___t_i_m___output___compare___preload___state.map new file mode 100644 index 0000000..ee205e3 --- /dev/null +++ b/group___t_i_m___output___compare___preload___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___preload___state.md5 b/group___t_i_m___output___compare___preload___state.md5 new file mode 100644 index 0000000..4131542 --- /dev/null +++ b/group___t_i_m___output___compare___preload___state.md5 @@ -0,0 +1 @@ +5d086ed8addbe6f11a06401c7ed50a96 \ No newline at end of file diff --git a/group___t_i_m___output___compare___preload___state.png b/group___t_i_m___output___compare___preload___state.png new file mode 100644 index 0000000..0b4e024 Binary files /dev/null and b/group___t_i_m___output___compare___preload___state.png differ diff --git a/group___t_i_m___output___compare___state.html b/group___t_i_m___output___compare___state.html new file mode 100644 index 0000000..166ec3b --- /dev/null +++ b/group___t_i_m___output___compare___state.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Output_Compare_State + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_State
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_State:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_OutputState_Disable   ((uint16_t)0x0000)
 
+#define TIM_OutputState_Enable   ((uint16_t)0x0001)
 
#define IS_TIM_OUTPUT_STATE(STATE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OUTPUT_STATE( STATE)
+
+Value:
(((STATE) == TIM_OutputState_Disable) || \
+
((STATE) == TIM_OutputState_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare___state.map b/group___t_i_m___output___compare___state.map new file mode 100644 index 0000000..aaff3c5 --- /dev/null +++ b/group___t_i_m___output___compare___state.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare___state.md5 b/group___t_i_m___output___compare___state.md5 new file mode 100644 index 0000000..5253958 --- /dev/null +++ b/group___t_i_m___output___compare___state.md5 @@ -0,0 +1 @@ +386a0ae0a4c10280b5769a9699fbe3c7 \ No newline at end of file diff --git a/group___t_i_m___output___compare___state.png b/group___t_i_m___output___compare___state.png new file mode 100644 index 0000000..709a305 Binary files /dev/null and b/group___t_i_m___output___compare___state.png differ diff --git a/group___t_i_m___output___compare__and___p_w_m__modes.html b/group___t_i_m___output___compare__and___p_w_m__modes.html new file mode 100644 index 0000000..cccc2bf --- /dev/null +++ b/group___t_i_m___output___compare__and___p_w_m__modes.html @@ -0,0 +1,175 @@ + + + + + + +discoverpixy: TIM_Output_Compare_and_PWM_modes + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Output_Compare_and_PWM_modes
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Output_Compare_and_PWM_modes:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_OCMode_Timing   ((uint16_t)0x0000)
 
+#define TIM_OCMode_Active   ((uint16_t)0x0010)
 
+#define TIM_OCMode_Inactive   ((uint16_t)0x0020)
 
+#define TIM_OCMode_Toggle   ((uint16_t)0x0030)
 
+#define TIM_OCMode_PWM1   ((uint16_t)0x0060)
 
+#define TIM_OCMode_PWM2   ((uint16_t)0x0070)
 
#define IS_TIM_OC_MODE(MODE)
 
#define IS_TIM_OCM(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_OC_MODE( MODE)
+
+Value:
(((MODE) == TIM_OCMode_Timing) || \
+
((MODE) == TIM_OCMode_Active) || \
+
((MODE) == TIM_OCMode_Inactive) || \
+
((MODE) == TIM_OCMode_Toggle)|| \
+
((MODE) == TIM_OCMode_PWM1) || \
+
((MODE) == TIM_OCMode_PWM2))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_TIM_OCM( MODE)
+
+Value:
(((MODE) == TIM_OCMode_Timing) || \
+
((MODE) == TIM_OCMode_Active) || \
+
((MODE) == TIM_OCMode_Inactive) || \
+
((MODE) == TIM_OCMode_Toggle)|| \
+
((MODE) == TIM_OCMode_PWM1) || \
+
((MODE) == TIM_OCMode_PWM2) || \
+
((MODE) == TIM_ForcedAction_Active) || \
+
((MODE) == TIM_ForcedAction_InActive))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___output___compare__and___p_w_m__modes.map b/group___t_i_m___output___compare__and___p_w_m__modes.map new file mode 100644 index 0000000..f21fb81 --- /dev/null +++ b/group___t_i_m___output___compare__and___p_w_m__modes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___output___compare__and___p_w_m__modes.md5 b/group___t_i_m___output___compare__and___p_w_m__modes.md5 new file mode 100644 index 0000000..dde3a94 --- /dev/null +++ b/group___t_i_m___output___compare__and___p_w_m__modes.md5 @@ -0,0 +1 @@ +ccd051e1976e62e9da60566a1e1b2b49 \ No newline at end of file diff --git a/group___t_i_m___output___compare__and___p_w_m__modes.png b/group___t_i_m___output___compare__and___p_w_m__modes.png new file mode 100644 index 0000000..9606251 Binary files /dev/null and b/group___t_i_m___output___compare__and___p_w_m__modes.png differ diff --git a/group___t_i_m___prescaler___reload___mode.html b/group___t_i_m___prescaler___reload___mode.html new file mode 100644 index 0000000..ff847fc --- /dev/null +++ b/group___t_i_m___prescaler___reload___mode.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Prescaler_Reload_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Prescaler_Reload_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Prescaler_Reload_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_PSCReloadMode_Update   ((uint16_t)0x0000)
 
+#define TIM_PSCReloadMode_Immediate   ((uint16_t)0x0001)
 
#define IS_TIM_PRESCALER_RELOAD(RELOAD)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_PRESCALER_RELOAD( RELOAD)
+
+Value:
(((RELOAD) == TIM_PSCReloadMode_Update) || \
+
((RELOAD) == TIM_PSCReloadMode_Immediate))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___prescaler___reload___mode.map b/group___t_i_m___prescaler___reload___mode.map new file mode 100644 index 0000000..eeaff4a --- /dev/null +++ b/group___t_i_m___prescaler___reload___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___prescaler___reload___mode.md5 b/group___t_i_m___prescaler___reload___mode.md5 new file mode 100644 index 0000000..925a750 --- /dev/null +++ b/group___t_i_m___prescaler___reload___mode.md5 @@ -0,0 +1 @@ +9a0f83d2ed9cfa0f3ba98f80c48bb97e \ No newline at end of file diff --git a/group___t_i_m___prescaler___reload___mode.png b/group___t_i_m___prescaler___reload___mode.png new file mode 100644 index 0000000..4b25458 Binary files /dev/null and b/group___t_i_m___prescaler___reload___mode.png differ diff --git a/group___t_i_m___private___functions.html b/group___t_i_m___private___functions.html new file mode 100644 index 0000000..4849426 --- /dev/null +++ b/group___t_i_m___private___functions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: TIM_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
TIM_Private_Functions
STM32F4xx_StdPeriph_Driver » TIM
+
+
+
+Collaboration diagram for TIM_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 TimeBase management functions
 TimeBase management functions.
 
 Output Compare management functions
 Output Compare management functions.
 
 Input Capture management functions
 Input Capture management functions.
 
 Advanced-control timers (TIM1 and TIM8) specific features
 Advanced-control timers (TIM1 and TIM8) specific features.
 
 Interrupts DMA and flags management functions
 Interrupts, DMA and flags management functions.
 
 Clocks management functions
 Clocks management functions.
 
 Synchronization management functions
 Synchronization management functions.
 
 Specific interface management functions
 Specific interface management functions.
 
 Specific remapping management function
 Specific remapping management function.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___private___functions.map b/group___t_i_m___private___functions.map new file mode 100644 index 0000000..eb87561 --- /dev/null +++ b/group___t_i_m___private___functions.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___t_i_m___private___functions.md5 b/group___t_i_m___private___functions.md5 new file mode 100644 index 0000000..6713a7e --- /dev/null +++ b/group___t_i_m___private___functions.md5 @@ -0,0 +1 @@ +c3c062798b7901c83a5d4fe938e86799 \ No newline at end of file diff --git a/group___t_i_m___private___functions.png b/group___t_i_m___private___functions.png new file mode 100644 index 0000000..7ba7d40 Binary files /dev/null and b/group___t_i_m___private___functions.png differ diff --git a/group___t_i_m___remap.html b/group___t_i_m___remap.html new file mode 100644 index 0000000..c17e95b --- /dev/null +++ b/group___t_i_m___remap.html @@ -0,0 +1,165 @@ + + + + + + +discoverpixy: TIM_Remap + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Remap
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Remap:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM2_TIM8_TRGO   ((uint16_t)0x0000)
 
+#define TIM2_ETH_PTP   ((uint16_t)0x0400)
 
+#define TIM2_USBFS_SOF   ((uint16_t)0x0800)
 
+#define TIM2_USBHS_SOF   ((uint16_t)0x0C00)
 
+#define TIM5_GPIO   ((uint16_t)0x0000)
 
+#define TIM5_LSI   ((uint16_t)0x0040)
 
+#define TIM5_LSE   ((uint16_t)0x0080)
 
+#define TIM5_RTC   ((uint16_t)0x00C0)
 
+#define TIM11_GPIO   ((uint16_t)0x0000)
 
+#define TIM11_HSE   ((uint16_t)0x0002)
 
#define IS_TIM_REMAP(TIM_REMAP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_REMAP( TIM_REMAP)
+
+Value:
(((TIM_REMAP) == TIM2_TIM8_TRGO)||\
+
((TIM_REMAP) == TIM2_ETH_PTP)||\
+
((TIM_REMAP) == TIM2_USBFS_SOF)||\
+
((TIM_REMAP) == TIM2_USBHS_SOF)||\
+
((TIM_REMAP) == TIM5_GPIO)||\
+
((TIM_REMAP) == TIM5_LSI)||\
+
((TIM_REMAP) == TIM5_LSE)||\
+
((TIM_REMAP) == TIM5_RTC)||\
+
((TIM_REMAP) == TIM11_GPIO)||\
+
((TIM_REMAP) == TIM11_HSE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___remap.map b/group___t_i_m___remap.map new file mode 100644 index 0000000..a4ff46d --- /dev/null +++ b/group___t_i_m___remap.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___remap.md5 b/group___t_i_m___remap.md5 new file mode 100644 index 0000000..9586ea8 --- /dev/null +++ b/group___t_i_m___remap.md5 @@ -0,0 +1 @@ +0a279e855e9465b9ea40c5ea5027e0ba \ No newline at end of file diff --git a/group___t_i_m___remap.png b/group___t_i_m___remap.png new file mode 100644 index 0000000..7958284 Binary files /dev/null and b/group___t_i_m___remap.png differ diff --git a/group___t_i_m___slave___mode.html b/group___t_i_m___slave___mode.html new file mode 100644 index 0000000..a38dbff --- /dev/null +++ b/group___t_i_m___slave___mode.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: TIM_Slave_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_Slave_Mode
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Slave_Mode:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define TIM_SlaveMode_Reset   ((uint16_t)0x0004)
 
+#define TIM_SlaveMode_Gated   ((uint16_t)0x0005)
 
+#define TIM_SlaveMode_Trigger   ((uint16_t)0x0006)
 
+#define TIM_SlaveMode_External1   ((uint16_t)0x0007)
 
#define IS_TIM_SLAVE_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_SLAVE_MODE( MODE)
+
+Value:
(((MODE) == TIM_SlaveMode_Reset) || \
+
((MODE) == TIM_SlaveMode_Gated) || \
+
((MODE) == TIM_SlaveMode_Trigger) || \
+
((MODE) == TIM_SlaveMode_External1))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___slave___mode.map b/group___t_i_m___slave___mode.map new file mode 100644 index 0000000..29c78ae --- /dev/null +++ b/group___t_i_m___slave___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___slave___mode.md5 b/group___t_i_m___slave___mode.md5 new file mode 100644 index 0000000..57e4354 --- /dev/null +++ b/group___t_i_m___slave___mode.md5 @@ -0,0 +1 @@ +6e260d9311381a561bb35a9ac7d95211 \ No newline at end of file diff --git a/group___t_i_m___slave___mode.png b/group___t_i_m___slave___mode.png new file mode 100644 index 0000000..93e84b5 Binary files /dev/null and b/group___t_i_m___slave___mode.png differ diff --git a/group___t_i_m___t_ix___external___clock___source.html b/group___t_i_m___t_ix___external___clock___source.html new file mode 100644 index 0000000..f5aab75 --- /dev/null +++ b/group___t_i_m___t_ix___external___clock___source.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: TIM_TIx_External_Clock_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
TIM_TIx_External_Clock_Source
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_TIx_External_Clock_Source:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define TIM_TIxExternalCLK1Source_TI1   ((uint16_t)0x0050)
 
+#define TIM_TIxExternalCLK1Source_TI2   ((uint16_t)0x0060)
 
+#define TIM_TIxExternalCLK1Source_TI1ED   ((uint16_t)0x0040)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___t_ix___external___clock___source.map b/group___t_i_m___t_ix___external___clock___source.map new file mode 100644 index 0000000..31cb337 --- /dev/null +++ b/group___t_i_m___t_ix___external___clock___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___t_ix___external___clock___source.md5 b/group___t_i_m___t_ix___external___clock___source.md5 new file mode 100644 index 0000000..74bfddd --- /dev/null +++ b/group___t_i_m___t_ix___external___clock___source.md5 @@ -0,0 +1 @@ +459ec77d07ef2cadbebf11926629599e \ No newline at end of file diff --git a/group___t_i_m___t_ix___external___clock___source.png b/group___t_i_m___t_ix___external___clock___source.png new file mode 100644 index 0000000..b5f9708 Binary files /dev/null and b/group___t_i_m___t_ix___external___clock___source.png differ diff --git a/group___t_i_m___trigger___output___source.html b/group___t_i_m___trigger___output___source.html new file mode 100644 index 0000000..6cbb919 --- /dev/null +++ b/group___t_i_m___trigger___output___source.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: TIM_Trigger_Output_Source + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ +
+ +
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+Macros
+
+
TIM_Trigger_Output_Source
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Trigger_Output_Source:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_TRGOSource_Reset   ((uint16_t)0x0000)
 
+#define TIM_TRGOSource_Enable   ((uint16_t)0x0010)
 
+#define TIM_TRGOSource_Update   ((uint16_t)0x0020)
 
+#define TIM_TRGOSource_OC1   ((uint16_t)0x0030)
 
+#define TIM_TRGOSource_OC1Ref   ((uint16_t)0x0040)
 
+#define TIM_TRGOSource_OC2Ref   ((uint16_t)0x0050)
 
+#define TIM_TRGOSource_OC3Ref   ((uint16_t)0x0060)
 
+#define TIM_TRGOSource_OC4Ref   ((uint16_t)0x0070)
 
#define IS_TIM_TRGO_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_TRGO_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == TIM_TRGOSource_Reset) || \
+
((SOURCE) == TIM_TRGOSource_Enable) || \
+
((SOURCE) == TIM_TRGOSource_Update) || \
+
((SOURCE) == TIM_TRGOSource_OC1) || \
+
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+
((SOURCE) == TIM_TRGOSource_OC4Ref))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___trigger___output___source.map b/group___t_i_m___trigger___output___source.map new file mode 100644 index 0000000..e40374b --- /dev/null +++ b/group___t_i_m___trigger___output___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___trigger___output___source.md5 b/group___t_i_m___trigger___output___source.md5 new file mode 100644 index 0000000..ccfa801 --- /dev/null +++ b/group___t_i_m___trigger___output___source.md5 @@ -0,0 +1 @@ +eb39ad1aacccbc5a3e76e1019a9f2b68 \ No newline at end of file diff --git a/group___t_i_m___trigger___output___source.png b/group___t_i_m___trigger___output___source.png new file mode 100644 index 0000000..2648464 Binary files /dev/null and b/group___t_i_m___trigger___output___source.png differ diff --git a/group___t_i_m___update___source.html b/group___t_i_m___update___source.html new file mode 100644 index 0000000..35e6cb1 --- /dev/null +++ b/group___t_i_m___update___source.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: TIM_Update_Source + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+Macros
+
+
TIM_Update_Source
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_Update_Source:
+
+
+ + +
+
+ + + + + + + + +

+Macros

#define TIM_UpdateSource_Global   ((uint16_t)0x0000)
 
#define TIM_UpdateSource_Regular   ((uint16_t)0x0001)
 
#define IS_TIM_UPDATE_SOURCE(SOURCE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_UPDATE_SOURCE( SOURCE)
+
+Value:
(((SOURCE) == TIM_UpdateSource_Global) || \
+
((SOURCE) == TIM_UpdateSource_Regular))
+
TIM_UpdateSource_Regular
#define TIM_UpdateSource_Regular
Definition: stm32f4xx_tim.h:819
+
TIM_UpdateSource_Global
#define TIM_UpdateSource_Global
Definition: stm32f4xx_tim.h:814
+
+
+
+ +
+
+ + + + +
#define TIM_UpdateSource_Global   ((uint16_t)0x0000)
+
+

Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller.

+ +
+
+ +
+
+ + + + +
#define TIM_UpdateSource_Regular   ((uint16_t)0x0001)
+
+

Source of update is counter overflow/underflow.

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m___update___source.map b/group___t_i_m___update___source.map new file mode 100644 index 0000000..7bb5a78 --- /dev/null +++ b/group___t_i_m___update___source.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m___update___source.md5 b/group___t_i_m___update___source.md5 new file mode 100644 index 0000000..f09008e --- /dev/null +++ b/group___t_i_m___update___source.md5 @@ -0,0 +1 @@ +0934a14b97902fdbc327334e12be9878 \ No newline at end of file diff --git a/group___t_i_m___update___source.png b/group___t_i_m___update___source.png new file mode 100644 index 0000000..5cff1f6 Binary files /dev/null and b/group___t_i_m___update___source.png differ diff --git a/group___t_i_m__interrupt__sources.html b/group___t_i_m__interrupt__sources.html new file mode 100644 index 0000000..079b063 --- /dev/null +++ b/group___t_i_m__interrupt__sources.html @@ -0,0 +1,160 @@ + + + + + + +discoverpixy: TIM_interrupt_sources + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Macros
+
+
TIM_interrupt_sources
STM32F4xx_StdPeriph_Driver » TIM » TIM_Exported_constants
+
+
+
+Collaboration diagram for TIM_interrupt_sources:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define TIM_IT_Update   ((uint16_t)0x0001)
 
+#define TIM_IT_CC1   ((uint16_t)0x0002)
 
+#define TIM_IT_CC2   ((uint16_t)0x0004)
 
+#define TIM_IT_CC3   ((uint16_t)0x0008)
 
+#define TIM_IT_CC4   ((uint16_t)0x0010)
 
+#define TIM_IT_COM   ((uint16_t)0x0020)
 
+#define TIM_IT_Trigger   ((uint16_t)0x0040)
 
+#define TIM_IT_Break   ((uint16_t)0x0080)
 
+#define IS_TIM_IT(IT)   ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
 
#define IS_TIM_GET_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_TIM_GET_IT( IT)
+
+Value:
(((IT) == TIM_IT_Update) || \
+
((IT) == TIM_IT_CC1) || \
+
((IT) == TIM_IT_CC2) || \
+
((IT) == TIM_IT_CC3) || \
+
((IT) == TIM_IT_CC4) || \
+
((IT) == TIM_IT_COM) || \
+
((IT) == TIM_IT_Trigger) || \
+
((IT) == TIM_IT_Break))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___t_i_m__interrupt__sources.map b/group___t_i_m__interrupt__sources.map new file mode 100644 index 0000000..53c8ac4 --- /dev/null +++ b/group___t_i_m__interrupt__sources.map @@ -0,0 +1,3 @@ + + + diff --git a/group___t_i_m__interrupt__sources.md5 b/group___t_i_m__interrupt__sources.md5 new file mode 100644 index 0000000..23c5aef --- /dev/null +++ b/group___t_i_m__interrupt__sources.md5 @@ -0,0 +1 @@ +3bff36fc477e1709a69a28525e81250c \ No newline at end of file diff --git a/group___t_i_m__interrupt__sources.png b/group___t_i_m__interrupt__sources.png new file mode 100644 index 0000000..9b9cc7c Binary files /dev/null and b/group___t_i_m__interrupt__sources.png differ diff --git a/group___t_i_m_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map b/group___t_i_m_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map new file mode 100644 index 0000000..2c438eb --- /dev/null +++ b/group___t_i_m_ga0a9cbcbab32326cbbdaf4c111f59ec20_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git 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discoverpixy +
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+Modules | +Classes | +Macros | +Functions
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+
USART
STM32F4xx_StdPeriph_Driver
+
+
+ +

USART driver modules. +More...

+
+Collaboration diagram for USART:
+
+
+ + +
+
+ + + + + + +

+Modules

 USART_Exported_Constants
 
 USART_Private_Functions
 
+ + + + + + + +

+Classes

struct  USART_InitTypeDef
 USART Init Structure definition. More...
 
struct  USART_ClockInitTypeDef
 USART Clock Init Structure definition. More...
 
+ + + + + + + + + +

+Macros

#define CR1_CLEAR_MASK
 
#define CR2_CLOCK_CLEAR_MASK
 
#define CR3_CLEAR_MASK   ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
 
+#define IT_MASK   ((uint16_t)0x001F)
 
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+Functions

void USART_DeInit (USART_TypeDef *USARTx)
 Deinitializes the USARTx peripheral registers to their default reset values. More...
 
void USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
 Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct . More...
 
void USART_StructInit (USART_InitTypeDef *USART_InitStruct)
 Fills each USART_InitStruct member with its default value. More...
 
void USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
 Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct . More...
 
void USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
 Fills each USART_ClockInitStruct member with its default value. More...
 
void USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the specified USART peripheral. More...
 
void USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
 Sets the system clock prescaler. More...
 
void USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's 8x oversampling mode. More...
 
void USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's one bit sampling method. More...
 
void USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
 Transmits single data through the USARTx peripheral. More...
 
uint16_t USART_ReceiveData (USART_TypeDef *USARTx)
 Returns the most recent received data by the USARTx peripheral. More...
 
void USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
 Sets the address of the USART node. More...
 
void USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
 Selects the USART WakeUp method. More...
 
void USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Determines if the USART is in mute mode or not. More...
 
void USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
 Sets the USART LIN Break detection length. More...
 
void USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's LIN mode. More...
 
void USART_SendBreak (USART_TypeDef *USARTx)
 Transmits break characters. More...
 
void USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Half Duplex communication. More...
 
void USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Smart Card mode. More...
 
void USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables NACK transmission. More...
 
void USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
 Sets the specified USART guard time. More...
 
void USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
 Configures the USART's IrDA interface. More...
 
void USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's IrDA interface. More...
 
void USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
 Enables or disables the USART's DMA interface. More...
 
void USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
 Enables or disables the specified USART interrupts. More...
 
FlagStatus USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Checks whether the specified USART flag is set or not. More...
 
void USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Clears the USARTx's pending flags. More...
 
ITStatus USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
 Checks whether the specified USART interrupt has occurred or not. More...
 
void USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
 Clears the USARTx's interrupt pending bits. More...
 
+

Detailed Description

+

USART driver modules.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CR1_CLEAR_MASK
+
+Value:
((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
+
USART_CR1_PS | USART_CR1_TE | \
+
USART_CR1_RE))
+
USART_CR1_PCE
#define USART_CR1_PCE
Definition: stm32f4xx.h:8564
+
USART_CR1_TE
#define USART_CR1_TE
Definition: stm32f4xx.h:8557
+
USART_CR1_M
#define USART_CR1_M
Definition: stm32f4xx.h:8566
+
USART_CR1_PS
#define USART_CR1_PS
Definition: stm32f4xx.h:8563
+
USART_CR1_RE
#define USART_CR1_RE
Definition: stm32f4xx.h:8556
+

< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF))

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+ + + + +
#define CR2_CLOCK_CLEAR_MASK
+
+Value:
((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+
USART_CR2_CPHA | USART_CR2_LBCL))
+
USART_CR2_CPHA
#define USART_CR2_CPHA
Definition: stm32f4xx.h:8575
+
USART_CR2_CLKEN
#define USART_CR2_CLKEN
Definition: stm32f4xx.h:8577
+
USART_CR2_CPOL
#define USART_CR2_CPOL
Definition: stm32f4xx.h:8576
+
USART_CR2_LBCL
#define USART_CR2_LBCL
Definition: stm32f4xx.h:8574
+

USART CR3 register clear Mask ((~(uint16_t)0xFCFF))

+ +
+
+ +
+
+ + + + +
#define CR3_CLEAR_MASK   ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+

USART Interrupts mask

+ +
+
+

Function Documentation

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void USART_ClearFlag (USART_TypeDef * USARTx,
uint16_t USART_FLAG 
)
+
+ +

Clears the USARTx's pending flags.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
    • +
  • USART_FLAG_LBD: LIN Break detection flag.
    • +
  • USART_FLAG_TC: Transmission Complete flag.
    • +
  • USART_FLAG_RXNE: Receive data register not empty flag.
    • +
+
+
+
+
Note
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
+
+RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
+
+TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
+
+TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
+
Return values
+ + +
None
+
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void USART_ClearITPendingBit (USART_TypeDef * USARTx,
uint16_t USART_IT 
)
+
+ +

Clears the USARTx's interrupt pending bits.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt.
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt.
    • +
+
+
+
+
Note
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
+
+RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
+
+TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
+
+TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
+
Return values
+ + +
None
+
+
+ +
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void USART_ClockInit (USART_TypeDef * USARTx,
USART_ClockInitTypeDef * USART_ClockInitStruct 
)
+
+ +

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART peripheral.
USART_ClockInitStructpointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
+
+
+
Note
The Smart Card and Synchronous modes are not available for UART4 and UART5.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_ClockStructInit (USART_ClockInitTypeDef * USART_ClockInitStruct)
+
+ +

Fills each USART_ClockInitStruct member with its default value.

+
Parameters
+ + +
USART_ClockInitStructpointer to a USART_ClockInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
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void USART_Cmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified USART peripheral.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
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void USART_DeInit (USART_TypeDef * USARTx)
+
+ +

Deinitializes the USARTx peripheral registers to their default reset values.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
None
+
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void USART_DMACmd (USART_TypeDef * USARTx,
uint16_t USART_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's DMA interface.

+
Parameters
+ + + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_DMAReqspecifies the DMA request. This parameter can be any combination of the following values:
    +
  • USART_DMAReq_Tx: USART DMA transmit request
    • +
  • USART_DMAReq_Rx: USART DMA receive request
    • +
+
NewStatenew state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
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FlagStatus USART_GetFlagStatus (USART_TypeDef * USARTx,
uint16_t USART_FLAG 
)
+
+ +

Checks whether the specified USART flag is set or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
    • +
  • USART_FLAG_LBD: LIN Break detection flag
    • +
  • USART_FLAG_TXE: Transmit data register empty flag
    • +
  • USART_FLAG_TC: Transmission Complete flag
    • +
  • USART_FLAG_RXNE: Receive data register not empty flag
    • +
  • USART_FLAG_IDLE: Idle Line detection flag
    • +
  • USART_FLAG_ORE: OverRun Error flag
    • +
  • USART_FLAG_NE: Noise Error flag
    • +
  • USART_FLAG_FE: Framing Error flag
    • +
  • USART_FLAG_PE: Parity Error flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of USART_FLAG (SET or RESET).
+
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ITStatus USART_GetITStatus (USART_TypeDef * USARTx,
uint16_t USART_IT 
)
+
+ +

Checks whether the specified USART interrupt has occurred or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the USART interrupt source to check. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TXE: Transmit Data Register empty interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt
    • +
  • USART_IT_IDLE: Idle line detection interrupt
    • +
  • USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
    • +
  • USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
    • +
  • USART_IT_NE: Noise Error interrupt
    • +
  • USART_IT_FE: Framing Error interrupt
    • +
  • USART_IT_PE: Parity Error interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of USART_IT (SET or RESET).
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void USART_HalfDuplexCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's Half Duplex communication.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART Communication. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
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+ +
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void USART_Init (USART_TypeDef * USARTx,
USART_InitTypeDef * USART_InitStruct 
)
+
+ +

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_InitStructpointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
+
+
+
Return values
+ + +
None
+
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+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_IrDACmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's IrDA interface.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_IrDAConfig (USART_TypeDef * USARTx,
uint16_t USART_IrDAMode 
)
+
+ +

Configures the USART's IrDA interface.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_IrDAModespecifies the IrDA mode. This parameter can be one of the following values:
    +
  • USART_IrDAMode_LowPower
    • +
  • USART_IrDAMode_Normal
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void USART_ITConfig (USART_TypeDef * USARTx,
uint16_t USART_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified USART interrupts.

+
Parameters
+ + + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TXE: Transmit Data Register empty interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt
    • +
  • USART_IT_IDLE: Idle line detection interrupt
    • +
  • USART_IT_PE: Parity Error interrupt
    • +
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
    • +
+
NewStatenew state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_LINBreakDetectLengthConfig (USART_TypeDef * USARTx,
uint16_t USART_LINBreakDetectLength 
)
+
+ +

Sets the USART LIN Break detection length.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_LINBreakDetectLengthspecifies the LIN break detection length. This parameter can be one of the following values:
    +
  • USART_LINBreakDetectLength_10b: 10-bit break detection
    • +
  • USART_LINBreakDetectLength_11b: 11-bit break detection
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_LINCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's LIN mode.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_OneBitMethodCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's one bit sampling method.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_OverSampling8Cmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's 8x oversampling mode.

+
Note
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART 8x oversampling mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
uint16_t USART_ReceiveData (USART_TypeDef * USARTx)
+
+ +

Returns the most recent received data by the USARTx peripheral.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
Thereceived data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_ReceiverWakeUpCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Determines if the USART is in mute mode or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_SendBreak (USART_TypeDef * USARTx)
+
+ +

Transmits break characters.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SendData (USART_TypeDef * USARTx,
uint16_t Data 
)
+
+ +

Transmits single data through the USARTx peripheral.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Datathe data to transmit.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetAddress (USART_TypeDef * USARTx,
uint8_t USART_Address 
)
+
+ +

Sets the address of the USART node.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_AddressIndicates the address of the USART node.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetGuardTime (USART_TypeDef * USARTx,
uint8_t USART_GuardTime 
)
+
+ +

Sets the specified USART guard time.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
USART_GuardTimespecifies the guard time.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetPrescaler (USART_TypeDef * USARTx,
uint8_t USART_Prescaler 
)
+
+ +

Sets the system clock prescaler.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_Prescalerspecifies the prescaler clock.
+
+
+
Note
The function is used for IrDA mode with UART4 and UART5.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SmartCardCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's Smart Card mode.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SmartCardNACKCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables NACK transmission.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
NewStatenew state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_StructInit (USART_InitTypeDef * USART_InitStruct)
+
+ +

Fills each USART_InitStruct member with its default value.

+
Parameters
+ + +
USART_InitStructpointer to a USART_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_WakeUpConfig (USART_TypeDef * USARTx,
uint16_t USART_WakeUp 
)
+
+ +

Selects the USART WakeUp method.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_WakeUpspecifies the USART wakeup method. This parameter can be one of the following values:
    +
  • USART_WakeUp_IdleLine: WakeUp by an idle line detection
    • +
  • USART_WakeUp_AddressMark: WakeUp by an address mark
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t.map b/group___u_s_a_r_t.map new file mode 100644 index 0000000..cc19a45 --- /dev/null +++ b/group___u_s_a_r_t.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___u_s_a_r_t.md5 b/group___u_s_a_r_t.md5 new file mode 100644 index 0000000..b16cf95 --- /dev/null +++ b/group___u_s_a_r_t.md5 @@ -0,0 +1 @@ +c73e1d3430ab90869a13d46d87f87d45 \ No newline at end of file diff --git a/group___u_s_a_r_t.png b/group___u_s_a_r_t.png new file mode 100644 index 0000000..d971298 Binary files /dev/null and b/group___u_s_a_r_t.png differ diff --git a/group___u_s_a_r_t___clock.html b/group___u_s_a_r_t___clock.html new file mode 100644 index 0000000..d2cfbee --- /dev/null +++ b/group___u_s_a_r_t___clock.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_Clock + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Clock
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Clock:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_Clock_Disable   ((uint16_t)0x0000)
 
+#define USART_Clock_Enable   ((uint16_t)0x0800)
 
#define IS_USART_CLOCK(CLOCK)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_CLOCK( CLOCK)
+
+Value:
(((CLOCK) == USART_Clock_Disable) || \
+
((CLOCK) == USART_Clock_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___clock.map b/group___u_s_a_r_t___clock.map new file mode 100644 index 0000000..b5b889b --- /dev/null +++ b/group___u_s_a_r_t___clock.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___clock.md5 b/group___u_s_a_r_t___clock.md5 new file mode 100644 index 0000000..d8b0ce6 --- /dev/null +++ b/group___u_s_a_r_t___clock.md5 @@ -0,0 +1 @@ +6e86eeb32a94fa458a093c0aaaf7e598 \ No newline at end of file diff --git a/group___u_s_a_r_t___clock.png b/group___u_s_a_r_t___clock.png new file mode 100644 index 0000000..7d1f001 Binary files /dev/null and b/group___u_s_a_r_t___clock.png differ diff --git a/group___u_s_a_r_t___clock___phase.html b/group___u_s_a_r_t___clock___phase.html new file mode 100644 index 0000000..997a715 --- /dev/null +++ b/group___u_s_a_r_t___clock___phase.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USART_Clock_Phase + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Clock_Phase
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Clock_Phase:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_CPHA_1Edge   ((uint16_t)0x0000)
 
+#define USART_CPHA_2Edge   ((uint16_t)0x0200)
 
+#define IS_USART_CPHA(CPHA)   (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___clock___phase.map b/group___u_s_a_r_t___clock___phase.map new file mode 100644 index 0000000..ab2c32e --- /dev/null +++ b/group___u_s_a_r_t___clock___phase.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___clock___phase.md5 b/group___u_s_a_r_t___clock___phase.md5 new file mode 100644 index 0000000..9b3e2dd --- /dev/null +++ b/group___u_s_a_r_t___clock___phase.md5 @@ -0,0 +1 @@ +18b5b5eb76f6fb5b5314643f5afb02a1 \ No newline at end of file diff --git a/group___u_s_a_r_t___clock___phase.png b/group___u_s_a_r_t___clock___phase.png new file mode 100644 index 0000000..0157051 Binary files /dev/null and b/group___u_s_a_r_t___clock___phase.png differ diff --git a/group___u_s_a_r_t___clock___polarity.html b/group___u_s_a_r_t___clock___polarity.html new file mode 100644 index 0000000..e9b9afd --- /dev/null +++ b/group___u_s_a_r_t___clock___polarity.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USART_Clock_Polarity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Clock_Polarity
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Clock_Polarity:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_CPOL_Low   ((uint16_t)0x0000)
 
+#define USART_CPOL_High   ((uint16_t)0x0400)
 
+#define IS_USART_CPOL(CPOL)   (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___clock___polarity.map b/group___u_s_a_r_t___clock___polarity.map new file mode 100644 index 0000000..0b03c08 --- /dev/null +++ b/group___u_s_a_r_t___clock___polarity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___clock___polarity.md5 b/group___u_s_a_r_t___clock___polarity.md5 new file mode 100644 index 0000000..123fd1c --- /dev/null +++ b/group___u_s_a_r_t___clock___polarity.md5 @@ -0,0 +1 @@ +14eb2436db6c3b91e53d588fa299294a \ No newline at end of file diff --git a/group___u_s_a_r_t___clock___polarity.png b/group___u_s_a_r_t___clock___polarity.png new file mode 100644 index 0000000..93da3fb Binary files /dev/null and b/group___u_s_a_r_t___clock___polarity.png differ diff --git a/group___u_s_a_r_t___d_m_a___requests.html b/group___u_s_a_r_t___d_m_a___requests.html new file mode 100644 index 0000000..9f96937 --- /dev/null +++ b/group___u_s_a_r_t___d_m_a___requests.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USART_DMA_Requests + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_DMA_Requests
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_DMA_Requests:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_DMAReq_Tx   ((uint16_t)0x0080)
 
+#define USART_DMAReq_Rx   ((uint16_t)0x0040)
 
+#define IS_USART_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___d_m_a___requests.map b/group___u_s_a_r_t___d_m_a___requests.map new file mode 100644 index 0000000..c84868a --- /dev/null +++ b/group___u_s_a_r_t___d_m_a___requests.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___d_m_a___requests.md5 b/group___u_s_a_r_t___d_m_a___requests.md5 new file mode 100644 index 0000000..d67f61d --- /dev/null +++ b/group___u_s_a_r_t___d_m_a___requests.md5 @@ -0,0 +1 @@ +fe83f452a3c01a55eb6c7789d94b73b7 \ No newline at end of file diff --git a/group___u_s_a_r_t___d_m_a___requests.png b/group___u_s_a_r_t___d_m_a___requests.png new file mode 100644 index 0000000..75f0121 Binary files /dev/null and b/group___u_s_a_r_t___d_m_a___requests.png differ diff --git a/group___u_s_a_r_t___exported___constants.html b/group___u_s_a_r_t___exported___constants.html new file mode 100644 index 0000000..661bbda --- /dev/null +++ b/group___u_s_a_r_t___exported___constants.html @@ -0,0 +1,189 @@ + + + + + + +discoverpixy: USART_Exported_Constants + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules | +Macros
+
+
USART_Exported_Constants
STM32F4xx_StdPeriph_Driver » USART
+
+
+
+Collaboration diagram for USART_Exported_Constants:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USART_Word_Length
 
 USART_Stop_Bits
 
 USART_Parity
 
 USART_Mode
 
 USART_Hardware_Flow_Control
 
 USART_Clock
 
 USART_Clock_Polarity
 
 USART_Clock_Phase
 
 USART_Last_Bit
 
 USART_Interrupt_definition
 
 USART_DMA_Requests
 
 USART_WakeUp_methods
 
 USART_LIN_Break_Detection_Length
 
 USART_IrDA_Low_Power
 
 USART_Flags
 
+ + + + + +

+Macros

#define IS_USART_ALL_PERIPH(PERIPH)
 
#define IS_USART_1236_PERIPH(PERIPH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_1236_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == USART1) || \
+
((PERIPH) == USART2) || \
+
((PERIPH) == USART3) || \
+
((PERIPH) == USART6))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_USART_ALL_PERIPH( PERIPH)
+
+Value:
(((PERIPH) == USART1) || \
+
((PERIPH) == USART2) || \
+
((PERIPH) == USART3) || \
+
((PERIPH) == UART4) || \
+
((PERIPH) == UART5) || \
+
((PERIPH) == USART6) || \
+
((PERIPH) == UART7) || \
+
((PERIPH) == UART8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___exported___constants.map b/group___u_s_a_r_t___exported___constants.map new file mode 100644 index 0000000..6971be9 --- /dev/null +++ b/group___u_s_a_r_t___exported___constants.map @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/group___u_s_a_r_t___exported___constants.md5 b/group___u_s_a_r_t___exported___constants.md5 new file mode 100644 index 0000000..a94bae2 --- /dev/null +++ b/group___u_s_a_r_t___exported___constants.md5 @@ -0,0 +1 @@ +f5f76fe6d0412055ed64d219626c8549 \ No newline at end of file diff --git a/group___u_s_a_r_t___exported___constants.png b/group___u_s_a_r_t___exported___constants.png new file mode 100644 index 0000000..5191929 Binary files /dev/null and b/group___u_s_a_r_t___exported___constants.png differ diff --git a/group___u_s_a_r_t___flags.html b/group___u_s_a_r_t___flags.html new file mode 100644 index 0000000..73ee59d --- /dev/null +++ b/group___u_s_a_r_t___flags.html @@ -0,0 +1,172 @@ + + + + + + +discoverpixy: USART_Flags + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Flags
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Flags:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USART_FLAG_CTS   ((uint16_t)0x0200)
 
+#define USART_FLAG_LBD   ((uint16_t)0x0100)
 
+#define USART_FLAG_TXE   ((uint16_t)0x0080)
 
+#define USART_FLAG_TC   ((uint16_t)0x0040)
 
+#define USART_FLAG_RXNE   ((uint16_t)0x0020)
 
+#define USART_FLAG_IDLE   ((uint16_t)0x0010)
 
+#define USART_FLAG_ORE   ((uint16_t)0x0008)
 
+#define USART_FLAG_NE   ((uint16_t)0x0004)
 
+#define USART_FLAG_FE   ((uint16_t)0x0002)
 
+#define USART_FLAG_PE   ((uint16_t)0x0001)
 
#define IS_USART_FLAG(FLAG)
 
+#define IS_USART_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
+#define IS_USART_BAUDRATE(BAUDRATE)   (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
 
+#define IS_USART_ADDRESS(ADDRESS)   ((ADDRESS) <= 0xF)
 
+#define IS_USART_DATA(DATA)   ((DATA) <= 0x1FF)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_FLAG( FLAG)
+
+Value:
(((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___flags.map b/group___u_s_a_r_t___flags.map new file mode 100644 index 0000000..cb03570 --- /dev/null +++ b/group___u_s_a_r_t___flags.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___flags.md5 b/group___u_s_a_r_t___flags.md5 new file mode 100644 index 0000000..a52a527 --- /dev/null +++ b/group___u_s_a_r_t___flags.md5 @@ -0,0 +1 @@ +db1e535b1c03827308c61d41c9f4870a \ No newline at end of file diff --git a/group___u_s_a_r_t___flags.png b/group___u_s_a_r_t___flags.png new file mode 100644 index 0000000..9df175d Binary files /dev/null and b/group___u_s_a_r_t___flags.png differ diff --git a/group___u_s_a_r_t___group1.html b/group___u_s_a_r_t___group1.html new file mode 100644 index 0000000..be47bbd --- /dev/null +++ b/group___u_s_a_r_t___group1.html @@ -0,0 +1,535 @@ + + + + + + +discoverpixy: Initialization and Configuration functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Initialization and Configuration functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Initialization and Configuration functions. +More...

+
+Collaboration diagram for Initialization and Configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USART_DeInit (USART_TypeDef *USARTx)
 Deinitializes the USARTx peripheral registers to their default reset values. More...
 
void USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
 Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct . More...
 
void USART_StructInit (USART_InitTypeDef *USART_InitStruct)
 Fills each USART_InitStruct member with its default value. More...
 
void USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
 Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct . More...
 
void USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
 Fills each USART_ClockInitStruct member with its default value. More...
 
void USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the specified USART peripheral. More...
 
void USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
 Sets the system clock prescaler. More...
 
void USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's 8x oversampling mode. More...
 
void USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's one bit sampling method. More...
 
+

Detailed Description

+

Initialization and Configuration functions.

+
 ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to initialize the USART 
+    in asynchronous and in synchronous modes.
+      (+) For the asynchronous mode only these parameters can be configured: 
+        (++) Baud Rate
+        (++) Word Length 
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             the possible USART frame formats are as listed in the following table:
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+
+    [..]
+    The USART_Init() function follows the USART  asynchronous configuration 
+    procedure (details for the procedure are available in reference manual (RM0090)).
+
+     (+) For the synchronous mode in addition to the asynchronous mode parameters these 
+         parameters should be also configured:
+        (++) USART Clock Enabled
+        (++) USART polarity
+        (++) USART phase
+        (++) USART LastBit
+  
+    [..]
+    These parameters can be configured using the USART_ClockInit() function.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_ClockInit (USART_TypeDef * USARTx,
USART_ClockInitTypeDef * USART_ClockInitStruct 
)
+
+ +

Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct .

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART peripheral.
USART_ClockInitStructpointer to a USART_ClockInitTypeDef structure that contains the configuration information for the specified USART peripheral.
+
+
+
Note
The Smart Card and Synchronous modes are not available for UART4 and UART5.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_ClockStructInit (USART_ClockInitTypeDef * USART_ClockInitStruct)
+
+ +

Fills each USART_ClockInitStruct member with its default value.

+
Parameters
+ + +
USART_ClockInitStructpointer to a USART_ClockInitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_Cmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified USART peripheral.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USARTx peripheral. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_DeInit (USART_TypeDef * USARTx)
+
+ +

Deinitializes the USARTx peripheral registers to their default reset values.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_Init (USART_TypeDef * USARTx,
USART_InitTypeDef * USART_InitStruct 
)
+
+ +

Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct .

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_InitStructpointer to a USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_OneBitMethodCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's one bit sampling method.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART one bit sampling method. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_OverSampling8Cmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's 8x oversampling mode.

+
Note
This function has to be called before calling USART_Init() function in order to have correct baudrate Divider value.
+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART 8x oversampling mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetPrescaler (USART_TypeDef * USARTx,
uint8_t USART_Prescaler 
)
+
+ +

Sets the system clock prescaler.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_Prescalerspecifies the prescaler clock.
+
+
+
Note
The function is used for IrDA mode with UART4 and UART5.
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_StructInit (USART_InitTypeDef * USART_InitStruct)
+
+ +

Fills each USART_InitStruct member with its default value.

+
Parameters
+ + +
USART_InitStructpointer to a USART_InitTypeDef structure which will be initialized.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group1.map b/group___u_s_a_r_t___group1.map new file mode 100644 index 0000000..439022f --- /dev/null +++ b/group___u_s_a_r_t___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group1.md5 b/group___u_s_a_r_t___group1.md5 new file mode 100644 index 0000000..3a1542a --- /dev/null +++ b/group___u_s_a_r_t___group1.md5 @@ -0,0 +1 @@ +90bbb6284e0abbda50d0bcc7d672d9c3 \ No newline at end of file diff --git a/group___u_s_a_r_t___group1.png b/group___u_s_a_r_t___group1.png new file mode 100644 index 0000000..90c4835 Binary files /dev/null and b/group___u_s_a_r_t___group1.png differ diff --git a/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.map b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.map new file mode 100644 index 0000000..b9432a4 --- /dev/null +++ b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.md5 b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.md5 new file mode 100644 index 0000000..fd7b637 --- /dev/null +++ b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.md5 @@ -0,0 +1 @@ +8ec2202fcd93175899d7e69a1bc21ae6 \ No newline at end of file diff --git a/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.png b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.png new file mode 100644 index 0000000..2fda48c Binary files /dev/null and b/group___u_s_a_r_t___group1_ga2f8e1ce72da21b6539d8e1f299ec3b0d_cgraph.png differ diff --git a/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.map b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.map new file mode 100644 index 0000000..7c39bf2 --- /dev/null +++ b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.md5 b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.md5 new file mode 100644 index 0000000..c2699ba --- /dev/null +++ b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.md5 @@ -0,0 +1 @@ +0b4843922de2854273dc6bcafd84d1e8 \ No newline at end of file diff --git a/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.png b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.png new file mode 100644 index 0000000..0116ef4 Binary files /dev/null and b/group___u_s_a_r_t___group1_ga98da340ea0324002ba1b4263e91ab2ff_cgraph.png differ diff --git a/group___u_s_a_r_t___group2.html b/group___u_s_a_r_t___group2.html new file mode 100644 index 0000000..038c79d --- /dev/null +++ b/group___u_s_a_r_t___group2.html @@ -0,0 +1,206 @@ + + + + + + +discoverpixy: Data transfers functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Data transfers functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Data transfers functions. +More...

+
+Collaboration diagram for Data transfers functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
 Transmits single data through the USARTx peripheral. More...
 
uint16_t USART_ReceiveData (USART_TypeDef *USARTx)
 Returns the most recent received data by the USARTx peripheral. More...
 
+

Detailed Description

+

Data transfers functions.

+
 ===============================================================================
+                      ##### Data transfers functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART data 
+    transfers.
+    [..]
+    During an USART reception, data shifts in least significant bit first through 
+    the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) 
+    between the internal bus and the received shift register.
+    [..]
+    When a transmission is taking place, a write instruction to the USART_DR register 
+    stores the data in the TDR register and which is copied in the shift register 
+    at the end of the current transmission.
+    [..]
+    The read access of the USART_DR register can be done using the USART_ReceiveData()
+    function and returns the RDR buffered value. Whereas a write access to the USART_DR 
+    can be done using USART_SendData() function and stores the written data into 
+    TDR buffer.

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t USART_ReceiveData (USART_TypeDef * USARTx)
+
+ +

Returns the most recent received data by the USARTx peripheral.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
Thereceived data.
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SendData (USART_TypeDef * USARTx,
uint16_t Data 
)
+
+ +

Transmits single data through the USARTx peripheral.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
Datathe data to transmit.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group2.map b/group___u_s_a_r_t___group2.map new file mode 100644 index 0000000..50966e7 --- /dev/null +++ b/group___u_s_a_r_t___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group2.md5 b/group___u_s_a_r_t___group2.md5 new file mode 100644 index 0000000..8e1af51 --- /dev/null +++ b/group___u_s_a_r_t___group2.md5 @@ -0,0 +1 @@ +dad7e48c582d9553b163be8b624c60ba \ No newline at end of file diff --git a/group___u_s_a_r_t___group2.png b/group___u_s_a_r_t___group2.png new file mode 100644 index 0000000..f8fc208 Binary files /dev/null and b/group___u_s_a_r_t___group2.png differ diff --git a/group___u_s_a_r_t___group3.html b/group___u_s_a_r_t___group3.html new file mode 100644 index 0000000..5a33a70 --- /dev/null +++ b/group___u_s_a_r_t___group3.html @@ -0,0 +1,269 @@ + + + + + + +discoverpixy: MultiProcessor Communication functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
MultiProcessor Communication functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Multi-Processor Communication functions. +More...

+
+Collaboration diagram for MultiProcessor Communication functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
 Sets the address of the USART node. More...
 
void USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Determines if the USART is in mute mode or not. More...
 
void USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
 Selects the USART WakeUp method. More...
 
+

Detailed Description

+

Multi-Processor Communication functions.

+
 ===============================================================================
+              ##### Multi-Processor Communication functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART 
+    multiprocessor communication.
+    [..]
+    For instance one of the USARTs can be the master, its TX output is connected 
+    to the RX input of the other USART. The others are slaves, their respective 
+    TX outputs are logically ANDed together and connected to the RX input of the 
+    master.
+    [..]
+    USART multiprocessor communication is possible through the following procedure:
+      (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode 
+          transmitter or Mode receiver and hardware flow control values using 
+          the USART_Init() function.
+      (#) Configures the USART address using the USART_SetAddress() function.
+      (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
+          using USART_WakeUpConfig() function only for the slaves.
+      (#) Enable the USART using the USART_Cmd() function.
+      (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
+    [..]
+    The USART Slave exit from mute mode when receive the wake up condition.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_ReceiverWakeUpCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Determines if the USART is in mute mode or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART mute mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetAddress (USART_TypeDef * USARTx,
uint8_t USART_Address 
)
+
+ +

Sets the address of the USART node.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_AddressIndicates the address of the USART node.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_WakeUpConfig (USART_TypeDef * USARTx,
uint16_t USART_WakeUp 
)
+
+ +

Selects the USART WakeUp method.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_WakeUpspecifies the USART wakeup method. This parameter can be one of the following values:
    +
  • USART_WakeUp_IdleLine: WakeUp by an idle line detection
    • +
  • USART_WakeUp_AddressMark: WakeUp by an address mark
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group3.map b/group___u_s_a_r_t___group3.map new file mode 100644 index 0000000..efc2987 --- /dev/null +++ b/group___u_s_a_r_t___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group3.md5 b/group___u_s_a_r_t___group3.md5 new file mode 100644 index 0000000..4dec308 --- /dev/null +++ b/group___u_s_a_r_t___group3.md5 @@ -0,0 +1 @@ +00e6552bb73ea10109c413026b8c5839 \ No newline at end of file diff --git a/group___u_s_a_r_t___group3.png b/group___u_s_a_r_t___group3.png new file mode 100644 index 0000000..0897e7b Binary files /dev/null and b/group___u_s_a_r_t___group3.png differ diff --git a/group___u_s_a_r_t___group4.html b/group___u_s_a_r_t___group4.html new file mode 100644 index 0000000..0bc2f32 --- /dev/null +++ b/group___u_s_a_r_t___group4.html @@ -0,0 +1,271 @@ + + + + + + +discoverpixy: LIN mode functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
LIN mode functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

LIN mode functions. +More...

+
+Collaboration diagram for LIN mode functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
 Sets the USART LIN Break detection length. More...
 
void USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's LIN mode. More...
 
void USART_SendBreak (USART_TypeDef *USARTx)
 Transmits break characters. More...
 
+

Detailed Description

+

LIN mode functions.

+
 ===============================================================================
+                        ##### LIN mode functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART LIN 
+    Mode communication.
+    [..]
+    In LIN mode, 8-bit data format with 1 stop bit is required in accordance with 
+    the LIN standard.
+    [..]
+    Only this LIN Feature is supported by the USART IP:
+      (+) LIN Master Synchronous Break send capability and LIN slave break detection
+          capability :  13-bit break generation and 10/11 bit break detection
+
+    [..]
+    USART LIN Master transmitter communication is possible through the following 
+    procedure:
+      (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+        Mode transmitter or Mode receiver and hardware flow control values using 
+        the USART_Init() function.
+      (#) Enable the USART using the USART_Cmd() function.
+      (#) Enable the LIN mode using the USART_LINCmd() function.
+      (#) Send the break character using USART_SendBreak() function.
+    [..]
+    USART LIN Master receiver communication is possible through the following procedure:
+      (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+          Mode transmitter or Mode receiver and hardware flow control values using 
+          the USART_Init() function.
+      (#) Enable the USART using the USART_Cmd() function.
+      (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig()
+          function.
+      (#) Enable the LIN mode using the USART_LINCmd() function.
+
+      -@- In LIN mode, the following bits must be kept cleared:
+       (+@) CLKEN in the USART_CR2 register,
+       (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_LINBreakDetectLengthConfig (USART_TypeDef * USARTx,
uint16_t USART_LINBreakDetectLength 
)
+
+ +

Sets the USART LIN Break detection length.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_LINBreakDetectLengthspecifies the LIN break detection length. This parameter can be one of the following values:
    +
  • USART_LINBreakDetectLength_10b: 10-bit break detection
    • +
  • USART_LINBreakDetectLength_11b: 11-bit break detection
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_LINCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's LIN mode.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART LIN mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USART_SendBreak (USART_TypeDef * USARTx)
+
+ +

Transmits break characters.

+
Parameters
+ + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group4.map b/group___u_s_a_r_t___group4.map new file mode 100644 index 0000000..54e7dcc --- /dev/null +++ b/group___u_s_a_r_t___group4.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group4.md5 b/group___u_s_a_r_t___group4.md5 new file mode 100644 index 0000000..cc2320b --- /dev/null +++ b/group___u_s_a_r_t___group4.md5 @@ -0,0 +1 @@ +45d474d595783546d0c942ec5d818cbd \ No newline at end of file diff --git a/group___u_s_a_r_t___group4.png b/group___u_s_a_r_t___group4.png new file mode 100644 index 0000000..2e0fb08 Binary files /dev/null and b/group___u_s_a_r_t___group4.png differ diff --git a/group___u_s_a_r_t___group5.html b/group___u_s_a_r_t___group5.html new file mode 100644 index 0000000..e9d11be --- /dev/null +++ b/group___u_s_a_r_t___group5.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: Halfduplex mode function + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Halfduplex mode function
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Half-duplex mode function. +More...

+
+Collaboration diagram for Halfduplex mode function:
+
+
+ + +
+
+ + + + + +

+Functions

void USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Half Duplex communication. More...
 
+

Detailed Description

+

Half-duplex mode function.

+
 ===============================================================================
+                    ##### Half-duplex mode function #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART 
+    Half-duplex communication.
+    [..]
+    The USART can be configured to follow a single-wire half-duplex protocol where 
+    the TX and RX lines are internally connected.
+    [..]
+    USART Half duplex communication is possible through the following procedure:
+      (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+          or Mode receiver and hardware flow control values using the USART_Init()
+          function.
+      (#) Configures the USART address using the USART_SetAddress() function.
+      (#) Enable the USART using the USART_Cmd() function.
+      (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
+
+
+    -@- The RX pin is no longer used
+    -@- In Half-duplex mode the following bits must be kept cleared:
+      (+@) LINEN and CLKEN bits in the USART_CR2 register.
+      (+@) SCEN and IREN bits in the USART_CR3 register.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_HalfDuplexCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's Half Duplex communication.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the USART Communication. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group5.map b/group___u_s_a_r_t___group5.map new file mode 100644 index 0000000..c9d8d37 --- /dev/null +++ b/group___u_s_a_r_t___group5.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group5.md5 b/group___u_s_a_r_t___group5.md5 new file mode 100644 index 0000000..858bb8f --- /dev/null +++ b/group___u_s_a_r_t___group5.md5 @@ -0,0 +1 @@ +0f1fbf1f5f39eacd19a9cabfbf66a7b4 \ No newline at end of file diff --git a/group___u_s_a_r_t___group5.png b/group___u_s_a_r_t___group5.png new file mode 100644 index 0000000..636c221 Binary files /dev/null and b/group___u_s_a_r_t___group5.png differ diff --git a/group___u_s_a_r_t___group6.html b/group___u_s_a_r_t___group6.html new file mode 100644 index 0000000..5690b54 --- /dev/null +++ b/group___u_s_a_r_t___group6.html @@ -0,0 +1,287 @@ + + + + + + +discoverpixy: Smartcard mode functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Smartcard mode functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Smartcard mode functions. +More...

+
+Collaboration diagram for Smartcard mode functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Functions

void USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
 Sets the specified USART guard time. More...
 
void USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Smart Card mode. More...
 
void USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables NACK transmission. More...
 
+

Detailed Description

+

Smartcard mode functions.

+
 ===============================================================================
+                              ##### Smartcard mode functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART 
+    Smartcard communication.
+    [..]
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard.
+    [..]
+    The USART can provide a clock to the smartcard through the SCLK output.
+    In smartcard mode, SCLK is not associated to the communication but is simply derived 
+    from the internal peripheral input clock through a 5-bit prescaler.
+    [..]
+    Smartcard communication is possible through the following procedure:
+      (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
+      (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
+      (#) Program the USART clock using the USART_ClockInit() function as following:
+        (++) USART Clock enabled
+        (++) USART CPOL Low
+        (++) USART CPHA on first edge
+        (++) USART Last Bit Clock Enabled
+      (#) Program the Smartcard interface using the USART_Init() function as following:
+        (++) Word Length = 9 Bits
+        (++) 1.5 Stop Bit
+        (++) Even parity
+        (++) BaudRate = 12096 baud
+        (++) Hardware flow control disabled (RTS and CTS signals)
+        (++) Tx and Rx enabled
+      (#) POptionally you can enable the parity error interrupt using the USART_ITConfig()
+          function
+      (#) PEnable the USART using the USART_Cmd() function.
+      (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+      (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function.
+
+    Please refer to the ISO 7816-3 specification for more details.
+
+      -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended 
+          to use 1.5 stop bits for both transmitting and receiving to avoid switching 
+          between the two configurations.
+      -@- In smartcard mode, the following bits must be kept cleared:
+        (+@) LINEN bit in the USART_CR2 register.
+        (+@) HDSEL and IREN bits in the USART_CR3 register.
+      -@- Smartcard mode is available on USART peripherals only (not available on UART4 
+          and UART5 peripherals).

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SetGuardTime (USART_TypeDef * USARTx,
uint8_t USART_GuardTime 
)
+
+ +

Sets the specified USART guard time.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
USART_GuardTimespecifies the guard time.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SmartCardCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's Smart Card mode.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
NewStatenew state of the Smart Card mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_SmartCardNACKCmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables NACK transmission.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3 or 6 to select the USART or UART peripheral.
NewStatenew state of the NACK transmission. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group6.map b/group___u_s_a_r_t___group6.map new file mode 100644 index 0000000..3db9f04 --- /dev/null +++ b/group___u_s_a_r_t___group6.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group6.md5 b/group___u_s_a_r_t___group6.md5 new file mode 100644 index 0000000..398f528 --- /dev/null +++ b/group___u_s_a_r_t___group6.md5 @@ -0,0 +1 @@ +9828e5ea3ee2f2fee06051273131afc6 \ No newline at end of file diff --git a/group___u_s_a_r_t___group6.png b/group___u_s_a_r_t___group6.png new file mode 100644 index 0000000..24d6147 Binary files /dev/null and b/group___u_s_a_r_t___group6.png differ diff --git a/group___u_s_a_r_t___group7.html b/group___u_s_a_r_t___group7.html new file mode 100644 index 0000000..1a7bd7d --- /dev/null +++ b/group___u_s_a_r_t___group7.html @@ -0,0 +1,233 @@ + + + + + + +discoverpixy: IrDA mode functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
IrDA mode functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

IrDA mode functions. +More...

+
+Collaboration diagram for IrDA mode functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

void USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
 Configures the USART's IrDA interface. More...
 
void USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's IrDA interface. More...
 
+

Detailed Description

+

IrDA mode functions.

+
 ===============================================================================
+                        ##### IrDA mode functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the USART 
+    IrDA communication.
+    [..]
+    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+    While receiving data, transmission should be avoided as the data to be transmitted
+    could be corrupted.
+    [..]
+    IrDA communication is possible through the following procedure:
+      (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver 
+          modes and hardware flow control values using the USART_Init() function.
+      (#) Enable the USART using the USART_Cmd() function.
+      (#) Configures the IrDA pulse width by configuring the prescaler using  
+          the USART_SetPrescaler() function.
+      (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
+          using the USART_IrDAConfig() function.
+      (#) Enable the IrDA using the USART_IrDACmd() function.
+
+      -@- A pulse of width less than two and greater than one PSC period(s) may or may
+          not be rejected.
+      -@- The receiver set up time should be managed by software. The IrDA physical layer
+          specification specifies a minimum of 10 ms delay between transmission and 
+          reception (IrDA is a half duplex protocol).
+      -@- In IrDA mode, the following bits must be kept cleared:
+        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        (+@) SCEN and HDSEL bits in the USART_CR3 register.

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_IrDACmd (USART_TypeDef * USARTx,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's IrDA interface.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
NewStatenew state of the IrDA mode. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_IrDAConfig (USART_TypeDef * USARTx,
uint16_t USART_IrDAMode 
)
+
+ +

Configures the USART's IrDA interface.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_IrDAModespecifies the IrDA mode. This parameter can be one of the following values:
    +
  • USART_IrDAMode_LowPower
    • +
  • USART_IrDAMode_Normal
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group7.map b/group___u_s_a_r_t___group7.map new file mode 100644 index 0000000..9cfe097 --- /dev/null +++ b/group___u_s_a_r_t___group7.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group7.md5 b/group___u_s_a_r_t___group7.md5 new file mode 100644 index 0000000..d1366d6 --- /dev/null +++ b/group___u_s_a_r_t___group7.md5 @@ -0,0 +1 @@ +a49ce567a8805d7086350169be09e409 \ No newline at end of file diff --git a/group___u_s_a_r_t___group7.png b/group___u_s_a_r_t___group7.png new file mode 100644 index 0000000..79e8632 Binary files /dev/null and b/group___u_s_a_r_t___group7.png differ diff --git a/group___u_s_a_r_t___group8.html b/group___u_s_a_r_t___group8.html new file mode 100644 index 0000000..6f13e5f --- /dev/null +++ b/group___u_s_a_r_t___group8.html @@ -0,0 +1,168 @@ + + + + + + +discoverpixy: DMA transfers management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
DMA transfers management functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

DMA transfers management functions. +More...

+
+Collaboration diagram for DMA transfers management functions:
+
+
+ + +
+
+ + + + + +

+Functions

void USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
 Enables or disables the USART's DMA interface. More...
 
+

Detailed Description

+

DMA transfers management functions.

+
 ===============================================================================
+              ##### DMA transfers management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void USART_DMACmd (USART_TypeDef * USARTx,
uint16_t USART_DMAReq,
FunctionalState NewState 
)
+
+ +

Enables or disables the USART's DMA interface.

+
Parameters
+ + + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_DMAReqspecifies the DMA request. This parameter can be any combination of the following values:
    +
  • USART_DMAReq_Tx: USART DMA transmit request
    • +
  • USART_DMAReq_Rx: USART DMA receive request
    • +
+
NewStatenew state of the DMA Request sources. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group8.map b/group___u_s_a_r_t___group8.map new file mode 100644 index 0000000..11b2db4 --- /dev/null +++ b/group___u_s_a_r_t___group8.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group8.md5 b/group___u_s_a_r_t___group8.md5 new file mode 100644 index 0000000..2313370 --- /dev/null +++ b/group___u_s_a_r_t___group8.md5 @@ -0,0 +1 @@ +feb4eb62f1fbba48fb1e7ad740c29e93 \ No newline at end of file diff --git a/group___u_s_a_r_t___group8.png b/group___u_s_a_r_t___group8.png new file mode 100644 index 0000000..a2272ea Binary files /dev/null and b/group___u_s_a_r_t___group8.png differ diff --git a/group___u_s_a_r_t___group9.html b/group___u_s_a_r_t___group9.html new file mode 100644 index 0000000..7cf7e48 --- /dev/null +++ b/group___u_s_a_r_t___group9.html @@ -0,0 +1,478 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
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Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » USART » USART_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
 Enables or disables the specified USART interrupts. More...
 
FlagStatus USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Checks whether the specified USART flag is set or not. More...
 
void USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Clears the USARTx's pending flags. More...
 
ITStatus USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
 Checks whether the specified USART interrupt has occurred or not. More...
 
void USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
 Clears the USARTx's interrupt pending bits. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to configure the USART 
+    Interrupts sources, DMA channels requests and check or clear the flags or 
+    pending bits status.
+    The user should identify which mode will be used in his application to manage 
+    the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+    *** Polling Mode ***
+    ====================
+    [..]
+    In Polling Mode, the SPI communication can be managed by 10 flags:
+      (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register
+      (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register
+      (#) USART_FLAG_TC : to indicate the status of the transmit operation
+      (#) USART_FLAG_IDLE : to indicate the status of the Idle Line             
+      (#) USART_FLAG_CTS : to indicate the status of the nCTS input
+      (#) USART_FLAG_LBD : to indicate the status of the LIN break detection
+      (#) USART_FLAG_NE : to indicate if a noise error occur
+      (#) USART_FLAG_FE : to indicate if a frame error occur
+      (#) USART_FLAG_PE : to indicate if a parity error occur
+      (#) USART_FLAG_ORE : to indicate if an Overrun error occur
+    [..]
+    In this Mode it is advised to use the following functions:
+      (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+      (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+
+    *** Interrupt Mode ***
+    ======================
+    [..]
+    In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
+    and 10 pending bits: 
+
+      (#) Pending Bits:
+
+        (##) USART_IT_TXE : to indicate the status of the transmit buffer register
+        (##) USART_IT_RXNE : to indicate the status of the receive buffer register
+        (##) USART_IT_TC : to indicate the status of the transmit operation
+        (##) USART_IT_IDLE : to indicate the status of the Idle Line             
+        (##) USART_IT_CTS : to indicate the status of the nCTS input
+        (##) USART_IT_LBD : to indicate the status of the LIN break detection
+        (##) USART_IT_NE : to indicate if a noise error occur
+        (##) USART_IT_FE : to indicate if a frame error occur
+        (##) USART_IT_PE : to indicate if a parity error occur
+        (##) USART_IT_ORE : to indicate if an Overrun error occur
+
+      (#) Interrupt Source:
+
+        (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty 
+                            interrupt. 
+        (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+                             empty interrupt.
+        (##) USART_IT_TC : specifies the interrupt source for the Transmit complete 
+                           interrupt. 
+        (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.             
+        (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. 
+        (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection
+                            interrupt. 
+        (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. 
+        (##) USART_IT_ERR :  specifies the interrupt source for the errors interrupt.
+
+      -@@- Some parameters are coded in order to use them as interrupt source 
+          or as pending bits.
+    [..]
+    In this Mode it is advised to use the following functions:
+      (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+      (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+      (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+    *** DMA Mode ***
+    ================
+    [..]
+    In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
+      (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+      (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+    [..]
+    In this Mode it is advised to use the following function:
+      (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_ClearFlag (USART_TypeDef * USARTx,
uint16_t USART_FLAG 
)
+
+ +

Clears the USARTx's pending flags.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_FLAGspecifies the flag to clear. This parameter can be any combination of the following values:
    +
  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
    • +
  • USART_FLAG_LBD: LIN Break detection flag.
    • +
  • USART_FLAG_TC: Transmission Complete flag.
    • +
  • USART_FLAG_RXNE: Receive data register not empty flag.
    • +
+
+
+
+
Note
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
+
+RXNE flag can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
+
+TC flag can be also cleared by software sequence: a read operation to USART_SR register (USART_GetFlagStatus()) followed by a write operation to USART_DR register (USART_SendData()).
+
+TXE flag is cleared only by a write to the USART_DR register (USART_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void USART_ClearITPendingBit (USART_TypeDef * USARTx,
uint16_t USART_IT 
)
+
+ +

Clears the USARTx's interrupt pending bits.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the interrupt pending bit to clear. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt.
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt.
    • +
+
+
+
+
Note
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) pending bits are cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a read operation to USART_DR register (USART_ReceiveData()).
+
+RXNE pending bit can be also cleared by a read to the USART_DR register (USART_ReceiveData()).
+
+TC pending bit can be also cleared by software sequence: a read operation to USART_SR register (USART_GetITStatus()) followed by a write operation to USART_DR register (USART_SendData()).
+
+TXE pending bit is cleared only by a write to the USART_DR register (USART_SendData()).
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
FlagStatus USART_GetFlagStatus (USART_TypeDef * USARTx,
uint16_t USART_FLAG 
)
+
+ +

Checks whether the specified USART flag is set or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_FLAGspecifies the flag to check. This parameter can be one of the following values:
    +
  • USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
    • +
  • USART_FLAG_LBD: LIN Break detection flag
    • +
  • USART_FLAG_TXE: Transmit data register empty flag
    • +
  • USART_FLAG_TC: Transmission Complete flag
    • +
  • USART_FLAG_RXNE: Receive data register not empty flag
    • +
  • USART_FLAG_IDLE: Idle Line detection flag
    • +
  • USART_FLAG_ORE: OverRun Error flag
    • +
  • USART_FLAG_NE: Noise Error flag
    • +
  • USART_FLAG_FE: Framing Error flag
    • +
  • USART_FLAG_PE: Parity Error flag
    • +
+
+
+
+
Return values
+ + +
Thenew state of USART_FLAG (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
ITStatus USART_GetITStatus (USART_TypeDef * USARTx,
uint16_t USART_IT 
)
+
+ +

Checks whether the specified USART interrupt has occurred or not.

+
Parameters
+ + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the USART interrupt source to check. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TXE: Transmit Data Register empty interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt
    • +
  • USART_IT_IDLE: Idle line detection interrupt
    • +
  • USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
    • +
  • USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
    • +
  • USART_IT_NE: Noise Error interrupt
    • +
  • USART_IT_FE: Framing Error interrupt
    • +
  • USART_IT_PE: Parity Error interrupt
    • +
+
+
+
+
Return values
+ + +
Thenew state of USART_IT (SET or RESET).
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void USART_ITConfig (USART_TypeDef * USARTx,
uint16_t USART_IT,
FunctionalState NewState 
)
+
+ +

Enables or disables the specified USART interrupts.

+
Parameters
+ + + + +
USARTxwhere x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or UART peripheral.
USART_ITspecifies the USART interrupt sources to be enabled or disabled. This parameter can be one of the following values:
    +
  • USART_IT_CTS: CTS change interrupt
    • +
  • USART_IT_LBD: LIN Break detection interrupt
    • +
  • USART_IT_TXE: Transmit Data Register empty interrupt
    • +
  • USART_IT_TC: Transmission complete interrupt
    • +
  • USART_IT_RXNE: Receive Data register not empty interrupt
    • +
  • USART_IT_IDLE: Idle line detection interrupt
    • +
  • USART_IT_PE: Parity Error interrupt
    • +
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
    • +
+
NewStatenew state of the specified USARTx interrupts. This parameter can be: ENABLE or DISABLE.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___group9.map b/group___u_s_a_r_t___group9.map new file mode 100644 index 0000000..7f26959 --- /dev/null +++ b/group___u_s_a_r_t___group9.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___group9.md5 b/group___u_s_a_r_t___group9.md5 new file mode 100644 index 0000000..5a93ab8 --- /dev/null +++ b/group___u_s_a_r_t___group9.md5 @@ -0,0 +1 @@ +a03a11da855f7e7c16d625d28d2bad29 \ No newline at end of file diff --git a/group___u_s_a_r_t___group9.png b/group___u_s_a_r_t___group9.png new file mode 100644 index 0000000..08b837f Binary files /dev/null and b/group___u_s_a_r_t___group9.png differ diff --git a/group___u_s_a_r_t___hardware___flow___control.html b/group___u_s_a_r_t___hardware___flow___control.html new file mode 100644 index 0000000..2348b73 --- /dev/null +++ b/group___u_s_a_r_t___hardware___flow___control.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: USART_Hardware_Flow_Control + + + + + + + + + + +
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USART_Hardware_Flow_Control
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Hardware_Flow_Control:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define USART_HardwareFlowControl_None   ((uint16_t)0x0000)
 
+#define USART_HardwareFlowControl_RTS   ((uint16_t)0x0100)
 
+#define USART_HardwareFlowControl_CTS   ((uint16_t)0x0200)
 
+#define USART_HardwareFlowControl_RTS_CTS   ((uint16_t)0x0300)
 
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_HARDWARE_FLOW_CONTROL( CONTROL)
+
+Value:
(((CONTROL) == USART_HardwareFlowControl_None) || \
+
((CONTROL) == USART_HardwareFlowControl_RTS) || \
+
((CONTROL) == USART_HardwareFlowControl_CTS) || \
+
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___hardware___flow___control.map b/group___u_s_a_r_t___hardware___flow___control.map new file mode 100644 index 0000000..cf0fcb6 --- /dev/null +++ b/group___u_s_a_r_t___hardware___flow___control.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___hardware___flow___control.md5 b/group___u_s_a_r_t___hardware___flow___control.md5 new file mode 100644 index 0000000..eb11a3d --- /dev/null +++ b/group___u_s_a_r_t___hardware___flow___control.md5 @@ -0,0 +1 @@ +b42d7a9690b77306d48b52ff8f7ff309 \ No newline at end of file diff --git a/group___u_s_a_r_t___hardware___flow___control.png b/group___u_s_a_r_t___hardware___flow___control.png new file mode 100644 index 0000000..733171f Binary files /dev/null and b/group___u_s_a_r_t___hardware___flow___control.png differ diff --git a/group___u_s_a_r_t___interrupt__definition.html b/group___u_s_a_r_t___interrupt__definition.html new file mode 100644 index 0000000..a167a4b --- /dev/null +++ b/group___u_s_a_r_t___interrupt__definition.html @@ -0,0 +1,215 @@ + + + + + + +discoverpixy: USART_Interrupt_definition + + + + + + + + + + +
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USART_Interrupt_definition
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Interrupt_definition:
+
+
+ + +
+
+ + + + +

+Modules

 USART_Legacy
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USART_IT_PE   ((uint16_t)0x0028)
 
+#define USART_IT_TXE   ((uint16_t)0x0727)
 
+#define USART_IT_TC   ((uint16_t)0x0626)
 
+#define USART_IT_RXNE   ((uint16_t)0x0525)
 
+#define USART_IT_ORE_RX   ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
 
+#define USART_IT_IDLE   ((uint16_t)0x0424)
 
+#define USART_IT_LBD   ((uint16_t)0x0846)
 
+#define USART_IT_CTS   ((uint16_t)0x096A)
 
+#define USART_IT_ERR   ((uint16_t)0x0060)
 
+#define USART_IT_ORE_ER   ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
 
+#define USART_IT_NE   ((uint16_t)0x0260)
 
+#define USART_IT_FE   ((uint16_t)0x0160)
 
#define IS_USART_CONFIG_IT(IT)
 
#define IS_USART_GET_IT(IT)
 
#define IS_USART_CLEAR_IT(IT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_CLEAR_IT( IT)
+
+Value:
(((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_USART_CONFIG_IT( IT)
+
+Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+
+
+
+ +
+
+ + + + + + + + +
#define IS_USART_GET_IT( IT)
+
+Value:
(((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+
((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
+
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___interrupt__definition.map b/group___u_s_a_r_t___interrupt__definition.map new file mode 100644 index 0000000..1f7e917 --- /dev/null +++ b/group___u_s_a_r_t___interrupt__definition.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___u_s_a_r_t___interrupt__definition.md5 b/group___u_s_a_r_t___interrupt__definition.md5 new file mode 100644 index 0000000..33c2b52 --- /dev/null +++ b/group___u_s_a_r_t___interrupt__definition.md5 @@ -0,0 +1 @@ +a583f982c0b66a68ea9fd00fca325a63 \ No newline at end of file diff --git a/group___u_s_a_r_t___interrupt__definition.png b/group___u_s_a_r_t___interrupt__definition.png new file mode 100644 index 0000000..c22427f Binary files /dev/null and b/group___u_s_a_r_t___interrupt__definition.png differ diff --git a/group___u_s_a_r_t___ir_d_a___low___power.html b/group___u_s_a_r_t___ir_d_a___low___power.html new file mode 100644 index 0000000..c3d112c --- /dev/null +++ b/group___u_s_a_r_t___ir_d_a___low___power.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_IrDA_Low_Power + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
USART_IrDA_Low_Power
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_IrDA_Low_Power:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_IrDAMode_LowPower   ((uint16_t)0x0004)
 
+#define USART_IrDAMode_Normal   ((uint16_t)0x0000)
 
#define IS_USART_IRDA_MODE(MODE)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_IRDA_MODE( MODE)
+
+Value:
(((MODE) == USART_IrDAMode_LowPower) || \
+
((MODE) == USART_IrDAMode_Normal))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___ir_d_a___low___power.map b/group___u_s_a_r_t___ir_d_a___low___power.map new file mode 100644 index 0000000..dbc8246 --- /dev/null +++ b/group___u_s_a_r_t___ir_d_a___low___power.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___ir_d_a___low___power.md5 b/group___u_s_a_r_t___ir_d_a___low___power.md5 new file mode 100644 index 0000000..affe7cb --- /dev/null +++ b/group___u_s_a_r_t___ir_d_a___low___power.md5 @@ -0,0 +1 @@ +887d4a820b92727e69f19ebd30dfbb82 \ No newline at end of file diff --git a/group___u_s_a_r_t___ir_d_a___low___power.png b/group___u_s_a_r_t___ir_d_a___low___power.png new file mode 100644 index 0000000..0551522 Binary files /dev/null and b/group___u_s_a_r_t___ir_d_a___low___power.png differ diff --git a/group___u_s_a_r_t___l_i_n___break___detection___length.html b/group___u_s_a_r_t___l_i_n___break___detection___length.html new file mode 100644 index 0000000..42bab43 --- /dev/null +++ b/group___u_s_a_r_t___l_i_n___break___detection___length.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_LIN_Break_Detection_Length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_LIN_Break_Detection_Length
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_LIN_Break_Detection_Length:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_LINBreakDetectLength_10b   ((uint16_t)0x0000)
 
+#define USART_LINBreakDetectLength_11b   ((uint16_t)0x0020)
 
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_LIN_BREAK_DETECT_LENGTH( LENGTH)
+
+Value:
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
+
((LENGTH) == USART_LINBreakDetectLength_11b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___l_i_n___break___detection___length.map b/group___u_s_a_r_t___l_i_n___break___detection___length.map new file mode 100644 index 0000000..cceca0a --- /dev/null +++ b/group___u_s_a_r_t___l_i_n___break___detection___length.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___l_i_n___break___detection___length.md5 b/group___u_s_a_r_t___l_i_n___break___detection___length.md5 new file mode 100644 index 0000000..0c6eb27 --- /dev/null +++ b/group___u_s_a_r_t___l_i_n___break___detection___length.md5 @@ -0,0 +1 @@ +b5d6f5828bf2b47de4e4ff4d2a94caa6 \ No newline at end of file diff --git a/group___u_s_a_r_t___l_i_n___break___detection___length.png b/group___u_s_a_r_t___l_i_n___break___detection___length.png new file mode 100644 index 0000000..908f5ca Binary files /dev/null and b/group___u_s_a_r_t___l_i_n___break___detection___length.png differ diff --git a/group___u_s_a_r_t___last___bit.html b/group___u_s_a_r_t___last___bit.html new file mode 100644 index 0000000..1079c37 --- /dev/null +++ b/group___u_s_a_r_t___last___bit.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_Last_Bit + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+Macros
+
+
USART_Last_Bit
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Last_Bit:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_LastBit_Disable   ((uint16_t)0x0000)
 
+#define USART_LastBit_Enable   ((uint16_t)0x0100)
 
#define IS_USART_LASTBIT(LASTBIT)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_LASTBIT( LASTBIT)
+
+Value:
(((LASTBIT) == USART_LastBit_Disable) || \
+
((LASTBIT) == USART_LastBit_Enable))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___last___bit.map b/group___u_s_a_r_t___last___bit.map new file mode 100644 index 0000000..395b75c --- /dev/null +++ b/group___u_s_a_r_t___last___bit.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___last___bit.md5 b/group___u_s_a_r_t___last___bit.md5 new file mode 100644 index 0000000..823dfe4 --- /dev/null +++ b/group___u_s_a_r_t___last___bit.md5 @@ -0,0 +1 @@ +a02bd7016d0a27a8d23f2a4d5b611051 \ No newline at end of file diff --git a/group___u_s_a_r_t___last___bit.png b/group___u_s_a_r_t___last___bit.png new file mode 100644 index 0000000..87fac85 Binary files /dev/null and b/group___u_s_a_r_t___last___bit.png differ diff --git a/group___u_s_a_r_t___legacy.html b/group___u_s_a_r_t___legacy.html new file mode 100644 index 0000000..619ed32 --- /dev/null +++ b/group___u_s_a_r_t___legacy.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USART_Legacy + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Legacy
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants » USART_Interrupt_definition
+
+
+
+Collaboration diagram for USART_Legacy:
+
+
+ + +
+
+ + + + +

+Macros

+#define USART_IT_ORE   USART_IT_ORE_ER
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___legacy.map b/group___u_s_a_r_t___legacy.map new file mode 100644 index 0000000..2323e83 --- /dev/null +++ b/group___u_s_a_r_t___legacy.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___legacy.md5 b/group___u_s_a_r_t___legacy.md5 new file mode 100644 index 0000000..a00499e --- /dev/null +++ b/group___u_s_a_r_t___legacy.md5 @@ -0,0 +1 @@ +8872e14e3a92da4fc0490af7d4dbfd95 \ No newline at end of file diff --git a/group___u_s_a_r_t___legacy.png b/group___u_s_a_r_t___legacy.png new file mode 100644 index 0000000..afafc23 Binary files /dev/null and b/group___u_s_a_r_t___legacy.png differ diff --git a/group___u_s_a_r_t___mode.html b/group___u_s_a_r_t___mode.html new file mode 100644 index 0000000..6431c11 --- /dev/null +++ b/group___u_s_a_r_t___mode.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USART_Mode + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Mode
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Mode:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_Mode_Rx   ((uint16_t)0x0004)
 
+#define USART_Mode_Tx   ((uint16_t)0x0008)
 
+#define IS_USART_MODE(MODE)   ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___mode.map b/group___u_s_a_r_t___mode.map new file mode 100644 index 0000000..bd2733b --- /dev/null +++ b/group___u_s_a_r_t___mode.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___mode.md5 b/group___u_s_a_r_t___mode.md5 new file mode 100644 index 0000000..b66f13f --- /dev/null +++ b/group___u_s_a_r_t___mode.md5 @@ -0,0 +1 @@ +92537b7b8f3c3e0b7e5709bfd737c063 \ No newline at end of file diff --git a/group___u_s_a_r_t___mode.png b/group___u_s_a_r_t___mode.png new file mode 100644 index 0000000..dd8b8c1 Binary files /dev/null and b/group___u_s_a_r_t___mode.png differ diff --git a/group___u_s_a_r_t___parity.html b/group___u_s_a_r_t___parity.html new file mode 100644 index 0000000..6d21998 --- /dev/null +++ b/group___u_s_a_r_t___parity.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: USART_Parity + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Parity
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Parity:
+
+
+ + +
+
+ + + + + + + + + + +

+Macros

+#define USART_Parity_No   ((uint16_t)0x0000)
 
+#define USART_Parity_Even   ((uint16_t)0x0400)
 
+#define USART_Parity_Odd   ((uint16_t)0x0600)
 
#define IS_USART_PARITY(PARITY)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_PARITY( PARITY)
+
+Value:
(((PARITY) == USART_Parity_No) || \
+
((PARITY) == USART_Parity_Even) || \
+
((PARITY) == USART_Parity_Odd))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___parity.map b/group___u_s_a_r_t___parity.map new file mode 100644 index 0000000..fbd6896 --- /dev/null +++ b/group___u_s_a_r_t___parity.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___parity.md5 b/group___u_s_a_r_t___parity.md5 new file mode 100644 index 0000000..b341e51 --- /dev/null +++ b/group___u_s_a_r_t___parity.md5 @@ -0,0 +1 @@ +b09de12697e9a5f2c5e4a6bdd259cd81 \ No newline at end of file diff --git a/group___u_s_a_r_t___parity.png b/group___u_s_a_r_t___parity.png new file mode 100644 index 0000000..2bb8f33 Binary files /dev/null and b/group___u_s_a_r_t___parity.png differ diff --git a/group___u_s_a_r_t___private___functions.html b/group___u_s_a_r_t___private___functions.html new file mode 100644 index 0000000..3e58e05 --- /dev/null +++ b/group___u_s_a_r_t___private___functions.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Modules
+
+
USART_Private_Functions
STM32F4xx_StdPeriph_Driver » USART
+
+
+
+Collaboration diagram for USART_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 Initialization and Configuration functions
 Initialization and Configuration functions.
 
 Data transfers functions
 Data transfers functions.
 
 MultiProcessor Communication functions
 Multi-Processor Communication functions.
 
 LIN mode functions
 LIN mode functions.
 
 Halfduplex mode function
 Half-duplex mode function.
 
 Smartcard mode functions
 Smartcard mode functions.
 
 IrDA mode functions
 IrDA mode functions.
 
 DMA transfers management functions
 DMA transfers management functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___private___functions.map b/group___u_s_a_r_t___private___functions.map new file mode 100644 index 0000000..2634750 --- /dev/null +++ b/group___u_s_a_r_t___private___functions.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group___u_s_a_r_t___private___functions.md5 b/group___u_s_a_r_t___private___functions.md5 new file mode 100644 index 0000000..e40b36c --- /dev/null +++ b/group___u_s_a_r_t___private___functions.md5 @@ -0,0 +1 @@ +34a0461715c3f2f583322d41504a75b3 \ No newline at end of file diff --git a/group___u_s_a_r_t___private___functions.png b/group___u_s_a_r_t___private___functions.png new file mode 100644 index 0000000..ad08c29 Binary files /dev/null and b/group___u_s_a_r_t___private___functions.png differ diff --git a/group___u_s_a_r_t___stop___bits.html b/group___u_s_a_r_t___stop___bits.html new file mode 100644 index 0000000..081d97e --- /dev/null +++ b/group___u_s_a_r_t___stop___bits.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: USART_Stop_Bits + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_Stop_Bits
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Stop_Bits:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define USART_StopBits_1   ((uint16_t)0x0000)
 
+#define USART_StopBits_0_5   ((uint16_t)0x1000)
 
+#define USART_StopBits_2   ((uint16_t)0x2000)
 
+#define USART_StopBits_1_5   ((uint16_t)0x3000)
 
#define IS_USART_STOPBITS(STOPBITS)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_STOPBITS( STOPBITS)
+
+Value:
(((STOPBITS) == USART_StopBits_1) || \
+
((STOPBITS) == USART_StopBits_0_5) || \
+
((STOPBITS) == USART_StopBits_2) || \
+
((STOPBITS) == USART_StopBits_1_5))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___stop___bits.map b/group___u_s_a_r_t___stop___bits.map new file mode 100644 index 0000000..67a16b4 --- /dev/null +++ b/group___u_s_a_r_t___stop___bits.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___stop___bits.md5 b/group___u_s_a_r_t___stop___bits.md5 new file mode 100644 index 0000000..39c8d08 --- /dev/null +++ b/group___u_s_a_r_t___stop___bits.md5 @@ -0,0 +1 @@ +750b56fe9852f338d4728f64b63fa157 \ No newline at end of file diff --git a/group___u_s_a_r_t___stop___bits.png b/group___u_s_a_r_t___stop___bits.png new file mode 100644 index 0000000..d718ae2 Binary files /dev/null and b/group___u_s_a_r_t___stop___bits.png differ diff --git a/group___u_s_a_r_t___wake_up__methods.html b/group___u_s_a_r_t___wake_up__methods.html new file mode 100644 index 0000000..1bb7523 --- /dev/null +++ b/group___u_s_a_r_t___wake_up__methods.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_WakeUp_methods + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
USART_WakeUp_methods
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_WakeUp_methods:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_WakeUp_IdleLine   ((uint16_t)0x0000)
 
+#define USART_WakeUp_AddressMark   ((uint16_t)0x0800)
 
#define IS_USART_WAKEUP(WAKEUP)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_WAKEUP( WAKEUP)
+
+Value:
(((WAKEUP) == USART_WakeUp_IdleLine) || \
+
((WAKEUP) == USART_WakeUp_AddressMark))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_a_r_t___wake_up__methods.map b/group___u_s_a_r_t___wake_up__methods.map new file mode 100644 index 0000000..826e38b --- /dev/null +++ b/group___u_s_a_r_t___wake_up__methods.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_a_r_t___wake_up__methods.md5 b/group___u_s_a_r_t___wake_up__methods.md5 new file mode 100644 index 0000000..6cc1cd2 --- /dev/null +++ b/group___u_s_a_r_t___wake_up__methods.md5 @@ -0,0 +1 @@ +77463a88ca41e981d6e4535d152c25b8 \ No newline at end of file diff --git a/group___u_s_a_r_t___wake_up__methods.png b/group___u_s_a_r_t___wake_up__methods.png new file mode 100644 index 0000000..97dd28e Binary files /dev/null and b/group___u_s_a_r_t___wake_up__methods.png differ diff --git a/group___u_s_a_r_t___word___length.html b/group___u_s_a_r_t___word___length.html new file mode 100644 index 0000000..ed2e07d --- /dev/null +++ b/group___u_s_a_r_t___word___length.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USART_Word_Length + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
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+Macros
+
+
USART_Word_Length
STM32F4xx_StdPeriph_Driver » USART » USART_Exported_Constants
+
+
+
+Collaboration diagram for USART_Word_Length:
+
+
+ + +
+
+ + + + + + + + +

+Macros

+#define USART_WordLength_8b   ((uint16_t)0x0000)
 
+#define USART_WordLength_9b   ((uint16_t)0x1000)
 
#define IS_USART_WORD_LENGTH(LENGTH)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_USART_WORD_LENGTH( LENGTH)
+
+Value:
(((LENGTH) == USART_WordLength_8b) || \
+
((LENGTH) == USART_WordLength_9b))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Modules
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USB_BSP
USB_OTG_DRIVER
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+ +

This file is the. +More...

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+Collaboration diagram for USB_BSP:
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+Modules

 USB_BSP_Exported_Defines
 
 USB_BSP_Exported_Types
 
 USB_BSP_Exported_Macros
 
 USB_BSP_Exported_Variables
 
 USB_BSP_Exported_FunctionsPrototype
 
+

Detailed Description

+

This file is the.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___b_s_p.map b/group___u_s_b___b_s_p.map new file mode 100644 index 0000000..a310bb3 --- /dev/null +++ b/group___u_s_b___b_s_p.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___u_s_b___b_s_p.md5 b/group___u_s_b___b_s_p.md5 new file mode 100644 index 0000000..ab32c4c --- /dev/null +++ b/group___u_s_b___b_s_p.md5 @@ -0,0 +1 @@ +9ddffad5e7f371f487c9c48bf6d1c426 \ No newline at end of file diff --git a/group___u_s_b___b_s_p.png b/group___u_s_b___b_s_p.png new file mode 100644 index 0000000..7eb5753 Binary files /dev/null and b/group___u_s_b___b_s_p.png differ diff --git a/group___u_s_b___b_s_p___exported___defines.html b/group___u_s_b___b_s_p___exported___defines.html new file mode 100644 index 0000000..022f130 --- /dev/null +++ b/group___u_s_b___b_s_p___exported___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_BSP_Exported_Defines + + + + + + + + + + +
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discoverpixy +
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USB_BSP_Exported_Defines
USB_OTG_DRIVER » USB_BSP
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+Functions
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USB_BSP_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_BSP
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+Functions

void BSP_Init (void)
 BSP_Init board user initializations. More...
 
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_Init Initilizes BSP configurations. More...
 
void USB_OTG_BSP_uDelay (const uint32_t usec)
 USB_OTG_BSP_uDelay This function provides delay time in micro sec. More...
 
void USB_OTG_BSP_mDelay (const uint32_t msec)
 USB_OTG_BSP_mDelay This function provides delay time in milli sec. More...
 
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt. More...
 
+

Detailed Description

+

Function Documentation

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+ + + + + + + + +
void BSP_Init (void )
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+ +

BSP_Init board user initializations.

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Parameters
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None
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None
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void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt.

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Parameters
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None
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Return values
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None
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void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_BSP_Init Initilizes BSP configurations.

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Parameters
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None
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None
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void USB_OTG_BSP_mDelay (const uint32_t msec)
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USB_OTG_BSP_mDelay This function provides delay time in milli sec.

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Parameters
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msec: Value of delay required in milli sec
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Return values
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None
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void USB_OTG_BSP_uDelay (const uint32_t usec)
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USB_OTG_BSP_uDelay This function provides delay time in micro sec.

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Parameters
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usec: Value of delay required in micro sec
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Return values
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None
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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0000000..f9a2c3c --- /dev/null +++ b/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.md5 b/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.md5 new file mode 100644 index 0000000..a613129 --- /dev/null +++ b/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.md5 @@ -0,0 +1 @@ +baeb4f801193eb2b3df63aca444966c5 \ No newline at end of file diff --git a/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.png b/group___u_s_b___b_s_p___exported___functions_prototype_gacffb89e4346b11dee704fe5a40326a1f_icgraph.png new file mode 100644 index 0000000..3564a23 Binary files /dev/null and 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+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
+
+ + +
+ +
+ +
+
+
USB_BSP_Exported_Macros
USB_OTG_DRIVER » USB_BSP
+
+
+
+Collaboration diagram for USB_BSP_Exported_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___b_s_p___exported___macros.map b/group___u_s_b___b_s_p___exported___macros.map new file mode 100644 index 0000000..af82a10 --- /dev/null +++ b/group___u_s_b___b_s_p___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___b_s_p___exported___macros.md5 b/group___u_s_b___b_s_p___exported___macros.md5 new file mode 100644 index 0000000..f9fb12b --- /dev/null +++ b/group___u_s_b___b_s_p___exported___macros.md5 @@ -0,0 +1 @@ +defb4763a564065862dd1e0ca4ab2fde \ No newline at end of file diff --git a/group___u_s_b___b_s_p___exported___macros.png b/group___u_s_b___b_s_p___exported___macros.png new file mode 100644 index 0000000..2066d32 Binary files /dev/null and b/group___u_s_b___b_s_p___exported___macros.png differ diff --git a/group___u_s_b___b_s_p___exported___types.html b/group___u_s_b___b_s_p___exported___types.html new file mode 100644 index 0000000..44b6def --- /dev/null +++ b/group___u_s_b___b_s_p___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_BSP_Exported_Types + + + + + + + + + + +
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USB_BSP_Exported_Types
USB_OTG_DRIVER » USB_BSP
+
+
+
+Collaboration diagram for USB_BSP_Exported_Types:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___b_s_p___exported___types.map b/group___u_s_b___b_s_p___exported___types.map new file mode 100644 index 0000000..2ffdc38 --- /dev/null +++ b/group___u_s_b___b_s_p___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___b_s_p___exported___types.md5 b/group___u_s_b___b_s_p___exported___types.md5 new file mode 100644 index 0000000..cbff16f --- /dev/null +++ b/group___u_s_b___b_s_p___exported___types.md5 @@ -0,0 +1 @@ +2d6c4eba7121342e8bed991dcb9ea0d3 \ No newline at end of file diff --git a/group___u_s_b___b_s_p___exported___types.png b/group___u_s_b___b_s_p___exported___types.png new file mode 100644 index 0000000..d48d65e Binary files /dev/null and b/group___u_s_b___b_s_p___exported___types.png differ diff --git a/group___u_s_b___b_s_p___exported___variables.html b/group___u_s_b___b_s_p___exported___variables.html new file mode 100644 index 0000000..a5f9087 --- /dev/null +++ b/group___u_s_b___b_s_p___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_BSP_Exported_Variables + + + + + + + + + + +
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USB_BSP_Exported_Variables
USB_OTG_DRIVER » USB_BSP
+
+
+
+Collaboration diagram for USB_BSP_Exported_Variables:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___b_s_p___exported___variables.map b/group___u_s_b___b_s_p___exported___variables.map new file mode 100644 index 0000000..b19bf0e --- /dev/null +++ b/group___u_s_b___b_s_p___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___b_s_p___exported___variables.md5 b/group___u_s_b___b_s_p___exported___variables.md5 new file mode 100644 index 0000000..38b146f --- /dev/null +++ b/group___u_s_b___b_s_p___exported___variables.md5 @@ -0,0 +1 @@ +0f14a83578adf72801d22efe8ce092c2 \ No newline at end of file diff --git a/group___u_s_b___b_s_p___exported___variables.png b/group___u_s_b___b_s_p___exported___variables.png new file mode 100644 index 0000000..28a226f Binary files /dev/null and b/group___u_s_b___b_s_p___exported___variables.png differ diff --git a/group___u_s_b___c_o_n_f.html b/group___u_s_b___c_o_n_f.html new file mode 100644 index 0000000..7ccdc30 --- /dev/null +++ b/group___u_s_b___c_o_n_f.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: USB_CONF + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
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+Modules
+
+
USB_CONF
USB_OTG_DRIVER
+
+
+ +

USB low level driver configuration file. +More...

+
+Collaboration diagram for USB_CONF:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Modules

 USB_CONF_Exported_Defines
 
 USB_CONF_Exported_Types
 
 USB_CONF_Exported_Macros
 
 USB_CONF_Exported_Variables
 
 USB_CONF_Exported_FunctionsPrototype
 
+

Detailed Description

+

USB low level driver configuration file.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f.map b/group___u_s_b___c_o_n_f.map new file mode 100644 index 0000000..983e69f --- /dev/null +++ b/group___u_s_b___c_o_n_f.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___u_s_b___c_o_n_f.md5 b/group___u_s_b___c_o_n_f.md5 new file mode 100644 index 0000000..70d45e9 --- /dev/null +++ b/group___u_s_b___c_o_n_f.md5 @@ -0,0 +1 @@ +b391b230ad5ac920ab3d5dd5fc300cc5 \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f.png b/group___u_s_b___c_o_n_f.png new file mode 100644 index 0000000..c6b6303 Binary files /dev/null and b/group___u_s_b___c_o_n_f.png differ diff --git a/group___u_s_b___c_o_n_f___exported___defines.html b/group___u_s_b___c_o_n_f___exported___defines.html new file mode 100644 index 0000000..9f5d701 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___defines.html @@ -0,0 +1,102 @@ + + + + + + +discoverpixy: USB_CONF_Exported_Defines + + + + + + + + + + +
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+Macros
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+
USB_CONF_Exported_Defines
USB_OTG_DRIVER » USB_CONF
+
+
+
+Collaboration diagram for USB_CONF_Exported_Defines:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f___exported___defines.map b/group___u_s_b___c_o_n_f___exported___defines.map new file mode 100644 index 0000000..d3bcff3 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_n_f___exported___defines.md5 b/group___u_s_b___c_o_n_f___exported___defines.md5 new file mode 100644 index 0000000..7496012 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___defines.md5 @@ -0,0 +1 @@ +8090db55276fb08521b9eeba5d7d79ca \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f___exported___defines.png b/group___u_s_b___c_o_n_f___exported___defines.png new file mode 100644 index 0000000..0b8c3ca Binary files /dev/null and b/group___u_s_b___c_o_n_f___exported___defines.png differ diff --git a/group___u_s_b___c_o_n_f___exported___functions_prototype.html b/group___u_s_b___c_o_n_f___exported___functions_prototype.html new file mode 100644 index 0000000..5afe355 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___functions_prototype.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_CONF_Exported_FunctionsPrototype + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ +
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+
USB_CONF_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_CONF
+
+
+
+Collaboration diagram for USB_CONF_Exported_FunctionsPrototype:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f___exported___functions_prototype.map b/group___u_s_b___c_o_n_f___exported___functions_prototype.map new file mode 100644 index 0000000..e870f75 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_n_f___exported___functions_prototype.md5 b/group___u_s_b___c_o_n_f___exported___functions_prototype.md5 new file mode 100644 index 0000000..2ca0758 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___functions_prototype.md5 @@ -0,0 +1 @@ +f8f7f84555a35f97cc63b12a9101cb66 \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f___exported___functions_prototype.png b/group___u_s_b___c_o_n_f___exported___functions_prototype.png new file mode 100644 index 0000000..af09aa3 Binary files /dev/null and b/group___u_s_b___c_o_n_f___exported___functions_prototype.png differ diff --git a/group___u_s_b___c_o_n_f___exported___macros.html b/group___u_s_b___c_o_n_f___exported___macros.html new file mode 100644 index 0000000..babe338 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_CONF_Exported_Macros + + + + + + + + + + +
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+ + + + +
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+
USB_CONF_Exported_Macros
USB_OTG_DRIVER » USB_CONF
+
+
+
+Collaboration diagram for USB_CONF_Exported_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f___exported___macros.map b/group___u_s_b___c_o_n_f___exported___macros.map new file mode 100644 index 0000000..5f72afb --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_n_f___exported___macros.md5 b/group___u_s_b___c_o_n_f___exported___macros.md5 new file mode 100644 index 0000000..c1ff1a6 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___macros.md5 @@ -0,0 +1 @@ +276efed489db627b0dd2322131fbeda8 \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f___exported___macros.png b/group___u_s_b___c_o_n_f___exported___macros.png new file mode 100644 index 0000000..cb31503 Binary files /dev/null and b/group___u_s_b___c_o_n_f___exported___macros.png differ diff --git a/group___u_s_b___c_o_n_f___exported___types.html b/group___u_s_b___c_o_n_f___exported___types.html new file mode 100644 index 0000000..79ae1b0 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_CONF_Exported_Types + + + + + + + + + + +
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USB_CONF_Exported_Types
USB_OTG_DRIVER » USB_CONF
+
+
+
+Collaboration diagram for USB_CONF_Exported_Types:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f___exported___types.map b/group___u_s_b___c_o_n_f___exported___types.map new file mode 100644 index 0000000..3e31853 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_n_f___exported___types.md5 b/group___u_s_b___c_o_n_f___exported___types.md5 new file mode 100644 index 0000000..c911889 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___types.md5 @@ -0,0 +1 @@ +2dce20b1e1b34b6d27a70d91ce844c4d \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f___exported___types.png b/group___u_s_b___c_o_n_f___exported___types.png new file mode 100644 index 0000000..879d77b Binary files /dev/null and b/group___u_s_b___c_o_n_f___exported___types.png differ diff --git a/group___u_s_b___c_o_n_f___exported___variables.html b/group___u_s_b___c_o_n_f___exported___variables.html new file mode 100644 index 0000000..2383eb7 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_CONF_Exported_Variables + + + + + + + + + + +
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+ + + + + + +
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discoverpixy +
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+
USB_CONF_Exported_Variables
USB_OTG_DRIVER » USB_CONF
+
+
+
+Collaboration diagram for USB_CONF_Exported_Variables:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_n_f___exported___variables.map b/group___u_s_b___c_o_n_f___exported___variables.map new file mode 100644 index 0000000..c1a1944 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_n_f___exported___variables.md5 b/group___u_s_b___c_o_n_f___exported___variables.md5 new file mode 100644 index 0000000..c1402e4 --- /dev/null +++ b/group___u_s_b___c_o_n_f___exported___variables.md5 @@ -0,0 +1 @@ +54d3339b0aa647bcd88933975b644c03 \ No newline at end of file diff --git a/group___u_s_b___c_o_n_f___exported___variables.png b/group___u_s_b___c_o_n_f___exported___variables.png new file mode 100644 index 0000000..5cefc07 Binary files /dev/null and b/group___u_s_b___c_o_n_f___exported___variables.png differ diff --git a/group___u_s_b___c_o_r_e.html b/group___u_s_b___c_o_r_e.html new file mode 100644 index 0000000..4514233 --- /dev/null +++ b/group___u_s_b___c_o_r_e.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: USB_CORE + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
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+
+Modules | +Macros
+
+
USB_CORE
USB_OTG_DRIVER
+
+
+ +

usb otg driver core layer +More...

+
+Collaboration diagram for USB_CORE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USB_CORE_Exported_Defines
 
 USB_CORE_Exported_Types
 
 USB_CORE_Exported_Macros
 
 USB_CORE_Exported_Variables
 
 USB_CORE_Exported_FunctionsPrototype
 
 USB_CORE_Private_Defines
 
 USB_CORE_Private_TypesDefinitions
 
 USB_CORE_Private_Macros
 
 USB_CORE_Private_Variables
 
 USB_CORE_Private_FunctionPrototypes
 
 USB_CORE_Private_Functions
 
+ + + +

+Macros

+#define MAX_DATA_LENGTH   0xFF
 
+

Detailed Description

+

usb otg driver core layer

+

This file includes the USB-OTG Core Layer.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_r_e.map b/group___u_s_b___c_o_r_e.map new file mode 100644 index 0000000..bf01645 --- /dev/null +++ b/group___u_s_b___c_o_r_e.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b___c_o_r_e.md5 b/group___u_s_b___c_o_r_e.md5 new file mode 100644 index 0000000..418531c --- /dev/null +++ b/group___u_s_b___c_o_r_e.md5 @@ -0,0 +1 @@ +e89646aee821b89ff99a1a305a246c1d \ No newline at end of file diff --git a/group___u_s_b___c_o_r_e.png b/group___u_s_b___c_o_r_e.png new file mode 100644 index 0000000..8a8c989 Binary files /dev/null and b/group___u_s_b___c_o_r_e.png differ diff --git a/group___u_s_b___c_o_r_e___exported___defines.html b/group___u_s_b___c_o_r_e___exported___defines.html new file mode 100644 index 0000000..5e68e40 --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___defines.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: USB_CORE_Exported_Defines + + + + + + + + + + +
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+Macros
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USB_CORE_Exported_Defines
USB_OTG_DRIVER » USB_CORE
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+Macros

+#define USB_OTG_EP0_IDLE   0
 
+#define USB_OTG_EP0_SETUP   1
 
+#define USB_OTG_EP0_DATA_IN   2
 
+#define USB_OTG_EP0_DATA_OUT   3
 
+#define USB_OTG_EP0_STATUS_IN   4
 
+#define USB_OTG_EP0_STATUS_OUT   5
 
+#define USB_OTG_EP0_STALL   6
 
+#define USB_OTG_EP_TX_DIS   0x0000
 
+#define USB_OTG_EP_TX_STALL   0x0010
 
+#define USB_OTG_EP_TX_NAK   0x0020
 
+#define USB_OTG_EP_TX_VALID   0x0030
 
+#define USB_OTG_EP_RX_DIS   0x0000
 
+#define USB_OTG_EP_RX_STALL   0x1000
 
+#define USB_OTG_EP_RX_NAK   0x2000
 
+#define USB_OTG_EP_RX_VALID   0x3000
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_r_e___exported___defines.map b/group___u_s_b___c_o_r_e___exported___defines.map new file mode 100644 index 0000000..b3bb93c --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_r_e___exported___defines.md5 b/group___u_s_b___c_o_r_e___exported___defines.md5 new file mode 100644 index 0000000..3a8aa3b --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___defines.md5 @@ -0,0 +1 @@ +349be78f4a228398248f48177a5de14a \ No newline at end of file diff --git a/group___u_s_b___c_o_r_e___exported___defines.png b/group___u_s_b___c_o_r_e___exported___defines.png new file mode 100644 index 0000000..7cc69a5 Binary files /dev/null and b/group___u_s_b___c_o_r_e___exported___defines.png differ diff --git a/group___u_s_b___c_o_r_e___exported___functions_prototype.html b/group___u_s_b___c_o_r_e___exported___functions_prototype.html new file mode 100644 index 0000000..373486b --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___functions_prototype.html @@ -0,0 +1,774 @@ + + + + + + +discoverpixy: USB_CORE_Exported_FunctionsPrototype + + + + + + + + + + +
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+Functions
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USB_CORE_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_CORE
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+Functions

USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation. More...
 
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 USB_OTG_SelectCore Initialize core registers address. More...
 
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
void * USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
 USB_OTG_ReadPacket : Reads a packet from the Rx FIFO. More...
 
USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
 USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP. More...
 
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev, uint32_t num)
 USB_OTG_FlushTxFifo : Flush a Tx FIFO. More...
 
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_FlushRxFifo : Flush a Rx FIFO. More...
 
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadCoreItr : returns the Core Interrupt register. More...
 
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register. More...
 
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsHostMode : Check if it is host mode. More...
 
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsDeviceMode : Check if it is device mode. More...
 
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_GetMode : Get current mode. More...
 
+USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev)
 
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
 USB_OTG_SetCurrentMode : Set ID line. More...
 
+

Detailed Description

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Function Documentation

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USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation.

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Parameters
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pdev: Selected device
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Return values
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg.

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Parameters
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pdev: Selected device
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Return values
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg.

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Parameters
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pdev: Selected device
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Return values
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_FlushRxFifo : Flush a Rx FIFO.

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Parameters
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pdev: Selected device
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Return values
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE * pdev,
uint32_t num 
)
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USB_OTG_FlushTxFifo : Flush a Tx FIFO.

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Parameters
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pdev: Selected device
num: FO num
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USB_OTG_STS: status
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uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_GetMode : Get current mode.

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Parameters
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pdev: Selected device
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Return values
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currentmode
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uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_IsDeviceMode : Check if it is device mode.

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pdev: Selected device
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num_in_ep
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uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_IsHostMode : Check if it is host mode.

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Parameters
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pdev: Selected device
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Return values
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num_in_ep
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uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_ReadCoreItr : returns the Core Interrupt register.

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Parameters
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pdev: Selected device
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Return values
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Status
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uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register.

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pdev: Selected device
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Status
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void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dest,
uint16_t len 
)
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USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.

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Parameters
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pdev: Selected device
dest: Destination Pointer
bytes: No. of bytes
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USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID 
)
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USB_OTG_SelectCore Initialize core registers address.

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pdev: Selected device
coreID: USB OTG Core ID
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE * pdev,
uint8_t mode 
)
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USB_OTG_SetCurrentMode : Set ID line.

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pdev: Selected device
mode: (Host/device)
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE * pdev,
uint8_t * src,
uint8_t ch_ep_num,
uint16_t len 
)
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USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.

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Parameters
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pdev: Selected device
src: source pointer
ch_ep_num: end point number
bytes: No. of bytes
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USB_OTG_STS: status
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USB_CORE_Exported_Macros
USB_OTG_DRIVER » USB_CORE
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+Collaboration diagram for USB_CORE_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_r_e___exported___macros.map b/group___u_s_b___c_o_r_e___exported___macros.map new file mode 100644 index 0000000..6bced60 --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_r_e___exported___macros.md5 b/group___u_s_b___c_o_r_e___exported___macros.md5 new file mode 100644 index 0000000..bb7cfeb --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___macros.md5 @@ -0,0 +1 @@ +53af613590d439818799fadae87a25e5 \ No newline at end of file diff --git a/group___u_s_b___c_o_r_e___exported___macros.png b/group___u_s_b___c_o_r_e___exported___macros.png new file mode 100644 index 0000000..4850b0d Binary files /dev/null and b/group___u_s_b___c_o_r_e___exported___macros.png differ diff --git a/group___u_s_b___c_o_r_e___exported___types.html b/group___u_s_b___c_o_r_e___exported___types.html new file mode 100644 index 0000000..60a1a2c --- /dev/null +++ b/group___u_s_b___c_o_r_e___exported___types.html @@ -0,0 +1,242 @@ + + + + + + +discoverpixy: USB_CORE_Exported_Types + + + + + + + + + + +
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+Classes | +Typedefs | +Enumerations
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USB_CORE_Exported_Types
USB_OTG_DRIVER » USB_CORE
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+Collaboration diagram for USB_CORE_Exported_Types:
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+Classes

struct  USB_OTG_hc
 
struct  USB_OTG_ep
 
struct  USB_OTG_core_cfg
 
struct  usb_setup_req
 
struct  _Device_TypeDef
 
struct  USB_OTG_hPort
 
struct  _Device_cb
 
struct  _USBD_USR_PROP
 
struct  _DCD
 
struct  _HCD
 
struct  _OTG
 
struct  USB_OTG_handle
 
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+Typedefs

+typedef struct USB_OTG_hc USB_OTG_HC
 
+typedef struct USB_OTG_hc * PUSB_OTG_HC
 
+typedef struct USB_OTG_ep USB_OTG_EP
 
+typedef struct USB_OTG_ep * PUSB_OTG_EP
 
+typedef struct USB_OTG_core_cfg USB_OTG_CORE_CFGS
 
+typedef struct USB_OTG_core_cfg * PUSB_OTG_CORE_CFGS
 
+typedef struct usb_setup_req USB_SETUP_REQ
 
+typedef struct _Device_TypeDef USBD_DEVICE
 
+typedef struct _Device_TypeDef * pUSBD_DEVICE
 
+typedef struct USB_OTG_hPort USB_OTG_hPort_TypeDef
 
+typedef struct _Device_cb USBD_Class_cb_TypeDef
 
+typedef struct _USBD_USR_PROP USBD_Usr_cb_TypeDef
 
+typedef struct _DCD DCD_DEV
 
+typedef struct _DCD * DCD_PDEV
 
+typedef struct _HCD HCD_DEV
 
+typedef struct _HCD * USB_OTG_USBH_PDEV
 
+typedef struct _OTG OTG_DEV
 
+typedef struct _OTG * USB_OTG_USBO_PDEV
 
+typedef struct USB_OTG_handle USB_OTG_CORE_HANDLE
 
+typedef struct USB_OTG_handle * PUSB_OTG_CORE_HANDLE
 
+ + + + + + + + + +

+Enumerations

enum  USB_OTG_STS { USB_OTG_OK = 0, +USB_OTG_FAIL + }
 
enum  HC_STATUS {
+  HC_IDLE = 0, +HC_XFRC, +HC_HALTED, +HC_NAK, +
+  HC_NYET, +HC_STALL, +HC_XACTERR, +HC_BBLERR, +
+  HC_DATATGLERR +
+ }
 
enum  URB_STATE {
+  URB_IDLE = 0, +URB_DONE, +URB_NOTREADY, +URB_ERROR, +
+  URB_STALL +
+ }
 
enum  CTRL_STATUS {
+  CTRL_START = 0, +CTRL_XFRC, +CTRL_HALTED, +CTRL_NAK, +
+  CTRL_STALL, +CTRL_XACTERR, +CTRL_BBLERR, +CTRL_DATATGLERR, +
+  CTRL_FAIL +
+ }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_CORE_Exported_Variables
USB_OTG_DRIVER » USB_CORE
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_CORE_Private_Defines
USB_OTG_DRIVER » USB_CORE
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USB_CORE_Private_FunctionPrototypes
USB_OTG_DRIVER » USB_CORE
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+Functions
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USB_CORE_Private_Functions
USB_OTG_DRIVER » USB_CORE
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+Functions

USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
 USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP. More...
 
void * USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
 USB_OTG_ReadPacket : Reads a packet from the Rx FIFO. More...
 
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 USB_OTG_SelectCore Initialize core registers address. More...
 
USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation. More...
 
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev, uint32_t num)
 USB_OTG_FlushTxFifo : Flush a Tx FIFO. More...
 
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_FlushRxFifo : Flush a Rx FIFO. More...
 
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
 USB_OTG_SetCurrentMode : Set ID line. More...
 
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_GetMode : Get current mode. More...
 
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsDeviceMode : Check if it is device mode. More...
 
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsHostMode : Check if it is host mode. More...
 
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadCoreItr : returns the Core Interrupt register. More...
 
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register. More...
 
+

Detailed Description

+

Function Documentation

+ +
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+ + + + + + + + +
USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation.

+
Parameters
+ + +
pdev: Selected device
+
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Return values
+ + +
USB_OTG_STS: status
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USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg.

+
Parameters
+ + +
pdev: Selected device
+
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Return values
+ + +
USB_OTG_STS: status
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USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg.

+
Parameters
+ + +
pdev: Selected device
+
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Return values
+ + +
USB_OTG_STS: status
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USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE * pdev)
+
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USB_OTG_FlushRxFifo : Flush a Rx FIFO.

+
Parameters
+ + +
pdev: Selected device
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Return values
+ + +
USB_OTG_STS: status
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USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE * pdev,
uint32_t num 
)
+
+ +

USB_OTG_FlushTxFifo : Flush a Tx FIFO.

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Parameters
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pdev: Selected device
num: FO num
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Return values
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USB_OTG_STS: status
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uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_GetMode : Get current mode.

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Parameters
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pdev: Selected device
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Return values
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currentmode
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uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_IsDeviceMode : Check if it is device mode.

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Parameters
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pdev: Selected device
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Return values
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num_in_ep
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uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_IsHostMode : Check if it is host mode.

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Parameters
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pdev: Selected device
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Return values
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num_in_ep
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uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_ReadCoreItr : returns the Core Interrupt register.

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Parameters
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pdev: Selected device
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Return values
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Status
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uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE * pdev)
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USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register.

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pdev: Selected device
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Status
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void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dest,
uint16_t len 
)
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USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.

+
Parameters
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pdev: Selected device
dest: Destination Pointer
bytes: No. of bytes
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Return values
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None
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USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID 
)
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USB_OTG_SelectCore Initialize core registers address.

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Parameters
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pdev: Selected device
coreID: USB OTG Core ID
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE * pdev,
uint8_t mode 
)
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USB_OTG_SetCurrentMode : Set ID line.

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Parameters
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pdev: Selected device
mode: (Host/device)
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Return values
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USB_OTG_STS: status
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USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE * pdev,
uint8_t * src,
uint8_t ch_ep_num,
uint16_t len 
)
+
+ +

USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.

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Parameters
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pdev: Selected device
src: source pointer
ch_ep_num: end point number
bytes: No. of bytes
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USB_OTG_STS: status
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_CORE_Private_Macros
USB_OTG_DRIVER » USB_CORE
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USB_CORE_Private_TypesDefinitions
USB_OTG_DRIVER » USB_CORE
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_r_e___private___types_definitions.map b/group___u_s_b___c_o_r_e___private___types_definitions.map new file mode 100644 index 0000000..bb3968d --- /dev/null +++ b/group___u_s_b___c_o_r_e___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_r_e___private___types_definitions.md5 b/group___u_s_b___c_o_r_e___private___types_definitions.md5 new file mode 100644 index 0000000..250c70f --- /dev/null +++ b/group___u_s_b___c_o_r_e___private___types_definitions.md5 @@ -0,0 +1 @@ +4d20b7d73d8c959db5a9c7887f716291 \ No newline at end of file diff --git a/group___u_s_b___c_o_r_e___private___types_definitions.png b/group___u_s_b___c_o_r_e___private___types_definitions.png new file mode 100644 index 0000000..26224f4 Binary files /dev/null and b/group___u_s_b___c_o_r_e___private___types_definitions.png differ diff --git a/group___u_s_b___c_o_r_e___private___variables.html b/group___u_s_b___c_o_r_e___private___variables.html new file mode 100644 index 0000000..38f841c --- /dev/null +++ b/group___u_s_b___c_o_r_e___private___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_CORE_Private_Variables + + + + + + + + + + +
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USB_CORE_Private_Variables
USB_OTG_DRIVER » USB_CORE
+
+
+
+Collaboration diagram for USB_CORE_Private_Variables:
+
+
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+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___c_o_r_e___private___variables.map b/group___u_s_b___c_o_r_e___private___variables.map new file mode 100644 index 0000000..87cc20f --- /dev/null +++ b/group___u_s_b___c_o_r_e___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___c_o_r_e___private___variables.md5 b/group___u_s_b___c_o_r_e___private___variables.md5 new file mode 100644 index 0000000..7119763 --- /dev/null +++ b/group___u_s_b___c_o_r_e___private___variables.md5 @@ -0,0 +1 @@ +0f906fe1ae7009354b9d6a50c8eba4d7 \ No newline at end of file diff --git a/group___u_s_b___c_o_r_e___private___variables.png b/group___u_s_b___c_o_r_e___private___variables.png new file mode 100644 index 0000000..ed1986a Binary files /dev/null and b/group___u_s_b___c_o_r_e___private___variables.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s.html b/group___u_s_b___d_e_f_i_n_e_s.html new file mode 100644 index 0000000..dd2ba84 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: USB_DEFINES + + + + + + + + + + +
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+Modules
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USB_DEFINES
USB_OTG_DRIVER
+
+
+ +

This file is the. +More...

+
+Collaboration diagram for USB_DEFINES:
+
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+Modules

 USB_DEFINES_Exported_Defines
 
 _CORE_DEFINES_
 
 _GLOBAL_DEFINES_
 
 _OnTheGo_DEFINES_
 
 __DEVICE_DEFINES_
 
 __HOST_DEFINES_
 
 USB_DEFINES_Exported_Types
 
 USB_DEFINES_Exported_Macros
 
 USB_DEFINES_Exported_Variables
 
 USB_DEFINES_Exported_FunctionsPrototype
 
 's
 
+

Detailed Description

+

This file is the.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s.map b/group___u_s_b___d_e_f_i_n_e_s.map new file mode 100644 index 0000000..d53ce4f --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s.md5 b/group___u_s_b___d_e_f_i_n_e_s.md5 new file mode 100644 index 0000000..2a158bc --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s.md5 @@ -0,0 +1 @@ +e93ecd52c0e0d793072045a73498d7a2 \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s.png b/group___u_s_b___d_e_f_i_n_e_s.png new file mode 100644 index 0000000..b4ad50b Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___defines.html b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.html new file mode 100644 index 0000000..6aeb62a --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_DEFINES_Exported_Defines + + + + + + + + + + +
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USB_DEFINES_Exported_Defines
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for USB_DEFINES_Exported_Defines:
+
+
+ + +
+
+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___defines.map b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.map new file mode 100644 index 0000000..b9caf6e --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___defines.md5 b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.md5 new file mode 100644 index 0000000..8c105ce --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.md5 @@ -0,0 +1 @@ +f30fb2db61c298b2e59256c0330ee815 \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___defines.png b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.png new file mode 100644 index 0000000..523b98c Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s___exported___defines.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.html b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.html new file mode 100644 index 0000000..b6799a5 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_DEFINES_Exported_FunctionsPrototype + + + + + + + + + + +
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USB_DEFINES_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for USB_DEFINES_Exported_FunctionsPrototype:
+
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+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.map b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.map new file mode 100644 index 0000000..d0779ed --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.md5 b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.md5 new file mode 100644 index 0000000..30a4fb6 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.md5 @@ -0,0 +1 @@ +f4e515a83d9559a46a1b0d87a3954325 \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.png b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.png new file mode 100644 index 0000000..dd62a6c Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s___exported___functions_prototype.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___macros.html b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.html new file mode 100644 index 0000000..e183bf9 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_DEFINES_Exported_Macros + + + + + + + + + + +
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USB_DEFINES_Exported_Macros
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for USB_DEFINES_Exported_Macros:
+
+
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+
+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___macros.map b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.map new file mode 100644 index 0000000..79f0019 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___macros.md5 b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.md5 new file mode 100644 index 0000000..c302d2d --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.md5 @@ -0,0 +1 @@ +1739a11cfb9fe85b8afda4c96dc168a8 \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___macros.png b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.png new file mode 100644 index 0000000..e4a4533 Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s___exported___macros.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___types.html b/group___u_s_b___d_e_f_i_n_e_s___exported___types.html new file mode 100644 index 0000000..5f31791 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___types.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: USB_DEFINES_Exported_Types + + + + + + + + + + +
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discoverpixy +
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+Enumerations
+
+
USB_DEFINES_Exported_Types
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for USB_DEFINES_Exported_Types:
+
+
+ + +
+
+ + + + +

+Enumerations

enum  USB_OTG_CORE_ID_TypeDef { USB_OTG_HS_CORE_ID = 0, +USB_OTG_FS_CORE_ID = 1 + }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___types.map b/group___u_s_b___d_e_f_i_n_e_s___exported___types.map new file mode 100644 index 0000000..763da96 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___types.md5 b/group___u_s_b___d_e_f_i_n_e_s___exported___types.md5 new file mode 100644 index 0000000..e0d2fcb --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___types.md5 @@ -0,0 +1 @@ +4a4bf8e764532e31aa0b3f1c7265a669 \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___types.png b/group___u_s_b___d_e_f_i_n_e_s___exported___types.png new file mode 100644 index 0000000..ecb9acb Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s___exported___types.png differ diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___variables.html b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.html new file mode 100644 index 0000000..b489bd9 --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_DEFINES_Exported_Variables + + + + + + + + + + +
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USB_DEFINES_Exported_Variables
USB_OTG_DRIVER » USB_DEFINES
+
+
+
+Collaboration diagram for USB_DEFINES_Exported_Variables:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___variables.map b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.map new file mode 100644 index 0000000..40dd00d --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___variables.md5 b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.md5 new file mode 100644 index 0000000..cd824db --- /dev/null +++ b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.md5 @@ -0,0 +1 @@ +4fb946c7a6c792ea244b4fb0243dc52d \ No newline at end of file diff --git a/group___u_s_b___d_e_f_i_n_e_s___exported___variables.png b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.png new file mode 100644 index 0000000..fbc6916 Binary files /dev/null and b/group___u_s_b___d_e_f_i_n_e_s___exported___variables.png differ diff --git a/group___u_s_b___h_c_d.html b/group___u_s_b___h_c_d.html new file mode 100644 index 0000000..e5e678f --- /dev/null +++ b/group___u_s_b___h_c_d.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USB_HCD + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Modules
+
+
USB_HCD
USB_OTG_DRIVER
+
+
+ +

This file is the. +More...

+
+Collaboration diagram for USB_HCD:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USB_HCD_Exported_Defines
 
 USB_HCD_Exported_Types
 
 USB_HCD_Exported_Macros
 
 USB_HCD_Exported_Variables
 
 USB_HCD_Exported_FunctionsPrototype
 
 USB_HCD_Private_Defines
 
 USB_HCD_Private_TypesDefinitions
 
 USB_HCD_Private_Macros
 
 USB_HCD_Private_Variables
 
 USB_HCD_Private_FunctionPrototypes
 
 USB_HCD_Private_Functions
 
+

Detailed Description

+

This file is the.

+

This file is the interface between EFSL ans Host mass-storage class.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d.map b/group___u_s_b___h_c_d.map new file mode 100644 index 0000000..4448132 --- /dev/null +++ b/group___u_s_b___h_c_d.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b___h_c_d.md5 b/group___u_s_b___h_c_d.md5 new file mode 100644 index 0000000..9aac6e5 --- /dev/null +++ b/group___u_s_b___h_c_d.md5 @@ -0,0 +1 @@ +3893a64c561810a7492ee6cb84c5588e \ No newline at end of file diff --git a/group___u_s_b___h_c_d.png b/group___u_s_b___h_c_d.png new file mode 100644 index 0000000..f976500 Binary files /dev/null and b/group___u_s_b___h_c_d.png differ diff --git a/group___u_s_b___h_c_d___exported___defines.html b/group___u_s_b___h_c_d___exported___defines.html new file mode 100644 index 0000000..eea7937 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_Exported_Defines + + + + + + + + + + +
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USB_HCD_Exported_Defines
USB_OTG_DRIVER » USB_HCD
+
+
+
+Collaboration diagram for USB_HCD_Exported_Defines:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___exported___defines.map b/group___u_s_b___h_c_d___exported___defines.map new file mode 100644 index 0000000..8857d96 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___exported___defines.md5 b/group___u_s_b___h_c_d___exported___defines.md5 new file mode 100644 index 0000000..7882813 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___defines.md5 @@ -0,0 +1 @@ +eca58cfbb0269831862d49ac7b453eb8 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___exported___defines.png b/group___u_s_b___h_c_d___exported___defines.png new file mode 100644 index 0000000..9c32efa Binary files /dev/null and b/group___u_s_b___h_c_d___exported___defines.png differ diff --git a/group___u_s_b___h_c_d___exported___functions_prototype.html b/group___u_s_b___h_c_d___exported___functions_prototype.html new file mode 100644 index 0000000..20bc36d --- /dev/null +++ b/group___u_s_b___h_c_d___exported___functions_prototype.html @@ -0,0 +1,581 @@ + + + + + + +discoverpixy: USB_HCD_Exported_FunctionsPrototype + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
USB_HCD_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_HCD
+
+
+
+Collaboration diagram for USB_HCD_Exported_FunctionsPrototype:
+
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+Functions

uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 HCD_Init Initialize the HOST portion of the driver. More...
 
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_HC_Init This function prepare a HC and start a transfer. More...
 
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_SubmitRequest This function prepare a HC and start a transfer. More...
 
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentSpeed Get Current device Speed. More...
 
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev)
 HCD_ResetPort Issues the reset command to device. More...
 
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev)
 HCD_IsDeviceConnected Check if the device is connected. More...
 
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentFrame This function returns the frame number for sof packet. More...
 
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetURB_State This function returns the last URBstate. More...
 
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetXferCnt This function returns the last URBstate. More...
 
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetHCState This function returns the HC Status. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_GetCurrentFrame This function returns the frame number for sof packet.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Framenumber
+
+
+ +

+Here is the caller graph for this function:
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uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_GetCurrentSpeed Get Current device Speed.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Status
+
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HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetHCState This function returns the HC Status.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
HC_STATUS
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetURB_State This function returns the last URBstate.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
URB_STATE
+
+
+ +

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uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetXferCnt This function returns the last URBstate.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
No.of data bytes transferred
+
+
+ +

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uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num 
)
+
+ +

HCD_HC_Init This function prepare a HC and start a transfer.

+
Parameters
+ + + +
pdevSelected device
hc_numChannel number
+
+
+
Return values
+ + +
status
+
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
uint32_t HCD_Init (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID 
)
+
+ +

HCD_Init Initialize the HOST portion of the driver.

+
Parameters
+ + + +
pdevSelected device
base_addressOTG base address
+
+
+
Return values
+ + +
Status
+
+
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uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_IsDeviceConnected Check if the device is connected.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Deviceconnection status. 1 -> connected and 0 -> disconnected
+
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uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_ResetPort Issues the reset command to device.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Status
+
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uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num 
)
+
+ +

HCD_SubmitRequest This function prepare a HC and start a transfer.

+
Parameters
+ + + +
pdevSelected device
hc_numChannel number
+
+
+
Return values
+ + +
status
+
+
+ +

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+discoverpixy: USB_HCD_Exported_Macros + + + + + + + + + + +
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USB_HCD_Exported_Macros
USB_OTG_DRIVER » USB_HCD
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+Collaboration diagram for USB_HCD_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_HCD_Exported_Types
USB_OTG_DRIVER » USB_HCD
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+Collaboration diagram for USB_HCD_Exported_Types:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___exported___types.map b/group___u_s_b___h_c_d___exported___types.map new file mode 100644 index 0000000..3ccf607 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___exported___types.md5 b/group___u_s_b___h_c_d___exported___types.md5 new file mode 100644 index 0000000..2aaf8e7 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___types.md5 @@ -0,0 +1 @@ +e56c50703db7c1129800866b570b8014 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___exported___types.png b/group___u_s_b___h_c_d___exported___types.png new file mode 100644 index 0000000..13e040e Binary files /dev/null and b/group___u_s_b___h_c_d___exported___types.png differ diff --git a/group___u_s_b___h_c_d___exported___variables.html b/group___u_s_b___h_c_d___exported___variables.html new file mode 100644 index 0000000..aac7e13 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_Exported_Variables + + + + + + + + + + +
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USB_HCD_Exported_Variables
USB_OTG_DRIVER » USB_HCD
+
+
+
+Collaboration diagram for USB_HCD_Exported_Variables:
+
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+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___exported___variables.map b/group___u_s_b___h_c_d___exported___variables.map new file mode 100644 index 0000000..2ff382c --- /dev/null +++ b/group___u_s_b___h_c_d___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___exported___variables.md5 b/group___u_s_b___h_c_d___exported___variables.md5 new file mode 100644 index 0000000..4b3e666 --- /dev/null +++ b/group___u_s_b___h_c_d___exported___variables.md5 @@ -0,0 +1 @@ +53ae7d2e11ba3eb5803fac522d20c42d \ No newline at end of file diff --git a/group___u_s_b___h_c_d___exported___variables.png b/group___u_s_b___h_c_d___exported___variables.png new file mode 100644 index 0000000..75e4070 Binary files /dev/null and b/group___u_s_b___h_c_d___exported___variables.png differ diff --git a/group___u_s_b___h_c_d___i_n_t.html b/group___u_s_b___h_c_d___i_n_t.html new file mode 100644 index 0000000..0fd0d10 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USB_HCD_INT + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Modules
+
+
USB_HCD_INT
USB_OTG_DRIVER
+
+
+ +

This file is the. +More...

+
+Collaboration diagram for USB_HCD_INT:
+
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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USB_HCD_INT_Exported_Defines
 
 USB_HCD_INT_Exported_Types
 
 USB_HCD_INT_Exported_Macros
 
 USB_HCD_INT_Exported_Variables
 
 USB_HCD_INT_Exported_FunctionsPrototype
 
 USB_HCD_INT_Private_Defines
 
 USB_HCD_INT_Private_TypesDefinitions
 
 USB_HCD_INT_Private_Macros
 
 USB_HCD_INT_Private_Variables
 
 USB_HCD_INT_Private_FunctionPrototypes
 
 USB_HCD_INT_Private_Functions
 
+

Detailed Description

+

This file is the.

+

This file contains the interrupt subroutines for the Host mode.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t.map b/group___u_s_b___h_c_d___i_n_t.map new file mode 100644 index 0000000..8d1d180 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b___h_c_d___i_n_t.md5 b/group___u_s_b___h_c_d___i_n_t.md5 new file mode 100644 index 0000000..0cdb204 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t.md5 @@ -0,0 +1 @@ +e78828f268db71ad8aaa6c390e8d86a7 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t.png b/group___u_s_b___h_c_d___i_n_t.png new file mode 100644 index 0000000..a242025 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___defines.html b/group___u_s_b___h_c_d___i_n_t___exported___defines.html new file mode 100644 index 0000000..96b5ef1 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Exported_Defines + + + + + + + + + + +
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USB_HCD_INT_Exported_Defines
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Exported_Defines:
+
+
+ + +
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___defines.map b/group___u_s_b___h_c_d___i_n_t___exported___defines.map new file mode 100644 index 0000000..d58c08f --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___defines.md5 b/group___u_s_b___h_c_d___i_n_t___exported___defines.md5 new file mode 100644 index 0000000..1bd8d5f --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___defines.md5 @@ -0,0 +1 @@ +8a2eaaf0fc29ff3920f7333f4638eff0 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___defines.png b/group___u_s_b___h_c_d___i_n_t___exported___defines.png new file mode 100644 index 0000000..eac5ee1 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___defines.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.html b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.html new file mode 100644 index 0000000..676175e --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.html @@ -0,0 +1,158 @@ + + + + + + +discoverpixy: USB_HCD_INT_Exported_FunctionsPrototype + + + + + + + + + + +
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+
discoverpixy +
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+Functions
+
+
USB_HCD_INT_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Exported_FunctionsPrototype:
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+ + + + + + + + + + + +

+Functions

+void ConnectCallback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
+void Disconnect_Callback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
+void Overcurrent_Callback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
 HOST_Handle_ISR This function handles all USB Host Interrupts. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HOST_Handle_ISR This function handles all USB Host Interrupts.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
status
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.map b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.map new file mode 100644 index 0000000..288655b --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.md5 b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.md5 new file mode 100644 index 0000000..84d38b5 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.md5 @@ -0,0 +1 @@ +76099addfaff2730c3cb9d2556164297 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.png b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.png new file mode 100644 index 0000000..7495643 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map new file mode 100644 index 0000000..06330d9 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 new file mode 100644 index 0000000..2cdfc9b --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 @@ -0,0 +1 @@ +6274ca24c842bbcfcaab04df2f531df9 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png new file mode 100644 index 0000000..7cbdd45 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___functions_prototype_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___macros.html b/group___u_s_b___h_c_d___i_n_t___exported___macros.html new file mode 100644 index 0000000..eb32772 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___macros.html @@ -0,0 +1,233 @@ + + + + + + +discoverpixy: USB_HCD_INT_Exported_Macros + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
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+Macros
+
+
USB_HCD_INT_Exported_Macros
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Exported_Macros:
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+
+ + +
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+ + + + + + + + + + + + +

+Macros

#define CLEAR_HC_INT(HC_REGS, intr)
 
#define MASK_HOST_INT_CHH(hc_num)
 
#define UNMASK_HOST_INT_CHH(hc_num)
 
#define MASK_HOST_INT_ACK(hc_num)
 
#define UNMASK_HOST_INT_ACK(hc_num)
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define CLEAR_HC_INT( HC_REGS,
 intr 
)
+
+Value:
{\
+
USB_OTG_HCINTn_TypeDef hcint_clear; \
+
hcint_clear.d32 = 0; \
+
hcint_clear.b.intr = 1; \
+
USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
+
}\
+
+
+
+ +
+
+ + + + + + + + +
#define MASK_HOST_INT_ACK( hc_num)
+
+Value:
{ USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
GINTMSK.b.ack = 0; \
+
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
_USB_OTG_HCGINTMSK_TypeDef
Definition: usb_regs.h:1121
+
+
+
+ +
+
+ + + + + + + + +
#define MASK_HOST_INT_CHH( hc_num)
+
+Value:
{ USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
GINTMSK.b.chhltd = 0; \
+
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
_USB_OTG_HCGINTMSK_TypeDef
Definition: usb_regs.h:1121
+
+
+
+ +
+
+ + + + + + + + +
#define UNMASK_HOST_INT_ACK( hc_num)
+
+Value:
{ USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
GINTMSK.b.ack = 1; \
+
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
_USB_OTG_HCGINTMSK_TypeDef
Definition: usb_regs.h:1121
+
+
+
+ +
+
+ + + + + + + + +
#define UNMASK_HOST_INT_CHH( hc_num)
+
+Value:
{ USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
GINTMSK.b.chhltd = 1; \
+
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
_USB_OTG_HCGINTMSK_TypeDef
Definition: usb_regs.h:1121
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___macros.map b/group___u_s_b___h_c_d___i_n_t___exported___macros.map new file mode 100644 index 0000000..38d4421 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___macros.md5 b/group___u_s_b___h_c_d___i_n_t___exported___macros.md5 new file mode 100644 index 0000000..c540e14 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___macros.md5 @@ -0,0 +1 @@ +4f128f6e02a28520d36d3832a30d1b78 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___macros.png b/group___u_s_b___h_c_d___i_n_t___exported___macros.png new file mode 100644 index 0000000..cf1c08d Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___macros.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___types.html b/group___u_s_b___h_c_d___i_n_t___exported___types.html new file mode 100644 index 0000000..45e3f78 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Exported_Types + + + + + + + + + + +
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USB_HCD_INT_Exported_Types
USB_OTG_DRIVER » USB_HCD_INT
+
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+
+Collaboration diagram for USB_HCD_INT_Exported_Types:
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+ + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___types.map b/group___u_s_b___h_c_d___i_n_t___exported___types.map new file mode 100644 index 0000000..be2057b --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___types.md5 b/group___u_s_b___h_c_d___i_n_t___exported___types.md5 new file mode 100644 index 0000000..61dfd01 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___types.md5 @@ -0,0 +1 @@ +de2f6eea6f64dd2bf4b752221ae7d87b \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___types.png b/group___u_s_b___h_c_d___i_n_t___exported___types.png new file mode 100644 index 0000000..6ecef03 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___types.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___exported___variables.html b/group___u_s_b___h_c_d___i_n_t___exported___variables.html new file mode 100644 index 0000000..769a820 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Exported_Variables + + + + + + + + + + +
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USB_HCD_INT_Exported_Variables
USB_OTG_DRIVER » USB_HCD_INT
+
+
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+Collaboration diagram for USB_HCD_INT_Exported_Variables:
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+ + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___variables.map b/group___u_s_b___h_c_d___i_n_t___exported___variables.map new file mode 100644 index 0000000..6b13538 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___exported___variables.md5 b/group___u_s_b___h_c_d___i_n_t___exported___variables.md5 new file mode 100644 index 0000000..16026a9 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___exported___variables.md5 @@ -0,0 +1 @@ +b86bea29f048575462b7b90154c6546a \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___exported___variables.png b/group___u_s_b___h_c_d___i_n_t___exported___variables.png new file mode 100644 index 0000000..eb70284 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___exported___variables.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___defines.html b/group___u_s_b___h_c_d___i_n_t___private___defines.html new file mode 100644 index 0000000..5db3cf8 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_Defines + + + + + + + + + + +
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USB_HCD_INT_Private_Defines
USB_OTG_DRIVER » USB_HCD_INT
+
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+Collaboration diagram for USB_HCD_INT_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___defines.map b/group___u_s_b___h_c_d___i_n_t___private___defines.map new file mode 100644 index 0000000..f2c0afd --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___defines.md5 b/group___u_s_b___h_c_d___i_n_t___private___defines.md5 new file mode 100644 index 0000000..12196f5 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___defines.md5 @@ -0,0 +1 @@ +7fd693b43f70164162d82f06ff510fd0 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___defines.png b/group___u_s_b___h_c_d___i_n_t___private___defines.png new file mode 100644 index 0000000..1d383ce Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___defines.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.html b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.html new file mode 100644 index 0000000..a35edce --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_FunctionPrototypes + + + + + + + + + + +
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USB_HCD_INT_Private_FunctionPrototypes
USB_OTG_DRIVER » USB_HCD_INT
+
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+
+Collaboration diagram for USB_HCD_INT_Private_FunctionPrototypes:
+
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+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.map b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.map new file mode 100644 index 0000000..e0bcaa8 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.md5 b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.md5 new file mode 100644 index 0000000..0b05974 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.md5 @@ -0,0 +1 @@ +c3a6489ec9664d6a1962ac0b76df8aa7 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.png b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.png new file mode 100644 index 0000000..10f2e76 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___function_prototypes.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions.html b/group___u_s_b___h_c_d___i_n_t___private___functions.html new file mode 100644 index 0000000..55abd47 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___functions.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_Functions + + + + + + + + + + +
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+Functions
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USB_HCD_INT_Private_Functions
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Private_Functions:
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+Functions

uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
 HOST_Handle_ISR This function handles all USB Host Interrupts. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HOST_Handle_ISR This function handles all USB Host Interrupts.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
status
+
+
+ +

+Here is the call graph for this function:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions.map b/group___u_s_b___h_c_d___i_n_t___private___functions.map new file mode 100644 index 0000000..9505c59 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions.md5 b/group___u_s_b___h_c_d___i_n_t___private___functions.md5 new file mode 100644 index 0000000..d9b7f5a --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___functions.md5 @@ -0,0 +1 @@ +f8393846b76a17518e35393723da0c50 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions.png b/group___u_s_b___h_c_d___i_n_t___private___functions.png new file mode 100644 index 0000000..2ace6da Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___functions.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map new file mode 100644 index 0000000..06330d9 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 new file mode 100644 index 0000000..2cdfc9b --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.md5 @@ -0,0 +1 @@ +6274ca24c842bbcfcaab04df2f531df9 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png new file mode 100644 index 0000000..7cbdd45 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___functions_ga0d058eb3d6ea01a9e47e6447690aa8c1_cgraph.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___macros.html b/group___u_s_b___h_c_d___i_n_t___private___macros.html new file mode 100644 index 0000000..a2a2351 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_Macros + + + + + + + + + + +
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USB_HCD_INT_Private_Macros
USB_OTG_DRIVER » USB_HCD_INT
+
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+Collaboration diagram for USB_HCD_INT_Private_Macros:
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+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___macros.map b/group___u_s_b___h_c_d___i_n_t___private___macros.map new file mode 100644 index 0000000..b04102a --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___macros.md5 b/group___u_s_b___h_c_d___i_n_t___private___macros.md5 new file mode 100644 index 0000000..e541483 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___macros.md5 @@ -0,0 +1 @@ +a77fa6ea6534eb732580acaab53e55b8 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___macros.png b/group___u_s_b___h_c_d___i_n_t___private___macros.png new file mode 100644 index 0000000..3aae8d7 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___macros.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___types_definitions.html b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.html new file mode 100644 index 0000000..40a2846 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_TypesDefinitions + + + + + + + + + + +
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USB_HCD_INT_Private_TypesDefinitions
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___types_definitions.map b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.map new file mode 100644 index 0000000..2c26a35 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___types_definitions.md5 b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.md5 new file mode 100644 index 0000000..ebe5d4c --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.md5 @@ -0,0 +1 @@ +239f3810c2495a7859845bddbe243b22 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___types_definitions.png b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.png new file mode 100644 index 0000000..8ef3888 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___types_definitions.png differ diff --git a/group___u_s_b___h_c_d___i_n_t___private___variables.html b/group___u_s_b___h_c_d___i_n_t___private___variables.html new file mode 100644 index 0000000..ce7311d --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_INT_Private_Variables + + + + + + + + + + +
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USB_HCD_INT_Private_Variables
USB_OTG_DRIVER » USB_HCD_INT
+
+
+
+Collaboration diagram for USB_HCD_INT_Private_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___i_n_t___private___variables.map b/group___u_s_b___h_c_d___i_n_t___private___variables.map new file mode 100644 index 0000000..a10cd76 --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___i_n_t___private___variables.md5 b/group___u_s_b___h_c_d___i_n_t___private___variables.md5 new file mode 100644 index 0000000..6f68aac --- /dev/null +++ b/group___u_s_b___h_c_d___i_n_t___private___variables.md5 @@ -0,0 +1 @@ +72008ff3a18c8a1ad26e4f2402782118 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___i_n_t___private___variables.png b/group___u_s_b___h_c_d___i_n_t___private___variables.png new file mode 100644 index 0000000..1925db3 Binary files /dev/null and b/group___u_s_b___h_c_d___i_n_t___private___variables.png differ diff --git a/group___u_s_b___h_c_d___private___defines.html b/group___u_s_b___h_c_d___private___defines.html new file mode 100644 index 0000000..d088120 --- /dev/null +++ b/group___u_s_b___h_c_d___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_Private_Defines + + + + + + + + + + +
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USB_HCD_Private_Defines
USB_OTG_DRIVER » USB_HCD
+
+
+
+Collaboration diagram for USB_HCD_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___private___defines.map b/group___u_s_b___h_c_d___private___defines.map new file mode 100644 index 0000000..0f85db2 --- /dev/null +++ b/group___u_s_b___h_c_d___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___private___defines.md5 b/group___u_s_b___h_c_d___private___defines.md5 new file mode 100644 index 0000000..6f427ae --- /dev/null +++ b/group___u_s_b___h_c_d___private___defines.md5 @@ -0,0 +1 @@ +9ea8f5bb5fad0be515197d1a5aa52a6c \ No newline at end of file diff --git a/group___u_s_b___h_c_d___private___defines.png b/group___u_s_b___h_c_d___private___defines.png new file mode 100644 index 0000000..1292351 Binary files /dev/null and b/group___u_s_b___h_c_d___private___defines.png differ diff --git a/group___u_s_b___h_c_d___private___function_prototypes.html b/group___u_s_b___h_c_d___private___function_prototypes.html new file mode 100644 index 0000000..2603239 --- /dev/null +++ b/group___u_s_b___h_c_d___private___function_prototypes.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_HCD_Private_FunctionPrototypes + + + + + + + + + + +
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USB_HCD_Private_FunctionPrototypes
USB_OTG_DRIVER » USB_HCD
+
+
+
+Collaboration diagram for USB_HCD_Private_FunctionPrototypes:
+
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+ + +
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___h_c_d___private___function_prototypes.map b/group___u_s_b___h_c_d___private___function_prototypes.map new file mode 100644 index 0000000..d3995ed --- /dev/null +++ b/group___u_s_b___h_c_d___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___h_c_d___private___function_prototypes.md5 b/group___u_s_b___h_c_d___private___function_prototypes.md5 new file mode 100644 index 0000000..e0dedbe --- /dev/null +++ b/group___u_s_b___h_c_d___private___function_prototypes.md5 @@ -0,0 +1 @@ +9fb5c8adb881c3826045160613f9e6c3 \ No newline at end of file diff --git a/group___u_s_b___h_c_d___private___function_prototypes.png b/group___u_s_b___h_c_d___private___function_prototypes.png new file mode 100644 index 0000000..a7899b5 Binary files /dev/null and b/group___u_s_b___h_c_d___private___function_prototypes.png differ diff --git a/group___u_s_b___h_c_d___private___functions.html b/group___u_s_b___h_c_d___private___functions.html new file mode 100644 index 0000000..097341c --- /dev/null +++ b/group___u_s_b___h_c_d___private___functions.html @@ -0,0 +1,581 @@ + + + + + + +discoverpixy: USB_HCD_Private_Functions + + + + + + + + + + +
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+Functions
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+
USB_HCD_Private_Functions
USB_OTG_DRIVER » USB_HCD
+
+
+
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+Functions

uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 HCD_Init Initialize the HOST portion of the driver. More...
 
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentSpeed Get Current device Speed. More...
 
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev)
 HCD_ResetPort Issues the reset command to device. More...
 
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev)
 HCD_IsDeviceConnected Check if the device is connected. More...
 
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentFrame This function returns the frame number for sof packet. More...
 
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetURB_State This function returns the last URBstate. More...
 
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetXferCnt This function returns the last URBstate. More...
 
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetHCState This function returns the HC Status. More...
 
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_HC_Init This function prepare a HC and start a transfer. More...
 
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_SubmitRequest This function prepare a HC and start a transfer. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_GetCurrentFrame This function returns the frame number for sof packet.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Framenumber
+
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uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_GetCurrentSpeed Get Current device Speed.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Status
+
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HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetHCState This function returns the HC Status.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
HC_STATUS
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetURB_State This function returns the last URBstate.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
URB_STATE
+
+
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uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE * pdev,
uint8_t ch_num 
)
+
+ +

HCD_GetXferCnt This function returns the last URBstate.

+
Parameters
+ + +
pdevSelected device
+
+
+
Return values
+ + +
No.of data bytes transferred
+
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uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num 
)
+
+ +

HCD_HC_Init This function prepare a HC and start a transfer.

+
Parameters
+ + + +
pdevSelected device
hc_numChannel number
+
+
+
Return values
+ + +
status
+
+
+ +
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uint32_t HCD_Init (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID 
)
+
+ +

HCD_Init Initialize the HOST portion of the driver.

+
Parameters
+ + + +
pdevSelected device
base_addressOTG base address
+
+
+
Return values
+ + +
Status
+
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uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_IsDeviceConnected Check if the device is connected.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Deviceconnection status. 1 -> connected and 0 -> disconnected
+
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uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE * pdev)
+
+ +

HCD_ResetPort Issues the reset command to device.

+
Parameters
+ + +
pdev: Selected device
+
+
+
Return values
+ + +
Status
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uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num 
)
+
+ +

HCD_SubmitRequest This function prepare a HC and start a transfer.

+
Parameters
+ + + +
pdevSelected device
hc_numChannel number
+
+
+
Return values
+ + +
status
+
+
+ +

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_HCD_Private_Macros
USB_OTG_DRIVER » USB_HCD
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+Collaboration diagram for USB_HCD_Private_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_HCD_Private_TypesDefinitions
USB_OTG_DRIVER » USB_HCD
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+Collaboration diagram for USB_HCD_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USB_HCD_Private_Variables
USB_OTG_DRIVER » USB_HCD
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+Collaboration diagram for USB_HCD_Private_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Modules | +Enumerator | +Variables
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USB_OTG_DRIVER
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+Collaboration diagram for USB_OTG_DRIVER:
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+Modules

 USB_CONF
 USB low level driver configuration file.
 
 USB_BSP
 This file is the.
 
 USB_CORE
 usb otg driver core layer
 
 USB_DEFINES
 This file is the.
 
 USB_HCD
 This file is the.
 
 USB_HCD_INT
 This file is the.
 
 USB_REGS
 This file is the.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+__IO uint32_t _USB_OTG_GREGS::GOTGCTL
 
+__IO uint32_t _USB_OTG_GREGS::GOTGINT
 
+__IO uint32_t _USB_OTG_GREGS::GAHBCFG
 
+__IO uint32_t _USB_OTG_GREGS::GUSBCFG
 
+__IO uint32_t _USB_OTG_GREGS::GRSTCTL
 
+__IO uint32_t _USB_OTG_GREGS::GINTSTS
 
+__IO uint32_t _USB_OTG_GREGS::GINTMSK
 
+__IO uint32_t _USB_OTG_GREGS::GRXSTSR
 
+__IO uint32_t _USB_OTG_GREGS::GRXSTSP
 
+__IO uint32_t _USB_OTG_GREGS::GRXFSIZ
 
+__IO uint32_t _USB_OTG_GREGS::DIEPTXF0_HNPTXFSIZ
 
+__IO uint32_t _USB_OTG_GREGS::HNPTXSTS
 
+__IO uint32_t _USB_OTG_GREGS::GI2CCTL
 
+uint32_t _USB_OTG_GREGS::Reserved34
 
+__IO uint32_t _USB_OTG_GREGS::GCCFG
 
+__IO uint32_t _USB_OTG_GREGS::CID
 
+uint32_t _USB_OTG_GREGS::Reserved40 [48]
 
+__IO uint32_t _USB_OTG_GREGS::HPTXFSIZ
 
+__IO uint32_t _USB_OTG_GREGS::DIEPTXF [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t _USB_OTG_DREGS::DCFG
 
+__IO uint32_t _USB_OTG_DREGS::DCTL
 
+__IO uint32_t _USB_OTG_DREGS::DSTS
 
+uint32_t _USB_OTG_DREGS::Reserved0C
 
+__IO uint32_t _USB_OTG_DREGS::DIEPMSK
 
+__IO uint32_t _USB_OTG_DREGS::DOEPMSK
 
+__IO uint32_t _USB_OTG_DREGS::DAINT
 
+__IO uint32_t _USB_OTG_DREGS::DAINTMSK
 
+uint32_t _USB_OTG_DREGS::Reserved20
 
+uint32_t _USB_OTG_DREGS::Reserved9
 
+__IO uint32_t _USB_OTG_DREGS::DVBUSDIS
 
+__IO uint32_t _USB_OTG_DREGS::DVBUSPULSE
 
+__IO uint32_t _USB_OTG_DREGS::DTHRCTL
 
+__IO uint32_t _USB_OTG_DREGS::DIEPEMPMSK
 
+__IO uint32_t _USB_OTG_DREGS::DEACHINT
 
+__IO uint32_t _USB_OTG_DREGS::DEACHMSK
 
+uint32_t _USB_OTG_DREGS::Reserved40
 
+__IO uint32_t _USB_OTG_DREGS::DINEP1MSK
 
+uint32_t _USB_OTG_DREGS::Reserved44 [15]
 
+__IO uint32_t _USB_OTG_DREGS::DOUTEP1MSK
 
+__IO uint32_t _USB_OTG_INEPREGS::DIEPCTL
 
+uint32_t _USB_OTG_INEPREGS::Reserved04
 
+__IO uint32_t _USB_OTG_INEPREGS::DIEPINT
 
+uint32_t _USB_OTG_INEPREGS::Reserved0C
 
+__IO uint32_t _USB_OTG_INEPREGS::DIEPTSIZ
 
+__IO uint32_t _USB_OTG_INEPREGS::DIEPDMA
 
+__IO uint32_t _USB_OTG_INEPREGS::DTXFSTS
 
+uint32_t _USB_OTG_INEPREGS::Reserved18
 
+__IO uint32_t _USB_OTG_OUTEPREGS::DOEPCTL
 
+__IO uint32_t _USB_OTG_OUTEPREGS::DOUTEPFRM
 
+__IO uint32_t _USB_OTG_OUTEPREGS::DOEPINT
 
+uint32_t _USB_OTG_OUTEPREGS::Reserved0C
 
+__IO uint32_t _USB_OTG_OUTEPREGS::DOEPTSIZ
 
+__IO uint32_t _USB_OTG_OUTEPREGS::DOEPDMA
 
+uint32_t _USB_OTG_OUTEPREGS::Reserved18 [2]
 
+__IO uint32_t _USB_OTG_HREGS::HCFG
 
+__IO uint32_t _USB_OTG_HREGS::HFIR
 
+__IO uint32_t _USB_OTG_HREGS::HFNUM
 
+uint32_t _USB_OTG_HREGS::Reserved40C
 
+__IO uint32_t _USB_OTG_HREGS::HPTXSTS
 
+__IO uint32_t _USB_OTG_HREGS::HAINT
 
+__IO uint32_t _USB_OTG_HREGS::HAINTMSK
 
+__IO uint32_t _USB_OTG_HC_REGS::HCCHAR
 
+__IO uint32_t _USB_OTG_HC_REGS::HCSPLT
 
+__IO uint32_t _USB_OTG_HC_REGS::HCINT
 
+__IO uint32_t _USB_OTG_HC_REGS::HCGINTMSK
 
+__IO uint32_t _USB_OTG_HC_REGS::HCTSIZ
 
+__IO uint32_t _USB_OTG_HC_REGS::HCDMA
 
+uint32_t _USB_OTG_HC_REGS::Reserved [2]
 
+USB_OTG_GREGS * USB_OTG_core_regs::GREGS
 
+USB_OTG_DREGS * USB_OTG_core_regs::DREGS
 
+USB_OTG_HREGS * USB_OTG_core_regs::HREGS
 
+USB_OTG_INEPREGS * USB_OTG_core_regs::INEP_REGS [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_OUTEPREGS * USB_OTG_core_regs::OUTEP_REGS [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_HC_REGS * USB_OTG_core_regs::HC_REGS [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t * USB_OTG_core_regs::HPRT0
 
+__IO uint32_t * USB_OTG_core_regs::DFIFO [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t * USB_OTG_core_regs::PCGCCTL
 
+uint32_t _USB_OTG_OTGCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::sesreqscs: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::sesreq: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::Reserved2_7: 6
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::hstnegscs: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::hnpreq: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::hstsethnpen: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::devhnpen: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::Reserved12_15: 4
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::conidsts: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::Reserved17: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::asesvld: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::bsesvld: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::currmod: 1
 
+uint32_t   _USB_OTG_OTGCTL_TypeDef::Reserved21_31: 11
 
+struct {
+   uint32_t   sesreqscs: 1
 
+   uint32_t   sesreq: 1
 
+   uint32_t   Reserved2_7: 6
 
+   uint32_t   hstnegscs: 1
 
+   uint32_t   hnpreq: 1
 
+   uint32_t   hstsethnpen: 1
 
+   uint32_t   devhnpen: 1
 
+   uint32_t   Reserved12_15: 4
 
+   uint32_t   conidsts: 1
 
+   uint32_t   Reserved17: 1
 
+   uint32_t   asesvld: 1
 
+   uint32_t   bsesvld: 1
 
+   uint32_t   currmod: 1
 
+   uint32_t   Reserved21_31: 11
 
} _USB_OTG_OTGCTL_TypeDef::b
 
+uint32_t _USB_OTG_GOTGINT_TypeDef::d32
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::Reserved0_1: 2
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::sesenddet: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::Reserved3_7: 5
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::sesreqsucstschng: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::hstnegsucstschng: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::reserver10_16: 7
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::hstnegdet: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::adevtoutchng: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::debdone: 1
 
+uint32_t   _USB_OTG_GOTGINT_TypeDef::Reserved31_20: 12
 
+struct {
+   uint32_t   Reserved0_1: 2
 
+   uint32_t   sesenddet: 1
 
+   uint32_t   Reserved3_7: 5
 
+   uint32_t   sesreqsucstschng: 1
 
+   uint32_t   hstnegsucstschng: 1
 
+   uint32_t   reserver10_16: 7
 
+   uint32_t   hstnegdet: 1
 
+   uint32_t   adevtoutchng: 1
 
+   uint32_t   debdone: 1
 
+   uint32_t   Reserved31_20: 12
 
} _USB_OTG_GOTGINT_TypeDef::b
 
+uint32_t _USB_OTG_GAHBCFG_TypeDef::d32
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::glblintrmsk: 1
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::hburstlen: 4
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::dmaenable: 1
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::Reserved: 1
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::nptxfemplvl_txfemplvl: 1
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::ptxfemplvl: 1
 
+uint32_t   _USB_OTG_GAHBCFG_TypeDef::Reserved9_31: 23
 
+struct {
+   uint32_t   glblintrmsk: 1
 
+   uint32_t   hburstlen: 4
 
+   uint32_t   dmaenable: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   nptxfemplvl_txfemplvl: 1
 
+   uint32_t   ptxfemplvl: 1
 
+   uint32_t   Reserved9_31: 23
 
} _USB_OTG_GAHBCFG_TypeDef::b
 
+uint32_t _USB_OTG_GUSBCFG_TypeDef::d32
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::toutcal: 3
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::phyif: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_utmi_sel: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::fsintf: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::physel: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ddrsel: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::srpcap: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::hnpcap: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::usbtrdtim: 4
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::nptxfrwnden: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::phylpwrclksel: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::otgutmifssel: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_fsls: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_auto_res: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_clk_sus_m: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_ext_vbus_drv: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::ulpi_int_vbus_indicator: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::term_sel_dl_pulse: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::Reserved: 6
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::force_host: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::force_dev: 1
 
+uint32_t   _USB_OTG_GUSBCFG_TypeDef::corrupt_tx: 1
 
+struct {
+   uint32_t   toutcal: 3
 
+   uint32_t   phyif: 1
 
+   uint32_t   ulpi_utmi_sel: 1
 
+   uint32_t   fsintf: 1
 
+   uint32_t   physel: 1
 
+   uint32_t   ddrsel: 1
 
+   uint32_t   srpcap: 1
 
+   uint32_t   hnpcap: 1
 
+   uint32_t   usbtrdtim: 4
 
+   uint32_t   nptxfrwnden: 1
 
+   uint32_t   phylpwrclksel: 1
 
+   uint32_t   otgutmifssel: 1
 
+   uint32_t   ulpi_fsls: 1
 
+   uint32_t   ulpi_auto_res: 1
 
+   uint32_t   ulpi_clk_sus_m: 1
 
+   uint32_t   ulpi_ext_vbus_drv: 1
 
+   uint32_t   ulpi_int_vbus_indicator: 1
 
+   uint32_t   term_sel_dl_pulse: 1
 
+   uint32_t   Reserved: 6
 
+   uint32_t   force_host: 1
 
+   uint32_t   force_dev: 1
 
+   uint32_t   corrupt_tx: 1
 
} _USB_OTG_GUSBCFG_TypeDef::b
 
+uint32_t _USB_OTG_GRSTCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::csftrst: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::hsftrst: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::hstfrm: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::intknqflsh: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::rxfflsh: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::txfflsh: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::txfnum: 5
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::Reserved11_29: 19
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::dmareq: 1
 
+uint32_t   _USB_OTG_GRSTCTL_TypeDef::ahbidle: 1
 
+struct {
+   uint32_t   csftrst: 1
 
+   uint32_t   hsftrst: 1
 
+   uint32_t   hstfrm: 1
 
+   uint32_t   intknqflsh: 1
 
+   uint32_t   rxfflsh: 1
 
+   uint32_t   txfflsh: 1
 
+   uint32_t   txfnum: 5
 
+   uint32_t   Reserved11_29: 19
 
+   uint32_t   dmareq: 1
 
+   uint32_t   ahbidle: 1
 
} _USB_OTG_GRSTCTL_TypeDef::b
 
+uint32_t _USB_OTG_GINTMSK_TypeDef::d32
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::Reserved0: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::modemismatch: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::otgintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::sofintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::rxstsqlvl: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::nptxfempty: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::ginnakeff: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::goutnakeff: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::Reserved8: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::i2cintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::erlysuspend: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::usbsuspend: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::usbreset: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::enumdone: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::isooutdrop: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::eopframe: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::Reserved16: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::epmismatch: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::inepintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::outepintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::incomplisoin: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::incomplisoout: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::Reserved22_23: 2
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::portintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::hcintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::ptxfempty: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::Reserved27: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::conidstschng: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::disconnect: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::sessreqintr: 1
 
+uint32_t   _USB_OTG_GINTMSK_TypeDef::wkupintr: 1
 
+struct {
+   uint32_t   Reserved0: 1
 
+   uint32_t   modemismatch: 1
 
+   uint32_t   otgintr: 1
 
+   uint32_t   sofintr: 1
 
+   uint32_t   rxstsqlvl: 1
 
+   uint32_t   nptxfempty: 1
 
+   uint32_t   ginnakeff: 1
 
+   uint32_t   goutnakeff: 1
 
+   uint32_t   Reserved8: 1
 
+   uint32_t   i2cintr: 1
 
+   uint32_t   erlysuspend: 1
 
+   uint32_t   usbsuspend: 1
 
+   uint32_t   usbreset: 1
 
+   uint32_t   enumdone: 1
 
+   uint32_t   isooutdrop: 1
 
+   uint32_t   eopframe: 1
 
+   uint32_t   Reserved16: 1
 
+   uint32_t   epmismatch: 1
 
+   uint32_t   inepintr: 1
 
+   uint32_t   outepintr: 1
 
+   uint32_t   incomplisoin: 1
 
+   uint32_t   incomplisoout: 1
 
+   uint32_t   Reserved22_23: 2
 
+   uint32_t   portintr: 1
 
+   uint32_t   hcintr: 1
 
+   uint32_t   ptxfempty: 1
 
+   uint32_t   Reserved27: 1
 
+   uint32_t   conidstschng: 1
 
+   uint32_t   disconnect: 1
 
+   uint32_t   sessreqintr: 1
 
+   uint32_t   wkupintr: 1
 
} _USB_OTG_GINTMSK_TypeDef::b
 
+uint32_t _USB_OTG_GINTSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::curmode: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::modemismatch: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::otgintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::sofintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::rxstsqlvl: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::nptxfempty: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::ginnakeff: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::goutnakeff: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::Reserved8: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::i2cintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::erlysuspend: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::usbsuspend: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::usbreset: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::enumdone: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::isooutdrop: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::eopframe: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::intimerrx: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::epmismatch: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::inepint: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::outepintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::incomplisoin: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::incomplisoout: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::Reserved22_23: 2
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::portintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::hcintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::ptxfempty: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::Reserved27: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::conidstschng: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::disconnect: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::sessreqintr: 1
 
+uint32_t   _USB_OTG_GINTSTS_TypeDef::wkupintr: 1
 
+struct {
+   uint32_t   curmode: 1
 
+   uint32_t   modemismatch: 1
 
+   uint32_t   otgintr: 1
 
+   uint32_t   sofintr: 1
 
+   uint32_t   rxstsqlvl: 1
 
+   uint32_t   nptxfempty: 1
 
+   uint32_t   ginnakeff: 1
 
+   uint32_t   goutnakeff: 1
 
+   uint32_t   Reserved8: 1
 
+   uint32_t   i2cintr: 1
 
+   uint32_t   erlysuspend: 1
 
+   uint32_t   usbsuspend: 1
 
+   uint32_t   usbreset: 1
 
+   uint32_t   enumdone: 1
 
+   uint32_t   isooutdrop: 1
 
+   uint32_t   eopframe: 1
 
+   uint32_t   intimerrx: 1
 
+   uint32_t   epmismatch: 1
 
+   uint32_t   inepint: 1
 
+   uint32_t   outepintr: 1
 
+   uint32_t   incomplisoin: 1
 
+   uint32_t   incomplisoout: 1
 
+   uint32_t   Reserved22_23: 2
 
+   uint32_t   portintr: 1
 
+   uint32_t   hcintr: 1
 
+   uint32_t   ptxfempty: 1
 
+   uint32_t   Reserved27: 1
 
+   uint32_t   conidstschng: 1
 
+   uint32_t   disconnect: 1
 
+   uint32_t   sessreqintr: 1
 
+   uint32_t   wkupintr: 1
 
} _USB_OTG_GINTSTS_TypeDef::b
 
+uint32_t _USB_OTG_DRXSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::epnum: 4
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::bcnt: 11
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::dpid: 2
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::pktsts: 4
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::fn: 4
 
+uint32_t   _USB_OTG_DRXSTS_TypeDef::Reserved: 7
 
+struct {
+   uint32_t   epnum: 4
 
+   uint32_t   bcnt: 11
 
+   uint32_t   dpid: 2
 
+   uint32_t   pktsts: 4
 
+   uint32_t   fn: 4
 
+   uint32_t   Reserved: 7
 
} _USB_OTG_DRXSTS_TypeDef::b
 
+uint32_t _USB_OTG_GRXSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_GRXSTS_TypeDef::chnum: 4
 
+uint32_t   _USB_OTG_GRXSTS_TypeDef::bcnt: 11
 
+uint32_t   _USB_OTG_GRXSTS_TypeDef::dpid: 2
 
+uint32_t   _USB_OTG_GRXSTS_TypeDef::pktsts: 4
 
+uint32_t   _USB_OTG_GRXSTS_TypeDef::Reserved: 11
 
+struct {
+   uint32_t   chnum: 4
 
+   uint32_t   bcnt: 11
 
+   uint32_t   dpid: 2
 
+   uint32_t   pktsts: 4
 
+   uint32_t   Reserved: 11
 
} _USB_OTG_GRXSTS_TypeDef::b
 
+uint32_t _USB_OTG_FSIZ_TypeDef::d32
 
+uint32_t   _USB_OTG_FSIZ_TypeDef::startaddr: 16
 
+uint32_t   _USB_OTG_FSIZ_TypeDef::depth: 16
 
+struct {
+   uint32_t   startaddr: 16
 
+   uint32_t   depth: 16
 
} _USB_OTG_FSIZ_TypeDef::b
 
+uint32_t _USB_OTG_HNPTXSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::nptxfspcavail: 16
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::nptxqspcavail: 8
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::nptxqtop_terminate: 1
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::nptxqtop_timer: 2
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::nptxqtop: 2
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::chnum: 2
 
+uint32_t   _USB_OTG_HNPTXSTS_TypeDef::Reserved: 1
 
+struct {
+   uint32_t   nptxfspcavail: 16
 
+   uint32_t   nptxqspcavail: 8
 
+   uint32_t   nptxqtop_terminate: 1
 
+   uint32_t   nptxqtop_timer: 2
 
+   uint32_t   nptxqtop: 2
 
+   uint32_t   chnum: 2
 
+   uint32_t   Reserved: 1
 
} _USB_OTG_HNPTXSTS_TypeDef::b
 
+uint32_t _USB_OTG_DTXFSTSn_TypeDef::d32
 
+uint32_t   _USB_OTG_DTXFSTSn_TypeDef::txfspcavail: 16
 
+uint32_t   _USB_OTG_DTXFSTSn_TypeDef::Reserved: 16
 
+struct {
+   uint32_t   txfspcavail: 16
 
+   uint32_t   Reserved: 16
 
} _USB_OTG_DTXFSTSn_TypeDef::b
 
+uint32_t _USB_OTG_GI2CCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::rwdata: 8
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::regaddr: 8
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::addr: 7
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::i2cen: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::ack: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::i2csuspctl: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::i2cdevaddr: 2
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::dat_se0: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::Reserved: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::rw: 1
 
+uint32_t   _USB_OTG_GI2CCTL_TypeDef::bsydne: 1
 
+struct {
+   uint32_t   rwdata: 8
 
+   uint32_t   regaddr: 8
 
+   uint32_t   addr: 7
 
+   uint32_t   i2cen: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   i2csuspctl: 1
 
+   uint32_t   i2cdevaddr: 2
 
+   uint32_t   dat_se0: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   rw: 1
 
+   uint32_t   bsydne: 1
 
} _USB_OTG_GI2CCTL_TypeDef::b
 
+uint32_t _USB_OTG_GCCFG_TypeDef::d32
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::Reserved_in: 16
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::pwdn: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::i2cifen: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::vbussensingA: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::vbussensingB: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::sofouten: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::disablevbussensing: 1
 
+uint32_t   _USB_OTG_GCCFG_TypeDef::Reserved_out: 10
 
+struct {
+   uint32_t   Reserved_in: 16
 
+   uint32_t   pwdn: 1
 
+   uint32_t   i2cifen: 1
 
+   uint32_t   vbussensingA: 1
 
+   uint32_t   vbussensingB: 1
 
+   uint32_t   sofouten: 1
 
+   uint32_t   disablevbussensing: 1
 
+   uint32_t   Reserved_out: 10
 
} _USB_OTG_GCCFG_TypeDef::b
 
+uint32_t _USB_OTG_DCFG_TypeDef::d32
 
+uint32_t   _USB_OTG_DCFG_TypeDef::devspd: 2
 
+uint32_t   _USB_OTG_DCFG_TypeDef::nzstsouthshk: 1
 
+uint32_t   _USB_OTG_DCFG_TypeDef::Reserved3: 1
 
+uint32_t   _USB_OTG_DCFG_TypeDef::devaddr: 7
 
+uint32_t   _USB_OTG_DCFG_TypeDef::perfrint: 2
 
+uint32_t   _USB_OTG_DCFG_TypeDef::Reserved13_17: 5
 
+uint32_t   _USB_OTG_DCFG_TypeDef::epmscnt: 4
 
+struct {
+   uint32_t   devspd: 2
 
+   uint32_t   nzstsouthshk: 1
 
+   uint32_t   Reserved3: 1
 
+   uint32_t   devaddr: 7
 
+   uint32_t   perfrint: 2
 
+   uint32_t   Reserved13_17: 5
 
+   uint32_t   epmscnt: 4
 
} _USB_OTG_DCFG_TypeDef::b
 
+uint32_t _USB_OTG_DCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_DCTL_TypeDef::rmtwkupsig: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::sftdiscon: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::gnpinnaksts: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::goutnaksts: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::tstctl: 3
 
+uint32_t   _USB_OTG_DCTL_TypeDef::sgnpinnak: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::cgnpinnak: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::sgoutnak: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::cgoutnak: 1
 
+uint32_t   _USB_OTG_DCTL_TypeDef::Reserved: 21
 
+struct {
+   uint32_t   rmtwkupsig: 1
 
+   uint32_t   sftdiscon: 1
 
+   uint32_t   gnpinnaksts: 1
 
+   uint32_t   goutnaksts: 1
 
+   uint32_t   tstctl: 3
 
+   uint32_t   sgnpinnak: 1
 
+   uint32_t   cgnpinnak: 1
 
+   uint32_t   sgoutnak: 1
 
+   uint32_t   cgoutnak: 1
 
+   uint32_t   Reserved: 21
 
} _USB_OTG_DCTL_TypeDef::b
 
+uint32_t _USB_OTG_DSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_DSTS_TypeDef::suspsts: 1
 
+uint32_t   _USB_OTG_DSTS_TypeDef::enumspd: 2
 
+uint32_t   _USB_OTG_DSTS_TypeDef::errticerr: 1
 
+uint32_t   _USB_OTG_DSTS_TypeDef::Reserved4_7: 4
 
+uint32_t   _USB_OTG_DSTS_TypeDef::soffn: 14
 
+uint32_t   _USB_OTG_DSTS_TypeDef::Reserved22_31: 10
 
+struct {
+   uint32_t   suspsts: 1
 
+   uint32_t   enumspd: 2
 
+   uint32_t   errticerr: 1
 
+   uint32_t   Reserved4_7: 4
 
+   uint32_t   soffn: 14
 
+   uint32_t   Reserved22_31: 10
 
} _USB_OTG_DSTS_TypeDef::b
 
+uint32_t _USB_OTG_DIEPINTn_TypeDef::d32
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::xfercompl: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::epdisabled: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::ahberr: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::timeout: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::intktxfemp: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::intknepmis: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::inepnakeff: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::emptyintr: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::txfifoundrn: 1
 
+uint32_t   _USB_OTG_DIEPINTn_TypeDef::Reserved08_31: 23
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   epdisabled: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   timeout: 1
 
+   uint32_t   intktxfemp: 1
 
+   uint32_t   intknepmis: 1
 
+   uint32_t   inepnakeff: 1
 
+   uint32_t   emptyintr: 1
 
+   uint32_t   txfifoundrn: 1
 
+   uint32_t   Reserved08_31: 23
 
} _USB_OTG_DIEPINTn_TypeDef::b
 
+uint32_t _USB_OTG_DOEPINTn_TypeDef::d32
 
+uint32_t   _USB_OTG_DOEPINTn_TypeDef::xfercompl: 1
 
+uint32_t   _USB_OTG_DOEPINTn_TypeDef::epdisabled: 1
 
+uint32_t   _USB_OTG_DOEPINTn_TypeDef::ahberr: 1
 
+uint32_t   _USB_OTG_DOEPINTn_TypeDef::setup: 1
 
+uint32_t   _USB_OTG_DOEPINTn_TypeDef::Reserved04_31: 28
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   epdisabled: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   setup: 1
 
+   uint32_t   Reserved04_31: 28
 
} _USB_OTG_DOEPINTn_TypeDef::b
 
+uint32_t _USB_OTG_DAINT_TypeDef::d32
 
+uint32_t   _USB_OTG_DAINT_TypeDef::in: 16
 
+uint32_t   _USB_OTG_DAINT_TypeDef::out: 16
 
+struct {
+   uint32_t   in: 16
 
+   uint32_t   out: 16
 
} _USB_OTG_DAINT_TypeDef::ep
 
+uint32_t _USB_OTG_DTHRCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::non_iso_thr_en: 1
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::iso_thr_en: 1
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::tx_thr_len: 9
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::Reserved11_15: 5
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::rx_thr_en: 1
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::rx_thr_len: 9
 
+uint32_t   _USB_OTG_DTHRCTL_TypeDef::Reserved26_31: 6
 
+struct {
+   uint32_t   non_iso_thr_en: 1
 
+   uint32_t   iso_thr_en: 1
 
+   uint32_t   tx_thr_len: 9
 
+   uint32_t   Reserved11_15: 5
 
+   uint32_t   rx_thr_en: 1
 
+   uint32_t   rx_thr_len: 9
 
+   uint32_t   Reserved26_31: 6
 
} _USB_OTG_DTHRCTL_TypeDef::b
 
+uint32_t _USB_OTG_DEPCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::mps: 11
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::reserved: 4
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::usbactep: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::dpid: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::naksts: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::eptype: 2
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::snp: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::stall: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::txfnum: 4
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::cnak: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::snak: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::setd0pid: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::setd1pid: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::epdis: 1
 
+uint32_t   _USB_OTG_DEPCTL_TypeDef::epena: 1
 
+struct {
+   uint32_t   mps: 11
 
+   uint32_t   reserved: 4
 
+   uint32_t   usbactep: 1
 
+   uint32_t   dpid: 1
 
+   uint32_t   naksts: 1
 
+   uint32_t   eptype: 2
 
+   uint32_t   snp: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   txfnum: 4
 
+   uint32_t   cnak: 1
 
+   uint32_t   snak: 1
 
+   uint32_t   setd0pid: 1
 
+   uint32_t   setd1pid: 1
 
+   uint32_t   epdis: 1
 
+   uint32_t   epena: 1
 
} _USB_OTG_DEPCTL_TypeDef::b
 
+uint32_t _USB_OTG_DEPXFRSIZ_TypeDef::d32
 
+uint32_t   _USB_OTG_DEPXFRSIZ_TypeDef::xfersize: 19
 
+uint32_t   _USB_OTG_DEPXFRSIZ_TypeDef::pktcnt: 10
 
+uint32_t   _USB_OTG_DEPXFRSIZ_TypeDef::mc: 2
 
+uint32_t   _USB_OTG_DEPXFRSIZ_TypeDef::Reserved: 1
 
+struct {
+   uint32_t   xfersize: 19
 
+   uint32_t   pktcnt: 10
 
+   uint32_t   mc: 2
 
+   uint32_t   Reserved: 1
 
} _USB_OTG_DEPXFRSIZ_TypeDef::b
 
+uint32_t _USB_OTG_DEP0XFRSIZ_TypeDef::d32
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::xfersize: 7
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::Reserved7_18: 12
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::pktcnt: 2
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::Reserved20_28: 9
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::supcnt: 2
 
+uint32_t   _USB_OTG_DEP0XFRSIZ_TypeDef::Reserved31
 
+struct {
+   uint32_t   xfersize: 7
 
+   uint32_t   Reserved7_18: 12
 
+   uint32_t   pktcnt: 2
 
+   uint32_t   Reserved20_28: 9
 
+   uint32_t   supcnt: 2
 
+   uint32_t   Reserved31
 
} _USB_OTG_DEP0XFRSIZ_TypeDef::b
 
+uint32_t _USB_OTG_HCFG_TypeDef::d32
 
+uint32_t   _USB_OTG_HCFG_TypeDef::fslspclksel: 2
 
+uint32_t   _USB_OTG_HCFG_TypeDef::fslssupp: 1
 
+struct {
+   uint32_t   fslspclksel: 2
 
+   uint32_t   fslssupp: 1
 
} _USB_OTG_HCFG_TypeDef::b
 
+uint32_t _USB_OTG_HFRMINTRVL_TypeDef::d32
 
+uint32_t   _USB_OTG_HFRMINTRVL_TypeDef::frint: 16
 
+uint32_t   _USB_OTG_HFRMINTRVL_TypeDef::Reserved: 16
 
+struct {
+   uint32_t   frint: 16
 
+   uint32_t   Reserved: 16
 
} _USB_OTG_HFRMINTRVL_TypeDef::b
 
+uint32_t _USB_OTG_HFNUM_TypeDef::d32
 
+uint32_t   _USB_OTG_HFNUM_TypeDef::frnum: 16
 
+uint32_t   _USB_OTG_HFNUM_TypeDef::frrem: 16
 
+struct {
+   uint32_t   frnum: 16
 
+   uint32_t   frrem: 16
 
} _USB_OTG_HFNUM_TypeDef::b
 
+uint32_t _USB_OTG_HPTXSTS_TypeDef::d32
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxfspcavail: 16
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxqspcavail: 8
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxqtop_terminate: 1
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxqtop_timer: 2
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxqtop: 2
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::chnum: 2
 
+uint32_t   _USB_OTG_HPTXSTS_TypeDef::ptxqtop_odd: 1
 
+struct {
+   uint32_t   ptxfspcavail: 16
 
+   uint32_t   ptxqspcavail: 8
 
+   uint32_t   ptxqtop_terminate: 1
 
+   uint32_t   ptxqtop_timer: 2
 
+   uint32_t   ptxqtop: 2
 
+   uint32_t   chnum: 2
 
+   uint32_t   ptxqtop_odd: 1
 
} _USB_OTG_HPTXSTS_TypeDef::b
 
+uint32_t _USB_OTG_HPRT0_TypeDef::d32
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtconnsts: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtconndet: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtena: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtenchng: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtovrcurract: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtovrcurrchng: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtres: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtsusp: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtrst: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::Reserved9: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtlnsts: 2
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtpwr: 1
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prttstctl: 4
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::prtspd: 2
 
+uint32_t   _USB_OTG_HPRT0_TypeDef::Reserved19_31: 13
 
+struct {
+   uint32_t   prtconnsts: 1
 
+   uint32_t   prtconndet: 1
 
+   uint32_t   prtena: 1
 
+   uint32_t   prtenchng: 1
 
+   uint32_t   prtovrcurract: 1
 
+   uint32_t   prtovrcurrchng: 1
 
+   uint32_t   prtres: 1
 
+   uint32_t   prtsusp: 1
 
+   uint32_t   prtrst: 1
 
+   uint32_t   Reserved9: 1
 
+   uint32_t   prtlnsts: 2
 
+   uint32_t   prtpwr: 1
 
+   uint32_t   prttstctl: 4
 
+   uint32_t   prtspd: 2
 
+   uint32_t   Reserved19_31: 13
 
} _USB_OTG_HPRT0_TypeDef::b
 
+uint32_t _USB_OTG_HAINT_TypeDef::d32
 
+uint32_t   _USB_OTG_HAINT_TypeDef::chint: 16
 
+uint32_t   _USB_OTG_HAINT_TypeDef::Reserved: 16
 
+struct {
+   uint32_t   chint: 16
 
+   uint32_t   Reserved: 16
 
} _USB_OTG_HAINT_TypeDef::b
 
+uint32_t _USB_OTG_HAINTMSK_TypeDef::d32
 
+uint32_t   _USB_OTG_HAINTMSK_TypeDef::chint: 16
 
+uint32_t   _USB_OTG_HAINTMSK_TypeDef::Reserved: 16
 
+struct {
+   uint32_t   chint: 16
 
+   uint32_t   Reserved: 16
 
} _USB_OTG_HAINTMSK_TypeDef::b
 
+uint32_t _USB_OTG_HCCHAR_TypeDef::d32
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::mps: 11
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::epnum: 4
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::epdir: 1
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::Reserved: 1
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::lspddev: 1
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::eptype: 2
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::multicnt: 2
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::devaddr: 7
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::oddfrm: 1
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::chdis: 1
 
+uint32_t   _USB_OTG_HCCHAR_TypeDef::chen: 1
 
+struct {
+   uint32_t   mps: 11
 
+   uint32_t   epnum: 4
 
+   uint32_t   epdir: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   lspddev: 1
 
+   uint32_t   eptype: 2
 
+   uint32_t   multicnt: 2
 
+   uint32_t   devaddr: 7
 
+   uint32_t   oddfrm: 1
 
+   uint32_t   chdis: 1
 
+   uint32_t   chen: 1
 
} _USB_OTG_HCCHAR_TypeDef::b
 
+uint32_t _USB_OTG_HCSPLT_TypeDef::d32
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::prtaddr: 7
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::hubaddr: 7
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::xactpos: 2
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::compsplt: 1
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::Reserved: 14
 
+uint32_t   _USB_OTG_HCSPLT_TypeDef::spltena: 1
 
+struct {
+   uint32_t   prtaddr: 7
 
+   uint32_t   hubaddr: 7
 
+   uint32_t   xactpos: 2
 
+   uint32_t   compsplt: 1
 
+   uint32_t   Reserved: 14
 
+   uint32_t   spltena: 1
 
} _USB_OTG_HCSPLT_TypeDef::b
 
+uint32_t _USB_OTG_HCINTn_TypeDef::d32
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::xfercompl: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::chhltd: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::ahberr: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::stall: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::nak: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::ack: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::nyet: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::xacterr: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::bblerr: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::frmovrun: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::datatglerr: 1
 
+uint32_t   _USB_OTG_HCINTn_TypeDef::Reserved: 21
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   chhltd: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   nak: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   nyet: 1
 
+   uint32_t   xacterr: 1
 
+   uint32_t   bblerr: 1
 
+   uint32_t   frmovrun: 1
 
+   uint32_t   datatglerr: 1
 
+   uint32_t   Reserved: 21
 
} _USB_OTG_HCINTn_TypeDef::b
 
+uint32_t _USB_OTG_HCTSIZn_TypeDef::d32
 
+uint32_t   _USB_OTG_HCTSIZn_TypeDef::xfersize: 19
 
+uint32_t   _USB_OTG_HCTSIZn_TypeDef::pktcnt: 10
 
+uint32_t   _USB_OTG_HCTSIZn_TypeDef::pid: 2
 
+uint32_t   _USB_OTG_HCTSIZn_TypeDef::dopng: 1
 
+struct {
+   uint32_t   xfersize: 19
 
+   uint32_t   pktcnt: 10
 
+   uint32_t   pid: 2
 
+   uint32_t   dopng: 1
 
} _USB_OTG_HCTSIZn_TypeDef::b
 
+uint32_t _USB_OTG_HCGINTMSK_TypeDef::d32
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::xfercompl: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::chhltd: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::ahberr: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::stall: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::nak: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::ack: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::nyet: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::xacterr: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::bblerr: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::frmovrun: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::datatglerr: 1
 
+uint32_t   _USB_OTG_HCGINTMSK_TypeDef::Reserved: 21
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   chhltd: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   nak: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   nyet: 1
 
+   uint32_t   xacterr: 1
 
+   uint32_t   bblerr: 1
 
+   uint32_t   frmovrun: 1
 
+   uint32_t   datatglerr: 1
 
+   uint32_t   Reserved: 21
 
} _USB_OTG_HCGINTMSK_TypeDef::b
 
+uint32_t _USB_OTG_PCGCCTL_TypeDef::d32
 
+uint32_t   _USB_OTG_PCGCCTL_TypeDef::stoppclk: 1
 
+uint32_t   _USB_OTG_PCGCCTL_TypeDef::gatehclk: 1
 
+uint32_t   _USB_OTG_PCGCCTL_TypeDef::Reserved: 30
 
+struct {
+   uint32_t   stoppclk: 1
 
+   uint32_t   gatehclk: 1
 
+   uint32_t   Reserved: 30
 
} _USB_OTG_PCGCCTL_TypeDef::b
 
+

Detailed Description

+

< ARM Compiler

+

< IAR Compiler

+

< GNU Compiler

+

< TASKING Compiler

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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___o_t_g___d_r_i_v_e_r.map b/group___u_s_b___o_t_g___d_r_i_v_e_r.map new file mode 100644 index 0000000..61accc9 --- /dev/null +++ b/group___u_s_b___o_t_g___d_r_i_v_e_r.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group___u_s_b___o_t_g___d_r_i_v_e_r.md5 b/group___u_s_b___o_t_g___d_r_i_v_e_r.md5 new file mode 100644 index 0000000..152e6fe --- /dev/null +++ b/group___u_s_b___o_t_g___d_r_i_v_e_r.md5 @@ -0,0 +1 @@ +75685e94dc3b6b3d6f4ebca689006e9d \ No newline at end of file diff --git a/group___u_s_b___o_t_g___d_r_i_v_e_r.png b/group___u_s_b___o_t_g___d_r_i_v_e_r.png new file mode 100644 index 0000000..60d8645 Binary files /dev/null and b/group___u_s_b___o_t_g___d_r_i_v_e_r.png differ diff --git a/group___u_s_b___r_e_g_s.html b/group___u_s_b___r_e_g_s.html new file mode 100644 index 0000000..cf7ff3e --- /dev/null +++ b/group___u_s_b___r_e_g_s.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: USB_REGS + + + + + + + + + + +
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USB_REGS
USB_OTG_DRIVER
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+Modules

 USB_REGS_Exported_Defines
 
 USB_REGS_Exported_Types
 
+

Detailed Description

+

This file is the.

+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___r_e_g_s.map b/group___u_s_b___r_e_g_s.map new file mode 100644 index 0000000..13c8ced --- /dev/null +++ b/group___u_s_b___r_e_g_s.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___u_s_b___r_e_g_s.md5 b/group___u_s_b___r_e_g_s.md5 new file mode 100644 index 0000000..07dd8d5 --- /dev/null +++ b/group___u_s_b___r_e_g_s.md5 @@ -0,0 +1 @@ +e3ace44e1634d88066a81863a9e79da4 \ No newline at end of file diff --git a/group___u_s_b___r_e_g_s.png b/group___u_s_b___r_e_g_s.png new file mode 100644 index 0000000..511f9f9 Binary files /dev/null and b/group___u_s_b___r_e_g_s.png differ diff --git a/group___u_s_b___r_e_g_s___exported___defines.html b/group___u_s_b___r_e_g_s___exported___defines.html new file mode 100644 index 0000000..7f80201 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___defines.html @@ -0,0 +1,160 @@ + + + + + + +discoverpixy: USB_REGS_Exported_Defines + + + + + + + + + + +
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USB_REGS_Exported_Defines
USB_OTG_DRIVER » USB_REGS
+
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+Collaboration diagram for USB_REGS_Exported_Defines:
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USB_OTG_HS_BASE_ADDR   0x40040000
 
+#define USB_OTG_FS_BASE_ADDR   0x50000000
 
+#define USB_OTG_CORE_GLOBAL_REGS_OFFSET   0x000
 
+#define USB_OTG_DEV_GLOBAL_REG_OFFSET   0x800
 
+#define USB_OTG_DEV_IN_EP_REG_OFFSET   0x900
 
+#define USB_OTG_EP_REG_OFFSET   0x20
 
+#define USB_OTG_DEV_OUT_EP_REG_OFFSET   0xB00
 
+#define USB_OTG_HOST_GLOBAL_REG_OFFSET   0x400
 
+#define USB_OTG_HOST_PORT_REGS_OFFSET   0x440
 
+#define USB_OTG_HOST_CHAN_REGS_OFFSET   0x500
 
+#define USB_OTG_CHAN_REGS_OFFSET   0x20
 
+#define USB_OTG_PCGCCTL_OFFSET   0xE00
 
+#define USB_OTG_DATA_FIFO_OFFSET   0x1000
 
+#define USB_OTG_DATA_FIFO_SIZE   0x1000
 
+#define USB_OTG_MAX_TX_FIFOS   15
 
+#define USB_OTG_HS_MAX_PACKET_SIZE   512
 
+#define USB_OTG_FS_MAX_PACKET_SIZE   64
 
+#define USB_OTG_MAX_EP0_SIZE   64
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___r_e_g_s___exported___defines.map b/group___u_s_b___r_e_g_s___exported___defines.map new file mode 100644 index 0000000..95b5d14 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___r_e_g_s___exported___defines.md5 b/group___u_s_b___r_e_g_s___exported___defines.md5 new file mode 100644 index 0000000..5f7452f --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___defines.md5 @@ -0,0 +1 @@ +a26804aadb6ccf17da726ca97e3561c8 \ No newline at end of file diff --git a/group___u_s_b___r_e_g_s___exported___defines.png b/group___u_s_b___r_e_g_s___exported___defines.png new file mode 100644 index 0000000..04eb82e Binary files /dev/null and b/group___u_s_b___r_e_g_s___exported___defines.png differ diff --git a/group___u_s_b___r_e_g_s___exported___functions_prototype.html b/group___u_s_b___r_e_g_s___exported___functions_prototype.html new file mode 100644 index 0000000..8bbe143 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___functions_prototype.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_REGS_Exported_FunctionsPrototype + + + + + + + + + + +
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USB_REGS_Exported_FunctionsPrototype
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
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+Collaboration diagram for USB_REGS_Exported_FunctionsPrototype:
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USB_REGS_Exported_Macros
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
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USB_REGS_Exported_Types
USB_OTG_DRIVER » USB_REGS
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+Modules

 __USB_OTG_Core_register
 
 __device_Registers
 
 __IN_Endpoint-Specific_Register
 
 __OUT_Endpoint-Specific_Registers
 
 __Host_Mode_Register_Structures
 
 __Host_Channel_Specific_Registers
 
 __otg_Core_registers
 
 USB_REGS_Exported_Macros
 
 USB_REGS_Exported_Variables
 
 USB_REGS_Exported_FunctionsPrototype
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___r_e_g_s___exported___types.map b/group___u_s_b___r_e_g_s___exported___types.map new file mode 100644 index 0000000..ae02d68 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___types.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/group___u_s_b___r_e_g_s___exported___types.md5 b/group___u_s_b___r_e_g_s___exported___types.md5 new file mode 100644 index 0000000..72fdfcb --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___types.md5 @@ -0,0 +1 @@ +36f623b563a02f18bc7c151c1f46300e \ No newline at end of file diff --git a/group___u_s_b___r_e_g_s___exported___types.png b/group___u_s_b___r_e_g_s___exported___types.png new file mode 100644 index 0000000..ba8ae74 Binary files /dev/null and b/group___u_s_b___r_e_g_s___exported___types.png differ diff --git a/group___u_s_b___r_e_g_s___exported___variables.html b/group___u_s_b___r_e_g_s___exported___variables.html new file mode 100644 index 0000000..b721ef4 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USB_REGS_Exported_Variables + + + + + + + + + + +
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USB_REGS_Exported_Variables
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types
+
+
+
+Collaboration diagram for USB_REGS_Exported_Variables:
+
+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b___r_e_g_s___exported___variables.map b/group___u_s_b___r_e_g_s___exported___variables.map new file mode 100644 index 0000000..cf12fd8 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b___r_e_g_s___exported___variables.md5 b/group___u_s_b___r_e_g_s___exported___variables.md5 new file mode 100644 index 0000000..0d72658 --- /dev/null +++ b/group___u_s_b___r_e_g_s___exported___variables.md5 @@ -0,0 +1 @@ +095fdd779ddc277ddd51852c2b3e9ee1 \ No newline at end of file diff --git a/group___u_s_b___r_e_g_s___exported___variables.png b/group___u_s_b___r_e_g_s___exported___variables.png new file mode 100644 index 0000000..213b836 Binary files /dev/null and b/group___u_s_b___r_e_g_s___exported___variables.png differ diff --git a/group___u_s_b_h___c_l_a_s_s.html b/group___u_s_b_h___c_l_a_s_s.html new file mode 100644 index 0000000..6dbd9d4 --- /dev/null +++ b/group___u_s_b_h___c_l_a_s_s.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: USBH_CLASS + + + + + + + + + + +
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discoverpixy +
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+Modules
+
+
USBH_CLASS
USBH_LIB
+
+
+
+Collaboration diagram for USBH_CLASS:
+
+
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+
+ + + + + + +

+Modules

 USBH_HID_CLASS
 
 USBH_MSC_CLASS
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_l_a_s_s.map b/group___u_s_b_h___c_l_a_s_s.map new file mode 100644 index 0000000..04bb23a --- /dev/null +++ b/group___u_s_b_h___c_l_a_s_s.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___u_s_b_h___c_l_a_s_s.md5 b/group___u_s_b_h___c_l_a_s_s.md5 new file mode 100644 index 0000000..925b6ac --- /dev/null +++ b/group___u_s_b_h___c_l_a_s_s.md5 @@ -0,0 +1 @@ +d5e86402f42bffc92b65edb251cdde8d \ No newline at end of file diff --git a/group___u_s_b_h___c_l_a_s_s.png b/group___u_s_b_h___c_l_a_s_s.png new file mode 100644 index 0000000..4bb1d19 Binary files /dev/null and b/group___u_s_b_h___c_l_a_s_s.png differ diff --git a/group___u_s_b_h___c_o_n_f.html b/group___u_s_b_h___c_o_n_f.html new file mode 100644 index 0000000..4a242b1 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: USBH_CONF + + + + + + + + + + +
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+Modules
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USBH_CONF
USBH_OTG_DRIVER
+
+
+ +

usb otg low level driver configuration file +More...

+
+Collaboration diagram for USBH_CONF:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Modules

 USBH_CONF_Exported_Defines
 
 USBH_CONF_Exported_Types
 
 USBH_CONF_Exported_Macros
 
 USBH_CONF_Exported_Variables
 
 USBH_CONF_Exported_FunctionsPrototype
 
+

Detailed Description

+

usb otg low level driver configuration file

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f.map b/group___u_s_b_h___c_o_n_f.map new file mode 100644 index 0000000..7790181 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___u_s_b_h___c_o_n_f.md5 b/group___u_s_b_h___c_o_n_f.md5 new file mode 100644 index 0000000..1b370da --- /dev/null +++ b/group___u_s_b_h___c_o_n_f.md5 @@ -0,0 +1 @@ +ab48e234bdcd665a725f393b5fd90271 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f.png b/group___u_s_b_h___c_o_n_f.png new file mode 100644 index 0000000..ab86028 Binary files /dev/null and b/group___u_s_b_h___c_o_n_f.png differ diff --git a/group___u_s_b_h___c_o_n_f___exported___defines.html b/group___u_s_b_h___c_o_n_f___exported___defines.html new file mode 100644 index 0000000..6322c28 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___defines.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: USBH_CONF_Exported_Defines + + + + + + + + + + +
+
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discoverpixy +
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+Macros
+
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USBH_CONF_Exported_Defines
USBH_OTG_DRIVER » USBH_CONF
+
+
+
+Collaboration diagram for USBH_CONF_Exported_Defines:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Macros

+#define USBH_MAX_NUM_ENDPOINTS   2
 
+#define USBH_MAX_NUM_INTERFACES   2
 
+#define USBH_MSC_MPS_SIZE   0x200
 
+#define USBH_MAX_NUM_ENDPOINTS   2
 
+#define USBH_MAX_NUM_INTERFACES   2
 
+#define USBH_MSC_MPS_SIZE   0x200
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f___exported___defines.map b/group___u_s_b_h___c_o_n_f___exported___defines.map new file mode 100644 index 0000000..debbba4 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_n_f___exported___defines.md5 b/group___u_s_b_h___c_o_n_f___exported___defines.md5 new file mode 100644 index 0000000..9088919 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___defines.md5 @@ -0,0 +1 @@ +3364a4102e89244dbd086df510d2db56 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f___exported___defines.png b/group___u_s_b_h___c_o_n_f___exported___defines.png new file mode 100644 index 0000000..c4fd813 Binary files /dev/null and b/group___u_s_b_h___c_o_n_f___exported___defines.png differ diff --git a/group___u_s_b_h___c_o_n_f___exported___functions_prototype.html b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.html new file mode 100644 index 0000000..f3e57e7 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CONF_Exported_FunctionsPrototype + + + + + + + + + + +
+
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+
discoverpixy +
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+
USBH_CONF_Exported_FunctionsPrototype
USBH_OTG_DRIVER » USBH_CONF
+
+
+
+Collaboration diagram for USBH_CONF_Exported_FunctionsPrototype:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f___exported___functions_prototype.map b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.map new file mode 100644 index 0000000..410560d --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_n_f___exported___functions_prototype.md5 b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.md5 new file mode 100644 index 0000000..bbdaeeb --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.md5 @@ -0,0 +1 @@ +1553a535f0ee1f4e63386f2187d98c82 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f___exported___functions_prototype.png b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.png new file mode 100644 index 0000000..b7624b0 Binary files /dev/null and b/group___u_s_b_h___c_o_n_f___exported___functions_prototype.png differ diff --git a/group___u_s_b_h___c_o_n_f___exported___macros.html b/group___u_s_b_h___c_o_n_f___exported___macros.html new file mode 100644 index 0000000..d8235a6 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CONF_Exported_Macros + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+
USBH_CONF_Exported_Macros
USBH_OTG_DRIVER » USBH_CONF
+
+
+
+Collaboration diagram for USBH_CONF_Exported_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f___exported___macros.map b/group___u_s_b_h___c_o_n_f___exported___macros.map new file mode 100644 index 0000000..93b68ff --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_n_f___exported___macros.md5 b/group___u_s_b_h___c_o_n_f___exported___macros.md5 new file mode 100644 index 0000000..aa02f0d --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___macros.md5 @@ -0,0 +1 @@ +621eb5fe662d3ea782ef7b6f48e86270 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f___exported___macros.png b/group___u_s_b_h___c_o_n_f___exported___macros.png new file mode 100644 index 0000000..539adb4 Binary files /dev/null and b/group___u_s_b_h___c_o_n_f___exported___macros.png differ diff --git a/group___u_s_b_h___c_o_n_f___exported___types.html b/group___u_s_b_h___c_o_n_f___exported___types.html new file mode 100644 index 0000000..7e418ff --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CONF_Exported_Types + + + + + + + + + + +
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discoverpixy +
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USBH_CONF_Exported_Types
USBH_OTG_DRIVER » USBH_CONF
+
+
+
+Collaboration diagram for USBH_CONF_Exported_Types:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f___exported___types.map b/group___u_s_b_h___c_o_n_f___exported___types.map new file mode 100644 index 0000000..862c228 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_n_f___exported___types.md5 b/group___u_s_b_h___c_o_n_f___exported___types.md5 new file mode 100644 index 0000000..154e3da --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___types.md5 @@ -0,0 +1 @@ +e13e90d160216316a6cc6f4102ba880a \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f___exported___types.png b/group___u_s_b_h___c_o_n_f___exported___types.png new file mode 100644 index 0000000..ed79e3c Binary files /dev/null and b/group___u_s_b_h___c_o_n_f___exported___types.png differ diff --git a/group___u_s_b_h___c_o_n_f___exported___variables.html b/group___u_s_b_h___c_o_n_f___exported___variables.html new file mode 100644 index 0000000..4e41ddf --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CONF_Exported_Variables + + + + + + + + + + +
+
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discoverpixy +
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USBH_CONF_Exported_Variables
USBH_OTG_DRIVER » USBH_CONF
+
+
+
+Collaboration diagram for USBH_CONF_Exported_Variables:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_n_f___exported___variables.map b/group___u_s_b_h___c_o_n_f___exported___variables.map new file mode 100644 index 0000000..5c74416 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_n_f___exported___variables.md5 b/group___u_s_b_h___c_o_n_f___exported___variables.md5 new file mode 100644 index 0000000..982bb30 --- /dev/null +++ b/group___u_s_b_h___c_o_n_f___exported___variables.md5 @@ -0,0 +1 @@ +ef0e8ad9ad5594842b9d0b643078acc6 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_n_f___exported___variables.png b/group___u_s_b_h___c_o_n_f___exported___variables.png new file mode 100644 index 0000000..82fbeb1 Binary files /dev/null and b/group___u_s_b_h___c_o_n_f___exported___variables.png differ diff --git a/group___u_s_b_h___c_o_r_e.html b/group___u_s_b_h___c_o_r_e.html new file mode 100644 index 0000000..a33f3d3 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_CORE + + + + + + + + + + +
+
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discoverpixy +
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+Modules
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USBH_CORE
USBH_LIB » USBH_LIB_CORE
+
+
+ +

This file is the Header file for usbh_core.c. +More...

+
+Collaboration diagram for USBH_CORE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_CORE_Exported_Defines
 
 USBH_CORE_Exported_Types
 
 USBH_CORE_Exported_Macros
 
 USBH_CORE_Exported_Variables
 
 USBH_CORE_Exported_FunctionsPrototype
 
 USBH_CORE_Private_TypesDefinitions
 
 USBH_CORE_Private_Defines
 
 USBH_CORE_Private_Macros
 
 USBH_CORE_Private_Variables
 
 USBH_CORE_Private_FunctionPrototypes
 
 USBH_CORE_Private_Functions
 
+

Detailed Description

+

This file is the Header file for usbh_core.c.

+

TThis file handles the basic enumaration when a device is connected to the host.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_r_e.map b/group___u_s_b_h___c_o_r_e.map new file mode 100644 index 0000000..1d7fb1c --- /dev/null +++ b/group___u_s_b_h___c_o_r_e.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___c_o_r_e.md5 b/group___u_s_b_h___c_o_r_e.md5 new file mode 100644 index 0000000..f0ebf71 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e.md5 @@ -0,0 +1 @@ +b1c14362cab555cb906844d09d2cec99 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_r_e.png b/group___u_s_b_h___c_o_r_e.png new file mode 100644 index 0000000..4eb272f Binary files /dev/null and b/group___u_s_b_h___c_o_r_e.png differ diff --git a/group___u_s_b_h___c_o_r_e___exported___defines.html b/group___u_s_b_h___c_o_r_e___exported___defines.html new file mode 100644 index 0000000..e0c08c4 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___defines.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: USBH_CORE_Exported_Defines + + + + + + + + + + +
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discoverpixy +
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+Macros
+
+
USBH_CORE_Exported_Defines
USBH_LIB » USBH_LIB_CORE » USBH_CORE
+
+
+
+Collaboration diagram for USBH_CORE_Exported_Defines:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define MSC_CLASS   0x08
 
+#define HID_CLASS   0x03
 
+#define MSC_PROTOCOL   0x50
 
+#define CBI_PROTOCOL   0x01
 
+#define USBH_MAX_ERROR_COUNT   2
 
+#define USBH_DEVICE_ADDRESS_DEFAULT   0
 
+#define USBH_DEVICE_ADDRESS   1
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_r_e___exported___defines.map b/group___u_s_b_h___c_o_r_e___exported___defines.map new file mode 100644 index 0000000..b207773 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_r_e___exported___defines.md5 b/group___u_s_b_h___c_o_r_e___exported___defines.md5 new file mode 100644 index 0000000..548f3be --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___defines.md5 @@ -0,0 +1 @@ +6827ad1446d090d2a44182db68880cd0 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_r_e___exported___defines.png b/group___u_s_b_h___c_o_r_e___exported___defines.png new file mode 100644 index 0000000..28173e3 Binary files /dev/null and b/group___u_s_b_h___c_o_r_e___exported___defines.png differ diff --git a/group___u_s_b_h___c_o_r_e___exported___functions_prototype.html b/group___u_s_b_h___c_o_r_e___exported___functions_prototype.html new file mode 100644 index 0000000..8a10fae --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___functions_prototype.html @@ -0,0 +1,343 @@ + + + + + + +discoverpixy: USBH_CORE_Exported_FunctionsPrototype + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + +
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+Functions
+
+
USBH_CORE_Exported_FunctionsPrototype
USBH_LIB » USBH_LIB_CORE » USBH_CORE
+
+
+
+Collaboration diagram for USBH_CORE_Exported_FunctionsPrototype:
+
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+ + + + + + + + + + + + + + +

+Functions

void USBH_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb)
 USBH_Init Host hardware and stack initializations. More...
 
USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_DeInit Re-Initialize Host. More...
 
void USBH_Process (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_Process USB Host core main state machine process. More...
 
void USBH_ErrorHandle (USBH_HOST *phost, USBH_Status errType)
 USBH_ErrorHandle This function handles the Error on Host side. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_DeInit Re-Initialize Host.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
statusUSBH_Status
+
+
+ +

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void USBH_ErrorHandle (USBH_HOST * phost,
USBH_Status errType 
)
+
+ +

USBH_ErrorHandle This function handles the Error on Host side.

+
Parameters
+ + +
errType: Type of Error or Busy/OK state
+
+
+
Return values
+ + +
None
+
+
+ +

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void USBH_Init (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID,
USBH_HOST * phost,
USBH_Class_cb_TypeDef * class_cb,
USBH_Usr_cb_TypeDef * usr_cb 
)
+
+ +

USBH_Init Host hardware and stack initializations.

+
Parameters
+ + + +
class_cbClass callback structure address
usr_cbUser callback structure address
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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+ + +
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void USBH_Process (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_Process USB Host core main state machine process.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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-0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CORE_Exported_Macros + + + + + + + + + + +
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USBH_CORE_Exported_Macros
USBH_LIB » USBH_LIB_CORE » USBH_CORE
+
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+
+Collaboration diagram for USBH_CORE_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_r_e___exported___macros.map b/group___u_s_b_h___c_o_r_e___exported___macros.map new file mode 100644 index 0000000..52be7bc --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_r_e___exported___macros.md5 b/group___u_s_b_h___c_o_r_e___exported___macros.md5 new file mode 100644 index 0000000..ac0c379 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___macros.md5 @@ -0,0 +1 @@ +12fcae263c09740b98c354d050aa7431 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_r_e___exported___macros.png b/group___u_s_b_h___c_o_r_e___exported___macros.png new file mode 100644 index 0000000..dfc5996 Binary files /dev/null and b/group___u_s_b_h___c_o_r_e___exported___macros.png differ diff --git a/group___u_s_b_h___c_o_r_e___exported___types.html b/group___u_s_b_h___c_o_r_e___exported___types.html new file mode 100644 index 0000000..3adf2c8 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___types.html @@ -0,0 +1,217 @@ + + + + + + +discoverpixy: USBH_CORE_Exported_Types + + + + + + + + + + +
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+Classes | +Typedefs | +Enumerations
+
+
USBH_CORE_Exported_Types
USBH_LIB » USBH_LIB_CORE » USBH_CORE
+
+
+
+Collaboration diagram for USBH_CORE_Exported_Types:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Classes

struct  _Ctrl
 
struct  _DeviceProp
 
struct  _USBH_Class_cb
 
struct  _USBH_USR_PROP
 
struct  _Host_TypeDef
 
+ + + + + + + + + + + + + +

+Typedefs

+typedef struct _Ctrl USBH_Ctrl_TypeDef
 
+typedef struct _DeviceProp USBH_Device_TypeDef
 
+typedef struct _USBH_Class_cb USBH_Class_cb_TypeDef
 
+typedef struct _USBH_USR_PROP USBH_Usr_cb_TypeDef
 
+typedef struct _Host_TypeDef USBH_HOST
 
+typedef struct _Host_TypeDef * pUSBH_HOST
 
+ + + + + + + + + + + + + +

+Enumerations

enum  USBH_Status {
+  USBH_OK = 0, +USBH_BUSY, +USBH_FAIL, +USBH_NOT_SUPPORTED, +
+  USBH_UNRECOVERED_ERROR, +USBH_ERROR_SPEED_UNKNOWN, +USBH_APPLY_DEINIT +
+ }
 
enum  HOST_State {
+  HOST_IDLE =0, +HOST_ISSUE_CORE_RESET, +HOST_DEV_ATTACHED, +HOST_DEV_DISCONNECTED, +
+  HOST_ISSUE_RESET, +HOST_DETECT_DEVICE_SPEED, +HOST_ENUMERATION, +HOST_CLASS_REQUEST, +
+  HOST_CLASS, +HOST_CTRL_XFER, +HOST_USR_INPUT, +HOST_SUSPENDED, +
+  HOST_ERROR_STATE +
+ }
 
enum  ENUM_State {
+  ENUM_IDLE = 0, +ENUM_GET_FULL_DEV_DESC, +ENUM_SET_ADDR, +ENUM_GET_CFG_DESC, +
+  ENUM_GET_FULL_CFG_DESC, +ENUM_GET_MFC_STRING_DESC, +ENUM_GET_PRODUCT_STRING_DESC, +ENUM_GET_SERIALNUM_STRING_DESC, +
+  ENUM_SET_CONFIGURATION, +ENUM_DEV_CONFIGURED +
+ }
 
enum  CTRL_State {
+  CTRL_IDLE =0, +CTRL_SETUP, +CTRL_SETUP_WAIT, +CTRL_DATA_IN, +
+  CTRL_DATA_IN_WAIT, +CTRL_DATA_OUT, +CTRL_DATA_OUT_WAIT, +CTRL_STATUS_IN, +
+  CTRL_STATUS_IN_WAIT, +CTRL_STATUS_OUT, +CTRL_STATUS_OUT_WAIT, +CTRL_ERROR +
+ }
 
enum  USBH_USR_Status { USBH_USR_NO_RESP = 0, +USBH_USR_RESP_OK = 1 + }
 
enum  CMD_State { CMD_IDLE =0, +CMD_SEND, +CMD_WAIT + }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_r_e___exported___types.map b/group___u_s_b_h___c_o_r_e___exported___types.map new file mode 100644 index 0000000..a567c5c --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_r_e___exported___types.md5 b/group___u_s_b_h___c_o_r_e___exported___types.md5 new file mode 100644 index 0000000..5653f06 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___types.md5 @@ -0,0 +1 @@ +58312409e2b2172e1d8078b76bc8678c \ No newline at end of file diff --git a/group___u_s_b_h___c_o_r_e___exported___types.png b/group___u_s_b_h___c_o_r_e___exported___types.png new file mode 100644 index 0000000..ae5238c Binary files /dev/null and b/group___u_s_b_h___c_o_r_e___exported___types.png differ diff --git a/group___u_s_b_h___c_o_r_e___exported___variables.html b/group___u_s_b_h___c_o_r_e___exported___variables.html new file mode 100644 index 0000000..8519a7f --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_CORE_Exported_Variables + + + + + + + + + + +
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USBH_CORE_Exported_Variables
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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+Collaboration diagram for USBH_CORE_Exported_Variables:
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USBH_CORE_Private_Defines
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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USBH_CORE_Private_FunctionPrototypes
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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Detailed Description

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USBH_CORE_Private_Functions
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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+Functions

void USBH_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb)
 USBH_Init Host hardware and stack initializations. More...
 
USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_DeInit Re-Initialize Host. More...
 
void USBH_Process (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_Process USB Host core main state machine process. More...
 
void USBH_ErrorHandle (USBH_HOST *phost, USBH_Status errType)
 USBH_ErrorHandle This function handles the Error on Host side. More...
 
void USBH_Connect (void *pdev)
 USBH_Connect USB Connect callback function from the Interrupt. More...
 
void USBH_Disconnect (void *pdev)
 USBH_Disconnect USB Disconnect callback function from the Interrupt. More...
 
USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_HandleControl Handles the USB control transfer state machine. More...
 
+

Detailed Description

+

Function Documentation

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void USBH_Connect (void * pdev)
+
+ +

USBH_Connect USB Connect callback function from the Interrupt.

+
Parameters
+ + +
selecteddevice
+
+
+
Return values
+ + +
none
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USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_DeInit Re-Initialize Host.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
statusUSBH_Status
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void USBH_Disconnect (void * pdev)
+
+ +

USBH_Disconnect USB Disconnect callback function from the Interrupt.

+
Parameters
+ + +
selecteddevice
+
+
+
Return values
+ + +
none
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void USBH_ErrorHandle (USBH_HOST * phost,
USBH_Status errType 
)
+
+ +

USBH_ErrorHandle This function handles the Error on Host side.

+
Parameters
+ + +
errType: Type of Error or Busy/OK state
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Return values
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None
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USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_HandleControl Handles the USB control transfer state machine.

+
Parameters
+ + +
pdevSelected device
+
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Return values
+ + +
Status
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void USBH_Init (USB_OTG_CORE_HANDLE * pdev,
USB_OTG_CORE_ID_TypeDef coreID,
USBH_HOST * phost,
USBH_Class_cb_TypeDef * class_cb,
USBH_Usr_cb_TypeDef * usr_cb 
)
+
+ +

USBH_Init Host hardware and stack initializations.

+
Parameters
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class_cbClass callback structure address
usr_cbUser callback structure address
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Return values
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None
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void USBH_Process (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_Process USB Host core main state machine process.

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Parameters
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None
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Return values
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None
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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USBH_CORE_Private_Macros
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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+Collaboration diagram for USBH_CORE_Private_Macros:
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+Variables
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USBH_CORE_Private_TypesDefinitions
USBH_LIB » USBH_LIB_CORE » USBH_CORE
+
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+Collaboration diagram for USBH_CORE_Private_TypesDefinitions:
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+Variables

USB_OTG_hPort_TypeDef USBH_DeviceConnStatus_cb
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
USB_OTG_hPort_TypeDef USBH_DeviceConnStatus_cb
+
+Initial value:
=
+
{
+
USBH_Disconnect,
+
USBH_Connect,
+
0,
+
0,
+
0,
+
0
+
}
+
USBH_Connect
void USBH_Connect(void *pdev)
USBH_Connect USB Connect callback function from the Interrupt.
Definition: usbh_core.c:111
+
USBH_Disconnect
void USBH_Disconnect(void *pdev)
USBH_Disconnect USB Disconnect callback function from the Interrupt.
Definition: usbh_core.c:125
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USBH_CORE_Private_Variables
USBH_LIB » USBH_LIB_CORE » USBH_CORE
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___c_o_r_e___private___variables.map b/group___u_s_b_h___c_o_r_e___private___variables.map new file mode 100644 index 0000000..33477a2 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___c_o_r_e___private___variables.md5 b/group___u_s_b_h___c_o_r_e___private___variables.md5 new file mode 100644 index 0000000..9806064 --- /dev/null +++ b/group___u_s_b_h___c_o_r_e___private___variables.md5 @@ -0,0 +1 @@ +1fedd1c8b512b33f9e9ea95e8f33c945 \ No newline at end of file diff --git a/group___u_s_b_h___c_o_r_e___private___variables.png b/group___u_s_b_h___c_o_r_e___private___variables.png new file mode 100644 index 0000000..d756661 Binary files /dev/null and b/group___u_s_b_h___c_o_r_e___private___variables.png differ diff --git a/group___u_s_b_h___d_e_f.html b/group___u_s_b_h___d_e_f.html new file mode 100644 index 0000000..49d5a23 --- /dev/null +++ b/group___u_s_b_h___d_e_f.html @@ -0,0 +1,353 @@ + + + + + + +discoverpixy: USBH_DEF + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Macros
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USBH_DEF
USBH_LIB » USBH_LIB_CORE
+
+
+ +

This file is includes USB descriptors. +More...

+
+Collaboration diagram for USBH_DEF:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USBH_NULL   ((void *)0)
 
+#define FALSE   0
 
+#define TRUE   1
 
+#define ValBit(VAR, POS)   (VAR & (1 << POS))
 
+#define SetBit(VAR, POS)   (VAR |= (1 << POS))
 
+#define ClrBit(VAR, POS)   (VAR &= ((1 << POS)^255))
 
#define LE16(addr)
 
+#define USB_LEN_DESC_HDR   0x02
 
+#define USB_LEN_DEV_DESC   0x12
 
+#define USB_LEN_CFG_DESC   0x09
 
+#define USB_LEN_IF_DESC   0x09
 
+#define USB_LEN_EP_DESC   0x07
 
+#define USB_LEN_OTG_DESC   0x03
 
+#define USB_LEN_SETUP_PKT   0x08
 
+#define USB_REQ_DIR_MASK   0x80
 
+#define USB_H2D   0x00
 
+#define USB_D2H   0x80
 
+#define USB_REQ_TYPE_STANDARD   0x00
 
+#define USB_REQ_TYPE_CLASS   0x20
 
+#define USB_REQ_TYPE_VENDOR   0x40
 
+#define USB_REQ_TYPE_RESERVED   0x60
 
+#define USB_REQ_RECIPIENT_DEVICE   0x00
 
+#define USB_REQ_RECIPIENT_INTERFACE   0x01
 
+#define USB_REQ_RECIPIENT_ENDPOINT   0x02
 
+#define USB_REQ_RECIPIENT_OTHER   0x03
 
+#define USB_REQ_GET_STATUS   0x00
 
+#define USB_REQ_CLEAR_FEATURE   0x01
 
+#define USB_REQ_SET_FEATURE   0x03
 
+#define USB_REQ_SET_ADDRESS   0x05
 
+#define USB_REQ_GET_DESCRIPTOR   0x06
 
+#define USB_REQ_SET_DESCRIPTOR   0x07
 
+#define USB_REQ_GET_CONFIGURATION   0x08
 
+#define USB_REQ_SET_CONFIGURATION   0x09
 
+#define USB_REQ_GET_INTERFACE   0x0A
 
+#define USB_REQ_SET_INTERFACE   0x0B
 
+#define USB_REQ_SYNCH_FRAME   0x0C
 
+#define USB_DESC_TYPE_DEVICE   1
 
+#define USB_DESC_TYPE_CONFIGURATION   2
 
+#define USB_DESC_TYPE_STRING   3
 
+#define USB_DESC_TYPE_INTERFACE   4
 
+#define USB_DESC_TYPE_ENDPOINT   5
 
+#define USB_DESC_TYPE_DEVICE_QUALIFIER   6
 
+#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION   7
 
+#define USB_DESC_TYPE_INTERFACE_POWER   8
 
+#define USB_DESC_TYPE_HID   0x21
 
+#define USB_DESC_TYPE_HID_REPORT   0x22
 
+#define USB_DEVICE_DESC_SIZE   18
 
+#define USB_CONFIGURATION_DESC_SIZE   9
 
+#define USB_HID_DESC_SIZE   9
 
+#define USB_INTERFACE_DESC_SIZE   9
 
+#define USB_ENDPOINT_DESC_SIZE   7
 
+#define USB_DESC_DEVICE   ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00)
 
+#define USB_DESC_CONFIGURATION   ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00)
 
+#define USB_DESC_STRING   ((USB_DESC_TYPE_STRING << 8) & 0xFF00)
 
+#define USB_DESC_INTERFACE   ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
 
+#define USB_DESC_ENDPOINT   ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
 
+#define USB_DESC_DEVICE_QUALIFIER   ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00)
 
+#define USB_DESC_OTHER_SPEED_CONFIGURATION   ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00)
 
+#define USB_DESC_INTERFACE_POWER   ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00)
 
+#define USB_DESC_HID_REPORT   ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00)
 
+#define USB_DESC_HID   ((USB_DESC_TYPE_HID << 8) & 0xFF00)
 
+#define USB_EP_TYPE_CTRL   0x00
 
+#define USB_EP_TYPE_ISOC   0x01
 
+#define USB_EP_TYPE_BULK   0x02
 
+#define USB_EP_TYPE_INTR   0x03
 
+#define USB_EP_DIR_OUT   0x00
 
+#define USB_EP_DIR_IN   0x80
 
+#define USB_EP_DIR_MSK   0x80
 
+#define USB_MSC_CLASS   0x08
 
+#define USB_HID_CLASS   0x03
 
+#define HID_BOOT_CODE   0x01
 
+#define HID_KEYBRD_BOOT_CODE   0x01
 
+#define HID_MOUSE_BOOT_CODE   0x02
 
+#define DATA_STAGE_TIMEOUT   5000
 
+#define NODATA_STAGE_TIMEOUT   50
 
+

Detailed Description

+

This file is includes USB descriptors.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define LE16( addr)
+
+Value:
(((u16)(*((u8 *)(addr))))\
+
+ (((u16)(*(((u8 *)(addr)) + 1))) << 8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___d_e_f.map b/group___u_s_b_h___d_e_f.map new file mode 100644 index 0000000..0d97323 --- /dev/null +++ b/group___u_s_b_h___d_e_f.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___d_e_f.md5 b/group___u_s_b_h___d_e_f.md5 new file mode 100644 index 0000000..82f723b --- /dev/null +++ b/group___u_s_b_h___d_e_f.md5 @@ -0,0 +1 @@ +16f06c187dd91223d011a5765de10d59 \ No newline at end of file diff --git a/group___u_s_b_h___d_e_f.png b/group___u_s_b_h___d_e_f.png new file mode 100644 index 0000000..940a090 Binary files /dev/null and b/group___u_s_b_h___d_e_f.png differ diff --git a/group___u_s_b_h___h_c_s.html b/group___u_s_b_h___h_c_s.html new file mode 100644 index 0000000..b9c04f0 --- /dev/null +++ b/group___u_s_b_h___h_c_s.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_HCS + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
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+
+ + +
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+ +
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+Modules
+
+
USBH_HCS
USBH_LIB » USBH_LIB_CORE
+
+
+ +

This file is the header file for usbh_hcs.c. +More...

+
+Collaboration diagram for USBH_HCS:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_HCS_Exported_Defines
 
 USBH_HCS_Exported_Types
 
 USBH_HCS_Exported_Macros
 
 USBH_HCS_Exported_Variables
 
 USBH_HCS_Exported_FunctionsPrototype
 
 USBH_HCS_Private_Defines
 
 USBH_HCS_Private_TypesDefinitions
 
 USBH_HCS_Private_Macros
 
 USBH_HCS_Private_Variables
 
 USBH_HCS_Private_FunctionPrototypes
 
 USBH_HCS_Private_Functions
 
+

Detailed Description

+

This file is the header file for usbh_hcs.c.

+

This file includes opening and closing host channels.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s.map b/group___u_s_b_h___h_c_s.map new file mode 100644 index 0000000..eb13223 --- /dev/null +++ b/group___u_s_b_h___h_c_s.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___h_c_s.md5 b/group___u_s_b_h___h_c_s.md5 new file mode 100644 index 0000000..d985c14 --- /dev/null +++ b/group___u_s_b_h___h_c_s.md5 @@ -0,0 +1 @@ +05874fc87396cdbe0a8c53f446ae8224 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s.png b/group___u_s_b_h___h_c_s.png new file mode 100644 index 0000000..b2f4ea0 Binary files /dev/null and b/group___u_s_b_h___h_c_s.png differ diff --git a/group___u_s_b_h___h_c_s___exported___defines.html b/group___u_s_b_h___h_c_s___exported___defines.html new file mode 100644 index 0000000..4ad73e7 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___defines.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: USBH_HCS_Exported_Defines + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
USBH_HCS_Exported_Defines
USBH_LIB » USBH_LIB_CORE » USBH_HCS
+
+
+
+Collaboration diagram for USBH_HCS_Exported_Defines:
+
+
+ + +
+
+ + + + + + + + + + + + +

+Macros

+#define HC_MAX   8
 
+#define HC_OK   0x0000
 
+#define HC_USED   0x8000
 
+#define HC_ERROR   0xFFFF
 
+#define HC_USED_MASK   0x7FFF
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___exported___defines.map b/group___u_s_b_h___h_c_s___exported___defines.map new file mode 100644 index 0000000..37c959e --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___exported___defines.md5 b/group___u_s_b_h___h_c_s___exported___defines.md5 new file mode 100644 index 0000000..50f5281 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___defines.md5 @@ -0,0 +1 @@ +535ce527902eb93e7531b6f5c143375c \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___exported___defines.png b/group___u_s_b_h___h_c_s___exported___defines.png new file mode 100644 index 0000000..a4025fb Binary files /dev/null and b/group___u_s_b_h___h_c_s___exported___defines.png differ diff --git a/group___u_s_b_h___h_c_s___exported___functions_prototype.html b/group___u_s_b_h___h_c_s___exported___functions_prototype.html new file mode 100644 index 0000000..eed87b0 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___functions_prototype.html @@ -0,0 +1,406 @@ + + + + + + +discoverpixy: USBH_HCS_Exported_FunctionsPrototype + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
USBH_HCS_Exported_FunctionsPrototype
USBH_LIB » USBH_LIB_CORE » USBH_HCS
+
+
+
+Collaboration diagram for USBH_HCS_Exported_FunctionsPrototype:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
 USBH_Alloc_Channel Allocate a new channel for the pipe. More...
 
uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
 USBH_Free_Pipe Free the USB host channel. More...
 
uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev)
 USBH_DeAllocate_AllChannel Free all USB host channel. More...
 
uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Open_Channel Open a pipe. More...
 
uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Modify_Channel Modify a pipe. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t ep_addr 
)
+
+ +

USBH_Alloc_Channel Allocate a new channel for the pipe.

+
Parameters
+ + +
ep_addrEnd point for which the channel to be allocated
+
+
+
Return values
+ + +
hc_numHost channel number
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_DeAllocate_AllChannel Free all USB host channel.

+
Parameters
+ + +
pdev: core instance
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t idx 
)
+
+ +

USBH_Free_Pipe Free the USB host channel.

+
Parameters
+ + +
idxChannel number to be freed
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the caller graph for this function:
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+

+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps 
)
+
+ +

USBH_Modify_Channel Modify a pipe.

+
Parameters
+ + + + + + + +
pdev: Selected device
hc_numHost channel Number
dev_addressUSB Device address allocated to attached device
speed: USB device speed (Full/Low)
ep_typeend point type (Bulk/int/ctl)
mpsmax pkt size
+
+
+
Return values
+ + +
Status
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps 
)
+
+ +

USBH_Open_Channel Open a pipe.

+
Parameters
+ + + + + + + +
pdev: Selected device
hc_numHost channel Number
dev_addressUSB Device address allocated to attached device
speed: USB device speed (Full/Low)
ep_typeend point type (Bulk/int/ctl)
mpsmax pkt size
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___exported___functions_prototype.map b/group___u_s_b_h___h_c_s___exported___functions_prototype.map new file mode 100644 index 0000000..b36d604 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___exported___functions_prototype.md5 b/group___u_s_b_h___h_c_s___exported___functions_prototype.md5 new file mode 100644 index 0000000..c488b5e --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___functions_prototype.md5 @@ -0,0 +1 @@ +b560c93437b280178bb023e140a7a5ab \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___exported___functions_prototype.png b/group___u_s_b_h___h_c_s___exported___functions_prototype.png new file mode 100644 index 0000000..70d3529 Binary files /dev/null and b/group___u_s_b_h___h_c_s___exported___functions_prototype.png differ diff --git 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USBH_HCS_Exported_Macros
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___exported___macros.map b/group___u_s_b_h___h_c_s___exported___macros.map new file mode 100644 index 0000000..db82bae --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___exported___macros.md5 b/group___u_s_b_h___h_c_s___exported___macros.md5 new file mode 100644 index 0000000..8bb3233 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___macros.md5 @@ -0,0 +1 @@ +5bd0703efe416f733addd62a637e3047 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___exported___macros.png b/group___u_s_b_h___h_c_s___exported___macros.png new file mode 100644 index 0000000..36ae84e Binary files /dev/null and b/group___u_s_b_h___h_c_s___exported___macros.png differ diff --git a/group___u_s_b_h___h_c_s___exported___types.html b/group___u_s_b_h___h_c_s___exported___types.html new file mode 100644 index 0000000..9be27e8 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HCS_Exported_Types + + + + + + + + + + +
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USBH_HCS_Exported_Types
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Exported_Types:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___exported___types.map b/group___u_s_b_h___h_c_s___exported___types.map new file mode 100644 index 0000000..acfa520 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___exported___types.md5 b/group___u_s_b_h___h_c_s___exported___types.md5 new file mode 100644 index 0000000..86b9aa2 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___types.md5 @@ -0,0 +1 @@ +eedb04f3586a04ac0fb689bcad83a51d \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___exported___types.png b/group___u_s_b_h___h_c_s___exported___types.png new file mode 100644 index 0000000..6e3c26c Binary files /dev/null and b/group___u_s_b_h___h_c_s___exported___types.png differ diff --git a/group___u_s_b_h___h_c_s___exported___variables.html b/group___u_s_b_h___h_c_s___exported___variables.html new file mode 100644 index 0000000..35a8c7d --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HCS_Exported_Variables + + + + + + + + + + +
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USBH_HCS_Exported_Variables
USBH_LIB » USBH_LIB_CORE » USBH_HCS
+
+
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+Collaboration diagram for USBH_HCS_Exported_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___exported___variables.map b/group___u_s_b_h___h_c_s___exported___variables.map new file mode 100644 index 0000000..5ac765e --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___exported___variables.md5 b/group___u_s_b_h___h_c_s___exported___variables.md5 new file mode 100644 index 0000000..8bb7579 --- /dev/null +++ b/group___u_s_b_h___h_c_s___exported___variables.md5 @@ -0,0 +1 @@ +835dc6fb1bfe4c23ad7fb699b4af3755 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___exported___variables.png b/group___u_s_b_h___h_c_s___exported___variables.png new file mode 100644 index 0000000..5bfed5f Binary files /dev/null and b/group___u_s_b_h___h_c_s___exported___variables.png differ diff --git a/group___u_s_b_h___h_c_s___private___defines.html b/group___u_s_b_h___h_c_s___private___defines.html new file mode 100644 index 0000000..f562d5b --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HCS_Private_Defines + + + + + + + + + + +
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USBH_HCS_Private_Defines
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_Defines:
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+ + diff --git a/group___u_s_b_h___h_c_s___private___defines.map b/group___u_s_b_h___h_c_s___private___defines.map new file mode 100644 index 0000000..f3d285d --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___private___defines.md5 b/group___u_s_b_h___h_c_s___private___defines.md5 new file mode 100644 index 0000000..3e368af --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___defines.md5 @@ -0,0 +1 @@ +5841044dedea3b038d365e4e6bb902c6 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___private___defines.png b/group___u_s_b_h___h_c_s___private___defines.png new file mode 100644 index 0000000..a498f2d Binary files /dev/null and b/group___u_s_b_h___h_c_s___private___defines.png differ diff --git a/group___u_s_b_h___h_c_s___private___function_prototypes.html b/group___u_s_b_h___h_c_s___private___function_prototypes.html new file mode 100644 index 0000000..a7d7912 --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USBH_HCS_Private_FunctionPrototypes + + + + + + + + + + +
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USBH_HCS_Private_FunctionPrototypes
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_FunctionPrototypes:
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Detailed Description

+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_c_s___private___function_prototypes.map b/group___u_s_b_h___h_c_s___private___function_prototypes.map new file mode 100644 index 0000000..638f39c --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___private___function_prototypes.md5 b/group___u_s_b_h___h_c_s___private___function_prototypes.md5 new file mode 100644 index 0000000..c1a6891 --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___function_prototypes.md5 @@ -0,0 +1 @@ +c623fc3f8a04fb00035be50c96628eb7 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___private___function_prototypes.png b/group___u_s_b_h___h_c_s___private___function_prototypes.png new file mode 100644 index 0000000..abb149c Binary files /dev/null and b/group___u_s_b_h___h_c_s___private___function_prototypes.png differ diff --git a/group___u_s_b_h___h_c_s___private___functions.html b/group___u_s_b_h___h_c_s___private___functions.html new file mode 100644 index 0000000..273dfe5 --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___functions.html @@ -0,0 +1,406 @@ + + + + + + +discoverpixy: USBH_HCS_Private_Functions + + + + + + + + + + +
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+Functions
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+
USBH_HCS_Private_Functions
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_Functions:
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+Functions

uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Open_Channel Open a pipe. More...
 
uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Modify_Channel Modify a pipe. More...
 
uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
 USBH_Alloc_Channel Allocate a new channel for the pipe. More...
 
uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
 USBH_Free_Pipe Free the USB host channel. More...
 
uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev)
 USBH_DeAllocate_AllChannel Free all USB host channel. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t ep_addr 
)
+
+ +

USBH_Alloc_Channel Allocate a new channel for the pipe.

+
Parameters
+ + +
ep_addrEnd point for which the channel to be allocated
+
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Return values
+ + +
hc_numHost channel number
+
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uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_DeAllocate_AllChannel Free all USB host channel.

+
Parameters
+ + +
pdev: core instance
+
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Return values
+ + +
Status
+
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uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t idx 
)
+
+ +

USBH_Free_Pipe Free the USB host channel.

+
Parameters
+ + +
idxChannel number to be freed
+
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Return values
+ + +
Status
+
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uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps 
)
+
+ +

USBH_Modify_Channel Modify a pipe.

+
Parameters
+ + + + + + + +
pdev: Selected device
hc_numHost channel Number
dev_addressUSB Device address allocated to attached device
speed: USB device speed (Full/Low)
ep_typeend point type (Bulk/int/ctl)
mpsmax pkt size
+
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Return values
+ + +
Status
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uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE * pdev,
uint8_t hc_num,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps 
)
+
+ +

USBH_Open_Channel Open a pipe.

+
Parameters
+ + + + + + + +
pdev: Selected device
hc_numHost channel Number
dev_addressUSB Device address allocated to attached device
speed: USB device speed (Full/Low)
ep_typeend point type (Bulk/int/ctl)
mpsmax pkt size
+
+
+
Return values
+ + +
Status
+
+
+ +

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_HCS_Private_Macros
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_Macros:
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USBH_HCS_Private_TypesDefinitions
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_TypesDefinitions:
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+ + diff --git a/group___u_s_b_h___h_c_s___private___types_definitions.map b/group___u_s_b_h___h_c_s___private___types_definitions.map new file mode 100644 index 0000000..bc0983b --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___private___types_definitions.md5 b/group___u_s_b_h___h_c_s___private___types_definitions.md5 new file mode 100644 index 0000000..321c9e3 --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___types_definitions.md5 @@ -0,0 +1 @@ +31597d5c063ecd627ad1810fd32b3b21 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___private___types_definitions.png b/group___u_s_b_h___h_c_s___private___types_definitions.png new file mode 100644 index 0000000..a366810 Binary files /dev/null and b/group___u_s_b_h___h_c_s___private___types_definitions.png differ diff --git a/group___u_s_b_h___h_c_s___private___variables.html b/group___u_s_b_h___h_c_s___private___variables.html new file mode 100644 index 0000000..32f26cc --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HCS_Private_Variables + + + + + + + + + + +
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USBH_HCS_Private_Variables
USBH_LIB » USBH_LIB_CORE » USBH_HCS
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+Collaboration diagram for USBH_HCS_Private_Variables:
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+ + diff --git a/group___u_s_b_h___h_c_s___private___variables.map b/group___u_s_b_h___h_c_s___private___variables.map new file mode 100644 index 0000000..63790d5 --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_c_s___private___variables.md5 b/group___u_s_b_h___h_c_s___private___variables.md5 new file mode 100644 index 0000000..3da714e --- /dev/null +++ b/group___u_s_b_h___h_c_s___private___variables.md5 @@ -0,0 +1 @@ +92f790638979a83bbc722834aaac7d92 \ No newline at end of file diff --git a/group___u_s_b_h___h_c_s___private___variables.png b/group___u_s_b_h___h_c_s___private___variables.png new file mode 100644 index 0000000..edcd54a Binary files /dev/null and b/group___u_s_b_h___h_c_s___private___variables.png differ diff --git a/group___u_s_b_h___h_i_d___c_l_a_s_s.html b/group___u_s_b_h___h_i_d___c_l_a_s_s.html new file mode 100644 index 0000000..50b4001 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_l_a_s_s.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_HID_CLASS + + + + + + + + + + +
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+Modules
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USBH_HID_CLASS
USBH_LIB » USBH_CLASS
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+Collaboration diagram for USBH_HID_CLASS:
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+Modules

 USBH_HID_CORE
 This file is the Header file for USBH_HID_CORE.c.
 
 USBH_HID_KEYBD
 This file is the Header file for USBH_HID_KEYBD.c.
 
 USBH_HID_MOUSE
 This file is the Header file for USBH_HID_MOUSE.c.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_l_a_s_s.map b/group___u_s_b_h___h_i_d___c_l_a_s_s.map new file mode 100644 index 0000000..5e7b521 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_l_a_s_s.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___u_s_b_h___h_i_d___c_l_a_s_s.md5 b/group___u_s_b_h___h_i_d___c_l_a_s_s.md5 new file mode 100644 index 0000000..e9b0703 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_l_a_s_s.md5 @@ -0,0 +1 @@ +6794a9dc8b4a6b3c6cb7d9c3d6349f91 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_l_a_s_s.png b/group___u_s_b_h___h_i_d___c_l_a_s_s.png new file mode 100644 index 0000000..3ba5b74 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_l_a_s_s.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e.html b/group___u_s_b_h___h_i_d___c_o_r_e.html new file mode 100644 index 0000000..a3c50e8 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_HID_CORE + + + + + + + + + + +
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+Modules
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USBH_HID_CORE
USBH_LIB » USBH_CLASS » USBH_HID_CLASS
+
+
+ +

This file is the Header file for USBH_HID_CORE.c. +More...

+
+Collaboration diagram for USBH_HID_CORE:
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+Modules

 USBH_HID_CORE_Exported_Types
 
 USBH_HID_CORE_Exported_Defines
 
 USBH_HID_CORE_Exported_Macros
 
 USBH_HID_CORE_Exported_Variables
 
 USBH_HID_CORE_Exported_FunctionsPrototype
 
 USBH_HID_CORE_Private_TypesDefinitions
 
 USBH_HID_CORE_Private_Defines
 
 USBH_HID_CORE_Private_Macros
 
 USBH_HID_CORE_Private_Variables
 
 USBH_HID_CORE_Private_FunctionPrototypes
 
 USBH_HID_CORE_Private_Functions
 
+

Detailed Description

+

This file is the Header file for USBH_HID_CORE.c.

+

This file includes HID Layer Handlers for USB Host HID class.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e.map b/group___u_s_b_h___h_i_d___c_o_r_e.map new file mode 100644 index 0000000..1fc35a7 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e.md5 b/group___u_s_b_h___h_i_d___c_o_r_e.md5 new file mode 100644 index 0000000..a92eb10 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e.md5 @@ -0,0 +1 @@ +89053b37b8a8ededd84a1f69a2e5547e \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e.png b/group___u_s_b_h___h_i_d___c_o_r_e.png new file mode 100644 index 0000000..eca1fc2 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.html b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.html new file mode 100644 index 0000000..5f91403 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Exported_Defines + + + + + + + + + + +
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+Macros
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USBH_HID_CORE_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
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+Collaboration diagram for USBH_HID_CORE_Exported_Defines:
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+Macros

+#define USB_HID_REQ_GET_REPORT   0x01
 
+#define USB_HID_GET_IDLE   0x02
 
+#define USB_HID_GET_PROTOCOL   0x03
 
+#define USB_HID_SET_REPORT   0x09
 
+#define USB_HID_SET_IDLE   0x0A
 
+#define USB_HID_SET_PROTOCOL   0x0B
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.map new file mode 100644 index 0000000..fd4ffbb --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.md5 new file mode 100644 index 0000000..7eb0e94 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.md5 @@ -0,0 +1 @@ +f69bb80adabd9ec63545283704404202 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.png new file mode 100644 index 0000000..35e6bd3 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___defines.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.html b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.html new file mode 100644 index 0000000..e4c209e --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.html @@ -0,0 +1,187 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Exported_FunctionsPrototype + + + + + + + + + + +
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+Functions
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USBH_HID_CORE_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
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+Collaboration diagram for USBH_HID_CORE_Exported_FunctionsPrototype:
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+Functions

USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t *reportBuff)
 USBH_Set_Report Issues Set Report. More...
 
+

Detailed Description

+

Function Documentation

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USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t reportType,
uint8_t reportId,
uint8_t reportLen,
uint8_t * reportBuff 
)
+
+ +

USBH_Set_Report Issues Set Report.

+
Parameters
+ + + + + + +
pdevSelected device
reportType: Report type to be sent
reportID: Targetted report ID for Set Report request
reportLen: Length of data report to be send
reportBuff: Report Buffer
+
+
+
Return values
+ + +
USBH_Status: Response for USB Set Idle request
+
+
+ +

+Here is the call graph for this function:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.map new file mode 100644 index 0000000..0ecd2d3 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.md5 new file mode 100644 index 0000000..a8f390c --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.md5 @@ -0,0 +1 @@ +1ec83d1b4f76fd321b2016f25f3af017 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.png new file mode 100644 index 0000000..8209e33 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.map new file mode 100644 index 0000000..2c01034 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.md5 new file mode 100644 index 0000000..80ee306 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.md5 @@ -0,0 +1 @@ +61c4de5c99da0acc07f4476644e82700 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.png new file mode 100644 index 0000000..b5cce40 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___functions_prototype_gac10798074f64963bd6265f542bfce36e_cgraph.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.html b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.html new file mode 100644 index 0000000..eee12a6 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Exported_Macros + + + + + + + + + + +
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discoverpixy +
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USBH_HID_CORE_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Exported_Macros:
+
+
+ + +
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+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.map new file mode 100644 index 0000000..92ca5f2 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.md5 new file mode 100644 index 0000000..d9fa005 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.md5 @@ -0,0 +1 @@ +6c4d3d845f2a794af9405fb2e68d6b46 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.png new file mode 100644 index 0000000..c28b88b Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___macros.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.html b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.html new file mode 100644 index 0000000..30c90da --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Exported_Types + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Classes | +Typedefs | +Enumerations
+
+
USBH_HID_CORE_Exported_Types
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Exported_Types:
+
+
+ + +
+
+ + + + + + + + +

+Classes

struct  HID_cb
 
struct  _HID_Report
 
struct  _HID_Process
 
+ + + + + + + +

+Typedefs

+typedef struct HID_cb HID_cb_TypeDef
 
+typedef struct _HID_Report HID_Report_TypeDef
 
+typedef struct _HID_Process HID_Machine_TypeDef
 
+ + + + + +

+Enumerations

enum  HID_State {
+  HID_IDLE = 0, +HID_SEND_DATA, +HID_BUSY, +HID_GET_DATA, +
+  HID_POLL, +HID_ERROR +
+ }
 
enum  HID_CtlState {
+  HID_REQ_IDLE = 0, +HID_REQ_GET_REPORT_DESC, +HID_REQ_GET_HID_DESC, +HID_REQ_SET_IDLE, +
+  HID_REQ_SET_PROTOCOL, +HID_REQ_SET_REPORT +
+ }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.map new file mode 100644 index 0000000..0142e58 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.md5 new file mode 100644 index 0000000..15b4bc8 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.md5 @@ -0,0 +1 @@ +a99be56575a93c7a2b02c9773cda7940 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.png new file mode 100644 index 0000000..21c2b99 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___types.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.html b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.html new file mode 100644 index 0000000..87a3d6d --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Exported_Variables + + + + + + + + + + +
+
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+
discoverpixy +
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+Variables
+
+
USBH_HID_CORE_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Exported_Variables:
+
+
+ + +
+
+ + + + +

+Variables

+USBH_Class_cb_TypeDef HID_cb
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.map b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.map new file mode 100644 index 0000000..9f3b764 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.md5 new file mode 100644 index 0000000..be8fa01 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.md5 @@ -0,0 +1 @@ +e77848a7bc42348ce3607ae7716493e6 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.png b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.png new file mode 100644 index 0000000..25e72af Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___exported___variables.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.html new file mode 100644 index 0000000..647f88f --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_Defines + + + + + + + + + + +
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discoverpixy +
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USBH_HID_CORE_Private_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Private_Defines:
+
+
+ + +
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+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.map new file mode 100644 index 0000000..6fbfcc6 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.md5 new file mode 100644 index 0000000..260955a --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.md5 @@ -0,0 +1 @@ +7b9c1c0572ea8365c820aaa9991e22db \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.png new file mode 100644 index 0000000..a8824e8 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___defines.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.html new file mode 100644 index 0000000..284f31e --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_FunctionPrototypes + + + + + + + + + + +
+
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+
discoverpixy +
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+Variables
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USBH_HID_CORE_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Private_FunctionPrototypes:
+
+
+ + +
+
+ + + + +

+Variables

USBH_Class_cb_TypeDef HID_cb
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
USBH_Class_cb_TypeDef HID_cb
+
+Initial value:
=
+
{
+
USBH_HID_InterfaceInit,
+
USBH_HID_InterfaceDeInit,
+
USBH_HID_ClassRequest,
+
USBH_HID_Handle
+
}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.map new file mode 100644 index 0000000..9105450 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.md5 new file mode 100644 index 0000000..c00ac90 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.md5 @@ -0,0 +1 @@ +cc09d82d7848b4c36819166e5e1e9a0f \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.png new file mode 100644 index 0000000..0682b77 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___function_prototypes.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.html new file mode 100644 index 0000000..8f7b0dc --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.html @@ -0,0 +1,187 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_Functions + + + + + + + + + + +
+
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discoverpixy +
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+Functions
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+
USBH_HID_CORE_Private_Functions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Private_Functions:
+
+
+ + +
+
+ + + + + +

+Functions

USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t *reportBuff)
 USBH_Set_Report Issues Set Report. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t reportType,
uint8_t reportId,
uint8_t reportLen,
uint8_t * reportBuff 
)
+
+ +

USBH_Set_Report Issues Set Report.

+
Parameters
+ + + + + + +
pdevSelected device
reportType: Report type to be sent
reportID: Targetted report ID for Set Report request
reportLen: Length of data report to be send
reportBuff: Report Buffer
+
+
+
Return values
+ + +
USBH_Status: Response for USB Set Idle request
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.map new file mode 100644 index 0000000..5205d2b --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.md5 new file mode 100644 index 0000000..a37173a --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.md5 @@ -0,0 +1 @@ +76353efbff137f412573599a788899e9 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.png new file mode 100644 index 0000000..4503c98 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.map new file mode 100644 index 0000000..2c01034 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.md5 new file mode 100644 index 0000000..80ee306 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.md5 @@ -0,0 +1 @@ +61c4de5c99da0acc07f4476644e82700 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.png new file mode 100644 index 0000000..b5cce40 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___functions_gac10798074f64963bd6265f542bfce36e_cgraph.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.html new file mode 100644 index 0000000..04705da --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_Macros + + + + + + + + + + +
+
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+
discoverpixy +
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USBH_HID_CORE_Private_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
+
+
+
+Collaboration diagram for USBH_HID_CORE_Private_Macros:
+
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+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.map new file mode 100644 index 0000000..9e6c80b --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.md5 new file mode 100644 index 0000000..0f8dd41 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.md5 @@ -0,0 +1 @@ +81271ed8c8311d566cdca964c268ec03 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.png new file mode 100644 index 0000000..bb5ece2 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___macros.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.html new file mode 100644 index 0000000..30096cb --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_TypesDefinitions + + + + + + + + + + +
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USBH_HID_CORE_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
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+Collaboration diagram for USBH_HID_CORE_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.map new file mode 100644 index 0000000..e350bb0 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.md5 new file mode 100644 index 0000000..7be5bd0 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.md5 @@ -0,0 +1 @@ +e68d2783289e84cddaf3976fc043d2bc \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.png new file mode 100644 index 0000000..af71a26 Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___types_definitions.png differ diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.html b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.html new file mode 100644 index 0000000..bcfb5df --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_HID_CORE_Private_Variables + + + + + + + + + + +
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+Variables
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USBH_HID_CORE_Private_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE
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+Collaboration diagram for USBH_HID_CORE_Private_Variables:
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+Variables

+__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END
 
+__IO uint8_t flag = 0
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.map b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.map new file mode 100644 index 0000000..ad273a8 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.md5 b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.md5 new file mode 100644 index 0000000..2fd9782 --- /dev/null +++ b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.md5 @@ -0,0 +1 @@ +4070760d546d1b637229738bb59cbea3 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.png b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.png new file mode 100644 index 0000000..6d1e2dd Binary files /dev/null and b/group___u_s_b_h___h_i_d___c_o_r_e___private___variables.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d.html b/group___u_s_b_h___h_i_d___k_e_y_b_d.html new file mode 100644 index 0000000..3ebd710 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD + + + + + + + + + + +
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+Modules
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USBH_HID_KEYBD
USBH_LIB » USBH_CLASS » USBH_HID_CLASS
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+ +

This file is the Header file for USBH_HID_KEYBD.c. +More...

+
+Collaboration diagram for USBH_HID_KEYBD:
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+Modules

 USBH_HID_KEYBD_Exported_Types
 
 USBH_HID_KEYBD_Exported_Defines
 
 USBH_HID_KEYBD_Exported_Macros
 
 USBH_HID_KEYBD_Exported_Variables
 
 USBH_HID_KEYBD_Exported_FunctionsPrototype
 
 USBH_HID_KEYBD_Private_TypesDefinitions
 
 USBH_HID_KEYBD_Private_Defines
 
 USBH_HID_KEYBD_Private_Macros
 
 USBH_HID_KEYBD_Private_FunctionPrototypes
 
 USBH_HID_KEYBD_Private_Variables
 
 USBH_HID_KEYBD_Private_Functions
 
+

Detailed Description

+

This file is the Header file for USBH_HID_KEYBD.c.

+

This file includes HID Layer Handlers for USB Host HID class.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d.map b/group___u_s_b_h___h_i_d___k_e_y_b_d.map new file mode 100644 index 0000000..9de278d --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d.md5 new file mode 100644 index 0000000..3abab4f --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d.md5 @@ -0,0 +1 @@ +eb4fd05f4a27404125452886a0fe12b0 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d.png b/group___u_s_b_h___h_i_d___k_e_y_b_d.png new file mode 100644 index 0000000..92072e8 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.html new file mode 100644 index 0000000..b665d1b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Exported_Defines + + + + + + + + + + +
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+Macros
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USBH_HID_KEYBD_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
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+Collaboration diagram for USBH_HID_KEYBD_Exported_Defines:
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+Macros

+#define AZERTY_KEYBOARD
 
+#define KBD_LEFT_CTRL   0x01
 
+#define KBD_LEFT_SHIFT   0x02
 
+#define KBD_LEFT_ALT   0x04
 
+#define KBD_LEFT_GUI   0x08
 
+#define KBD_RIGHT_CTRL   0x10
 
+#define KBD_RIGHT_SHIFT   0x20
 
+#define KBD_RIGHT_ALT   0x40
 
+#define KBD_RIGHT_GUI   0x80
 
+#define KBR_MAX_NBR_PRESSED   6
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.map new file mode 100644 index 0000000..8f3d23b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.md5 new file mode 100644 index 0000000..af86071 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.md5 @@ -0,0 +1 @@ +e8977a4a63f1a639bdb3a1d8fedc3c8c \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.png new file mode 100644 index 0000000..2a25035 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___defines.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.html new file mode 100644 index 0000000..baf6d58 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Exported_FunctionsPrototype + + + + + + + + + + +
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+Functions
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USBH_HID_KEYBD_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Exported_FunctionsPrototype:
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+ + +
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+ + + + + + +

+Functions

+void USR_KEYBRD_Init (void)
 
+void USR_KEYBRD_ProcessData (uint8_t pbuf)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.map new file mode 100644 index 0000000..9bc0d94 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.md5 new file mode 100644 index 0000000..7dcc816 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.md5 @@ -0,0 +1 @@ +3920705261b95eb7504bd70ed8c51017 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.png new file mode 100644 index 0000000..0bfb41a Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___functions_prototype.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.html new file mode 100644 index 0000000..0ac0027 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Exported_Macros + + + + + + + + + + +
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USBH_HID_KEYBD_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
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+
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+Collaboration diagram for USBH_HID_KEYBD_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.map new file mode 100644 index 0000000..1a4b121 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.md5 new file mode 100644 index 0000000..4f5a67e --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.md5 @@ -0,0 +1 @@ +5fc28b51177383b67a5220c38a0b8c61 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.png new file mode 100644 index 0000000..0d4931f Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___macros.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.html new file mode 100644 index 0000000..10e156a --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Exported_Types + + + + + + + + + + +
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USBH_HID_KEYBD_Exported_Types
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
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+Collaboration diagram for USBH_HID_KEYBD_Exported_Types:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.map new file mode 100644 index 0000000..a0b064b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.md5 new file mode 100644 index 0000000..a803996 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.md5 @@ -0,0 +1 @@ +0c6c0ad5fccda0430aacd9726b6d54c5 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.png new file mode 100644 index 0000000..5d0821b Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___types.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.html new file mode 100644 index 0000000..a680eb7 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Exported_Variables + + + + + + + + + + +
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discoverpixy +
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+Variables
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USBH_HID_KEYBD_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Exported_Variables:
+
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+ + +
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+ + + + +

+Variables

+HID_cb_TypeDef HID_KEYBRD_cb
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.map new file mode 100644 index 0000000..94e7abb --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.md5 new file mode 100644 index 0000000..c3d68e8 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.md5 @@ -0,0 +1 @@ +d9f8b9cbad368dc03373bf31664ee5d1 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.png new file mode 100644 index 0000000..5aa3b38 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___exported___variables.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.html new file mode 100644 index 0000000..b0c773b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_Defines + + + + + + + + + + +
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USBH_HID_KEYBD_Private_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
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+Collaboration diagram for USBH_HID_KEYBD_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.map new file mode 100644 index 0000000..e8545f1 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.md5 new file mode 100644 index 0000000..b6646fc --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.md5 @@ -0,0 +1 @@ +bbf3d1634e2061f6eb89dd03b3097723 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.png new file mode 100644 index 0000000..574889e Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___defines.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.html new file mode 100644 index 0000000..f66caeb --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_FunctionPrototypes + + + + + + + + + + +
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discoverpixy +
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USBH_HID_KEYBD_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Private_FunctionPrototypes:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.map new file mode 100644 index 0000000..c21f672 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.md5 new file mode 100644 index 0000000..9664aa8 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.md5 @@ -0,0 +1 @@ +e5115dea01ad3fede9995e262fd82402 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.png new file mode 100644 index 0000000..38440c2 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___function_prototypes.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.html new file mode 100644 index 0000000..117680b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_Functions + + + + + + + + + + +
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USBH_HID_KEYBD_Private_Functions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Private_Functions:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.map new file mode 100644 index 0000000..748a9d3 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.md5 new file mode 100644 index 0000000..8f66ead --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.md5 @@ -0,0 +1 @@ +091bb2d1318d4001d6832406c9808e07 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.png new file mode 100644 index 0000000..5cb7058 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___functions.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.html new file mode 100644 index 0000000..2cd53fc --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_Macros + + + + + + + + + + +
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discoverpixy +
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USBH_HID_KEYBD_Private_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Private_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.map new file mode 100644 index 0000000..61c4799 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.md5 new file mode 100644 index 0000000..049242a --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.md5 @@ -0,0 +1 @@ +3b66d81e1f9e080207ac5dde65085eba \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.png new file mode 100644 index 0000000..0fbc83f Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___macros.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.html new file mode 100644 index 0000000..6acffe9 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_TypesDefinitions + + + + + + + + + + +
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USBH_HID_KEYBD_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Private_TypesDefinitions:
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+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.map new file mode 100644 index 0000000..9195669 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.md5 new file mode 100644 index 0000000..e24b9fb --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.md5 @@ -0,0 +1 @@ +1000b9b11d8f6f72d3de1949f5651690 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.png new file mode 100644 index 0000000..9e68ab6 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___types_definitions.png differ diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.html b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.html new file mode 100644 index 0000000..791b95b --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: USBH_HID_KEYBD_Private_Variables + + + + + + + + + + +
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discoverpixy +
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+Variables
+
+
USBH_HID_KEYBD_Private_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_KEYBD
+
+
+
+Collaboration diagram for USBH_HID_KEYBD_Private_Variables:
+
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+ + +
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+ + + + +

+Variables

HID_cb_TypeDef HID_KEYBRD_cb
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
HID_cb_TypeDef HID_KEYBRD_cb
+
+Initial value:
=
+
{
+
KEYBRD_Init,
+
KEYBRD_Decode
+
}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.map b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.map new file mode 100644 index 0000000..0f6a2bb --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.md5 b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.md5 new file mode 100644 index 0000000..998e485 --- /dev/null +++ b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.md5 @@ -0,0 +1 @@ +8cb7962e229c923ea00eccf93bd96ba8 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.png b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.png new file mode 100644 index 0000000..4d926b5 Binary files /dev/null and b/group___u_s_b_h___h_i_d___k_e_y_b_d___private___variables.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e.html b/group___u_s_b_h___h_i_d___m_o_u_s_e.html new file mode 100644 index 0000000..05584bf --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE + + + + + + + + + + +
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discoverpixy +
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+Modules
+
+
USBH_HID_MOUSE
USBH_LIB » USBH_CLASS » USBH_HID_CLASS
+
+
+ +

This file is the Header file for USBH_HID_MOUSE.c. +More...

+
+Collaboration diagram for USBH_HID_MOUSE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_HID_MOUSE_Exported_Types
 
 USBH_HID_MOUSE_Exported_Defines
 
 USBH_HID_MOUSE_Exported_Macros
 
 USBH_HID_MOUSE_Exported_Variables
 
 USBH_HID_MOUSE_Exported_FunctionsPrototype
 
 USBH_HID_MOUSE_Private_TypesDefinitions
 
 USBH_HID_MOUSE_Private_Defines
 
 USBH_HID_MOUSE_Private_Macros
 
 USBH_HID_MOUSE_Private_FunctionPrototypes
 
 USBH_HID_MOUSE_Private_Variables
 
 USBH_HID_MOUSE_Private_Functions
 
+

Detailed Description

+

This file is the Header file for USBH_HID_MOUSE.c.

+

This file includes HID Layer Handlers for USB Host HID class.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e.map b/group___u_s_b_h___h_i_d___m_o_u_s_e.map new file mode 100644 index 0000000..cb82e72 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e.md5 new file mode 100644 index 0000000..100a1d2 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e.md5 @@ -0,0 +1 @@ +d98c487cfe2a0f2920e0c50f635b81eb \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e.png b/group___u_s_b_h___h_i_d___m_o_u_s_e.png new file mode 100644 index 0000000..a4da52d Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.html new file mode 100644 index 0000000..6ee5556 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Exported_Defines + + + + + + + + + + +
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USBH_HID_MOUSE_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Exported_Defines:
+
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+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.map new file mode 100644 index 0000000..3108370 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.md5 new file mode 100644 index 0000000..e091ebf --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.md5 @@ -0,0 +1 @@ +4efa6b0cde3070667aeb4708dcdf5359 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.png new file mode 100644 index 0000000..48dbf46 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___defines.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.html new file mode 100644 index 0000000..d5d4b48 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Exported_FunctionsPrototype + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
USBH_HID_MOUSE_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Exported_FunctionsPrototype:
+
+
+ + +
+
+ + + + + + +

+Functions

+void USR_MOUSE_Init (void)
 
+void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.map new file mode 100644 index 0000000..3eeb9a0 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.md5 new file mode 100644 index 0000000..87b56b0 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.md5 @@ -0,0 +1 @@ +69bd4daed3393124fb98d046f7f7c58e \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.png new file mode 100644 index 0000000..8cefc21 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___functions_prototype.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.html new file mode 100644 index 0000000..c6934b3 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Exported_Macros + + + + + + + + + + +
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discoverpixy +
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USBH_HID_MOUSE_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Exported_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.map new file mode 100644 index 0000000..b432080 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.md5 new file mode 100644 index 0000000..cf7d6aa --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.md5 @@ -0,0 +1 @@ +511243a7c4b051473aab5052740bf3e6 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.png new file mode 100644 index 0000000..fd6ad02 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___macros.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.html new file mode 100644 index 0000000..abac94c --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Exported_Types + + + + + + + + + + +
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+
discoverpixy +
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+Classes | +Typedefs
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+
USBH_HID_MOUSE_Exported_Types
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Exported_Types:
+
+
+ + +
+
+ + + + +

+Classes

struct  _HID_MOUSE_Data
 
+ + + +

+Typedefs

+typedef struct _HID_MOUSE_Data HID_MOUSE_Data_TypeDef
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.map new file mode 100644 index 0000000..3fd203a --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.md5 new file mode 100644 index 0000000..542f594 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.md5 @@ -0,0 +1 @@ +0f700619c905eebf1e26a1dfff6456c8 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.png new file mode 100644 index 0000000..001063e Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___types.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.html new file mode 100644 index 0000000..5d43aa5 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Exported_Variables + + + + + + + + + + +
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+
discoverpixy +
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+Variables
+
+
USBH_HID_MOUSE_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Exported_Variables:
+
+
+ + +
+
+ + + + + + +

+Variables

+HID_cb_TypeDef HID_MOUSE_cb
 
+HID_MOUSE_Data_TypeDef HID_MOUSE_Data
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.map new file mode 100644 index 0000000..2e6ef61 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.md5 new file mode 100644 index 0000000..b4c346c --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.md5 @@ -0,0 +1 @@ +16ad1f684cdb4ff1f059a33b8e384621 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.png new file mode 100644 index 0000000..404546a Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___exported___variables.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.html new file mode 100644 index 0000000..47c9e6e --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_Defines + + + + + + + + + + +
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+
discoverpixy +
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+ + + + +
+ +
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+ + +
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+
USBH_HID_MOUSE_Private_Defines
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_Defines:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.map new file mode 100644 index 0000000..6d2414e --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.md5 new file mode 100644 index 0000000..bfd3829 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.md5 @@ -0,0 +1 @@ +dc8fa170b2a4ecdd7895d91b699a3e50 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.png new file mode 100644 index 0000000..bfbee9e Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___defines.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.html new file mode 100644 index 0000000..9677b2e --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_FunctionPrototypes + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ +
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USBH_HID_MOUSE_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_FunctionPrototypes:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.map new file mode 100644 index 0000000..f84932c --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.md5 new file mode 100644 index 0000000..34dd679 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.md5 @@ -0,0 +1 @@ +6f20b0cd640e3fdb6e6c4371aac8d1c0 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.png new file mode 100644 index 0000000..977e2b5 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___function_prototypes.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.html new file mode 100644 index 0000000..c42bcf3 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.html @@ -0,0 +1,100 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+
USBH_HID_MOUSE_Private_Functions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_Functions:
+
+
+ + +
+
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.map new file mode 100644 index 0000000..d569f33 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.md5 new file mode 100644 index 0000000..abc64ef --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.md5 @@ -0,0 +1 @@ +7cb7c489e6eec6d5ffd39e6f38aca834 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.png new file mode 100644 index 0000000..e42c10f Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___functions.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.html new file mode 100644 index 0000000..1549684 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_Macros + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+
USBH_HID_MOUSE_Private_Macros
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_Macros:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.map new file mode 100644 index 0000000..36e15d5 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.md5 new file mode 100644 index 0000000..f127cf0 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.md5 @@ -0,0 +1 @@ +a71f3805d0769dc750a0dba5c4d5e8ba \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.png new file mode 100644 index 0000000..a893660 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___macros.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.html new file mode 100644 index 0000000..294c89e --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_TypesDefinitions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
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USBH_HID_MOUSE_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_TypesDefinitions:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.map new file mode 100644 index 0000000..06d3beb --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.md5 new file mode 100644 index 0000000..cbc9d45 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.md5 @@ -0,0 +1 @@ +16c180640ec04ba1fc772dd54ba52e9d \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.png new file mode 100644 index 0000000..b036051 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___types_definitions.png differ diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.html b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.html new file mode 100644 index 0000000..f691d05 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.html @@ -0,0 +1,129 @@ + + + + + + +discoverpixy: USBH_HID_MOUSE_Private_Variables + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
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+Variables
+
+
USBH_HID_MOUSE_Private_Variables
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE
+
+
+
+Collaboration diagram for USBH_HID_MOUSE_Private_Variables:
+
+
+ + +
+
+ + + + + + +

+Variables

+HID_MOUSE_Data_TypeDef HID_MOUSE_Data
 
HID_cb_TypeDef HID_MOUSE_cb
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
HID_cb_TypeDef HID_MOUSE_cb
+
+Initial value:
=
+
{
+
MOUSE_Init,
+
MOUSE_Decode,
+
}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.map b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.map new file mode 100644 index 0000000..32ca82e --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.md5 b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.md5 new file mode 100644 index 0000000..c3bc749 --- /dev/null +++ b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.md5 @@ -0,0 +1 @@ +b8524dae50141d1a966a0c7f2145a383 \ No newline at end of file diff --git a/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.png b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.png new file mode 100644 index 0000000..857b750 Binary files /dev/null and b/group___u_s_b_h___h_i_d___m_o_u_s_e___private___variables.png differ diff --git a/group___u_s_b_h___i_o_r_e_q.html b/group___u_s_b_h___i_o_r_e_q.html new file mode 100644 index 0000000..a3ef52d --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_IOREQ + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
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+ + +
+ +
+ +
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+Modules
+
+
USBH_IOREQ
USBH_LIB » USBH_LIB_CORE
+
+
+ +

This file is the header file for usbh_ioreq.c. +More...

+
+Collaboration diagram for USBH_IOREQ:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_IOREQ_Exported_Defines
 
 USBH_IOREQ_Exported_Types
 
 USBH_IOREQ_Exported_Macros
 
 USBH_IOREQ_Exported_Variables
 
 USBH_IOREQ_Exported_FunctionsPrototype
 
 USBH_IOREQ_Private_Defines
 
 USBH_IOREQ_Private_TypesDefinitions
 
 USBH_IOREQ_Private_Macros
 
 USBH_IOREQ_Private_Variables
 
 USBH_IOREQ_Private_FunctionPrototypes
 
 USBH_IOREQ_Private_Functions
 
+

Detailed Description

+

This file is the header file for usbh_ioreq.c.

+

This file handles the standard protocol processing (USB v2.0)

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___i_o_r_e_q.map b/group___u_s_b_h___i_o_r_e_q.map new file mode 100644 index 0000000..9745b04 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___i_o_r_e_q.md5 b/group___u_s_b_h___i_o_r_e_q.md5 new file mode 100644 index 0000000..0500983 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q.md5 @@ -0,0 +1 @@ +a52777a1d2a1b3a40b365bed51ec289d \ No newline at end of file diff --git a/group___u_s_b_h___i_o_r_e_q.png b/group___u_s_b_h___i_o_r_e_q.png new file mode 100644 index 0000000..6c8813d Binary files /dev/null and b/group___u_s_b_h___i_o_r_e_q.png differ diff --git a/group___u_s_b_h___i_o_r_e_q___exported___defines.html b/group___u_s_b_h___i_o_r_e_q___exported___defines.html new file mode 100644 index 0000000..4a4835f --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___defines.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_IOREQ_Exported_Defines + + + + + + + + + + +
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discoverpixy +
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+Macros
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USBH_IOREQ_Exported_Defines
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Macros

+#define USBH_SETUP_PKT_SIZE   8
 
+#define USBH_EP0_EP_NUM   0
 
+#define USBH_MAX_PACKET_SIZE   0x40
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___defines.map b/group___u_s_b_h___i_o_r_e_q___exported___defines.map new file mode 100644 index 0000000..11f9631 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___defines.md5 b/group___u_s_b_h___i_o_r_e_q___exported___defines.md5 new file mode 100644 index 0000000..a505ae5 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___defines.md5 @@ -0,0 +1 @@ +9871da0abf3b0e7db78bf69b51462f29 \ No newline at end of file diff --git a/group___u_s_b_h___i_o_r_e_q___exported___defines.png b/group___u_s_b_h___i_o_r_e_q___exported___defines.png new file mode 100644 index 0000000..8090d98 Binary files /dev/null and b/group___u_s_b_h___i_o_r_e_q___exported___defines.png differ diff --git a/group___u_s_b_h___i_o_r_e_q___exported___functions_prototype.html b/group___u_s_b_h___i_o_r_e_q___exported___functions_prototype.html new file mode 100644 index 0000000..2820164 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___functions_prototype.html @@ -0,0 +1,690 @@ + + + + + + +discoverpixy: USBH_IOREQ_Exported_FunctionsPrototype + + + + + + + + + + +
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+Functions
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USBH_IOREQ_Exported_FunctionsPrototype
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Functions

USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t hc_num)
 USBH_CtlSendSetup Sends the Setup Packet to the Device. More...
 
USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlSendData Sends a data Packet to the Device. More...
 
USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlReceiveData Receives the Device Response to the Setup Packet. More...
 
USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkReceiveData Receives IN bulk packet from device. More...
 
USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkSendData Sends the Bulk Packet to the device. More...
 
USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token. More...
 
USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint. More...
 
USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length)
 USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request. More...
 
+

Detailed Description

+

Function Documentation

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USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint16_t length,
uint8_t hc_num 
)
+
+ +

USBH_BulkReceiveData Receives IN bulk packet from device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the received data packet to be copied
lengthLength of the data to be received
hc_numHost channel Number
+
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Return values
+ + +
Status.
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USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint16_t length,
uint8_t hc_num 
)
+
+ +

USBH_BulkSendData Sends the Bulk Packet to the device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from which the Data will be sent to Device
lengthLength of the data to be sent
hc_numHost channel Number
+
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Return values
+ + +
Status
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USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_CtlReceiveData Receives the Device Response to the Setup Packet.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the response needs to be copied
lengthLength of the data to be received
hc_numHost channel Number
+
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Return values
+ + +
Status.
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USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t * buff,
uint16_t length 
)
+
+ +

USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request.

+
Parameters
+ + + + + +
pdevSelected device
reqSetup Request Structure
buffdata buffer address to store the response
lengthlength of the response
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Return values
+ + +
Status
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USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_CtlSendData Sends a data Packet to the Device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from which the Data will be sent to Device
lengthLength of the data to be sent
hc_numHost channel Number
+
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Return values
+ + +
Status
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USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t hc_num 
)
+
+ +

USBH_CtlSendSetup Sends the Setup Packet to the Device.

+
Parameters
+ + + + +
pdevSelected device
buffBuffer pointer from which the Data will be send to Device
hc_numHost channel Number
+
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Return values
+ + +
Status
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USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the response needs to be copied
lengthLength of the data to be received
hc_numHost channel Number
+
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Return values
+ + +
Status.
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USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from where the data needs to be copied
lengthLength of the data to be sent
hc_numHost channel Number
+
+
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Return values
+ + +
Status.
+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_IOREQ_Exported_Macros
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___macros.map b/group___u_s_b_h___i_o_r_e_q___exported___macros.map new file mode 100644 index 0000000..bf64584 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___macros.md5 b/group___u_s_b_h___i_o_r_e_q___exported___macros.md5 new file mode 100644 index 0000000..5e7fd2a --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___macros.md5 @@ -0,0 +1 @@ +803c72a582c4259f606a3d67047db065 \ No newline at end of file diff --git a/group___u_s_b_h___i_o_r_e_q___exported___macros.png b/group___u_s_b_h___i_o_r_e_q___exported___macros.png new file mode 100644 index 0000000..a390ecf Binary files /dev/null and b/group___u_s_b_h___i_o_r_e_q___exported___macros.png differ diff --git a/group___u_s_b_h___i_o_r_e_q___exported___types.html b/group___u_s_b_h___i_o_r_e_q___exported___types.html new file mode 100644 index 0000000..7b9b22e --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___types.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_IOREQ_Exported_Types + + + + + + + + + + +
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USBH_IOREQ_Exported_Types
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Exported_Types:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___types.map b/group___u_s_b_h___i_o_r_e_q___exported___types.map new file mode 100644 index 0000000..96fb283 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___i_o_r_e_q___exported___types.md5 b/group___u_s_b_h___i_o_r_e_q___exported___types.md5 new file mode 100644 index 0000000..015787c --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___types.md5 @@ -0,0 +1 @@ +bbffb47438f3b54f00dcf8a96259d644 \ No newline at end of file diff --git a/group___u_s_b_h___i_o_r_e_q___exported___types.png b/group___u_s_b_h___i_o_r_e_q___exported___types.png new file mode 100644 index 0000000..eff2191 Binary files /dev/null and b/group___u_s_b_h___i_o_r_e_q___exported___types.png differ diff --git a/group___u_s_b_h___i_o_r_e_q___exported___variables.html b/group___u_s_b_h___i_o_r_e_q___exported___variables.html new file mode 100644 index 0000000..d840a20 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_IOREQ_Exported_Variables + + + + + + + + + + +
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USBH_IOREQ_Exported_Variables
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Exported_Variables:
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USBH_IOREQ_Private_Defines
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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USBH_IOREQ_Private_FunctionPrototypes
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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Detailed Description

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+Functions
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USBH_IOREQ_Private_Functions
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Functions

USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length)
 USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request. More...
 
USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t hc_num)
 USBH_CtlSendSetup Sends the Setup Packet to the Device. More...
 
USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlSendData Sends a data Packet to the Device. More...
 
USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlReceiveData Receives the Device Response to the Setup Packet. More...
 
USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkSendData Sends the Bulk Packet to the device. More...
 
USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkReceiveData Receives IN bulk packet from device. More...
 
USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token. More...
 
USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint. More...
 
+

Detailed Description

+

Function Documentation

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USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint16_t length,
uint8_t hc_num 
)
+
+ +

USBH_BulkReceiveData Receives IN bulk packet from device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the received data packet to be copied
lengthLength of the data to be received
hc_numHost channel Number
+
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Return values
+ + +
Status.
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USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint16_t length,
uint8_t hc_num 
)
+
+ +

USBH_BulkSendData Sends the Bulk Packet to the device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from which the Data will be sent to Device
lengthLength of the data to be sent
hc_numHost channel Number
+
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Return values
+ + +
Status
+
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USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_CtlReceiveData Receives the Device Response to the Setup Packet.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the response needs to be copied
lengthLength of the data to be received
hc_numHost channel Number
+
+
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Return values
+ + +
Status.
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USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t * buff,
uint16_t length 
)
+
+ +

USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request.

+
Parameters
+ + + + + +
pdevSelected device
reqSetup Request Structure
buffdata buffer address to store the response
lengthlength of the response
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Return values
+ + +
Status
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USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_CtlSendData Sends a data Packet to the Device.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from which the Data will be sent to Device
lengthLength of the data to be sent
hc_numHost channel Number
+
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Return values
+ + +
Status
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USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t hc_num 
)
+
+ +

USBH_CtlSendSetup Sends the Setup Packet to the Device.

+
Parameters
+ + + + +
pdevSelected device
buffBuffer pointer from which the Data will be send to Device
hc_numHost channel Number
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Return values
+ + +
Status
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USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
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+ +

USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer in which the response needs to be copied
lengthLength of the data to be received
hc_numHost channel Number
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Return values
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Status.
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USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE * pdev,
uint8_t * buff,
uint8_t length,
uint8_t hc_num 
)
+
+ +

USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint.

+
Parameters
+ + + + + +
pdevSelected device
buffBuffer pointer from where the data needs to be copied
lengthLength of the data to be sent
hc_numHost channel Number
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Return values
+ + +
Status.
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USBH_IOREQ_Private_Macros
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Private_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_IOREQ_Private_TypesDefinitions
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_IOREQ_Private_Variables
USBH_LIB » USBH_LIB_CORE » USBH_IOREQ
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+Collaboration diagram for USBH_IOREQ_Private_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___i_o_r_e_q___private___variables.map b/group___u_s_b_h___i_o_r_e_q___private___variables.map new file mode 100644 index 0000000..60b9742 --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___i_o_r_e_q___private___variables.md5 b/group___u_s_b_h___i_o_r_e_q___private___variables.md5 new file mode 100644 index 0000000..ce3cf3c --- /dev/null +++ b/group___u_s_b_h___i_o_r_e_q___private___variables.md5 @@ -0,0 +1 @@ +6760d6d36851af695df91ed214b2802c \ No newline at end of file diff --git a/group___u_s_b_h___i_o_r_e_q___private___variables.png b/group___u_s_b_h___i_o_r_e_q___private___variables.png new file mode 100644 index 0000000..5cad7e4 Binary files /dev/null and b/group___u_s_b_h___i_o_r_e_q___private___variables.png differ diff --git a/group___u_s_b_h___l_i_b.html b/group___u_s_b_h___l_i_b.html new file mode 100644 index 0000000..778bcb6 --- /dev/null +++ b/group___u_s_b_h___l_i_b.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: USBH_LIB + + + + + + + + + + +
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USBH_LIB
+
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+Collaboration diagram for USBH_LIB:
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+
+ + + + + + +

+Modules

 USBH_CLASS
 
 USBH_LIB_CORE
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___l_i_b.map b/group___u_s_b_h___l_i_b.map new file mode 100644 index 0000000..f109dc0 --- /dev/null +++ b/group___u_s_b_h___l_i_b.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___u_s_b_h___l_i_b.md5 b/group___u_s_b_h___l_i_b.md5 new file mode 100644 index 0000000..d41a513 --- /dev/null +++ b/group___u_s_b_h___l_i_b.md5 @@ -0,0 +1 @@ +abc7538d08a9174bf15a26bcebccbc66 \ No newline at end of file diff --git a/group___u_s_b_h___l_i_b.png b/group___u_s_b_h___l_i_b.png new file mode 100644 index 0000000..095dcb7 Binary files /dev/null and b/group___u_s_b_h___l_i_b.png differ diff --git a/group___u_s_b_h___l_i_b___c_o_r_e.html b/group___u_s_b_h___l_i_b___c_o_r_e.html new file mode 100644 index 0000000..056074c --- /dev/null +++ b/group___u_s_b_h___l_i_b___c_o_r_e.html @@ -0,0 +1,383 @@ + + + + + + +discoverpixy: USBH_LIB_CORE + + + + + + + + + + +
+
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discoverpixy +
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+Modules | +Classes | +Macros | +Typedefs | +Variables
+
+
USBH_LIB_CORE
USBH_LIB
+
+
+
+Collaboration diagram for USBH_LIB_CORE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Modules

 USBH_CORE
 This file is the Header file for usbh_core.c.
 
 USBH_DEF
 This file is includes USB descriptors.
 
 USBH_HCS
 This file is the header file for usbh_hcs.c.
 
 USBH_IOREQ
 This file is the header file for usbh_ioreq.c.
 
 USBH_STDREQ
 This file is the.
 
+ + + + + + + + + + + + + + + + + + + + + +

+Classes

union  uint16_t_uint8_t
 
struct  uint16_t_uint8_t::BW
 
union  _USB_Setup
 
struct  _USB_Setup::_SetupPkt_Struc
 
struct  _DescHeader
 
struct  _DeviceDescriptor
 
struct  _ConfigurationDescriptor
 
struct  _HIDDescriptor
 
struct  _InterfaceDescriptor
 
struct  _EndpointDescriptor
 
+ + + + + +

+Macros

#define USBH_CONFIGURATION_DESCRIPTOR_SIZE
 
#define CONFIG_DESC_wTOTAL_LENGTH
 
+ + + + + + + + + + + + + + + +

+Typedefs

+typedef union _USB_Setup USB_Setup_TypeDef
 
+typedef struct _DescHeader USBH_DescHeader_t
 
+typedef struct _DeviceDescriptor USBH_DevDesc_TypeDef
 
+typedef struct _ConfigurationDescriptor USBH_CfgDesc_TypeDef
 
+typedef struct _HIDDescriptor USBH_HIDDesc_TypeDef
 
+typedef struct _InterfaceDescriptor USBH_InterfaceDesc_TypeDef
 
+typedef struct _EndpointDescriptor USBH_EpDesc_TypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

+uint16_t uint16_t_uint8_t::w
 
+uint8_t uint16_t_uint8_t::BW::msb
 
+uint8_t uint16_t_uint8_t::BW::lsb
 
+struct uint16_t_uint8_t::BW uint16_t_uint8_t::bw
 
+uint8_t _USB_Setup::d8 [8]
 
+uint8_t _USB_Setup::_SetupPkt_Struc::bmRequestType
 
+uint8_t _USB_Setup::_SetupPkt_Struc::bRequest
 
+uint16_t_uint8_t _USB_Setup::_SetupPkt_Struc::wValue
 
+uint16_t_uint8_t _USB_Setup::_SetupPkt_Struc::wIndex
 
+uint16_t_uint8_t _USB_Setup::_SetupPkt_Struc::wLength
 
+struct _USB_Setup::_SetupPkt_Struc _USB_Setup::b
 
+uint8_t _DescHeader::bLength
 
+uint8_t _DescHeader::bDescriptorType
 
+uint8_t _DeviceDescriptor::bLength
 
+uint8_t _DeviceDescriptor::bDescriptorType
 
+uint16_t _DeviceDescriptor::bcdUSB
 
+uint8_t _DeviceDescriptor::bDeviceClass
 
+uint8_t _DeviceDescriptor::bDeviceSubClass
 
+uint8_t _DeviceDescriptor::bDeviceProtocol
 
+uint8_t _DeviceDescriptor::bMaxPacketSize
 
+uint16_t _DeviceDescriptor::idVendor
 
+uint16_t _DeviceDescriptor::idProduct
 
+uint16_t _DeviceDescriptor::bcdDevice
 
+uint8_t _DeviceDescriptor::iManufacturer
 
+uint8_t _DeviceDescriptor::iProduct
 
+uint8_t _DeviceDescriptor::iSerialNumber
 
+uint8_t _DeviceDescriptor::bNumConfigurations
 
+uint8_t _ConfigurationDescriptor::bLength
 
+uint8_t _ConfigurationDescriptor::bDescriptorType
 
+uint16_t _ConfigurationDescriptor::wTotalLength
 
+uint8_t _ConfigurationDescriptor::bNumInterfaces
 
+uint8_t _ConfigurationDescriptor::bConfigurationValue
 
+uint8_t _ConfigurationDescriptor::iConfiguration
 
+uint8_t _ConfigurationDescriptor::bmAttributes
 
+uint8_t _ConfigurationDescriptor::bMaxPower
 
+uint8_t _HIDDescriptor::bLength
 
+uint8_t _HIDDescriptor::bDescriptorType
 
+uint16_t _HIDDescriptor::bcdHID
 
+uint8_t _HIDDescriptor::bCountryCode
 
+uint8_t _HIDDescriptor::bNumDescriptors
 
+uint8_t _HIDDescriptor::bReportDescriptorType
 
+uint16_t _HIDDescriptor::wItemLength
 
+uint8_t _InterfaceDescriptor::bLength
 
+uint8_t _InterfaceDescriptor::bDescriptorType
 
+uint8_t _InterfaceDescriptor::bInterfaceNumber
 
+uint8_t _InterfaceDescriptor::bAlternateSetting
 
+uint8_t _InterfaceDescriptor::bNumEndpoints
 
+uint8_t _InterfaceDescriptor::bInterfaceClass
 
+uint8_t _InterfaceDescriptor::bInterfaceSubClass
 
+uint8_t _InterfaceDescriptor::bInterfaceProtocol
 
+uint8_t _InterfaceDescriptor::iInterface
 
+uint8_t _EndpointDescriptor::bLength
 
+uint8_t _EndpointDescriptor::bDescriptorType
 
+uint8_t _EndpointDescriptor::bEndpointAddress
 
+uint8_t _EndpointDescriptor::bmAttributes
 
+uint16_t _EndpointDescriptor::wMaxPacketSize
 
+uint8_t _EndpointDescriptor::bInterval
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CONFIG_DESC_wTOTAL_LENGTH
+
+Value:
(ConfigurationDescriptorData.ConfigDescfield.\ + ConfigurationDescriptor.wTotalLength)
+
+
+
+ +
+
+ + + + +
#define USBH_CONFIGURATION_DESCRIPTOR_SIZE
+
+Value:
(USB_CONFIGURATION_DESC_SIZE \
+
+ USB_INTERFACE_DESC_SIZE\
+
+ (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___l_i_b___c_o_r_e.map b/group___u_s_b_h___l_i_b___c_o_r_e.map new file mode 100644 index 0000000..d371d2d --- /dev/null +++ b/group___u_s_b_h___l_i_b___c_o_r_e.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/group___u_s_b_h___l_i_b___c_o_r_e.md5 b/group___u_s_b_h___l_i_b___c_o_r_e.md5 new file mode 100644 index 0000000..ce26dea --- /dev/null +++ b/group___u_s_b_h___l_i_b___c_o_r_e.md5 @@ -0,0 +1 @@ +97672637612dea47281ed26d970bb683 \ No newline at end of file diff --git a/group___u_s_b_h___l_i_b___c_o_r_e.png b/group___u_s_b_h___l_i_b___c_o_r_e.png new file mode 100644 index 0000000..4bf1b35 Binary files /dev/null and b/group___u_s_b_h___l_i_b___c_o_r_e.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t.html b/group___u_s_b_h___m_s_c___b_o_t.html new file mode 100644 index 0000000..03eedbb --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_MSC_BOT + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Modules
+
+
USBH_MSC_BOT
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS
+
+
+ +

This file is the Header file for usbh_msc_core.c. +More...

+
+Collaboration diagram for USBH_MSC_BOT:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_MSC_BOT_Exported_Types
 
 USBH_MSC_BOT_Exported_Defines
 
 USBH_MSC_BOT_Exported_Macros
 
 USBH_MSC_BOT_Exported_Variables
 
 USBH_MSC_BOT_Exported_FunctionsPrototype
 
 USBH_MSC_BOT_Private_TypesDefinitions
 
 USBH_MSC_BOT_Private_Defines
 
 USBH_MSC_BOT_Private_Macros
 
 USBH_MSC_BOT_Private_Variables
 
 USBH_MSC_BOT_Private_FunctionPrototypes
 
 USBH_MSC_BOT_Private_Functions
 
+

Detailed Description

+

This file is the Header file for usbh_msc_core.c.

+

This file includes the mass storage related functions.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t.map b/group___u_s_b_h___m_s_c___b_o_t.map new file mode 100644 index 0000000..e9ec78d --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t.md5 b/group___u_s_b_h___m_s_c___b_o_t.md5 new file mode 100644 index 0000000..0e32bcb --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t.md5 @@ -0,0 +1 @@ +0ecbaf9aafaeb0a089bf62ea3eb6d248 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t.png b/group___u_s_b_h___m_s_c___b_o_t.png new file mode 100644 index 0000000..53ed245 Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___defines.html b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.html new file mode 100644 index 0000000..0b7b20c --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.html @@ -0,0 +1,212 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Exported_Defines + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
USBH_MSC_BOT_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
+
+
+
+Collaboration diagram for USBH_MSC_BOT_Exported_Defines:
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USBH_MSC_SEND_CBW   1
 
+#define USBH_MSC_SENT_CBW   2
 
+#define USBH_MSC_BOT_DATAIN_STATE   3
 
+#define USBH_MSC_BOT_DATAOUT_STATE   4
 
+#define USBH_MSC_RECEIVE_CSW_STATE   5
 
+#define USBH_MSC_DECODE_CSW   6
 
+#define USBH_MSC_BOT_ERROR_IN   7
 
+#define USBH_MSC_BOT_ERROR_OUT   8
 
+#define USBH_MSC_BOT_CBW_SIGNATURE   0x43425355
 
+#define USBH_MSC_BOT_CBW_TAG   0x20304050
 
+#define USBH_MSC_BOT_CSW_SIGNATURE   0x53425355
 
+#define USBH_MSC_CSW_DATA_LENGTH   0x000D
 
+#define USBH_MSC_BOT_CBW_PACKET_LENGTH   31
 
+#define USBH_MSC_CSW_LENGTH   13
 
+#define USBH_MSC_CSW_MAX_LENGTH   63
 
+#define USBH_MSC_CSW_CMD_PASSED   0x00
 
+#define USBH_MSC_CSW_CMD_FAILED   0x01
 
+#define USBH_MSC_CSW_PHASE_ERROR   0x02
 
+#define USBH_MSC_SEND_CSW_DISABLE   0
 
+#define USBH_MSC_SEND_CSW_ENABLE   1
 
+#define USBH_MSC_DIR_IN   0
 
+#define USBH_MSC_DIR_OUT   1
 
+#define USBH_MSC_BOTH_DIR   2
 
+#define USBH_MSC_PAGE_LENGTH   512
 
+#define CBW_CB_LENGTH   16
 
+#define CBW_LENGTH   10
 
+#define CBW_LENGTH_TEST_UNIT_READY   6
 
+#define USB_REQ_BOT_RESET   0xFF
 
+#define USB_REQ_GET_MAX_LUN   0xFE
 
#define MAX_BULK_STALL_COUNT_LIMIT
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define MAX_BULK_STALL_COUNT_LIMIT
+
+Value:
0x04 /* If STALL is seen on Bulk
+
Endpoint continously, this means
+
that device and Host has phase error
+
Hence a Reset is needed */
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___defines.map b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.map new file mode 100644 index 0000000..3fa3314 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___defines.md5 b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.md5 new file mode 100644 index 0000000..b0eaac0 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.md5 @@ -0,0 +1 @@ +717fbf001dfa93cf6d41c6712a4eaef9 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___defines.png b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.png new file mode 100644 index 0000000..52a1ed3 Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___exported___defines.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___functions_prototype.html b/group___u_s_b_h___m_s_c___b_o_t___exported___functions_prototype.html new file mode 100644 index 0000000..1d9b3f2 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___functions_prototype.html @@ -0,0 +1,334 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Exported_FunctionsPrototype + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Functions
+
+
USBH_MSC_BOT_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
+
+
+
+Collaboration diagram for USBH_MSC_BOT_Exported_FunctionsPrototype:
+
+
+ + +
+
+ + + + + + + + + + + + + + +

+Functions

void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer. More...
 
uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer. More...
 
void USBH_MSC_Init (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_Init Initializes the mass storage parameters. More...
 
USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t direction)
 USBH_MSC_BOT_Abort This function manages the different Error handling for STALL. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t direction 
)
+
+ +

USBH_MSC_BOT_Abort This function manages the different Error handling for STALL.

+
Parameters
+ + +
direction: IN / OUT
+
+
+
Return values
+ + +
None
+
+
+ +

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uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Onsuccess USBH_MSC_OK, on failure USBH_MSC_FAIL Refer to USB Mass-Storage Class : BOT (www.usb.org) 6.3.1 Valid CSW Conditions : The host shall consider the CSW valid when:
    +
  1. dCSWSignature is equal to 53425355h
    2. +
  2. the CSW is 13 (Dh) bytes in length,
    3. +
  3. dCSWTag matches the dCBWTag from the corresponding CBW.
    4. +
+
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void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
+
+ +

USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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+ +
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+ +
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+ + + + + + + + +
void USBH_MSC_Init (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_MSC_Init Initializes the mass storage parameters.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
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+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_MSC_BOT_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___macros.map b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.map new file mode 100644 index 0000000..3f483cb --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___macros.md5 b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.md5 new file mode 100644 index 0000000..140e89a --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.md5 @@ -0,0 +1 @@ +5111f5d2d15b7b50d2ba0c9a9f195000 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___macros.png b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.png new file mode 100644 index 0000000..4b1ef1d Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___exported___macros.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___types.html b/group___u_s_b_h___m_s_c___b_o_t___exported___types.html new file mode 100644 index 0000000..fded8be --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___types.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Exported_Types + + + + + + + + + + +
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+Classes | +Typedefs | +Enumerations
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+
USBH_MSC_BOT_Exported_Types
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Exported_Types:
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+Classes

union  _USBH_CBW_Block
 
struct  _USBH_CBW_Block::__CBW
 
struct  _BOTXfer
 
union  _USBH_CSW_Block
 
struct  _USBH_CSW_Block::__CSW
 
+ + + + + + + +

+Typedefs

+typedef union _USBH_CBW_Block HostCBWPkt_TypeDef
 
+typedef struct _BOTXfer USBH_BOTXfer_TypeDef
 
+typedef union _USBH_CSW_Block HostCSWPkt_TypeDef
 
+ + + +

+Enumerations

enum  MSCState {
+  USBH_MSC_BOT_INIT_STATE = 0, +USBH_MSC_BOT_RESET, +USBH_MSC_GET_MAX_LUN, +USBH_MSC_TEST_UNIT_READY, +
+  USBH_MSC_READ_CAPACITY10, +USBH_MSC_MODE_SENSE6, +USBH_MSC_REQUEST_SENSE, +USBH_MSC_BOT_USB_TRANSFERS, +
+  USBH_MSC_DEFAULT_APPLI_STATE, +USBH_MSC_CTRL_ERROR_STATE, +USBH_MSC_UNRECOVERED_STATE +
+ }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___types.map b/group___u_s_b_h___m_s_c___b_o_t___exported___types.map new file mode 100644 index 0000000..fa1edda --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___types.md5 b/group___u_s_b_h___m_s_c___b_o_t___exported___types.md5 new file mode 100644 index 0000000..efdb7ff --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___types.md5 @@ -0,0 +1 @@ +03b4c09bb42203a156c2f8f97a84651b \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___types.png b/group___u_s_b_h___m_s_c___b_o_t___exported___types.png new file mode 100644 index 0000000..14c298f Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___exported___types.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___variables.html b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.html new file mode 100644 index 0000000..0bb6835 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Exported_Variables + + + + + + + + + + +
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+Variables
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+
USBH_MSC_BOT_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Exported_Variables:
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+Variables

+USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam
 
+HostCBWPkt_TypeDef USBH_MSC_CBWData
 
+HostCSWPkt_TypeDef USBH_MSC_CSWData
 
+USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___variables.map b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.map new file mode 100644 index 0000000..7f8930d --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___variables.md5 b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.md5 new file mode 100644 index 0000000..d23d8ad --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.md5 @@ -0,0 +1 @@ +27da744dc519d10398d62b3c3e5e869f \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___exported___variables.png b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.png new file mode 100644 index 0000000..13de69d Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___exported___variables.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___defines.html b/group___u_s_b_h___m_s_c___b_o_t___private___defines.html new file mode 100644 index 0000000..808ed3d --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Private_Defines + + + + + + + + + + +
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USBH_MSC_BOT_Private_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___defines.map b/group___u_s_b_h___m_s_c___b_o_t___private___defines.map new file mode 100644 index 0000000..1a74389 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___defines.md5 b/group___u_s_b_h___m_s_c___b_o_t___private___defines.md5 new file mode 100644 index 0000000..758bcaa --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___defines.md5 @@ -0,0 +1 @@ +2bfb783de0ba883977fbf7c8bcbc8226 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___defines.png b/group___u_s_b_h___m_s_c___b_o_t___private___defines.png new file mode 100644 index 0000000..f1fc196 Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___private___defines.png differ diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___function_prototypes.html b/group___u_s_b_h___m_s_c___b_o_t___private___function_prototypes.html new file mode 100644 index 0000000..c482731 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___function_prototypes.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_BOT_Private_FunctionPrototypes + + + + + + + + + + +
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USBH_MSC_BOT_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Private_FunctionPrototypes:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Functions
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USBH_MSC_BOT_Private_Functions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Private_Functions:
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+Functions

void USBH_MSC_Init (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_Init Initializes the mass storage parameters. More...
 
void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer. More...
 
USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t direction)
 USBH_MSC_BOT_Abort This function manages the different Error handling for STALL. More...
 
uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer. More...
 
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Detailed Description

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Function Documentation

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USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t direction 
)
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+ +

USBH_MSC_BOT_Abort This function manages the different Error handling for STALL.

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Parameters
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direction: IN / OUT
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Return values
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None
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uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
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USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer.

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Parameters
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None
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Return values
+ + +
Onsuccess USBH_MSC_OK, on failure USBH_MSC_FAIL Refer to USB Mass-Storage Class : BOT (www.usb.org) 6.3.1 Valid CSW Conditions : The host shall consider the CSW valid when:
    +
  1. dCSWSignature is equal to 53425355h
    2. +
  2. the CSW is 13 (Dh) bytes in length,
    3. +
  3. dCSWTag matches the dCBWTag from the corresponding CBW.
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void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost 
)
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+ +

USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer.

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Parameters
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None
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Return values
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None
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void USBH_MSC_Init (USB_OTG_CORE_HANDLE * pdev)
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USBH_MSC_Init Initializes the mass storage parameters.

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Parameters
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None
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Return values
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None
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USBH_MSC_BOT_Private_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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USBH_MSC_BOT_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Variables
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USBH_MSC_BOT_Private_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT
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+Collaboration diagram for USBH_MSC_BOT_Private_Variables:
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+Variables

+__ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData __ALIGN_END
 
+

Detailed Description

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___variables.map b/group___u_s_b_h___m_s_c___b_o_t___private___variables.map new file mode 100644 index 0000000..3bb83e9 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___variables.md5 b/group___u_s_b_h___m_s_c___b_o_t___private___variables.md5 new file mode 100644 index 0000000..a34cc08 --- /dev/null +++ b/group___u_s_b_h___m_s_c___b_o_t___private___variables.md5 @@ -0,0 +1 @@ +f211be87f2b37055e15a0cbf53955b42 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___b_o_t___private___variables.png b/group___u_s_b_h___m_s_c___b_o_t___private___variables.png new file mode 100644 index 0000000..dbe4a8a Binary files /dev/null and b/group___u_s_b_h___m_s_c___b_o_t___private___variables.png differ diff --git a/group___u_s_b_h___m_s_c___c_l_a_s_s.html b/group___u_s_b_h___m_s_c___c_l_a_s_s.html new file mode 100644 index 0000000..34a7e0c --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_l_a_s_s.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_MSC_CLASS + + + + + + + + + + +
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+Modules
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USBH_MSC_CLASS
USBH_LIB » USBH_CLASS
+
+
+
+Collaboration diagram for USBH_MSC_CLASS:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 USBH_MSC_BOT
 This file is the Header file for usbh_msc_core.c.
 
 USBH_MSC_CORE
 This file is the Header file for usbh_msc_core.c.
 
 USBH_MSC_SCSI
 This file is the Header file for usbh_msc_scsi.c.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_l_a_s_s.map b/group___u_s_b_h___m_s_c___c_l_a_s_s.map new file mode 100644 index 0000000..d01ea55 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_l_a_s_s.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___u_s_b_h___m_s_c___c_l_a_s_s.md5 b/group___u_s_b_h___m_s_c___c_l_a_s_s.md5 new file mode 100644 index 0000000..6194e21 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_l_a_s_s.md5 @@ -0,0 +1 @@ +a151d026ed7304cb50a1b7ac1b8ff169 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_l_a_s_s.png b/group___u_s_b_h___m_s_c___c_l_a_s_s.png new file mode 100644 index 0000000..e99336b Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_l_a_s_s.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e.html b/group___u_s_b_h___m_s_c___c_o_r_e.html new file mode 100644 index 0000000..7e2e362 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_MSC_CORE + + + + + + + + + + +
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+Modules
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USBH_MSC_CORE
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS
+
+
+ +

This file is the Header file for usbh_msc_core.c. +More...

+
+Collaboration diagram for USBH_MSC_CORE:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_MSC_CORE_Exported_Types
 
 USBH_MSC_CORE_Exported_Defines
 
 USBH_MSC_CORE_Exported_Macros
 
 USBH_MSC_CORE_Exported_Variables
 
 USBH_MSC_CORE_Exported_FunctionsPrototype
 
 USBH_MSC_CORE_Private_TypesDefinitions
 
 USBH_MSC_CORE_Private_Defines
 
 USBH_MSC_CORE_Private_Macros
 
 USBH_MSC_CORE_Private_Variables
 
 USBH_MSC_CORE_Private_FunctionPrototypes
 
 USBH_MSC_CORE_Private_Functions
 
+

Detailed Description

+

This file is the Header file for usbh_msc_core.c.

+

This file includes the mass storage related functions.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e.map b/group___u_s_b_h___m_s_c___c_o_r_e.map new file mode 100644 index 0000000..7238d6e --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e.md5 b/group___u_s_b_h___m_s_c___c_o_r_e.md5 new file mode 100644 index 0000000..0950c33 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e.md5 @@ -0,0 +1 @@ +2f73455fe9225f0469b605e2a2e5c2fd \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e.png b/group___u_s_b_h___m_s_c___c_o_r_e.png new file mode 100644 index 0000000..130ed42 Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.html b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.html new file mode 100644 index 0000000..aed435f --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Exported_Defines + + + + + + + + + + +
+
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discoverpixy +
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+Macros
+
+
USBH_MSC_CORE_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Exported_Defines:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define USB_REQ_BOT_RESET   0xFF
 
+#define USB_REQ_GET_MAX_LUN   0xFE
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.map b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.map new file mode 100644 index 0000000..2413b9e --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.md5 new file mode 100644 index 0000000..62e0444 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.md5 @@ -0,0 +1 @@ +9ead338654661e4075e2434f68f21429 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.png b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.png new file mode 100644 index 0000000..57be3cb Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___exported___defines.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.html b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.html new file mode 100644 index 0000000..47a999d --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Exported_FunctionsPrototype + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
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+
USBH_MSC_CORE_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Exported_FunctionsPrototype:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.map b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.map new file mode 100644 index 0000000..e2d685b --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.md5 new file mode 100644 index 0000000..490f9ae --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.md5 @@ -0,0 +1 @@ +b7e8542f782cefea34b72b5fec6cb149 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.png b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.png new file mode 100644 index 0000000..f0635fb Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___exported___functions_prototype.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.html b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.html new file mode 100644 index 0000000..f7158b9 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Exported_Macros + + + + + + + + + + +
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+
discoverpixy +
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+
USBH_MSC_CORE_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Exported_Macros:
+
+
+ + +
+
+
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.map b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.map new file mode 100644 index 0000000..5721f94 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.md5 new file mode 100644 index 0000000..5b7fb40 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.md5 @@ -0,0 +1 @@ +b5a63a90ea301bc1ecdf9d29c6ebd588 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.png b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.png new file mode 100644 index 0000000..702b6db Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___exported___macros.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.html b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.html new file mode 100644 index 0000000..5f07a12 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Exported_Types + + + + + + + + + + +
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+ + + + + + +
+
discoverpixy +
+
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+Classes | +Typedefs
+
+
USBH_MSC_CORE_Exported_Types
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Exported_Types:
+
+
+ + +
+
+ + + + +

+Classes

struct  _MSC_Process
 
+ + + +

+Typedefs

+typedef struct _MSC_Process MSC_Machine_TypeDef
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.map b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.map new file mode 100644 index 0000000..c06db5c --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.md5 new file mode 100644 index 0000000..82e84cf --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.md5 @@ -0,0 +1 @@ +6a5071d87b396407458381ccb3e91d17 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.png b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.png new file mode 100644 index 0000000..99b024b Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___exported___types.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.html b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.html new file mode 100644 index 0000000..9a3e71c --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Exported_Variables + + + + + + + + + + +
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+
discoverpixy +
+
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+Variables
+
+
USBH_MSC_CORE_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Exported_Variables:
+
+
+ + +
+
+ + + + + + + + +

+Variables

+USBH_Class_cb_TypeDef USBH_MSC_cb
 
+MSC_Machine_TypeDef MSC_Machine
 
+uint8_t MSCErrorCount
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.map b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.map new file mode 100644 index 0000000..3913da7 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.md5 new file mode 100644 index 0000000..c0425ae --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.md5 @@ -0,0 +1 @@ +5303c47d53bf7c7d7a88c3e9cf94d878 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.png b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.png new file mode 100644 index 0000000..6e1cfd7 Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___exported___variables.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.html new file mode 100644 index 0000000..ec40851 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_Defines + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Macros
+
+
USBH_MSC_CORE_Private_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Private_Defines:
+
+
+ + +
+
+ + + + +

+Macros

+#define USBH_MSC_ERROR_RETRY_LIMIT   10
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.map new file mode 100644 index 0000000..84e7cc4 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.md5 new file mode 100644 index 0000000..42b828a --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.md5 @@ -0,0 +1 @@ +b74401c8dca2cd4339d589b4277827fd \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.png new file mode 100644 index 0000000..9ac0ddc Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___defines.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.html new file mode 100644 index 0000000..929225a --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_FunctionPrototypes + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Variables
+
+
USBH_MSC_CORE_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Private_FunctionPrototypes:
+
+
+ + +
+
+ + + + +

+Variables

USBH_Class_cb_TypeDef USBH_MSC_cb
 
+

Detailed Description

+

Variable Documentation

+ +
+
+ + + + +
USBH_Class_cb_TypeDef USBH_MSC_cb
+
+Initial value:
=
+
{
+
USBH_MSC_InterfaceInit,
+
USBH_MSC_InterfaceDeInit,
+
USBH_MSC_ClassRequest,
+
USBH_MSC_Handle,
+
}
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.map new file mode 100644 index 0000000..463e8f0 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.md5 new file mode 100644 index 0000000..7df4cd4 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.md5 @@ -0,0 +1 @@ +7d71fbb590fa2657ea37d12eabebbc86 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.png new file mode 100644 index 0000000..1f8f461 Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___function_prototypes.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.html new file mode 100644 index 0000000..1216c16 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_Functions + + + + + + + + + + +
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+Functions
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USBH_MSC_CORE_Private_Functions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Private_Functions:
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+ + + + + +

+Functions

void USBH_MSC_ErrorHandle (uint8_t status)
 USBH_MSC_ErrorHandle The function is for handling errors occuring during the MSC state machine. More...
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void USBH_MSC_ErrorHandle (uint8_t status)
+
+ +

USBH_MSC_ErrorHandle The function is for handling errors occuring during the MSC state machine.

+
Parameters
+ + +
status
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.map new file mode 100644 index 0000000..37d776c --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.md5 new file mode 100644 index 0000000..4cc0a19 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.md5 @@ -0,0 +1 @@ +10371fd996373342d23f81b2a377d163 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.png new file mode 100644 index 0000000..e530670 Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___functions.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.html new file mode 100644 index 0000000..6313e38 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_Macros + + + + + + + + + + +
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USBH_MSC_CORE_Private_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
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+Collaboration diagram for USBH_MSC_CORE_Private_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.map new file mode 100644 index 0000000..bb27943 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.md5 new file mode 100644 index 0000000..b4d6162 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.md5 @@ -0,0 +1 @@ +75d731250f04177af938d8d5e9d015e9 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.png new file mode 100644 index 0000000..77cc8aa Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___macros.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.html new file mode 100644 index 0000000..7e93f17 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_TypesDefinitions + + + + + + + + + + +
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USBH_MSC_CORE_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
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+Collaboration diagram for USBH_MSC_CORE_Private_TypesDefinitions:
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+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.map new file mode 100644 index 0000000..f33f097 --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.md5 new file mode 100644 index 0000000..c2a549c --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.md5 @@ -0,0 +1 @@ +32fc6fc48db8897c034d684ddb851528 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.png new file mode 100644 index 0000000..dc001eb Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___types_definitions.png differ diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.html b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.html new file mode 100644 index 0000000..d07b21a --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: USBH_MSC_CORE_Private_Variables + + + + + + + + + + +
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discoverpixy +
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+Variables
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USBH_MSC_CORE_Private_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE
+
+
+
+Collaboration diagram for USBH_MSC_CORE_Private_Variables:
+
+
+ + +
+
+ + + + + + +

+Variables

+__ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine __ALIGN_END
 
+uint8_t MSCErrorCount = 0
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.map b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.map new file mode 100644 index 0000000..99152bd --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.md5 b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.md5 new file mode 100644 index 0000000..d23c66a --- /dev/null +++ b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.md5 @@ -0,0 +1 @@ +c681af9288c5efd474a6710417b6b23c \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.png b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.png new file mode 100644 index 0000000..06dadcb Binary files /dev/null and b/group___u_s_b_h___m_s_c___c_o_r_e___private___variables.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i.html b/group___u_s_b_h___m_s_c___s_c_s_i.html new file mode 100644 index 0000000..08222a8 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI + + + + + + + + + + +
+
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discoverpixy +
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+Modules
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+
USBH_MSC_SCSI
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS
+
+
+ +

This file is the Header file for usbh_msc_scsi.c. +More...

+
+Collaboration diagram for USBH_MSC_SCSI:
+
+
+ + +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Modules

 USBH_MSC_SCSI_Exported_Types
 
 USBH_MSC_SCSI_Exported_Defines
 
 USBH_MSC_SCSI_Exported_Macros
 
 _Exported_Variables
 
 USBH_MSC_SCSI_Exported_FunctionsPrototype
 
 USBH_MSC_SCSI_Private_TypesDefinitions
 
 USBH_MSC_SCSI_Private_Defines
 
 USBH_MSC_SCSI_Private_Macros
 
 USBH_MSC_SCSI_Private_Variables
 
 USBH_MSC_SCSI_Private_FunctionPrototypes
 
 USBH_MSC_SCSI_Exported_Variables
 
 USBH_MSC_SCSI_Private_Functions
 
+

Detailed Description

+

This file is the Header file for usbh_msc_scsi.c.

+

This file includes the mass storage related functions.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i.map b/group___u_s_b_h___m_s_c___s_c_s_i.map new file mode 100644 index 0000000..8998a43 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i.map @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i.md5 b/group___u_s_b_h___m_s_c___s_c_s_i.md5 new file mode 100644 index 0000000..df23a84 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i.md5 @@ -0,0 +1 @@ +315fcd480a2a5f2235fd7f4d50744b68 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i.png b/group___u_s_b_h___m_s_c___s_c_s_i.png new file mode 100644 index 0000000..48a6345 Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.html b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.html new file mode 100644 index 0000000..4bf0dbc --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Exported_Defines + + + + + + + + + + +
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discoverpixy +
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USBH_MSC_SCSI_Exported_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
+
+
+
+Collaboration diagram for USBH_MSC_SCSI_Exported_Defines:
+
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+Macros

+#define OPCODE_TEST_UNIT_READY   0X00
 
+#define OPCODE_READ_CAPACITY10   0x25
 
+#define OPCODE_MODE_SENSE6   0x1A
 
+#define OPCODE_READ10   0x28
 
+#define OPCODE_WRITE10   0x2A
 
+#define OPCODE_REQUEST_SENSE   0x03
 
+#define DESC_REQUEST_SENSE   0X00
 
+#define ALLOCATION_LENGTH_REQUEST_SENSE   63
 
+#define XFER_LEN_READ_CAPACITY10   8
 
+#define XFER_LEN_MODE_SENSE6   63
 
+#define MASK_MODE_SENSE_WRITE_PROTECT   0x80
 
+#define MODE_SENSE_PAGE_CONTROL_FIELD   0x00
 
+#define MODE_SENSE_PAGE_CODE   0x3F
 
+#define DISK_WRITE_PROTECTED   0x01
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.map b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.map new file mode 100644 index 0000000..c2ebf07 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.md5 new file mode 100644 index 0000000..ff9a401 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.md5 @@ -0,0 +1 @@ +0748fbad052b61aeaae33bed6dd60955 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.png b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.png new file mode 100644 index 0000000..47217f9 Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___exported___defines.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___functions_prototype.html b/group___u_s_b_h___m_s_c___s_c_s_i___exported___functions_prototype.html new file mode 100644 index 0000000..4cb49ec --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___functions_prototype.html @@ -0,0 +1,410 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Exported_FunctionsPrototype + + + + + + + + + + +
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+Functions
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USBH_MSC_SCSI_Exported_FunctionsPrototype
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
+
+
+
+Collaboration diagram for USBH_MSC_SCSI_Exported_FunctionsPrototype:
+
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+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device. More...
 
uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
 USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
 USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer. More...
 
+void USBH_MSC_StateMachine (USB_OTG_CORE_HANDLE *pdev)
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the call graph for this function:
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uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dataBuffer,
uint32_t address,
uint32_t nbOfbytes 
)
+
+ +

USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer.

+
Parameters
+ + + + +
dataBuffer: DataBuffer will contain the data to be read
address: Address from which the data will be read
nbOfbytes: NbOfbytes to be read
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the call graph for this function:
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+

+ +
+
+ +
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+ + + + + + + + +
uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the call graph for this function:
+
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+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Status
+
+
+ +

+Here is the call graph for this function:
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+ + +
+

+ +
+
+ +
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+ + + + + + + + +
uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Status
+
+
+ +

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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dataBuffer,
uint32_t address,
uint32_t nbOfbytes 
)
+
+ +

USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer.

+
Parameters
+ + + + +
dataBuffer: DataBuffer contains the data to write
address: Address to which the data will be written
nbOfbytes: NbOfbytes to be written
+
+
+
Return values
+ + +
Status
+
+
+ +

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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_MSC_SCSI_Exported_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.map b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.map new file mode 100644 index 0000000..2f17284 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.md5 new file mode 100644 index 0000000..c6fda7b --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.md5 @@ -0,0 +1 @@ +5e2ee056a0be31b945d2ce0756789c59 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.png b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.png new file mode 100644 index 0000000..081913e Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___exported___macros.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.html b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.html new file mode 100644 index 0000000..226a595 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.html @@ -0,0 +1,130 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Exported_Types + + + + + + + + + + +
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+Classes | +Typedefs | +Enumerations
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USBH_MSC_SCSI_Exported_Types
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Exported_Types:
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+Classes

struct  __MassStorageParameter
 
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+Typedefs

+typedef struct __MassStorageParameter MassStorageParameter_TypeDef
 
+ + + + + +

+Enumerations

enum  USBH_MSC_Status_TypeDef { USBH_MSC_OK = 0, +USBH_MSC_FAIL = 1, +USBH_MSC_PHASE_ERROR = 2, +USBH_MSC_BUSY = 3 + }
 
enum  CMD_STATES_TypeDef { CMD_UNINITIALIZED_STATE =0, +CMD_SEND_STATE, +CMD_WAIT_STATUS + }
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.map b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.map new file mode 100644 index 0000000..186bab9 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.md5 new file mode 100644 index 0000000..ec80bf2 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.md5 @@ -0,0 +1 @@ +58ab91e469d25c3bd3954dad866b6657 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.png b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.png new file mode 100644 index 0000000..4839dc5 Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___exported___types.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.html b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.html new file mode 100644 index 0000000..8bb5788 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Exported_Variables + + + + + + + + + + +
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USBH_MSC_SCSI_Exported_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Exported_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.map b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.map new file mode 100644 index 0000000..804bbcf --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.md5 new file mode 100644 index 0000000..d30c054 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.md5 @@ -0,0 +1 @@ +fce19c21429a4130c191c82fb28ed057 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.png b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.png new file mode 100644 index 0000000..e2893d3 Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___exported___variables.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___defines.html b/group___u_s_b_h___m_s_c___s_c_s_i___private___defines.html new file mode 100644 index 0000000..d20e258 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___defines.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Private_Defines + + + + + + + + + + +
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USBH_MSC_SCSI_Private_Defines
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_MSC_SCSI_Private_FunctionPrototypes
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Private_FunctionPrototypes:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Functions
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USBH_MSC_SCSI_Private_Functions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Functions

uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device. More...
 
uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes)
 USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes)
 USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer. More...
 
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Detailed Description

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Function Documentation

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uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE * pdev)
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USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device.

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uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dataBuffer,
uint32_t address,
uint32_t nbOfbytes 
)
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USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer.

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Parameters
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dataBuffer: DataBuffer will contain the data to be read
address: Address from which the data will be read
nbOfbytes: NbOfbytes to be read
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Status
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uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE * pdev)
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USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer.

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Parameters
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None
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Return values
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Status
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uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE * pdev)
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USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer.

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Parameters
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Status
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uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE * pdev)
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USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer.

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Parameters
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Status
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uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE * pdev,
uint8_t * dataBuffer,
uint32_t address,
uint32_t nbOfbytes 
)
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USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer.

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Parameters
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dataBuffer: DataBuffer contains the data to write
address: Address to which the data will be written
nbOfbytes: NbOfbytes to be written
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Status
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_MSC_SCSI_Private_Macros
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Private_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Variables
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USBH_MSC_SCSI_Private_TypesDefinitions
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Private_TypesDefinitions:
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+Variables

+MassStorageParameter_TypeDef USBH_MSC_Param
 
+

Detailed Description

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+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.map b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.map new file mode 100644 index 0000000..0323439 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.md5 new file mode 100644 index 0000000..027bc3e --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.md5 @@ -0,0 +1 @@ +0c6d0d4b73d403568270c578ef63d8d9 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.png b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.png new file mode 100644 index 0000000..605099c Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___private___types_definitions.png differ diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.html b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.html new file mode 100644 index 0000000..d9199a7 --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USBH_MSC_SCSI_Private_Variables + + + + + + + + + + +
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+Variables
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USBH_MSC_SCSI_Private_Variables
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI
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+Collaboration diagram for USBH_MSC_SCSI_Private_Variables:
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+ + + + +

+Variables

+__ALIGN_BEGIN uint8_t USBH_DataInBuffer[512] __ALIGN_END
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.map b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.map new file mode 100644 index 0000000..78e501c --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.md5 b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.md5 new file mode 100644 index 0000000..470b57b --- /dev/null +++ b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.md5 @@ -0,0 +1 @@ +0417bf2a5b3a71b1d1820076be0aa229 \ No newline at end of file diff --git a/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.png b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.png new file mode 100644 index 0000000..d4aa56a Binary files /dev/null and b/group___u_s_b_h___m_s_c___s_c_s_i___private___variables.png differ diff --git a/group___u_s_b_h___o_t_g___d_r_i_v_e_r.html b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.html new file mode 100644 index 0000000..382d957 --- /dev/null +++ b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: USBH_OTG_DRIVER + + + + + + + + + + +
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discoverpixy +
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+Modules
+
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USBH_OTG_DRIVER
+
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+Collaboration diagram for USBH_OTG_DRIVER:
+
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+ + +
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+ + + + + +

+Modules

 USBH_CONF
 usb otg low level driver configuration file
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___o_t_g___d_r_i_v_e_r.map b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.map new file mode 100644 index 0000000..6f302f8 --- /dev/null +++ b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___o_t_g___d_r_i_v_e_r.md5 b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.md5 new file mode 100644 index 0000000..e22fcb1 --- /dev/null +++ b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.md5 @@ -0,0 +1 @@ +74df895ea7c1c4f6c36c09574c2d048c \ No newline at end of file diff --git a/group___u_s_b_h___o_t_g___d_r_i_v_e_r.png b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.png new file mode 100644 index 0000000..4003eb2 Binary files /dev/null and b/group___u_s_b_h___o_t_g___d_r_i_v_e_r.png differ diff --git a/group___u_s_b_h___s_t_d_r_e_q.html b/group___u_s_b_h___s_t_d_r_e_q.html new file mode 100644 index 0000000..456b262 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: USBH_STDREQ + + + + + + + + + + +
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+Modules
+
+
USBH_STDREQ
USBH_LIB » USBH_LIB_CORE
+
+
+ +

This file is the. +More...

+
+Collaboration diagram for USBH_STDREQ:
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+Modules

 USBH_STDREQ_Exported_Defines
 
 USBH_STDREQ_Exported_Types
 
 USBH_STDREQ_Exported_Macros
 
 USBH_STDREQ_Exported_Variables
 
 USBH_STDREQ_Exported_FunctionsPrototype
 
 USBH_STDREQ_Private_Defines
 
 USBH_STDREQ_Private_TypesDefinitions
 
 USBH_STDREQ_Private_Macros
 
 USBH_STDREQ_Private_Variables
 
 USBH_STDREQ_Private_FunctionPrototypes
 
 USBH_STDREQ_Private_Functions
 
+

Detailed Description

+

This file is the.

+

This file implements the standard requests for device enumeration.

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___s_t_d_r_e_q.map b/group___u_s_b_h___s_t_d_r_e_q.map new file mode 100644 index 0000000..f723c05 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/group___u_s_b_h___s_t_d_r_e_q.md5 b/group___u_s_b_h___s_t_d_r_e_q.md5 new file mode 100644 index 0000000..aa2ba5b --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q.md5 @@ -0,0 +1 @@ +e81b2941b1643986bcce7b1d65c64b12 \ No newline at end of file diff --git a/group___u_s_b_h___s_t_d_r_e_q.png b/group___u_s_b_h___s_t_d_r_e_q.png new file mode 100644 index 0000000..bbb19d6 Binary files /dev/null and b/group___u_s_b_h___s_t_d_r_e_q.png differ diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___defines.html b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.html new file mode 100644 index 0000000..eff36f6 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: USBH_STDREQ_Exported_Defines + + + + + + + + + + +
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discoverpixy +
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+Macros
+
+
USBH_STDREQ_Exported_Defines
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
+
+
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+Collaboration diagram for USBH_STDREQ_Exported_Defines:
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+Macros

+#define FEATURE_SELECTOR_ENDPOINT   0X00
 
+#define FEATURE_SELECTOR_DEVICE   0X01
 
+#define INTERFACE_DESC_TYPE   0x04
 
+#define ENDPOINT_DESC_TYPE   0x05
 
+#define INTERFACE_DESC_SIZE   0x09
 
+#define USBH_HID_CLASS   0x03
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___defines.map b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.map new file mode 100644 index 0000000..fb88fc2 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___defines.md5 b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.md5 new file mode 100644 index 0000000..627c229 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.md5 @@ -0,0 +1 @@ +b27ac83c410df519488faf4d66204056 \ No newline at end of file diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___defines.png b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.png new file mode 100644 index 0000000..461b056 Binary files /dev/null and b/group___u_s_b_h___s_t_d_r_e_q___exported___defines.png differ diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___functions_prototype.html b/group___u_s_b_h___s_t_d_r_e_q___exported___functions_prototype.html new file mode 100644 index 0000000..be65cce --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___functions_prototype.html @@ -0,0 +1,588 @@ + + + + + + +discoverpixy: USBH_STDREQ_Exported_FunctionsPrototype + + + + + + + + + + +
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discoverpixy +
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+ +
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+Functions
+
+
USBH_STDREQ_Exported_FunctionsPrototype
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
+
+
+
+Collaboration diagram for USBH_STDREQ_Exported_FunctionsPrototype:
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+Functions

USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t *buff, uint16_t length)
 USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status. More...
 
USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t length)
 USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status. More...
 
USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
 USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status. More...
 
USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t configuration_value)
 USBH_SetCfg The command sets the configuration value to the connected device. More...
 
USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t length)
 USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status. More...
 
USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t DeviceAddress)
 USBH_SetAddress This command sets the address to the connected device. More...
 
USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num)
 USBH_ClrFeature This request is used to clear or disable a specific feature. More...
 
+USBH_Status USBH_Issue_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num)
 
+

Detailed Description

+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t ep_num,
uint8_t hc_num 
)
+
+ +

USBH_ClrFeature This request is used to clear or disable a specific feature.

+
Parameters
+ + + + +
pdevSelected device
ep_numendpoint number
hc_numHost channel number
+
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Return values
+ + +
Status
+
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USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint16_t length 
)
+
+ +

USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status.

+
Parameters
+ + + + + + +
pdevSelected device
cfg_descConfiguration Descriptor address
itf_descInterface Descriptor address
ep_descEndpoint Descriptor address
lengthLength of the descriptor
+
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Return values
+ + +
Status
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USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t length 
)
+
+ +

USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status.

+
Parameters
+ + + + + +
pdevSelected device
dev_descDevice Descriptor buffer address
pdev->host.Rx_BufferReceive Buffer address
lengthLength of the descriptor
+
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Return values
+ + +
Status
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USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t string_index,
uint8_t * buff,
uint16_t length 
)
+
+ +

USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status.

+
Parameters
+ + + + + +
pdevSelected device
string_indexString index for the descriptor
buffBuffer address for the descriptor
lengthLength of the descriptor
+
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Return values
+ + +
Status
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USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t req_type,
uint16_t value_idx,
uint8_t * buff,
uint16_t length 
)
+
+ +

USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status.

+
Parameters
+ + + + + + +
pdevSelected device
req_typeDescriptor type
value_idxwValue for the GetDescriptr request
buffBuffer to store the descriptor
lengthLength of the descriptor
+
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Return values
+ + +
Status
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USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t DeviceAddress 
)
+
+ +

USBH_SetAddress This command sets the address to the connected device.

+
Parameters
+ + + +
pdevSelected device
DeviceAddressDevice address to assign
+
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Return values
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Status
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USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint16_t cfg_idx 
)
+
+ +

USBH_SetCfg The command sets the configuration value to the connected device.

+
Parameters
+ + + +
pdevSelected device
cfg_idxConfiguration value
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Return values
+ + +
Status
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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b/group___u_s_b_h___s_t_d_r_e_q___exported___macros.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_STDREQ_Exported_Macros + + + + + + + + + + +
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USBH_STDREQ_Exported_Macros
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Collaboration diagram for USBH_STDREQ_Exported_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_STDREQ_Exported_Types
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Collaboration diagram for USBH_STDREQ_Exported_Types:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___types.map b/group___u_s_b_h___s_t_d_r_e_q___exported___types.map new file mode 100644 index 0000000..1aa0c00 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___types.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___types.md5 b/group___u_s_b_h___s_t_d_r_e_q___exported___types.md5 new file mode 100644 index 0000000..65da34c --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___types.md5 @@ -0,0 +1 @@ +b4defa6e6a9f671df085359dacb01ab0 \ No newline at end of file diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___types.png b/group___u_s_b_h___s_t_d_r_e_q___exported___types.png new file mode 100644 index 0000000..a8e1777 Binary files /dev/null and b/group___u_s_b_h___s_t_d_r_e_q___exported___types.png differ diff --git a/group___u_s_b_h___s_t_d_r_e_q___exported___variables.html b/group___u_s_b_h___s_t_d_r_e_q___exported___variables.html new file mode 100644 index 0000000..27289ce --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___exported___variables.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_STDREQ_Exported_Variables + + + + + + + + + + +
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USBH_STDREQ_Exported_Variables
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Collaboration diagram for USBH_STDREQ_Exported_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_STDREQ_Private_Defines
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Collaboration diagram for USBH_STDREQ_Private_Defines:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_STDREQ_Private_FunctionPrototypes
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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Detailed Description

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+Functions
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USBH_STDREQ_Private_Functions
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Functions

USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t length)
 USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status. More...
 
USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t length)
 USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status. More...
 
USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
 USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status. More...
 
USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t *buff, uint16_t length)
 USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status. More...
 
USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t DeviceAddress)
 USBH_SetAddress This command sets the address to the connected device. More...
 
USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t cfg_idx)
 USBH_SetCfg The command sets the configuration value to the connected device. More...
 
USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num)
 USBH_ClrFeature This request is used to clear or disable a specific feature. More...
 
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Detailed Description

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Function Documentation

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USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t ep_num,
uint8_t hc_num 
)
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USBH_ClrFeature This request is used to clear or disable a specific feature.

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Parameters
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pdevSelected device
ep_numendpoint number
hc_numHost channel number
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Return values
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Status
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USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint16_t length 
)
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USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status.

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Parameters
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pdevSelected device
cfg_descConfiguration Descriptor address
itf_descInterface Descriptor address
ep_descEndpoint Descriptor address
lengthLength of the descriptor
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Return values
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Status
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USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t length 
)
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USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status.

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Parameters
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pdevSelected device
dev_descDevice Descriptor buffer address
pdev->host.Rx_BufferReceive Buffer address
lengthLength of the descriptor
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Return values
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Status
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USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t string_index,
uint8_t * buff,
uint16_t length 
)
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USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status.

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Parameters
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pdevSelected device
string_indexString index for the descriptor
buffBuffer address for the descriptor
lengthLength of the descriptor
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Return values
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Status
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USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t req_type,
uint16_t value_idx,
uint8_t * buff,
uint16_t length 
)
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USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status.

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Parameters
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pdevSelected device
req_typeDescriptor type
value_idxwValue for the GetDescriptr request
buffBuffer to store the descriptor
lengthLength of the descriptor
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Return values
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Status
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USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint8_t DeviceAddress 
)
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USBH_SetAddress This command sets the address to the connected device.

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Parameters
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pdevSelected device
DeviceAddressDevice address to assign
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Return values
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Status
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USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE * pdev,
USBH_HOST * phost,
uint16_t cfg_idx 
)
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USBH_SetCfg The command sets the configuration value to the connected device.

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Parameters
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pdevSelected device
cfg_idxConfiguration value
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Return values
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Status
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discoverpixy +
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USBH_STDREQ_Private_Macros
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
+
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+Collaboration diagram for USBH_STDREQ_Private_Macros:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___macros.map b/group___u_s_b_h___s_t_d_r_e_q___private___macros.map new file mode 100644 index 0000000..246e2ed --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___private___macros.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___macros.md5 b/group___u_s_b_h___s_t_d_r_e_q___private___macros.md5 new file mode 100644 index 0000000..bca20d0 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___private___macros.md5 @@ -0,0 +1 @@ +8fff9915e73aef85a6d228960723fcbf \ No newline at end of file diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___macros.png b/group___u_s_b_h___s_t_d_r_e_q___private___macros.png new file mode 100644 index 0000000..254e287 Binary files /dev/null and b/group___u_s_b_h___s_t_d_r_e_q___private___macros.png differ diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___types_definitions.html b/group___u_s_b_h___s_t_d_r_e_q___private___types_definitions.html new file mode 100644 index 0000000..15e768e --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___private___types_definitions.html @@ -0,0 +1,99 @@ + + + + + + +discoverpixy: USBH_STDREQ_Private_TypesDefinitions + + + + + + + + + + +
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USBH_STDREQ_Private_TypesDefinitions
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
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+Collaboration diagram for USBH_STDREQ_Private_TypesDefinitions:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
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USBH_STDREQ_Private_Variables
USBH_LIB » USBH_LIB_CORE » USBH_STDREQ
+
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+Collaboration diagram for USBH_STDREQ_Private_Variables:
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+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___variables.map b/group___u_s_b_h___s_t_d_r_e_q___private___variables.map new file mode 100644 index 0000000..fb7a359 --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___private___variables.map @@ -0,0 +1,3 @@ + + + diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___variables.md5 b/group___u_s_b_h___s_t_d_r_e_q___private___variables.md5 new file mode 100644 index 0000000..e0a6dbe --- /dev/null +++ b/group___u_s_b_h___s_t_d_r_e_q___private___variables.md5 @@ -0,0 +1 @@ +e593aeb59612345e9ebb9d0aadf33203 \ No newline at end of file diff --git a/group___u_s_b_h___s_t_d_r_e_q___private___variables.png b/group___u_s_b_h___s_t_d_r_e_q___private___variables.png new file mode 100644 index 0000000..b14f018 Binary files /dev/null and b/group___u_s_b_h___s_t_d_r_e_q___private___variables.png differ diff --git a/group___utilities.html b/group___utilities.html new file mode 100644 index 0000000..9d0935a --- /dev/null +++ b/group___utilities.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Utilities + + + + + + + + + + +
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+Modules | +Enumerator
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Utilities
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+Modules

 STM32F4_DISCOVERY
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___utilities.map b/group___utilities.map new file mode 100644 index 0000000..53092b7 --- /dev/null +++ b/group___utilities.map @@ -0,0 +1,3 @@ + + + diff --git a/group___utilities.md5 b/group___utilities.md5 new file mode 100644 index 0000000..7865f5a --- /dev/null +++ b/group___utilities.md5 @@ -0,0 +1 @@ +ddd3062296da3ade4dec1724a10e8ea4 \ No newline at end of file diff --git a/group___utilities.png b/group___utilities.png new file mode 100644 index 0000000..f4b3a97 Binary files /dev/null and b/group___utilities.png differ diff --git a/group___w_w_d_g.html b/group___w_w_d_g.html new file mode 100644 index 0000000..ad85d38 --- /dev/null +++ b/group___w_w_d_g.html @@ -0,0 +1,424 @@ + + + + + + +discoverpixy: WWDG + + + + + + + + + + +
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+Modules | +Macros | +Functions
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+
WWDG
STM32F4xx_StdPeriph_Driver
+
+
+ +

WWDG driver modules. +More...

+
+Collaboration diagram for WWDG:
+
+
+ + +
+
+ + + + + + +

+Modules

 WWDG_Exported_Constants
 
 WWDG_Private_Functions
 
+ + + + + + + + + + + + + + + +

+Macros

+#define WWDG_OFFSET   (WWDG_BASE - PERIPH_BASE)
 
+#define CFR_OFFSET   (WWDG_OFFSET + 0x04)
 
+#define EWI_BitNumber   0x09
 
+#define CFR_EWI_BB   (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
 
+#define CFR_WDGTB_MASK   ((uint32_t)0xFFFFFE7F)
 
+#define CFR_W_MASK   ((uint32_t)0xFFFFFF80)
 
+#define BIT_MASK   ((uint8_t)0x7F)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void WWDG_DeInit (void)
 Deinitializes the WWDG peripheral registers to their default reset values. More...
 
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
 Sets the WWDG Prescaler. More...
 
void WWDG_SetWindowValue (uint8_t WindowValue)
 Sets the WWDG window value. More...
 
void WWDG_EnableIT (void)
 Enables the WWDG Early Wakeup interrupt(EWI). More...
 
void WWDG_SetCounter (uint8_t Counter)
 Sets the WWDG counter value. More...
 
void WWDG_Enable (uint8_t Counter)
 Enables WWDG and load the counter value. More...
 
FlagStatus WWDG_GetFlagStatus (void)
 Checks whether the Early Wakeup interrupt flag is set or not. More...
 
void WWDG_ClearFlag (void)
 Clears Early Wakeup interrupt flag. More...
 
+

Detailed Description

+

WWDG driver modules.

+

Function Documentation

+ +
+
+ + + + + + + + +
void WWDG_ClearFlag (void )
+
+ +

Clears Early Wakeup interrupt flag.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_DeInit (void )
+
+ +

Deinitializes the WWDG peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
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+

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+ + + + + + + + +
void WWDG_Enable (uint8_t Counter)
+
+ +

Enables WWDG and load the counter value.

+
Parameters
+ + +
Counterspecifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_EnableIT (void )
+
+ +

Enables the WWDG Early Wakeup interrupt(EWI).

+
Note
Once enabled this interrupt cannot be disabled except by a system reset.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus WWDG_GetFlagStatus (void )
+
+ +

Checks whether the Early Wakeup interrupt flag is set or not.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thenew state of the Early Wakeup interrupt flag (SET or RESET)
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetCounter (uint8_t Counter)
+
+ +

Sets the WWDG counter value.

+
Parameters
+ + +
Counterspecifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
+
+ +

Sets the WWDG Prescaler.

+
Parameters
+ + +
WWDG_Prescalerspecifies the WWDG Prescaler. This parameter can be one of the following values:
    +
  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
    • +
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
    • +
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
    • +
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetWindowValue (uint8_t WindowValue)
+
+ +

Sets the WWDG window value.

+
Parameters
+ + +
WindowValuespecifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g.map b/group___w_w_d_g.map new file mode 100644 index 0000000..10cec38 --- /dev/null +++ b/group___w_w_d_g.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group___w_w_d_g.md5 b/group___w_w_d_g.md5 new file mode 100644 index 0000000..d83e82d --- /dev/null +++ b/group___w_w_d_g.md5 @@ -0,0 +1 @@ +2b0d5d636e1cc8e9f75ffd88087bc843 \ No newline at end of file diff --git a/group___w_w_d_g.png b/group___w_w_d_g.png new file mode 100644 index 0000000..6b1bdca Binary files /dev/null and b/group___w_w_d_g.png differ diff --git a/group___w_w_d_g___exported___constants.html b/group___w_w_d_g___exported___constants.html new file mode 100644 index 0000000..3f493d0 --- /dev/null +++ b/group___w_w_d_g___exported___constants.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: WWDG_Exported_Constants + + + + + + + + + + +
+
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discoverpixy +
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+Modules
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+
WWDG_Exported_Constants
STM32F4xx_StdPeriph_Driver » WWDG
+
+
+
+Collaboration diagram for WWDG_Exported_Constants:
+
+
+ + +
+
+ + + + +

+Modules

 WWDG_Prescaler
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___exported___constants.map b/group___w_w_d_g___exported___constants.map new file mode 100644 index 0000000..79045ca --- /dev/null +++ b/group___w_w_d_g___exported___constants.map @@ -0,0 +1,4 @@ + + + + diff --git a/group___w_w_d_g___exported___constants.md5 b/group___w_w_d_g___exported___constants.md5 new file mode 100644 index 0000000..edb50ca --- /dev/null +++ b/group___w_w_d_g___exported___constants.md5 @@ -0,0 +1 @@ +e4c43b0efd5c120efc4b4540e8d131ab \ No newline at end of file diff --git a/group___w_w_d_g___exported___constants.png b/group___w_w_d_g___exported___constants.png new file mode 100644 index 0000000..93669fb Binary files /dev/null and b/group___w_w_d_g___exported___constants.png differ diff --git a/group___w_w_d_g___group1.html b/group___w_w_d_g___group1.html new file mode 100644 index 0000000..cab69f5 --- /dev/null +++ b/group___w_w_d_g___group1.html @@ -0,0 +1,294 @@ + + + + + + +discoverpixy: Prescaler, Refresh window and Counter configuration functions + + + + + + + + + + +
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discoverpixy +
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+Functions
+
+
Prescaler, Refresh window and Counter configuration functions
STM32F4xx_StdPeriph_Driver » WWDG » WWDG_Private_Functions
+
+
+ +

Prescaler, Refresh window and Counter configuration functions. +More...

+
+Collaboration diagram for Prescaler, Refresh window and Counter configuration functions:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

void WWDG_DeInit (void)
 Deinitializes the WWDG peripheral registers to their default reset values. More...
 
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
 Sets the WWDG Prescaler. More...
 
void WWDG_SetWindowValue (uint8_t WindowValue)
 Sets the WWDG window value. More...
 
void WWDG_EnableIT (void)
 Enables the WWDG Early Wakeup interrupt(EWI). More...
 
void WWDG_SetCounter (uint8_t Counter)
 Sets the WWDG counter value. More...
 
+

Detailed Description

+

Prescaler, Refresh window and Counter configuration functions.

+
 ===============================================================================
+    ##### Prescaler, Refresh window and Counter configuration functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void WWDG_DeInit (void )
+
+ +

Deinitializes the WWDG peripheral registers to their default reset values.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + + +
void WWDG_EnableIT (void )
+
+ +

Enables the WWDG Early Wakeup interrupt(EWI).

+
Note
Once enabled this interrupt cannot be disabled except by a system reset.
+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetCounter (uint8_t Counter)
+
+ +

Sets the WWDG counter value.

+
Parameters
+ + +
Counterspecifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
+
+ +

Sets the WWDG Prescaler.

+
Parameters
+ + +
WWDG_Prescalerspecifies the WWDG Prescaler. This parameter can be one of the following values:
    +
  • WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
    • +
  • WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
    • +
  • WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
    • +
  • WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
    • +
+
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void WWDG_SetWindowValue (uint8_t WindowValue)
+
+ +

Sets the WWDG window value.

+
Parameters
+ + +
WindowValuespecifies the window value to be compared to the downcounter. This parameter value must be lower than 0x80.
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___group1.map b/group___w_w_d_g___group1.map new file mode 100644 index 0000000..b0a6fc1 --- /dev/null +++ b/group___w_w_d_g___group1.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g___group1.md5 b/group___w_w_d_g___group1.md5 new file mode 100644 index 0000000..efb8896 --- /dev/null +++ b/group___w_w_d_g___group1.md5 @@ -0,0 +1 @@ +2ff1c4acc53badd2b97c2b6ffd30829e \ No newline at end of file diff --git a/group___w_w_d_g___group1.png b/group___w_w_d_g___group1.png new file mode 100644 index 0000000..f0fddb9 Binary files /dev/null and b/group___w_w_d_g___group1.png differ diff --git a/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map new file mode 100644 index 0000000..11a19e5 --- /dev/null +++ b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 new file mode 100644 index 0000000..15a4c00 --- /dev/null +++ b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 @@ -0,0 +1 @@ +4945c2a34c3d376576f28f0b575d2751 \ No newline at end of file diff --git a/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png new file mode 100644 index 0000000..a53a4c7 Binary files /dev/null and b/group___w_w_d_g___group1_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png differ diff --git a/group___w_w_d_g___group2.html b/group___w_w_d_g___group2.html new file mode 100644 index 0000000..8c83f63 --- /dev/null +++ b/group___w_w_d_g___group2.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: WWDG activation functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
WWDG activation functions
STM32F4xx_StdPeriph_Driver » WWDG » WWDG_Private_Functions
+
+
+ +

WWDG activation functions. +More...

+
+Collaboration diagram for WWDG activation functions:
+
+
+ + +
+
+ + + + + +

+Functions

void WWDG_Enable (uint8_t Counter)
 Enables WWDG and load the counter value. More...
 
+

Detailed Description

+

WWDG activation functions.

+
 ===============================================================================
+                    ##### WWDG activation function #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void WWDG_Enable (uint8_t Counter)
+
+ +

Enables WWDG and load the counter value.

+
Parameters
+ + +
Counterspecifies the watchdog counter value. This parameter must be a number between 0x40 and 0x7F (to prevent generating an immediate reset)
+
+
+
Return values
+ + +
None
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___group2.map b/group___w_w_d_g___group2.map new file mode 100644 index 0000000..7dfb96a --- /dev/null +++ b/group___w_w_d_g___group2.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g___group2.md5 b/group___w_w_d_g___group2.md5 new file mode 100644 index 0000000..ef9935d --- /dev/null +++ b/group___w_w_d_g___group2.md5 @@ -0,0 +1 @@ +552d90f0263bf89a5b0935b23c254f62 \ No newline at end of file diff --git a/group___w_w_d_g___group2.png b/group___w_w_d_g___group2.png new file mode 100644 index 0000000..2973f7c Binary files /dev/null and b/group___w_w_d_g___group2.png differ diff --git a/group___w_w_d_g___group3.html b/group___w_w_d_g___group3.html new file mode 100644 index 0000000..6766a79 --- /dev/null +++ b/group___w_w_d_g___group3.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: Interrupts and flags management functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Interrupts and flags management functions
STM32F4xx_StdPeriph_Driver » WWDG » WWDG_Private_Functions
+
+
+ +

Interrupts and flags management functions. +More...

+
+Collaboration diagram for Interrupts and flags management functions:
+
+
+ + +
+
+ + + + + + + + +

+Functions

FlagStatus WWDG_GetFlagStatus (void)
 Checks whether the Early Wakeup interrupt flag is set or not. More...
 
void WWDG_ClearFlag (void)
 Clears Early Wakeup interrupt flag. More...
 
+

Detailed Description

+

Interrupts and flags management functions.

+
 ===============================================================================
+            ##### Interrupts and flags management functions #####
+ ===============================================================================

Function Documentation

+ +
+
+ + + + + + + + +
void WWDG_ClearFlag (void )
+
+ +

Clears Early Wakeup interrupt flag.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
FlagStatus WWDG_GetFlagStatus (void )
+
+ +

Checks whether the Early Wakeup interrupt flag is set or not.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Thenew state of the Early Wakeup interrupt flag (SET or RESET)
+
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___group3.map b/group___w_w_d_g___group3.map new file mode 100644 index 0000000..193d6a5 --- /dev/null +++ b/group___w_w_d_g___group3.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g___group3.md5 b/group___w_w_d_g___group3.md5 new file mode 100644 index 0000000..0eff781 --- /dev/null +++ b/group___w_w_d_g___group3.md5 @@ -0,0 +1 @@ +ac9b4fba455942073dfe89adbef7234d \ No newline at end of file diff --git a/group___w_w_d_g___group3.png b/group___w_w_d_g___group3.png new file mode 100644 index 0000000..7cdf7e8 Binary files /dev/null and b/group___w_w_d_g___group3.png differ diff --git a/group___w_w_d_g___prescaler.html b/group___w_w_d_g___prescaler.html new file mode 100644 index 0000000..8c9667d --- /dev/null +++ b/group___w_w_d_g___prescaler.html @@ -0,0 +1,147 @@ + + + + + + +discoverpixy: WWDG_Prescaler + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
+
+ + +
+ +
+ +
+
+Macros
+
+
WWDG_Prescaler
STM32F4xx_StdPeriph_Driver » WWDG » WWDG_Exported_Constants
+
+
+
+Collaboration diagram for WWDG_Prescaler:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Macros

+#define WWDG_Prescaler_1   ((uint32_t)0x00000000)
 
+#define WWDG_Prescaler_2   ((uint32_t)0x00000080)
 
+#define WWDG_Prescaler_4   ((uint32_t)0x00000100)
 
+#define WWDG_Prescaler_8   ((uint32_t)0x00000180)
 
#define IS_WWDG_PRESCALER(PRESCALER)
 
+#define IS_WWDG_WINDOW_VALUE(VALUE)   ((VALUE) <= 0x7F)
 
+#define IS_WWDG_COUNTER(COUNTER)   (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
 
+

Detailed Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define IS_WWDG_PRESCALER( PRESCALER)
+
+Value:
(((PRESCALER) == WWDG_Prescaler_1) || \
+
((PRESCALER) == WWDG_Prescaler_2) || \
+
((PRESCALER) == WWDG_Prescaler_4) || \
+
((PRESCALER) == WWDG_Prescaler_8))
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___prescaler.map b/group___w_w_d_g___prescaler.map new file mode 100644 index 0000000..db29403 --- /dev/null +++ b/group___w_w_d_g___prescaler.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g___prescaler.md5 b/group___w_w_d_g___prescaler.md5 new file mode 100644 index 0000000..db197c6 --- /dev/null +++ b/group___w_w_d_g___prescaler.md5 @@ -0,0 +1 @@ +90823505c01c4372d58df28c1e45ce7c \ No newline at end of file diff --git a/group___w_w_d_g___prescaler.png b/group___w_w_d_g___prescaler.png new file mode 100644 index 0000000..0483199 Binary files /dev/null and b/group___w_w_d_g___prescaler.png differ diff --git a/group___w_w_d_g___private___functions.html b/group___w_w_d_g___private___functions.html new file mode 100644 index 0000000..6e62c0f --- /dev/null +++ b/group___w_w_d_g___private___functions.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: WWDG_Private_Functions + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Modules
+
+
WWDG_Private_Functions
STM32F4xx_StdPeriph_Driver » WWDG
+
+
+
+Collaboration diagram for WWDG_Private_Functions:
+
+
+ + +
+
+ + + + + + + + + + + +

+Modules

 Prescaler, Refresh window and Counter configuration functions
 Prescaler, Refresh window and Counter configuration functions.
 
 WWDG activation functions
 WWDG activation functions.
 
 Interrupts and flags management functions
 Interrupts and flags management functions.
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group___w_w_d_g___private___functions.map b/group___w_w_d_g___private___functions.map new file mode 100644 index 0000000..47ef2cb --- /dev/null +++ b/group___w_w_d_g___private___functions.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group___w_w_d_g___private___functions.md5 b/group___w_w_d_g___private___functions.md5 new file mode 100644 index 0000000..8a6b45b --- /dev/null +++ b/group___w_w_d_g___private___functions.md5 @@ -0,0 +1 @@ +ac06be072e6de55848519d0d905fb355 \ No newline at end of file diff --git a/group___w_w_d_g___private___functions.png b/group___w_w_d_g___private___functions.png new file mode 100644 index 0000000..6815ccb Binary files /dev/null and b/group___w_w_d_g___private___functions.png differ diff --git a/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map new file mode 100644 index 0000000..11a19e5 --- /dev/null +++ b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 new file mode 100644 index 0000000..15a4c00 --- /dev/null +++ b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.md5 @@ -0,0 +1 @@ +4945c2a34c3d376576f28f0b575d2751 \ No newline at end of file diff --git a/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png new file mode 100644 index 0000000..a53a4c7 Binary files /dev/null and b/group___w_w_d_g_ga7130f4dc861b9234b62e73f9f57f89a1_cgraph.png differ diff --git a/group__app.html b/group__app.html new file mode 100644 index 0000000..3959f64 --- /dev/null +++ b/group__app.html @@ -0,0 +1,167 @@ + + + + + + +discoverpixy: Application + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
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+
+Modules | +Functions
+
+
Application
+
+
+
+Collaboration diagram for Application:
+
+
+ + +
+
+ + + + +

+Modules

 Screens
 
+ + + + + +

+Functions

void app_init ()
 
void app_process ()
 
+

Detailed Description

+

The App Module contains the effective, platform independent application.

+

Function Documentation

+ +
+
+ + + + + + + +
void app_init ()
+
+

Starts/Initializes the app This function should be called at the top of the main function of your platform

+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + + + +
void app_process ()
+
+

Executes one cycle of the app Call this function repeatedly from a loop inside the main function

+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__app.map b/group__app.map new file mode 100644 index 0000000..2bc75f6 --- /dev/null +++ b/group__app.map @@ -0,0 +1,3 @@ + + + diff --git a/group__app.md5 b/group__app.md5 new file mode 100644 index 0000000..e1ff515 --- /dev/null +++ b/group__app.md5 @@ -0,0 +1 @@ +55b82d009ddec35bae997534b7da6175 \ No newline at end of file diff --git a/group__app.png b/group__app.png new file mode 100644 index 0000000..001ef50 Binary files /dev/null and b/group__app.png differ diff --git a/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.map b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.map new file mode 100644 index 0000000..090669f --- /dev/null +++ b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.md5 b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.md5 new file mode 100644 index 0000000..544a05c --- /dev/null +++ b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.md5 @@ -0,0 +1 @@ +9af81aa5c3b8fbe5ee35985fa4b0c5c7 \ No newline at end of file diff --git a/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.png b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.png new file mode 100644 index 0000000..9742f1f Binary files /dev/null and b/group__app_ga071d403b77a003f23a0d2ab1fbb67a36_cgraph.png differ diff --git a/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.map b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.map new file mode 100644 index 0000000..9c54735 --- /dev/null +++ b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.md5 b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.md5 new file mode 100644 index 0000000..2e43522 --- /dev/null +++ b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.md5 @@ -0,0 +1 @@ +1a9262877f0d71fcfae1c2f5c923c70a \ No newline at end of file diff --git a/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.png b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.png new file mode 100644 index 0000000..ca45ee3 Binary files /dev/null and b/group__app_ga8c6e58bb7e2a0dcf8537fc940ebfa385_cgraph.png differ diff --git a/group__appscreens.html b/group__appscreens.html new file mode 100644 index 0000000..07be419 --- /dev/null +++ b/group__appscreens.html @@ -0,0 +1,98 @@ + + + + + + +discoverpixy: Appscreens + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
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+ +
+
+ + +
+ +
+ +
+
+
Appscreens
App
+
+
+
+Collaboration diagram for Appscreens:
+
+
+ + +
+
+
+ +
+Generated on Sun May 10 2015 15:45:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__appscreens.map b/group__appscreens.map new file mode 100644 index 0000000..a1a2a25 --- /dev/null +++ b/group__appscreens.map @@ -0,0 +1,3 @@ + + + diff --git a/group__appscreens.md5 b/group__appscreens.md5 new file mode 100644 index 0000000..f4fa24a --- /dev/null +++ b/group__appscreens.md5 @@ -0,0 +1 @@ +0bf5a0d2f0e972cf0d8ff165142cadb3 \ No newline at end of file diff --git a/group__appscreens.png b/group__appscreens.png new file mode 100644 index 0000000..529afdd Binary files /dev/null and b/group__appscreens.png differ diff --git a/group__button.html b/group__button.html new file mode 100644 index 0000000..8bb64d1 --- /dev/null +++ b/group__button.html @@ -0,0 +1,287 @@ + + + + + + +discoverpixy: Button + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+Data Structures | +Macros | +Typedefs | +Functions
+
+
Button
Gui
+
+
+
+Collaboration diagram for Button:
+
+
+ + +
+
+ + + + +

+Data Structures

struct  BUTTON_STRUCT
 
+ + + + +

+Macros

#define AUTO   0
 Use this value instead of x2, y2 in the BUTTON_STRUCT to autocalculate the button width/height. More...
 
+ + + +

+Typedefs

typedef void(* BUTTON_CALLBACK) (void *button)
 
+ + + + + + + +

+Functions

bool gui_button_add (BUTTON_STRUCT *button)
 
void gui_button_remove (BUTTON_STRUCT *button)
 
void gui_button_redraw (BUTTON_STRUCT *button)
 
+

Detailed Description

+

The Button Gui-Element

+

Macro Definition Documentation

+ +
+
+ + + + +
#define AUTO   0
+
+ +

Use this value instead of x2, y2 in the BUTTON_STRUCT to autocalculate the button width/height.

+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* BUTTON_CALLBACK) (void *button)
+
+

Prototype for Event Listeners (called when the button is pressed)

Parameters
+ + +
buttonThe pointer to the BUTTON_STRUCT where to corresponding Button was pressed
+
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
bool gui_button_add (BUTTON_STRUCT * button)
+
+

Adds a button. Your Callback will be called from now on, if the button was pressed

Parameters
+ + +
buttonA Pointer to the preinitialized BUTTON_STRUCT
+
+
+
Returns
true on success
+ +

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void gui_button_redraw (BUTTON_STRUCT * button)
+
+

Redraws the button. Call this method if you have to redraw the entire screen or if you want to draw a button on top of an image.

Parameters
+ + +
buttonA Pointer to the BUTTON_STRUCT
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void gui_button_remove (BUTTON_STRUCT * button)
+
+

Removes the button. You will no longer receive events for this button. This function will not overdraw the region where the button was located.

Parameters
+ + +
buttonA Pointer to the BUTTON_STRUCT
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
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+
discoverpixy +
+
+
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+ + +
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+ +
+
+Data Structures | +Macros | +Typedefs | +Functions
+
+
Checkbox
Gui
+
+
+
+Collaboration diagram for Checkbox:
+
+
+ + +
+
+ + + + +

+Data Structures

struct  CHECKBOX_STRUCT
 
+ + + +

+Macros

#define CHECKBOX_WIN_FG_COLOR   RGB(32,161,34)
 
+ + + + +

+Typedefs

typedef void(* CHECKBOX_CALLBACK) (void *checkbox, bool checked)
 Function pointer used... More...
 
+ + + + + + + + + +

+Functions

bool gui_checkbox_add (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_remove (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_update (CHECKBOX_STRUCT *checkbox)
 
void gui_checkbox_redraw (CHECKBOX_STRUCT *checkbox)
 
+

Detailed Description

+

The Checkbox Gui-Element

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CHECKBOX_WIN_FG_COLOR   RGB(32,161,34)
+
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* CHECKBOX_CALLBACK) (void *checkbox, bool checked)
+
+ +

Function pointer used...

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
bool gui_checkbox_add (CHECKBOX_STRUCT * checkbox)
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void gui_checkbox_redraw (CHECKBOX_STRUCT * checkbox)
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void gui_checkbox_remove (CHECKBOX_STRUCT * checkbox)
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void gui_checkbox_update (CHECKBOX_STRUCT * checkbox)
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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a/group__filetest.html b/group__filetest.html new file mode 100644 index 0000000..85c157a --- /dev/null +++ b/group__filetest.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Filetest + + + + + + + + + + +
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discoverpixy +
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Filetest
Application » Screens
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+Collaboration diagram for Filetest:
+
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+Functions

SCREEN_STRUCT * get_screen_filetest ()
 
+

Detailed Description

+

The File-Test Screen tests the filesystem module. It read/writes from/to files and shows a bitmap

+

Function Documentation

+ +
+
+ + + + + + + +
SCREEN_STRUCT* get_screen_filetest ()
+
+

Returns a pointer to the filetest screen

See also
gui_screen_navigate
+
Returns
+ +

+Here is the caller graph for this function:
+
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+

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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__filetest.map b/group__filetest.map new file mode 100644 index 0000000..453e5a3 --- /dev/null +++ b/group__filetest.map @@ -0,0 +1,3 @@ + + + diff --git a/group__filetest.md5 b/group__filetest.md5 new file mode 100644 index 0000000..80b932d --- /dev/null +++ b/group__filetest.md5 @@ -0,0 +1 @@ +fc00a2831e53ca974d3c6aad97922d17 \ No newline at end of file diff --git a/group__filetest.png b/group__filetest.png new file mode 100644 index 0000000..4d3f45a Binary files /dev/null and b/group__filetest.png differ diff --git a/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map new file mode 100644 index 0000000..67d9b31 --- /dev/null +++ b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 new file mode 100644 index 0000000..02c33f3 --- /dev/null +++ b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 @@ -0,0 +1 @@ +aea667d65fcc686862e74aadd5929fd9 \ No newline at end of file diff --git a/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png new file mode 100644 index 0000000..3acd0bb Binary files /dev/null and b/group__filetest_gab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png differ diff --git a/group__gui.html b/group__gui.html new file mode 100644 index 0000000..8d19736 --- /dev/null +++ b/group__gui.html @@ -0,0 +1,459 @@ + + + + + + +discoverpixy: Gui + + + + + + + + + + +
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+Modules | +Variables
+
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Gui
+
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+Collaboration diagram for Gui:
+
+
+ + +
+
+ + + + + + + + + + +

+Modules

 Button
 
 Checkbox
 
 NummericUpDown
 
 Screen
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Variables

TOUCH_AREA_STRUCT base
 Basic geometry of the button. You only need to set the x1, y1, x2, y2 members of this struct. More...
 
uint16_t bgcolor
 The 16-bit background color of the button. More...
 
BUTTON_CALLBACK callback
 Callback. More...
 
uint16_t txtcolor
 The 16-bit text color. More...
 
uint8_t font
 The number of the font to use. More...
 
const char * text
 The label of the button. More...
 
TOUCH_AREA_STRUCT base
 
uint16_t fgcolor
 
bool checked
 
CHECKBOX_CALLBACK callback
 
uint16_t x
 
uint16_t y
 
uint16_t fgcolor
 
int16_t value
 
int16_t min
 
int16_t max
 
NUMUPDOWN_CALLBACK callback
 
BUTTON_STRUCT buttonUp
 
BUTTON_STRUCT buttonDown
 
SCREEN_CALLBACK on_enter
 
SCREEN_CALLBACK on_leave
 
SCREEN_CALLBACK on_update
 
struct SCREEN_S * next
 
+

Detailed Description

+

The Gui Module

+

Variable Documentation

+ +
+
+ + + + +
TOUCH_AREA_STRUCT base
+
+ +
+
+ +
+
+ + + + +
TOUCH_AREA_STRUCT base
+
+ +

Basic geometry of the button. You only need to set the x1, y1, x2, y2 members of this struct.

+ +
+
+ +
+
+ + + + +
uint16_t bgcolor
+
+ +

The 16-bit background color of the button.

+ +
+
+ +
+
+ + + + +
BUTTON_STRUCT buttonDown
+
+ +
+
+ +
+
+ + + + +
BUTTON_STRUCT buttonUp
+
+ +
+
+ +
+
+ + + + +
CHECKBOX_CALLBACK callback
+
+ +
+
+ +
+
+ + + + +
NUMUPDOWN_CALLBACK callback
+
+ +
+
+ +
+
+ + + + +
BUTTON_CALLBACK callback
+
+ +

Callback.

+ +
+
+ +
+
+ + + + +
bool checked
+
+ +
+
+ +
+
+ + + + +
uint16_t fgcolor
+
+ +
+
+ +
+
+ + + + +
uint16_t fgcolor
+
+ +
+
+ +
+
+ + + + +
uint8_t font
+
+ +

The number of the font to use.

+ +
+
+ +
+
+ + + + +
int16_t max
+
+ +
+
+ +
+
+ + + + +
int16_t min
+
+ +
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+ +
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+ + + + +
struct SCREEN_S* next
+
+ +
+
+ +
+
+ + + + +
SCREEN_CALLBACK on_enter
+
+ +
+
+ +
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+ + + + +
SCREEN_CALLBACK on_leave
+
+ +
+
+ +
+
+ + + + +
SCREEN_CALLBACK on_update
+
+ +
+
+ +
+
+ + + + +
const char* text
+
+ +

The label of the button.

+ +
+
+ +
+
+ + + + +
uint16_t txtcolor
+
+ +

The 16-bit text color.

+ +
+
+ +
+
+ + + + +
int16_t value
+
+ +
+
+ +
+
+ + + + +
uint16_t x
+
+ +
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+ +
+
+ + + + +
uint16_t y
+
+ +
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__gui.map b/group__gui.map new file mode 100644 index 0000000..98b122c --- /dev/null +++ b/group__gui.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/group__gui.md5 b/group__gui.md5 new file mode 100644 index 0000000..32e1847 --- /dev/null +++ b/group__gui.md5 @@ -0,0 +1 @@ +facff8307ad345f82086722ba129b8bd \ No newline at end of file diff --git a/group__gui.png b/group__gui.png new file mode 100644 index 0000000..7c5dd94 Binary files /dev/null and b/group__gui.png differ diff --git a/group__guitest.html b/group__guitest.html new file mode 100644 index 0000000..07bf2d5 --- /dev/null +++ b/group__guitest.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Guitest + + + + + + + + + + +
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discoverpixy +
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Guitest
Application » Screens
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+Collaboration diagram for Guitest:
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+
+ + + + +

+Functions

SCREEN_STRUCT * get_screen_guitest ()
 
+

Detailed Description

+

The Gui-Test Screen tests the gui and the tft module.

+

Function Documentation

+ +
+
+ + + + + + + +
SCREEN_STRUCT* get_screen_guitest ()
+
+

Returns a pointer to the guitest screen

See also
gui_screen_navigate
+
Returns
+ +

+Here is the caller graph for this function:
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__guitest.map b/group__guitest.map new file mode 100644 index 0000000..b0ce468 --- /dev/null +++ b/group__guitest.map @@ -0,0 +1,3 @@ + + + diff --git a/group__guitest.md5 b/group__guitest.md5 new file mode 100644 index 0000000..f0db10a --- /dev/null +++ b/group__guitest.md5 @@ -0,0 +1 @@ +fc1bbca54400bd12828f0f3887f3881e \ No newline at end of file diff --git a/group__guitest.png b/group__guitest.png new file mode 100644 index 0000000..02ff0b9 Binary files /dev/null and b/group__guitest.png differ diff --git a/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.map b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.map new file mode 100644 index 0000000..aae48c7 --- /dev/null +++ b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 new file mode 100644 index 0000000..bd0a053 --- /dev/null +++ b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 @@ -0,0 +1 @@ +a0aae466d9d5fec807e7d61f2dacc86f \ No newline at end of file diff --git a/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.png b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.png new file mode 100644 index 0000000..cb2ed06 Binary files /dev/null and b/group__guitest_ga75970b2a161e3fce8c6be83c96c75d98_icgraph.png differ diff --git a/group__latch___interrupt___request__selection.html b/group__latch___interrupt___request__selection.html new file mode 100644 index 0000000..57eb7af --- /dev/null +++ b/group__latch___interrupt___request__selection.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Latch_Interrupt_Request_selection + + + + + + + + + + +
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Latch_Interrupt_Request_selection
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Constants
+
+
+
+Collaboration diagram for Latch_Interrupt_Request_selection:
+
+
+ + +
+
+ + + + + + +

+Macros

+#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED   ((uint8_t)0x00)
 
+#define LIS302DL_INTERRUPTREQUEST_LATCHED   ((uint8_t)0x40)
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__latch___interrupt___request__selection.map b/group__latch___interrupt___request__selection.map new file mode 100644 index 0000000..cc62017 --- /dev/null +++ b/group__latch___interrupt___request__selection.map @@ -0,0 +1,3 @@ + + + diff --git a/group__latch___interrupt___request__selection.md5 b/group__latch___interrupt___request__selection.md5 new file mode 100644 index 0000000..8401bfb --- /dev/null +++ b/group__latch___interrupt___request__selection.md5 @@ -0,0 +1 @@ +29f26f8b3f68fca845832880f24887bd \ No newline at end of file diff --git a/group__latch___interrupt___request__selection.png b/group__latch___interrupt___request__selection.png new file mode 100644 index 0000000..09ba9eb Binary files /dev/null and b/group__latch___interrupt___request__selection.png differ diff --git a/group__main.html b/group__main.html new file mode 100644 index 0000000..8f056b0 --- /dev/null +++ b/group__main.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Main + + + + + + + + + + +
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+
+Functions
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+
Main
Application » Screens
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+
+
+Collaboration diagram for Main:
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+Functions

SCREEN_STRUCT * get_screen_main ()
 
+

Detailed Description

+

The Main Screen is the start-screen for the application

+

Function Documentation

+ +
+
+ + + + + + + +
SCREEN_STRUCT* get_screen_main ()
+
+

Returns a pointer to the main screen

See also
gui_screen_navigate
+
Returns
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
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+ + + + +
+ +
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+ + +
+ +
+ +
+
+Data Structures | +Typedefs | +Functions
+
+
NummericUpDown
Gui
+
+
+
+Collaboration diagram for NummericUpDown:
+
+
+ + +
+
+ + + + +

+Data Structures

struct  NUMUPDOWN_STRUCT
 
+ + + + +

+Typedefs

typedef void(* NUMUPDOWN_CALLBACK) (void *numupdown, int16_t value)
 Function pointer used... More...
 
+ + + + + + + + + +

+Functions

bool gui_numupdown_add (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_remove (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_update (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_redraw (NUMUPDOWN_STRUCT *numupdown)
 
+

Detailed Description

+

The NummericUpDown Gui Element

+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* NUMUPDOWN_CALLBACK) (void *numupdown, int16_t value)
+
+ +

Function pointer used...

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
bool gui_numupdown_add (NUMUPDOWN_STRUCT * numupdown)
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void gui_numupdown_redraw (NUMUPDOWN_STRUCT * numupdown)
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void gui_numupdown_remove (NUMUPDOWN_STRUCT * numupdown)
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void gui_numupdown_update (NUMUPDOWN_STRUCT * numupdown)
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
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+ +
+
+ + +
+ +
+ +
+
+Functions
+
+
Pixytest
Application » Screens
+
+
+
+Collaboration diagram for Pixytest:
+
+
+ + +
+
+ + + + +

+Functions

SCREEN_STRUCT * get_screen_pixytest ()
 
+

Detailed Description

+

The Pixy-Test Screen tests the pixy module.

+

Function Documentation

+ +
+
+ + + + + + + +
SCREEN_STRUCT* get_screen_pixytest ()
+
+

Returns a pointer to the pixytest screen

See also
gui_screen_navigate
+
Returns
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
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+
discoverpixy +
+
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+ + + + +
+ +
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+ +
+ +
+
+Data Structures | +Typedefs | +Functions
+
+
Screen
Gui
+
+
+
+Collaboration diagram for Screen:
+
+
+ + +
+
+ + + + +

+Data Structures

struct  SCREEN_S
 
+ + + + + + +

+Typedefs

typedef void(* SCREEN_CALLBACK) (void *screen)
 Function pointer used... More...
 
typedef struct SCREEN_S SCREEN_STRUCT
 
+ + + + + + + + + +

+Functions

bool gui_screen_navigate (SCREEN_STRUCT *screen)
 
bool gui_screen_back ()
 
SCREEN_STRUCT * gui_screen_get_current ()
 
void gui_screen_update ()
 
+

Detailed Description

+

The Screen Submodule

+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* SCREEN_CALLBACK) (void *screen)
+
+ +

Function pointer used...

+ +
+
+ +
+
+ + + + +
typedef struct SCREEN_S SCREEN_STRUCT
+
+ +
+
+

Function Documentation

+ +
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+ + + + + + + +
bool gui_screen_back ()
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SCREEN_STRUCT* gui_screen_get_current ()
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bool gui_screen_navigate (SCREEN_STRUCT * screen)
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void gui_screen_update ()
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+
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discoverpixy +
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+Modules
+
+
Screens
Application
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+
+
+Collaboration diagram for Screens:
+
+
+ + +
+
+ + + + + + + + + + +

+Modules

 Filetest
 
 Guitest
 
 Main
 
 Pixytest
 
+

Detailed Description

+

The Screens of the application.

See also
Screen
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
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+ +
+
+Modules
+
+
Stm32f4xx
CMSIS
+
+
+
+Collaboration diagram for Stm32f4xx:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Modules

 Library_configuration_section
 
 Configuration_section_for_CMSIS
 
 Exported_types
 
 Peripheral_registers_structures
 
 Peripheral_memory_map
 
 Peripheral_declaration
 
 Exported_constants
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:15:20 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__stm32f4xx.map b/group__stm32f4xx.map new file mode 100644 index 0000000..ccab135 --- /dev/null +++ b/group__stm32f4xx.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group__stm32f4xx.md5 b/group__stm32f4xx.md5 new file mode 100644 index 0000000..acb4392 --- /dev/null +++ b/group__stm32f4xx.md5 @@ -0,0 +1 @@ +c6dcc026b9966369a0872698eb7380e7 \ No newline at end of file diff --git a/group__stm32f4xx.png b/group__stm32f4xx.png new file mode 100644 index 0000000..336913b Binary files /dev/null and b/group__stm32f4xx.png differ diff --git a/group__stm32f4xx__system.html b/group__stm32f4xx__system.html new file mode 100644 index 0000000..d75f224 --- /dev/null +++ b/group__stm32f4xx__system.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: Stm32f4xx_system + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + +
+ +
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+ + +
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+ +
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+Modules
+
+
Stm32f4xx_system
CMSIS
+
+
+
+Collaboration diagram for Stm32f4xx_system:
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+
+ + +
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+ + + + + + + + + + + + + + + + +

+Modules

 STM32F4xx_System_Private_Includes
 
 STM32F4xx_System_Private_TypesDefinitions
 
 STM32F4xx_System_Private_Defines
 
 STM32F4xx_System_Private_Macros
 
 STM32F4xx_System_Private_Variables
 
 STM32F4xx_System_Private_FunctionPrototypes
 
 STM32F4xx_System_Private_Functions
 
+

Detailed Description

+
+ +
+Generated on Sun May 10 2015 15:16:14 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/group__stm32f4xx__system.map b/group__stm32f4xx__system.map new file mode 100644 index 0000000..26028a8 --- /dev/null +++ b/group__stm32f4xx__system.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/group__stm32f4xx__system.md5 b/group__stm32f4xx__system.md5 new file mode 100644 index 0000000..e8025aa --- /dev/null +++ b/group__stm32f4xx__system.md5 @@ -0,0 +1 @@ +3645d84037d9c12a64fcd9989cdc34c8 \ No newline at end of file diff --git a/group__stm32f4xx__system.png b/group__stm32f4xx__system.png new file mode 100644 index 0000000..9146b00 Binary files /dev/null and b/group__stm32f4xx__system.png differ diff --git a/group__system.html b/group__system.html new file mode 100644 index 0000000..955ddcc --- /dev/null +++ b/group__system.html @@ -0,0 +1,231 @@ + + + + + + +discoverpixy: System + + + + + + + + + + +
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discoverpixy +
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+ +
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+Functions
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+
System
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+ + + + + + + + + + +

+Functions

bool system_init ()
 
void system_delay (uint32_t msec)
 
void system_process ()
 
void system_toggle_led ()
 
+

Detailed Description

+

The System Module provides access to delay functions, leds and provides a system init function

+

Function Documentation

+ +
+
+ + + + + + + + +
void system_delay (uint32_t msec)
+
+

Sleeps for a certain amount of time

Parameters
+ + +
msecThe number of milliseconds to sleep
+
+
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bool system_init ()
+
+

Initializes the system. Call this method at the start of your app_init() function and before using any system_* functions

Returns
true on success
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void system_process ()
+
+

Executes pending system events (like handling usb, timers etc). Call this somewhere in app_process().

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void system_toggle_led ()
+
+

Toggles a Status Led. Use this function for debugging or to show activity

+ +

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+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + +
+ +
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+ + +
+ +
+ +
+
+Macros | +Functions
+
+
TFT
+
+
+ + + + + + + + + + + + + + + + + + +

+Macros

#define RGB(r, g, b)   ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3))
 
#define RED   RGB(255,0,0)
 
#define GREEN   RGB(0,255,0)
 
#define BLUE   RGB(0,0,255)
 
#define WHITE   0xF7BE
 
#define BLACK   RGB(0,0,0)
 
#define HEX(h)   (RGB(((h)>>16),((h)>>8),(h)))
 
#define TRANSPARENT   ((uint16_t)0x80C2)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

bool tft_init ()
 
void tft_clear (uint16_t color)
 
void tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t tft_num_fonts ()
 
uint8_t tft_font_height (uint8_t fontnum)
 
uint8_t tft_font_width (uint8_t fontnum)
 
void tft_print_line (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *text)
 
void tft_print_formatted (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *format,...)
 
+

Detailed Description

+

The TFT Modul provides access to the display

+

Macro Definition Documentation

+ +
+
+ + + + +
#define BLACK   RGB(0,0,0)
+
+ +
+
+ +
+
+ + + + +
#define BLUE   RGB(0,0,255)
+
+ +
+
+ +
+
+ + + + +
#define GREEN   RGB(0,255,0)
+
+ +
+
+ +
+
+ + + + + + + + +
#define HEX( h)   (RGB(((h)>>16),((h)>>8),(h)))
+
+

Creates a 16bit color from a 24bit hex rgb color code

Returns
+ +
+
+ +
+
+ + + + +
#define RED   RGB(255,0,0)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define RGB( r,
 g,
 b 
)   ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3))
+
+

Creates a 16bit color from 8bit * 3 colors (r,g,b)

Returns
+ +
+
+ +
+
+ + + + +
#define TRANSPARENT   ((uint16_t)0x80C2)
+
+

Transparent color

Returns
+ +
+
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#define WHITE   0xF7BE
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Function Documentation

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void tft_clear (uint16_t color)
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Clears the entire display with the given color. Overpaints everything which was there before.

Parameters
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colorThe 16-bit color to clear the display with.
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void tft_draw_bitmap_unscaled (uint16_t x,
uint16_t y,
uint16_t width,
uint16_t height,
const uint16_t * dat 
)
+
+

Draws a bitmap onto the display without scaling/cropping. The bitmap must be provided as an array of 16-bit colors

Parameters
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xThe x-coordinate of the top-left corner to draw the bitmap at
yThe y-coordinate of the top-left corner to draw the bitmap at
widthThe width of the bitmap in pixels
heightThe height of the bitmap in pixels
datA pointer to a uint16_t array containing the colors for each pixel. Starting in the topleft and going from left to right, line by line.
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void tft_draw_circle (uint16_t x,
uint16_t y,
uint16_t r,
uint16_t color 
)
+
+

Draws the outline of a circle onto the display

Parameters
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xThe x-Coordinate of the center point
yThe y-Coordinate of the center point
rThe Radius in Pixels
colorThe 16-Bit color to draw the circle with
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void tft_draw_line (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
+
+

Draws a line onto the display. The pixels specified by start/end point are inclusive!

Parameters
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x1The x-Coordinate of the start-point
y1The y-Coordinate of the start-point
x2The x-Coordinate of the end-point
y2The y-Coordinate of the end-point
colorThe 16-bit color to draw the line with
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void tft_draw_pixel (uint16_t x,
uint16_t y,
uint16_t color 
)
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+

Draws a pixel onto the display.

Parameters
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xThe x-Coordinate of the pixel
yThe y-Coordinate of the pixel
The16-bit color to draw the pixel with
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void tft_draw_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
+
+

Draws the outline of a rectangle onto the display. The outline is one pixel wide and goes through the specified start and endpoint.

Parameters
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x1The x-Coordinate of the start-point
y1The y-Coordinate of the start-point
x2The x-Coordinate of the end-point
y2The y-Coordinate of the end-point
The16-bit color to draw the pixel with
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void tft_fill_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
+
+

Draws a filled rectangle onto the display. The start,end points are inclusive

Parameters
+ + + + + + +
x1The x-Coordinate of the start-point
y1The y-Coordinate of the start-point
x2The x-Coordinate of the end-point
y2The y-Coordinate of the end-point
The16-bit color to draw the pixel with
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uint8_t tft_font_height (uint8_t fontnum)
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Get the height of a font

Parameters
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fontnumThe number of the font, from 0 .. (num_fonts -1)
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Returns
The height in pixel
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uint8_t tft_font_width (uint8_t fontnum)
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Get the width of a font

Parameters
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fontnumThe number of the font, from 0 .. (num_fonts -1)
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Returns
The width in pixel
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bool tft_init ()
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Initializes the display. Call this method before using any tft_* functions

Returns
true on success
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uint8_t tft_num_fonts ()
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Queries the number of available fonts

Returns
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void tft_print_formatted (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
uint8_t font,
const char * format,
 ... 
)
+
+

Prints a formatted text (like printf) onto the display

Parameters
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xThe x-Coordinate of the Top-Left corner where the text should be drawn
yThe y-Coordinate of the Top-Left corner where the text should be drawn
colorThe 16-bit foreground color of the text
bgcolorThe 16-bit background color of the text. You may pass TRANSPARENT as Color
fontThe Fontnum to use for drawing
formatThe format string (like printf)
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void tft_print_line (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
uint8_t font,
const char * text 
)
+
+

Prints a unformatted/preformatted string onto the display

Parameters
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xThe x-Coordinate of the Top-Left corner where the text should be drawn
yThe y-Coordinate of the Top-Left corner where the text should be drawn
colorThe 16-bit foreground color of the text
bgcolorThe 16-bit background color of the text. You may pass TRANSPARENT as Color
fontThe Fontnum to use for drawing
textThe text to draw
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
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+Data Structures | +Typedefs | +Enumerations | +Functions
+
+
Touch
+
+
+ + + + + + +

+Data Structures

struct  TOUCH_AREA_STRUCT
 
struct  POINT_STRUCT
 
+ + + +

+Typedefs

typedef void(* TOUCH_CALLBACK) (void *touchArea, TOUCH_ACTION triggeredAction)
 
+ + + + + +

+Enumerations

enum  TOUCH_STATE { TOUCH_UP, +TOUCH_DOWN + }
 
enum  TOUCH_ACTION {
+  NONE =0x00, +PEN_DOWN =0x01, +PEN_UP =0x02, +PEN_ENTER =0x04, +
+  PEN_LEAVE =0x08, +PEN_MOVE =0x10 +
+ }
 
+ + + + + + + + + + + + + +

+Functions

bool touch_init ()
 
bool touch_add_raw_event (uint16_t x, uint16_t y, TOUCH_STATE state)
 
bool touch_have_empty (unsigned char num)
 
bool touch_register_area (TOUCH_AREA_STRUCT *area)
 
void touch_unregister_area (TOUCH_AREA_STRUCT *area)
 
POINT_STRUCT touch_get_last_point ()
 
+

Detailed Description

+

The Touch module provides access to the touch controller, and executes a callback if a certain region is touched

+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* TOUCH_CALLBACK) (void *touchArea, TOUCH_ACTION triggeredAction)
+
+

Prototype for Event Listeners (called for every occurring, hooked action)

Parameters
+ + + +
touchAreaThe pointer to the TOUCH_AREA_STRUCT in which the event occurred
triggeredActionThe Action which occurred
+
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum TOUCH_ACTION
+
+

Enum to describe the hooked actions for which you want to receive events for. You can OR-combine them.

See also
touch_register_area
+ + + + + + + +
Enumerator
NONE  +

Do not receive any events.

+
PEN_DOWN  +

Receive an event when the pen goes down inside the region.

+
PEN_UP  +

Receive an event when the pen goes up inside the region.

+
PEN_ENTER  +

Receive an event when the pen enters the region (pen was down before)

+
PEN_LEAVE  +

Receive an event when the pen leaves the region (pen was inside region before)

+
PEN_MOVE  +

Receive an event when the pen moves inside the region (pen is down)

+
+ +
+
+ +
+
+ + + + +
enum TOUCH_STATE
+
+

Enum to describe the current Touch State.

See also
touch_add_raw_event
+ + + +
Enumerator
TOUCH_UP  +

The display is currently not touched.

+
TOUCH_DOWN  +

The display is currently touched at some point.

+
+ +
+
+

Function Documentation

+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + +
bool touch_add_raw_event (uint16_t x,
uint16_t y,
TOUCH_STATE state 
)
+
+

Processes a native touch event. Call this function when the pen goes down (TOUCH_DOWN), when it moves (TOUCH_DOWN) and also when it goes up again (TOUCH_UP)! It's safe to call this function from an (SPI)-Interrupt.

Parameters
+ + + + +
xThe x-Coordinate of the touch event
yThe y-Coordinate of the touch event
stateWhether the pen is up or down
+
+
+
Returns
True on success
+ +
+
+ +
+
+ + + + + + + +
POINT_STRUCT touch_get_last_point ()
+
+

Gets the last touched point

Returns
The Coordinates of the last touched points
+ +

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bool touch_have_empty (unsigned char num)
+
+

Checks whether or not we have memory to manage and track additional num TOUCH_AREA_STRUCTs

Parameters
+ + +
numThe number of touch areas you would like to allocate
+
+
+
Returns
True if there's enough memory to allocate num TOUCH_AREAs
+ +

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bool touch_init ()
+
+

Initializes the Touch Controller. Call this method before using any touch_* functions

Returns
true on success
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bool touch_register_area (TOUCH_AREA_STRUCT * area)
+
+

Registers a new touch Area. You will receive events for this area from now on.

Parameters
+ + +
areaA pointer to the configured TOUCH_AREA_STRUCT
+
+
+
Returns
True if everything was successful and the corresponding Touch Area will be monitored from now on
+ +

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void touch_unregister_area (TOUCH_AREA_STRUCT * area)
+
+

Unregisters a touch area. You will no longer receive events for this area

Parameters
+ + +
areaA pointer to the TOUCH_AREA_STRUCT instance
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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Class Hierarchy
+
+
+
+

Go to the graphical class hierarchy

+This inheritance list is sorted roughly, but not completely, alphabetically:
+
[detail level 12]
+ + + + + + + + + + + + + + + + +
 CBlock
 CBUTTON_STRUCT
 CCHECKBOX_STRUCT
 CDIRECTORY_STRUCT
 CFILE_DATE_STRUCT
 ▼CFILE_HANDLE
 CQT_FILE_HANDLE
 CFILE_STRUCT
 CFILE_TIME_STRUCT
 CMSC_Machine_TypeDef
 CNUMUPDOWN_STRUCT
 CPOINT_STRUCT
 ▼CQMainWindow
 CMainWindow
 CSCREEN_S
 CTOUCH_AREA_STRUCT
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/index.html b/index.html new file mode 100644 index 0000000..ca2bbab --- /dev/null +++ b/index.html @@ -0,0 +1,90 @@ + + + + + + +discoverpixy: Main Page + + + + + + + + + + +
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discoverpixy +
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+
discoverpixy Documentation
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+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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Class Hierarchy
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+

Go to the textual class hierarchy

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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(hl.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var 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t=c(this).data("resizable"),i=t.options,f=t.containerSize,p=t.containerOffset,m=t.size,n=t.position,r=t._aspectRatio||g.shiftKey,e={top:0,left:0},h=t.containerElement;if(h[0]!=document&&(/static/).test(h.css("position"))){e=p}if(n.left<(t._helper?p.left:0)){t.size.width=t.size.width+(t._helper?(t.position.left-p.left):(t.position.left-e.left));if(r){t.size.height=t.size.width/i.aspectRatio}t.position.left=i.helper?p.left:0}if(n.top<(t._helper?p.top:0)){t.size.height=t.size.height+(t._helper?(t.position.top-p.top):t.position.top);if(r){t.size.width=t.size.height*i.aspectRatio}t.position.top=t._helper?p.top:0}t.offset.left=t.parentData.left+t.position.left;t.offset.top=t.parentData.top+t.position.top;var l=Math.abs((t._helper?t.offset.left-e.left:(t.offset.left-e.left))+t.sizeDiff.width),s=Math.abs((t._helper?t.offset.top-e.top:(t.offset.top-p.top))+t.sizeDiff.height);var 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+
+
usbh_msc_core.h
+
+
+
1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_MSC_CORE_H
+
24 #define __USBH_MSC_CORE_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usbh_core.h"
+
28 #include "usbh_stdreq.h"
+
29 #include "usb_bsp.h"
+
30 #include "usbh_ioreq.h"
+
31 #include "usbh_hcs.h"
+
32 #include "usbh_msc_core.h"
+
33 #include "usbh_msc_scsi.h"
+
34 #include "usbh_msc_bot.h"
+
35 
+
59 /* Structure for MSC process */
+
60 typedef struct _MSC_Process
+
61 {
+
62  uint8_t hc_num_in;
+
63  uint8_t hc_num_out;
+
64  uint8_t MSBulkOutEp;
+
65  uint8_t MSBulkInEp;
+
66  uint16_t MSBulkInEpSize;
+
67  uint16_t MSBulkOutEpSize;
+
68  uint8_t buff[USBH_MSC_MPS_SIZE];
+
69  uint8_t maxLun;
+
70 }
+
71 MSC_Machine_TypeDef;
+
72 
+
73 
+
84 #define USB_REQ_BOT_RESET 0xFF
+
85 #define USB_REQ_GET_MAX_LUN 0xFE
+
86 
+
87 
+
102 extern USBH_Class_cb_TypeDef USBH_MSC_cb;
+
103 extern MSC_Machine_TypeDef MSC_Machine;
+
104 extern uint8_t MSCErrorCount;
+
105 
+
120 #endif /* __USBH_MSC_CORE_H */
+
121 
+
122 
+
138 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
139 
+
140 
+
141 
+
usb_bsp.h
Specific api's relative to the used hardware platform.
+
usbh_core.h
Header file for usbh_core.c.
+
usbh_stdreq.h
Header file for usbh_stdreq.c.
+
usbh_msc_bot.h
Header file for usbh_msc_bot.c.
+
usbh_ioreq.h
Header file for usbh_ioreq.c.
+
MSC_Machine_TypeDef
Definition: usbh_msc_core.c:33
+
_MSC_Process
Definition: usbh_msc_core.h:60
+
usbh_msc_scsi.h
Header file for usbh_msc_scsi.c.
+
usbh_hcs.h
Header file for usbh_hcs.c.
+
_USBH_Class_cb
Definition: usbh_core.h:174
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__filesystem_8c.html b/ll__filesystem_8c.html new file mode 100644 index 0000000..8a4fcad --- /dev/null +++ b/ll__filesystem_8c.html @@ -0,0 +1,301 @@ + + + + + + +discoverpixy: discovery/src/ll_filesystem.c File Reference + + + + + + + + + + +
+
+
+ + + + + +
+
discoverpixy +
+
+ + + + + + + +
+
+ + +
+ +
+ + + +
+
+Functions
+
+
ll_filesystem.c File Reference
+
+
+
#include "ll_filesystem.h"
+#include <stdio.h>
+
+Include dependency graph for ll_filesystem.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

bool ll_filesystem_init ()
 
DIRECTORY_STRUCT * ll_filesystem_dir_open (const char *path)
 
void ll_filesystem_dir_close (DIRECTORY_STRUCT *dir)
 
FILE_HANDLE * ll_filesystem_file_open (const char *filename)
 
void ll_filesystem_file_close (FILE_HANDLE *handle)
 
FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE *handle, uint32_t offset)
 
FILE_STATUS ll_filesystem_file_read (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
FILE_STATUS ll_filesystem_file_write (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
+

Function Documentation

+ +
+
+ + + + + + + + +
void ll_filesystem_dir_close (DIRECTORY_STRUCT * dir)
+
+ +
+
+ +
+
+ + + + + + + + +
DIRECTORY_STRUCT* ll_filesystem_dir_open (const char * path)
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+ + + + + + + + +
void ll_filesystem_file_close (FILE_HANDLE * handle)
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FILE_HANDLE* ll_filesystem_file_open (const char * filename)
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+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + +
FILE_STATUS ll_filesystem_file_read (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE * handle,
uint32_t offset 
)
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+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
FILE_STATUS ll_filesystem_file_write (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
+
+ +
+
+ +
+
+ + + + + + + +
bool ll_filesystem_init ()
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__filesystem_8c__incl.map b/ll__filesystem_8c__incl.map new file mode 100644 index 0000000..31008c5 --- /dev/null +++ b/ll__filesystem_8c__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/ll__filesystem_8c__incl.md5 b/ll__filesystem_8c__incl.md5 new file mode 100644 index 0000000..27e05c1 --- /dev/null +++ b/ll__filesystem_8c__incl.md5 @@ -0,0 +1 @@ +50824f6047939d23f6ec6e9c352b7879 \ No newline at end of file diff --git a/ll__filesystem_8c__incl.png b/ll__filesystem_8c__incl.png new file mode 100644 index 0000000..210723b Binary files /dev/null and b/ll__filesystem_8c__incl.png differ diff --git a/ll__filesystem_8cpp.html b/ll__filesystem_8cpp.html new file mode 100644 index 0000000..1ef1e19 --- /dev/null +++ b/ll__filesystem_8cpp.html @@ -0,0 +1,428 @@ + + + + + + +discoverpixy: emulator/qt/ll_filesystem.cpp File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Data Structures | +Functions
+
+
ll_filesystem.cpp File Reference
+
+
+
#include "ll_filesystem.h"
+#include <QFile>
+#include <QDir>
+#include <QDebug>
+#include <QFileInfoList>
+#include <QDateTime>
+
+Include dependency graph for ll_filesystem.cpp:
+
+
+ + +
+
+ + + +

+Data Structures

struct  QT_FILE_HANDLE
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

QDir rootdir ("./emulated")
 
bool ll_filesystem_init ()
 
DIRECTORY_STRUCT * ll_filesystem_dir_open (const char *path)
 
void ll_filesystem_dir_close (DIRECTORY_STRUCT *dir)
 
FILE_HANDLE * ll_filesystem_file_open (const char *filename)
 
void ll_filesystem_file_close (FILE_HANDLE *handle)
 
FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE *handle, uint32_t offset)
 
FILE_STATUS ll_filesystem_file_read (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
FILE_STATUS ll_filesystem_file_write (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
+

Function Documentation

+ +
+
+ + + + + + + + +
void ll_filesystem_dir_close (DIRECTORY_STRUCT * dir)
+
+ +
+
+ +
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+ + + + + + + + +
DIRECTORY_STRUCT* ll_filesystem_dir_open (const char * path)
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void ll_filesystem_file_close (FILE_HANDLE * handle)
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FILE_HANDLE* ll_filesystem_file_open (const char * filename)
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FILE_STATUS ll_filesystem_file_read (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE * handle,
uint32_t offset 
)
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FILE_STATUS ll_filesystem_file_write (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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bool ll_filesystem_init ()
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QDir rootdir ("./emulated" )
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+ +
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+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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ll_filesystem.h File Reference
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#include "filesystem.h"
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+Functions

bool ll_filesystem_init ()
 
DIRECTORY_STRUCT * ll_filesystem_dir_open (const char *path)
 
void ll_filesystem_dir_close (DIRECTORY_STRUCT *dir)
 
FILE_HANDLE * ll_filesystem_file_open (const char *filename)
 
void ll_filesystem_file_close (FILE_HANDLE *handle)
 
FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE *handle, uint32_t offset)
 
FILE_STATUS ll_filesystem_file_read (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
FILE_STATUS ll_filesystem_file_write (FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
 
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Function Documentation

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void ll_filesystem_dir_close (DIRECTORY_STRUCT * dir)
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DIRECTORY_STRUCT* ll_filesystem_dir_open (const char * path)
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void ll_filesystem_file_close (FILE_HANDLE * handle)
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FILE_HANDLE* ll_filesystem_file_open (const char * filename)
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FILE_STATUS ll_filesystem_file_read (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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FILE_STATUS ll_filesystem_file_seek (FILE_HANDLE * handle,
uint32_t offset 
)
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FILE_STATUS ll_filesystem_file_write (FILE_HANDLE * handle,
uint8_t * buf,
uint32_t size 
)
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bool ll_filesystem_init ()
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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ll_filesystem.h
+
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+Go to the documentation of this file.
1 #include "filesystem.h"
+
2 
+
3 bool ll_filesystem_init();
+
4 
+
5 DIRECTORY_STRUCT* ll_filesystem_dir_open(const char* path);
+
6 void ll_filesystem_dir_close(DIRECTORY_STRUCT* dir);
+
7 FILE_HANDLE* ll_filesystem_file_open(const char* filename);
+
8 void ll_filesystem_file_close(FILE_HANDLE* handle);
+
9 FILE_STATUS ll_filesystem_file_seek(FILE_HANDLE* handle, uint32_t offset);
+
10 FILE_STATUS ll_filesystem_file_read(FILE_HANDLE* handle, uint8_t* buf, uint32_t size);
+
11 FILE_STATUS ll_filesystem_file_write(FILE_HANDLE* handle, uint8_t* buf, uint32_t size);
+
ll_filesystem_file_seek
FILE_STATUS ll_filesystem_file_seek(FILE_HANDLE *handle, uint32_t offset)
+
FILE_HANDLE
Definition: filesystem.h:44
+
FILE_STATUS
FILE_STATUS
Definition: filesystem.h:50
+
ll_filesystem_file_open
FILE_HANDLE * ll_filesystem_file_open(const char *filename)
+ +
ll_filesystem_dir_close
void ll_filesystem_dir_close(DIRECTORY_STRUCT *dir)
+
ll_filesystem_file_close
void ll_filesystem_file_close(FILE_HANDLE *handle)
+
DIRECTORY_STRUCT
Definition: filesystem.h:38
+
ll_filesystem_file_write
FILE_STATUS ll_filesystem_file_write(FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
+
ll_filesystem_dir_open
DIRECTORY_STRUCT * ll_filesystem_dir_open(const char *path)
+
ll_filesystem_init
bool ll_filesystem_init()
+
ll_filesystem_file_read
FILE_STATUS ll_filesystem_file_read(FILE_HANDLE *handle, uint8_t *buf, uint32_t size)
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__system_8c.html b/ll__system_8c.html new file mode 100644 index 0000000..5bc4841 --- /dev/null +++ b/ll__system_8c.html @@ -0,0 +1,320 @@ + + + + + + +discoverpixy: discovery/src/ll_system.c File Reference + + + + + + + + + + +
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+Functions | +Variables
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ll_system.c File Reference
+
+
+
#include "ll_system.h"
+#include "stm32f4xx.h"
+#include "stm32f4_discovery.h"
+#include <stdio.h>
+#include "usb_hcd_int.h"
+#include "usbh_usr.h"
+#include "usbh_core.h"
+#include "usbh_msc_core.h"
+
+Include dependency graph for ll_system.c:
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+Functions

void SysTick_Handler (void)
 
void TIM2_IRQHandler (void)
 
void OTG_FS_IRQHandler (void)
 
bool ll_system_init (void)
 
void ll_system_process ()
 
void ll_system_delay (uint32_t msec)
 
void ll_system_toggle_led ()
 
+ + + + + + + +

+Variables

USB_OTG_CORE_HANDLE USB_OTG_Core
 
USBH_HOST USB_Host
 
RCC_ClocksTypeDef RCC_Clocks
 
+

Function Documentation

+ +
+
+ + + + + + + + +
void ll_system_delay (uint32_t msec)
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bool ll_system_init (void )
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void ll_system_process ()
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void ll_system_toggle_led ()
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void OTG_FS_IRQHandler (void )
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void SysTick_Handler (void )
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void TIM2_IRQHandler (void )
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Variable Documentation

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RCC_ClocksTypeDef RCC_Clocks
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USBH_HOST USB_Host
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USB_OTG_CORE_HANDLE USB_OTG_Core
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+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__system_8c__incl.map b/ll__system_8c__incl.map new file mode 100644 index 0000000..838a786 --- /dev/null +++ b/ll__system_8c__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/ll__system_8c__incl.md5 b/ll__system_8c__incl.md5 new file mode 100644 index 0000000..3e86fde --- /dev/null +++ b/ll__system_8c__incl.md5 @@ -0,0 +1 @@ +1093ac51eed62d4b2ae8ff6d43f72a16 \ No newline at end of file diff --git a/ll__system_8c__incl.png b/ll__system_8c__incl.png new file mode 100644 index 0000000..24f71a2 Binary files /dev/null and b/ll__system_8c__incl.png differ diff --git a/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.map b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.map new file mode 100644 index 0000000..1032b5f --- /dev/null +++ b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.md5 b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.md5 new file mode 100644 index 0000000..990137d --- /dev/null +++ b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.md5 @@ -0,0 +1 @@ +f5ea744a295ca1b7698b8167a0c74289 \ No newline at end of file diff --git a/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.png b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.png new file mode 100644 index 0000000..08207dd Binary files /dev/null and b/ll__system_8c_a02dc69a2258a680c99ace8167652ea91_cgraph.png differ diff --git a/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.map b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.map new file mode 100644 index 0000000..069cc13 --- /dev/null +++ b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.md5 b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.md5 new file mode 100644 index 0000000..dd9ab01 --- /dev/null +++ b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.md5 @@ -0,0 +1 @@ +23175299d25d48cd05c5ef5a9cdb53c1 \ No newline at end of file diff --git a/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.png b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.png new file mode 100644 index 0000000..f158c09 Binary files /dev/null and b/ll__system_8c_a38ad4725462bdc5e86c4ead4f04b9fc2_cgraph.png differ diff --git a/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.map b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.map new file mode 100644 index 0000000..abcdcd2 --- /dev/null +++ b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.md5 b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.md5 new file mode 100644 index 0000000..ae2a778 --- /dev/null +++ b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.md5 @@ -0,0 +1 @@ +84f71c10c8493983d8d49bbb1dca7f8b \ No newline at end of file diff --git a/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.png b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.png new file mode 100644 index 0000000..40b1650 Binary files /dev/null and b/ll__system_8c_ab5e09814056d617c521549e542639b7e_cgraph.png differ diff --git a/ll__system_8cpp.html b/ll__system_8cpp.html new file mode 100644 index 0000000..1902dad --- /dev/null +++ b/ll__system_8cpp.html @@ -0,0 +1,223 @@ + + + + + + +discoverpixy: emulator/qt/ll_system.cpp File Reference + + + + + + + + + + +
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ll_system.cpp File Reference
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#include <QThread>
+#include <QApplication>
+#include "ll_system.h"
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+Include dependency graph for ll_system.cpp:
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+Functions

bool ll_system_init ()
 
void ll_system_delay (uint32_t msec)
 
void ll_system_process ()
 
void ll_system_toggle_led ()
 
+

Function Documentation

+ +
+
+ + + + + + + + +
void ll_system_delay (uint32_t msec)
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bool ll_system_init (void )
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void ll_system_process ()
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void ll_system_toggle_led ()
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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ll_system.h File Reference
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#include <stdbool.h>
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+Functions

bool ll_system_init ()
 
void ll_system_delay (uint32_t msec)
 
void ll_system_process ()
 
void ll_system_toggle_led ()
 
+

Function Documentation

+ +
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void ll_system_delay (uint32_t msec)
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bool ll_system_init ()
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void ll_system_process ()
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void ll_system_toggle_led ()
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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ll_system.h
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+Go to the documentation of this file.
1 #include <stdbool.h>
+
2 #include <stdint.h>
+
3 
+
4 bool ll_system_init();
+
5 void ll_system_delay(uint32_t msec);
+
6 void ll_system_process();
+
7 void ll_system_toggle_led();
+
ll_system_init
bool ll_system_init()
+
ll_system_process
void ll_system_process()
+
ll_system_delay
void ll_system_delay(uint32_t msec)
+
ll_system_toggle_led
void ll_system_toggle_led()
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__tft_8c.html b/ll__tft_8c.html new file mode 100644 index 0000000..2056be8 --- /dev/null +++ b/ll__tft_8c.html @@ -0,0 +1,513 @@ + + + + + + +discoverpixy: discovery/src/ll_tft.c File Reference + + + + + + + + + + +
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ll_tft.c File Reference
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+
#include "ll_tft.h"
+
+Include dependency graph for ll_tft.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

bool ll_tft_init ()
 
void ll_tft_clear (uint16_t color)
 
void ll_tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void ll_tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void ll_tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t ll_tft_num_fonts ()
 
uint8_t ll_tft_font_height (uint8_t fontnum)
 
uint8_t ll_tft_font_width (uint8_t fontnum)
 
void ll_tft_draw_char (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, char c)
 
+

Function Documentation

+ +
+
+ + + + + + + + +
void ll_tft_clear (uint16_t color)
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void ll_tft_draw_bitmap_unscaled (uint16_t x,
uint16_t y,
uint16_t width,
uint16_t height,
const uint16_t * dat 
)
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void ll_tft_draw_char (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
uint8_t font,
char c 
)
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void ll_tft_draw_circle (uint16_t x,
uint16_t y,
uint16_t r,
uint16_t color 
)
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void ll_tft_draw_line (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + +
void ll_tft_draw_pixel (uint16_t x,
uint16_t y,
uint16_t color 
)
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void ll_tft_draw_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void ll_tft_fill_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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uint8_t ll_tft_font_height (uint8_t fontnum)
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uint8_t ll_tft_font_width (uint8_t fontnum)
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bool ll_tft_init ()
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uint8_t ll_tft_num_fonts ()
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ll__tft_8c__incl.map b/ll__tft_8c__incl.map new file mode 100644 index 0000000..b71ec9b --- /dev/null +++ b/ll__tft_8c__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/ll__tft_8c__incl.md5 b/ll__tft_8c__incl.md5 new file mode 100644 index 0000000..51b15e0 --- /dev/null +++ b/ll__tft_8c__incl.md5 @@ -0,0 +1 @@ +21c416f85645b18c14b354851fe05c40 \ No newline at end of file diff --git a/ll__tft_8c__incl.png b/ll__tft_8c__incl.png new file mode 100644 index 0000000..e23a1ac Binary files /dev/null and b/ll__tft_8c__incl.png differ diff --git a/ll__tft_8cpp.html b/ll__tft_8cpp.html new file mode 100644 index 0000000..22190ae --- /dev/null +++ b/ll__tft_8cpp.html @@ -0,0 +1,759 @@ + + + + + + +discoverpixy: emulator/qt/ll_tft.cpp File Reference + + + + + + + + + + +
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+Functions | +Variables
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+
ll_tft.cpp File Reference
+
+
+
#include "mainwindow.h"
+#include <QDebug>
+#include "ll_tft.h"
+
+Include dependency graph for ll_tft.cpp:
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+Functions

bool ll_tft_init ()
 
void ll_tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_clear (uint16_t color)
 
void ll_tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void ll_tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void ll_tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t ll_tft_num_fonts ()
 
QFont get_font (uint8_t fontnum)
 
uint8_t ll_tft_font_height (uint8_t fontnum)
 
uint8_t ll_tft_font_width (uint8_t fontnum)
 
void ll_tft_draw_char (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, char c)
 
+ + + +

+Variables

MainWindow * mainwindow
 
+

Function Documentation

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QFont get_font (uint8_t fontnum)
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void ll_tft_clear (uint16_t color)
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void ll_tft_draw_bitmap_unscaled (uint16_t x,
uint16_t y,
uint16_t width,
uint16_t height,
const uint16_t * dat 
)
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void ll_tft_draw_char (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
uint8_t font,
char c 
)
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void ll_tft_draw_circle (uint16_t x,
uint16_t y,
uint16_t r,
uint16_t color 
)
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void ll_tft_draw_line (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void ll_tft_draw_pixel (uint16_t x,
uint16_t y,
uint16_t color 
)
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void ll_tft_draw_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void ll_tft_fill_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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uint8_t ll_tft_font_height (uint8_t fontnum)
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uint8_t ll_tft_font_width (uint8_t fontnum)
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bool ll_tft_init ()
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uint8_t ll_tft_num_fonts ()
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Variable Documentation

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MainWindow* mainwindow
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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ll_tft.h File Reference
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#include <stdint.h>
+#include <stdbool.h>
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+Functions

bool ll_tft_init ()
 
void ll_tft_clear (uint16_t color)
 
void ll_tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void ll_tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void ll_tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void ll_tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t ll_tft_num_fonts ()
 
uint8_t ll_tft_font_height (uint8_t fontnum)
 
uint8_t ll_tft_font_width (uint8_t fontnum)
 
void ll_tft_draw_char (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, char c)
 
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Function Documentation

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void ll_tft_clear (uint16_t color)
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void ll_tft_draw_bitmap_unscaled (uint16_t x,
uint16_t y,
uint16_t width,
uint16_t height,
const uint16_t * dat 
)
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void ll_tft_draw_char (uint16_t x,
uint16_t y,
uint16_t color,
uint16_t bgcolor,
uint8_t font,
char c 
)
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void ll_tft_draw_circle (uint16_t x,
uint16_t y,
uint16_t r,
uint16_t color 
)
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void ll_tft_draw_line (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void ll_tft_draw_pixel (uint16_t x,
uint16_t y,
uint16_t color 
)
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void ll_tft_draw_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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void ll_tft_fill_rectangle (uint16_t x1,
uint16_t y1,
uint16_t x2,
uint16_t y2,
uint16_t color 
)
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uint8_t ll_tft_font_height (uint8_t fontnum)
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uint8_t ll_tft_font_width (uint8_t fontnum)
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bool ll_tft_init ()
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uint8_t ll_tft_num_fonts ()
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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a/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.md5 b/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.md5 new file mode 100644 index 0000000..7406f9b --- /dev/null +++ b/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.md5 @@ -0,0 +1 @@ +ab6dc4d9bdb98ac1cef3e8a30c2aa2f2 \ No newline at end of file diff --git a/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.png b/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.png new file mode 100644 index 0000000..3835b91 Binary files /dev/null and b/ll__tft_8h_afaf8d5f70b46fcbdd3c700a030f14b61_icgraph.png differ diff --git a/ll__tft_8h_source.html b/ll__tft_8h_source.html new file mode 100644 index 0000000..5d3ea94 --- /dev/null +++ b/ll__tft_8h_source.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: common/lowlevel/ll_tft.h Source File + + + + + + + + + + +
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ll_tft.h
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+Go to the documentation of this file.
1 #include <stdint.h>
+
2 #include <stdbool.h>
+
3 
+
4 // init functions
+
5 bool ll_tft_init();
+
6 
+
7 // draw functions
+
8 void ll_tft_clear(uint16_t color);
+
9 void ll_tft_draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color);
+
10 void ll_tft_draw_pixel(uint16_t x,uint16_t y,uint16_t color);
+
11 void ll_tft_draw_rectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint16_t color);
+
12 void ll_tft_fill_rectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint16_t color);
+
13 void ll_tft_draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat);
+
14 void ll_tft_draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color);
+
15 
+
16 
+
17 uint8_t ll_tft_num_fonts();
+
18 uint8_t ll_tft_font_height(uint8_t fontnum);
+
19 uint8_t ll_tft_font_width(uint8_t fontnum);
+
20 void ll_tft_draw_char(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, char c);
+
21 
+
22 
+
23 
+
24 
+
ll_tft_draw_line
void ll_tft_draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
+
ll_tft_clear
void ll_tft_clear(uint16_t color)
+
ll_tft_draw_char
void ll_tft_draw_char(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, char c)
+
ll_tft_fill_rectangle
void ll_tft_fill_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
+
ll_tft_font_height
uint8_t ll_tft_font_height(uint8_t fontnum)
+
ll_tft_font_width
uint8_t ll_tft_font_width(uint8_t fontnum)
+
ll_tft_draw_rectangle
void ll_tft_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
+
ll_tft_init
bool ll_tft_init()
+
ll_tft_num_fonts
uint8_t ll_tft_num_fonts()
+
ll_tft_draw_circle
void ll_tft_draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color)
+
ll_tft_draw_pixel
void ll_tft_draw_pixel(uint16_t x, uint16_t y, uint16_t color)
+
ll_tft_draw_bitmap_unscaled
void ll_tft_draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
+
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bool ll_touch_init ()
 
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bool ll_touch_init ()
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bool ll_touch_init ()
 
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bool ll_touch_init ()
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bool ll_touch_init ()
 
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bool ll_touch_init ()
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ll_touch_init
bool ll_touch_init()
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void app_init ()
 
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int main (int argc, char *argv[])
 
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mainwindow.cpp File Reference
+
+
+
#include "mainwindow.h"
+#include "ui_mainwindow.h"
+#include <QDebug>
+#include <QPainter>
+#include <math.h>
+#include <QMouseEvent>
+#include "touch.h"
+#include "tft.h"
+
+Include dependency graph for mainwindow.cpp:
+
+
+ + +
+
+ + + + + +

+Macros

#define DISPLAY_WIDTH   320
 
#define DISPLAY_HEIGHT   240
 
+ + + + + +

+Functions

QColor QColorFromRGB565 (uint16_t color)
 
QRgb QRgbFromRGB565 (uint16_t color)
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define DISPLAY_HEIGHT   240
+
+ +
+
+ +
+
+ + + + +
#define DISPLAY_WIDTH   320
+
+ +
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+

Function Documentation

+ +
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+ + + + + + + + +
QColor QColorFromRGB565 (uint16_t color)
+
+ +

+Here is the caller graph for this function:
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QRgb QRgbFromRGB565 (uint16_t color)
+
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/mainwindow_8cpp__incl.map b/mainwindow_8cpp__incl.map new file mode 100644 index 0000000..95cd9e4 --- /dev/null +++ b/mainwindow_8cpp__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/mainwindow_8cpp__incl.md5 b/mainwindow_8cpp__incl.md5 new file mode 100644 index 0000000..d396e39 --- /dev/null +++ b/mainwindow_8cpp__incl.md5 @@ -0,0 +1 @@ +a71e44834900a03613f9651eb8af163c \ No newline at end of file diff --git a/mainwindow_8cpp__incl.png b/mainwindow_8cpp__incl.png new file mode 100644 index 0000000..9cf26fa Binary files /dev/null and b/mainwindow_8cpp__incl.png differ diff --git a/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.map b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.map new file mode 100644 index 0000000..d480253 --- /dev/null +++ b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.md5 b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.md5 new file mode 100644 index 0000000..d79c4ce --- /dev/null +++ b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.md5 @@ -0,0 +1 @@ +afffad2c18368d83c9dfc1a6eb64aced \ No newline at end of file diff --git a/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.png b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.png new file mode 100644 index 0000000..1894f7a Binary files /dev/null and b/mainwindow_8cpp_ab8c1e3a91d2e8b988afea24b6ad49425_icgraph.png differ diff --git a/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.map b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.map new file mode 100644 index 0000000..fda74c3 --- /dev/null +++ b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.md5 b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.md5 new file mode 100644 index 0000000..9b21f45 --- /dev/null +++ b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.md5 @@ -0,0 +1 @@ +9212f1368479b7539097960a02bfa5c7 \ No newline at end of file diff --git a/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.png b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.png new file mode 100644 index 0000000..c245851 Binary files /dev/null and b/mainwindow_8cpp_ae66187ed2f21cc6d89422f49b344ddca_icgraph.png differ diff --git a/mainwindow_8h.html b/mainwindow_8h.html new file mode 100644 index 0000000..6af39ed --- /dev/null +++ b/mainwindow_8h.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: emulator/qt/mainwindow.h File Reference + + + + + + + + + + +
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+Data Structures | +Namespaces
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+
mainwindow.h File Reference
+
+
+
#include <QMainWindow>
+#include <QMutex>
+#include <stdint.h>
+
+Include dependency graph for mainwindow.h:
+
+
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

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+Data Structures

class  MainWindow
 
+ + + +

+Namespaces

 Ui
 
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/mainwindow_8h__dep__incl.map b/mainwindow_8h__dep__incl.map new file mode 100644 index 0000000..7c5afa6 --- /dev/null +++ b/mainwindow_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/mainwindow_8h__dep__incl.md5 b/mainwindow_8h__dep__incl.md5 new file mode 100644 index 0000000..2fd9057 --- /dev/null +++ b/mainwindow_8h__dep__incl.md5 @@ -0,0 +1 @@ +7f1573605405916d36533309f982b3c7 \ No newline at end of file diff --git a/mainwindow_8h__dep__incl.png b/mainwindow_8h__dep__incl.png new file mode 100644 index 0000000..52e5738 Binary files /dev/null and b/mainwindow_8h__dep__incl.png differ diff --git a/mainwindow_8h__incl.map b/mainwindow_8h__incl.map new file mode 100644 index 0000000..d9e4284 --- /dev/null +++ b/mainwindow_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/mainwindow_8h__incl.md5 b/mainwindow_8h__incl.md5 new file mode 100644 index 0000000..ecef046 --- /dev/null +++ b/mainwindow_8h__incl.md5 @@ -0,0 +1 @@ +397d73006a859cb93f8965a1c44dbf3e \ No newline at end of file diff --git a/mainwindow_8h__incl.png b/mainwindow_8h__incl.png new file mode 100644 index 0000000..97f4294 Binary files /dev/null and b/mainwindow_8h__incl.png differ diff --git a/mainwindow_8h_source.html b/mainwindow_8h_source.html new file mode 100644 index 0000000..4fde5c0 --- /dev/null +++ b/mainwindow_8h_source.html @@ -0,0 +1,168 @@ + + + + + + +discoverpixy: emulator/qt/mainwindow.h Source File + + + + + + + + + + +
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mainwindow.h
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+Go to the documentation of this file.
1 #ifndef MAINWINDOW_H
+
2 #define MAINWINDOW_H
+
3 
+
4 #include <QMainWindow>
+
5 #include <QMutex>
+
6 #include <stdint.h>
+
7 
+
8 namespace Ui {
+
9 class MainWindow;
+
10 }
+
11 
+
12 class MainWindow : public QMainWindow
+
13 {
+
14  Q_OBJECT
+
15 
+
16 public:
+
17  explicit MainWindow(QWidget *parent = 0);
+
18  void draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color);
+
19  void draw_pixel(uint16_t x,uint16_t y,uint16_t color);
+
20  void clear(uint16_t color);
+
21  void draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color);
+
22  void fill_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color);
+
23  void draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat);
+
24  void draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color);
+
25  void draw_char(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, QFont font, char c);
+
26 
+
27 protected:
+
28  void paintEvent(QPaintEvent * evt);
+
29  void mousePressEvent(QMouseEvent* evt);
+
30  void mouseReleaseEvent(QMouseEvent* evt);
+
31  void mouseMoveEvent(QMouseEvent* evt);
+
32  ~MainWindow();
+
33 
+
34 private slots:
+
35  void on_cboZoom_currentIndexChanged(int index);
+
36 
+
37 private:
+
38  //QMutex render_mutex;
+
39  QImage image;
+
40  int currentScale;
+
41  void checkAndSendEvent(QPoint pos, bool down);
+
42 
+
43  Ui::MainWindow *ui;
+
44 
+
45 };
+
46 #endif // MAINWINDOW_H
+
MainWindow::draw_char
void draw_char(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, QFont font, char c)
Definition: mainwindow.cpp:113
+
MainWindow::mousePressEvent
void mousePressEvent(QMouseEvent *evt)
Definition: mainwindow.cpp:146
+
MainWindow::fill_rectangle
void fill_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: mainwindow.cpp:75
+
MainWindow::MainWindow
MainWindow(QWidget *parent=0)
Definition: mainwindow.cpp:33
+
MainWindow::image
QImage image
Definition: mainwindow.h:39
+
MainWindow::draw_rectangle
void draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: mainwindow.cpp:65
+
MainWindow::ui
Ui::MainWindow * ui
Definition: mainwindow.h:43
+
Ui
Definition: mainwindow.h:8
+
MainWindow::draw_bitmap_unscaled
void draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
Definition: mainwindow.cpp:84
+
MainWindow::draw_line
void draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: mainwindow.cpp:39
+
MainWindow::on_cboZoom_currentIndexChanged
void on_cboZoom_currentIndexChanged(int index)
Definition: mainwindow.cpp:183
+
pos
volatile POINT_STRUCT pos
Definition: touch.c:8
+
MainWindow::paintEvent
void paintEvent(QPaintEvent *evt)
Definition: mainwindow.cpp:131
+
MainWindow::clear
void clear(uint16_t color)
Definition: mainwindow.cpp:57
+
MainWindow::mouseMoveEvent
void mouseMoveEvent(QMouseEvent *evt)
Definition: mainwindow.cpp:158
+
MainWindow::draw_circle
void draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color)
Definition: mainwindow.cpp:103
+
MainWindow::~MainWindow
~MainWindow()
Definition: mainwindow.cpp:166
+
MainWindow::draw_pixel
void draw_pixel(uint16_t x, uint16_t y, uint16_t color)
Definition: mainwindow.cpp:49
+
MainWindow::currentScale
int currentScale
Definition: mainwindow.h:40
+
MainWindow::checkAndSendEvent
void checkAndSendEvent(QPoint pos, bool down)
Definition: mainwindow.cpp:171
+
MainWindow
Definition: mainwindow.h:12
+
MainWindow::mouseReleaseEvent
void mouseReleaseEvent(QMouseEvent *evt)
Definition: mainwindow.cpp:152
+
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Project with the Pixy cam and the STM32F4 Discovery

+

Folder structure

+
    +
  • common: device independent code and the "Application" itself
    • +
  • emulator: display/touch/sd emulator written in qt. pixy can be connect via usb to computer
    • +
  • discovery: display/touch/sd/pixy can be connected to STM32F4Discovery
    • +
+

All code in the common folder MUST be device independent.

+

The folder common/lowlevel provides the function headers for the device specific code.

+

How to build

+

Go into the emulator or the discovery folder an use make

+
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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misc.c File Reference
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+ +

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions). +More...

+
#include "misc.h"
+
+Include dependency graph for misc.c:
+
+
+ + +
+
+ + + +

+Macros

+#define AIRCR_VECTKEY_MASK   ((uint32_t)0x05FA0000)
 
+ + + + + + + + + + + + + + + + +

+Functions

void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
 Configures the priority grouping: pre-emption priority and subpriority. More...
 
void NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
 Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. More...
 
void NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
 Sets the vector table location and Offset. More...
 
void NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
 Selects the condition for the system to enter low power mode. More...
 
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
 Configures the SysTick clock source. More...
 
+

Detailed Description

+

This file provides all the miscellaneous firmware functions (add-on to CMSIS functions).

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
*                               
+*          ===================================================================      
+*                        How to configure Interrupts using driver 
+*          ===================================================================      
+* 
+*            This section provide functions allowing to configure the NVIC interrupts (IRQ).
+*            The Cortex-M4 exceptions are managed by CMSIS functions.
+*
+*            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+*                function according to the following table.
+
+*  The table below gives the allowed values of the pre-emption priority and subpriority according
+*  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+*    ==========================================================================================================================
+*      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+*    ==========================================================================================================================
+*     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+*                           |                                   |                             | 4 bits for subpriority
+*    --------------------------------------------------------------------------------------------------------------------------
+*     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+*                           |                                   |                             | 3 bits for subpriority
+*    --------------------------------------------------------------------------------------------------------------------------    
+*     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+*                           |                                   |                             | 2 bits for subpriority
+*    --------------------------------------------------------------------------------------------------------------------------    
+*     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+*                           |                                   |                             | 1 bits for subpriority
+*    --------------------------------------------------------------------------------------------------------------------------    
+*     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
+*                           |                                   |                             | 0 bits for subpriority                       
+*    ==========================================================================================================================     
+*
+*            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+*
+* @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+*        The pending IRQ priority will be managed only by the subpriority.
+*
+* @note  IRQ priority order (sorted by highest to lowest priority):
+*         - Lowest pre-emption priority
+*         - Lowest subpriority
+*         - Lowest hardware priority (IRQ number)
+*
+*
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/misc_8c__incl.map b/misc_8c__incl.map new file mode 100644 index 0000000..5c3a69a --- /dev/null +++ b/misc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/misc_8c__incl.md5 b/misc_8c__incl.md5 new file mode 100644 index 0000000..4ad9f86 --- /dev/null +++ b/misc_8c__incl.md5 @@ -0,0 +1 @@ +2901b6d6e5403d057e4c1e57b71fc9d7 \ No newline at end of file diff --git a/misc_8c__incl.png b/misc_8c__incl.png new file mode 100644 index 0000000..fc87347 Binary files /dev/null and b/misc_8c__incl.png differ diff --git a/misc_8h.html b/misc_8h.html new file mode 100644 index 0000000..4bb6b65 --- /dev/null +++ b/misc_8h.html @@ -0,0 +1,210 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/misc.h File Reference + + + + + + + + + + +
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misc.h File Reference
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+ +

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions). +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for misc.h:
+
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

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+Classes

struct  NVIC_InitTypeDef
 NVIC Init Structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define NVIC_VectTab_RAM   ((uint32_t)0x20000000)
 
+#define NVIC_VectTab_FLASH   ((uint32_t)0x08000000)
 
#define IS_NVIC_VECTTAB(VECTTAB)
 
+#define NVIC_LP_SEVONPEND   ((uint8_t)0x10)
 
+#define NVIC_LP_SLEEPDEEP   ((uint8_t)0x04)
 
+#define NVIC_LP_SLEEPONEXIT   ((uint8_t)0x02)
 
#define IS_NVIC_LP(LP)
 
#define NVIC_PriorityGroup_0   ((uint32_t)0x700)
 
#define NVIC_PriorityGroup_1   ((uint32_t)0x600)
 
#define NVIC_PriorityGroup_2   ((uint32_t)0x500)
 
#define NVIC_PriorityGroup_3   ((uint32_t)0x400)
 
#define NVIC_PriorityGroup_4   ((uint32_t)0x300)
 
#define IS_NVIC_PRIORITY_GROUP(GROUP)
 
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)   ((PRIORITY) < 0x10)
 
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)   ((PRIORITY) < 0x10)
 
+#define IS_NVIC_OFFSET(OFFSET)   ((OFFSET) < 0x000FFFFF)
 
+#define SysTick_CLKSource_HCLK_Div8   ((uint32_t)0xFFFFFFFB)
 
+#define SysTick_CLKSource_HCLK   ((uint32_t)0x00000004)
 
#define IS_SYSTICK_CLK_SOURCE(SOURCE)
 
+ + + + + + + + + + + + + + + + +

+Functions

void NVIC_PriorityGroupConfig (uint32_t NVIC_PriorityGroup)
 Configures the priority grouping: pre-emption priority and subpriority. More...
 
void NVIC_Init (NVIC_InitTypeDef *NVIC_InitStruct)
 Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct. More...
 
void NVIC_SetVectorTable (uint32_t NVIC_VectTab, uint32_t Offset)
 Sets the vector table location and Offset. More...
 
void NVIC_SystemLPConfig (uint8_t LowPowerMode, FunctionalState NewState)
 Selects the condition for the system to enter low power mode. More...
 
void SysTick_CLKSourceConfig (uint32_t SysTick_CLKSource)
 Configures the SysTick clock source. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the miscellaneous firmware library functions (add-on to CMSIS functions).

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/misc_8h__dep__incl.map b/misc_8h__dep__incl.map new file mode 100644 index 0000000..4e234c9 --- /dev/null +++ b/misc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/misc_8h__dep__incl.md5 b/misc_8h__dep__incl.md5 new file mode 100644 index 0000000..2134ebe --- /dev/null +++ b/misc_8h__dep__incl.md5 @@ -0,0 +1 @@ +53e990c48e63d0e6ec9a77d13300c569 \ No newline at end of file diff --git a/misc_8h__dep__incl.png b/misc_8h__dep__incl.png new file mode 100644 index 0000000..37c06fa Binary files /dev/null and b/misc_8h__dep__incl.png differ diff --git a/misc_8h__incl.map b/misc_8h__incl.map new file mode 100644 index 0000000..773f41d --- /dev/null +++ b/misc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/misc_8h__incl.md5 b/misc_8h__incl.md5 new file mode 100644 index 0000000..90fa912 --- /dev/null +++ b/misc_8h__incl.md5 @@ -0,0 +1 @@ +8b293ed371ac0c4a382f646d297fc548 \ No newline at end of file diff --git a/misc_8h__incl.png b/misc_8h__incl.png new file mode 100644 index 0000000..01a91cd Binary files /dev/null and b/misc_8h__incl.png differ diff --git a/misc_8h_source.html b/misc_8h_source.html new file mode 100644 index 0000000..b4fc323 --- /dev/null +++ b/misc_8h_source.html @@ -0,0 +1,186 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/misc.h Source File + + + + + + + + + + +
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misc.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __MISC_H
+
31 #define __MISC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint8_t NVIC_IRQChannel;
+
61  uint8_t NVIC_IRQChannelPreemptionPriority;
+
66  uint8_t NVIC_IRQChannelSubPriority;
+
71  FunctionalState NVIC_IRQChannelCmd;
+
74 } NVIC_InitTypeDef;
+
75 
+
76 /* Exported constants --------------------------------------------------------*/
+
77 
+
86 #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+
87 #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+
88 #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+
89  ((VECTTAB) == NVIC_VectTab_FLASH))
+
90 
+
98 #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+
99 #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+
100 #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+
101 #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+
102  ((LP) == NVIC_LP_SLEEPDEEP) || \
+
103  ((LP) == NVIC_LP_SLEEPONEXIT))
+
104 
+
112 #define NVIC_PriorityGroup_0 ((uint32_t)0x700)
+
114 #define NVIC_PriorityGroup_1 ((uint32_t)0x600)
+
116 #define NVIC_PriorityGroup_2 ((uint32_t)0x500)
+
118 #define NVIC_PriorityGroup_3 ((uint32_t)0x400)
+
120 #define NVIC_PriorityGroup_4 ((uint32_t)0x300)
+
123 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+
124  ((GROUP) == NVIC_PriorityGroup_1) || \
+
125  ((GROUP) == NVIC_PriorityGroup_2) || \
+
126  ((GROUP) == NVIC_PriorityGroup_3) || \
+
127  ((GROUP) == NVIC_PriorityGroup_4))
+
128 
+
129 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
130 
+
131 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
132 
+
133 #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
134 
+
143 #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+
144 #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+
145 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+
146  ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+
147 
+
155 /* Exported macro ------------------------------------------------------------*/
+
156 /* Exported functions --------------------------------------------------------*/
+
157 
+
158 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+
159 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
160 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+
161 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+
162 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
163 
+
164 #ifdef __cplusplus
+
165 }
+
166 #endif
+
167 
+
168 #endif /* __MISC_H */
+
169 
+
178 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
NVIC_InitTypeDef::NVIC_IRQChannelSubPriority
uint8_t NVIC_IRQChannelSubPriority
Definition: misc.h:66
+
NVIC_Init
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
Initializes the NVIC peripheral according to the specified parameters in the NVIC_InitStruct.
Definition: misc.c:136
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
NVIC_SetVectorTable
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
Sets the vector table location and Offset.
Definition: misc.c:180
+
NVIC_InitTypeDef
NVIC Init Structure definition.
Definition: misc.h:54
+
NVIC_InitTypeDef::NVIC_IRQChannelCmd
FunctionalState NVIC_IRQChannelCmd
Definition: misc.h:71
+
NVIC_PriorityGroupConfig
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
Configures the priority grouping: pre-emption priority and subpriority.
Definition: misc.c:118
+
NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority
uint8_t NVIC_IRQChannelPreemptionPriority
Definition: misc.h:61
+
NVIC_SystemLPConfig
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
Selects the condition for the system to enter low power mode.
Definition: misc.c:199
+
SysTick_CLKSourceConfig
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
Configures the SysTick clock source.
Definition: misc.c:223
+
NVIC_InitTypeDef::NVIC_IRQChannel
uint8_t NVIC_IRQChannel
Definition: misc.h:56
+
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+
+Include dependency graph for moc_mainwindow.cpp:
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struct  qt_meta_stringdata_MainWindow_t
 
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#define QT_MOC_LITERAL(idx, ofs, len)
 
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static const qt_meta_stringdata_MainWindow_t qt_meta_stringdata_MainWindow
 
static const uint qt_meta_data_MainWindow []
 
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#define QT_MOC_LITERAL( idx,
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)
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Q_STATIC_BYTE_ARRAY_DATA_HEADER_INITIALIZER_WITH_OFFSET(len, \
+
qptrdiff(offsetof(qt_meta_stringdata_MainWindow_t, stringdata) + ofs \
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const uint qt_meta_data_MainWindow[]
+ 		+static
+
+Initial value:
= {
+
+
+
7,
+
0,
+
0, 0,
+
1, 14,
+
0, 0,
+
0, 0,
+
0, 0,
+
0,
+
0,
+
+
+
1, 1, 19, 2, 0x08 ,
+
+
+
QMetaType::Void, QMetaType::Int, 3,
+
+
0
+
}
+
+
+
+ +
+
+ + + + + +
+ + + + +
const qt_meta_stringdata_MainWindow_t qt_meta_stringdata_MainWindow
+ 		+static
+
+Initial value:
= {
+
{
+
QT_MOC_LITERAL(0, 0, 10),
+
QT_MOC_LITERAL(1, 11, 30),
+
QT_MOC_LITERAL(2, 42, 0),
+
QT_MOC_LITERAL(3, 43, 5)
+
+
},
+
"MainWindow\0on_cboZoom_currentIndexChanged\0"
+
"\0index"
+
}
+
QT_MOC_LITERAL
#define QT_MOC_LITERAL(idx, ofs, len)
Definition: moc_mainwindow.cpp:25
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+#include <sys/stat.h>
+#include <sys/times.h>
+#include <sys/unistd.h>
+#include "stm32f4xx.h"
+
+Include dependency graph for newlib_stubs.c:
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+Functions

int _write (int file, char *ptr, int len)
 
void _exit (int status)
 
int _close (int file)
 
int _execve (char *name, char **argv, char **env)
 
int _fork ()
 
int _fstat (int file, struct stat *st)
 
int _getpid ()
 
int _isatty (int file)
 
int _kill (int pid, int sig)
 
int _link (char *old, char *new)
 
int _lseek (int file, int ptr, int dir)
 
caddr_t _sbrk (int incr)
 
int _open (char *path, int flags,...)
 
int _read (int file, char *ptr, int len)
 
int _stat (const char *filepath, struct stat *st)
 
clock_t _times (struct tms *buf)
 
int _unlink (char *name)
 
int _wait (int *status)
 
+ + + + + + + +

+Variables

int errno
 
char * __env [1] = { 0 }
 
char ** environ = __env
 
+

Function Documentation

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int _close (int file)
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int _execve (char * name,
char ** argv,
char ** env 
)
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void _exit (int status)
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int _fork ()
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int _fstat (int file,
struct stat * st 
)
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int _getpid ()
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int _isatty (int file)
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int _kill (int pid,
int sig 
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int _link (char * old,
char * new 
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int _lseek (int file,
int ptr,
int dir 
)
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int _open (char * path,
int flags,
 ... 
)
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int _read (int file,
char * ptr,
int len 
)
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caddr_t _sbrk (int incr)
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int _stat (const char * filepath,
struct stat * st 
)
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clock_t _times (struct tms * buf)
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int _unlink (char * name)
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int _wait (int * status)
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int _write (int file,
char * ptr,
int len 
)
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Variable Documentation

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char* __env[1] = { 0 }
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char** environ = __env
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int errno
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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+ + + + + + +
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discoverpixy +
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+Macros | +Functions
+
+
numupdown.c File Reference
+
+
+
#include "tft.h"
+#include "touch.h"
+#include "button.h"
+#include "numupdown.h"
+#include <stdio.h>
+#include <stddef.h>
+#include <stdlib.h>
+
+Include dependency graph for numupdown.c:
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+Macros

#define BASE_COLOR   RGB(90,90,90)
 
+ + + + + + + + + + + + + + + +

+Functions

void button_up_cb (void *button)
 
void button_down_cb (void *button)
 
static uint8_t calc_text_width (int16_t val)
 
bool gui_numupdown_add (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_remove (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_update (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_redraw (NUMUPDOWN_STRUCT *numupdown)
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define BASE_COLOR   RGB(90,90,90)
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+ +
+
+

Function Documentation

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+
+ + + + + + + + +
void button_down_cb (void * button)
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void button_up_cb (void * button)
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static uint8_t calc_text_width (int16_t val)
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Data Structures | +Typedefs | +Functions
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numupdown.h File Reference
+
+
+
#include "button.h"
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+Include dependency graph for numupdown.h:
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

+ + + + +

+Data Structures

struct  NUMUPDOWN_STRUCT
 
+ + + + +

+Typedefs

typedef void(* NUMUPDOWN_CALLBACK) (void *numupdown, int16_t value)
 Function pointer used... More...
 
+ + + + + + + + + +

+Functions

bool gui_numupdown_add (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_remove (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_update (NUMUPDOWN_STRUCT *numupdown)
 
void gui_numupdown_redraw (NUMUPDOWN_STRUCT *numupdown)
 
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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numupdown.h
+
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+Go to the documentation of this file.
1 #ifndef NUMUPDOWN_H
+
2 #define NUMUPDOWN_H
+
3 
+
8 
+
14 
+
15 
+
16 #include "button.h"
+
17 
+
18 typedef void (*NUMUPDOWN_CALLBACK)(void *numupdown, int16_t value);
+
19 typedef struct {
+
20  uint16_t x;
+
21  uint16_t y;
+
22  uint16_t fgcolor;
+
23  int16_t value;
+
24  int16_t min;
+
25  int16_t max;
+
26  NUMUPDOWN_CALLBACK callback; //Callback
+
27 
+
28  //Internally used:
+
29  BUTTON_STRUCT buttonUp;
+
30  BUTTON_STRUCT buttonDown;
+
31 } NUMUPDOWN_STRUCT;
+
32 
+
33 
+
34 bool gui_numupdown_add(NUMUPDOWN_STRUCT* numupdown);
+
35 void gui_numupdown_remove(NUMUPDOWN_STRUCT* numupdown);
+
36 void gui_numupdown_update(NUMUPDOWN_STRUCT* numupdown);
+
37 void gui_numupdown_redraw(NUMUPDOWN_STRUCT* numupdown);
+
38 
+
41 #endif /* NUMUPDOWN_H */
+
BUTTON_STRUCT
Definition: button.h:30
+
NUMUPDOWN_STRUCT::min
int16_t min
Definition: numupdown.h:24
+ +
NUMUPDOWN_STRUCT
Definition: numupdown.h:19
+
NUMUPDOWN_STRUCT::buttonDown
BUTTON_STRUCT buttonDown
Definition: numupdown.h:30
+
NUMUPDOWN_CALLBACK
void(* NUMUPDOWN_CALLBACK)(void *numupdown, int16_t value)
Function pointer used...
Definition: numupdown.h:18
+
gui_numupdown_remove
void gui_numupdown_remove(NUMUPDOWN_STRUCT *numupdown)
Definition: numupdown.c:96
+
NUMUPDOWN_STRUCT::value
int16_t value
Definition: numupdown.h:23
+
NUMUPDOWN_STRUCT::x
uint16_t x
Definition: numupdown.h:20
+
NUMUPDOWN_STRUCT::callback
NUMUPDOWN_CALLBACK callback
Definition: numupdown.h:26
+
gui_numupdown_redraw
void gui_numupdown_redraw(NUMUPDOWN_STRUCT *numupdown)
Definition: numupdown.c:115
+
NUMUPDOWN_STRUCT::buttonUp
BUTTON_STRUCT buttonUp
Definition: numupdown.h:29
+
NUMUPDOWN_STRUCT::y
uint16_t y
Definition: numupdown.h:21
+
NUMUPDOWN_STRUCT::max
int16_t max
Definition: numupdown.h:25
+
gui_numupdown_update
void gui_numupdown_update(NUMUPDOWN_STRUCT *numupdown)
Definition: numupdown.c:102
+
NUMUPDOWN_STRUCT::fgcolor
uint16_t fgcolor
Definition: numupdown.h:22
+
gui_numupdown_add
bool gui_numupdown_add(NUMUPDOWN_STRUCT *numupdown)
Definition: numupdown.c:47
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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Related Pages
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Here is a list of all related documentation pages:
+ + +
 discoverpixy
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+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/pixy_8h.html b/pixy_8h.html new file mode 100644 index 0000000..5b05650 --- /dev/null +++ b/pixy_8h.html @@ -0,0 +1,1095 @@ + + + + + + +discoverpixy: common/pixy/pixy.h File Reference + + + + + + + + + + +
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discoverpixy +
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+Data Structures | +Macros | +Functions
+
+
pixy.h File Reference
+
+
+
#include <stdint.h>
+#include <unistd.h>
+#include "pixydefs.h"
+
+Include dependency graph for pixy.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
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+ + +
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+

Go to the source code of this file.

+ + + + +

+Data Structures

struct  Block
 
+ + + + + + + + + + + + + + + + + + + + + +

+Macros

#define PIXY_MAX_SIGNATURE   7
 
#define PIXY_MIN_X   0
 
#define PIXY_MAX_X   319
 
#define PIXY_MIN_Y   0
 
#define PIXY_MAX_Y   199
 
#define PIXY_RCS_MIN_POS   0
 
#define PIXY_RCS_MAX_POS   1000
 
#define PIXY_RCS_CENTER_POS   ((PIXY_RCS_MAX_POS-PIXY_RCS_MIN_POS)/2)
 
#define PIXY_BLOCKTYPE_NORMAL   0
 
#define PIXY_BLOCKTYPE_COLOR_CODE   1
 
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+Functions

int pixy_init ()
 Creates a connection with Pixy and listens for Pixy messages. More...
 
int pixy_blocks_are_new ()
 Indicates when new block data from Pixy is received. More...
 
int pixy_get_blocks (uint16_t max_blocks, struct Block *blocks)
 Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. More...
 
int pixy_service ()
 
int pixy_command (const char *name,...)
 Send a command to Pixy. More...
 
void pixy_close ()
 Terminates connection with Pixy. More...
 
void pixy_error (int error_code)
 Send description of pixy error to stdout. More...
 
int pixy_led_set_RGB (uint8_t red, uint8_t green, uint8_t blue)
 Set color of pixy LED. More...
 
int pixy_led_set_max_current (uint32_t current)
 Set pixy LED maximum current. More...
 
int pixy_led_get_max_current ()
 Get pixy LED maximum current. More...
 
int pixy_cam_set_auto_white_balance (uint8_t value)
 Enable or disable pixy camera auto white balance. More...
 
int pixy_cam_get_auto_white_balance ()
 Get pixy camera auto white balance setting. More...
 
uint32_t pixy_cam_get_white_balance_value ()
 Get pixy camera white balance() More...
 
int pixy_cam_set_white_balance_value (uint8_t red, uint8_t green, uint8_t blue)
 Set pixy camera white balance. More...
 
int pixy_cam_set_auto_exposure_compensation (uint8_t enable)
 Enable or disable pixy camera auto exposure compensation. More...
 
int pixy_cam_get_auto_exposure_compensation ()
 Get pixy camera auto exposure compensation setting. More...
 
int pixy_cam_set_exposure_compensation (uint8_t gain, uint16_t compensation)
 Set pixy camera exposure compensation. More...
 
int pixy_cam_get_exposure_compensation (uint8_t *gain, uint16_t *compensation)
 Get pixy camera exposure compensation. More...
 
int pixy_cam_set_brightness (uint8_t brightness)
 Set pixy camera brightness. More...
 
int pixy_cam_get_brightness ()
 Get pixy camera brightness. More...
 
int pixy_rcs_get_position (uint8_t channel)
 Get pixy servo axis position. More...
 
int pixy_rcs_set_position (uint8_t channel, uint16_t position)
 Set pixy servo axis position. More...
 
int pixy_rcs_set_frequency (uint16_t frequency)
 Set pixy servo pulse width modulation (PWM) frequency. More...
 
int pixy_get_firmware_version (uint16_t *major, uint16_t *minor, uint16_t *build)
 Get pixy firmware version. More...
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define PIXY_BLOCKTYPE_COLOR_CODE   1
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+ +
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+ +
+
+ + + + +
#define PIXY_BLOCKTYPE_NORMAL   0
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+ +
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+ +
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+ + + + +
#define PIXY_MAX_SIGNATURE   7
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+ +
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+ +
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+ + + + +
#define PIXY_MAX_X   319
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+ +
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+ +
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+ + + + +
#define PIXY_MAX_Y   199
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+ +
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+ +
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+ + + + +
#define PIXY_MIN_X   0
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+ +
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+ +
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+ + + + +
#define PIXY_MIN_Y   0
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+ +
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+ +
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+ + + + +
#define PIXY_RCS_CENTER_POS   ((PIXY_RCS_MAX_POS-PIXY_RCS_MIN_POS)/2)
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+ +
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+ + + + +
#define PIXY_RCS_MAX_POS   1000
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+ + + + +
#define PIXY_RCS_MIN_POS   0
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+ +
+
+

Function Documentation

+ +
+
+ + + + + + + +
int pixy_blocks_are_new ()
+
+ +

Indicates when new block data from Pixy is received.

+
Returns
1 New Data: Block data has been updated.
+
+0 Stale Data: Block data has not changed since pixy_get_blocks() was last called.
+ +
+
+ +
+
+ + + + + + + +
int pixy_cam_get_auto_exposure_compensation ()
+
+ +

Get pixy camera auto exposure compensation setting.

+
Returns
1 Auto exposure compensation enabled.
+
+0 Auto exposure compensation disabled.
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + +
int pixy_cam_get_auto_white_balance ()
+
+ +

Get pixy camera auto white balance setting.

+
Returns
1 Auto white balance is enabled.
+
+0 Auto white balance is disabled.
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + +
int pixy_cam_get_brightness ()
+
+ +

Get pixy camera brightness.

+
Returns
Non-negative Brightness value.
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int pixy_cam_get_exposure_compensation (uint8_t * gain,
uint16_t * compensation 
)
+
+ +

Get pixy camera exposure compensation.

+
Parameters
+ + + +
[out]gainCamera gain.
[out]compCamera exposure compensation.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + +
uint32_t pixy_cam_get_white_balance_value ()
+
+ +

Get pixy camera white balance()

+
Returns
Composite value for RGB white balance: white balance = green_value + (red_value << 8) + (blue << 16)
+ +
+
+ +
+
+ + + + + + + + +
int pixy_cam_set_auto_exposure_compensation (uint8_t enable)
+
+ +

Enable or disable pixy camera auto exposure compensation.

+
Parameters
+ + +
[in]enable0: Disable auto exposure compensation. 1: Enable auto exposure compensation.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + +
int pixy_cam_set_auto_white_balance (uint8_t value)
+
+ +

Enable or disable pixy camera auto white balance.

+
Parameters
+ + +
enable1: Enable white balance. 0: Disable white balance.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + +
int pixy_cam_set_brightness (uint8_t brightness)
+
+ +

Set pixy camera brightness.

+
Parameters
+ + +
[in]brightnessBrightness value.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int pixy_cam_set_exposure_compensation (uint8_t gain,
uint16_t compensation 
)
+
+ +

Set pixy camera exposure compensation.

+
Parameters
+ + + +
[in]gainCamera gain.
[in]compCamera exposure compensation.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int pixy_cam_set_white_balance_value (uint8_t red,
uint8_t green,
uint8_t blue 
)
+
+ +

Set pixy camera white balance.

+
Parameters
+ + + + +
[in]redRed white balance value.
[in]greenGreen white balance value.
[in]blueBlue white balance value.
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + +
void pixy_close ()
+
+ +

Terminates connection with Pixy.

+ +

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int pixy_command (const char * name,
 ... 
)
+
+ +

Send a command to Pixy.

+
Parameters
+ + +
[in]nameChirp remote procedure call identifier string.
+
+
+
Returns
-1 Error
+ +

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+ +
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+ +
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+ + + + + + + + +
void pixy_error (int error_code)
+
+ +

Send description of pixy error to stdout.

+
Parameters
+ + +
[in]error_codePixy error code
+
+
+ +
+
+ +
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int pixy_get_blocks (uint16_t max_blocks,
struct Block * blocks 
)
+
+ +

Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'.

+
Parameters
+ + + +
[in]max_blocksMaximum number of Blocks to copy to the address pointed to by 'blocks'.
[out]blocksAddress of an array in which to copy the blocks to. The array must be large enough to write 'max_blocks' number of Blocks to.
+
+
+
Returns
Non-negative Success: Number of blocks copied
+
+PIXY_ERROR_USB_IO USB Error: I/O
+
+PIXY_ERROR_NOT_FOUND USB Error: Pixy not found
+
+PIXY_ERROR_USB_BUSY USB Error: Busy
+
+PIXY_ERROR_USB_NO_DEVICE USB Error: No device
+
+PIXY_ERROR_INVALID_PARAMETER Invalid pararmeter specified
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int pixy_get_firmware_version (uint16_t * major,
uint16_t * minor,
uint16_t * build 
)
+
+ +

Get pixy firmware version.

+
Parameters
+ + + + +
[out]majorMajor version component
[out]minorMinor version component
[out]buildBuild identifier
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + +
int pixy_init ()
+
+ +

Creates a connection with Pixy and listens for Pixy messages.

+
Returns
0 Success
+
+PIXY_ERROR_USB_IO USB Error: I/O
+
+PIXY_ERROR_NOT_FOUND USB Error: Pixy not found
+
+PIXY_ERROR_USB_BUSY USB Error: Busy
+
+PIXY_ERROR_USB_NO_DEVICE USB Error: No device
+ +

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int pixy_led_get_max_current ()
+
+ +

Get pixy LED maximum current.

+
Returns
Non-negative Maximum LED current value (microamps).
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + +
int pixy_led_set_max_current (uint32_t current)
+
+ +

Set pixy LED maximum current.

+
Parameters
+ + +
[in]currentMaximum current (microamps).
+
+
+
Returns
0 Success
+
+Negative Error
+ +

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int pixy_led_set_RGB (uint8_t red,
uint8_t green,
uint8_t blue 
)
+
+ +

Set color of pixy LED.

+
Parameters
+ + + + +
[in]redBrightness value for red LED element. [0, 255] 0 = Off, 255 = On
[in]greenBrightness value for green LED element. [0, 255] 0 = Off, 255 = On
[in]blueBrightness value for blue LED element. [0, 255] 0 = Off, 255 = On
+
+
+
Returns
0 Success
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + +
int pixy_rcs_get_position (uint8_t channel)
+
+ +

Get pixy servo axis position.

+
Parameters
+ + +
channelChannel value. Range: [0, 1]
+
+
+
Returns
Position of channel. Range: [0, 999]
+
+Negative Error
+ +
+
+ +
+
+ + + + + + + + +
int pixy_rcs_set_frequency (uint16_t frequency)
+
+ +

Set pixy servo pulse width modulation (PWM) frequency.

+
Parameters
+ + +
frequencyRange: [20, 300] Hz Default: 50 Hz
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int pixy_rcs_set_position (uint8_t channel,
uint16_t position 
)
+
+ +

Set pixy servo axis position.

+
Parameters
+ + + +
channelChannel value. Range: [0, 1]
positionPosition value of the channel. Range: [0, 999]
+
+
+
Returns
0 Success
+
+Negative Error
+ +

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int pixy_service ()
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixy.h
+
+
+Go to the documentation of this file.
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __PIXY_H__
+
17 #define __PIXY_H__
+
18 
+
19 #include <stdint.h>
+
20 #include <unistd.h>
+
21 #include "pixydefs.h"
+
22 
+
23 // Pixy C API //
+
24 
+
25 #ifdef __cplusplus
+
26 extern "C"
+
27 {
+
28 #endif
+
29 
+
30  #define PIXY_MAX_SIGNATURE 7
+
31 
+
32  // Pixy x-y position values
+
33  #define PIXY_MIN_X 0
+
34  #define PIXY_MAX_X 319
+
35  #define PIXY_MIN_Y 0
+
36  #define PIXY_MAX_Y 199
+
37 
+
38  // RC-servo values
+
39  #define PIXY_RCS_MIN_POS 0
+
40  #define PIXY_RCS_MAX_POS 1000
+
41  #define PIXY_RCS_CENTER_POS ((PIXY_RCS_MAX_POS-PIXY_RCS_MIN_POS)/2)
+
42 
+
43  // Block types
+
44  #define PIXY_BLOCKTYPE_NORMAL 0
+
45  #define PIXY_BLOCKTYPE_COLOR_CODE 1
+
46 
+
47  struct Block
+
48  {
+
49  /*void print(char *buf)
+
50  {
+
51  int i, j;
+
52  char sig[6], d;
+
53  bool flag;
+
54  if (type==PIXY_BLOCKTYPE_COLOR_CODE)
+
55  {
+
56  // convert signature number to an octal string
+
57  for (i=12, j=0, flag=false; i>=0; i-=3)
+
58  {
+
59  d = (signature>>i)&0x07;
+
60  if (d>0 && !flag)
+
61  flag = true;
+
62  if (flag)
+
63  sig[j++] = d + '0';
+
64  }
+
65  sig[j] = '\0';
+
66  sprintf(buf, "CC block! sig: %s (%d decimal) x: %d y: %d width: %d height: %d angle %d", sig, signature, x, y, width, height, angle);
+
67  }
+
68  else // regular block. Note, angle is always zero, so no need to print
+
69  sprintf(buf, "sig: %d x: %d y: %d width: %d height: %d", signature, x, y, width, height);
+
70  }*/
+
71 
+
72  uint16_t type;
+
73  uint16_t signature;
+
74  uint16_t x;
+
75  uint16_t y;
+
76  uint16_t width;
+
77  uint16_t height;
+
78  int16_t angle;
+
79  };
+
80 
+
89  int pixy_init();
+
90 
+
98  int pixy_blocks_are_new();
+
99 
+
115  int pixy_get_blocks(uint16_t max_blocks, struct Block * blocks);
+
116 
+
117 
+
118 
+
119  int pixy_service();
+
120 
+
127  int pixy_command(const char *name, ...);
+
128 
+
132  void pixy_close();
+
133 
+
138  void pixy_error(int error_code);
+
139 
+
148  int pixy_led_set_RGB(uint8_t red, uint8_t green, uint8_t blue);
+
149 
+
156  int pixy_led_set_max_current(uint32_t current);
+
157 
+
163  int pixy_led_get_max_current();
+
164 
+
172  int pixy_cam_set_auto_white_balance(uint8_t value);
+
173 
+
180  int pixy_cam_get_auto_white_balance();
+
181 
+
187  uint32_t pixy_cam_get_white_balance_value();
+
188 
+
197  int pixy_cam_set_white_balance_value(uint8_t red, uint8_t green, uint8_t blue);
+
198 
+
206  int pixy_cam_set_auto_exposure_compensation(uint8_t enable);
+
207 
+
214  int pixy_cam_get_auto_exposure_compensation();
+
215 
+
223  int pixy_cam_set_exposure_compensation(uint8_t gain, uint16_t compensation);
+
224 
+
232  int pixy_cam_get_exposure_compensation(uint8_t * gain, uint16_t * compensation);
+
233 
+
240  int pixy_cam_set_brightness(uint8_t brightness);
+
241 
+
247  int pixy_cam_get_brightness();
+
248 
+
255  int pixy_rcs_get_position(uint8_t channel);
+
256 
+
264  int pixy_rcs_set_position(uint8_t channel, uint16_t position);
+
265 
+
270  int pixy_rcs_set_frequency(uint16_t frequency);
+
271 
+
280  int pixy_get_firmware_version(uint16_t * major, uint16_t * minor, uint16_t * build);
+
281 
+
282 #ifdef __cplusplus
+
283 }
+
284 #endif
+
285 
+
286 #endif
+
pixy_rcs_set_position
int pixy_rcs_set_position(uint8_t channel, uint16_t position)
Set pixy servo axis position.
+
pixy_cam_set_brightness
int pixy_cam_set_brightness(uint8_t brightness)
Set pixy camera brightness.
+
pixy_close
void pixy_close()
Terminates connection with Pixy.
+
Block::y
uint16_t y
Definition: pixy.h:75
+
pixy_get_firmware_version
int pixy_get_firmware_version(uint16_t *major, uint16_t *minor, uint16_t *build)
Get pixy firmware version.
+
pixy_cam_set_auto_white_balance
int pixy_cam_set_auto_white_balance(uint8_t value)
Enable or disable pixy camera auto white balance.
+
pixy_cam_get_white_balance_value
uint32_t pixy_cam_get_white_balance_value()
Get pixy camera white balance()
+
Block::type
uint16_t type
Definition: pixy.h:72
+
Block::height
uint16_t height
Definition: pixy.h:77
+
pixy_rcs_get_position
int pixy_rcs_get_position(uint8_t channel)
Get pixy servo axis position.
+
pixy_cam_get_auto_exposure_compensation
int pixy_cam_get_auto_exposure_compensation()
Get pixy camera auto exposure compensation setting.
+
pixy_cam_set_exposure_compensation
int pixy_cam_set_exposure_compensation(uint8_t gain, uint16_t compensation)
Set pixy camera exposure compensation.
+
pixy_cam_set_white_balance_value
int pixy_cam_set_white_balance_value(uint8_t red, uint8_t green, uint8_t blue)
Set pixy camera white balance.
+
pixy_cam_set_auto_exposure_compensation
int pixy_cam_set_auto_exposure_compensation(uint8_t enable)
Enable or disable pixy camera auto exposure compensation.
+
Block::width
uint16_t width
Definition: pixy.h:76
+
pixy_service
int pixy_service()
+
pixy_led_set_RGB
int pixy_led_set_RGB(uint8_t red, uint8_t green, uint8_t blue)
Set color of pixy LED.
+
pixy_led_get_max_current
int pixy_led_get_max_current()
Get pixy LED maximum current.
+
pixy_cam_get_auto_white_balance
int pixy_cam_get_auto_white_balance()
Get pixy camera auto white balance setting.
+
pixy_led_set_max_current
int pixy_led_set_max_current(uint32_t current)
Set pixy LED maximum current.
+
pixy_cam_get_exposure_compensation
int pixy_cam_get_exposure_compensation(uint8_t *gain, uint16_t *compensation)
Get pixy camera exposure compensation.
+
Block::signature
uint16_t signature
Definition: pixy.h:73
+
pixy_command
int pixy_command(const char *name,...)
Send a command to Pixy.
+
Block::x
uint16_t x
Definition: pixy.h:74
+
pixy_cam_get_brightness
int pixy_cam_get_brightness()
Get pixy camera brightness.
+
pixy_blocks_are_new
int pixy_blocks_are_new()
Indicates when new block data from Pixy is received.
+
Block
Definition: pixy.h:47
+ +
pixy_init
int pixy_init()
Creates a connection with Pixy and listens for Pixy messages.
+
pixy_error
void pixy_error(int error_code)
Send description of pixy error to stdout.
+
pixy_rcs_set_frequency
int pixy_rcs_set_frequency(uint16_t frequency)
Set pixy servo pulse width modulation (PWM) frequency.
+
pixy_get_blocks
int pixy_get_blocks(uint16_t max_blocks, struct Block *blocks)
Copies up to 'max_blocks' number of Blocks to the address pointed to by 'blocks'. ...
+
Block::angle
int16_t angle
Definition: pixy.h:78
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/pixydefs_8h.html b/pixydefs_8h.html new file mode 100644 index 0000000..ccde017 --- /dev/null +++ b/pixydefs_8h.html @@ -0,0 +1,990 @@ + + + + + + +discoverpixy: common/pixy/pixydefs.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros
+
+
pixydefs.h File Reference
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define PIXY_ERROR_INVALID_PARAMETER   -150
 
#define PIXY_ERROR_CHIRP   -151
 
#define PIXY_ERROR_INVALID_COMMAND   -152
 
#define CRP_ARRAY   0x80
 
#define CRP_FLT   0x10
 
#define CRP_NO_COPY   (0x10 | 0x20)
 
#define CRP_NULLTERM_ARRAY   (0x20 | CRP_ARRAY)
 
#define CRP_INT8   0x01
 
#define CRP_UINT8   0x01
 
#define CRP_INT16   0x02
 
#define CRP_UINT16   0x02
 
#define CRP_INT32   0x04
 
#define CRP_UINT32   0x04
 
#define CRP_FLT32   (CRP_FLT | 0x04)
 
#define CRP_FLT64   (CRP_FLT | 0x08)
 
#define CRP_STRING   (CRP_NULLTERM_ARRAY | CRP_INT8)
 
#define CRP_TYPE_HINT   0x64
 
#define CRP_INTS8   (CRP_INT8 | CRP_ARRAY)
 
#define CRP_INTS16   (CRP_INT16 | CRP_ARRAY)
 
#define CRP_INTS32   (CRP_INT32 | CRP_ARRAY)
 
#define CRP_UINTS8   CRP_INTS8
 
#define CRP_UINTS8_NO_COPY   (CRP_INTS8 | CRP_NO_COPY)
 
#define CRP_UINTS16_NO_COPY   (CRP_INTS16 | CRP_NO_COPY)
 
#define CRP_UINTS32_NO_COPY   (CRP_INTS32 | CRP_NO_COPY)
 
#define CRP_UINTS16   CRP_INTS16
 
#define CRP_UINTS32   CRP_INTS32
 
#define CRP_FLTS32   (CRP_FLT32 | CRP_ARRAY)
 
#define CRP_FLTS64   (CRP_FLT64 | CRP_ARRAY)
 
#define INT8(v)   CRP_INT8, v
 
#define UINT8(v)   CRP_INT8, v
 
#define INT16(v)   CRP_INT16, v
 
#define UINT16(v)   CRP_INT16, v
 
#define INT32(v)   CRP_INT32, v
 
#define UINT32(v)   CRP_INT32, v
 
#define FLT32(v)   CRP_FLT32, v
 
#define FLT64(v)   CRP_FLT64, v
 
#define STRING(s)   CRP_STRING, s
 
#define INTS8(len, a)   CRP_INTS8, len, a
 
#define UINTS8(len, a)   CRP_INTS8, len, a
 
#define UINTS8_NO_COPY(len)   CRP_UINTS8_NO_COPY, len
 
#define UINTS16_NO_COPY(len)   CRP_UINTS16_NO_COPY, len
 
#define UINTS32_NO_COPY(len)   CRP_UINTS32_NO_COPY, len
 
#define INTS16(len, a)   CRP_INTS16, len, a
 
#define UINTS16(len, a)   CRP_INTS16, len, a
 
#define INTS32(len, a)   CRP_INTS32, len, a
 
#define UINTS32(len, a)   CRP_INTS32, len, a
 
#define FLTS32(len, a)   CRP_FLTS32, len, a
 
#define FLTS64(len, a)   CRP_FLTS64, len, a
 
#define END   0
 
#define END_OUT_ARGS   END
 
#define END_IN_ARGS   END
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define CRP_ARRAY   0x80
+
+ +
+
+ +
+
+ + + + +
#define CRP_FLT   0x10
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+ +
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+ +
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+ + + + +
#define CRP_FLT32   (CRP_FLT | 0x04)
+
+ +
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+ +
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+ + + + +
#define CRP_FLT64   (CRP_FLT | 0x08)
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+ +
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+ +
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+ + + + +
#define CRP_FLTS32   (CRP_FLT32 | CRP_ARRAY)
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+ +
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+ +
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+ + + + +
#define CRP_FLTS64   (CRP_FLT64 | CRP_ARRAY)
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+ +
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+ +
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+ + + + +
#define CRP_INT16   0x02
+
+ +
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+ +
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+ + + + +
#define CRP_INT32   0x04
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+ +
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+ +
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+ + + + +
#define CRP_INT8   0x01
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+ +
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+ +
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+ + + + +
#define CRP_INTS16   (CRP_INT16 | CRP_ARRAY)
+
+ +
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+ +
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+ + + + +
#define CRP_INTS32   (CRP_INT32 | CRP_ARRAY)
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+ +
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+ +
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+ + + + +
#define CRP_INTS8   (CRP_INT8 | CRP_ARRAY)
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+ +
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+ +
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+ + + + +
#define CRP_NO_COPY   (0x10 | 0x20)
+
+ +
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+ + + + +
#define CRP_NULLTERM_ARRAY   (0x20 | CRP_ARRAY)
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+ +
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#define CRP_STRING   (CRP_NULLTERM_ARRAY | CRP_INT8)
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+ +
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#define CRP_TYPE_HINT   0x64
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+ +
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+ +
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+ + + + +
#define CRP_UINT16   0x02
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+ +
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+ +
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+ + + + +
#define CRP_UINT32   0x04
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+ +
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+ +
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+ + + + +
#define CRP_UINT8   0x01
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+ +
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+ +
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+ + + + +
#define CRP_UINTS16   CRP_INTS16
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+ +
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+ +
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+ + + + +
#define CRP_UINTS16_NO_COPY   (CRP_INTS16 | CRP_NO_COPY)
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+ +
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+ +
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+ + + + +
#define CRP_UINTS32   CRP_INTS32
+
+ +
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+ +
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+ + + + +
#define CRP_UINTS32_NO_COPY   (CRP_INTS32 | CRP_NO_COPY)
+
+ +
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+ +
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+ + + + +
#define CRP_UINTS8   CRP_INTS8
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+ +
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+ +
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+ + + + +
#define CRP_UINTS8_NO_COPY   (CRP_INTS8 | CRP_NO_COPY)
+
+ +
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+ +
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+ + + + +
#define END   0
+
+ +
+
+ +
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#define END_IN_ARGS   END
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+ +
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+ +
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+ + + + +
#define END_OUT_ARGS   END
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+ +
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+ +
+
+ + + + + + + + +
#define FLT32( v)   CRP_FLT32, v
+
+ +
+
+ +
+
+ + + + + + + + +
#define FLT64( v)   CRP_FLT64, v
+
+ +
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+ +
+
+ + + + + + + + + + + + + + + + + + +
#define FLTS32( len,
 a 
)   CRP_FLTS32, len, a
+
+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + +
#define FLTS64( len,
 a 
)   CRP_FLTS64, len, a
+
+ +
+
+ +
+
+ + + + + + + + +
#define INT16( v)   CRP_INT16, v
+
+ +
+
+ +
+
+ + + + + + + + +
#define INT32( v)   CRP_INT32, v
+
+ +
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+ +
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+ + + + + + + + +
#define INT8( v)   CRP_INT8, v
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+ +
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+ +
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#define INTS16( len,
 a 
)   CRP_INTS16, len, a
+
+ +
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+ +
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#define INTS32( len,
 a 
)   CRP_INTS32, len, a
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#define INTS8( len,
 a 
)   CRP_INTS8, len, a
+
+ +
+
+ +
+
+ + + + +
#define PIXY_ERROR_CHIRP   -151
+
+ +
+
+ +
+
+ + + + +
#define PIXY_ERROR_INVALID_COMMAND   -152
+
+ +
+
+ +
+
+ + + + +
#define PIXY_ERROR_INVALID_PARAMETER   -150
+
+ +
+
+ +
+
+ + + + + + + + +
#define STRING( s)   CRP_STRING, s
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINT16( v)   CRP_INT16, v
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINT32( v)   CRP_INT32, v
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINT8( v)   CRP_INT8, v
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define UINTS16( len,
 a 
)   CRP_INTS16, len, a
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINTS16_NO_COPY( len)   CRP_UINTS16_NO_COPY, len
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define UINTS32( len,
 a 
)   CRP_INTS32, len, a
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINTS32_NO_COPY( len)   CRP_UINTS32_NO_COPY, len
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define UINTS8( len,
 a 
)   CRP_INTS8, len, a
+
+ +
+
+ +
+
+ + + + + + + + +
#define UINTS8_NO_COPY( len)   CRP_UINTS8_NO_COPY, len
+
+ +
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/pixydefs_8h__dep__incl.map b/pixydefs_8h__dep__incl.map new file mode 100644 index 0000000..f07a07f --- /dev/null +++ b/pixydefs_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/pixydefs_8h__dep__incl.md5 b/pixydefs_8h__dep__incl.md5 new file mode 100644 index 0000000..f657056 --- /dev/null +++ b/pixydefs_8h__dep__incl.md5 @@ -0,0 +1 @@ +22b539e058c8855629228d6654970031 \ No newline at end of file diff --git a/pixydefs_8h__dep__incl.png b/pixydefs_8h__dep__incl.png new file mode 100644 index 0000000..a6221a9 Binary files /dev/null and b/pixydefs_8h__dep__incl.png differ diff --git a/pixydefs_8h_source.html b/pixydefs_8h_source.html new file mode 100644 index 0000000..8004998 --- /dev/null +++ b/pixydefs_8h_source.html @@ -0,0 +1,192 @@ + + + + + + +discoverpixy: common/pixy/pixydefs.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
pixydefs.h
+
+
+Go to the documentation of this file.
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __PIXYDEFS_H__
+
17 #define __PIXYDEFS_H__
+
18 
+
19 //#include "libusb.h"
+
20 
+
21 //#define PIXY_VID 0xB1AC
+
22 //#define PIXY_DID 0xF000
+
23 //#define PIXY_DFU_VID 0x1FC9
+
24 //#define PIXY_DFU_DID 0x000C
+
25 
+
26 //#define PIXY_ERROR_USB_IO LIBUSB_ERROR_IO
+
27 //#define PIXY_ERROR_USB_NOT_FOUND LIBUSB_ERROR_NOT_FOUND
+
28 //#define PIXY_ERROR_USB_BUSY LIBUSB_ERROR_BUSY
+
29 //#define PIXY_ERROR_USB_NO_DEVICE LIBUSB_ERROR_NO_DEVICE
+
30 #define PIXY_ERROR_INVALID_PARAMETER -150
+
31 #define PIXY_ERROR_CHIRP -151
+
32 #define PIXY_ERROR_INVALID_COMMAND -152
+
33 
+
34 #define CRP_ARRAY 0x80 // bit
+
35 #define CRP_FLT 0x10 // bit
+
36 #define CRP_NO_COPY (0x10 | 0x20)
+
37 #define CRP_NULLTERM_ARRAY (0x20 | CRP_ARRAY) // bits
+
38 #define CRP_INT8 0x01
+
39 #define CRP_UINT8 0x01
+
40 #define CRP_INT16 0x02
+
41 #define CRP_UINT16 0x02
+
42 #define CRP_INT32 0x04
+
43 #define CRP_UINT32 0x04
+
44 #define CRP_FLT32 (CRP_FLT | 0x04)
+
45 #define CRP_FLT64 (CRP_FLT | 0x08)
+
46 #define CRP_STRING (CRP_NULLTERM_ARRAY | CRP_INT8)
+
47 #define CRP_TYPE_HINT 0x64 // type hint identifier
+
48 #define CRP_INTS8 (CRP_INT8 | CRP_ARRAY)
+
49 #define CRP_INTS16 (CRP_INT16 | CRP_ARRAY)
+
50 #define CRP_INTS32 (CRP_INT32 | CRP_ARRAY)
+
51 #define CRP_UINTS8 CRP_INTS8
+
52 #define CRP_UINTS8_NO_COPY (CRP_INTS8 | CRP_NO_COPY)
+
53 #define CRP_UINTS16_NO_COPY (CRP_INTS16 | CRP_NO_COPY)
+
54 #define CRP_UINTS32_NO_COPY (CRP_INTS32 | CRP_NO_COPY)
+
55 #define CRP_UINTS16 CRP_INTS16
+
56 #define CRP_UINTS32 CRP_INTS32
+
57 #define CRP_FLTS32 (CRP_FLT32 | CRP_ARRAY)
+
58 #define CRP_FLTS64 (CRP_FLT64 | CRP_ARRAY)
+
59 
+
60 // regular call args
+
61 #define INT8(v) CRP_INT8, v
+
62 #define UINT8(v) CRP_INT8, v
+
63 #define INT16(v) CRP_INT16, v
+
64 #define UINT16(v) CRP_INT16, v
+
65 #define INT32(v) CRP_INT32, v
+
66 #define UINT32(v) CRP_INT32, v
+
67 #define FLT32(v) CRP_FLT32, v
+
68 #define FLT64(v) CRP_FLT64, v
+
69 #define STRING(s) CRP_STRING, s
+
70 #define INTS8(len, a) CRP_INTS8, len, a
+
71 #define UINTS8(len, a) CRP_INTS8, len, a
+
72 #define UINTS8_NO_COPY(len) CRP_UINTS8_NO_COPY, len
+
73 #define UINTS16_NO_COPY(len) CRP_UINTS16_NO_COPY, len
+
74 #define UINTS32_NO_COPY(len) CRP_UINTS32_NO_COPY, len
+
75 #define INTS16(len, a) CRP_INTS16, len, a
+
76 #define UINTS16(len, a) CRP_INTS16, len, a
+
77 #define INTS32(len, a) CRP_INTS32, len, a
+
78 #define UINTS32(len, a) CRP_INTS32, len, a
+
79 #define FLTS32(len, a) CRP_FLTS32, len, a
+
80 #define FLTS64(len, a) CRP_FLTS64, len, a
+
81 
+
82 #ifndef END
+
83 #ifdef __x86_64__
+
84 #define END (int64_t)0
+
85 #else
+
86 #define END 0
+
87 #endif
+
88 #endif
+
89 #define END_OUT_ARGS END
+
90 #define END_IN_ARGS END
+
91 
+
92 #endif
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen_8c.html b/screen_8c.html new file mode 100644 index 0000000..242803c --- /dev/null +++ b/screen_8c.html @@ -0,0 +1,193 @@ + + + + + + +discoverpixy: common/gui/screen.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
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+Functions | +Variables
+
+
screen.c File Reference
+
+
+
#include "screen.h"
+
+Include dependency graph for screen.c:
+
+
+ + +
+
+ + + + + + + + + +

+Functions

SCREEN_STRUCT * gui_screen_get_current ()
 
void gui_screen_update ()
 
bool gui_screen_navigate (SCREEN_STRUCT *screen)
 
bool gui_screen_back ()
 
+ + + + + + + +

+Variables

static SCREEN_STRUCT * screen_list = NULL
 
static SCREEN_STRUCT * screen_current = NULL
 
static volatile SCREEN_STRUCT * screen_goto = NULL
 
+

Variable Documentation

+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT* screen_current = NULL
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
volatile SCREEN_STRUCT* screen_goto = NULL
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT* screen_list = NULL
+ 		+static
+
+ +
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen_8c__incl.map b/screen_8c__incl.map new file mode 100644 index 0000000..7f6f77e --- /dev/null +++ b/screen_8c__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/screen_8c__incl.md5 b/screen_8c__incl.md5 new file mode 100644 index 0000000..0dc7c19 --- /dev/null +++ b/screen_8c__incl.md5 @@ -0,0 +1 @@ +6be83e8453ce94a48236cdfba15d1fc0 \ No newline at end of file diff --git a/screen_8c__incl.png b/screen_8c__incl.png new file mode 100644 index 0000000..cf91bda Binary files /dev/null and b/screen_8c__incl.png differ diff --git a/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map new file mode 100644 index 0000000..be7f910 --- /dev/null +++ b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 new file mode 100644 index 0000000..6af8ebc --- /dev/null +++ b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 @@ -0,0 +1 @@ +86f7eb24169ee0a087b3d1308a914559 \ No newline at end of file diff --git a/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png new file mode 100644 index 0000000..11a1b5d Binary files /dev/null and b/screen_8c_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png differ diff --git a/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.map b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.map new file mode 100644 index 0000000..c3071c6 --- /dev/null +++ b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.md5 b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.md5 new file mode 100644 index 0000000..22feacb --- /dev/null +++ b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.md5 @@ -0,0 +1 @@ +c9e3ce97be04049887cc5b217b398544 \ No newline at end of file diff --git a/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.png b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.png new file mode 100644 index 0000000..5e4b58d Binary files /dev/null and b/screen_8c_ab7394734ee1d57093721cbd22b901323_icgraph.png differ diff --git a/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map new file mode 100644 index 0000000..77eb376 --- /dev/null +++ b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 new file mode 100644 index 0000000..3508b0f --- /dev/null +++ b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 @@ -0,0 +1 @@ +54ddc1580219fc27daa0bf79d0aabcd2 \ No newline at end of file diff --git a/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png new file mode 100644 index 0000000..c5a5d68 Binary files /dev/null and b/screen_8c_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png differ diff --git a/screen_8h.html b/screen_8h.html new file mode 100644 index 0000000..9057d66 --- /dev/null +++ b/screen_8h.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: common/gui/screen.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Data Structures | +Typedefs | +Functions
+
+
screen.h File Reference
+
+
+
#include <stdio.h>
+#include <stdbool.h>
+
+Include dependency graph for screen.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + +

+Data Structures

struct  SCREEN_S
 
+ + + + + + +

+Typedefs

typedef void(* SCREEN_CALLBACK) (void *screen)
 Function pointer used... More...
 
typedef struct SCREEN_S SCREEN_STRUCT
 
+ + + + + + + + + +

+Functions

bool gui_screen_navigate (SCREEN_STRUCT *screen)
 
bool gui_screen_back ()
 
SCREEN_STRUCT * gui_screen_get_current ()
 
void gui_screen_update ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen_8h__dep__incl.map b/screen_8h__dep__incl.map new file mode 100644 index 0000000..f7ca452 --- /dev/null +++ b/screen_8h__dep__incl.map @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/screen_8h__dep__incl.md5 b/screen_8h__dep__incl.md5 new file mode 100644 index 0000000..0820bac --- /dev/null +++ b/screen_8h__dep__incl.md5 @@ -0,0 +1 @@ +81d3818aa3bfa8ba6a0b2934bb991af3 \ No newline at end of file diff --git a/screen_8h__dep__incl.png b/screen_8h__dep__incl.png new file mode 100644 index 0000000..a7ccc29 Binary files /dev/null and b/screen_8h__dep__incl.png differ diff --git a/screen_8h__incl.map b/screen_8h__incl.map new file mode 100644 index 0000000..83827f9 --- /dev/null +++ b/screen_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/screen_8h__incl.md5 b/screen_8h__incl.md5 new file mode 100644 index 0000000..94582e5 --- /dev/null +++ b/screen_8h__incl.md5 @@ -0,0 +1 @@ +de0a1a517c88a37bd47c40845f0ea417 \ No newline at end of file diff --git a/screen_8h__incl.png b/screen_8h__incl.png new file mode 100644 index 0000000..5db3f1f Binary files /dev/null and b/screen_8h__incl.png differ diff --git a/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map new file mode 100644 index 0000000..be7f910 --- /dev/null +++ b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 new file mode 100644 index 0000000..6af8ebc --- /dev/null +++ b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.md5 @@ -0,0 +1 @@ +86f7eb24169ee0a087b3d1308a914559 \ No newline at end of file diff --git a/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png new file mode 100644 index 0000000..11a1b5d Binary files /dev/null and b/screen_8h_a8e14bc7ee0214e2926965f9bdb54a866_icgraph.png differ diff --git a/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.map b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.map new file mode 100644 index 0000000..c3071c6 --- /dev/null +++ b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.md5 b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.md5 new file mode 100644 index 0000000..22feacb --- /dev/null +++ b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.md5 @@ -0,0 +1 @@ +c9e3ce97be04049887cc5b217b398544 \ No newline at end of file diff --git a/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.png b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.png new file mode 100644 index 0000000..5e4b58d Binary files /dev/null and b/screen_8h_ab7394734ee1d57093721cbd22b901323_icgraph.png differ diff --git a/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map new file mode 100644 index 0000000..77eb376 --- /dev/null +++ b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 new file mode 100644 index 0000000..3508b0f --- /dev/null +++ b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.md5 @@ -0,0 +1 @@ +54ddc1580219fc27daa0bf79d0aabcd2 \ No newline at end of file diff --git a/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png new file mode 100644 index 0000000..c5a5d68 Binary files /dev/null and b/screen_8h_ad4473a16eaf48dab405d23f5f63af3aa_icgraph.png differ diff --git a/screen_8h_source.html b/screen_8h_source.html new file mode 100644 index 0000000..bf3a5a7 --- /dev/null +++ b/screen_8h_source.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: common/gui/screen.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
screen.h
+
+
+Go to the documentation of this file.
1 #ifndef SCREEN_H
+
2 #define SCREEN_H
+
3 
+
8 
+
14 
+
15 #include <stdio.h>
+
16 #include <stdbool.h>
+
17 
+
18 typedef void (*SCREEN_CALLBACK)(void* screen);
+
19 
+
20 typedef struct SCREEN_S{
+
21  SCREEN_CALLBACK on_enter;
+
22  SCREEN_CALLBACK on_leave;
+
23  SCREEN_CALLBACK on_update;
+
24 
+
25 
+
26  struct SCREEN_S* next; //Used internally. do not modify
+
27 
+
28 } SCREEN_STRUCT;
+
29 
+
30 
+
31 //Navigate to the given string as soon as the app enters the main loop again. Method can be called from an interrupt
+
32 bool gui_screen_navigate(SCREEN_STRUCT* screen);
+
33 
+
34 //Navigate one screen back as soon as the app enters the main loop again. Method can be called from an interrupt
+
35 bool gui_screen_back();
+
36 
+
37 //Returns the current active screen
+
38 SCREEN_STRUCT* gui_screen_get_current();
+
39 
+
40 //Updates/switches the screens. Call this from the app main loop, as fast as you can.
+
41 void gui_screen_update();
+
42 
+
45 #endif /* SCREEN_H */
+
SCREEN_STRUCT
struct SCREEN_S SCREEN_STRUCT
+
gui_screen_update
void gui_screen_update()
Definition: screen.c:12
+
SCREEN_S::on_leave
SCREEN_CALLBACK on_leave
Definition: screen.h:22
+
SCREEN_S::next
struct SCREEN_S * next
Definition: screen.h:26
+
gui_screen_get_current
SCREEN_STRUCT * gui_screen_get_current()
Definition: screen.c:8
+
gui_screen_navigate
bool gui_screen_navigate(SCREEN_STRUCT *screen)
Definition: screen.c:39
+
SCREEN_S
Definition: screen.h:20
+
screen
static SCREEN_STRUCT screen
Definition: screen_filetest.c:120
+
SCREEN_CALLBACK
void(* SCREEN_CALLBACK)(void *screen)
Function pointer used...
Definition: screen.h:18
+
SCREEN_S::on_update
SCREEN_CALLBACK on_update
Definition: screen.h:23
+
gui_screen_back
bool gui_screen_back()
Definition: screen.c:48
+
SCREEN_S::on_enter
SCREEN_CALLBACK on_enter
Definition: screen.h:21
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__filetest_8c.html b/screen__filetest_8c.html new file mode 100644 index 0000000..28043ad --- /dev/null +++ b/screen__filetest_8c.html @@ -0,0 +1,361 @@ + + + + + + +discoverpixy: common/app/screen_filetest.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
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+ + +
+ +
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+
+
+Functions | +Variables
+
+
screen_filetest.c File Reference
+
+
+
#include "screen_filetest.h"
+#include "button.h"
+#include "tft.h"
+#include "filesystem.h"
+#include <stdlib.h>
+
+Include dependency graph for screen_filetest.c:
+
+
+ + +
+
+ + + + + + + + + + + + + +

+Functions

static void b_back_cb (void *button)
 
static void image_test ()
 
static void enter (void *screen)
 
static void leave (void *screen)
 
static void update (void *screen)
 
SCREEN_STRUCT * get_screen_filetest ()
 
+ + + + + +

+Variables

static BUTTON_STRUCT b_back
 
static SCREEN_STRUCT screen
 
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + +
static void b_back_cb (void * button)
+ 		+static
+
+ +

+Here is the call graph for this function:
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static void enter (void * screen)
+ 		+static
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+ +

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+ + + + + +
+ + + + + + + +
static void image_test ()
+ 		+static
+
+ +

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static void leave (void * screen)
+ 		+static
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static void update (void * screen)
+ 		+static
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + + +
+ + + + +
BUTTON_STRUCT b_back
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT screen
+ 		+static
+
+Initial value:
= {
+
enter,
+
leave,
+
update
+
}
+
leave
static void leave(void *screen)
Definition: screen_filetest.c:112
+
update
static void update(void *screen)
Definition: screen_filetest.c:116
+
enter
static void enter(void *screen)
Definition: screen_filetest.c:17
+
+
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
screen_filetest.h File Reference
+
+
+
#include "screen.h"
+
+Include dependency graph for screen_filetest.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+
+

Go to the source code of this file.

+ + + + +

+Functions

SCREEN_STRUCT * get_screen_filetest ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__filetest_8h__dep__incl.map b/screen__filetest_8h__dep__incl.map new file mode 100644 index 0000000..0b17a3d --- /dev/null +++ b/screen__filetest_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen__filetest_8h__dep__incl.md5 b/screen__filetest_8h__dep__incl.md5 new file mode 100644 index 0000000..781ee0e --- /dev/null +++ b/screen__filetest_8h__dep__incl.md5 @@ -0,0 +1 @@ +d4970502c533b9869c5fe3511fa7a2e5 \ No newline at end of file diff --git a/screen__filetest_8h__dep__incl.png b/screen__filetest_8h__dep__incl.png new file mode 100644 index 0000000..a5548f4 Binary files /dev/null and b/screen__filetest_8h__dep__incl.png differ diff --git a/screen__filetest_8h__incl.map b/screen__filetest_8h__incl.map new file mode 100644 index 0000000..c11917a --- /dev/null +++ b/screen__filetest_8h__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/screen__filetest_8h__incl.md5 b/screen__filetest_8h__incl.md5 new file mode 100644 index 0000000..0af6f3b --- /dev/null +++ b/screen__filetest_8h__incl.md5 @@ -0,0 +1 @@ +406b0c5e99cb5429b051458578bb5353 \ No newline at end of file diff --git a/screen__filetest_8h__incl.png b/screen__filetest_8h__incl.png new file mode 100644 index 0000000..0ad0495 Binary files /dev/null and b/screen__filetest_8h__incl.png differ diff --git a/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map new file mode 100644 index 0000000..67d9b31 --- /dev/null +++ b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 new file mode 100644 index 0000000..02c33f3 --- /dev/null +++ b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.md5 @@ -0,0 +1 @@ +aea667d65fcc686862e74aadd5929fd9 \ No newline at end of file diff --git a/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png new file mode 100644 index 0000000..3acd0bb Binary files /dev/null and b/screen__filetest_8h_ab5ad1c15566c8fbc0cc49faf51d22176_icgraph.png differ diff --git a/screen__filetest_8h_source.html b/screen__filetest_8h_source.html new file mode 100644 index 0000000..8b1d55e --- /dev/null +++ b/screen__filetest_8h_source.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: common/app/screen_filetest.h Source File + + + + + + + + + + +
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screen_filetest.h
+
+
+Go to the documentation of this file.
1 #include "screen.h"
+
2 
+
7 
+
13 
+
14 
+
20 SCREEN_STRUCT* get_screen_filetest();
+
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+ +
get_screen_filetest
SCREEN_STRUCT * get_screen_filetest()
Definition: screen_filetest.c:127
+
SCREEN_S
Definition: screen.h:20
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__guitest_8c.html b/screen__guitest_8c.html new file mode 100644 index 0000000..72603c2 --- /dev/null +++ b/screen__guitest_8c.html @@ -0,0 +1,519 @@ + + + + + + +discoverpixy: common/app/screen_guitest.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions | +Variables
+
+
screen_guitest.c File Reference
+
+
+
#include "screen_guitest.h"
+#include "button.h"
+#include "tft.h"
+#include "checkbox.h"
+#include "numupdown.h"
+
+Include dependency graph for screen_guitest.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Functions

static void checkboxCB (void *checkbox, bool checked)
 
static void b_back_cb (void *button)
 
static void n_updown_cb (void *numupdown, int16_t value)
 
static void touchCB (void *touchArea, TOUCH_ACTION triggeredAction)
 
static void enter (void *screen)
 
static void leave (void *screen)
 
static void update (void *screen)
 
SCREEN_STRUCT * get_screen_guitest ()
 
+ + + + + + + + + + + +

+Variables

static BUTTON_STRUCT b_back
 
static TOUCH_AREA_STRUCT a_area
 
static CHECKBOX_STRUCT c_cbox
 
static NUMUPDOWN_STRUCT n_updown
 
static SCREEN_STRUCT screen
 
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + +
static void b_back_cb (void * button)
+ 		+static
+
+ +

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static void checkboxCB (void * checkbox,
bool checked 
)
+ 		+static
+
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static void enter (void * screen)
+ 		+static
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static void leave (void * screen)
+ 		+static
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static void n_updown_cb (void * numupdown,
int16_t value 
)
+ 		+static
+
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static void touchCB (void * touchArea,
TOUCH_ACTION triggeredAction 
)
+ 		+static
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static void update (void * screen)
+ 		+static
+
+ +
+
+

Variable Documentation

+ +
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+ + + + + +
+ + + + +
TOUCH_AREA_STRUCT a_area
+ 		+static
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BUTTON_STRUCT b_back
+ 		+static
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+ + + + +
CHECKBOX_STRUCT c_cbox
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
NUMUPDOWN_STRUCT n_updown
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT screen
+ 		+static
+
+Initial value:
= {
+
enter,
+
leave,
+
update
+
}
+
update
static void update(void *screen)
Definition: screen_guitest.c:118
+
enter
static void enter(void *screen)
Definition: screen_guitest.c:48
+
leave
static void leave(void *screen)
Definition: screen_guitest.c:111
+
+
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
screen_guitest.h File Reference
+
+
+
#include "screen.h"
+
+Include dependency graph for screen_guitest.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + +

+Functions

SCREEN_STRUCT * get_screen_guitest ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__guitest_8h__dep__incl.map b/screen__guitest_8h__dep__incl.map new file mode 100644 index 0000000..6ab4f50 --- /dev/null +++ b/screen__guitest_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen__guitest_8h__dep__incl.md5 b/screen__guitest_8h__dep__incl.md5 new file mode 100644 index 0000000..8627e5b --- /dev/null +++ b/screen__guitest_8h__dep__incl.md5 @@ -0,0 +1 @@ +6466537a11d69214c5efd6b9c80ca9fc \ No newline at end of file diff --git a/screen__guitest_8h__dep__incl.png b/screen__guitest_8h__dep__incl.png new file mode 100644 index 0000000..f6c4583 Binary files /dev/null and b/screen__guitest_8h__dep__incl.png differ diff --git a/screen__guitest_8h__incl.map b/screen__guitest_8h__incl.map new file mode 100644 index 0000000..2f98a59 --- /dev/null +++ b/screen__guitest_8h__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/screen__guitest_8h__incl.md5 b/screen__guitest_8h__incl.md5 new file mode 100644 index 0000000..791535d --- /dev/null +++ b/screen__guitest_8h__incl.md5 @@ -0,0 +1 @@ +3c150907bc2fe9e69d4347d5b830aa90 \ No newline at end of file diff --git a/screen__guitest_8h__incl.png b/screen__guitest_8h__incl.png new file mode 100644 index 0000000..7da7938 Binary files /dev/null and b/screen__guitest_8h__incl.png differ diff --git a/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.map b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.map new file mode 100644 index 0000000..aae48c7 --- /dev/null +++ b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 new file mode 100644 index 0000000..bd0a053 --- /dev/null +++ b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.md5 @@ -0,0 +1 @@ +a0aae466d9d5fec807e7d61f2dacc86f \ No newline at end of file diff --git a/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.png b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.png new file mode 100644 index 0000000..cb2ed06 Binary files /dev/null and b/screen__guitest_8h_a75970b2a161e3fce8c6be83c96c75d98_icgraph.png differ diff --git a/screen__guitest_8h_source.html b/screen__guitest_8h_source.html new file mode 100644 index 0000000..5f17c7f --- /dev/null +++ b/screen__guitest_8h_source.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: common/app/screen_guitest.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
+ + + + + + +
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+
+
screen_guitest.h
+
+
+Go to the documentation of this file.
1 #include "screen.h"
+
2 
+
3 
+
8 
+
14 
+
15 
+
21 SCREEN_STRUCT* get_screen_guitest();
+
22 
+ +
SCREEN_S
Definition: screen.h:20
+
get_screen_guitest
SCREEN_STRUCT * get_screen_guitest()
Definition: screen_guitest.c:131
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__main_8c.html b/screen__main_8c.html new file mode 100644 index 0000000..ff8285f --- /dev/null +++ b/screen__main_8c.html @@ -0,0 +1,427 @@ + + + + + + +discoverpixy: common/app/screen_main.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions | +Variables
+
+
screen_main.c File Reference
+
+
+
#include "screen_main.h"
+#include "screen_guitest.h"
+#include "screen_pixytest.h"
+#include "screen_filetest.h"
+#include "button.h"
+#include "tft.h"
+
+Include dependency graph for screen_main.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + +

+Functions

static void b_guitest_cb (void *button)
 
static void b_filetest_cb (void *button)
 
static void b_pixytest_cb (void *button)
 
static void enter (void *screen)
 
static void leave (void *screen)
 
static void update (void *screen)
 
SCREEN_STRUCT * get_screen_main ()
 
+ + + + + + + + + +

+Variables

BUTTON_STRUCT b_guitest
 
BUTTON_STRUCT b_pixytest
 
BUTTON_STRUCT b_filetest
 
static SCREEN_STRUCT screen
 
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + +
static void b_filetest_cb (void * button)
+ 		+static
+
+ +

+Here is the call graph for this function:
+
+
+ + +
+

+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void b_guitest_cb (void * button)
+ 		+static
+
+ +

+Here is the call graph for this function:
+
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+ + +
+

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+ + +
+

+ +
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+ +
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+ + + + + +
+ + + + + + + + +
static void b_pixytest_cb (void * button)
+ 		+static
+
+ +

+Here is the call graph for this function:
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+
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static void enter (void * screen)
+ 		+static
+
+ +

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+

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+ + + + + +
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static void leave (void * screen)
+ 		+static
+
+ +

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static void update (void * screen)
+ 		+static
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
BUTTON_STRUCT b_filetest
+
+ +
+
+ +
+
+ + + + +
BUTTON_STRUCT b_guitest
+
+ +
+
+ +
+
+ + + + +
BUTTON_STRUCT b_pixytest
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT screen
+ 		+static
+
+Initial value:
= {
+
enter,
+
leave,
+
update
+
}
+
enter
static void enter(void *screen)
Definition: screen_main.c:25
+
leave
static void leave(void *screen)
Definition: screen_main.c:68
+
update
static void update(void *screen)
Definition: screen_main.c:74
+
+
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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+Functions
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screen_main.h File Reference
+
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#include "screen.h"
+
+Include dependency graph for screen_main.h:
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+Functions

SCREEN_STRUCT * get_screen_main ()
 
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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screen_main.h
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1 #include "screen.h"
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32 SCREEN_STRUCT* get_screen_main();
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get_screen_main
SCREEN_STRUCT * get_screen_main()
Definition: screen_main.c:86
+
SCREEN_S
Definition: screen.h:20
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+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__pixytest_8c.html b/screen__pixytest_8c.html new file mode 100644 index 0000000..4091e56 --- /dev/null +++ b/screen__pixytest_8c.html @@ -0,0 +1,806 @@ + + + + + + +discoverpixy: common/app/screen_pixytest.c File Reference + + + + + + + + + + +
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+Functions | +Variables
+
+
screen_pixytest.c File Reference
+
+
+
#include "screen_pixytest.h"
+#include "button.h"
+#include "tft.h"
+#include "touch.h"
+#include "pixy.h"
+#include <stdlib.h>
+#include "system.h"
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+Functions

static void b_back_cb (void *button)
 
static void b_runstop_cb (void *button)
 
static void touchCB (void *touchArea, TOUCH_ACTION triggeredAction)
 
static void enter (void *screen)
 
static void leave (void *screen)
 
int pixy_led_test ()
 
int pixy_frame_test ()
 
static void update (void *screen)
 
SCREEN_STRUCT * get_screen_pixytest ()
 
int renderBA81 (uint8_t renderFlags, uint16_t width, uint16_t height, uint32_t frameLen, uint8_t *frame)
 
void interpolateBayer (uint16_t width, uint16_t x, uint16_t y, uint8_t *pixel, uint8_t *r, uint8_t *g, uint8_t *b)
 
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+Variables

static volatile bool pixy_connected = false
 
static BUTTON_STRUCT b_back
 
static BUTTON_STRUCT b_runstop
 
static TOUCH_AREA_STRUCT a_area
 
static volatile bool pixy_running = false
 
static bool old_pixy_running = false
 
static POINT_STRUCT pixy_pos
 
static POINT_STRUCT old_pos
 
static SCREEN_STRUCT screen
 
int colorind
 
const uint32_t colors [] = {0xFF0000, 0x00FF00,0x0000FF,0xFFFF00,0x00FFFF,0xFF00FF,0xFFFFFF,0x000000}
 
const int num_colors = sizeof(colors)/sizeof(uint32_t)
 
+

Function Documentation

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static void b_back_cb (void * button)
+ 		+static
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static void b_runstop_cb (void * button)
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static void enter (void * screen)
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void interpolateBayer (uint16_t width,
uint16_t x,
uint16_t y,
uint8_t * pixel,
uint8_t * r,
uint8_t * g,
uint8_t * b 
)
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static void leave (void * screen)
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int pixy_frame_test ()
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int pixy_led_test ()
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int renderBA81 (uint8_t renderFlags,
uint16_t width,
uint16_t height,
uint32_t frameLen,
uint8_t * frame 
)
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static void touchCB (void * touchArea,
TOUCH_ACTION triggeredAction 
)
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static void update (void * screen)
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Variable Documentation

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TOUCH_AREA_STRUCT a_area
+ 		+static
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BUTTON_STRUCT b_back
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BUTTON_STRUCT b_runstop
+ 		+static
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int colorind
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const uint32_t colors[] = {0xFF0000, 0x00FF00,0x0000FF,0xFFFF00,0x00FFFF,0xFF00FF,0xFFFFFF,0x000000}
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const int num_colors = sizeof(colors)/sizeof(uint32_t)
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bool old_pixy_running = false
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POINT_STRUCT old_pos
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
volatile bool pixy_connected = false
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
POINT_STRUCT pixy_pos
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
volatile bool pixy_running = false
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + +
SCREEN_STRUCT screen
+ 		+static
+
+Initial value:
= {
+
enter,
+
leave,
+
update
+
}
+
leave
static void leave(void *screen)
Definition: screen_pixytest.c:114
+
update
static void update(void *screen)
Definition: screen_pixytest.c:124
+
enter
static void enter(void *screen)
Definition: screen_pixytest.c:67
+
+
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/screen__pixytest_8c__incl.map b/screen__pixytest_8c__incl.map new file mode 100644 index 0000000..939a3aa --- /dev/null +++ b/screen__pixytest_8c__incl.map @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/screen__pixytest_8c__incl.md5 b/screen__pixytest_8c__incl.md5 new file mode 100644 index 0000000..4718cba --- /dev/null +++ b/screen__pixytest_8c__incl.md5 @@ -0,0 +1 @@ +6663e85250fc1c5f4bb63d6c257f9fe9 \ No newline at end of file diff --git a/screen__pixytest_8c__incl.png b/screen__pixytest_8c__incl.png new file mode 100644 index 0000000..e9805be Binary files /dev/null and b/screen__pixytest_8c__incl.png differ diff --git a/screen__pixytest_8c_a0a41b38f964c1c064f351623e2fbdfef_cgraph.map b/screen__pixytest_8c_a0a41b38f964c1c064f351623e2fbdfef_cgraph.map new file mode 100644 index 0000000..6814efc --- /dev/null +++ b/screen__pixytest_8c_a0a41b38f964c1c064f351623e2fbdfef_cgraph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git 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+
+ + + + + + +
+
discoverpixy +
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+
+ + + + + + +
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+ + +
+ +
+ + +
+
+
+Functions
+
+
screen_pixytest.h File Reference
+
+
+
#include "screen.h"
+
+Include dependency graph for screen_pixytest.h:
+
+
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

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+Functions

SCREEN_STRUCT * get_screen_pixytest ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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discoverpixy +
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screen_pixytest.h
+
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+Go to the documentation of this file.
1 #include "screen.h"
+
2 
+
7 
+
13 
+
19 SCREEN_STRUCT* get_screen_pixytest();
+
20 
+ +
get_screen_pixytest
SCREEN_STRUCT * get_screen_pixytest()
Definition: screen_pixytest.c:181
+
SCREEN_S
Definition: screen.h:20
+
+ +
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['rtc_5falarmmask_5fdefinitions',['RTC_AlarmMask_Definitions',['../group___r_t_c___alarm_mask___definitions.html',1,'']]], + ['rtc_5falarms_5fdefinitions',['RTC_Alarms_Definitions',['../group___r_t_c___alarms___definitions.html',1,'']]], + ['rtc_5fam_5fpm_5fdefinitions',['RTC_AM_PM_Definitions',['../group___r_t_c___a_m___p_m___definitions.html',1,'']]], + ['rtc_5fasynchronous_5fpredivider',['RTC_Asynchronous_Predivider',['../group___r_t_c___asynchronous___predivider.html',1,'']]], + ['rtc_5fbackup_5fregisters_5fdefinitions',['RTC_Backup_Registers_Definitions',['../group___r_t_c___backup___registers___definitions.html',1,'']]], + ['rtc_5fcalib_5foutput_5fselection_5fdefinitions',['RTC_Calib_Output_selection_Definitions',['../group___r_t_c___calib___output__selection___definitions.html',1,'']]], + ['rtc_5fdaylightsaving_5fdefinitions',['RTC_DayLightSaving_Definitions',['../group___r_t_c___day_light_saving___definitions.html',1,'']]], + ['rtc_5fdigital_5fcalibration_5fdefinitions',['RTC_Digital_Calibration_Definitions',['../group___r_t_c___digital___calibration___definitions.html',1,'']]], + ['rtc_5fexported_5fconstants',['RTC_Exported_Constants',['../group___r_t_c___exported___constants.html',1,'']]], + ['rtc_5fflags_5fdefinitions',['RTC_Flags_Definitions',['../group___r_t_c___flags___definitions.html',1,'']]], + ['rtc_20tamper_20and_20timestamp_20pins_20selection_20and_20output_20type_20config_20configuration_20functions',['RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions',['../group___r_t_c___group11.html',1,'']]], + ['rtc_5fhour_5fformats',['RTC_Hour_Formats',['../group___r_t_c___hour___formats.html',1,'']]], + ['rtc_5finput_5fparameter_5fformat_5fdefinitions',['RTC_Input_parameter_format_definitions',['../group___r_t_c___input__parameter__format__definitions.html',1,'']]], + ['rtc_5finterrupts_5fdefinitions',['RTC_Interrupts_Definitions',['../group___r_t_c___interrupts___definitions.html',1,'']]], + ['rtc_5flegacy',['RTC_Legacy',['../group___r_t_c___legacy.html',1,'']]], + ['rtc_5fmonth_5fdate_5fdefinitions',['RTC_Month_Date_Definitions',['../group___r_t_c___month___date___definitions.html',1,'']]], + ['rtc_5foutput_5fpolarity_5fdefinitions',['RTC_Output_Polarity_Definitions',['../group___r_t_c___output___polarity___definitions.html',1,'']]], + ['rtc_5foutput_5fselection_5fdefinitions',['RTC_Output_selection_Definitions',['../group___r_t_c___output__selection___definitions.html',1,'']]], + ['rtc_5foutput_5ftype_5falarm_5fout',['RTC_Output_Type_ALARM_OUT',['../group___r_t_c___output___type___a_l_a_r_m___o_u_t.html',1,'']]], + ['rtc_5fprivate_5ffunctions',['RTC_Private_Functions',['../group___r_t_c___private___functions.html',1,'']]], + ['rtc_5fsmooth_5fcalib_5fminus_5fpulses_5fdefinitions',['RTC_Smooth_calib_Minus_pulses_Definitions',['../group___r_t_c___smooth__calib___minus__pulses___definitions.html',1,'']]], + ['rtc_5fsmooth_5fcalib_5fperiod_5fdefinitions',['RTC_Smooth_calib_period_Definitions',['../group___r_t_c___smooth__calib__period___definitions.html',1,'']]], + ['rtc_5fsmooth_5fcalib_5fplus_5fpulses_5fdefinitions',['RTC_Smooth_calib_Plus_pulses_Definitions',['../group___r_t_c___smooth__calib___plus__pulses___definitions.html',1,'']]], + ['rtc_5fsubstract_5ffraction_5fof_5fsecond_5fvalue',['RTC_Substract_Fraction_Of_Second_Value',['../group___r_t_c___substract___fraction___of___second___value.html',1,'']]], + ['rtc_5fsynchronous_5fpredivider',['RTC_Synchronous_Predivider',['../group___r_t_c___synchronous___predivider.html',1,'']]], + ['rtc_5ftamper_5ffilter_5fdefinitions',['RTC_Tamper_Filter_Definitions',['../group___r_t_c___tamper___filter___definitions.html',1,'']]], + ['rtc_5ftamper_5fpin_5fprecharge_5fduration_5fdefinitions',['RTC_Tamper_Pin_Precharge_Duration_Definitions',['../group___r_t_c___tamper___pin___precharge___duration___definitions.html',1,'']]], + ['rtc_5ftamper_5fpin_5fselection',['RTC_Tamper_Pin_Selection',['../group___r_t_c___tamper___pin___selection.html',1,'']]], + ['rtc_5ftamper_5fpins_5fdefinitions',['RTC_Tamper_Pins_Definitions',['../group___r_t_c___tamper___pins___definitions.html',1,'']]], + ['rtc_5ftamper_5fsampling_5ffrequencies_5fdefinitions',['RTC_Tamper_Sampling_Frequencies_Definitions',['../group___r_t_c___tamper___sampling___frequencies___definitions.html',1,'']]], + ['rtc_5ftamper_5ftrigger_5fdefinitions',['RTC_Tamper_Trigger_Definitions',['../group___r_t_c___tamper___trigger___definitions.html',1,'']]], + ['rtc_5ftime_5fdefinitions',['RTC_Time_Definitions',['../group___r_t_c___time___definitions.html',1,'']]], + ['rtc_5ftime_5fstamp_5fedges_5fdefinitions',['RTC_Time_Stamp_Edges_definitions',['../group___r_t_c___time___stamp___edges__definitions.html',1,'']]], + ['rtc_5ftimestamp_5fpin_5fselection',['RTC_TimeStamp_Pin_Selection',['../group___r_t_c___time_stamp___pin___selection.html',1,'']]], + ['rtc_5fwakeup_5ftimer_5fdefinitions',['RTC_Wakeup_Timer_Definitions',['../group___r_t_c___wakeup___timer___definitions.html',1,'']]], + ['rtc_5fweekday_5fdefinitions',['RTC_WeekDay_Definitions',['../group___r_t_c___week_day___definitions.html',1,'']]], + ['rtc_5fyear_5fdate_5fdefinitions',['RTC_Year_Date_Definitions',['../group___r_t_c___year___date___definitions.html',1,'']]] +]; diff --git a/search/mag_sel.png b/search/mag_sel.png new file mode 100644 index 0000000..81f6040 Binary files /dev/null and b/search/mag_sel.png differ diff --git a/search/namespaces_0.html b/search/namespaces_0.html new file mode 100644 index 0000000..6d5853b --- /dev/null +++ b/search/namespaces_0.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/search/namespaces_0.js b/search/namespaces_0.js new file mode 100644 index 0000000..2b55cb3 --- /dev/null +++ b/search/namespaces_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['ui',['Ui',['../namespace_ui.html',1,'']]] +]; diff --git a/search/nomatches.html b/search/nomatches.html new file mode 100644 index 0000000..b1ded27 --- /dev/null +++ b/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
+
No Matches
+
+ + diff --git a/search/pages_0.html b/search/pages_0.html new file mode 100644 index 0000000..4b85b34 --- /dev/null +++ b/search/pages_0.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/search/pages_0.js b/search/pages_0.js new file mode 100644 index 0000000..b7bab63 --- /dev/null +++ b/search/pages_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['discoverpixy',['discoverpixy',['../md__r_e_a_d_m_e.html',1,'']]] +]; diff --git a/search/pages_1.html b/search/pages_1.html new file mode 100644 index 0000000..8c53f61 --- /dev/null +++ b/search/pages_1.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/search/pages_1.js b/search/pages_1.js new file mode 100644 index 0000000..f860a8f --- /dev/null +++ b/search/pages_1.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['libpixyusb_2d0_2e4_20api_20reference',['libpixyusb-0.4 API Reference',['../index.html',1,'']]] +]; diff --git a/search/pages_2.html b/search/pages_2.html new file mode 100644 index 0000000..949520e --- /dev/null +++ b/search/pages_2.html @@ -0,0 +1,26 @@ + + + + + + + + + +
+
Loading...
+
+ +
Searching...
+
No Matches
+ +
+ + diff --git a/search/pages_2.js b/search/pages_2.js new file mode 100644 index 0000000..740ffb3 --- /dev/null +++ b/search/pages_2.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['misra_2dc_3a2004_20compliance_20exceptions',['MISRA-C:2004 Compliance Exceptions',['../_c_m_s_i_s__m_i_s_r_a__exceptions.html',1,'']]] +]; diff --git a/search/search.css b/search/search.css new file mode 100644 index 0000000..4d7612f --- /dev/null +++ b/search/search.css @@ -0,0 +1,271 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 8px; + right: 0px; + width: 170px; + z-index: 102; + background-color: white; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:111px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.searchresult { + background-color: #F0F3F8; +} + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: url("../tab_a.png"); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + diff --git a/search/search.js b/search/search.js new file mode 100644 index 0000000..dedce3b --- /dev/null +++ b/search/search.js @@ -0,0 +1,791 @@ +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? 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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usbh_msc_core.h
+
+
+
1 
+
2 /* Define to prevent recursive ----------------------------------------------*/
+
3 #ifndef __USBH_MSC_CORE_H
+
4 #define __USBH_MSC_CORE_H
+
5 
+
6 /* Includes ------------------------------------------------------------------*/
+
7 #include "usbh_core.h"
+
8 #include "usbh_stdreq.h"
+
9 #include "usb_bsp.h"
+
10 #include "usbh_ioreq.h"
+
11 #include "usbh_hcs.h"
+
12 
+
13 
+
14 extern USBH_Class_cb_TypeDef USBH_MSC_cb;
+
15 
+
16 void USBH_LL_systick();
+
17 int USBH_LL_open();
+
18 int USBH_LL_close();
+
19 int USBH_LL_send(const uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
20 int USBH_LL_receive(uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
21 void USBH_LL_setTimer();
+
22 uint32_t USBH_LL_getTimer();
+
23 
+
24 
+
25 #endif /* __USBH_MSC_CORE_H */
+
26 
+
27 
+
usb_bsp.h
Specific api's relative to the used hardware platform.
+
usbh_core.h
Header file for usbh_core.c.
+
usbh_stdreq.h
Header file for usbh_stdreq.c.
+
usbh_ioreq.h
Header file for usbh_ioreq.c.
+
usbh_hcs.h
Header file for usbh_hcs.c.
+
_USBH_Class_cb
Definition: usbh_core.h:174
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery_8c.html b/stm32f4__discovery_8c.html new file mode 100644 index 0000000..cf7bd7b --- /dev/null +++ b/stm32f4__discovery_8c.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4_discovery.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions | +Variables
+
+
stm32f4_discovery.c File Reference
+
+
+ +

This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics. +More...

+
#include "stm32f4_discovery.h"
+
+Include dependency graph for stm32f4_discovery.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +

+Functions

void STM_EVAL_LEDInit (Led_TypeDef Led)
 Configures LED GPIO. More...
 
void STM_EVAL_LEDOn (Led_TypeDef Led)
 Turns selected LED On. More...
 
void STM_EVAL_LEDOff (Led_TypeDef Led)
 Turns selected LED Off. More...
 
void STM_EVAL_LEDToggle (Led_TypeDef Led)
 Toggles the selected LED. More...
 
void STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
 Configures Button GPIO and EXTI Line. More...
 
uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
 Returns the selected Button state. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + +

+Variables

GPIO_TypeDef * GPIO_PORT [LEDn]
 
const uint16_t GPIO_PIN [LEDn]
 
const uint32_t GPIO_CLK [LEDn]
 
+GPIO_TypeDef * BUTTON_PORT [BUTTONn] = {USER_BUTTON_GPIO_PORT }
 
+const uint16_t BUTTON_PIN [BUTTONn] = {USER_BUTTON_PIN }
 
+const uint32_t BUTTON_CLK [BUTTONn] = {USER_BUTTON_GPIO_CLK }
 
+const uint16_t BUTTON_EXTI_LINE [BUTTONn] = {USER_BUTTON_EXTI_LINE }
 
+const uint8_t BUTTON_PORT_SOURCE [BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE}
 
+const uint8_t BUTTON_PIN_SOURCE [BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE }
 
+const uint8_t BUTTON_IRQn [BUTTONn] = {USER_BUTTON_EXTI_IRQn }
 
+NVIC_InitTypeDef NVIC_InitStructure
 
+

Detailed Description

+

This file provides set of firmware functions to manage Leds and push-button available on STM32F4-Discovery Kit from STMicroelectronics.

+
Author
MCD Application Team
+
Version
V1.1.0
+
Date
28-October-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery_8c__incl.map b/stm32f4__discovery_8c__incl.map new file mode 100644 index 0000000..a86dca7 --- /dev/null +++ b/stm32f4__discovery_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4__discovery_8c__incl.md5 b/stm32f4__discovery_8c__incl.md5 new file mode 100644 index 0000000..1ec7590 --- /dev/null +++ b/stm32f4__discovery_8c__incl.md5 @@ -0,0 +1 @@ +de05ce780e53f240282510c98aed2396 \ No newline at end of file diff --git a/stm32f4__discovery_8c__incl.png b/stm32f4__discovery_8c__incl.png new file mode 100644 index 0000000..ff9acc2 Binary files /dev/null and b/stm32f4__discovery_8c__incl.png differ diff --git a/stm32f4__discovery_8h.html b/stm32f4__discovery_8h.html new file mode 100644 index 0000000..788c25e --- /dev/null +++ b/stm32f4__discovery_8h.html @@ -0,0 +1,238 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4_discovery.h File Reference + + + + + + + + + + +
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+Macros | +Enumerations | +Functions
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stm32f4_discovery.h File Reference
+
+
+ +

This file contains definitions for STM32F4-Discovery Kit's Leds and push-button hardware resources. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4_discovery.h:
+
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+
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Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LEDn   4
 
+#define LED4_PIN   GPIO_Pin_12
 
+#define LED4_GPIO_PORT   GPIOD
 
+#define LED4_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED3_PIN   GPIO_Pin_13
 
+#define LED3_GPIO_PORT   GPIOD
 
+#define LED3_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED5_PIN   GPIO_Pin_14
 
+#define LED5_GPIO_PORT   GPIOD
 
+#define LED5_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define LED6_PIN   GPIO_Pin_15
 
+#define LED6_GPIO_PORT   GPIOD
 
+#define LED6_GPIO_CLK   RCC_AHB1Periph_GPIOD
 
+#define BUTTONn   1
 
+#define USER_BUTTON_PIN   GPIO_Pin_0
 Wakeup push-button.
 
+#define USER_BUTTON_GPIO_PORT   GPIOA
 
+#define USER_BUTTON_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define USER_BUTTON_EXTI_LINE   EXTI_Line0
 
+#define USER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOA
 
+#define USER_BUTTON_EXTI_PIN_SOURCE   EXTI_PinSource0
 
+#define USER_BUTTON_EXTI_IRQn   EXTI0_IRQn
 
+ + + + + + + +

+Enumerations

enum  Led_TypeDef { LED4 = 0, +LED3 = 1, +LED5 = 2, +LED6 = 3 + }
 
enum  Button_TypeDef { BUTTON_USER = 0 + }
 
enum  ButtonMode_TypeDef { BUTTON_MODE_GPIO = 0, +BUTTON_MODE_EXTI = 1 + }
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

void STM_EVAL_LEDInit (Led_TypeDef Led)
 Configures LED GPIO. More...
 
void STM_EVAL_LEDOn (Led_TypeDef Led)
 Turns selected LED On. More...
 
void STM_EVAL_LEDOff (Led_TypeDef Led)
 Turns selected LED Off. More...
 
void STM_EVAL_LEDToggle (Led_TypeDef Led)
 Toggles the selected LED. More...
 
void STM_EVAL_PBInit (Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
 Configures Button GPIO and EXTI Line. More...
 
uint32_t STM_EVAL_PBGetState (Button_TypeDef Button)
 Returns the selected Button state. More...
 
+

Detailed Description

+

This file contains definitions for STM32F4-Discovery Kit's Leds and push-button hardware resources.

+
Author
MCD Application Team
+
Version
V1.1.0
+
Date
28-October-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery_8h__dep__incl.map b/stm32f4__discovery_8h__dep__incl.map new file mode 100644 index 0000000..79b928b --- /dev/null +++ b/stm32f4__discovery_8h__dep__incl.map @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/stm32f4__discovery_8h__dep__incl.md5 b/stm32f4__discovery_8h__dep__incl.md5 new file mode 100644 index 0000000..592c8de --- /dev/null +++ b/stm32f4__discovery_8h__dep__incl.md5 @@ -0,0 +1 @@ +8436761b3d2d3e609307e1811b00208f \ No newline at end of file diff --git a/stm32f4__discovery_8h__dep__incl.png b/stm32f4__discovery_8h__dep__incl.png new file mode 100644 index 0000000..fdcfd83 Binary files /dev/null and b/stm32f4__discovery_8h__dep__incl.png differ diff --git a/stm32f4__discovery_8h__incl.map b/stm32f4__discovery_8h__incl.map new file mode 100644 index 0000000..4512225 --- /dev/null +++ b/stm32f4__discovery_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4__discovery_8h__incl.md5 b/stm32f4__discovery_8h__incl.md5 new file mode 100644 index 0000000..c17ee88 --- /dev/null +++ b/stm32f4__discovery_8h__incl.md5 @@ -0,0 +1 @@ +86ff9937d48f8b87d72f691925bc3af7 \ No newline at end of file diff --git a/stm32f4__discovery_8h__incl.png b/stm32f4__discovery_8h__incl.png new file mode 100644 index 0000000..b21857f Binary files /dev/null and b/stm32f4__discovery_8h__incl.png differ diff --git a/stm32f4__discovery_8h_source.html b/stm32f4__discovery_8h_source.html new file mode 100644 index 0000000..d52dcd1 --- /dev/null +++ b/stm32f4__discovery_8h_source.html @@ -0,0 +1,179 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4_discovery.h Source File + + + + + + + + + + +
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stm32f4_discovery.h
+
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+Go to the documentation of this file.
1 
+
23 /* Define to prevent recursive inclusion -------------------------------------*/
+
24 #ifndef __STM32F4_DISCOVERY_H
+
25 #define __STM32F4_DISCOVERY_H
+
26 
+
27 #ifdef __cplusplus
+
28  extern "C" {
+
29 #endif
+
30 
+
31 /* Includes ------------------------------------------------------------------*/
+
32  #include "stm32f4xx.h"
+
33 
+
49 typedef enum
+
50 {
+
51  LED4 = 0,
+
52  LED3 = 1,
+
53  LED5 = 2,
+
54  LED6 = 3
+
55 } Led_TypeDef;
+
56 
+
57 typedef enum
+
58 {
+
59  BUTTON_USER = 0,
+
60 } Button_TypeDef;
+
61 
+
62 typedef enum
+
63 {
+
64  BUTTON_MODE_GPIO = 0,
+
65  BUTTON_MODE_EXTI = 1
+
66 } ButtonMode_TypeDef;
+
78 #define LEDn 4
+
79 
+
80 #define LED4_PIN GPIO_Pin_12
+
81 #define LED4_GPIO_PORT GPIOD
+
82 #define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD
+
83 
+
84 #define LED3_PIN GPIO_Pin_13
+
85 #define LED3_GPIO_PORT GPIOD
+
86 #define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD
+
87 
+
88 #define LED5_PIN GPIO_Pin_14
+
89 #define LED5_GPIO_PORT GPIOD
+
90 #define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD
+
91 
+
92 #define LED6_PIN GPIO_Pin_15
+
93 #define LED6_GPIO_PORT GPIOD
+
94 #define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD
+
95 
+
102 #define BUTTONn 1
+
103 
+
107 #define USER_BUTTON_PIN GPIO_Pin_0
+
108 #define USER_BUTTON_GPIO_PORT GPIOA
+
109 #define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA
+
110 #define USER_BUTTON_EXTI_LINE EXTI_Line0
+
111 #define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
+
112 #define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
+
113 #define USER_BUTTON_EXTI_IRQn EXTI0_IRQn
+
114 
+
129 void STM_EVAL_LEDInit(Led_TypeDef Led);
+
130 void STM_EVAL_LEDOn(Led_TypeDef Led);
+
131 void STM_EVAL_LEDOff(Led_TypeDef Led);
+
132 void STM_EVAL_LEDToggle(Led_TypeDef Led);
+
133 void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+
134 uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+
139 #ifdef __cplusplus
+
140 }
+
141 #endif
+
142 
+
143 #endif /* __STM32F4_DISCOVERY_H */
+
144 
+
158 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
STM_EVAL_PBGetState
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
Returns the selected Button state.
Definition: stm32f4_discovery.c:232
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
STM_EVAL_PBInit
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
Configures Button GPIO and EXTI Line.
Definition: stm32f4_discovery.c:188
+
STM_EVAL_LEDOn
void STM_EVAL_LEDOn(Led_TypeDef Led)
Turns selected LED On.
Definition: stm32f4_discovery.c:142
+
STM_EVAL_LEDOff
void STM_EVAL_LEDOff(Led_TypeDef Led)
Turns selected LED Off.
Definition: stm32f4_discovery.c:157
+
STM_EVAL_LEDToggle
void STM_EVAL_LEDToggle(Led_TypeDef Led)
Toggles the selected LED.
Definition: stm32f4_discovery.c:172
+
STM_EVAL_LEDInit
void STM_EVAL_LEDInit(Led_TypeDef Led)
Configures LED GPIO.
Definition: stm32f4_discovery.c:116
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery__lis302dl_8c.html b/stm32f4__discovery__lis302dl_8c.html new file mode 100644 index 0000000..bcdacee --- /dev/null +++ b/stm32f4__discovery__lis302dl_8c.html @@ -0,0 +1,176 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4_discovery_lis302dl.c File Reference + + + + + + + + + + +
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+Macros | +Functions | +Variables
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stm32f4_discovery_lis302dl.c File Reference
+
+
+ +

This file provides a set of functions needed to manage the LIS302DL MEMS accelerometer available on STM32F4-Discovery Kit. +More...

+
#include "stm32f4_discovery_lis302dl.h"
+
+Include dependency graph for stm32f4_discovery_lis302dl.c:
+
+
+ + +
+
+ + + + + + + +

+Macros

+#define READWRITE_CMD   ((uint8_t)0x80)
 
+#define MULTIPLEBYTE_CMD   ((uint8_t)0x40)
 
+#define DUMMY_BYTE   ((uint8_t)0x00)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LIS302DL_Init (LIS302DL_InitTypeDef *LIS302DL_InitStruct)
 Set LIS302DL Initialization. More...
 
void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
 Set LIS302DL Internal High Pass Filter configuration. More...
 
void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct)
 Set LIS302DL Interrupt configuration. More...
 
void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
 Change the lowpower mode for LIS302DL. More...
 
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
 Data Rate command. More...
 
void LIS302DL_FullScaleCmd (uint8_t FS_value)
 Change the Full Scale of LIS302DL. More...
 
void LIS302DL_RebootCmd (void)
 Reboot memory content of LIS302DL. More...
 
void LIS302DL_Write (uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
 Writes one byte to the LIS302DL. More...
 
void LIS302DL_Read (uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
 Reads a block of data from the LIS302DL. More...
 
void LIS302DL_ReadACC (int32_t *out)
 Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) More...
 
+ + + +

+Variables

+__IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT
 
+

Detailed Description

+

This file provides a set of functions needed to manage the LIS302DL MEMS accelerometer available on STM32F4-Discovery Kit.

+
Author
MCD Application Team
+
Version
V1.1.0
+
Date
28-October-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery__lis302dl_8c__incl.map b/stm32f4__discovery__lis302dl_8c__incl.map new file mode 100644 index 0000000..1dc7b1e --- /dev/null +++ b/stm32f4__discovery__lis302dl_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4__discovery__lis302dl_8c__incl.md5 b/stm32f4__discovery__lis302dl_8c__incl.md5 new file mode 100644 index 0000000..9a14e61 --- /dev/null +++ b/stm32f4__discovery__lis302dl_8c__incl.md5 @@ -0,0 +1 @@ +78a2ff5fae99f80326bffa2b2fa612d2 \ No newline at end of file diff --git a/stm32f4__discovery__lis302dl_8c__incl.png b/stm32f4__discovery__lis302dl_8c__incl.png new file mode 100644 index 0000000..5243199 Binary files /dev/null and b/stm32f4__discovery__lis302dl_8c__incl.png differ diff --git a/stm32f4__discovery__lis302dl_8h.html b/stm32f4__discovery__lis302dl_8h.html new file mode 100644 index 0000000..13881ce --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h.html @@ -0,0 +1,489 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4_discovery_lis302dl.h File Reference + + + + + + + + + + +
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stm32f4_discovery_lis302dl.h File Reference
+
+
+ +

This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c firmware driver. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4_discovery_lis302dl.h:
+
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+Classes

struct  LIS302DL_InitTypeDef
 
struct  LIS302DL_FilterConfigTypeDef
 
struct  LIS302DL_InterruptConfigTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LIS302DL_FLAG_TIMEOUT   ((uint32_t)0x1000)
 
+#define LIS302DL_SPI   SPI1
 LIS302DL SPI Interface pins.
 
+#define LIS302DL_SPI_CLK   RCC_APB2Periph_SPI1
 
+#define LIS302DL_SPI_SCK_PIN   GPIO_Pin_5 /* PA.05 */
 
+#define LIS302DL_SPI_SCK_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_SCK_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_SCK_SOURCE   GPIO_PinSource5
 
+#define LIS302DL_SPI_SCK_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_MISO_PIN   GPIO_Pin_6 /* PA.6 */
 
+#define LIS302DL_SPI_MISO_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_MISO_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_MISO_SOURCE   GPIO_PinSource6
 
+#define LIS302DL_SPI_MISO_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_MOSI_PIN   GPIO_Pin_7 /* PA.7 */
 
+#define LIS302DL_SPI_MOSI_GPIO_PORT   GPIOA /* GPIOA */
 
+#define LIS302DL_SPI_MOSI_GPIO_CLK   RCC_AHB1Periph_GPIOA
 
+#define LIS302DL_SPI_MOSI_SOURCE   GPIO_PinSource7
 
+#define LIS302DL_SPI_MOSI_AF   GPIO_AF_SPI1
 
+#define LIS302DL_SPI_CS_PIN   GPIO_Pin_3 /* PE.03 */
 
+#define LIS302DL_SPI_CS_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_CS_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT1_PIN   GPIO_Pin_0 /* PE.00 */
 
+#define LIS302DL_SPI_INT1_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_INT1_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT1_EXTI_LINE   EXTI_Line0
 
+#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOE
 
+#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE   EXTI_PinSource0
 
+#define LIS302DL_SPI_INT1_EXTI_IRQn   EXTI0_IRQn
 
+#define LIS302DL_SPI_INT2_PIN   GPIO_Pin_1 /* PE.01 */
 
+#define LIS302DL_SPI_INT2_GPIO_PORT   GPIOE /* GPIOE */
 
+#define LIS302DL_SPI_INT2_GPIO_CLK   RCC_AHB1Periph_GPIOE
 
+#define LIS302DL_SPI_INT2_EXTI_LINE   EXTI_Line1
 
+#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOE
 
+#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE   EXTI_PinSource1
 
+#define LIS302DL_SPI_INT2_EXTI_IRQn   EXTI1_IRQn
 
+#define LIS302DL_WHO_AM_I_ADDR   0x0F
 
+#define LIS302DL_CTRL_REG1_ADDR   0x20
 
+#define LIS302DL_CTRL_REG2_ADDR   0x21
 
+#define LIS302DL_CTRL_REG3_ADDR   0x22
 
+#define LIS302DL_HP_FILTER_RESET_REG_ADDR   0x23
 
+#define LIS302DL_STATUS_REG_ADDR   0x27
 
+#define LIS302DL_OUT_X_ADDR   0x29
 
+#define LIS302DL_OUT_Y_ADDR   0x2B
 
+#define LIS302DL_OUT_Z_ADDR   0x2D
 
+#define LIS302DL_FF_WU_CFG1_REG_ADDR   0x30
 
+#define LIS302DL_FF_WU_SRC1_REG_ADDR   0x31
 
+#define LIS302DL_FF_WU_THS1_REG_ADDR   0x32
 
+#define LIS302DL_FF_WU_DURATION1_REG_ADDR   0x33
 
+#define LIS302DL_FF_WU_CFG2_REG_ADDR   0x34
 
+#define LIS302DL_FF_WU_SRC2_REG_ADDR   0x35
 
+#define LIS302DL_FF_WU_THS2_REG_ADDR   0x36
 
+#define LIS302DL_FF_WU_DURATION2_REG_ADDR   0x37
 
+#define LIS302DL_CLICK_CFG_REG_ADDR   0x38
 
+#define LIS302DL_CLICK_SRC_REG_ADDR   0x39
 
+#define LIS302DL_CLICK_THSY_X_REG_ADDR   0x3B
 
+#define LIS302DL_CLICK_THSZ_REG_ADDR   0x3C
 
+#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR   0x3D
 
+#define LIS302DL_CLICK_LATENCY_REG_ADDR   0x3E
 
+#define LIS302DL_CLICK_WINDOW_REG_ADDR   0x3F
 
+#define LIS302DL_SENSITIVITY_2_3G   18 /* 18 mg/digit*/
 
+#define LIS302DL_SENSITIVITY_9_2G   72 /* 72 mg/digit*/
 
+#define LIS302DL_DATARATE_100   ((uint8_t)0x00)
 
+#define LIS302DL_DATARATE_400   ((uint8_t)0x80)
 
+#define LIS302DL_LOWPOWERMODE_POWERDOWN   ((uint8_t)0x00)
 
+#define LIS302DL_LOWPOWERMODE_ACTIVE   ((uint8_t)0x40)
 
+#define LIS302DL_FULLSCALE_2_3   ((uint8_t)0x00)
 
+#define LIS302DL_FULLSCALE_9_2   ((uint8_t)0x20)
 
+#define LIS302DL_SELFTEST_NORMAL   ((uint8_t)0x00)
 
+#define LIS302DL_SELFTEST_P   ((uint8_t)0x10)
 
+#define LIS302DL_SELFTEST_M   ((uint8_t)0x08)
 
+#define LIS302DL_X_ENABLE   ((uint8_t)0x01)
 
+#define LIS302DL_Y_ENABLE   ((uint8_t)0x02)
 
+#define LIS302DL_Z_ENABLE   ((uint8_t)0x04)
 
+#define LIS302DL_XYZ_ENABLE   ((uint8_t)0x07)
 
+#define LIS302DL_SERIALINTERFACE_4WIRE   ((uint8_t)0x00)
 
+#define LIS302DL_SERIALINTERFACE_3WIRE   ((uint8_t)0x80)
 
+#define LIS302DL_BOOT_NORMALMODE   ((uint8_t)0x00)
 
+#define LIS302DL_BOOT_REBOOTMEMORY   ((uint8_t)0x40)
 
+#define LIS302DL_FILTEREDDATASELECTION_BYPASSED   ((uint8_t)0x00)
 
+#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER   ((uint8_t)0x20)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF   ((uint8_t)0x00)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1   ((uint8_t)0x04)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_2   ((uint8_t)0x08)
 
+#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2   ((uint8_t)0x0C)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_0   ((uint8_t)0x00)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_1   ((uint8_t)0x01)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_2   ((uint8_t)0x02)
 
+#define LIS302DL_HIGHPASSFILTER_LEVEL_3   ((uint8_t)0x03)
 
+#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED   ((uint8_t)0x00)
 
+#define LIS302DL_INTERRUPTREQUEST_LATCHED   ((uint8_t)0x40)
 
+#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE   ((uint8_t)0x00)
 
+#define LIS302DL_CLICKINTERRUPT_X_ENABLE   ((uint8_t)0x01)
 
+#define LIS302DL_CLICKINTERRUPT_Y_ENABLE   ((uint8_t)0x04)
 
+#define LIS302DL_CLICKINTERRUPT_Z_ENABLE   ((uint8_t)0x10)
 
+#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE   ((uint8_t)0x15)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE   ((uint8_t)0x00)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE   ((uint8_t)0x02)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE   ((uint8_t)0x08)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE   ((uint8_t)0x20)
 
+#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE   ((uint8_t)0x2A)
 
+#define LIS302DL_CS_LOW()   GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
 
+#define LIS302DL_CS_HIGH()   GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LIS302DL_Init (LIS302DL_InitTypeDef *LIS302DL_InitStruct)
 Set LIS302DL Initialization. More...
 
void LIS302DL_InterruptConfig (LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct)
 Set LIS302DL Interrupt configuration. More...
 
void LIS302DL_FilterConfig (LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
 Set LIS302DL Internal High Pass Filter configuration. More...
 
void LIS302DL_LowpowerCmd (uint8_t LowPowerMode)
 Change the lowpower mode for LIS302DL. More...
 
void LIS302DL_FullScaleCmd (uint8_t FS_value)
 Change the Full Scale of LIS302DL. More...
 
void LIS302DL_DataRateCmd (uint8_t DataRateValue)
 Data Rate command. More...
 
void LIS302DL_RebootCmd (void)
 Reboot memory content of LIS302DL. More...
 
void LIS302DL_ReadACC (int32_t *out)
 Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) More...
 
void LIS302DL_Write (uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
 Writes one byte to the LIS302DL. More...
 
void LIS302DL_Read (uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
 Reads a block of data from the LIS302DL. More...
 
+uint32_t LIS302DL_TIMEOUT_UserCallback (void)
 
+

Detailed Description

+

This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c firmware driver.

+
Author
MCD Application Team
+
Version
V1.1.0
+
Date
28-October-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4__discovery__lis302dl_8h__dep__incl.map b/stm32f4__discovery__lis302dl_8h__dep__incl.map new file mode 100644 index 0000000..1474dbc --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/stm32f4__discovery__lis302dl_8h__dep__incl.md5 b/stm32f4__discovery__lis302dl_8h__dep__incl.md5 new file mode 100644 index 0000000..0ec5dfd --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h__dep__incl.md5 @@ -0,0 +1 @@ +8726aedd5c9d50238407fda1c561c933 \ No newline at end of file diff --git a/stm32f4__discovery__lis302dl_8h__dep__incl.png b/stm32f4__discovery__lis302dl_8h__dep__incl.png new file mode 100644 index 0000000..ebd3fef Binary files /dev/null and b/stm32f4__discovery__lis302dl_8h__dep__incl.png differ diff --git a/stm32f4__discovery__lis302dl_8h__incl.map b/stm32f4__discovery__lis302dl_8h__incl.map new file mode 100644 index 0000000..57f3ee7 --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4__discovery__lis302dl_8h__incl.md5 b/stm32f4__discovery__lis302dl_8h__incl.md5 new file mode 100644 index 0000000..d87a9d3 --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h__incl.md5 @@ -0,0 +1 @@ +f05e5999ad2c58109fcf3fa105218cda \ No newline at end of file diff --git a/stm32f4__discovery__lis302dl_8h__incl.png b/stm32f4__discovery__lis302dl_8h__incl.png new file mode 100644 index 0000000..4b404ef Binary files /dev/null and b/stm32f4__discovery__lis302dl_8h__incl.png differ diff --git a/stm32f4__discovery__lis302dl_8h_source.html b/stm32f4__discovery__lis302dl_8h_source.html new file mode 100644 index 0000000..de1547b --- /dev/null +++ b/stm32f4__discovery__lis302dl_8h_source.html @@ -0,0 +1,731 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4_discovery_lis302dl.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4_discovery_lis302dl.h
+
+
+Go to the documentation of this file.
1 
+
23 /* Define to prevent recursive inclusion -------------------------------------*/
+
24 #ifndef __STM32F4_DISCOVERY_LIS302DL_H
+
25 #define __STM32F4_DISCOVERY_LIS302DL_H
+
26 
+
27 #ifdef __cplusplus
+
28  extern "C" {
+
29 #endif
+
30 
+
31 /* Includes ------------------------------------------------------------------*/
+
32  #include "stm32f4xx.h"
+
33 
+
51 /* LIS302DL struct */
+
52 typedef struct
+
53 {
+
54  uint8_t Power_Mode; /* Power-down/Active Mode */
+
55  uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */
+
56  uint8_t Axes_Enable; /* Axes enable */
+
57  uint8_t Full_Scale; /* Full scale */
+
58  uint8_t Self_Test; /* Self test */
+
59 }LIS302DL_InitTypeDef;
+
60 
+
61 /* LIS302DL High Pass Filter struct */
+
62 typedef struct
+
63 {
+
64  uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/
+
65  uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
+
66  uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */
+
67 }LIS302DL_FilterConfigTypeDef;
+
68 
+
69 /* LIS302DL Interrupt struct */
+
70 typedef struct
+
71 {
+
72  uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/
+
73  uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */
+
74  uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */
+
75 }LIS302DL_InterruptConfigTypeDef;
+
76 
+
85 /* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback()
+
86  function implemented in stm32f4_discovery_lis302dl.c file.
+
87  LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition
+
88  occure during communication (waiting transmit data register empty flag(TXE)
+
89  or waiting receive data register is not empty flag (RXNE)). */
+
90 /* #define USE_DEFAULT_TIMEOUT_CALLBACK */
+
91 
+
92 /* Maximum Timeout values for flags waiting loops. These timeouts are not based
+
93  on accurate values, they just guarantee that the application will not remain
+
94  stuck if the SPI communication is corrupted.
+
95  You may modify these timeout values depending on CPU frequency and application
+
96  conditions (interrupts routines ...). */
+
97 #define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000)
+
98 
+
102 #define LIS302DL_SPI SPI1
+
103 #define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1
+
104 
+
105 #define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */
+
106 #define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */
+
107 #define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA
+
108 #define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5
+
109 #define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1
+
110 
+
111 #define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */
+
112 #define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */
+
113 #define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA
+
114 #define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6
+
115 #define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1
+
116 
+
117 #define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */
+
118 #define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */
+
119 #define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA
+
120 #define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7
+
121 #define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1
+
122 
+
123 #define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */
+
124 #define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */
+
125 #define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE
+
126 
+
127 #define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */
+
128 #define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */
+
129 #define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE
+
130 #define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0
+
131 #define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
+
132 #define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0
+
133 #define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn
+
134 
+
135 #define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */
+
136 #define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */
+
137 #define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE
+
138 #define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1
+
139 #define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE
+
140 #define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1
+
141 #define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn
+
142 
+
143 
+
144 /******************************************************************************/
+
145 /*************************** START REGISTER MAPPING **************************/
+
146 /******************************************************************************/
+
147 
+
148 /*******************************************************************************
+
149 * WHO_AM_I Register: Device Identification Register
+
150 * Read only register
+
151 * Default value: 0x3B
+
152 *******************************************************************************/
+
153 #define LIS302DL_WHO_AM_I_ADDR 0x0F
+
154 
+
155 /*******************************************************************************
+
156 * CTRL_REG1 Register: Control Register 1
+
157 * Read Write register
+
158 * Default value: 0x07
+
159 * 7 DR: Data Rate selection.
+
160 * 0 - 100 Hz output data rate
+
161 * 1 - 400 Hz output data rate
+
162 * 6 PD: Power Down control.
+
163 * 0 - power down mode
+
164 * 1 - active mode
+
165 * 5 FS: Full Scale selection.
+
166 * 0 - Typical measurement range 2.3
+
167 * 1 - Typical measurement range 9.2
+
168 * 4:3 STP-STM Self Test Enable:
+
169 * STP | STM | mode
+
170 * ----------------------------
+
171 * 0 | 0 | Normal mode
+
172 * 0 | 1 | Self Test M
+
173 * 1 | 0 | Self Test P
+
174 * 2 Zen: Z axis enable.
+
175 * 0 - Z axis disabled
+
176 * 1- Z axis enabled
+
177 * 1 Yen: Y axis enable.
+
178 * 0 - Y axis disabled
+
179 * 1- Y axis enabled
+
180 * 0 Xen: X axis enable.
+
181 * 0 - X axis disabled
+
182 * 1- X axis enabled
+
183 ********************************************************************************/
+
184 #define LIS302DL_CTRL_REG1_ADDR 0x20
+
185 
+
186 /*******************************************************************************
+
187 * CTRL_REG2 Regsiter: Control Register 2
+
188 * Read Write register
+
189 * Default value: 0x00
+
190 * 7 SIM: SPI Serial Interface Mode Selection.
+
191 * 0 - 4 wire interface
+
192 * 1 - 3 wire interface
+
193 * 6 BOOT: Reboot memory content
+
194 * 0 - normal mode
+
195 * 1 - reboot memory content
+
196 * 5 Reserved
+
197 * 4 FDS: Filtered data selection.
+
198 * 0 - internal filter bypassed
+
199 * 1 - data from internal filter sent to output register
+
200 * 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2.
+
201 * 0 - filter bypassed
+
202 * 1 - filter enabled
+
203 * 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1.
+
204 * 0 - filter bypassed
+
205 * 1 - filter enabled
+
206 * 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration.
+
207 * ft= ODR[hz]/6*HP coeff
+
208 * HP coeff2 | HP coeff1 | HP coeff
+
209 * -------------------------------------------
+
210 * 0 | 0 | 8
+
211 * 0 | 1 | 16
+
212 * 1 | 0 | 32
+
213 * 1 | 1 | 64
+
214 * HP coeff | ft[hz] | ft[hz] |
+
215 * |ODR 100Hz | ODR 400Hz |
+
216 * --------------------------------------------
+
217 * 00 | 2 | 8 |
+
218 * 01 | 1 | 4 |
+
219 * 10 | 0.5 | 2 |
+
220 * 11 | 0.25 | 1 |
+
221 *******************************************************************************/
+
222 #define LIS302DL_CTRL_REG2_ADDR 0x21
+
223 
+
224 /*******************************************************************************
+
225 * CTRL_REG3 Register: Interrupt Control Register
+
226 * Read Write register
+
227 * Default value: 0x00
+
228 * 7 IHL active: Interrupt active high/low.
+
229 * 0 - active high
+
230 * 1 - active low
+
231 * 6 PP_OD: push-pull/open-drain.
+
232 * 0 - push-pull
+
233 * 1 - open-drain
+
234 * 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits
+
235 * 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits
+
236 * I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad
+
237 * ----------------------------------------------------------
+
238 * 0 | 0 | 0 | GND
+
239 * 0 | 0 | 1 | FreeFall/WakeUp#1
+
240 * 0 | 1 | 0 | FreeFall/WakeUp#2
+
241 * 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2
+
242 * 1 | 0 | 0 | Data ready
+
243 * 1 | 1 | 1 | Click interrupt
+
244 *******************************************************************************/
+
245 #define LIS302DL_CTRL_REG3_ADDR 0x22
+
246 
+
247 /*******************************************************************************
+
248 * HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes
+
249 * instantaneously the content of the internal high pass filter. If the high pass
+
250 * filter is enabled all three axes are instantaneously set to 0g.
+
251 * This allows to overcome the settling time of the high pass filter.
+
252 * Read only register
+
253 * Default value: Dummy
+
254 *******************************************************************************/
+
255 #define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23
+
256 
+
257 /*******************************************************************************
+
258 * STATUS_REG Register: Status Register
+
259 * Default value: 0x00
+
260 * 7 ZYXOR: X, Y and Z axis data overrun.
+
261 * 0: no overrun has occurred
+
262 * 1: new data has overwritten the previous one before it was read
+
263 * 6 ZOR: Z axis data overrun.
+
264 * 0: no overrun has occurred
+
265 * 1: new data for Z-axis has overwritten the previous one before it was read
+
266 * 5 yOR: y axis data overrun.
+
267 * 0: no overrun has occurred
+
268 * 1: new data for y-axis has overwritten the previous one before it was read
+
269 * 4 XOR: X axis data overrun.
+
270 * 0: no overrun has occurred
+
271 * 1: new data for X-axis has overwritten the previous one before it was read
+
272 * 3 ZYXDA: X, Y and Z axis new data available
+
273 * 0: a new set of data is not yet available
+
274 * 1: a new set of data is available
+
275 * 2 ZDA: Z axis new data available.
+
276 * 0: a new set of data is not yet available
+
277 * 1: a new data for Z axis is available
+
278 * 1 YDA: Y axis new data available
+
279 * 0: a new set of data is not yet available
+
280 * 1: a new data for Y axis is available
+
281 * 0 XDA: X axis new data available
+
282 * 0: a new set of data is not yet available
+
283 * 1: a new data for X axis is available
+
284 *******************************************************************************/
+
285 #define LIS302DL_STATUS_REG_ADDR 0x27
+
286 
+
287 /*******************************************************************************
+
288 * OUT_X Register: X-axis output Data
+
289 * Read only register
+
290 * Default value: output
+
291 * 7:0 XD7-XD0: X-axis output Data
+
292 *******************************************************************************/
+
293 #define LIS302DL_OUT_X_ADDR 0x29
+
294 
+
295 /*******************************************************************************
+
296 * OUT_Y Register: Y-axis output Data
+
297 * Read only register
+
298 * Default value: output
+
299 * 7:0 YD7-YD0: Y-axis output Data
+
300 *******************************************************************************/
+
301 #define LIS302DL_OUT_Y_ADDR 0x2B
+
302 
+
303 /*******************************************************************************
+
304 * OUT_Z Register: Z-axis output Data
+
305 * Read only register
+
306 * Default value: output
+
307 * 7:0 ZD7-ZD0: Z-axis output Data
+
308 *******************************************************************************/
+
309 #define LIS302DL_OUT_Z_ADDR 0x2D
+
310 
+
311 /*******************************************************************************
+
312 * FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source.
+
313 * Read write register
+
314 * Default value: 0x00
+
315 * 7 AOI: AND/OR combination of Interrupt events.
+
316 * 0: OR combination of interrupt events
+
317 * 1: AND combination of interrupt events
+
318 * 6 LIR: Latch/not latch interrupt request
+
319 * 0: interrupt request not latched
+
320 * 1: interrupt request latched
+
321 * 5 ZHIE: Enable interrupt generation on Z high event.
+
322 * 0: disable interrupt request
+
323 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
324 * 4 ZLIE: Enable interrupt generation on Z low event.
+
325 * 0: disable interrupt request
+
326 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
327 * 3 YHIE: Enable interrupt generation on Y high event.
+
328 * 0: disable interrupt request
+
329 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
330 * 2 YLIE: Enable interrupt generation on Y low event.
+
331 * 0: disable interrupt request
+
332 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
333 * 1 XHIE: Enable interrupt generation on X high event.
+
334 * 0: disable interrupt request
+
335 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
336 * 0 XLIE: Enable interrupt generation on X low event.
+
337 * 0: disable interrupt request
+
338 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
339 *******************************************************************************/
+
340 #define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30
+
341 
+
342 /*******************************************************************************
+
343 * FF_WU_SRC_1 Register: Interrupt 1 source register.
+
344 * Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt
+
345 * and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option
+
346 * was chosen.
+
347 * Read only register
+
348 * Default value: 0x00
+
349 * 7 Reserved
+
350 * 6 IA: Interrupt active.
+
351 * 0: no interrupt has been generated
+
352 * 1: one or more interrupts have been generated
+
353 * 5 ZH: Z high.
+
354 * 0: no interrupt
+
355 * 1: ZH event has occurred
+
356 * 4 ZL: Z low.
+
357 * 0: no interrupt
+
358 * 1: ZL event has occurred
+
359 * 3 YH: Y high.
+
360 * 0: no interrupt
+
361 * 1: YH event has occurred
+
362 * 2 YL: Y low.
+
363 * 0: no interrupt
+
364 * 1: YL event has occurred
+
365 * 1 YH: X high.
+
366 * 0: no interrupt
+
367 * 1: XH event has occurred
+
368 * 0 YL: X low.
+
369 * 0: no interrupt
+
370 * 1: XL event has occurred
+
371 *******************************************************************************/
+
372 #define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31
+
373 
+
374 /*******************************************************************************
+
375 * FF_WU_THS_1 Register: Threshold register
+
376 * Read Write register
+
377 * Default value: 0x00
+
378 * 7 DCRM: Reset mode selection.
+
379 * 0 - counter resetted
+
380 * 1 - counter decremented
+
381 * 6 THS6-THS0: Free-fall/wake-up threshold value.
+
382 *******************************************************************************/
+
383 #define LIS302DL_FF_WU_THS1_REG_ADDR 0x32
+
384 
+
385 /*******************************************************************************
+
386 * FF_WU_DURATION_1 Register: duration Register
+
387 * Read Write register
+
388 * Default value: 0x00
+
389 * 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)
+
390  ******************************************************************************/
+
391 #define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33
+
392 
+
393 /*******************************************************************************
+
394 * FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source.
+
395 * Read write register
+
396 * Default value: 0x00
+
397 * 7 AOI: AND/OR combination of Interrupt events.
+
398 * 0: OR combination of interrupt events
+
399 * 1: AND combination of interrupt events
+
400 * 6 LIR: Latch/not latch interrupt request
+
401 * 0: interrupt request not latched
+
402 * 1: interrupt request latched
+
403 * 5 ZHIE: Enable interrupt generation on Z high event.
+
404 * 0: disable interrupt request
+
405 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
406 * 4 ZLIE: Enable interrupt generation on Z low event.
+
407 * 0: disable interrupt request
+
408 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
409 * 3 YHIE: Enable interrupt generation on Y high event.
+
410 * 0: disable interrupt request
+
411 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
412 * 2 YLIE: Enable interrupt generation on Y low event.
+
413 * 0: disable interrupt request
+
414 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
415 * 1 XHIE: Enable interrupt generation on X high event.
+
416 * 0: disable interrupt request
+
417 * 1: enable interrupt request on measured accel. value higher than preset threshold
+
418 * 0 XLIE: Enable interrupt generation on X low event.
+
419 * 0: disable interrupt request
+
420 * 1: enable interrupt request on measured accel. value lower than preset threshold
+
421 *******************************************************************************/
+
422 #define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34
+
423 
+
424 /*******************************************************************************
+
425 * FF_WU_SRC_2 Register: Interrupt 2 source register.
+
426 * Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt
+
427 * and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option
+
428 * was chosen.
+
429 * Read only register
+
430 * Default value: 0x00
+
431 * 7 Reserved
+
432 * 6 IA: Interrupt active.
+
433 * 0: no interrupt has been generated
+
434 * 1: one or more interrupts have been generated
+
435 * 5 ZH: Z high.
+
436 * 0: no interrupt
+
437 * 1: ZH event has occurred
+
438 * 4 ZL: Z low.
+
439 * 0: no interrupt
+
440 * 1: ZL event has occurred
+
441 * 3 YH: Y high.
+
442 * 0: no interrupt
+
443 * 1: YH event has occurred
+
444 * 2 YL: Y low.
+
445 * 0: no interrupt
+
446 * 1: YL event has occurred
+
447 * 1 YH: X high.
+
448 * 0: no interrupt
+
449 * 1: XH event has occurred
+
450 * 0 YL: X low.
+
451 * 0: no interrupt
+
452 * 1: XL event has occurred
+
453 *******************************************************************************/
+
454 #define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35
+
455 
+
456 /*******************************************************************************
+
457 * FF_WU_THS_2 Register: Threshold register
+
458 * Read Write register
+
459 * Default value: 0x00
+
460 * 7 DCRM: Reset mode selection.
+
461 * 0 - counter resetted
+
462 * 1 - counter decremented
+
463 * 6 THS6-THS0: Free-fall/wake-up threshold value.
+
464 *******************************************************************************/
+
465 #define LIS302DL_FF_WU_THS2_REG_ADDR 0x36
+
466 
+
467 /*******************************************************************************
+
468 * FF_WU_DURATION_2 Register: duration Register
+
469 * Read Write register
+
470 * Default value: 0x00
+
471 * 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen)
+
472  ******************************************************************************/
+
473 #define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37
+
474 
+
475 /******************************************************************************
+
476 * CLICK_CFG Register: click Register
+
477 * Read Write register
+
478 * Default value: 0x00
+
479 * 7 Reserved
+
480 * 6 LIR: Latch Interrupt request.
+
481 * 0: interrupt request not latched
+
482 * 1: interrupt request latched
+
483 * 5 Double_Z: Enable interrupt generation on double click event on Z axis.
+
484 * 0: disable interrupt request
+
485 * 1: enable interrupt request
+
486 * 4 Single_Z: Enable interrupt generation on single click event on Z axis.
+
487 * 0: disable interrupt request
+
488 * 1: enable interrupt request
+
489 * 3 Double_Y: Enable interrupt generation on double click event on Y axis.
+
490 * 0: disable interrupt request
+
491 * 1: enable interrupt request
+
492 * 2 Single_Y: Enable interrupt generation on single click event on Y axis.
+
493 * 0: disable interrupt request
+
494 * 1: enable interrupt request
+
495 * 1 Double_X: Enable interrupt generation on double click event on X axis.
+
496 * 0: disable interrupt request
+
497 * 1: enable interrupt request
+
498 * 0 Single_y: Enable interrupt generation on single click event on X axis.
+
499 * 0: disable interrupt request
+
500 * 1: enable interrupt request
+
501  ******************************************************************************/
+
502 #define LIS302DL_CLICK_CFG_REG_ADDR 0x38
+
503 
+
504 /******************************************************************************
+
505 * CLICK_SRC Register: click status Register
+
506 * Read only register
+
507 * Default value: 0x00
+
508 * 7 Reserved
+
509 * 6 IA: Interrupt active.
+
510 * 0: no interrupt has been generated
+
511 * 1: one or more interrupts have been generated
+
512 * 5 Double_Z: Double click on Z axis event.
+
513 * 0: no interrupt
+
514 * 1: Double Z event has occurred
+
515 * 4 Single_Z: Z low.
+
516 * 0: no interrupt
+
517 * 1: Single Z event has occurred
+
518 * 3 Double_Y: Y high.
+
519 * 0: no interrupt
+
520 * 1: Double Y event has occurred
+
521 * 2 Single_Y: Y low.
+
522 * 0: no interrupt
+
523 * 1: Single Y event has occurred
+
524 * 1 Double_X: X high.
+
525 * 0: no interrupt
+
526 * 1: Double X event has occurred
+
527 * 0 Single_X: X low.
+
528 * 0: no interrupt
+
529 * 1: Single X event has occurred
+
530 *******************************************************************************/
+
531 #define LIS302DL_CLICK_SRC_REG_ADDR 0x39
+
532 
+
533 /*******************************************************************************
+
534 * CLICK_THSY_X Register: Click threshold Y and X register
+
535 * Read Write register
+
536 * Default value: 0x00
+
537 * 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g
+
538 * 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g
+
539 *******************************************************************************/
+
540 #define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B
+
541 
+
542 /*******************************************************************************
+
543 * CLICK_THSZ Register: Click threshold Z register
+
544 * Read Write register
+
545 * Default value: 0x00
+
546 * 7:4 Reserved
+
547 * 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g
+
548 *******************************************************************************/
+
549 #define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C
+
550 
+
551 /*******************************************************************************
+
552 * CLICK_TimeLimit Register: Time Limit register
+
553 * Read Write register
+
554 * Default value: 0x00
+
555 * 7:0 Dur7-Dur0: Time Limit value, step 0.5g
+
556 *******************************************************************************/
+
557 #define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D
+
558 
+
559 /*******************************************************************************
+
560 * CLICK_Latency Register: Latency register
+
561 * Read Write register
+
562 * Default value: 0x00
+
563 * 7:0 Lat7-Lat0: Latency value, step 1msec
+
564 *******************************************************************************/
+
565 #define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E
+
566 
+
567 /*******************************************************************************
+
568 * CLICK_Window Register: Window register
+
569 * Read Write register
+
570 * Default value: 0x00
+
571 * 7:0 Win7-Win0: Window value, step 1msec
+
572 *******************************************************************************/
+
573 #define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F
+
574 
+
575 /******************************************************************************/
+
576 /**************************** END REGISTER MAPPING ***************************/
+
577 /******************************************************************************/
+
578 
+
579 #define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/
+
580 #define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/
+
581 
+
585 #define LIS302DL_DATARATE_100 ((uint8_t)0x00)
+
586 #define LIS302DL_DATARATE_400 ((uint8_t)0x80)
+
587 
+
594 #define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00)
+
595 #define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40)
+
596 
+
603 #define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00)
+
604 #define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20)
+
605 
+
612 #define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00)
+
613 #define LIS302DL_SELFTEST_P ((uint8_t)0x10)
+
614 #define LIS302DL_SELFTEST_M ((uint8_t)0x08)
+
615 
+
622 #define LIS302DL_X_ENABLE ((uint8_t)0x01)
+
623 #define LIS302DL_Y_ENABLE ((uint8_t)0x02)
+
624 #define LIS302DL_Z_ENABLE ((uint8_t)0x04)
+
625 #define LIS302DL_XYZ_ENABLE ((uint8_t)0x07)
+
626 
+
633 #define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00)
+
634 #define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80)
+
635 
+
642 #define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00)
+
643 #define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40)
+
644 
+
651 #define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00)
+
652 #define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20)
+
653 
+
660 #define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00)
+
661 #define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04)
+
662 #define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08)
+
663 #define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C)
+
664 
+
671 #define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00)
+
672 #define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01)
+
673 #define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02)
+
674 #define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03)
+
675 
+
683 #define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00)
+
684 #define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40)
+
685 
+
692 #define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)
+
693 #define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01)
+
694 #define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04)
+
695 #define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10)
+
696 #define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15)
+
697 
+
704 #define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00)
+
705 #define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02)
+
706 #define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08)
+
707 #define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20)
+
708 #define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A)
+
709 
+
719 #define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
+
720 #define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN)
+
721 
+
728 void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct);
+
729 void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct);
+
730 void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct);
+
731 void LIS302DL_LowpowerCmd(uint8_t LowPowerMode);
+
732 void LIS302DL_FullScaleCmd(uint8_t FS_value);
+
733 void LIS302DL_DataRateCmd(uint8_t DataRateValue);
+
734 void LIS302DL_RebootCmd(void);
+
735 void LIS302DL_ReadACC(int32_t* out);
+
736 void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
+
737 void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
+
738 
+
739 /* USER Callbacks: This is function for which prototype only is declared in
+
740  MEMS accelerometre driver and that should be implemented into user applicaiton. */
+
741 /* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition
+
742  occure during communication (waiting transmit data register empty flag(TXE)
+
743  or waiting receive data register is not empty flag (RXNE)).
+
744  You can use the default timeout callback implementation by uncommenting the
+
745  define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file.
+
746  Typically the user implementation of this callback should reset MEMS peripheral
+
747  and re-initialize communication or in worst case reset all the application. */
+
748 uint32_t LIS302DL_TIMEOUT_UserCallback(void);
+
749 
+
750 #ifdef __cplusplus
+
751 }
+
752 #endif
+
753 
+
754 #endif /* __STM32F4_DISCOVERY_LIS302DL_H */
+
755 
+
772 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
LIS302DL_Read
void LIS302DL_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
Reads a block of data from the LIS302DL.
Definition: stm32f4_discovery_lis302dl.c:291
+
LIS302DL_FullScaleCmd
void LIS302DL_FullScaleCmd(uint8_t FS_value)
Change the Full Scale of LIS302DL.
Definition: stm32f4_discovery_lis302dl.c:217
+
LIS302DL_DataRateCmd
void LIS302DL_DataRateCmd(uint8_t DataRateValue)
Data Rate command.
Definition: stm32f4_discovery_lis302dl.c:194
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
LIS302DL_ReadACC
void LIS302DL_ReadACC(int32_t *out)
Read LIS302DL output register, and calculate the acceleration ACC[mg]=SENSITIVITY* (out_h*256+out_l)/...
Definition: stm32f4_discovery_lis302dl.c:326
+
LIS302DL_FilterConfig
void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct)
Set LIS302DL Internal High Pass Filter configuration.
Definition: stm32f4_discovery_lis302dl.c:121
+
LIS302DL_FilterConfigTypeDef
Definition: stm32f4_discovery_lis302dl.h:62
+
LIS302DL_Init
void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct)
Set LIS302DL Initialization.
Definition: stm32f4_discovery_lis302dl.c:99
+
LIS302DL_InterruptConfigTypeDef
Definition: stm32f4_discovery_lis302dl.h:70
+
LIS302DL_InterruptConfig
void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct)
Set LIS302DL Interrupt configuration.
Definition: stm32f4_discovery_lis302dl.c:147
+
LIS302DL_LowpowerCmd
void LIS302DL_LowpowerCmd(uint8_t LowPowerMode)
Change the lowpower mode for LIS302DL.
Definition: stm32f4_discovery_lis302dl.c:171
+
LIS302DL_InitTypeDef
Definition: stm32f4_discovery_lis302dl.h:52
+
LIS302DL_RebootCmd
void LIS302DL_RebootCmd(void)
Reboot memory content of LIS302DL.
Definition: stm32f4_discovery_lis302dl.c:237
+
LIS302DL_Write
void LIS302DL_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
Writes one byte to the LIS302DL.
Definition: stm32f4_discovery_lis302dl.c:257
+
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stm32f4xx.h File Reference
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CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F4xx devices. +More...

+
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+#include "system_stm32f4xx.h"
+#include <stdint.h>
+#include "stm32f4xx_conf.h"
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struct  ADC_TypeDef
 Analog to Digital Converter. More...
 
struct  ADC_Common_TypeDef
 
struct  CAN_TxMailBox_TypeDef
 Controller Area Network TxMailBox. More...
 
struct  CAN_FIFOMailBox_TypeDef
 Controller Area Network FIFOMailBox. More...
 
struct  CAN_FilterRegister_TypeDef
 Controller Area Network FilterRegister. More...
 
struct  CAN_TypeDef
 Controller Area Network. More...
 
struct  CRC_TypeDef
 CRC calculation unit. More...
 
struct  DAC_TypeDef
 Digital to Analog Converter. More...
 
struct  DBGMCU_TypeDef
 Debug MCU. More...
 
struct  DCMI_TypeDef
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define STM32F40_41xxx
 
#define USE_STDPERIPH_DRIVER
 Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers. More...
 
#define HSE_VALUE   ((uint32_t)8000000)
 In the following line adjust the value of External High Speed oscillator (HSE) used in your application. More...
 
#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x05000)
 In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value. More...
 
#define HSI_VALUE   ((uint32_t)16000000)
 
#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01)
 STM32F4XX Standard Peripherals Library version number V1.4.0. More...
 
#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x04)
 
#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00)
 
#define __STM32F4XX_STDPERIPH_VERSION_RC   (0x00)
 
#define __STM32F4XX_STDPERIPH_VERSION
 
#define __CM4_REV   0x0001
 Configuration of the Cortex-M4 Processor and Core Peripherals. More...
 
#define __MPU_PRESENT   1
 
#define __NVIC_PRIO_BITS   4
 
#define __Vendor_SysTickConfig   0
 
#define __FPU_PRESENT   1
 
+#define IS_FUNCTIONAL_STATE(STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
#define FLASH_BASE   ((uint32_t)0x08000000)
 
#define CCMDATARAM_BASE   ((uint32_t)0x10000000)
 
#define SRAM1_BASE   ((uint32_t)0x20000000)
 
#define SRAM2_BASE   ((uint32_t)0x2001C000)
 
#define SRAM3_BASE   ((uint32_t)0x20020000)
 
#define PERIPH_BASE   ((uint32_t)0x40000000)
 
#define BKPSRAM_BASE   ((uint32_t)0x40024000)
 
#define FSMC_R_BASE   ((uint32_t)0xA0000000)
 
#define CCMDATARAM_BB_BASE   ((uint32_t)0x12000000)
 
#define SRAM1_BB_BASE   ((uint32_t)0x22000000)
 
#define SRAM2_BB_BASE   ((uint32_t)0x2201C000)
 
#define SRAM3_BB_BASE   ((uint32_t)0x22400000)
 
#define PERIPH_BB_BASE   ((uint32_t)0x42000000)
 
#define BKPSRAM_BB_BASE   ((uint32_t)0x42024000)
 
+#define SRAM_BASE   SRAM1_BASE
 
#define SRAM_BB_BASE   SRAM1_BB_BASE
 
+#define APB1PERIPH_BASE   PERIPH_BASE
 
+#define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000)
 
+#define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000)
 
#define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000)
 
+#define TIM2_BASE   (APB1PERIPH_BASE + 0x0000)
 
+#define TIM3_BASE   (APB1PERIPH_BASE + 0x0400)
 
+#define TIM4_BASE   (APB1PERIPH_BASE + 0x0800)
 
+#define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00)
 
+#define TIM6_BASE   (APB1PERIPH_BASE + 0x1000)
 
+#define TIM7_BASE   (APB1PERIPH_BASE + 0x1400)
 
+#define TIM12_BASE   (APB1PERIPH_BASE + 0x1800)
 
+#define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00)
 
+#define TIM14_BASE   (APB1PERIPH_BASE + 0x2000)
 
+#define RTC_BASE   (APB1PERIPH_BASE + 0x2800)
 
+#define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00)
 
+#define IWDG_BASE   (APB1PERIPH_BASE + 0x3000)
 
+#define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400)
 
+#define SPI2_BASE   (APB1PERIPH_BASE + 0x3800)
 
+#define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00)
 
+#define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000)
 
+#define USART2_BASE   (APB1PERIPH_BASE + 0x4400)
 
+#define USART3_BASE   (APB1PERIPH_BASE + 0x4800)
 
+#define UART4_BASE   (APB1PERIPH_BASE + 0x4C00)
 
+#define UART5_BASE   (APB1PERIPH_BASE + 0x5000)
 
+#define I2C1_BASE   (APB1PERIPH_BASE + 0x5400)
 
+#define I2C2_BASE   (APB1PERIPH_BASE + 0x5800)
 
+#define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00)
 
+#define CAN1_BASE   (APB1PERIPH_BASE + 0x6400)
 
+#define CAN2_BASE   (APB1PERIPH_BASE + 0x6800)
 
+#define PWR_BASE   (APB1PERIPH_BASE + 0x7000)
 
+#define DAC_BASE   (APB1PERIPH_BASE + 0x7400)
 
+#define UART7_BASE   (APB1PERIPH_BASE + 0x7800)
 
#define UART8_BASE   (APB1PERIPH_BASE + 0x7C00)
 
+#define TIM1_BASE   (APB2PERIPH_BASE + 0x0000)
 
+#define TIM8_BASE   (APB2PERIPH_BASE + 0x0400)
 
+#define USART1_BASE   (APB2PERIPH_BASE + 0x1000)
 
+#define USART6_BASE   (APB2PERIPH_BASE + 0x1400)
 
+#define ADC1_BASE   (APB2PERIPH_BASE + 0x2000)
 
+#define ADC2_BASE   (APB2PERIPH_BASE + 0x2100)
 
+#define ADC3_BASE   (APB2PERIPH_BASE + 0x2200)
 
+#define ADC_BASE   (APB2PERIPH_BASE + 0x2300)
 
+#define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00)
 
+#define SPI1_BASE   (APB2PERIPH_BASE + 0x3000)
 
+#define SPI4_BASE   (APB2PERIPH_BASE + 0x3400)
 
+#define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800)
 
+#define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00)
 
+#define TIM9_BASE   (APB2PERIPH_BASE + 0x4000)
 
+#define TIM10_BASE   (APB2PERIPH_BASE + 0x4400)
 
+#define TIM11_BASE   (APB2PERIPH_BASE + 0x4800)
 
+#define SPI5_BASE   (APB2PERIPH_BASE + 0x5000)
 
+#define SPI6_BASE   (APB2PERIPH_BASE + 0x5400)
 
+#define SAI1_BASE   (APB2PERIPH_BASE + 0x5800)
 
+#define SAI1_Block_A_BASE   (SAI1_BASE + 0x004)
 
+#define SAI1_Block_B_BASE   (SAI1_BASE + 0x024)
 
+#define LTDC_BASE   (APB2PERIPH_BASE + 0x6800)
 
+#define LTDC_Layer1_BASE   (LTDC_BASE + 0x84)
 
#define LTDC_Layer2_BASE   (LTDC_BASE + 0x104)
 
+#define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000)
 
+#define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400)
 
+#define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800)
 
+#define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00)
 
+#define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000)
 
+#define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400)
 
+#define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800)
 
+#define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00)
 
+#define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000)
 
+#define GPIOJ_BASE   (AHB1PERIPH_BASE + 0x2400)
 
+#define GPIOK_BASE   (AHB1PERIPH_BASE + 0x2800)
 
+#define CRC_BASE   (AHB1PERIPH_BASE + 0x3000)
 
+#define RCC_BASE   (AHB1PERIPH_BASE + 0x3800)
 
+#define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00)
 
+#define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000)
 
+#define DMA1_Stream0_BASE   (DMA1_BASE + 0x010)
 
+#define DMA1_Stream1_BASE   (DMA1_BASE + 0x028)
 
+#define DMA1_Stream2_BASE   (DMA1_BASE + 0x040)
 
+#define DMA1_Stream3_BASE   (DMA1_BASE + 0x058)
 
+#define DMA1_Stream4_BASE   (DMA1_BASE + 0x070)
 
+#define DMA1_Stream5_BASE   (DMA1_BASE + 0x088)
 
+#define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0)
 
+#define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8)
 
+#define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400)
 
+#define DMA2_Stream0_BASE   (DMA2_BASE + 0x010)
 
+#define DMA2_Stream1_BASE   (DMA2_BASE + 0x028)
 
+#define DMA2_Stream2_BASE   (DMA2_BASE + 0x040)
 
+#define DMA2_Stream3_BASE   (DMA2_BASE + 0x058)
 
+#define DMA2_Stream4_BASE   (DMA2_BASE + 0x070)
 
+#define DMA2_Stream5_BASE   (DMA2_BASE + 0x088)
 
+#define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0)
 
+#define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8)
 
+#define ETH_BASE   (AHB1PERIPH_BASE + 0x8000)
 
+#define ETH_MAC_BASE   (ETH_BASE)
 
+#define ETH_MMC_BASE   (ETH_BASE + 0x0100)
 
+#define ETH_PTP_BASE   (ETH_BASE + 0x0700)
 
+#define ETH_DMA_BASE   (ETH_BASE + 0x1000)
 
#define DMA2D_BASE   (AHB1PERIPH_BASE + 0xB000)
 
+#define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000)
 
+#define CRYP_BASE   (AHB2PERIPH_BASE + 0x60000)
 
+#define HASH_BASE   (AHB2PERIPH_BASE + 0x60400)
 
+#define HASH_DIGEST_BASE   (AHB2PERIPH_BASE + 0x60710)
 
#define RNG_BASE   (AHB2PERIPH_BASE + 0x60800)
 
+#define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000)
 
+#define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104)
 
+#define FSMC_Bank2_R_BASE   (FSMC_R_BASE + 0x0060)
 
+#define FSMC_Bank3_R_BASE   (FSMC_R_BASE + 0x0080)
 
+#define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0)
 
+#define DBGMCU_BASE   ((uint32_t )0xE0042000)
 
+#define TIM2   ((TIM_TypeDef *) TIM2_BASE)
 
+#define TIM3   ((TIM_TypeDef *) TIM3_BASE)
 
+#define TIM4   ((TIM_TypeDef *) TIM4_BASE)
 
+#define TIM5   ((TIM_TypeDef *) TIM5_BASE)
 
+#define TIM6   ((TIM_TypeDef *) TIM6_BASE)
 
+#define TIM7   ((TIM_TypeDef *) TIM7_BASE)
 
+#define TIM12   ((TIM_TypeDef *) TIM12_BASE)
 
+#define TIM13   ((TIM_TypeDef *) TIM13_BASE)
 
+#define TIM14   ((TIM_TypeDef *) TIM14_BASE)
 
+#define RTC   ((RTC_TypeDef *) RTC_BASE)
 
+#define WWDG   ((WWDG_TypeDef *) WWDG_BASE)
 
+#define IWDG   ((IWDG_TypeDef *) IWDG_BASE)
 
+#define I2S2ext   ((SPI_TypeDef *) I2S2ext_BASE)
 
+#define SPI2   ((SPI_TypeDef *) SPI2_BASE)
 
+#define SPI3   ((SPI_TypeDef *) SPI3_BASE)
 
+#define I2S3ext   ((SPI_TypeDef *) I2S3ext_BASE)
 
+#define USART2   ((USART_TypeDef *) USART2_BASE)
 
+#define USART3   ((USART_TypeDef *) USART3_BASE)
 
+#define UART4   ((USART_TypeDef *) UART4_BASE)
 
+#define UART5   ((USART_TypeDef *) UART5_BASE)
 
+#define I2C1   ((I2C_TypeDef *) I2C1_BASE)
 
+#define I2C2   ((I2C_TypeDef *) I2C2_BASE)
 
+#define I2C3   ((I2C_TypeDef *) I2C3_BASE)
 
+#define CAN1   ((CAN_TypeDef *) CAN1_BASE)
 
+#define CAN2   ((CAN_TypeDef *) CAN2_BASE)
 
+#define PWR   ((PWR_TypeDef *) PWR_BASE)
 
+#define DAC   ((DAC_TypeDef *) DAC_BASE)
 
+#define UART7   ((USART_TypeDef *) UART7_BASE)
 
+#define UART8   ((USART_TypeDef *) UART8_BASE)
 
+#define TIM1   ((TIM_TypeDef *) TIM1_BASE)
 
+#define TIM8   ((TIM_TypeDef *) TIM8_BASE)
 
+#define USART1   ((USART_TypeDef *) USART1_BASE)
 
+#define USART6   ((USART_TypeDef *) USART6_BASE)
 
+#define ADC   ((ADC_Common_TypeDef *) ADC_BASE)
 
+#define ADC1   ((ADC_TypeDef *) ADC1_BASE)
 
+#define ADC2   ((ADC_TypeDef *) ADC2_BASE)
 
+#define ADC3   ((ADC_TypeDef *) ADC3_BASE)
 
+#define SDIO   ((SDIO_TypeDef *) SDIO_BASE)
 
+#define SPI1   ((SPI_TypeDef *) SPI1_BASE)
 
+#define SPI4   ((SPI_TypeDef *) SPI4_BASE)
 
+#define SYSCFG   ((SYSCFG_TypeDef *) SYSCFG_BASE)
 
+#define EXTI   ((EXTI_TypeDef *) EXTI_BASE)
 
+#define TIM9   ((TIM_TypeDef *) TIM9_BASE)
 
+#define TIM10   ((TIM_TypeDef *) TIM10_BASE)
 
+#define TIM11   ((TIM_TypeDef *) TIM11_BASE)
 
+#define SPI5   ((SPI_TypeDef *) SPI5_BASE)
 
+#define SPI6   ((SPI_TypeDef *) SPI6_BASE)
 
+#define SAI1   ((SAI_TypeDef *) SAI1_BASE)
 
+#define SAI1_Block_A   ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
 
+#define SAI1_Block_B   ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
 
+#define LTDC   ((LTDC_TypeDef *)LTDC_BASE)
 
+#define LTDC_Layer1   ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
 
+#define LTDC_Layer2   ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
 
+#define GPIOA   ((GPIO_TypeDef *) GPIOA_BASE)
 
+#define GPIOB   ((GPIO_TypeDef *) GPIOB_BASE)
 
+#define GPIOC   ((GPIO_TypeDef *) GPIOC_BASE)
 
+#define GPIOD   ((GPIO_TypeDef *) GPIOD_BASE)
 
+#define GPIOE   ((GPIO_TypeDef *) GPIOE_BASE)
 
+#define GPIOF   ((GPIO_TypeDef *) GPIOF_BASE)
 
+#define GPIOG   ((GPIO_TypeDef *) GPIOG_BASE)
 
+#define GPIOH   ((GPIO_TypeDef *) GPIOH_BASE)
 
+#define GPIOI   ((GPIO_TypeDef *) GPIOI_BASE)
 
+#define GPIOJ   ((GPIO_TypeDef *) GPIOJ_BASE)
 
+#define GPIOK   ((GPIO_TypeDef *) GPIOK_BASE)
 
+#define CRC   ((CRC_TypeDef *) CRC_BASE)
 
+#define RCC   ((RCC_TypeDef *) RCC_BASE)
 
+#define FLASH   ((FLASH_TypeDef *) FLASH_R_BASE)
 
+#define DMA1   ((DMA_TypeDef *) DMA1_BASE)
 
+#define DMA1_Stream0   ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
 
+#define DMA1_Stream1   ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
 
+#define DMA1_Stream2   ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
 
+#define DMA1_Stream3   ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
 
+#define DMA1_Stream4   ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
 
+#define DMA1_Stream5   ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
 
+#define DMA1_Stream6   ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
 
+#define DMA1_Stream7   ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
 
+#define DMA2   ((DMA_TypeDef *) DMA2_BASE)
 
+#define DMA2_Stream0   ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
 
+#define DMA2_Stream1   ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
 
+#define DMA2_Stream2   ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
 
+#define DMA2_Stream3   ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
 
+#define DMA2_Stream4   ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
 
+#define DMA2_Stream5   ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
 
+#define DMA2_Stream6   ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
 
+#define DMA2_Stream7   ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
 
+#define ETH   ((ETH_TypeDef *) ETH_BASE)
 
+#define DMA2D   ((DMA2D_TypeDef *)DMA2D_BASE)
 
+#define DCMI   ((DCMI_TypeDef *) DCMI_BASE)
 
+#define CRYP   ((CRYP_TypeDef *) CRYP_BASE)
 
+#define HASH   ((HASH_TypeDef *) HASH_BASE)
 
+#define HASH_DIGEST   ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
 
+#define RNG   ((RNG_TypeDef *) RNG_BASE)
 
+#define FSMC_Bank1   ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
 
+#define FSMC_Bank1E   ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
 
+#define FSMC_Bank2   ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
 
+#define FSMC_Bank3   ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
 
+#define FSMC_Bank4   ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
 
+#define DBGMCU   ((DBGMCU_TypeDef *) DBGMCU_BASE)
 
#define ADC_SR_AWD   ((uint8_t)0x01)
 
#define ADC_SR_EOC   ((uint8_t)0x02)
 
#define ADC_SR_JEOC   ((uint8_t)0x04)
 
#define ADC_SR_JSTRT   ((uint8_t)0x08)
 
#define ADC_SR_STRT   ((uint8_t)0x10)
 
#define ADC_SR_OVR   ((uint8_t)0x20)
 
#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
 
#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
 
#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
 
#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
 
#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
 
#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
 
#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)
 
#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)
 
#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
 
#define ADC_CR1_SCAN   ((uint32_t)0x00000100)
 
#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
 
#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)
 
#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)
 
#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
 
#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
 
#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
 
#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
 
#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
 
#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
 
#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)
 
#define ADC_CR1_RES   ((uint32_t)0x03000000)
 
#define ADC_CR1_RES_0   ((uint32_t)0x01000000)
 
#define ADC_CR1_RES_1   ((uint32_t)0x02000000)
 
#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)
 
#define ADC_CR2_ADON   ((uint32_t)0x00000001)
 
#define ADC_CR2_CONT   ((uint32_t)0x00000002)
 
#define ADC_CR2_DMA   ((uint32_t)0x00000100)
 
#define ADC_CR2_DDS   ((uint32_t)0x00000200)
 
#define ADC_CR2_EOCS   ((uint32_t)0x00000400)
 
#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)
 
#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
 
#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
 
#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
 
#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
 
#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
 
#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
 
#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
 
#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
 
#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
 
#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
 
#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
 
#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
 
#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
 
#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
 
#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)
 
#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
 
#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
 
#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)
 
#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
 
#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
 
#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
 
#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
 
#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
 
#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
 
#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
 
#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
 
#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
 
#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
 
#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
 
#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
 
#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
 
#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
 
#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
 
#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
 
#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
 
#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
 
#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
 
#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
 
#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
 
#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
 
#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
 
#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
 
#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
 
#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
 
#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
 
#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
 
#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
 
#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
 
#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
 
#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
 
#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
 
#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
 
#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
 
#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
 
#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
 
#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
 
#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
 
#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
 
#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
 
#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
 
#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
 
#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
 
#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
 
#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
 
#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
 
#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
 
#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
 
#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
 
#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
 
#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
 
#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
 
#define ADC_HTR_HT   ((uint16_t)0x0FFF)
 
#define ADC_LTR_LT   ((uint16_t)0x0FFF)
 
#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
 
#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
 
#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
 
#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
 
#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
 
#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
 
#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
 
#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
 
#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
 
#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
 
#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
 
#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
 
#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
 
#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
 
#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
 
#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
 
#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
 
#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
 
#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
 
#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
 
#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
 
#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
 
#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
 
#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
 
#define ADC_SQR1_L   ((uint32_t)0x00F00000)
 
#define ADC_SQR1_L_0   ((uint32_t)0x00100000)
 
#define ADC_SQR1_L_1   ((uint32_t)0x00200000)
 
#define ADC_SQR1_L_2   ((uint32_t)0x00400000)
 
#define ADC_SQR1_L_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
 
#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
 
#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
 
#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
 
#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
 
#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
 
#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
 
#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
 
#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
 
#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
 
#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
 
#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
 
#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
 
#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
 
#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
 
#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
 
#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
 
#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
 
#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
 
#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
 
#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
 
#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
 
#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
 
#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
 
#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
 
#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
 
#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
 
#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
 
#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
 
#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
 
#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
 
#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
 
#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
 
#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
 
#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
 
#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
 
#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
 
#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
 
#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
 
#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
 
#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
 
#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
 
#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
 
#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
 
#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
 
#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
 
#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
 
#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
 
#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
 
#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
 
#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
 
#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
 
#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
 
#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
 
#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
 
#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
 
#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
 
#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
 
#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
 
#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
 
#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
 
#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
 
#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
 
#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
 
#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
 
#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
 
#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
 
#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
 
#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
 
#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
 
#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
 
#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
 
#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
 
#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
 
#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
 
#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
 
#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
 
#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
 
#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
 
#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
 
#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
 
#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
 
#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
 
#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
 
#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
 
#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
 
#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
 
#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
 
#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
 
#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
 
#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
 
#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
 
#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
 
#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
 
#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
 
#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
 
#define ADC_JSQR_JL   ((uint32_t)0x00300000)
 
#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)
 
#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)
 
#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
 
#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)
 
#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
 
#define ADC_CSR_AWD1   ((uint32_t)0x00000001)
 
#define ADC_CSR_EOC1   ((uint32_t)0x00000002)
 
#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)
 
#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
 
#define ADC_CSR_STRT1   ((uint32_t)0x00000010)
 
#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)
 
#define ADC_CSR_AWD2   ((uint32_t)0x00000100)
 
#define ADC_CSR_EOC2   ((uint32_t)0x00000200)
 
#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)
 
#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
 
#define ADC_CSR_STRT2   ((uint32_t)0x00001000)
 
#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)
 
#define ADC_CSR_AWD3   ((uint32_t)0x00010000)
 
#define ADC_CSR_EOC3   ((uint32_t)0x00020000)
 
#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)
 
#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
 
#define ADC_CSR_STRT3   ((uint32_t)0x00100000)
 
#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)
 
#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)
 
#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
 
#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
 
#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
 
#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
 
#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
 
#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)
 
#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
 
#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
 
#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
 
#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
 
#define ADC_CCR_DDS   ((uint32_t)0x00002000)
 
#define ADC_CCR_DMA   ((uint32_t)0x0000C000)
 
#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)
 
#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)
 
#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
 
#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
 
#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
 
#define ADC_CCR_VBATE   ((uint32_t)0x00400000)
 
#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
 
#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
 
#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
 
#define CAN_MCR_INRQ   ((uint16_t)0x0001)
 
#define CAN_MCR_SLEEP   ((uint16_t)0x0002)
 
#define CAN_MCR_TXFP   ((uint16_t)0x0004)
 
#define CAN_MCR_RFLM   ((uint16_t)0x0008)
 
#define CAN_MCR_NART   ((uint16_t)0x0010)
 
#define CAN_MCR_AWUM   ((uint16_t)0x0020)
 
#define CAN_MCR_ABOM   ((uint16_t)0x0040)
 
#define CAN_MCR_TTCM   ((uint16_t)0x0080)
 
#define CAN_MCR_RESET   ((uint16_t)0x8000)
 
#define CAN_MSR_INAK   ((uint16_t)0x0001)
 
#define CAN_MSR_SLAK   ((uint16_t)0x0002)
 
#define CAN_MSR_ERRI   ((uint16_t)0x0004)
 
#define CAN_MSR_WKUI   ((uint16_t)0x0008)
 
#define CAN_MSR_SLAKI   ((uint16_t)0x0010)
 
#define CAN_MSR_TXM   ((uint16_t)0x0100)
 
#define CAN_MSR_RXM   ((uint16_t)0x0200)
 
#define CAN_MSR_SAMP   ((uint16_t)0x0400)
 
#define CAN_MSR_RX   ((uint16_t)0x0800)
 
#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)
 
#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)
 
#define CAN_TSR_ALST0   ((uint32_t)0x00000004)
 
#define CAN_TSR_TERR0   ((uint32_t)0x00000008)
 
#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
 
#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)
 
#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)
 
#define CAN_TSR_ALST1   ((uint32_t)0x00000400)
 
#define CAN_TSR_TERR1   ((uint32_t)0x00000800)
 
#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
 
#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)
 
#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)
 
#define CAN_TSR_ALST2   ((uint32_t)0x00040000)
 
#define CAN_TSR_TERR2   ((uint32_t)0x00080000)
 
#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
 
#define CAN_TSR_CODE   ((uint32_t)0x03000000)
 
#define CAN_TSR_TME   ((uint32_t)0x1C000000)
 
#define CAN_TSR_TME0   ((uint32_t)0x04000000)
 
#define CAN_TSR_TME1   ((uint32_t)0x08000000)
 
#define CAN_TSR_TME2   ((uint32_t)0x10000000)
 
#define CAN_TSR_LOW   ((uint32_t)0xE0000000)
 
#define CAN_TSR_LOW0   ((uint32_t)0x20000000)
 
#define CAN_TSR_LOW1   ((uint32_t)0x40000000)
 
#define CAN_TSR_LOW2   ((uint32_t)0x80000000)
 
#define CAN_RF0R_FMP0   ((uint8_t)0x03)
 
#define CAN_RF0R_FULL0   ((uint8_t)0x08)
 
#define CAN_RF0R_FOVR0   ((uint8_t)0x10)
 
#define CAN_RF0R_RFOM0   ((uint8_t)0x20)
 
#define CAN_RF1R_FMP1   ((uint8_t)0x03)
 
#define CAN_RF1R_FULL1   ((uint8_t)0x08)
 
#define CAN_RF1R_FOVR1   ((uint8_t)0x10)
 
#define CAN_RF1R_RFOM1   ((uint8_t)0x20)
 
#define CAN_IER_TMEIE   ((uint32_t)0x00000001)
 
#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)
 
#define CAN_IER_FFIE0   ((uint32_t)0x00000004)
 
#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)
 
#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)
 
#define CAN_IER_FFIE1   ((uint32_t)0x00000020)
 
#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)
 
#define CAN_IER_EWGIE   ((uint32_t)0x00000100)
 
#define CAN_IER_EPVIE   ((uint32_t)0x00000200)
 
#define CAN_IER_BOFIE   ((uint32_t)0x00000400)
 
#define CAN_IER_LECIE   ((uint32_t)0x00000800)
 
#define CAN_IER_ERRIE   ((uint32_t)0x00008000)
 
#define CAN_IER_WKUIE   ((uint32_t)0x00010000)
 
#define CAN_IER_SLKIE   ((uint32_t)0x00020000)
 
#define CAN_ESR_EWGF   ((uint32_t)0x00000001)
 
#define CAN_ESR_EPVF   ((uint32_t)0x00000002)
 
#define CAN_ESR_BOFF   ((uint32_t)0x00000004)
 
#define CAN_ESR_LEC   ((uint32_t)0x00000070)
 
#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)
 
#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)
 
#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)
 
#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)
 
#define CAN_ESR_REC   ((uint32_t)0xFF000000)
 
#define CAN_BTR_BRP   ((uint32_t)0x000003FF)
 
#define CAN_BTR_TS1   ((uint32_t)0x000F0000)
 
#define CAN_BTR_TS2   ((uint32_t)0x00700000)
 
#define CAN_BTR_SJW   ((uint32_t)0x03000000)
 
#define CAN_BTR_LBKM   ((uint32_t)0x40000000)
 
#define CAN_BTR_SILM   ((uint32_t)0x80000000)
 
#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
 
#define CAN_TI2R_RTR   ((uint32_t)0x00000002)
 
#define CAN_TI2R_IDE   ((uint32_t)0x00000004)
 
#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)
 
#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI0R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI0R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_RI1R_RTR   ((uint32_t)0x00000002)
 
#define CAN_RI1R_IDE   ((uint32_t)0x00000004)
 
#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
 
#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)
 
#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
 
#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
 
#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
 
#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
 
#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
 
#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
 
#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
 
#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
 
#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
 
#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
 
#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
 
#define CAN_FMR_FINIT   ((uint8_t)0x01)
 
#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)
 
#define CAN_FM1R_FBM0   ((uint16_t)0x0001)
 
#define CAN_FM1R_FBM1   ((uint16_t)0x0002)
 
#define CAN_FM1R_FBM2   ((uint16_t)0x0004)
 
#define CAN_FM1R_FBM3   ((uint16_t)0x0008)
 
#define CAN_FM1R_FBM4   ((uint16_t)0x0010)
 
#define CAN_FM1R_FBM5   ((uint16_t)0x0020)
 
#define CAN_FM1R_FBM6   ((uint16_t)0x0040)
 
#define CAN_FM1R_FBM7   ((uint16_t)0x0080)
 
#define CAN_FM1R_FBM8   ((uint16_t)0x0100)
 
#define CAN_FM1R_FBM9   ((uint16_t)0x0200)
 
#define CAN_FM1R_FBM10   ((uint16_t)0x0400)
 
#define CAN_FM1R_FBM11   ((uint16_t)0x0800)
 
#define CAN_FM1R_FBM12   ((uint16_t)0x1000)
 
#define CAN_FM1R_FBM13   ((uint16_t)0x2000)
 
#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)
 
#define CAN_FS1R_FSC0   ((uint16_t)0x0001)
 
#define CAN_FS1R_FSC1   ((uint16_t)0x0002)
 
#define CAN_FS1R_FSC2   ((uint16_t)0x0004)
 
#define CAN_FS1R_FSC3   ((uint16_t)0x0008)
 
#define CAN_FS1R_FSC4   ((uint16_t)0x0010)
 
#define CAN_FS1R_FSC5   ((uint16_t)0x0020)
 
#define CAN_FS1R_FSC6   ((uint16_t)0x0040)
 
#define CAN_FS1R_FSC7   ((uint16_t)0x0080)
 
#define CAN_FS1R_FSC8   ((uint16_t)0x0100)
 
#define CAN_FS1R_FSC9   ((uint16_t)0x0200)
 
#define CAN_FS1R_FSC10   ((uint16_t)0x0400)
 
#define CAN_FS1R_FSC11   ((uint16_t)0x0800)
 
#define CAN_FS1R_FSC12   ((uint16_t)0x1000)
 
#define CAN_FS1R_FSC13   ((uint16_t)0x2000)
 
#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
 
#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)
 
#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)
 
#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)
 
#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)
 
#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)
 
#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)
 
#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)
 
#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)
 
#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)
 
#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)
 
#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)
 
#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)
 
#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)
 
#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)
 
#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)
 
#define CAN_FA1R_FACT0   ((uint16_t)0x0001)
 
#define CAN_FA1R_FACT1   ((uint16_t)0x0002)
 
#define CAN_FA1R_FACT2   ((uint16_t)0x0004)
 
#define CAN_FA1R_FACT3   ((uint16_t)0x0008)
 
#define CAN_FA1R_FACT4   ((uint16_t)0x0010)
 
#define CAN_FA1R_FACT5   ((uint16_t)0x0020)
 
#define CAN_FA1R_FACT6   ((uint16_t)0x0040)
 
#define CAN_FA1R_FACT7   ((uint16_t)0x0080)
 
#define CAN_FA1R_FACT8   ((uint16_t)0x0100)
 
#define CAN_FA1R_FACT9   ((uint16_t)0x0200)
 
#define CAN_FA1R_FACT10   ((uint16_t)0x0400)
 
#define CAN_FA1R_FACT11   ((uint16_t)0x0800)
 
#define CAN_FA1R_FACT12   ((uint16_t)0x1000)
 
#define CAN_FA1R_FACT13   ((uint16_t)0x2000)
 
#define CAN_F0R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R1_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R1_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R1_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R1_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R1_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R1_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R1_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R1_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R1_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R1_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R1_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R1_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R1_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R1_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R1_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R1_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R1_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R1_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R1_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R1_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R1_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R1_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R1_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R1_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R1_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R1_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R1_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R1_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R1_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R1_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R1_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R1_FB31   ((uint32_t)0x80000000)
 
#define CAN_F0R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F0R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F0R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F0R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F0R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F0R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F0R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F0R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F0R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F0R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F0R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F0R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F0R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F0R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F0R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F0R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F0R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F0R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F0R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F0R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F0R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F0R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F0R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F0R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F0R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F0R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F0R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F0R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F0R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F0R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F0R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F0R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F1R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F1R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F1R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F1R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F1R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F1R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F1R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F1R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F1R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F1R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F1R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F1R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F1R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F1R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F1R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F1R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F1R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F1R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F1R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F1R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F1R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F1R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F1R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F1R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F1R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F1R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F1R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F1R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F1R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F1R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F1R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F1R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F2R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F2R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F2R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F2R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F2R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F2R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F2R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F2R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F2R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F2R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F2R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F2R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F2R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F2R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F2R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F2R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F2R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F2R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F2R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F2R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F2R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F2R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F2R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F2R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F2R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F2R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F2R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F2R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F2R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F2R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F2R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F2R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F3R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F3R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F3R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F3R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F3R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F3R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F3R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F3R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F3R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F3R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F3R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F3R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F3R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F3R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F3R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F3R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F3R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F3R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F3R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F3R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F3R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F3R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F3R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F3R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F3R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F3R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F3R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F3R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F3R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F3R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F3R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F3R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F4R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F4R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F4R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F4R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F4R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F4R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F4R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F4R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F4R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F4R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F4R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F4R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F4R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F4R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F4R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F4R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F4R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F4R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F4R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F4R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F4R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F4R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F4R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F4R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F4R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F4R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F4R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F4R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F4R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F4R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F4R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F4R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F5R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F5R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F5R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F5R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F5R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F5R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F5R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F5R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F5R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F5R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F5R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F5R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F5R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F5R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F5R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F5R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F5R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F5R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F5R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F5R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F5R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F5R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F5R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F5R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F5R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F5R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F5R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F5R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F5R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F5R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F5R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F5R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F6R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F6R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F6R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F6R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F6R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F6R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F6R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F6R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F6R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F6R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F6R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F6R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F6R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F6R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F6R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F6R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F6R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F6R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F6R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F6R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F6R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F6R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F6R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F6R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F6R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F6R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F6R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F6R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F6R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F6R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F6R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F6R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F7R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F7R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F7R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F7R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F7R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F7R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F7R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F7R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F7R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F7R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F7R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F7R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F7R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F7R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F7R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F7R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F7R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F7R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F7R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F7R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F7R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F7R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F7R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F7R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F7R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F7R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F7R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F7R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F7R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F7R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F7R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F7R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F8R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F8R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F8R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F8R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F8R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F8R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F8R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F8R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F8R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F8R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F8R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F8R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F8R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F8R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F8R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F8R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F8R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F8R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F8R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F8R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F8R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F8R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F8R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F8R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F8R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F8R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F8R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F8R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F8R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F8R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F8R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F8R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F9R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F9R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F9R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F9R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F9R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F9R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F9R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F9R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F9R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F9R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F9R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F9R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F9R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F9R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F9R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F9R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F9R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F9R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F9R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F9R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F9R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F9R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F9R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F9R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F9R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F9R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F9R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F9R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F9R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F9R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F9R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F9R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F10R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F10R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F10R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F10R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F10R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F10R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F10R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F10R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F10R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F10R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F10R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F10R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F10R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F10R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F10R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F10R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F10R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F10R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F10R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F10R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F10R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F10R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F10R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F10R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F10R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F10R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F10R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F10R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F10R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F10R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F10R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F10R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F11R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F11R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F11R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F11R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F11R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F11R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F11R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F11R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F11R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F11R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F11R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F11R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F11R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F11R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F11R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F11R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F11R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F11R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F11R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F11R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F11R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F11R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F11R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F11R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F11R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F11R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F11R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F11R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F11R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F11R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F11R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F11R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F12R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F12R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F12R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F12R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F12R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F12R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F12R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F12R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F12R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F12R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F12R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F12R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F12R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F12R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F12R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F12R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F12R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F12R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F12R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F12R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F12R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F12R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F12R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F12R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F12R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F12R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F12R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F12R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F12R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F12R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F12R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F12R2_FB31   ((uint32_t)0x80000000)
 
#define CAN_F13R2_FB0   ((uint32_t)0x00000001)
 
#define CAN_F13R2_FB1   ((uint32_t)0x00000002)
 
#define CAN_F13R2_FB2   ((uint32_t)0x00000004)
 
#define CAN_F13R2_FB3   ((uint32_t)0x00000008)
 
#define CAN_F13R2_FB4   ((uint32_t)0x00000010)
 
#define CAN_F13R2_FB5   ((uint32_t)0x00000020)
 
#define CAN_F13R2_FB6   ((uint32_t)0x00000040)
 
#define CAN_F13R2_FB7   ((uint32_t)0x00000080)
 
#define CAN_F13R2_FB8   ((uint32_t)0x00000100)
 
#define CAN_F13R2_FB9   ((uint32_t)0x00000200)
 
#define CAN_F13R2_FB10   ((uint32_t)0x00000400)
 
#define CAN_F13R2_FB11   ((uint32_t)0x00000800)
 
#define CAN_F13R2_FB12   ((uint32_t)0x00001000)
 
#define CAN_F13R2_FB13   ((uint32_t)0x00002000)
 
#define CAN_F13R2_FB14   ((uint32_t)0x00004000)
 
#define CAN_F13R2_FB15   ((uint32_t)0x00008000)
 
#define CAN_F13R2_FB16   ((uint32_t)0x00010000)
 
#define CAN_F13R2_FB17   ((uint32_t)0x00020000)
 
#define CAN_F13R2_FB18   ((uint32_t)0x00040000)
 
#define CAN_F13R2_FB19   ((uint32_t)0x00080000)
 
#define CAN_F13R2_FB20   ((uint32_t)0x00100000)
 
#define CAN_F13R2_FB21   ((uint32_t)0x00200000)
 
#define CAN_F13R2_FB22   ((uint32_t)0x00400000)
 
#define CAN_F13R2_FB23   ((uint32_t)0x00800000)
 
#define CAN_F13R2_FB24   ((uint32_t)0x01000000)
 
#define CAN_F13R2_FB25   ((uint32_t)0x02000000)
 
#define CAN_F13R2_FB26   ((uint32_t)0x04000000)
 
#define CAN_F13R2_FB27   ((uint32_t)0x08000000)
 
#define CAN_F13R2_FB28   ((uint32_t)0x10000000)
 
#define CAN_F13R2_FB29   ((uint32_t)0x20000000)
 
#define CAN_F13R2_FB30   ((uint32_t)0x40000000)
 
#define CAN_F13R2_FB31   ((uint32_t)0x80000000)
 
#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
 
#define CRC_IDR_IDR   ((uint8_t)0xFF)
 
#define CRC_CR_RESET   ((uint8_t)0x01)
 
+#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)
 
+#define CRYP_CR_ALGOMODE   ((uint32_t)0x00080038)
 
+#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)
 
+#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)
 
+#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)
 
+#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)
 
+#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)
 
+#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)
 
+#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)
 
+#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)
 
+#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)
 
+#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)
 
+#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)
 
+#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)
 
+#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)
 
+#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)
 
+#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)
 
+#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)
 
+#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)
 
+#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)
 
+#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)
 
+#define CRYP_CR_GCM_CCMPH   ((uint32_t)0x00030000)
 
+#define CRYP_CR_GCM_CCMPH_0   ((uint32_t)0x00010000)
 
+#define CRYP_CR_GCM_CCMPH_1   ((uint32_t)0x00020000)
 
+#define CRYP_CR_ALGOMODE_3   ((uint32_t)0x00080000)
 
+#define CRYP_SR_IFEM   ((uint32_t)0x00000001)
 
+#define CRYP_SR_IFNF   ((uint32_t)0x00000002)
 
+#define CRYP_SR_OFNE   ((uint32_t)0x00000004)
 
+#define CRYP_SR_OFFU   ((uint32_t)0x00000008)
 
+#define CRYP_SR_BUSY   ((uint32_t)0x00000010)
 
+#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)
 
+#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)
 
+#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)
 
+#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)
 
+#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)
 
+#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)
 
+#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)
 
+#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)
 
#define DAC_CR_EN1   ((uint32_t)0x00000001)
 
#define DAC_CR_BOFF1   ((uint32_t)0x00000002)
 
#define DAC_CR_TEN1   ((uint32_t)0x00000004)
 
#define DAC_CR_TSEL1   ((uint32_t)0x00000038)
 
#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
 
#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
 
#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
 
#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)
 
#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
 
#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
 
#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)
 
#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
 
#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
 
#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
 
#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
 
#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)
 
#define DAC_CR_EN2   ((uint32_t)0x00010000)
 
#define DAC_CR_BOFF2   ((uint32_t)0x00020000)
 
#define DAC_CR_TEN2   ((uint32_t)0x00040000)
 
#define DAC_CR_TSEL2   ((uint32_t)0x00380000)
 
#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
 
#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
 
#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
 
#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)
 
#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
 
#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
 
#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)
 
#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
 
#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
 
#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
 
#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
 
#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)
 
#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
 
#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
 
#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
 
#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
 
#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
 
#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
 
#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
 
#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
 
#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
 
#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
 
#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
 
#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
 
#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
 
#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
 
#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
 
+#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)
 
+#define DCMI_CR_CM   ((uint32_t)0x00000002)
 
+#define DCMI_CR_CROP   ((uint32_t)0x00000004)
 
+#define DCMI_CR_JPEG   ((uint32_t)0x00000008)
 
+#define DCMI_CR_ESS   ((uint32_t)0x00000010)
 
+#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)
 
+#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)
 
+#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)
 
+#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)
 
+#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)
 
+#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)
 
+#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)
 
+#define DCMI_CR_CRE   ((uint32_t)0x00001000)
 
+#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)
 
+#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)
 
+#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)
 
+#define DCMI_SR_FNE   ((uint32_t)0x00000004)
 
+#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)
 
+#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)
 
+#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)
 
+#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)
 
+#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)
 
+#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)
 
+#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)
 
+#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)
 
+#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)
 
+#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)
 
+#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)
 
+#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)
 
+#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)
 
+#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)
 
+#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)
 
+#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)
 
+#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)
 
+#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)
 
+#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)
 
+#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)
 
+#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)
 
+#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)
 
+#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)
 
+#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)
 
+#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)
 
+#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)
 
+#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)
 
+#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)
 
+#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)
 
+#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)
 
+#define DMA_SxCR_ACK   ((uint32_t)0x00100000)
 
+#define DMA_SxCR_CT   ((uint32_t)0x00080000)
 
+#define DMA_SxCR_DBM   ((uint32_t)0x00040000)
 
+#define DMA_SxCR_PL   ((uint32_t)0x00030000)
 
+#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)
 
+#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)
 
+#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)
 
+#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)
 
+#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)
 
+#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)
 
+#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)
 
+#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)
 
+#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)
 
+#define DMA_SxCR_MINC   ((uint32_t)0x00000400)
 
+#define DMA_SxCR_PINC   ((uint32_t)0x00000200)
 
+#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)
 
+#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)
 
+#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)
 
+#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)
 
+#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)
 
+#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)
 
+#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)
 
+#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)
 
+#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)
 
+#define DMA_SxCR_EN   ((uint32_t)0x00000001)
 
+#define DMA_SxNDT   ((uint32_t)0x0000FFFF)
 
+#define DMA_SxNDT_0   ((uint32_t)0x00000001)
 
+#define DMA_SxNDT_1   ((uint32_t)0x00000002)
 
+#define DMA_SxNDT_2   ((uint32_t)0x00000004)
 
+#define DMA_SxNDT_3   ((uint32_t)0x00000008)
 
+#define DMA_SxNDT_4   ((uint32_t)0x00000010)
 
+#define DMA_SxNDT_5   ((uint32_t)0x00000020)
 
+#define DMA_SxNDT_6   ((uint32_t)0x00000040)
 
+#define DMA_SxNDT_7   ((uint32_t)0x00000080)
 
+#define DMA_SxNDT_8   ((uint32_t)0x00000100)
 
+#define DMA_SxNDT_9   ((uint32_t)0x00000200)
 
+#define DMA_SxNDT_10   ((uint32_t)0x00000400)
 
+#define DMA_SxNDT_11   ((uint32_t)0x00000800)
 
+#define DMA_SxNDT_12   ((uint32_t)0x00001000)
 
+#define DMA_SxNDT_13   ((uint32_t)0x00002000)
 
+#define DMA_SxNDT_14   ((uint32_t)0x00004000)
 
+#define DMA_SxNDT_15   ((uint32_t)0x00008000)
 
+#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)
 
+#define DMA_SxFCR_FS   ((uint32_t)0x00000038)
 
+#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)
 
+#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)
 
+#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)
 
+#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)
 
+#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)
 
+#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)
 
+#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)
 
+#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)
 
+#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)
 
+#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)
 
+#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)
 
+#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)
 
+#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)
 
+#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)
 
+#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)
 
+#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)
 
+#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)
 
+#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)
 
+#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)
 
+#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)
 
+#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)
 
+#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)
 
+#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)
 
+#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)
 
+#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)
 
+#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)
 
+#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)
 
+#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)
 
+#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)
 
+#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)
 
+#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)
 
+#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)
 
+#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)
 
+#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)
 
+#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)
 
+#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)
 
+#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)
 
+#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)
 
+#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)
 
+#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)
 
+#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)
 
+#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)
 
+#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)
 
+#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)
 
+#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)
 
+#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)
 
+#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)
 
+#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)
 
+#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)
 
+#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)
 
+#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)
 
+#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)
 
+#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)
 
+#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)
 
+#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)
 
+#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)
 
+#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)
 
+#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)
 
+#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)
 
+#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)
 
+#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)
 
+#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)
 
+#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)
 
+#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)
 
+#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)
 
+#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)
 
+#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)
 
+#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)
 
+#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)
 
+#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)
 
+#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)
 
+#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)
 
+#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)
 
+#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)
 
+#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)
 
+#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)
 
+#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)
 
+#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)
 
+#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)
 
+#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)
 
+#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)
 
+#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)
 
+#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)
 
+#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)
 
+#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)
 
+#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)
 
+#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)
 
#define DMA2D_CR_START   ((uint32_t)0x00000001)
 
#define DMA2D_CR_SUSP   ((uint32_t)0x00000002)
 
#define DMA2D_CR_ABORT   ((uint32_t)0x00000004)
 
#define DMA2D_CR_TEIE   ((uint32_t)0x00000100)
 
#define DMA2D_CR_TCIE   ((uint32_t)0x00000200)
 
#define DMA2D_CR_TWIE   ((uint32_t)0x00000400)
 
#define DMA2D_CR_CAEIE   ((uint32_t)0x00000800)
 
#define DMA2D_CR_CTCIE   ((uint32_t)0x00001000)
 
#define DMA2D_CR_CEIE   ((uint32_t)0x00002000)
 
#define DMA2D_CR_MODE   ((uint32_t)0x00030000)
 
#define DMA2D_ISR_TEIF   ((uint32_t)0x00000001)
 
#define DMA2D_ISR_TCIF   ((uint32_t)0x00000002)
 
#define DMA2D_ISR_TWIF   ((uint32_t)0x00000004)
 
#define DMA2D_ISR_CAEIF   ((uint32_t)0x00000008)
 
#define DMA2D_ISR_CTCIF   ((uint32_t)0x00000010)
 
#define DMA2D_ISR_CEIF   ((uint32_t)0x00000020)
 
#define DMA2D_IFSR_CTEIF   ((uint32_t)0x00000001)
 
#define DMA2D_IFSR_CTCIF   ((uint32_t)0x00000002)
 
#define DMA2D_IFSR_CTWIF   ((uint32_t)0x00000004)
 
#define DMA2D_IFSR_CCAEIF   ((uint32_t)0x00000008)
 
#define DMA2D_IFSR_CCTCIF   ((uint32_t)0x00000010)
 
#define DMA2D_IFSR_CCEIF   ((uint32_t)0x00000020)
 
#define DMA2D_FGMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_FGOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_BGMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_BGOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_FGPFCCR_CM   ((uint32_t)0x0000000F)
 
#define DMA2D_FGPFCCR_CCM   ((uint32_t)0x00000010)
 
#define DMA2D_FGPFCCR_START   ((uint32_t)0x00000020)
 
#define DMA2D_FGPFCCR_CS   ((uint32_t)0x0000FF00)
 
#define DMA2D_FGPFCCR_AM   ((uint32_t)0x00030000)
 
#define DMA2D_FGPFCCR_ALPHA   ((uint32_t)0xFF000000)
 
#define DMA2D_FGCOLR_BLUE   ((uint32_t)0x000000FF)
 
#define DMA2D_FGCOLR_GREEN   ((uint32_t)0x0000FF00)
 
#define DMA2D_FGCOLR_RED   ((uint32_t)0x00FF0000)
 
#define DMA2D_BGPFCCR_CM   ((uint32_t)0x0000000F)
 
#define DMA2D_BGPFCCR_CCM   ((uint32_t)0x00000010)
 
#define DMA2D_BGPFCCR_START   ((uint32_t)0x00000020)
 
#define DMA2D_BGPFCCR_CS   ((uint32_t)0x0000FF00)
 
#define DMA2D_BGPFCCR_AM   ((uint32_t)0x00030000)
 
#define DMA2D_BGPFCCR_ALPHA   ((uint32_t)0xFF000000)
 
#define DMA2D_BGCOLR_BLUE   ((uint32_t)0x000000FF)
 
#define DMA2D_BGCOLR_GREEN   ((uint32_t)0x0000FF00)
 
#define DMA2D_BGCOLR_RED   ((uint32_t)0x00FF0000)
 
#define DMA2D_FGCMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_BGCMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_OPFCCR_CM   ((uint32_t)0x00000007)
 
#define DMA2D_OCOLR_BLUE_1   ((uint32_t)0x000000FF)
 
#define DMA2D_OCOLR_GREEN_1   ((uint32_t)0x0000FF00)
 
#define DMA2D_OCOLR_RED_1   ((uint32_t)0x00FF0000)
 
#define DMA2D_OCOLR_ALPHA_1   ((uint32_t)0xFF000000)
 
#define DMA2D_OCOLR_BLUE_2   ((uint32_t)0x0000001F)
 
#define DMA2D_OCOLR_GREEN_2   ((uint32_t)0x000007E0)
 
#define DMA2D_OCOLR_RED_2   ((uint32_t)0x0000F800)
 
#define DMA2D_OCOLR_BLUE_3   ((uint32_t)0x0000001F)
 
#define DMA2D_OCOLR_GREEN_3   ((uint32_t)0x000003E0)
 
#define DMA2D_OCOLR_RED_3   ((uint32_t)0x00007C00)
 
#define DMA2D_OCOLR_ALPHA_3   ((uint32_t)0x00008000)
 
#define DMA2D_OCOLR_BLUE_4   ((uint32_t)0x0000000F)
 
#define DMA2D_OCOLR_GREEN_4   ((uint32_t)0x000000F0)
 
#define DMA2D_OCOLR_RED_4   ((uint32_t)0x00000F00)
 
#define DMA2D_OCOLR_ALPHA_4   ((uint32_t)0x0000F000)
 
#define DMA2D_OMAR_MA   ((uint32_t)0xFFFFFFFF)
 
#define DMA2D_OOR_LO   ((uint32_t)0x00003FFF)
 
#define DMA2D_NLR_NL   ((uint32_t)0x0000FFFF)
 
#define DMA2D_NLR_PL   ((uint32_t)0x3FFF0000)
 
#define DMA2D_LWR_LW   ((uint32_t)0x0000FFFF)
 
#define DMA2D_AMTCR_EN   ((uint32_t)0x00000001)
 
#define DMA2D_AMTCR_DT   ((uint32_t)0x0000FF00)
 
#define EXTI_IMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_IMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_IMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_IMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_IMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_IMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_IMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_IMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_IMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_IMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_IMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_IMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_IMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_IMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_IMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_IMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_IMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_IMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_IMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_IMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_EMR_MR0   ((uint32_t)0x00000001)
 
#define EXTI_EMR_MR1   ((uint32_t)0x00000002)
 
#define EXTI_EMR_MR2   ((uint32_t)0x00000004)
 
#define EXTI_EMR_MR3   ((uint32_t)0x00000008)
 
#define EXTI_EMR_MR4   ((uint32_t)0x00000010)
 
#define EXTI_EMR_MR5   ((uint32_t)0x00000020)
 
#define EXTI_EMR_MR6   ((uint32_t)0x00000040)
 
#define EXTI_EMR_MR7   ((uint32_t)0x00000080)
 
#define EXTI_EMR_MR8   ((uint32_t)0x00000100)
 
#define EXTI_EMR_MR9   ((uint32_t)0x00000200)
 
#define EXTI_EMR_MR10   ((uint32_t)0x00000400)
 
#define EXTI_EMR_MR11   ((uint32_t)0x00000800)
 
#define EXTI_EMR_MR12   ((uint32_t)0x00001000)
 
#define EXTI_EMR_MR13   ((uint32_t)0x00002000)
 
#define EXTI_EMR_MR14   ((uint32_t)0x00004000)
 
#define EXTI_EMR_MR15   ((uint32_t)0x00008000)
 
#define EXTI_EMR_MR16   ((uint32_t)0x00010000)
 
#define EXTI_EMR_MR17   ((uint32_t)0x00020000)
 
#define EXTI_EMR_MR18   ((uint32_t)0x00040000)
 
#define EXTI_EMR_MR19   ((uint32_t)0x00080000)
 
#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)
 
#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)
 
#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)
 
#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)
 
#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)
 
#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)
 
#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)
 
#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)
 
#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)
 
#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)
 
#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)
 
#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)
 
#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)
 
#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)
 
#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)
 
#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)
 
#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)
 
#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)
 
#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)
 
#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)
 
#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
 
#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
 
#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
 
#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
 
#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
 
#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
 
#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
 
#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
 
#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
 
#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
 
#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
 
#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
 
#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
 
#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
 
#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
 
#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
 
#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
 
#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
 
#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
 
#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
 
#define EXTI_PR_PR0   ((uint32_t)0x00000001)
 
#define EXTI_PR_PR1   ((uint32_t)0x00000002)
 
#define EXTI_PR_PR2   ((uint32_t)0x00000004)
 
#define EXTI_PR_PR3   ((uint32_t)0x00000008)
 
#define EXTI_PR_PR4   ((uint32_t)0x00000010)
 
#define EXTI_PR_PR5   ((uint32_t)0x00000020)
 
#define EXTI_PR_PR6   ((uint32_t)0x00000040)
 
#define EXTI_PR_PR7   ((uint32_t)0x00000080)
 
#define EXTI_PR_PR8   ((uint32_t)0x00000100)
 
#define EXTI_PR_PR9   ((uint32_t)0x00000200)
 
#define EXTI_PR_PR10   ((uint32_t)0x00000400)
 
#define EXTI_PR_PR11   ((uint32_t)0x00000800)
 
#define EXTI_PR_PR12   ((uint32_t)0x00001000)
 
#define EXTI_PR_PR13   ((uint32_t)0x00002000)
 
#define EXTI_PR_PR14   ((uint32_t)0x00004000)
 
#define EXTI_PR_PR15   ((uint32_t)0x00008000)
 
#define EXTI_PR_PR16   ((uint32_t)0x00010000)
 
#define EXTI_PR_PR17   ((uint32_t)0x00020000)
 
#define EXTI_PR_PR18   ((uint32_t)0x00040000)
 
#define EXTI_PR_PR19   ((uint32_t)0x00080000)
 
+#define FLASH_ACR_LATENCY   ((uint32_t)0x0000000F)
 
+#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)
 
+#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)
 
+#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)
 
+#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)
 
+#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)
 
+#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)
 
+#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)
 
+#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)
 
+#define FLASH_ACR_LATENCY_8WS   ((uint32_t)0x00000008)
 
+#define FLASH_ACR_LATENCY_9WS   ((uint32_t)0x00000009)
 
+#define FLASH_ACR_LATENCY_10WS   ((uint32_t)0x0000000A)
 
+#define FLASH_ACR_LATENCY_11WS   ((uint32_t)0x0000000B)
 
+#define FLASH_ACR_LATENCY_12WS   ((uint32_t)0x0000000C)
 
+#define FLASH_ACR_LATENCY_13WS   ((uint32_t)0x0000000D)
 
+#define FLASH_ACR_LATENCY_14WS   ((uint32_t)0x0000000E)
 
+#define FLASH_ACR_LATENCY_15WS   ((uint32_t)0x0000000F)
 
+#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)
 
+#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)
 
+#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)
 
+#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)
 
+#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)
 
+#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
 
+#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)
 
+#define FLASH_SR_EOP   ((uint32_t)0x00000001)
 
+#define FLASH_SR_SOP   ((uint32_t)0x00000002)
 
+#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)
 
+#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)
 
+#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)
 
+#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)
 
+#define FLASH_SR_BSY   ((uint32_t)0x00010000)
 
+#define FLASH_CR_PG   ((uint32_t)0x00000001)
 
+#define FLASH_CR_SER   ((uint32_t)0x00000002)
 
+#define FLASH_CR_MER   ((uint32_t)0x00000004)
 
+#define FLASH_CR_MER1   FLASH_CR_MER
 
+#define FLASH_CR_SNB   ((uint32_t)0x000000F8)
 
+#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)
 
+#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)
 
+#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)
 
+#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)
 
+#define FLASH_CR_SNB_4   ((uint32_t)0x00000040)
 
+#define FLASH_CR_PSIZE   ((uint32_t)0x00000300)
 
+#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)
 
+#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)
 
+#define FLASH_CR_MER2   ((uint32_t)0x00008000)
 
+#define FLASH_CR_STRT   ((uint32_t)0x00010000)
 
+#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)
 
+#define FLASH_CR_LOCK   ((uint32_t)0x80000000)
 
+#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)
 
+#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)
 
+#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)
 
+#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)
 
+#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)
 
+#define FLASH_OPTCR_BFB2   ((uint32_t)0x00000010)
 
+#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)
 
+#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)
 
+#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)
 
+#define FLASH_OPTCR_RDP   ((uint32_t)0x0000FF00)
 
+#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)
 
+#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)
 
+#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)
 
+#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)
 
+#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)
 
+#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)
 
+#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)
 
+#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)
 
+#define FLASH_OPTCR_nWRP   ((uint32_t)0x0FFF0000)
 
+#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)
 
+#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)
 
+#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)
 
+#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)
 
+#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)
 
+#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)
 
+#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)
 
+#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)
 
+#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)
 
+#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)
 
+#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)
 
+#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)
 
+#define FLASH_OPTCR_DB1M   ((uint32_t)0x40000000)
 
+#define FLASH_OPTCR_SPRMOD   ((uint32_t)0x80000000)
 
+#define FLASH_OPTCR1_nWRP   ((uint32_t)0x0FFF0000)
 
+#define FLASH_OPTCR1_nWRP_0   ((uint32_t)0x00010000)
 
+#define FLASH_OPTCR1_nWRP_1   ((uint32_t)0x00020000)
 
+#define FLASH_OPTCR1_nWRP_2   ((uint32_t)0x00040000)
 
+#define FLASH_OPTCR1_nWRP_3   ((uint32_t)0x00080000)
 
+#define FLASH_OPTCR1_nWRP_4   ((uint32_t)0x00100000)
 
+#define FLASH_OPTCR1_nWRP_5   ((uint32_t)0x00200000)
 
+#define FLASH_OPTCR1_nWRP_6   ((uint32_t)0x00400000)
 
+#define FLASH_OPTCR1_nWRP_7   ((uint32_t)0x00800000)
 
+#define FLASH_OPTCR1_nWRP_8   ((uint32_t)0x01000000)
 
+#define FLASH_OPTCR1_nWRP_9   ((uint32_t)0x02000000)
 
+#define FLASH_OPTCR1_nWRP_10   ((uint32_t)0x04000000)
 
+#define FLASH_OPTCR1_nWRP_11   ((uint32_t)0x08000000)
 
#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
 
#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
 
#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
 
#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
 
#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
 
#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)
 
#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
 
#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
 
#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
 
#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
 
#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
 
#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
 
#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
 
#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)
 
#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
 
#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
 
#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
 
#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
 
#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
 
#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
 
#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
 
#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
 
#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
 
#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
 
#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
 
#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
 
#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
 
#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
 
#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
 
#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
 
#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
 
#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
 
#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
 
#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
 
#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
 
#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
 
#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
 
#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
 
#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
 
#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
 
#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
 
#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
 
#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
 
#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
 
#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
 
#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
 
#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
 
#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
 
#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
 
#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
 
#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
 
#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
 
#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
 
#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)
 
#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
 
#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
 
#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
 
#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
 
#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
 
#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
 
#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
 
#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
 
#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
 
#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
 
#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
 
#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
 
#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
 
#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
 
#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
 
#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
 
#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
 
#define FSMC_SR2_IRS   ((uint8_t)0x01)
 
#define FSMC_SR2_ILS   ((uint8_t)0x02)
 
#define FSMC_SR2_IFS   ((uint8_t)0x04)
 
#define FSMC_SR2_IREN   ((uint8_t)0x08)
 
#define FSMC_SR2_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR2_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR2_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR3_IRS   ((uint8_t)0x01)
 
#define FSMC_SR3_ILS   ((uint8_t)0x02)
 
#define FSMC_SR3_IFS   ((uint8_t)0x04)
 
#define FSMC_SR3_IREN   ((uint8_t)0x08)
 
#define FSMC_SR3_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR3_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR3_FEMPT   ((uint8_t)0x40)
 
#define FSMC_SR4_IRS   ((uint8_t)0x01)
 
#define FSMC_SR4_ILS   ((uint8_t)0x02)
 
#define FSMC_SR4_IFS   ((uint8_t)0x04)
 
#define FSMC_SR4_IREN   ((uint8_t)0x08)
 
#define FSMC_SR4_ILEN   ((uint8_t)0x10)
 
#define FSMC_SR4_IFEN   ((uint8_t)0x20)
 
#define FSMC_SR4_FEMPT   ((uint8_t)0x40)
 
#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
 
#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
 
#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
 
#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
 
#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
 
#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
 
#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
 
#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
 
#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
 
#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
 
#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
 
#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
 
#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
 
#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
 
#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
 
#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
 
#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
 
#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
 
#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
 
#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
 
#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
 
#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
 
#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
 
#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
 
#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
 
#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
 
#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
 
#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
 
#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
 
#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
 
#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
 
#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
 
#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
 
#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
 
#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
 
#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
 
#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
 
#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
 
#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
 
#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
 
#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
 
#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
 
#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
 
+#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)
 
+#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
 
+#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
 
+#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
 
+#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
 
+#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
 
+#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)
 
+#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
 
+#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
 
+#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
 
+#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
 
+#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
 
+#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)
 
+#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
 
+#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
 
+#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
 
+#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
 
+#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
 
+#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)
 
+#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
 
+#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
 
+#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
 
+#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
 
+#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
 
+#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)
 
+#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
 
+#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
 
+#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
 
+#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
 
+#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
 
+#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)
 
+#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
 
+#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
 
+#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
 
+#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
 
+#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
 
+#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)
 
+#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
 
+#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
 
+#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
 
+#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
 
+#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
 
+#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)
 
+#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
 
+#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
 
+#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
 
+#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
 
+#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
 
+#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
 
+#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
 
+#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
 
+#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
 
+#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
 
+#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
 
+#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
 
+#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
 
+#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
 
+#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
 
+#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
 
+#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
 
+#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
 
+#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
 
+#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
 
+#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
 
+#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
 
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
 
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
 
+#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
 
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
 
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
 
+#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
 
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
 
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
 
+#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
 
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
 
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
 
+#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
 
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
 
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
 
+#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
 
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
 
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
 
+#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
 
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
 
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
 
+#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
 
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
 
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
 
+#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
 
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
 
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
 
+#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
 
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
 
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
 
+#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
 
+#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
 
+#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
 
+#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
 
+#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
 
+#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
 
+#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
 
+#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
 
+#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
 
+#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
 
+#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
 
+#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
 
+#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
 
+#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
 
+#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
 
+#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
 
+#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
 
+#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
 
+#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
 
+#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
 
+#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
 
+#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
 
+#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
 
+#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
 
+#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
 
+#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
 
+#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
 
+#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
 
+#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
 
+#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
 
+#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
 
+#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
 
+#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
 
+#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
 
+#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
 
+#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
 
+#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
 
+#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
 
+#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
 
+#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
 
+#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
 
+#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
 
+#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
 
+#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
 
+#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
 
+#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
 
+#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
 
+#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
 
+#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
 
+#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
 
+#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
 
+#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
 
+#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
 
+#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
 
+#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
 
+#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
 
+#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
 
+#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
 
+#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
 
+#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
 
+#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)
 
+#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)
 
+#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)
 
+#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)
 
+#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)
 
+#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)
 
+#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)
 
+#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)
 
+#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)
 
+#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)
 
+#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)
 
+#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)
 
+#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)
 
+#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)
 
+#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)
 
+#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)
 
+#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0
 
+#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1
 
+#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2
 
+#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3
 
+#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4
 
+#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5
 
+#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6
 
+#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7
 
+#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8
 
+#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9
 
+#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10
 
+#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11
 
+#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12
 
+#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13
 
+#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14
 
+#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15
 
+#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)
 
+#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)
 
+#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)
 
+#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)
 
+#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)
 
+#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)
 
+#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)
 
+#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)
 
+#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)
 
+#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)
 
+#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)
 
+#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)
 
+#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)
 
+#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)
 
+#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)
 
+#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)
 
+#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0
 
+#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1
 
+#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2
 
+#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3
 
+#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4
 
+#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5
 
+#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6
 
+#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7
 
+#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8
 
+#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9
 
+#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10
 
+#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11
 
+#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12
 
+#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13
 
+#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14
 
+#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15
 
+#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
 
+#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
 
+#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
 
+#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
 
+#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
 
+#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
 
+#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
 
+#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
 
+#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
 
+#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
 
+#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
 
+#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
 
+#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
 
+#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
 
+#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
 
+#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
 
+#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
 
+#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
 
+#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
 
+#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
 
+#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
 
+#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
 
+#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
 
+#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
 
+#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
 
+#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
 
+#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
 
+#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
 
+#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
 
+#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
 
+#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
 
+#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
 
+#define HASH_CR_INIT   ((uint32_t)0x00000004)
 
+#define HASH_CR_DMAE   ((uint32_t)0x00000008)
 
+#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)
 
+#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)
 
+#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)
 
+#define HASH_CR_MODE   ((uint32_t)0x00000040)
 
+#define HASH_CR_ALGO   ((uint32_t)0x00040080)
 
+#define HASH_CR_ALGO_0   ((uint32_t)0x00000080)
 
+#define HASH_CR_ALGO_1   ((uint32_t)0x00040000)
 
+#define HASH_CR_NBW   ((uint32_t)0x00000F00)
 
+#define HASH_CR_NBW_0   ((uint32_t)0x00000100)
 
+#define HASH_CR_NBW_1   ((uint32_t)0x00000200)
 
+#define HASH_CR_NBW_2   ((uint32_t)0x00000400)
 
+#define HASH_CR_NBW_3   ((uint32_t)0x00000800)
 
+#define HASH_CR_DINNE   ((uint32_t)0x00001000)
 
+#define HASH_CR_MDMAT   ((uint32_t)0x00002000)
 
+#define HASH_CR_LKEY   ((uint32_t)0x00010000)
 
+#define HASH_STR_NBW   ((uint32_t)0x0000001F)
 
+#define HASH_STR_NBW_0   ((uint32_t)0x00000001)
 
+#define HASH_STR_NBW_1   ((uint32_t)0x00000002)
 
+#define HASH_STR_NBW_2   ((uint32_t)0x00000004)
 
+#define HASH_STR_NBW_3   ((uint32_t)0x00000008)
 
+#define HASH_STR_NBW_4   ((uint32_t)0x00000010)
 
+#define HASH_STR_DCAL   ((uint32_t)0x00000100)
 
+#define HASH_IMR_DINIM   ((uint32_t)0x00000001)
 
+#define HASH_IMR_DCIM   ((uint32_t)0x00000002)
 
+#define HASH_SR_DINIS   ((uint32_t)0x00000001)
 
+#define HASH_SR_DCIS   ((uint32_t)0x00000002)
 
+#define HASH_SR_DMAS   ((uint32_t)0x00000004)
 
+#define HASH_SR_BUSY   ((uint32_t)0x00000008)
 
#define I2C_CR1_PE   ((uint16_t)0x0001)
 
#define I2C_CR1_SMBUS   ((uint16_t)0x0002)
 
#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
 
#define I2C_CR1_ENARP   ((uint16_t)0x0010)
 
#define I2C_CR1_ENPEC   ((uint16_t)0x0020)
 
#define I2C_CR1_ENGC   ((uint16_t)0x0040)
 
#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
 
#define I2C_CR1_START   ((uint16_t)0x0100)
 
#define I2C_CR1_STOP   ((uint16_t)0x0200)
 
#define I2C_CR1_ACK   ((uint16_t)0x0400)
 
#define I2C_CR1_POS   ((uint16_t)0x0800)
 
#define I2C_CR1_PEC   ((uint16_t)0x1000)
 
#define I2C_CR1_ALERT   ((uint16_t)0x2000)
 
#define I2C_CR1_SWRST   ((uint16_t)0x8000)
 
#define I2C_CR2_FREQ   ((uint16_t)0x003F)
 
#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)
 
#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)
 
#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)
 
#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)
 
#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)
 
#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)
 
#define I2C_CR2_ITERREN   ((uint16_t)0x0100)
 
#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
 
#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
 
#define I2C_CR2_DMAEN   ((uint16_t)0x0800)
 
#define I2C_CR2_LAST   ((uint16_t)0x1000)
 
#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
 
#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
 
#define I2C_OAR1_ADD0   ((uint16_t)0x0001)
 
#define I2C_OAR1_ADD1   ((uint16_t)0x0002)
 
#define I2C_OAR1_ADD2   ((uint16_t)0x0004)
 
#define I2C_OAR1_ADD3   ((uint16_t)0x0008)
 
#define I2C_OAR1_ADD4   ((uint16_t)0x0010)
 
#define I2C_OAR1_ADD5   ((uint16_t)0x0020)
 
#define I2C_OAR1_ADD6   ((uint16_t)0x0040)
 
#define I2C_OAR1_ADD7   ((uint16_t)0x0080)
 
#define I2C_OAR1_ADD8   ((uint16_t)0x0100)
 
#define I2C_OAR1_ADD9   ((uint16_t)0x0200)
 
#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
 
#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)
 
#define I2C_OAR2_ADD2   ((uint8_t)0xFE)
 
#define I2C_DR_DR   ((uint8_t)0xFF)
 
#define I2C_SR1_SB   ((uint16_t)0x0001)
 
#define I2C_SR1_ADDR   ((uint16_t)0x0002)
 
#define I2C_SR1_BTF   ((uint16_t)0x0004)
 
#define I2C_SR1_ADD10   ((uint16_t)0x0008)
 
#define I2C_SR1_STOPF   ((uint16_t)0x0010)
 
#define I2C_SR1_RXNE   ((uint16_t)0x0040)
 
#define I2C_SR1_TXE   ((uint16_t)0x0080)
 
#define I2C_SR1_BERR   ((uint16_t)0x0100)
 
#define I2C_SR1_ARLO   ((uint16_t)0x0200)
 
#define I2C_SR1_AF   ((uint16_t)0x0400)
 
#define I2C_SR1_OVR   ((uint16_t)0x0800)
 
#define I2C_SR1_PECERR   ((uint16_t)0x1000)
 
#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
 
#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)
 
#define I2C_SR2_MSL   ((uint16_t)0x0001)
 
#define I2C_SR2_BUSY   ((uint16_t)0x0002)
 
#define I2C_SR2_TRA   ((uint16_t)0x0004)
 
#define I2C_SR2_GENCALL   ((uint16_t)0x0010)
 
#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
 
#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)
 
#define I2C_SR2_DUALF   ((uint16_t)0x0080)
 
#define I2C_SR2_PEC   ((uint16_t)0xFF00)
 
#define I2C_CCR_CCR   ((uint16_t)0x0FFF)
 
#define I2C_CCR_DUTY   ((uint16_t)0x4000)
 
#define I2C_CCR_FS   ((uint16_t)0x8000)
 
#define I2C_TRISE_TRISE   ((uint8_t)0x3F)
 
#define I2C_FLTR_DNF   ((uint8_t)0x0F)
 
#define I2C_FLTR_ANOFF   ((uint8_t)0x10)
 
#define IWDG_KR_KEY   ((uint16_t)0xFFFF)
 
#define IWDG_PR_PR   ((uint8_t)0x07)
 
#define IWDG_PR_PR_0   ((uint8_t)0x01)
 
#define IWDG_PR_PR_1   ((uint8_t)0x02)
 
#define IWDG_PR_PR_2   ((uint8_t)0x04)
 
#define IWDG_RLR_RL   ((uint16_t)0x0FFF)
 
#define IWDG_SR_PVU   ((uint8_t)0x01)
 
#define IWDG_SR_RVU   ((uint8_t)0x02)
 
#define LTDC_SSCR_VSH   ((uint32_t)0x000007FF)
 
#define LTDC_SSCR_HSW   ((uint32_t)0x0FFF0000)
 
#define LTDC_BPCR_AVBP   ((uint32_t)0x000007FF)
 
#define LTDC_BPCR_AHBP   ((uint32_t)0x0FFF0000)
 
#define LTDC_AWCR_AAH   ((uint32_t)0x000007FF)
 
#define LTDC_AWCR_AAW   ((uint32_t)0x0FFF0000)
 
#define LTDC_TWCR_TOTALH   ((uint32_t)0x000007FF)
 
#define LTDC_TWCR_TOTALW   ((uint32_t)0x0FFF0000)
 
#define LTDC_GCR_LTDCEN   ((uint32_t)0x00000001)
 
#define LTDC_GCR_DBW   ((uint32_t)0x00000070)
 
#define LTDC_GCR_DGW   ((uint32_t)0x00000700)
 
#define LTDC_GCR_DRW   ((uint32_t)0x00007000)
 
#define LTDC_GCR_DTEN   ((uint32_t)0x00010000)
 
#define LTDC_GCR_PCPOL   ((uint32_t)0x10000000)
 
#define LTDC_GCR_DEPOL   ((uint32_t)0x20000000)
 
#define LTDC_GCR_VSPOL   ((uint32_t)0x40000000)
 
#define LTDC_GCR_HSPOL   ((uint32_t)0x80000000)
 
#define LTDC_SRCR_IMR   ((uint32_t)0x00000001)
 
#define LTDC_SRCR_VBR   ((uint32_t)0x00000002)
 
#define LTDC_BCCR_BCBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_BCCR_BCGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_BCCR_BCRED   ((uint32_t)0x00FF0000)
 
#define LTDC_IER_LIE   ((uint32_t)0x00000001)
 
#define LTDC_IER_FUIE   ((uint32_t)0x00000002)
 
#define LTDC_IER_TERRIE   ((uint32_t)0x00000004)
 
#define LTDC_IER_RRIE   ((uint32_t)0x00000008)
 
#define LTDC_ISR_LIF   ((uint32_t)0x00000001)
 
#define LTDC_ISR_FUIF   ((uint32_t)0x00000002)
 
#define LTDC_ISR_TERRIF   ((uint32_t)0x00000004)
 
#define LTDC_ISR_RRIF   ((uint32_t)0x00000008)
 
#define LTDC_ICR_CLIF   ((uint32_t)0x00000001)
 
#define LTDC_ICR_CFUIF   ((uint32_t)0x00000002)
 
#define LTDC_ICR_CTERRIF   ((uint32_t)0x00000004)
 
#define LTDC_ICR_CRRIF   ((uint32_t)0x00000008)
 
#define LTDC_LIPCR_LIPOS   ((uint32_t)0x000007FF)
 
#define LTDC_CPSR_CYPOS   ((uint32_t)0x0000FFFF)
 
#define LTDC_CPSR_CXPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_CDSR_VDES   ((uint32_t)0x00000001)
 
#define LTDC_CDSR_HDES   ((uint32_t)0x00000002)
 
#define LTDC_CDSR_VSYNCS   ((uint32_t)0x00000004)
 
#define LTDC_CDSR_HSYNCS   ((uint32_t)0x00000008)
 
#define LTDC_LxCR_LEN   ((uint32_t)0x00000001)
 
#define LTDC_LxCR_COLKEN   ((uint32_t)0x00000002)
 
#define LTDC_LxCR_CLUTEN   ((uint32_t)0x00000010)
 
#define LTDC_LxWHPCR_WHSTPOS   ((uint32_t)0x00000FFF)
 
#define LTDC_LxWHPCR_WHSPPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_LxWVPCR_WVSTPOS   ((uint32_t)0x00000FFF)
 
#define LTDC_LxWVPCR_WVSPPOS   ((uint32_t)0xFFFF0000)
 
#define LTDC_LxCKCR_CKBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxCKCR_CKGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxCKCR_CKRED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxPFCR_PF   ((uint32_t)0x00000007)
 
#define LTDC_LxCACR_CONSTA   ((uint32_t)0x000000FF)
 
#define LTDC_LxDCCR_DCBLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxDCCR_DCGREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxDCCR_DCRED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxDCCR_DCALPHA   ((uint32_t)0xFF000000)
 
#define LTDC_LxBFCR_BF2   ((uint32_t)0x00000007)
 
#define LTDC_LxBFCR_BF1   ((uint32_t)0x00000700)
 
#define LTDC_LxCFBAR_CFBADD   ((uint32_t)0xFFFFFFFF)
 
#define LTDC_LxCFBLR_CFBLL   ((uint32_t)0x00001FFF)
 
#define LTDC_LxCFBLR_CFBP   ((uint32_t)0x1FFF0000)
 
#define LTDC_LxCFBLNR_CFBLNBR   ((uint32_t)0x000007FF)
 
#define LTDC_LxCLUTWR_BLUE   ((uint32_t)0x000000FF)
 
#define LTDC_LxCLUTWR_GREEN   ((uint32_t)0x0000FF00)
 
#define LTDC_LxCLUTWR_RED   ((uint32_t)0x00FF0000)
 
#define LTDC_LxCLUTWR_CLUTADD   ((uint32_t)0xFF000000)
 
#define PWR_CR_LPDS   ((uint32_t)0x00000001)
 
#define PWR_CR_PDDS   ((uint32_t)0x00000002)
 
#define PWR_CR_CWUF   ((uint32_t)0x00000004)
 
#define PWR_CR_CSBF   ((uint32_t)0x00000008)
 
#define PWR_CR_PVDE   ((uint32_t)0x00000010)
 
#define PWR_CR_PLS   ((uint32_t)0x000000E0)
 
#define PWR_CR_PLS_0   ((uint32_t)0x00000020)
 
#define PWR_CR_PLS_1   ((uint32_t)0x00000040)
 
#define PWR_CR_PLS_2   ((uint32_t)0x00000080)
 
#define PWR_CR_PLS_LEV0   ((uint32_t)0x00000000)
 
#define PWR_CR_PLS_LEV1   ((uint32_t)0x00000020)
 
#define PWR_CR_PLS_LEV2   ((uint32_t)0x00000040)
 
#define PWR_CR_PLS_LEV3   ((uint32_t)0x00000060)
 
#define PWR_CR_PLS_LEV4   ((uint32_t)0x00000080)
 
#define PWR_CR_PLS_LEV5   ((uint32_t)0x000000A0)
 
#define PWR_CR_PLS_LEV6   ((uint32_t)0x000000C0)
 
#define PWR_CR_PLS_LEV7   ((uint32_t)0x000000E0)
 
#define PWR_CR_DBP   ((uint32_t)0x00000100)
 
#define PWR_CR_FPDS   ((uint32_t)0x00000200)
 
#define PWR_CR_LPUDS   ((uint32_t)0x00000400)
 
#define PWR_CR_MRUDS   ((uint32_t)0x00000800)
 
#define PWR_CR_LPLVDS   ((uint32_t)0x00000400)
 
#define PWR_CR_MRLVDS   ((uint32_t)0x00000800)
 
#define PWR_CR_ADCDC1   ((uint32_t)0x00002000)
 
#define PWR_CR_VOS   ((uint32_t)0x0000C000)
 
#define PWR_CR_VOS_0   ((uint32_t)0x00004000)
 
#define PWR_CR_VOS_1   ((uint32_t)0x00008000)
 
#define PWR_CR_ODEN   ((uint32_t)0x00010000)
 
#define PWR_CR_ODSWEN   ((uint32_t)0x00020000)
 
#define PWR_CR_UDEN   ((uint32_t)0x000C0000)
 
#define PWR_CR_UDEN_0   ((uint32_t)0x00040000)
 
#define PWR_CR_UDEN_1   ((uint32_t)0x00080000)
 
#define PWR_CR_FMSSR   ((uint32_t)0x00100000)
 
#define PWR_CR_FISSR   ((uint32_t)0x00200000)
 
+#define PWR_CR_PMODE   PWR_CR_VOS
 
#define PWR_CSR_WUF   ((uint32_t)0x00000001)
 
#define PWR_CSR_SBF   ((uint32_t)0x00000002)
 
#define PWR_CSR_PVDO   ((uint32_t)0x00000004)
 
#define PWR_CSR_BRR   ((uint32_t)0x00000008)
 
#define PWR_CSR_EWUP   ((uint32_t)0x00000100)
 
#define PWR_CSR_BRE   ((uint32_t)0x00000200)
 
#define PWR_CSR_VOSRDY   ((uint32_t)0x00004000)
 
#define PWR_CSR_ODRDY   ((uint32_t)0x00010000)
 
#define PWR_CSR_ODSWRDY   ((uint32_t)0x00020000)
 
#define PWR_CSR_UDSWRDY   ((uint32_t)0x000C0000)
 
+#define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
 
+#define RCC_CR_HSION   ((uint32_t)0x00000001)
 
+#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)
 
+#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
 
#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)
 
#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)
 
#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)
 
#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)
 
#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)
 
+#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
 
#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100)
 
#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200)
 
#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400)
 
#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800)
 
#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000)
 
#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000)
 
#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000)
 
#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000)
 
+#define RCC_CR_HSEON   ((uint32_t)0x00010000)
 
+#define RCC_CR_HSERDY   ((uint32_t)0x00020000)
 
+#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)
 
+#define RCC_CR_CSSON   ((uint32_t)0x00080000)
 
+#define RCC_CR_PLLON   ((uint32_t)0x01000000)
 
+#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)
 
+#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)
 
+#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)
 
+#define RCC_CR_PLLSAION   ((uint32_t)0x10000000)
 
+#define RCC_CR_PLLSAIRDY   ((uint32_t)0x20000000)
 
+#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)
 
+#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)
 
+#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)
 
+#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)
 
+#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)
 
+#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)
 
+#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)
 
+#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)
 
+#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)
 
+#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)
 
+#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)
 
+#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)
 
+#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)
 
+#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)
 
+#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)
 
+#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)
 
+#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)
 
+#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)
 
+#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)
 
+#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)
 
+#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)
 
+#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
 
+#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)
 
+#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)
 
+#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)
 
+#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)
 
#define RCC_CFGR_SW   ((uint32_t)0x00000003)
 
#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
 
#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
 
#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)
 
#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
 
#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
 
#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
 
#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
 
#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
 
#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
 
#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
 
#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
 
#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
 
#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
 
#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
 
#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
 
#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
 
#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
 
#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
 
#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
 
#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
 
#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
 
#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
 
#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
 
#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
 
#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
 
#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
 
#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
 
#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
 
#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
 
#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
 
#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
 
#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)
 
+#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)
 
+#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)
 
+#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)
 
+#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)
 
+#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)
 
#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
 
+#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)
 
+#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)
 
+#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)
 
+#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)
 
+#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)
 
+#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)
 
+#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)
 
+#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)
 
+#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)
 
+#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)
 
+#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)
 
+#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)
 
+#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)
 
+#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)
 
+#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)
 
+#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
 
+#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
 
+#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
 
+#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
 
+#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
 
+#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)
 
+#define RCC_CIR_PLLSAIRDYF   ((uint32_t)0x00000040)
 
+#define RCC_CIR_CSSF   ((uint32_t)0x00000080)
 
+#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
 
+#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
 
+#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
 
+#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
 
+#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
 
+#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)
 
+#define RCC_CIR_PLLSAIRDYIE   ((uint32_t)0x00004000)
 
+#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
 
+#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
 
+#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
 
+#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
 
+#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
 
+#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)
 
+#define RCC_CIR_PLLSAIRDYC   ((uint32_t)0x00400000)
 
+#define RCC_CIR_CSSC   ((uint32_t)0x00800000)
 
+#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)
 
+#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)
 
+#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)
 
+#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)
 
+#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)
 
+#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)
 
+#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)
 
+#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)
 
+#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)
 
+#define RCC_AHB1RSTR_GPIOJRST   ((uint32_t)0x00000200)
 
+#define RCC_AHB1RSTR_GPIOKRST   ((uint32_t)0x00000400)
 
+#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)
 
+#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)
 
+#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)
 
+#define RCC_AHB1RSTR_DMA2DRST   ((uint32_t)0x00800000)
 
+#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)
 
+#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)
 
+#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)
 
+#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)
 
+#define RCC_AHB2RSTR_HASHRST   ((uint32_t)0x00000020)
 
+#define RCC_AHB2RSTR_HSAHRST   RCC_AHB2RSTR_HASHRST
 
+#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)
 
+#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)
 
+#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)
 
+#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
 
+#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
 
+#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
 
+#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
 
+#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
 
+#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
 
+#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)
 
+#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)
 
+#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)
 
+#define RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)
 
+#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)
 
+#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00008000)
 
+#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
 
+#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
 
+#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
 
+#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
 
+#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
 
+#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
 
+#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)
 
+#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
 
+#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)
 
+#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
 
+#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
 
+#define RCC_APB1RSTR_UART7RST   ((uint32_t)0x40000000)
 
+#define RCC_APB1RSTR_UART8RST   ((uint32_t)0x80000000)
 
+#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)
 
+#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)
 
+#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)
 
+#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)
 
+#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)
 
+#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
 
+#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
 
+#define RCC_APB2RSTR_SPI4RST   ((uint32_t)0x00002000)
 
+#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)
 
+#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)
 
+#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)
 
+#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)
 
+#define RCC_APB2RSTR_SPI5RST   ((uint32_t)0x00100000)
 
+#define RCC_APB2RSTR_SPI6RST   ((uint32_t)0x00200000)
 
+#define RCC_APB2RSTR_SAI1RST   ((uint32_t)0x00400000)
 
+#define RCC_APB2RSTR_LTDCRST   ((uint32_t)0x04000000)
 
+#define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
 
+#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)
 
+#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)
 
+#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)
 
+#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)
 
+#define RCC_AHB1ENR_GPIOJEN   ((uint32_t)0x00000200)
 
+#define RCC_AHB1ENR_GPIOKEN   ((uint32_t)0x00000400)
 
+#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)
 
+#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)
 
+#define RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)
 
+#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)
 
+#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)
 
+#define RCC_AHB1ENR_DMA2DEN   ((uint32_t)0x00800000)
 
+#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)
 
+#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)
 
+#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)
 
+#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)
 
+#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)
 
+#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
 
+#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
 
+#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
 
+#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
 
+#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
 
+#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
 
+#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)
 
+#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)
 
+#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)
 
+#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
 
+#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
 
+#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
 
+#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
 
+#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
 
+#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
 
+#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
 
+#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
 
+#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
 
+#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)
 
+#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
 
+#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)
 
+#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
 
+#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
 
+#define RCC_APB1ENR_UART7EN   ((uint32_t)0x40000000)
 
+#define RCC_APB1ENR_UART8EN   ((uint32_t)0x80000000)
 
+#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)
 
+#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)
 
+#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)
 
+#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)
 
+#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)
 
+#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)
 
+#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)
 
+#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
 
+#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
 
+#define RCC_APB2ENR_SPI4EN   ((uint32_t)0x00002000)
 
+#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)
 
+#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)
 
+#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)
 
+#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)
 
+#define RCC_APB2ENR_SPI5EN   ((uint32_t)0x00100000)
 
+#define RCC_APB2ENR_SPI6EN   ((uint32_t)0x00200000)
 
+#define RCC_APB2ENR_SAI1EN   ((uint32_t)0x00400000)
 
+#define RCC_APB2ENR_LTDCEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)
 
+#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)
 
+#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)
 
+#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)
 
+#define RCC_AHB1LPENR_GPIOJLPEN   ((uint32_t)0x00000200)
 
+#define RCC_AHB1LPENR_GPIOKLPEN   ((uint32_t)0x00000400)
 
+#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)
 
+#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)
 
+#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)
 
+#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)
 
+#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)
 
+#define RCC_AHB1LPENR_SRAM3LPEN   ((uint32_t)0x00080000)
 
+#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)
 
+#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)
 
+#define RCC_AHB1LPENR_DMA2DLPEN   ((uint32_t)0x00800000)
 
+#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)
 
+#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)
 
+#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)
 
+#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)
 
+#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)
 
+#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)
 
+#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)
 
+#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)
 
+#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)
 
+#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)
 
+#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)
 
+#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
 
+#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
 
+#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
 
+#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
 
+#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
 
+#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)
 
+#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)
 
+#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)
 
+#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
 
+#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
 
+#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
 
+#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
 
+#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
 
+#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
 
+#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
 
+#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
 
+#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
 
+#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)
 
+#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)
 
+#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)
 
+#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
 
+#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
 
+#define RCC_APB1LPENR_UART7LPEN   ((uint32_t)0x40000000)
 
+#define RCC_APB1LPENR_UART8LPEN   ((uint32_t)0x80000000)
 
+#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)
 
+#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)
 
+#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)
 
+#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)
 
+#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)
 
+#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)
 
+#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)
 
+#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
 
+#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
 
+#define RCC_APB2LPENR_SPI4LPEN   ((uint32_t)0x00002000)
 
+#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)
 
+#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)
 
+#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)
 
+#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)
 
+#define RCC_APB2LPENR_SPI5LPEN   ((uint32_t)0x00100000)
 
+#define RCC_APB2LPENR_SPI6LPEN   ((uint32_t)0x00200000)
 
+#define RCC_APB2LPENR_SAI1LPEN   ((uint32_t)0x00400000)
 
+#define RCC_APB2LPENR_LTDCLPEN   ((uint32_t)0x04000000)
 
+#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)
 
+#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
 
+#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
 
+#define RCC_BDCR_LSEMOD   ((uint32_t)0x00000008)
 
+#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
 
+#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
 
+#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
 
+#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
 
+#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)
 
+#define RCC_CSR_LSION   ((uint32_t)0x00000001)
 
+#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
 
+#define RCC_CSR_RMVF   ((uint32_t)0x01000000)
 
+#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)
 
+#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)
 
+#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
 
+#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
 
+#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)
 
+#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
 
+#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
 
+#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)
 
+#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)
 
+#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)
 
+#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)
 
+#define RCC_PLLI2SCFGR_PLLI2SM   ((uint32_t)0x0000003F)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_0   ((uint32_t)0x00000001)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_1   ((uint32_t)0x00000002)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_2   ((uint32_t)0x00000004)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_3   ((uint32_t)0x00000008)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_4   ((uint32_t)0x00000010)
 
+#define RCC_PLLI2SCFGR_PLLI2SM_5   ((uint32_t)0x00000020)
 
+#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLI2SCFGR_PLLI2SQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)
 
+#define RCC_PLLSAICFGR_PLLI2SN   ((uint32_t)0x00007FC0)
 
+#define RCC_PLLSAICFGR_PLLI2SQ   ((uint32_t)0x0F000000)
 
+#define RCC_PLLSAICFGR_PLLI2SR   ((uint32_t)0x70000000)
 
+#define RCC_DCKCFGR_PLLI2SDIVQ   ((uint32_t)0x0000001F)
 
+#define RCC_DCKCFGR_PLLSAIDIVQ   ((uint32_t)0x00001F00)
 
+#define RCC_DCKCFGR_PLLSAIDIVR   ((uint32_t)0x00030000)
 
+#define RCC_DCKCFGR_SAI1ASRC   ((uint32_t)0x00300000)
 
+#define RCC_DCKCFGR_SAI1BSRC   ((uint32_t)0x00C00000)
 
+#define RCC_DCKCFGR_TIMPRE   ((uint32_t)0x01000000)
 
+#define RNG_CR_RNGEN   ((uint32_t)0x00000004)
 
+#define RNG_CR_IE   ((uint32_t)0x00000008)
 
+#define RNG_SR_DRDY   ((uint32_t)0x00000001)
 
+#define RNG_SR_CECS   ((uint32_t)0x00000002)
 
+#define RNG_SR_SECS   ((uint32_t)0x00000004)
 
+#define RNG_SR_CEIS   ((uint32_t)0x00000020)
 
+#define RNG_SR_SEIS   ((uint32_t)0x00000040)
 
+#define RTC_TR_PM   ((uint32_t)0x00400000)
 
+#define RTC_TR_HT   ((uint32_t)0x00300000)
 
+#define RTC_TR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_TR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_TR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_TR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_TR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_TR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_TR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_TR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_TR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_TR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_TR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_TR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_TR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_TR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_TR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_TR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_TR_ST   ((uint32_t)0x00000070)
 
+#define RTC_TR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_TR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_TR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_TR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_TR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_TR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_TR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_TR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_DR_YT   ((uint32_t)0x00F00000)
 
+#define RTC_DR_YT_0   ((uint32_t)0x00100000)
 
+#define RTC_DR_YT_1   ((uint32_t)0x00200000)
 
+#define RTC_DR_YT_2   ((uint32_t)0x00400000)
 
+#define RTC_DR_YT_3   ((uint32_t)0x00800000)
 
+#define RTC_DR_YU   ((uint32_t)0x000F0000)
 
+#define RTC_DR_YU_0   ((uint32_t)0x00010000)
 
+#define RTC_DR_YU_1   ((uint32_t)0x00020000)
 
+#define RTC_DR_YU_2   ((uint32_t)0x00040000)
 
+#define RTC_DR_YU_3   ((uint32_t)0x00080000)
 
+#define RTC_DR_WDU   ((uint32_t)0x0000E000)
 
+#define RTC_DR_WDU_0   ((uint32_t)0x00002000)
 
+#define RTC_DR_WDU_1   ((uint32_t)0x00004000)
 
+#define RTC_DR_WDU_2   ((uint32_t)0x00008000)
 
+#define RTC_DR_MT   ((uint32_t)0x00001000)
 
+#define RTC_DR_MU   ((uint32_t)0x00000F00)
 
+#define RTC_DR_MU_0   ((uint32_t)0x00000100)
 
+#define RTC_DR_MU_1   ((uint32_t)0x00000200)
 
+#define RTC_DR_MU_2   ((uint32_t)0x00000400)
 
+#define RTC_DR_MU_3   ((uint32_t)0x00000800)
 
+#define RTC_DR_DT   ((uint32_t)0x00000030)
 
+#define RTC_DR_DT_0   ((uint32_t)0x00000010)
 
+#define RTC_DR_DT_1   ((uint32_t)0x00000020)
 
+#define RTC_DR_DU   ((uint32_t)0x0000000F)
 
+#define RTC_DR_DU_0   ((uint32_t)0x00000001)
 
+#define RTC_DR_DU_1   ((uint32_t)0x00000002)
 
+#define RTC_DR_DU_2   ((uint32_t)0x00000004)
 
+#define RTC_DR_DU_3   ((uint32_t)0x00000008)
 
+#define RTC_CR_COE   ((uint32_t)0x00800000)
 
+#define RTC_CR_OSEL   ((uint32_t)0x00600000)
 
+#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)
 
+#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)
 
+#define RTC_CR_POL   ((uint32_t)0x00100000)
 
+#define RTC_CR_COSEL   ((uint32_t)0x00080000)
 
+#define RTC_CR_BCK   ((uint32_t)0x00040000)
 
+#define RTC_CR_SUB1H   ((uint32_t)0x00020000)
 
+#define RTC_CR_ADD1H   ((uint32_t)0x00010000)
 
+#define RTC_CR_TSIE   ((uint32_t)0x00008000)
 
+#define RTC_CR_WUTIE   ((uint32_t)0x00004000)
 
+#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)
 
+#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)
 
+#define RTC_CR_TSE   ((uint32_t)0x00000800)
 
+#define RTC_CR_WUTE   ((uint32_t)0x00000400)
 
+#define RTC_CR_ALRBE   ((uint32_t)0x00000200)
 
+#define RTC_CR_ALRAE   ((uint32_t)0x00000100)
 
+#define RTC_CR_DCE   ((uint32_t)0x00000080)
 
+#define RTC_CR_FMT   ((uint32_t)0x00000040)
 
+#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)
 
+#define RTC_CR_REFCKON   ((uint32_t)0x00000010)
 
+#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)
 
+#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
 
+#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
 
+#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
 
+#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
 
+#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)
 
+#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
 
+#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)
 
+#define RTC_ISR_TSF   ((uint32_t)0x00000800)
 
+#define RTC_ISR_WUTF   ((uint32_t)0x00000400)
 
+#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)
 
+#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)
 
+#define RTC_ISR_INIT   ((uint32_t)0x00000080)
 
+#define RTC_ISR_INITF   ((uint32_t)0x00000040)
 
+#define RTC_ISR_RSF   ((uint32_t)0x00000020)
 
+#define RTC_ISR_INITS   ((uint32_t)0x00000010)
 
+#define RTC_ISR_SHPF   ((uint32_t)0x00000008)
 
+#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)
 
+#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
 
+#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
 
+#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
 
+#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)
 
+#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
 
+#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)
 
+#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)
 
+#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
 
+#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
 
+#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)
 
+#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
 
+#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
 
+#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
 
+#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)
 
+#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)
 
+#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
 
+#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
 
+#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)
 
+#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
 
+#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
 
+#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)
 
+#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
 
+#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
 
+#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
 
+#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)
 
+#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)
 
+#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
 
+#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
 
+#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)
 
+#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_WPR_KEY   ((uint32_t)0x000000FF)
 
+#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)
 
+#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)
 
+#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)
 
+#define RTC_TSTR_PM   ((uint32_t)0x00400000)
 
+#define RTC_TSTR_HT   ((uint32_t)0x00300000)
 
+#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)
 
+#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)
 
+#define RTC_TSTR_HU   ((uint32_t)0x000F0000)
 
+#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)
 
+#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)
 
+#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)
 
+#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)
 
+#define RTC_TSTR_MNT   ((uint32_t)0x00007000)
 
+#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
 
+#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
 
+#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
 
+#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)
 
+#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
 
+#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
 
+#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
 
+#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
 
+#define RTC_TSTR_ST   ((uint32_t)0x00000070)
 
+#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)
 
+#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)
 
+#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)
 
+#define RTC_TSTR_SU   ((uint32_t)0x0000000F)
 
+#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)
 
+#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)
 
+#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)
 
+#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)
 
+#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)
 
+#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
 
+#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
 
+#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
 
+#define RTC_TSDR_MT   ((uint32_t)0x00001000)
 
+#define RTC_TSDR_MU   ((uint32_t)0x00000F00)
 
+#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)
 
+#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)
 
+#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)
 
+#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)
 
+#define RTC_TSDR_DT   ((uint32_t)0x00000030)
 
+#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)
 
+#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)
 
+#define RTC_TSDR_DU   ((uint32_t)0x0000000F)
 
+#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)
 
+#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)
 
+#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)
 
+#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)
 
+#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)
 
+#define RTC_CALR_CALP   ((uint32_t)0x00008000)
 
+#define RTC_CALR_CALW8   ((uint32_t)0x00004000)
 
+#define RTC_CALR_CALW16   ((uint32_t)0x00002000)
 
+#define RTC_CALR_CALM   ((uint32_t)0x000001FF)
 
+#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)
 
+#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)
 
+#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)
 
+#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)
 
+#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)
 
+#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)
 
+#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)
 
+#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)
 
+#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)
 
+#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
 
+#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)
 
+#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)
 
+#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)
 
+#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)
 
+#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)
 
+#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)
 
+#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)
 
+#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)
 
+#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)
 
+#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)
 
+#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)
 
+#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)
 
+#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)
 
+#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)
 
+#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
 
+#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
 
+#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
 
+#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)
 
+#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)
 
+#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)
 
+#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)
 
+#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)
 
+#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)
 
+#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)
 
+#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
 
#define SAI_GCR_SYNCIN   ((uint32_t)0x00000003)
 
#define SAI_GCR_SYNCIN_0   ((uint32_t)0x00000001)
 
#define SAI_GCR_SYNCIN_1   ((uint32_t)0x00000002)
 
#define SAI_GCR_SYNCOUT   ((uint32_t)0x00000030)
 
#define SAI_GCR_SYNCOUT_0   ((uint32_t)0x00000010)
 
#define SAI_GCR_SYNCOUT_1   ((uint32_t)0x00000020)
 
#define SAI_xCR1_MODE   ((uint32_t)0x00000003)
 
#define SAI_xCR1_MODE_0   ((uint32_t)0x00000001)
 
#define SAI_xCR1_MODE_1   ((uint32_t)0x00000002)
 
#define SAI_xCR1_PRTCFG   ((uint32_t)0x0000000C)
 
#define SAI_xCR1_PRTCFG_0   ((uint32_t)0x00000004)
 
#define SAI_xCR1_PRTCFG_1   ((uint32_t)0x00000008)
 
#define SAI_xCR1_DS   ((uint32_t)0x000000E0)
 
#define SAI_xCR1_DS_0   ((uint32_t)0x00000020)
 
#define SAI_xCR1_DS_1   ((uint32_t)0x00000040)
 
#define SAI_xCR1_DS_2   ((uint32_t)0x00000080)
 
#define SAI_xCR1_LSBFIRST   ((uint32_t)0x00000100)
 
#define SAI_xCR1_CKSTR   ((uint32_t)0x00000200)
 
#define SAI_xCR1_SYNCEN   ((uint32_t)0x00000C00)
 
#define SAI_xCR1_SYNCEN_0   ((uint32_t)0x00000400)
 
#define SAI_xCR1_SYNCEN_1   ((uint32_t)0x00000800)
 
#define SAI_xCR1_MONO   ((uint32_t)0x00001000)
 
#define SAI_xCR1_OUTDRIV   ((uint32_t)0x00002000)
 
#define SAI_xCR1_SAIEN   ((uint32_t)0x00010000)
 
#define SAI_xCR1_DMAEN   ((uint32_t)0x00020000)
 
#define SAI_xCR1_NODIV   ((uint32_t)0x00080000)
 
#define SAI_xCR1_MCKDIV   ((uint32_t)0x00780000)
 
#define SAI_xCR1_MCKDIV_0   ((uint32_t)0x00080000)
 
#define SAI_xCR1_MCKDIV_1   ((uint32_t)0x00100000)
 
#define SAI_xCR1_MCKDIV_2   ((uint32_t)0x00200000)
 
#define SAI_xCR1_MCKDIV_3   ((uint32_t)0x00400000)
 
#define SAI_xCR2_FTH   ((uint32_t)0x00000003)
 
#define SAI_xCR2_FTH_0   ((uint32_t)0x00000001)
 
#define SAI_xCR2_FTH_1   ((uint32_t)0x00000002)
 
#define SAI_xCR2_FFLUSH   ((uint32_t)0x00000008)
 
#define SAI_xCR2_TRIS   ((uint32_t)0x00000010)
 
#define SAI_xCR2_MUTE   ((uint32_t)0x00000020)
 
#define SAI_xCR2_MUTEVAL   ((uint32_t)0x00000040)
 
#define SAI_xCR2_MUTECNT   ((uint32_t)0x00001F80)
 
#define SAI_xCR2_MUTECNT_0   ((uint32_t)0x00000080)
 
#define SAI_xCR2_MUTECNT_1   ((uint32_t)0x00000100)
 
#define SAI_xCR2_MUTECNT_2   ((uint32_t)0x00000200)
 
#define SAI_xCR2_MUTECNT_3   ((uint32_t)0x00000400)
 
#define SAI_xCR2_MUTECNT_4   ((uint32_t)0x00000800)
 
#define SAI_xCR2_MUTECNT_5   ((uint32_t)0x00001000)
 
#define SAI_xCR2_CPL   ((uint32_t)0x00080000)
 
#define SAI_xCR2_COMP   ((uint32_t)0x0000C000)
 
#define SAI_xCR2_COMP_0   ((uint32_t)0x00004000)
 
#define SAI_xCR2_COMP_1   ((uint32_t)0x00008000)
 
#define SAI_xFRCR_FRL   ((uint32_t)0x000000FF)
 
#define SAI_xFRCR_FRL_0   ((uint32_t)0x00000001)
 
#define SAI_xFRCR_FRL_1   ((uint32_t)0x00000002)
 
#define SAI_xFRCR_FRL_2   ((uint32_t)0x00000004)
 
#define SAI_xFRCR_FRL_3   ((uint32_t)0x00000008)
 
#define SAI_xFRCR_FRL_4   ((uint32_t)0x00000010)
 
#define SAI_xFRCR_FRL_5   ((uint32_t)0x00000020)
 
#define SAI_xFRCR_FRL_6   ((uint32_t)0x00000040)
 
#define SAI_xFRCR_FRL_7   ((uint32_t)0x00000080)
 
#define SAI_xFRCR_FSALL   ((uint32_t)0x00007F00)
 
#define SAI_xFRCR_FSALL_0   ((uint32_t)0x00000100)
 
#define SAI_xFRCR_FSALL_1   ((uint32_t)0x00000200)
 
#define SAI_xFRCR_FSALL_2   ((uint32_t)0x00000400)
 
#define SAI_xFRCR_FSALL_3   ((uint32_t)0x00000800)
 
#define SAI_xFRCR_FSALL_4   ((uint32_t)0x00001000)
 
#define SAI_xFRCR_FSALL_5   ((uint32_t)0x00002000)
 
#define SAI_xFRCR_FSALL_6   ((uint32_t)0x00004000)
 
#define SAI_xFRCR_FSDEF   ((uint32_t)0x00010000)
 
#define SAI_xFRCR_FSPO   ((uint32_t)0x00020000)
 
#define SAI_xFRCR_FSOFF   ((uint32_t)0x00040000)
 
#define SAI_xSLOTR_FBOFF   ((uint32_t)0x0000001F)
 
#define SAI_xSLOTR_FBOFF_0   ((uint32_t)0x00000001)
 
#define SAI_xSLOTR_FBOFF_1   ((uint32_t)0x00000002)
 
#define SAI_xSLOTR_FBOFF_2   ((uint32_t)0x00000004)
 
#define SAI_xSLOTR_FBOFF_3   ((uint32_t)0x00000008)
 
#define SAI_xSLOTR_FBOFF_4   ((uint32_t)0x00000010)
 
#define SAI_xSLOTR_SLOTSZ   ((uint32_t)0x000000C0)
 
#define SAI_xSLOTR_SLOTSZ_0   ((uint32_t)0x00000040)
 
#define SAI_xSLOTR_SLOTSZ_1   ((uint32_t)0x00000080)
 
#define SAI_xSLOTR_NBSLOT   ((uint32_t)0x00000F00)
 
#define SAI_xSLOTR_NBSLOT_0   ((uint32_t)0x00000100)
 
#define SAI_xSLOTR_NBSLOT_1   ((uint32_t)0x00000200)
 
#define SAI_xSLOTR_NBSLOT_2   ((uint32_t)0x00000400)
 
#define SAI_xSLOTR_NBSLOT_3   ((uint32_t)0x00000800)
 
#define SAI_xSLOTR_SLOTEN   ((uint32_t)0xFFFF0000)
 
#define SAI_xIMR_OVRUDRIE   ((uint32_t)0x00000001)
 
#define SAI_xIMR_MUTEDETIE   ((uint32_t)0x00000002)
 
#define SAI_xIMR_WCKCFGIE   ((uint32_t)0x00000004)
 
#define SAI_xIMR_FREQIE   ((uint32_t)0x00000008)
 
#define SAI_xIMR_CNRDYIE   ((uint32_t)0x00000010)
 
#define SAI_xIMR_AFSDETIE   ((uint32_t)0x00000020)
 
#define SAI_xIMR_LFSDETIE   ((uint32_t)0x00000040)
 
#define SAI_xSR_OVRUDR   ((uint32_t)0x00000001)
 
#define SAI_xSR_MUTEDET   ((uint32_t)0x00000002)
 
#define SAI_xSR_WCKCFG   ((uint32_t)0x00000004)
 
#define SAI_xSR_FREQ   ((uint32_t)0x00000008)
 
#define SAI_xSR_CNRDY   ((uint32_t)0x00000010)
 
#define SAI_xSR_AFSDET   ((uint32_t)0x00000020)
 
#define SAI_xSR_LFSDET   ((uint32_t)0x00000040)
 
#define SAI_xSR_FLVL   ((uint32_t)0x00070000)
 
#define SAI_xSR_FLVL_0   ((uint32_t)0x00010000)
 
#define SAI_xSR_FLVL_1   ((uint32_t)0x00020000)
 
#define SAI_xSR_FLVL_2   ((uint32_t)0x00030000)
 
#define SAI_xCLRFR_COVRUDR   ((uint32_t)0x00000001)
 
#define SAI_xCLRFR_CMUTEDET   ((uint32_t)0x00000002)
 
#define SAI_xCLRFR_CWCKCFG   ((uint32_t)0x00000004)
 
#define SAI_xCLRFR_CFREQ   ((uint32_t)0x00000008)
 
#define SAI_xCLRFR_CCNRDY   ((uint32_t)0x00000010)
 
#define SAI_xCLRFR_CAFSDET   ((uint32_t)0x00000020)
 
#define SAI_xCLRFR_CLFSDET   ((uint32_t)0x00000040)
 
+#define SAI_xDR_DATA   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
 
#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
 
#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
 
#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
 
#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
 
#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
 
#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
 
#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
 
#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
 
#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
 
#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
 
#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
 
#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
 
#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
 
#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
 
#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
 
#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)
 
#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
 
#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
 
#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
 
#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
 
#define SDIO_CMD_NIEN   ((uint16_t)0x2000)
 
#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
 
#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
 
#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
 
#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
 
#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
 
#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
 
#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
 
#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
 
#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
 
#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
 
#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
 
#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
 
#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
 
#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
 
#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
 
#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
 
#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
 
#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
 
#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
 
#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
 
#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
 
#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
 
#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
 
#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
 
#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)
 
#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
 
#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)
 
#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)
 
#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
 
#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)
 
#define SDIO_STA_TXACT   ((uint32_t)0x00001000)
 
#define SDIO_STA_RXACT   ((uint32_t)0x00002000)
 
#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
 
#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
 
#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
 
#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
 
#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
 
#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
 
#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
 
#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
 
#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
 
#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
 
#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
 
#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
 
#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
 
#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
 
#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
 
#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
 
#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
 
#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
 
#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
 
#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
 
#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
 
#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
 
#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
 
#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
 
#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
 
#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
 
#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
 
#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
 
#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
 
#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
 
#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
 
#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
 
#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
 
#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
 
#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
 
#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
 
#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
 
#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
 
#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
 
#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
 
#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
 
#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
 
#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
 
#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
 
#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
 
#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
 
#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
 
#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
 
#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
 
#define SPI_CR1_CPHA   ((uint16_t)0x0001)
 
#define SPI_CR1_CPOL   ((uint16_t)0x0002)
 
#define SPI_CR1_MSTR   ((uint16_t)0x0004)
 
#define SPI_CR1_BR   ((uint16_t)0x0038)
 
#define SPI_CR1_BR_0   ((uint16_t)0x0008)
 
#define SPI_CR1_BR_1   ((uint16_t)0x0010)
 
#define SPI_CR1_BR_2   ((uint16_t)0x0020)
 
#define SPI_CR1_SPE   ((uint16_t)0x0040)
 
#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
 
#define SPI_CR1_SSI   ((uint16_t)0x0100)
 
#define SPI_CR1_SSM   ((uint16_t)0x0200)
 
#define SPI_CR1_RXONLY   ((uint16_t)0x0400)
 
#define SPI_CR1_DFF   ((uint16_t)0x0800)
 
#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
 
#define SPI_CR1_CRCEN   ((uint16_t)0x2000)
 
#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)
 
#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
 
#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)
 
#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)
 
#define SPI_CR2_SSOE   ((uint8_t)0x04)
 
#define SPI_CR2_ERRIE   ((uint8_t)0x20)
 
#define SPI_CR2_RXNEIE   ((uint8_t)0x40)
 
#define SPI_CR2_TXEIE   ((uint8_t)0x80)
 
#define SPI_SR_RXNE   ((uint8_t)0x01)
 
#define SPI_SR_TXE   ((uint8_t)0x02)
 
#define SPI_SR_CHSIDE   ((uint8_t)0x04)
 
#define SPI_SR_UDR   ((uint8_t)0x08)
 
#define SPI_SR_CRCERR   ((uint8_t)0x10)
 
#define SPI_SR_MODF   ((uint8_t)0x20)
 
#define SPI_SR_OVR   ((uint8_t)0x40)
 
#define SPI_SR_BSY   ((uint8_t)0x80)
 
#define SPI_DR_DR   ((uint16_t)0xFFFF)
 
#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
 
#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
 
#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
 
#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
 
#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
 
#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
 
#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
 
#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
 
#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
 
#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
 
#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
 
#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
 
#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
 
#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
 
#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
 
#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
 
#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
 
#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
 
#define SPI_I2SPR_ODD   ((uint16_t)0x0100)
 
#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
 
#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000007)
 
#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
 
#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
 
#define SYSCFG_MEMRMP_MEM_MODE_2   ((uint32_t)0x00000004)
 
#define SYSCFG_MEMRMP_FB_MODE   ((uint32_t)0x00000100)
 
#define SYSCFG_MEMRMP_SWP_FMC   ((uint32_t)0x00000C00)
 
#define SYSCFG_MEMRMP_SWP_FMC_0   ((uint32_t)0x00000400)
 
#define SYSCFG_MEMRMP_SWP_FMC_1   ((uint32_t)0x00000800)
 
#define SYSCFG_PMC_ADCxDC2   ((uint32_t)0x00070000)
 
#define SYSCFG_PMC_ADC1DC2   ((uint32_t)0x00010000)
 
#define SYSCFG_PMC_ADC2DC2   ((uint32_t)0x00020000)
 
#define SYSCFG_PMC_ADC3DC2   ((uint32_t)0x00040000)
 
#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)
 
+#define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
 
#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
 EXTI0 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR1_EXTI0_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR1_EXTI0_PK   ((uint16_t)0x000A)
 
#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
 EXTI1 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR1_EXTI1_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR1_EXTI1_PK   ((uint16_t)0x00A0)
 
#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
 EXTI2 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR1_EXTI2_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR1_EXTI2_PK   ((uint16_t)0x0A00)
 
#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
 EXTI3 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR1_EXTI3_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR1_EXTI3_PK   ((uint16_t)0xA000)
 
#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
 EXTI4 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR2_EXTI4_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR2_EXTI4_PK   ((uint16_t)0x000A)
 
#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
 EXTI5 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR2_EXTI5_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR2_EXTI5_PK   ((uint16_t)0x00A0)
 
#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
 EXTI6 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR2_EXTI6_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR2_EXTI6_PK   ((uint16_t)0x0A00)
 
#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
 EXTI7 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR2_EXTI7_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR2_EXTI7_PK   ((uint16_t)0xA000)
 
#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
 EXTI8 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR3_EXTI8_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
 EXTI9 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
 
#define SYSCFG_EXTICR3_EXTI9_PJ   ((uint16_t)0x0090)
 
#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
 EXTI10 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR3_EXTI10_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
 EXTI11 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR3_EXTI11_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
 
#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
 
#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
 
#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
 
#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
 EXTI12 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
 
#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
 
#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
 
#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
 
#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
 
#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
 
#define SYSCFG_EXTICR4_EXTI12_PH   ((uint16_t)0x0007)
 
#define SYSCFG_EXTICR4_EXTI12_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR4_EXTI12_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
 EXTI13 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
 
#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
 
#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
 
#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
 
#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
 
#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
 
#define SYSCFG_EXTICR4_EXTI13_PH   ((uint16_t)0x0070)
 
#define SYSCFG_EXTICR4_EXTI13_PI   ((uint16_t)0x0008)
 
#define SYSCFG_EXTICR4_EXTI13_PJ   ((uint16_t)0x0009)
 
#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
 EXTI14 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
 
#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
 
#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
 
#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
 
#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
 
#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
 
#define SYSCFG_EXTICR4_EXTI14_PH   ((uint16_t)0x0700)
 
#define SYSCFG_EXTICR4_EXTI14_PI   ((uint16_t)0x0800)
 
#define SYSCFG_EXTICR4_EXTI14_PJ   ((uint16_t)0x0900)
 
#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
 EXTI15 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
 
#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
 
#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
 
#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
 
#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
 
#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
 
#define SYSCFG_EXTICR4_EXTI15_PH   ((uint16_t)0x7000)
 
#define SYSCFG_EXTICR4_EXTI15_PI   ((uint16_t)0x8000)
 
#define SYSCFG_EXTICR4_EXTI15_PJ   ((uint16_t)0x9000)
 
#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
 
#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
 
#define TIM_CR1_CEN   ((uint16_t)0x0001)
 
#define TIM_CR1_UDIS   ((uint16_t)0x0002)
 
#define TIM_CR1_URS   ((uint16_t)0x0004)
 
#define TIM_CR1_OPM   ((uint16_t)0x0008)
 
#define TIM_CR1_DIR   ((uint16_t)0x0010)
 
#define TIM_CR1_CMS   ((uint16_t)0x0060)
 
#define TIM_CR1_CMS_0   ((uint16_t)0x0020)
 
#define TIM_CR1_CMS_1   ((uint16_t)0x0040)
 
#define TIM_CR1_ARPE   ((uint16_t)0x0080)
 
#define TIM_CR1_CKD   ((uint16_t)0x0300)
 
#define TIM_CR1_CKD_0   ((uint16_t)0x0100)
 
#define TIM_CR1_CKD_1   ((uint16_t)0x0200)
 
#define TIM_CR2_CCPC   ((uint16_t)0x0001)
 
#define TIM_CR2_CCUS   ((uint16_t)0x0004)
 
#define TIM_CR2_CCDS   ((uint16_t)0x0008)
 
#define TIM_CR2_MMS   ((uint16_t)0x0070)
 
#define TIM_CR2_MMS_0   ((uint16_t)0x0010)
 
#define TIM_CR2_MMS_1   ((uint16_t)0x0020)
 
#define TIM_CR2_MMS_2   ((uint16_t)0x0040)
 
#define TIM_CR2_TI1S   ((uint16_t)0x0080)
 
#define TIM_CR2_OIS1   ((uint16_t)0x0100)
 
#define TIM_CR2_OIS1N   ((uint16_t)0x0200)
 
#define TIM_CR2_OIS2   ((uint16_t)0x0400)
 
#define TIM_CR2_OIS2N   ((uint16_t)0x0800)
 
#define TIM_CR2_OIS3   ((uint16_t)0x1000)
 
#define TIM_CR2_OIS3N   ((uint16_t)0x2000)
 
#define TIM_CR2_OIS4   ((uint16_t)0x4000)
 
#define TIM_SMCR_SMS   ((uint16_t)0x0007)
 
#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)
 
#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)
 
#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)
 
#define TIM_SMCR_TS   ((uint16_t)0x0070)
 
#define TIM_SMCR_TS_0   ((uint16_t)0x0010)
 
#define TIM_SMCR_TS_1   ((uint16_t)0x0020)
 
#define TIM_SMCR_TS_2   ((uint16_t)0x0040)
 
#define TIM_SMCR_MSM   ((uint16_t)0x0080)
 
#define TIM_SMCR_ETF   ((uint16_t)0x0F00)
 
#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)
 
#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)
 
#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)
 
#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)
 
#define TIM_SMCR_ETPS   ((uint16_t)0x3000)
 
#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
 
#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
 
#define TIM_SMCR_ECE   ((uint16_t)0x4000)
 
#define TIM_SMCR_ETP   ((uint16_t)0x8000)
 
#define TIM_DIER_UIE   ((uint16_t)0x0001)
 
#define TIM_DIER_CC1IE   ((uint16_t)0x0002)
 
#define TIM_DIER_CC2IE   ((uint16_t)0x0004)
 
#define TIM_DIER_CC3IE   ((uint16_t)0x0008)
 
#define TIM_DIER_CC4IE   ((uint16_t)0x0010)
 
#define TIM_DIER_COMIE   ((uint16_t)0x0020)
 
#define TIM_DIER_TIE   ((uint16_t)0x0040)
 
#define TIM_DIER_BIE   ((uint16_t)0x0080)
 
#define TIM_DIER_UDE   ((uint16_t)0x0100)
 
#define TIM_DIER_CC1DE   ((uint16_t)0x0200)
 
#define TIM_DIER_CC2DE   ((uint16_t)0x0400)
 
#define TIM_DIER_CC3DE   ((uint16_t)0x0800)
 
#define TIM_DIER_CC4DE   ((uint16_t)0x1000)
 
#define TIM_DIER_COMDE   ((uint16_t)0x2000)
 
#define TIM_DIER_TDE   ((uint16_t)0x4000)
 
#define TIM_SR_UIF   ((uint16_t)0x0001)
 
#define TIM_SR_CC1IF   ((uint16_t)0x0002)
 
#define TIM_SR_CC2IF   ((uint16_t)0x0004)
 
#define TIM_SR_CC3IF   ((uint16_t)0x0008)
 
#define TIM_SR_CC4IF   ((uint16_t)0x0010)
 
#define TIM_SR_COMIF   ((uint16_t)0x0020)
 
#define TIM_SR_TIF   ((uint16_t)0x0040)
 
#define TIM_SR_BIF   ((uint16_t)0x0080)
 
#define TIM_SR_CC1OF   ((uint16_t)0x0200)
 
#define TIM_SR_CC2OF   ((uint16_t)0x0400)
 
#define TIM_SR_CC3OF   ((uint16_t)0x0800)
 
#define TIM_SR_CC4OF   ((uint16_t)0x1000)
 
#define TIM_EGR_UG   ((uint8_t)0x01)
 
#define TIM_EGR_CC1G   ((uint8_t)0x02)
 
#define TIM_EGR_CC2G   ((uint8_t)0x04)
 
#define TIM_EGR_CC3G   ((uint8_t)0x08)
 
#define TIM_EGR_CC4G   ((uint8_t)0x10)
 
#define TIM_EGR_COMG   ((uint8_t)0x20)
 
#define TIM_EGR_TG   ((uint8_t)0x40)
 
#define TIM_EGR_BG   ((uint8_t)0x80)
 
#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)
 
#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
 
#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
 
#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)
 
#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
 
#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)
 
#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
 
#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
 
#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)
 
#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
 
#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
 
#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)
 
#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
 
#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)
 
#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
 
#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
 
#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
 
#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
 
#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)
 
#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
 
#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)
 
#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
 
#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
 
#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
 
#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
 
#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)
 
#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
 
#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
 
#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
 
#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
 
#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
 
#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
 
#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
 
#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
 
#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
 
#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
 
#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
 
#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
 
#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)
 
#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
 
#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
 
#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
 
#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
 
#define TIM_CCER_CC1E   ((uint16_t)0x0001)
 
#define TIM_CCER_CC1P   ((uint16_t)0x0002)
 
#define TIM_CCER_CC1NE   ((uint16_t)0x0004)
 
#define TIM_CCER_CC1NP   ((uint16_t)0x0008)
 
#define TIM_CCER_CC2E   ((uint16_t)0x0010)
 
#define TIM_CCER_CC2P   ((uint16_t)0x0020)
 
#define TIM_CCER_CC2NE   ((uint16_t)0x0040)
 
#define TIM_CCER_CC2NP   ((uint16_t)0x0080)
 
#define TIM_CCER_CC3E   ((uint16_t)0x0100)
 
#define TIM_CCER_CC3P   ((uint16_t)0x0200)
 
#define TIM_CCER_CC3NE   ((uint16_t)0x0400)
 
#define TIM_CCER_CC3NP   ((uint16_t)0x0800)
 
#define TIM_CCER_CC4E   ((uint16_t)0x1000)
 
#define TIM_CCER_CC4P   ((uint16_t)0x2000)
 
#define TIM_CCER_CC4NP   ((uint16_t)0x8000)
 
#define TIM_CNT_CNT   ((uint16_t)0xFFFF)
 
#define TIM_PSC_PSC   ((uint16_t)0xFFFF)
 
#define TIM_ARR_ARR   ((uint16_t)0xFFFF)
 
#define TIM_RCR_REP   ((uint8_t)0xFF)
 
#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
 
#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
 
#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
 
#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
 
#define TIM_BDTR_DTG   ((uint16_t)0x00FF)
 
#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)
 
#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)
 
#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)
 
#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)
 
#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)
 
#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)
 
#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)
 
#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)
 
#define TIM_BDTR_LOCK   ((uint16_t)0x0300)
 
#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
 
#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
 
#define TIM_BDTR_OSSI   ((uint16_t)0x0400)
 
#define TIM_BDTR_OSSR   ((uint16_t)0x0800)
 
#define TIM_BDTR_BKE   ((uint16_t)0x1000)
 
#define TIM_BDTR_BKP   ((uint16_t)0x2000)
 
#define TIM_BDTR_AOE   ((uint16_t)0x4000)
 
#define TIM_BDTR_MOE   ((uint16_t)0x8000)
 
#define TIM_DCR_DBA   ((uint16_t)0x001F)
 
#define TIM_DCR_DBA_0   ((uint16_t)0x0001)
 
#define TIM_DCR_DBA_1   ((uint16_t)0x0002)
 
#define TIM_DCR_DBA_2   ((uint16_t)0x0004)
 
#define TIM_DCR_DBA_3   ((uint16_t)0x0008)
 
#define TIM_DCR_DBA_4   ((uint16_t)0x0010)
 
#define TIM_DCR_DBL   ((uint16_t)0x1F00)
 
#define TIM_DCR_DBL_0   ((uint16_t)0x0100)
 
#define TIM_DCR_DBL_1   ((uint16_t)0x0200)
 
#define TIM_DCR_DBL_2   ((uint16_t)0x0400)
 
#define TIM_DCR_DBL_3   ((uint16_t)0x0800)
 
#define TIM_DCR_DBL_4   ((uint16_t)0x1000)
 
#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
 
#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
 
#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
 
#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
 
#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
 
#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
 
#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
 
#define USART_SR_PE   ((uint16_t)0x0001)
 
#define USART_SR_FE   ((uint16_t)0x0002)
 
#define USART_SR_NE   ((uint16_t)0x0004)
 
#define USART_SR_ORE   ((uint16_t)0x0008)
 
#define USART_SR_IDLE   ((uint16_t)0x0010)
 
#define USART_SR_RXNE   ((uint16_t)0x0020)
 
#define USART_SR_TC   ((uint16_t)0x0040)
 
#define USART_SR_TXE   ((uint16_t)0x0080)
 
#define USART_SR_LBD   ((uint16_t)0x0100)
 
#define USART_SR_CTS   ((uint16_t)0x0200)
 
#define USART_DR_DR   ((uint16_t)0x01FF)
 
#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
 
#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
 
#define USART_CR1_SBK   ((uint16_t)0x0001)
 
#define USART_CR1_RWU   ((uint16_t)0x0002)
 
#define USART_CR1_RE   ((uint16_t)0x0004)
 
#define USART_CR1_TE   ((uint16_t)0x0008)
 
#define USART_CR1_IDLEIE   ((uint16_t)0x0010)
 
#define USART_CR1_RXNEIE   ((uint16_t)0x0020)
 
#define USART_CR1_TCIE   ((uint16_t)0x0040)
 
#define USART_CR1_TXEIE   ((uint16_t)0x0080)
 
#define USART_CR1_PEIE   ((uint16_t)0x0100)
 
#define USART_CR1_PS   ((uint16_t)0x0200)
 
#define USART_CR1_PCE   ((uint16_t)0x0400)
 
#define USART_CR1_WAKE   ((uint16_t)0x0800)
 
#define USART_CR1_M   ((uint16_t)0x1000)
 
#define USART_CR1_UE   ((uint16_t)0x2000)
 
#define USART_CR1_OVER8   ((uint16_t)0x8000)
 
#define USART_CR2_ADD   ((uint16_t)0x000F)
 
#define USART_CR2_LBDL   ((uint16_t)0x0020)
 
#define USART_CR2_LBDIE   ((uint16_t)0x0040)
 
#define USART_CR2_LBCL   ((uint16_t)0x0100)
 
#define USART_CR2_CPHA   ((uint16_t)0x0200)
 
#define USART_CR2_CPOL   ((uint16_t)0x0400)
 
#define USART_CR2_CLKEN   ((uint16_t)0x0800)
 
#define USART_CR2_STOP   ((uint16_t)0x3000)
 
#define USART_CR2_STOP_0   ((uint16_t)0x1000)
 
#define USART_CR2_STOP_1   ((uint16_t)0x2000)
 
#define USART_CR2_LINEN   ((uint16_t)0x4000)
 
#define USART_CR3_EIE   ((uint16_t)0x0001)
 
#define USART_CR3_IREN   ((uint16_t)0x0002)
 
#define USART_CR3_IRLP   ((uint16_t)0x0004)
 
#define USART_CR3_HDSEL   ((uint16_t)0x0008)
 
#define USART_CR3_NACK   ((uint16_t)0x0010)
 
#define USART_CR3_SCEN   ((uint16_t)0x0020)
 
#define USART_CR3_DMAR   ((uint16_t)0x0040)
 
#define USART_CR3_DMAT   ((uint16_t)0x0080)
 
#define USART_CR3_RTSE   ((uint16_t)0x0100)
 
#define USART_CR3_CTSE   ((uint16_t)0x0200)
 
#define USART_CR3_CTSIE   ((uint16_t)0x0400)
 
#define USART_CR3_ONEBIT   ((uint16_t)0x0800)
 
#define USART_GTPR_PSC   ((uint16_t)0x00FF)
 
#define USART_GTPR_PSC_0   ((uint16_t)0x0001)
 
#define USART_GTPR_PSC_1   ((uint16_t)0x0002)
 
#define USART_GTPR_PSC_2   ((uint16_t)0x0004)
 
#define USART_GTPR_PSC_3   ((uint16_t)0x0008)
 
#define USART_GTPR_PSC_4   ((uint16_t)0x0010)
 
#define USART_GTPR_PSC_5   ((uint16_t)0x0020)
 
#define USART_GTPR_PSC_6   ((uint16_t)0x0040)
 
#define USART_GTPR_PSC_7   ((uint16_t)0x0080)
 
#define USART_GTPR_GT   ((uint16_t)0xFF00)
 
#define WWDG_CR_T   ((uint8_t)0x7F)
 
#define WWDG_CR_T0   ((uint8_t)0x01)
 
#define WWDG_CR_T1   ((uint8_t)0x02)
 
#define WWDG_CR_T2   ((uint8_t)0x04)
 
#define WWDG_CR_T3   ((uint8_t)0x08)
 
#define WWDG_CR_T4   ((uint8_t)0x10)
 
#define WWDG_CR_T5   ((uint8_t)0x20)
 
#define WWDG_CR_T6   ((uint8_t)0x40)
 
#define WWDG_CR_WDGA   ((uint8_t)0x80)
 
#define WWDG_CFR_W   ((uint16_t)0x007F)
 
#define WWDG_CFR_W0   ((uint16_t)0x0001)
 
#define WWDG_CFR_W1   ((uint16_t)0x0002)
 
#define WWDG_CFR_W2   ((uint16_t)0x0004)
 
#define WWDG_CFR_W3   ((uint16_t)0x0008)
 
#define WWDG_CFR_W4   ((uint16_t)0x0010)
 
#define WWDG_CFR_W5   ((uint16_t)0x0020)
 
#define WWDG_CFR_W6   ((uint16_t)0x0040)
 
#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)
 
#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
 
#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
 
#define WWDG_CFR_EWI   ((uint16_t)0x0200)
 
#define WWDG_SR_EWIF   ((uint8_t)0x01)
 
+#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
 
+#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
 
+#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
 
+#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
 
+#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
 
+#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
 
#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
 
#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
 
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
 
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
 
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)
 
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)
 
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)
 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
 
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)
 
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)
 
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
 
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)
 
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)
 
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)
 
+#define ETH_MACCR_WD   ((uint32_t)0x00800000) /* Watchdog disable */
 
+#define ETH_MACCR_JD   ((uint32_t)0x00400000) /* Jabber disable */
 
+#define ETH_MACCR_IFG   ((uint32_t)0x000E0000) /* Inter-frame gap */
 
+#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
 
+#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
 
+#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
 
+#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
 
+#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
 
+#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
 
+#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
 
+#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
 
+#define ETH_MACCR_CSD   ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
 
+#define ETH_MACCR_FES   ((uint32_t)0x00004000) /* Fast ethernet speed */
 
+#define ETH_MACCR_ROD   ((uint32_t)0x00002000) /* Receive own disable */
 
+#define ETH_MACCR_LM   ((uint32_t)0x00001000) /* loopback mode */
 
+#define ETH_MACCR_DM   ((uint32_t)0x00000800) /* Duplex mode */
 
+#define ETH_MACCR_IPCO   ((uint32_t)0x00000400) /* IP Checksum offload */
 
+#define ETH_MACCR_RD   ((uint32_t)0x00000200) /* Retry disable */
 
+#define ETH_MACCR_APCS   ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
 
#define ETH_MACCR_BL
 
+#define ETH_MACCR_BL_10   ((uint32_t)0x00000000) /* k = min (n, 10) */
 
+#define ETH_MACCR_BL_8   ((uint32_t)0x00000020) /* k = min (n, 8) */
 
+#define ETH_MACCR_BL_4   ((uint32_t)0x00000040) /* k = min (n, 4) */
 
+#define ETH_MACCR_BL_1   ((uint32_t)0x00000060) /* k = min (n, 1) */
 
+#define ETH_MACCR_DC   ((uint32_t)0x00000010) /* Defferal check */
 
+#define ETH_MACCR_TE   ((uint32_t)0x00000008) /* Transmitter enable */
 
+#define ETH_MACCR_RE   ((uint32_t)0x00000004) /* Receiver enable */
 
+#define ETH_MACFFR_RA   ((uint32_t)0x80000000) /* Receive all */
 
+#define ETH_MACFFR_HPF   ((uint32_t)0x00000400) /* Hash or perfect filter */
 
+#define ETH_MACFFR_SAF   ((uint32_t)0x00000200) /* Source address filter enable */
 
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100) /* SA inverse filtering */
 
+#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
 
+#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
 
+#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
 
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
 
+#define ETH_MACFFR_BFD   ((uint32_t)0x00000020) /* Broadcast frame disable */
 
+#define ETH_MACFFR_PAM   ((uint32_t)0x00000010) /* Pass all mutlicast */
 
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008) /* DA Inverse filtering */
 
+#define ETH_MACFFR_HM   ((uint32_t)0x00000004) /* Hash multicast */
 
+#define ETH_MACFFR_HU   ((uint32_t)0x00000002) /* Hash unicast */
 
+#define ETH_MACFFR_PM   ((uint32_t)0x00000001) /* Promiscuous mode */
 
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF) /* Hash table high */
 
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF) /* Hash table low */
 
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800) /* Physical layer address */
 
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0) /* MII register in the selected PHY */
 
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
 
+#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 
+#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 
+#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 
+#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 
+#define ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
 
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002) /* MII write */
 
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001) /* MII busy */
 
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
 
+#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000) /* Pause time */
 
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080) /* Zero-quanta pause disable */
 
+#define ETH_MACFCR_PLT   ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
 
+#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
 
+#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
 
+#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
 
+#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
 
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008) /* Unicast pause frame detect */
 
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004) /* Receive flow control enable */
 
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002) /* Transmit flow control enable */
 
+#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
 
+#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
 
+#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
 
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
 
+#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
 
+#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200) /* Global Unicast */
 
+#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040) /* Wake-Up Frame Received */
 
+#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020) /* Magic Packet Received */
 
+#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
 
+#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002) /* Magic Packet Enable */
 
+#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001) /* Power Down */
 
+#define ETH_MACSR_TSTS   ((uint32_t)0x00000200) /* Time stamp trigger status */
 
+#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040) /* MMC transmit status */
 
+#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020) /* MMC receive status */
 
+#define ETH_MACSR_MMCS   ((uint32_t)0x00000010) /* MMC status */
 
+#define ETH_MACSR_PMTS   ((uint32_t)0x00000008) /* PMT status */
 
+#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
 
+#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008) /* PMT interrupt mask */
 
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF) /* MAC address0 high */
 
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
 
+#define ETH_MACA1HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA1HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
 
+#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
 
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
 
+#define ETH_MACA2HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA2HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
+#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF) /* MAC address1 high */
 
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
 
+#define ETH_MACA3HR_AE   ((uint32_t)0x80000000) /* Address enable */
 
+#define ETH_MACA3HR_SA   ((uint32_t)0x40000000) /* Source address */
 
+#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000) /* Mask byte control */
 
+#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
 
+#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
 
+#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
 
+#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
 
+#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
 
+#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
 
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF) /* MAC address3 high */
 
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
 
+#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
 
+#define ETH_MMCCR_MCP   ((uint32_t)0x00000010) /* MMC counter preset */
 
+#define ETH_MMCCR_MCF   ((uint32_t)0x00000008) /* MMC Counter Freeze */
 
+#define ETH_MMCCR_ROR   ((uint32_t)0x00000004) /* Reset on Read */
 
+#define ETH_MMCCR_CSR   ((uint32_t)0x00000002) /* Counter Stop Rollover */
 
+#define ETH_MMCCR_CR   ((uint32_t)0x00000001) /* Counters Reset */
 
+#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
 
+#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
 
+#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
 
+#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
 
+#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
 
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
+#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
+#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
 
+#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
 
+#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
 
+#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
 
+#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000) /* Time stamp clock node type */
 
+#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
 
+#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
 
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
 
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
 
+#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
 
+#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
 
+#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
 
+#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
 
+#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020) /* Addend register update */
 
+#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
 
+#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008) /* Time stamp update */
 
+#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004) /* Time stamp initialize */
 
+#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
 
+#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001) /* Time stamp enable */
 
+#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF) /* System time Sub-second increment value */
 
+#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF) /* System Time second */
 
+#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000) /* System Time Positive or negative time */
 
+#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
 
+#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
 
+#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
 
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
 
+#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
 
+#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
 
+#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
 
+#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020) /* Time stamp target time reached */
 
+#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010) /* Time stamp seconds overflow */
 
+#define ETH_DMABMR_AAB   ((uint32_t)0x02000000) /* Address-Aligned beats */
 
+#define ETH_DMABMR_FPM   ((uint32_t)0x01000000) /* 4xPBL mode */
 
+#define ETH_DMABMR_USP   ((uint32_t)0x00800000) /* Use separate PBL */
 
+#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000) /* RxDMA PBL */
 
+#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
 
+#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
 
+#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
+#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
+#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
+#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
+#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
+#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
 
+#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
 
+#define ETH_DMABMR_FB   ((uint32_t)0x00010000) /* Fixed Burst */
 
+#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
 
+#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00) /* Programmable burst length */
 
+#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
 
+#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
 
+#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
+#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
+#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
+#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
+#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
+#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
 
+#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 
+#define ETH_DMABMR_EDE   ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
 
+#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C) /* Descriptor Skip Length */
 
+#define ETH_DMABMR_DA   ((uint32_t)0x00000002) /* DMA arbitration scheme */
 
+#define ETH_DMABMR_SR   ((uint32_t)0x00000001) /* Software reset */
 
+#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
 
+#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
 
+#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF) /* Start of receive list */
 
+#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
 
+#define ETH_DMASR_TSTS   ((uint32_t)0x20000000) /* Time-stamp trigger status */
 
+#define ETH_DMASR_PMTS   ((uint32_t)0x10000000) /* PMT status */
 
+#define ETH_DMASR_MMCS   ((uint32_t)0x08000000) /* MMC status */
 
+#define ETH_DMASR_EBS   ((uint32_t)0x03800000) /* Error bits status */
 
+#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
 
+#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
 
+#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
 
+#define ETH_DMASR_TPS   ((uint32_t)0x00700000) /* Transmit process state */
 
+#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
 
+#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
 
+#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000) /* Running - waiting for status */
 
+#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000) /* Running - reading the data from host memory */
 
+#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
 
+#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
 
+#define ETH_DMASR_RPS   ((uint32_t)0x000E0000) /* Receive process state */
 
+#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
 
+#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
 
+#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000) /* Running - waiting for packet */
 
+#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
 
+#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000) /* Running - closing descriptor */
 
+#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
 
+#define ETH_DMASR_NIS   ((uint32_t)0x00010000) /* Normal interrupt summary */
 
+#define ETH_DMASR_AIS   ((uint32_t)0x00008000) /* Abnormal interrupt summary */
 
+#define ETH_DMASR_ERS   ((uint32_t)0x00004000) /* Early receive status */
 
+#define ETH_DMASR_FBES   ((uint32_t)0x00002000) /* Fatal bus error status */
 
+#define ETH_DMASR_ETS   ((uint32_t)0x00000400) /* Early transmit status */
 
+#define ETH_DMASR_RWTS   ((uint32_t)0x00000200) /* Receive watchdog timeout status */
 
+#define ETH_DMASR_RPSS   ((uint32_t)0x00000100) /* Receive process stopped status */
 
+#define ETH_DMASR_RBUS   ((uint32_t)0x00000080) /* Receive buffer unavailable status */
 
+#define ETH_DMASR_RS   ((uint32_t)0x00000040) /* Receive status */
 
+#define ETH_DMASR_TUS   ((uint32_t)0x00000020) /* Transmit underflow status */
 
+#define ETH_DMASR_ROS   ((uint32_t)0x00000010) /* Receive overflow status */
 
+#define ETH_DMASR_TJTS   ((uint32_t)0x00000008) /* Transmit jabber timeout status */
 
+#define ETH_DMASR_TBUS   ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
 
+#define ETH_DMASR_TPSS   ((uint32_t)0x00000002) /* Transmit process stopped status */
 
+#define ETH_DMASR_TS   ((uint32_t)0x00000001) /* Transmit status */
 
+#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
 
+#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000) /* Receive store and forward */
 
+#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000) /* Disable flushing of received frames */
 
+#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000) /* Transmit store and forward */
 
+#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000) /* Flush transmit FIFO */
 
+#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000) /* Transmit threshold control */
 
+#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
 
+#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
 
+#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
 
+#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
 
+#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
 
+#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
 
+#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
 
+#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
 
+#define ETH_DMAOMR_ST   ((uint32_t)0x00002000) /* Start/stop transmission command */
 
+#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080) /* Forward error frames */
 
+#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040) /* Forward undersized good frames */
 
+#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018) /* receive threshold control */
 
+#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
 
+#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
 
+#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
 
+#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
 
+#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004) /* operate on second frame */
 
+#define ETH_DMAOMR_SR   ((uint32_t)0x00000002) /* Start/stop receive */
 
+#define ETH_DMAIER_NISE   ((uint32_t)0x00010000) /* Normal interrupt summary enable */
 
+#define ETH_DMAIER_AISE   ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
 
+#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000) /* Early receive interrupt enable */
 
+#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
 
+#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400) /* Early transmit interrupt enable */
 
+#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
 
+#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
 
+#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
 
+#define ETH_DMAIER_RIE   ((uint32_t)0x00000040) /* Receive interrupt enable */
 
+#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
 
+#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
 
+#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
 
+#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
 
+#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
 
+#define ETH_DMAIER_TIE   ((uint32_t)0x00000001) /* Transmit interrupt enable */
 
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
 
+#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
 
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
 
+#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
 
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
 
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
 
+#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
 
+#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
 
+#define SET_BIT(REG, BIT)   ((REG) |= (BIT))
 
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
 
+#define READ_BIT(REG, BIT)   ((REG) & (BIT))
 
+#define CLEAR_REG(REG)   ((REG) = (0x0))
 
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
 
+#define READ_REG(REG)   ((REG))
 
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)   WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

+typedef enum IRQn IRQn_Type
 STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section.
 
typedef int32_t s32
 
+typedef int16_t s16
 
+typedef int8_t s8
 
typedef const int32_t sc32
 
typedef const int16_t sc16
 
typedef const int8_t sc8
 
+typedef __IO int32_t vs32
 
+typedef __IO int16_t vs16
 
+typedef __IO int8_t vs8
 
typedef __I int32_t vsc32
 
typedef __I int16_t vsc16
 
typedef __I int8_t vsc8
 
+typedef uint32_t u32
 
+typedef uint16_t u16
 
+typedef uint8_t u8
 
typedef const uint32_t uc32
 
typedef const uint16_t uc16
 
typedef const uint8_t uc8
 
+typedef __IO uint32_t vu32
 
+typedef __IO uint16_t vu16
 
+typedef __IO uint8_t vu8
 
typedef __I uint32_t vuc32
 
typedef __I uint16_t vuc16
 
typedef __I uint8_t vuc8
 
+typedef enum FlagStatus ITStatus
 
+ + + + + + + + + + +

+Enumerations

enum  IRQn {
+  NonMaskableInt_IRQn = -14, +MemoryManagement_IRQn = -12, +BusFault_IRQn = -11, +UsageFault_IRQn = -10, +
+  SVCall_IRQn = -5, +DebugMonitor_IRQn = -4, +PendSV_IRQn = -2, +SysTick_IRQn = -1, +
+  WWDG_IRQn = 0, +PVD_IRQn = 1, +TAMP_STAMP_IRQn = 2, +RTC_WKUP_IRQn = 3, +
+  FLASH_IRQn = 4, +RCC_IRQn = 5, +EXTI0_IRQn = 6, +EXTI1_IRQn = 7, +
+  EXTI2_IRQn = 8, +EXTI3_IRQn = 9, +EXTI4_IRQn = 10, +DMA1_Stream0_IRQn = 11, +
+  DMA1_Stream1_IRQn = 12, +DMA1_Stream2_IRQn = 13, +DMA1_Stream3_IRQn = 14, +DMA1_Stream4_IRQn = 15, +
+  DMA1_Stream5_IRQn = 16, +DMA1_Stream6_IRQn = 17, +ADC_IRQn = 18, +CAN1_TX_IRQn = 19, +
+  CAN1_RX0_IRQn = 20, +CAN1_RX1_IRQn = 21, +CAN1_SCE_IRQn = 22, +EXTI9_5_IRQn = 23, +
+  TIM1_BRK_TIM9_IRQn = 24, +TIM1_UP_TIM10_IRQn = 25, +TIM1_TRG_COM_TIM11_IRQn = 26, +TIM1_CC_IRQn = 27, +
+  TIM2_IRQn = 28, +TIM3_IRQn = 29, +TIM4_IRQn = 30, +I2C1_EV_IRQn = 31, +
+  I2C1_ER_IRQn = 32, +I2C2_EV_IRQn = 33, +I2C2_ER_IRQn = 34, +SPI1_IRQn = 35, +
+  SPI2_IRQn = 36, +USART1_IRQn = 37, +USART2_IRQn = 38, +USART3_IRQn = 39, +
+  EXTI15_10_IRQn = 40, +RTC_Alarm_IRQn = 41, +OTG_FS_WKUP_IRQn = 42, +TIM8_BRK_TIM12_IRQn = 43, +
+  TIM8_UP_TIM13_IRQn = 44, +TIM8_TRG_COM_TIM14_IRQn = 45, +TIM8_CC_IRQn = 46, +DMA1_Stream7_IRQn = 47, +
+  FSMC_IRQn = 48, +SDIO_IRQn = 49, +TIM5_IRQn = 50, +SPI3_IRQn = 51, +
+  UART4_IRQn = 52, +UART5_IRQn = 53, +TIM6_DAC_IRQn = 54, +TIM7_IRQn = 55, +
+  DMA2_Stream0_IRQn = 56, +DMA2_Stream1_IRQn = 57, +DMA2_Stream2_IRQn = 58, +DMA2_Stream3_IRQn = 59, +
+  DMA2_Stream4_IRQn = 60, +ETH_IRQn = 61, +ETH_WKUP_IRQn = 62, +CAN2_TX_IRQn = 63, +
+  CAN2_RX0_IRQn = 64, +CAN2_RX1_IRQn = 65, +CAN2_SCE_IRQn = 66, +OTG_FS_IRQn = 67, +
+  DMA2_Stream5_IRQn = 68, +DMA2_Stream6_IRQn = 69, +DMA2_Stream7_IRQn = 70, +USART6_IRQn = 71, +
+  I2C3_EV_IRQn = 72, +I2C3_ER_IRQn = 73, +OTG_HS_EP1_OUT_IRQn = 74, +OTG_HS_EP1_IN_IRQn = 75, +
+  OTG_HS_WKUP_IRQn = 76, +OTG_HS_IRQn = 77, +DCMI_IRQn = 78, +CRYP_IRQn = 79, +
+  HASH_RNG_IRQn = 80, +FPU_IRQn = 81 +
+ }
 STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...
 
enum  FlagStatus { RESET = 0, +SET = !RESET + }
 
enum  FunctionalState { DISABLE = 0, +ENABLE = !DISABLE + }
 
enum  ErrorStatus { ERROR = 0, +SUCCESS = !ERROR + }
 
+

Detailed Description

+

CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F4xx devices.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 The file is the unique include file that the application programmer is using in the C source code, usually in main.c. This file contains:
    +
  • Configuration section that allows to select:
      +
    • The device used in the target application
      • +
    • To use or not the peripheral’s drivers in application code(i.e. code will be based on direct access to peripheral’s registers rather than drivers API), this option is controlled by "#define USE_STDPERIPH_DRIVER"
      • +
    • To change few application-specific parameters such as the HSE crystal frequency
      • +
    +
    • +
  • Data structures and the address mapping for all peripherals
    • +
  • Peripheral's registers declarations and bits definition
    • +
  • Macros to access peripheral’s registers hardware
    • +
+
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx_8h__dep__incl.map b/stm32f4xx_8h__dep__incl.map new file mode 100644 index 0000000..74394a0 --- /dev/null +++ b/stm32f4xx_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx_8h__dep__incl.md5 b/stm32f4xx_8h__dep__incl.md5 new file mode 100644 index 0000000..7700d75 --- /dev/null +++ b/stm32f4xx_8h__dep__incl.md5 @@ -0,0 +1 @@ +a0e391e12928c5bb13bef9c79d3316c8 \ No newline at end of file diff --git a/stm32f4xx_8h__dep__incl.png b/stm32f4xx_8h__dep__incl.png new file mode 100644 index 0000000..72add69 Binary files /dev/null and b/stm32f4xx_8h__dep__incl.png differ diff --git a/stm32f4xx_8h__incl.map b/stm32f4xx_8h__incl.map new file mode 100644 index 0000000..b145b5b --- /dev/null +++ b/stm32f4xx_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx_8h__incl.md5 b/stm32f4xx_8h__incl.md5 new file mode 100644 index 0000000..7eb16d2 --- /dev/null +++ b/stm32f4xx_8h__incl.md5 @@ -0,0 +1 @@ +24dd7d7da65726bcd70fe0939e4e44d9 \ No newline at end of file diff --git a/stm32f4xx_8h__incl.png b/stm32f4xx_8h__incl.png new file mode 100644 index 0000000..b4a8b0f Binary files /dev/null and b/stm32f4xx_8h__incl.png differ diff --git a/stm32f4xx_8h_source.html b/stm32f4xx_8h_source.html new file mode 100644 index 0000000..8011477 --- /dev/null +++ b/stm32f4xx_8h_source.html @@ -0,0 +1,8350 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx.h
+
+
+Go to the documentation of this file.
1 
+
53 #ifndef __STM32F4xx_H
+
54 #define __STM32F4xx_H
+
55 
+
56 #ifdef __cplusplus
+
57  extern "C" {
+
58 #endif /* __cplusplus */
+
59 
+
64 /* Uncomment the line below according to the target STM32 device used in your
+
65  application
+
66  */
+
67 
+
68 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
+
69  #define STM32F40_41xxx
+
73  /* #define STM32F427_437xx */
+
76  /* #define STM32F429_439xx */
+
81  /* #define STM32F401xx */
+
84  /* #define STM32F411xE */
+
85 #endif
+
86 
+
87 /* Old STM32F40XX definition, maintained for legacy purpose */
+
88 #ifdef STM32F40XX
+
89  #define STM32F40_41xxx
+
90 #endif /* STM32F40XX */
+
91 
+
92 /* Old STM32F427X definition, maintained for legacy purpose */
+
93 #ifdef STM32F427X
+
94  #define STM32F427_437xx
+
95 #endif /* STM32F427X */
+
96 
+
97 /* Tip: To avoid modifying this file each time you need to switch between these
+
98  devices, you can define the device in your toolchain compiler preprocessor.
+
99  */
+
100 
+
101 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
+
102  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+
103 #endif
+
104 
+
105 #if !defined (USE_STDPERIPH_DRIVER)
+
106 
+
111  #define USE_STDPERIPH_DRIVER
+
112 #endif /* USE_STDPERIPH_DRIVER */
+
113 
+
122 #if !defined (HSE_VALUE)
+
123  //#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+
124  #define HSE_VALUE ((uint32_t)8000000)
+
125 #endif /* HSE_VALUE */
+
126 
+
131 #if !defined (HSE_STARTUP_TIMEOUT)
+
132  #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000)
+
133 #endif /* HSE_STARTUP_TIMEOUT */
+
134 
+
135 #if !defined (HSI_VALUE)
+
136  #define HSI_VALUE ((uint32_t)16000000)
+
137 #endif /* HSI_VALUE */
+
138 
+
142 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01)
+
143 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04)
+
144 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00)
+
145 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00)
+
146 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
+
147  |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
+
148  |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
+
149  |(__STM32F4XX_STDPERIPH_VERSION_RC))
+
150 
+
162 #define __CM4_REV 0x0001
+
163 #define __MPU_PRESENT 1
+
164 #define __NVIC_PRIO_BITS 4
+
165 #define __Vendor_SysTickConfig 0
+
166 #define __FPU_PRESENT 1
+
172 typedef enum IRQn
+
173 {
+
174 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+
175  NonMaskableInt_IRQn = -14,
+
176  MemoryManagement_IRQn = -12,
+
177  BusFault_IRQn = -11,
+
178  UsageFault_IRQn = -10,
+
179  SVCall_IRQn = -5,
+
180  DebugMonitor_IRQn = -4,
+
181  PendSV_IRQn = -2,
+
182  SysTick_IRQn = -1,
+
183 /****** STM32 specific Interrupt Numbers **********************************************************************/
+
184  WWDG_IRQn = 0,
+
185  PVD_IRQn = 1,
+
186  TAMP_STAMP_IRQn = 2,
+
187  RTC_WKUP_IRQn = 3,
+
188  FLASH_IRQn = 4,
+
189  RCC_IRQn = 5,
+
190  EXTI0_IRQn = 6,
+
191  EXTI1_IRQn = 7,
+
192  EXTI2_IRQn = 8,
+
193  EXTI3_IRQn = 9,
+
194  EXTI4_IRQn = 10,
+
195  DMA1_Stream0_IRQn = 11,
+
196  DMA1_Stream1_IRQn = 12,
+
197  DMA1_Stream2_IRQn = 13,
+
198  DMA1_Stream3_IRQn = 14,
+
199  DMA1_Stream4_IRQn = 15,
+
200  DMA1_Stream5_IRQn = 16,
+
201  DMA1_Stream6_IRQn = 17,
+
202  ADC_IRQn = 18,
+
204 #if defined (STM32F40_41xxx)
+
205  CAN1_TX_IRQn = 19,
+
206  CAN1_RX0_IRQn = 20,
+
207  CAN1_RX1_IRQn = 21,
+
208  CAN1_SCE_IRQn = 22,
+
209  EXTI9_5_IRQn = 23,
+
210  TIM1_BRK_TIM9_IRQn = 24,
+
211  TIM1_UP_TIM10_IRQn = 25,
+
212  TIM1_TRG_COM_TIM11_IRQn = 26,
+
213  TIM1_CC_IRQn = 27,
+
214  TIM2_IRQn = 28,
+
215  TIM3_IRQn = 29,
+
216  TIM4_IRQn = 30,
+
217  I2C1_EV_IRQn = 31,
+
218  I2C1_ER_IRQn = 32,
+
219  I2C2_EV_IRQn = 33,
+
220  I2C2_ER_IRQn = 34,
+
221  SPI1_IRQn = 35,
+
222  SPI2_IRQn = 36,
+
223  USART1_IRQn = 37,
+
224  USART2_IRQn = 38,
+
225  USART3_IRQn = 39,
+
226  EXTI15_10_IRQn = 40,
+
227  RTC_Alarm_IRQn = 41,
+
228  OTG_FS_WKUP_IRQn = 42,
+
229  TIM8_BRK_TIM12_IRQn = 43,
+
230  TIM8_UP_TIM13_IRQn = 44,
+
231  TIM8_TRG_COM_TIM14_IRQn = 45,
+
232  TIM8_CC_IRQn = 46,
+
233  DMA1_Stream7_IRQn = 47,
+
234  FSMC_IRQn = 48,
+
235  SDIO_IRQn = 49,
+
236  TIM5_IRQn = 50,
+
237  SPI3_IRQn = 51,
+
238  UART4_IRQn = 52,
+
239  UART5_IRQn = 53,
+
240  TIM6_DAC_IRQn = 54,
+
241  TIM7_IRQn = 55,
+
242  DMA2_Stream0_IRQn = 56,
+
243  DMA2_Stream1_IRQn = 57,
+
244  DMA2_Stream2_IRQn = 58,
+
245  DMA2_Stream3_IRQn = 59,
+
246  DMA2_Stream4_IRQn = 60,
+
247  ETH_IRQn = 61,
+
248  ETH_WKUP_IRQn = 62,
+
249  CAN2_TX_IRQn = 63,
+
250  CAN2_RX0_IRQn = 64,
+
251  CAN2_RX1_IRQn = 65,
+
252  CAN2_SCE_IRQn = 66,
+
253  OTG_FS_IRQn = 67,
+
254  DMA2_Stream5_IRQn = 68,
+
255  DMA2_Stream6_IRQn = 69,
+
256  DMA2_Stream7_IRQn = 70,
+
257  USART6_IRQn = 71,
+
258  I2C3_EV_IRQn = 72,
+
259  I2C3_ER_IRQn = 73,
+
260  OTG_HS_EP1_OUT_IRQn = 74,
+
261  OTG_HS_EP1_IN_IRQn = 75,
+
262  OTG_HS_WKUP_IRQn = 76,
+
263  OTG_HS_IRQn = 77,
+
264  DCMI_IRQn = 78,
+
265  CRYP_IRQn = 79,
+
266  HASH_RNG_IRQn = 80,
+
267  FPU_IRQn = 81
+
268 #endif /* STM32F40_41xxx */
+
269 
+
270 #if defined (STM32F427_437xx)
+
271  CAN1_TX_IRQn = 19,
+
272  CAN1_RX0_IRQn = 20,
+
273  CAN1_RX1_IRQn = 21,
+
274  CAN1_SCE_IRQn = 22,
+
275  EXTI9_5_IRQn = 23,
+
276  TIM1_BRK_TIM9_IRQn = 24,
+
277  TIM1_UP_TIM10_IRQn = 25,
+
278  TIM1_TRG_COM_TIM11_IRQn = 26,
+
279  TIM1_CC_IRQn = 27,
+
280  TIM2_IRQn = 28,
+
281  TIM3_IRQn = 29,
+
282  TIM4_IRQn = 30,
+
283  I2C1_EV_IRQn = 31,
+
284  I2C1_ER_IRQn = 32,
+
285  I2C2_EV_IRQn = 33,
+
286  I2C2_ER_IRQn = 34,
+
287  SPI1_IRQn = 35,
+
288  SPI2_IRQn = 36,
+
289  USART1_IRQn = 37,
+
290  USART2_IRQn = 38,
+
291  USART3_IRQn = 39,
+
292  EXTI15_10_IRQn = 40,
+
293  RTC_Alarm_IRQn = 41,
+
294  OTG_FS_WKUP_IRQn = 42,
+
295  TIM8_BRK_TIM12_IRQn = 43,
+
296  TIM8_UP_TIM13_IRQn = 44,
+
297  TIM8_TRG_COM_TIM14_IRQn = 45,
+
298  TIM8_CC_IRQn = 46,
+
299  DMA1_Stream7_IRQn = 47,
+
300  FMC_IRQn = 48,
+
301  SDIO_IRQn = 49,
+
302  TIM5_IRQn = 50,
+
303  SPI3_IRQn = 51,
+
304  UART4_IRQn = 52,
+
305  UART5_IRQn = 53,
+
306  TIM6_DAC_IRQn = 54,
+
307  TIM7_IRQn = 55,
+
308  DMA2_Stream0_IRQn = 56,
+
309  DMA2_Stream1_IRQn = 57,
+
310  DMA2_Stream2_IRQn = 58,
+
311  DMA2_Stream3_IRQn = 59,
+
312  DMA2_Stream4_IRQn = 60,
+
313  ETH_IRQn = 61,
+
314  ETH_WKUP_IRQn = 62,
+
315  CAN2_TX_IRQn = 63,
+
316  CAN2_RX0_IRQn = 64,
+
317  CAN2_RX1_IRQn = 65,
+
318  CAN2_SCE_IRQn = 66,
+
319  OTG_FS_IRQn = 67,
+
320  DMA2_Stream5_IRQn = 68,
+
321  DMA2_Stream6_IRQn = 69,
+
322  DMA2_Stream7_IRQn = 70,
+
323  USART6_IRQn = 71,
+
324  I2C3_EV_IRQn = 72,
+
325  I2C3_ER_IRQn = 73,
+
326  OTG_HS_EP1_OUT_IRQn = 74,
+
327  OTG_HS_EP1_IN_IRQn = 75,
+
328  OTG_HS_WKUP_IRQn = 76,
+
329  OTG_HS_IRQn = 77,
+
330  DCMI_IRQn = 78,
+
331  CRYP_IRQn = 79,
+
332  HASH_RNG_IRQn = 80,
+
333  FPU_IRQn = 81,
+
334  UART7_IRQn = 82,
+
335  UART8_IRQn = 83,
+
336  SPI4_IRQn = 84,
+
337  SPI5_IRQn = 85,
+
338  SPI6_IRQn = 86,
+
339  SAI1_IRQn = 87,
+
340  DMA2D_IRQn = 90
+
341 #endif /* STM32F427_437xx */
+
342 
+
343 #if defined (STM32F429_439xx)
+
344  CAN1_TX_IRQn = 19,
+
345  CAN1_RX0_IRQn = 20,
+
346  CAN1_RX1_IRQn = 21,
+
347  CAN1_SCE_IRQn = 22,
+
348  EXTI9_5_IRQn = 23,
+
349  TIM1_BRK_TIM9_IRQn = 24,
+
350  TIM1_UP_TIM10_IRQn = 25,
+
351  TIM1_TRG_COM_TIM11_IRQn = 26,
+
352  TIM1_CC_IRQn = 27,
+
353  TIM2_IRQn = 28,
+
354  TIM3_IRQn = 29,
+
355  TIM4_IRQn = 30,
+
356  I2C1_EV_IRQn = 31,
+
357  I2C1_ER_IRQn = 32,
+
358  I2C2_EV_IRQn = 33,
+
359  I2C2_ER_IRQn = 34,
+
360  SPI1_IRQn = 35,
+
361  SPI2_IRQn = 36,
+
362  USART1_IRQn = 37,
+
363  USART2_IRQn = 38,
+
364  USART3_IRQn = 39,
+
365  EXTI15_10_IRQn = 40,
+
366  RTC_Alarm_IRQn = 41,
+
367  OTG_FS_WKUP_IRQn = 42,
+
368  TIM8_BRK_TIM12_IRQn = 43,
+
369  TIM8_UP_TIM13_IRQn = 44,
+
370  TIM8_TRG_COM_TIM14_IRQn = 45,
+
371  TIM8_CC_IRQn = 46,
+
372  DMA1_Stream7_IRQn = 47,
+
373  FMC_IRQn = 48,
+
374  SDIO_IRQn = 49,
+
375  TIM5_IRQn = 50,
+
376  SPI3_IRQn = 51,
+
377  UART4_IRQn = 52,
+
378  UART5_IRQn = 53,
+
379  TIM6_DAC_IRQn = 54,
+
380  TIM7_IRQn = 55,
+
381  DMA2_Stream0_IRQn = 56,
+
382  DMA2_Stream1_IRQn = 57,
+
383  DMA2_Stream2_IRQn = 58,
+
384  DMA2_Stream3_IRQn = 59,
+
385  DMA2_Stream4_IRQn = 60,
+
386  ETH_IRQn = 61,
+
387  ETH_WKUP_IRQn = 62,
+
388  CAN2_TX_IRQn = 63,
+
389  CAN2_RX0_IRQn = 64,
+
390  CAN2_RX1_IRQn = 65,
+
391  CAN2_SCE_IRQn = 66,
+
392  OTG_FS_IRQn = 67,
+
393  DMA2_Stream5_IRQn = 68,
+
394  DMA2_Stream6_IRQn = 69,
+
395  DMA2_Stream7_IRQn = 70,
+
396  USART6_IRQn = 71,
+
397  I2C3_EV_IRQn = 72,
+
398  I2C3_ER_IRQn = 73,
+
399  OTG_HS_EP1_OUT_IRQn = 74,
+
400  OTG_HS_EP1_IN_IRQn = 75,
+
401  OTG_HS_WKUP_IRQn = 76,
+
402  OTG_HS_IRQn = 77,
+
403  DCMI_IRQn = 78,
+
404  CRYP_IRQn = 79,
+
405  HASH_RNG_IRQn = 80,
+
406  FPU_IRQn = 81,
+
407  UART7_IRQn = 82,
+
408  UART8_IRQn = 83,
+
409  SPI4_IRQn = 84,
+
410  SPI5_IRQn = 85,
+
411  SPI6_IRQn = 86,
+
412  SAI1_IRQn = 87,
+
413  LTDC_IRQn = 88,
+
414  LTDC_ER_IRQn = 89,
+
415  DMA2D_IRQn = 90
+
416 #endif /* STM32F429_439xx */
+
417 
+
418 #if defined (STM32F401xx) || defined (STM32F411xE)
+
419  EXTI9_5_IRQn = 23,
+
420  TIM1_BRK_TIM9_IRQn = 24,
+
421  TIM1_UP_TIM10_IRQn = 25,
+
422  TIM1_TRG_COM_TIM11_IRQn = 26,
+
423  TIM1_CC_IRQn = 27,
+
424  TIM2_IRQn = 28,
+
425  TIM3_IRQn = 29,
+
426  TIM4_IRQn = 30,
+
427  I2C1_EV_IRQn = 31,
+
428  I2C1_ER_IRQn = 32,
+
429  I2C2_EV_IRQn = 33,
+
430  I2C2_ER_IRQn = 34,
+
431  SPI1_IRQn = 35,
+
432  SPI2_IRQn = 36,
+
433  USART1_IRQn = 37,
+
434  USART2_IRQn = 38,
+
435  EXTI15_10_IRQn = 40,
+
436  RTC_Alarm_IRQn = 41,
+
437  OTG_FS_WKUP_IRQn = 42,
+
438  DMA1_Stream7_IRQn = 47,
+
439  SDIO_IRQn = 49,
+
440  TIM5_IRQn = 50,
+
441  SPI3_IRQn = 51,
+
442  DMA2_Stream0_IRQn = 56,
+
443  DMA2_Stream1_IRQn = 57,
+
444  DMA2_Stream2_IRQn = 58,
+
445  DMA2_Stream3_IRQn = 59,
+
446  DMA2_Stream4_IRQn = 60,
+
447  OTG_FS_IRQn = 67,
+
448  DMA2_Stream5_IRQn = 68,
+
449  DMA2_Stream6_IRQn = 69,
+
450  DMA2_Stream7_IRQn = 70,
+
451  USART6_IRQn = 71,
+
452  I2C3_EV_IRQn = 72,
+
453  I2C3_ER_IRQn = 73,
+
454  FPU_IRQn = 81,
+
455 #if defined (STM32F401xx)
+
456  SPI4_IRQn = 84
+
457 #endif /* STM32F411xE */
+
458 #if defined (STM32F411xE)
+
459  SPI4_IRQn = 84,
+
460  SPI5_IRQn = 85
+
461 #endif /* STM32F411xE */
+
462 #endif /* STM32F401xx || STM32F411xE */
+
463 
+
464 } IRQn_Type;
+
465 
+
470 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+
471 #include "system_stm32f4xx.h"
+
472 #include <stdint.h>
+
473 
+
478 typedef int32_t s32;
+
479 typedef int16_t s16;
+
480 typedef int8_t s8;
+
481 
+
482 typedef const int32_t sc32;
+
483 typedef const int16_t sc16;
+
484 typedef const int8_t sc8;
+
486 typedef __IO int32_t vs32;
+
487 typedef __IO int16_t vs16;
+
488 typedef __IO int8_t vs8;
+
489 
+
490 typedef __I int32_t vsc32;
+
491 typedef __I int16_t vsc16;
+
492 typedef __I int8_t vsc8;
+
494 typedef uint32_t u32;
+
495 typedef uint16_t u16;
+
496 typedef uint8_t u8;
+
497 
+
498 typedef const uint32_t uc32;
+
499 typedef const uint16_t uc16;
+
500 typedef const uint8_t uc8;
+
502 typedef __IO uint32_t vu32;
+
503 typedef __IO uint16_t vu16;
+
504 typedef __IO uint8_t vu8;
+
505 
+
506 typedef __I uint32_t vuc32;
+
507 typedef __I uint16_t vuc16;
+
508 typedef __I uint8_t vuc8;
+
510 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
511 
+
512 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
513 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
514 
+
515 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
516 
+
529 typedef struct
+
530 {
+
531  __IO uint32_t SR;
+
532  __IO uint32_t CR1;
+
533  __IO uint32_t CR2;
+
534  __IO uint32_t SMPR1;
+
535  __IO uint32_t SMPR2;
+
536  __IO uint32_t JOFR1;
+
537  __IO uint32_t JOFR2;
+
538  __IO uint32_t JOFR3;
+
539  __IO uint32_t JOFR4;
+
540  __IO uint32_t HTR;
+
541  __IO uint32_t LTR;
+
542  __IO uint32_t SQR1;
+
543  __IO uint32_t SQR2;
+
544  __IO uint32_t SQR3;
+
545  __IO uint32_t JSQR;
+
546  __IO uint32_t JDR1;
+
547  __IO uint32_t JDR2;
+
548  __IO uint32_t JDR3;
+
549  __IO uint32_t JDR4;
+
550  __IO uint32_t DR;
+
551 } ADC_TypeDef;
+
552 
+
553 typedef struct
+
554 {
+
555  __IO uint32_t CSR;
+
556  __IO uint32_t CCR;
+
557  __IO uint32_t CDR;
+
559 } ADC_Common_TypeDef;
+
560 
+
561 
+
566 typedef struct
+
567 {
+
568  __IO uint32_t TIR;
+
569  __IO uint32_t TDTR;
+
570  __IO uint32_t TDLR;
+
571  __IO uint32_t TDHR;
+
572 } CAN_TxMailBox_TypeDef;
+
573 
+
578 typedef struct
+
579 {
+
580  __IO uint32_t RIR;
+
581  __IO uint32_t RDTR;
+
582  __IO uint32_t RDLR;
+
583  __IO uint32_t RDHR;
+
584 } CAN_FIFOMailBox_TypeDef;
+
585 
+
590 typedef struct
+
591 {
+
592  __IO uint32_t FR1;
+
593  __IO uint32_t FR2;
+
594 } CAN_FilterRegister_TypeDef;
+
595 
+
600 typedef struct
+
601 {
+
602  __IO uint32_t MCR;
+
603  __IO uint32_t MSR;
+
604  __IO uint32_t TSR;
+
605  __IO uint32_t RF0R;
+
606  __IO uint32_t RF1R;
+
607  __IO uint32_t IER;
+
608  __IO uint32_t ESR;
+
609  __IO uint32_t BTR;
+
610  uint32_t RESERVED0[88];
+
611  CAN_TxMailBox_TypeDef sTxMailBox[3];
+
612  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+
613  uint32_t RESERVED1[12];
+
614  __IO uint32_t FMR;
+
615  __IO uint32_t FM1R;
+
616  uint32_t RESERVED2;
+
617  __IO uint32_t FS1R;
+
618  uint32_t RESERVED3;
+
619  __IO uint32_t FFA1R;
+
620  uint32_t RESERVED4;
+
621  __IO uint32_t FA1R;
+
622  uint32_t RESERVED5[8];
+
623  CAN_FilterRegister_TypeDef sFilterRegister[28];
+
624 } CAN_TypeDef;
+
625 
+
630 typedef struct
+
631 {
+
632  __IO uint32_t DR;
+
633  __IO uint8_t IDR;
+
634  uint8_t RESERVED0;
+
635  uint16_t RESERVED1;
+
636  __IO uint32_t CR;
+
637 } CRC_TypeDef;
+
638 
+
643 typedef struct
+
644 {
+
645  __IO uint32_t CR;
+
646  __IO uint32_t SWTRIGR;
+
647  __IO uint32_t DHR12R1;
+
648  __IO uint32_t DHR12L1;
+
649  __IO uint32_t DHR8R1;
+
650  __IO uint32_t DHR12R2;
+
651  __IO uint32_t DHR12L2;
+
652  __IO uint32_t DHR8R2;
+
653  __IO uint32_t DHR12RD;
+
654  __IO uint32_t DHR12LD;
+
655  __IO uint32_t DHR8RD;
+
656  __IO uint32_t DOR1;
+
657  __IO uint32_t DOR2;
+
658  __IO uint32_t SR;
+
659 } DAC_TypeDef;
+
660 
+
665 typedef struct
+
666 {
+
667  __IO uint32_t IDCODE;
+
668  __IO uint32_t CR;
+
669  __IO uint32_t APB1FZ;
+
670  __IO uint32_t APB2FZ;
+
671 }DBGMCU_TypeDef;
+
672 
+
677 typedef struct
+
678 {
+
679  __IO uint32_t CR;
+
680  __IO uint32_t SR;
+
681  __IO uint32_t RISR;
+
682  __IO uint32_t IER;
+
683  __IO uint32_t MISR;
+
684  __IO uint32_t ICR;
+
685  __IO uint32_t ESCR;
+
686  __IO uint32_t ESUR;
+
687  __IO uint32_t CWSTRTR;
+
688  __IO uint32_t CWSIZER;
+
689  __IO uint32_t DR;
+
690 } DCMI_TypeDef;
+
691 
+
696 typedef struct
+
697 {
+
698  __IO uint32_t CR;
+
699  __IO uint32_t NDTR;
+
700  __IO uint32_t PAR;
+
701  __IO uint32_t M0AR;
+
702  __IO uint32_t M1AR;
+
703  __IO uint32_t FCR;
+
704 } DMA_Stream_TypeDef;
+
705 
+
706 typedef struct
+
707 {
+
708  __IO uint32_t LISR;
+
709  __IO uint32_t HISR;
+
710  __IO uint32_t LIFCR;
+
711  __IO uint32_t HIFCR;
+
712 } DMA_TypeDef;
+
713 
+
718 typedef struct
+
719 {
+
720  __IO uint32_t CR;
+
721  __IO uint32_t ISR;
+
722  __IO uint32_t IFCR;
+
723  __IO uint32_t FGMAR;
+
724  __IO uint32_t FGOR;
+
725  __IO uint32_t BGMAR;
+
726  __IO uint32_t BGOR;
+
727  __IO uint32_t FGPFCCR;
+
728  __IO uint32_t FGCOLR;
+
729  __IO uint32_t BGPFCCR;
+
730  __IO uint32_t BGCOLR;
+
731  __IO uint32_t FGCMAR;
+
732  __IO uint32_t BGCMAR;
+
733  __IO uint32_t OPFCCR;
+
734  __IO uint32_t OCOLR;
+
735  __IO uint32_t OMAR;
+
736  __IO uint32_t OOR;
+
737  __IO uint32_t NLR;
+
738  __IO uint32_t LWR;
+
739  __IO uint32_t AMTCR;
+
740  uint32_t RESERVED[236];
+
741  __IO uint32_t FGCLUT[256];
+
742  __IO uint32_t BGCLUT[256];
+
743 } DMA2D_TypeDef;
+
744 
+
749 typedef struct
+
750 {
+
751  __IO uint32_t MACCR;
+
752  __IO uint32_t MACFFR;
+
753  __IO uint32_t MACHTHR;
+
754  __IO uint32_t MACHTLR;
+
755  __IO uint32_t MACMIIAR;
+
756  __IO uint32_t MACMIIDR;
+
757  __IO uint32_t MACFCR;
+
758  __IO uint32_t MACVLANTR; /* 8 */
+
759  uint32_t RESERVED0[2];
+
760  __IO uint32_t MACRWUFFR; /* 11 */
+
761  __IO uint32_t MACPMTCSR;
+
762  uint32_t RESERVED1[2];
+
763  __IO uint32_t MACSR; /* 15 */
+
764  __IO uint32_t MACIMR;
+
765  __IO uint32_t MACA0HR;
+
766  __IO uint32_t MACA0LR;
+
767  __IO uint32_t MACA1HR;
+
768  __IO uint32_t MACA1LR;
+
769  __IO uint32_t MACA2HR;
+
770  __IO uint32_t MACA2LR;
+
771  __IO uint32_t MACA3HR;
+
772  __IO uint32_t MACA3LR; /* 24 */
+
773  uint32_t RESERVED2[40];
+
774  __IO uint32_t MMCCR; /* 65 */
+
775  __IO uint32_t MMCRIR;
+
776  __IO uint32_t MMCTIR;
+
777  __IO uint32_t MMCRIMR;
+
778  __IO uint32_t MMCTIMR; /* 69 */
+
779  uint32_t RESERVED3[14];
+
780  __IO uint32_t MMCTGFSCCR; /* 84 */
+
781  __IO uint32_t MMCTGFMSCCR;
+
782  uint32_t RESERVED4[5];
+
783  __IO uint32_t MMCTGFCR;
+
784  uint32_t RESERVED5[10];
+
785  __IO uint32_t MMCRFCECR;
+
786  __IO uint32_t MMCRFAECR;
+
787  uint32_t RESERVED6[10];
+
788  __IO uint32_t MMCRGUFCR;
+
789  uint32_t RESERVED7[334];
+
790  __IO uint32_t PTPTSCR;
+
791  __IO uint32_t PTPSSIR;
+
792  __IO uint32_t PTPTSHR;
+
793  __IO uint32_t PTPTSLR;
+
794  __IO uint32_t PTPTSHUR;
+
795  __IO uint32_t PTPTSLUR;
+
796  __IO uint32_t PTPTSAR;
+
797  __IO uint32_t PTPTTHR;
+
798  __IO uint32_t PTPTTLR;
+
799  __IO uint32_t RESERVED8;
+
800  __IO uint32_t PTPTSSR;
+
801  uint32_t RESERVED9[565];
+
802  __IO uint32_t DMABMR;
+
803  __IO uint32_t DMATPDR;
+
804  __IO uint32_t DMARPDR;
+
805  __IO uint32_t DMARDLAR;
+
806  __IO uint32_t DMATDLAR;
+
807  __IO uint32_t DMASR;
+
808  __IO uint32_t DMAOMR;
+
809  __IO uint32_t DMAIER;
+
810  __IO uint32_t DMAMFBOCR;
+
811  __IO uint32_t DMARSWTR;
+
812  uint32_t RESERVED10[8];
+
813  __IO uint32_t DMACHTDR;
+
814  __IO uint32_t DMACHRDR;
+
815  __IO uint32_t DMACHTBAR;
+
816  __IO uint32_t DMACHRBAR;
+
817 } ETH_TypeDef;
+
818 
+
823 typedef struct
+
824 {
+
825  __IO uint32_t IMR;
+
826  __IO uint32_t EMR;
+
827  __IO uint32_t RTSR;
+
828  __IO uint32_t FTSR;
+
829  __IO uint32_t SWIER;
+
830  __IO uint32_t PR;
+
831 } EXTI_TypeDef;
+
832 
+
837 typedef struct
+
838 {
+
839  __IO uint32_t ACR;
+
840  __IO uint32_t KEYR;
+
841  __IO uint32_t OPTKEYR;
+
842  __IO uint32_t SR;
+
843  __IO uint32_t CR;
+
844  __IO uint32_t OPTCR;
+
845  __IO uint32_t OPTCR1;
+
846 } FLASH_TypeDef;
+
847 
+
848 #if defined (STM32F40_41xxx)
+
849 
+
853 typedef struct
+
854 {
+
855  __IO uint32_t BTCR[8];
+
856 } FSMC_Bank1_TypeDef;
+
857 
+
862 typedef struct
+
863 {
+
864  __IO uint32_t BWTR[7];
+
865 } FSMC_Bank1E_TypeDef;
+
866 
+
871 typedef struct
+
872 {
+
873  __IO uint32_t PCR2;
+
874  __IO uint32_t SR2;
+
875  __IO uint32_t PMEM2;
+
876  __IO uint32_t PATT2;
+
877  uint32_t RESERVED0;
+
878  __IO uint32_t ECCR2;
+
879 } FSMC_Bank2_TypeDef;
+
880 
+
885 typedef struct
+
886 {
+
887  __IO uint32_t PCR3;
+
888  __IO uint32_t SR3;
+
889  __IO uint32_t PMEM3;
+
890  __IO uint32_t PATT3;
+
891  uint32_t RESERVED0;
+
892  __IO uint32_t ECCR3;
+
893 } FSMC_Bank3_TypeDef;
+
894 
+
899 typedef struct
+
900 {
+
901  __IO uint32_t PCR4;
+
902  __IO uint32_t SR4;
+
903  __IO uint32_t PMEM4;
+
904  __IO uint32_t PATT4;
+
905  __IO uint32_t PIO4;
+
906 } FSMC_Bank4_TypeDef;
+
907 #endif /* STM32F40_41xxx */
+
908 
+
909 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
910 
+
914 typedef struct
+
915 {
+
916  __IO uint32_t BTCR[8];
+
917 } FMC_Bank1_TypeDef;
+
918 
+
923 typedef struct
+
924 {
+
925  __IO uint32_t BWTR[7];
+
926 } FMC_Bank1E_TypeDef;
+
927 
+
932 typedef struct
+
933 {
+
934  __IO uint32_t PCR2;
+
935  __IO uint32_t SR2;
+
936  __IO uint32_t PMEM2;
+
937  __IO uint32_t PATT2;
+
938  uint32_t RESERVED0;
+
939  __IO uint32_t ECCR2;
+
940 } FMC_Bank2_TypeDef;
+
941 
+
946 typedef struct
+
947 {
+
948  __IO uint32_t PCR3;
+
949  __IO uint32_t SR3;
+
950  __IO uint32_t PMEM3;
+
951  __IO uint32_t PATT3;
+
952  uint32_t RESERVED0;
+
953  __IO uint32_t ECCR3;
+
954 } FMC_Bank3_TypeDef;
+
955 
+
960 typedef struct
+
961 {
+
962  __IO uint32_t PCR4;
+
963  __IO uint32_t SR4;
+
964  __IO uint32_t PMEM4;
+
965  __IO uint32_t PATT4;
+
966  __IO uint32_t PIO4;
+
967 } FMC_Bank4_TypeDef;
+
968 
+
973 typedef struct
+
974 {
+
975  __IO uint32_t SDCR[2];
+
976  __IO uint32_t SDTR[2];
+
977  __IO uint32_t SDCMR;
+
978  __IO uint32_t SDRTR;
+
979  __IO uint32_t SDSR;
+
980 } FMC_Bank5_6_TypeDef;
+
981 #endif /* STM32F427_437xx || STM32F429_439xx */
+
982 
+
987 typedef struct
+
988 {
+
989  __IO uint32_t MODER;
+
990  __IO uint32_t OTYPER;
+
991  __IO uint32_t OSPEEDR;
+
992  __IO uint32_t PUPDR;
+
993  __IO uint32_t IDR;
+
994  __IO uint32_t ODR;
+
995  __IO uint16_t BSRRL;
+
996  __IO uint16_t BSRRH;
+
997  __IO uint32_t LCKR;
+
998  __IO uint32_t AFR[2];
+
999 } GPIO_TypeDef;
+
1000 
+
1005 typedef struct
+
1006 {
+
1007  __IO uint32_t MEMRMP;
+
1008  __IO uint32_t PMC;
+
1009  __IO uint32_t EXTICR[4];
+
1010  uint32_t RESERVED[2];
+
1011  __IO uint32_t CMPCR;
+
1012 } SYSCFG_TypeDef;
+
1013 
+
1018 typedef struct
+
1019 {
+
1020  __IO uint16_t CR1;
+
1021  uint16_t RESERVED0;
+
1022  __IO uint16_t CR2;
+
1023  uint16_t RESERVED1;
+
1024  __IO uint16_t OAR1;
+
1025  uint16_t RESERVED2;
+
1026  __IO uint16_t OAR2;
+
1027  uint16_t RESERVED3;
+
1028  __IO uint16_t DR;
+
1029  uint16_t RESERVED4;
+
1030  __IO uint16_t SR1;
+
1031  uint16_t RESERVED5;
+
1032  __IO uint16_t SR2;
+
1033  uint16_t RESERVED6;
+
1034  __IO uint16_t CCR;
+
1035  uint16_t RESERVED7;
+
1036  __IO uint16_t TRISE;
+
1037  uint16_t RESERVED8;
+
1038  __IO uint16_t FLTR;
+
1039  uint16_t RESERVED9;
+
1040 } I2C_TypeDef;
+
1041 
+
1046 typedef struct
+
1047 {
+
1048  __IO uint32_t KR;
+
1049  __IO uint32_t PR;
+
1050  __IO uint32_t RLR;
+
1051  __IO uint32_t SR;
+
1052 } IWDG_TypeDef;
+
1053 
+
1058 typedef struct
+
1059 {
+
1060  uint32_t RESERVED0[2];
+
1061  __IO uint32_t SSCR;
+
1062  __IO uint32_t BPCR;
+
1063  __IO uint32_t AWCR;
+
1064  __IO uint32_t TWCR;
+
1065  __IO uint32_t GCR;
+
1066  uint32_t RESERVED1[2];
+
1067  __IO uint32_t SRCR;
+
1068  uint32_t RESERVED2[1];
+
1069  __IO uint32_t BCCR;
+
1070  uint32_t RESERVED3[1];
+
1071  __IO uint32_t IER;
+
1072  __IO uint32_t ISR;
+
1073  __IO uint32_t ICR;
+
1074  __IO uint32_t LIPCR;
+
1075  __IO uint32_t CPSR;
+
1076  __IO uint32_t CDSR;
+
1077 } LTDC_TypeDef;
+
1078 
+
1083 typedef struct
+
1084 {
+
1085  __IO uint32_t CR;
+
1086  __IO uint32_t WHPCR;
+
1087  __IO uint32_t WVPCR;
+
1088  __IO uint32_t CKCR;
+
1089  __IO uint32_t PFCR;
+
1090  __IO uint32_t CACR;
+
1091  __IO uint32_t DCCR;
+
1092  __IO uint32_t BFCR;
+
1093  uint32_t RESERVED0[2];
+
1094  __IO uint32_t CFBAR;
+
1095  __IO uint32_t CFBLR;
+
1096  __IO uint32_t CFBLNR;
+
1097  uint32_t RESERVED1[3];
+
1098  __IO uint32_t CLUTWR;
+
1100 } LTDC_Layer_TypeDef;
+
1101 
+
1106 typedef struct
+
1107 {
+
1108  __IO uint32_t CR;
+
1109  __IO uint32_t CSR;
+
1110 } PWR_TypeDef;
+
1111 
+
1116 typedef struct
+
1117 {
+
1118  __IO uint32_t CR;
+
1119  __IO uint32_t PLLCFGR;
+
1120  __IO uint32_t CFGR;
+
1121  __IO uint32_t CIR;
+
1122  __IO uint32_t AHB1RSTR;
+
1123  __IO uint32_t AHB2RSTR;
+
1124  __IO uint32_t AHB3RSTR;
+
1125  uint32_t RESERVED0;
+
1126  __IO uint32_t APB1RSTR;
+
1127  __IO uint32_t APB2RSTR;
+
1128  uint32_t RESERVED1[2];
+
1129  __IO uint32_t AHB1ENR;
+
1130  __IO uint32_t AHB2ENR;
+
1131  __IO uint32_t AHB3ENR;
+
1132  uint32_t RESERVED2;
+
1133  __IO uint32_t APB1ENR;
+
1134  __IO uint32_t APB2ENR;
+
1135  uint32_t RESERVED3[2];
+
1136  __IO uint32_t AHB1LPENR;
+
1137  __IO uint32_t AHB2LPENR;
+
1138  __IO uint32_t AHB3LPENR;
+
1139  uint32_t RESERVED4;
+
1140  __IO uint32_t APB1LPENR;
+
1141  __IO uint32_t APB2LPENR;
+
1142  uint32_t RESERVED5[2];
+
1143  __IO uint32_t BDCR;
+
1144  __IO uint32_t CSR;
+
1145  uint32_t RESERVED6[2];
+
1146  __IO uint32_t SSCGR;
+
1147  __IO uint32_t PLLI2SCFGR;
+
1148  __IO uint32_t PLLSAICFGR;
+
1149  __IO uint32_t DCKCFGR;
+
1151 } RCC_TypeDef;
+
1152 
+
1157 typedef struct
+
1158 {
+
1159  __IO uint32_t TR;
+
1160  __IO uint32_t DR;
+
1161  __IO uint32_t CR;
+
1162  __IO uint32_t ISR;
+
1163  __IO uint32_t PRER;
+
1164  __IO uint32_t WUTR;
+
1165  __IO uint32_t CALIBR;
+
1166  __IO uint32_t ALRMAR;
+
1167  __IO uint32_t ALRMBR;
+
1168  __IO uint32_t WPR;
+
1169  __IO uint32_t SSR;
+
1170  __IO uint32_t SHIFTR;
+
1171  __IO uint32_t TSTR;
+
1172  __IO uint32_t TSDR;
+
1173  __IO uint32_t TSSSR;
+
1174  __IO uint32_t CALR;
+
1175  __IO uint32_t TAFCR;
+
1176  __IO uint32_t ALRMASSR;
+
1177  __IO uint32_t ALRMBSSR;
+
1178  uint32_t RESERVED7;
+
1179  __IO uint32_t BKP0R;
+
1180  __IO uint32_t BKP1R;
+
1181  __IO uint32_t BKP2R;
+
1182  __IO uint32_t BKP3R;
+
1183  __IO uint32_t BKP4R;
+
1184  __IO uint32_t BKP5R;
+
1185  __IO uint32_t BKP6R;
+
1186  __IO uint32_t BKP7R;
+
1187  __IO uint32_t BKP8R;
+
1188  __IO uint32_t BKP9R;
+
1189  __IO uint32_t BKP10R;
+
1190  __IO uint32_t BKP11R;
+
1191  __IO uint32_t BKP12R;
+
1192  __IO uint32_t BKP13R;
+
1193  __IO uint32_t BKP14R;
+
1194  __IO uint32_t BKP15R;
+
1195  __IO uint32_t BKP16R;
+
1196  __IO uint32_t BKP17R;
+
1197  __IO uint32_t BKP18R;
+
1198  __IO uint32_t BKP19R;
+
1199 } RTC_TypeDef;
+
1200 
+
1201 
+
1206 typedef struct
+
1207 {
+
1208  __IO uint32_t GCR;
+
1209 } SAI_TypeDef;
+
1210 
+
1211 typedef struct
+
1212 {
+
1213  __IO uint32_t CR1;
+
1214  __IO uint32_t CR2;
+
1215  __IO uint32_t FRCR;
+
1216  __IO uint32_t SLOTR;
+
1217  __IO uint32_t IMR;
+
1218  __IO uint32_t SR;
+
1219  __IO uint32_t CLRFR;
+
1220  __IO uint32_t DR;
+
1221 } SAI_Block_TypeDef;
+
1222 
+
1227 typedef struct
+
1228 {
+
1229  __IO uint32_t POWER;
+
1230  __IO uint32_t CLKCR;
+
1231  __IO uint32_t ARG;
+
1232  __IO uint32_t CMD;
+
1233  __I uint32_t RESPCMD;
+
1234  __I uint32_t RESP1;
+
1235  __I uint32_t RESP2;
+
1236  __I uint32_t RESP3;
+
1237  __I uint32_t RESP4;
+
1238  __IO uint32_t DTIMER;
+
1239  __IO uint32_t DLEN;
+
1240  __IO uint32_t DCTRL;
+
1241  __I uint32_t DCOUNT;
+
1242  __I uint32_t STA;
+
1243  __IO uint32_t ICR;
+
1244  __IO uint32_t MASK;
+
1245  uint32_t RESERVED0[2];
+
1246  __I uint32_t FIFOCNT;
+
1247  uint32_t RESERVED1[13];
+
1248  __IO uint32_t FIFO;
+
1249 } SDIO_TypeDef;
+
1250 
+
1255 typedef struct
+
1256 {
+
1257  __IO uint16_t CR1;
+
1258  uint16_t RESERVED0;
+
1259  __IO uint16_t CR2;
+
1260  uint16_t RESERVED1;
+
1261  __IO uint16_t SR;
+
1262  uint16_t RESERVED2;
+
1263  __IO uint16_t DR;
+
1264  uint16_t RESERVED3;
+
1265  __IO uint16_t CRCPR;
+
1266  uint16_t RESERVED4;
+
1267  __IO uint16_t RXCRCR;
+
1268  uint16_t RESERVED5;
+
1269  __IO uint16_t TXCRCR;
+
1270  uint16_t RESERVED6;
+
1271  __IO uint16_t I2SCFGR;
+
1272  uint16_t RESERVED7;
+
1273  __IO uint16_t I2SPR;
+
1274  uint16_t RESERVED8;
+
1275 } SPI_TypeDef;
+
1276 
+
1281 typedef struct
+
1282 {
+
1283  __IO uint16_t CR1;
+
1284  uint16_t RESERVED0;
+
1285  __IO uint16_t CR2;
+
1286  uint16_t RESERVED1;
+
1287  __IO uint16_t SMCR;
+
1288  uint16_t RESERVED2;
+
1289  __IO uint16_t DIER;
+
1290  uint16_t RESERVED3;
+
1291  __IO uint16_t SR;
+
1292  uint16_t RESERVED4;
+
1293  __IO uint16_t EGR;
+
1294  uint16_t RESERVED5;
+
1295  __IO uint16_t CCMR1;
+
1296  uint16_t RESERVED6;
+
1297  __IO uint16_t CCMR2;
+
1298  uint16_t RESERVED7;
+
1299  __IO uint16_t CCER;
+
1300  uint16_t RESERVED8;
+
1301  __IO uint32_t CNT;
+
1302  __IO uint16_t PSC;
+
1303  uint16_t RESERVED9;
+
1304  __IO uint32_t ARR;
+
1305  __IO uint16_t RCR;
+
1306  uint16_t RESERVED10;
+
1307  __IO uint32_t CCR1;
+
1308  __IO uint32_t CCR2;
+
1309  __IO uint32_t CCR3;
+
1310  __IO uint32_t CCR4;
+
1311  __IO uint16_t BDTR;
+
1312  uint16_t RESERVED11;
+
1313  __IO uint16_t DCR;
+
1314  uint16_t RESERVED12;
+
1315  __IO uint16_t DMAR;
+
1316  uint16_t RESERVED13;
+
1317  __IO uint16_t OR;
+
1318  uint16_t RESERVED14;
+
1319 } TIM_TypeDef;
+
1320 
+
1325 typedef struct
+
1326 {
+
1327  __IO uint16_t SR;
+
1328  uint16_t RESERVED0;
+
1329  __IO uint16_t DR;
+
1330  uint16_t RESERVED1;
+
1331  __IO uint16_t BRR;
+
1332  uint16_t RESERVED2;
+
1333  __IO uint16_t CR1;
+
1334  uint16_t RESERVED3;
+
1335  __IO uint16_t CR2;
+
1336  uint16_t RESERVED4;
+
1337  __IO uint16_t CR3;
+
1338  uint16_t RESERVED5;
+
1339  __IO uint16_t GTPR;
+
1340  uint16_t RESERVED6;
+
1341 } USART_TypeDef;
+
1342 
+
1347 typedef struct
+
1348 {
+
1349  __IO uint32_t CR;
+
1350  __IO uint32_t CFR;
+
1351  __IO uint32_t SR;
+
1352 } WWDG_TypeDef;
+
1353 
+
1358 typedef struct
+
1359 {
+
1360  __IO uint32_t CR;
+
1361  __IO uint32_t SR;
+
1362  __IO uint32_t DR;
+
1363  __IO uint32_t DOUT;
+
1364  __IO uint32_t DMACR;
+
1365  __IO uint32_t IMSCR;
+
1366  __IO uint32_t RISR;
+
1367  __IO uint32_t MISR;
+
1368  __IO uint32_t K0LR;
+
1369  __IO uint32_t K0RR;
+
1370  __IO uint32_t K1LR;
+
1371  __IO uint32_t K1RR;
+
1372  __IO uint32_t K2LR;
+
1373  __IO uint32_t K2RR;
+
1374  __IO uint32_t K3LR;
+
1375  __IO uint32_t K3RR;
+
1376  __IO uint32_t IV0LR;
+
1377  __IO uint32_t IV0RR;
+
1378  __IO uint32_t IV1LR;
+
1379  __IO uint32_t IV1RR;
+
1380  __IO uint32_t CSGCMCCM0R;
+
1381  __IO uint32_t CSGCMCCM1R;
+
1382  __IO uint32_t CSGCMCCM2R;
+
1383  __IO uint32_t CSGCMCCM3R;
+
1384  __IO uint32_t CSGCMCCM4R;
+
1385  __IO uint32_t CSGCMCCM5R;
+
1386  __IO uint32_t CSGCMCCM6R;
+
1387  __IO uint32_t CSGCMCCM7R;
+
1388  __IO uint32_t CSGCM0R;
+
1389  __IO uint32_t CSGCM1R;
+
1390  __IO uint32_t CSGCM2R;
+
1391  __IO uint32_t CSGCM3R;
+
1392  __IO uint32_t CSGCM4R;
+
1393  __IO uint32_t CSGCM5R;
+
1394  __IO uint32_t CSGCM6R;
+
1395  __IO uint32_t CSGCM7R;
+
1396 } CRYP_TypeDef;
+
1397 
+
1402 typedef struct
+
1403 {
+
1404  __IO uint32_t CR;
+
1405  __IO uint32_t DIN;
+
1406  __IO uint32_t STR;
+
1407  __IO uint32_t HR[5];
+
1408  __IO uint32_t IMR;
+
1409  __IO uint32_t SR;
+
1410  uint32_t RESERVED[52];
+
1411  __IO uint32_t CSR[54];
+
1412 } HASH_TypeDef;
+
1413 
+
1418 typedef struct
+
1419 {
+
1420  __IO uint32_t HR[8];
+
1421 } HASH_DIGEST_TypeDef;
+
1422 
+
1427 typedef struct
+
1428 {
+
1429  __IO uint32_t CR;
+
1430  __IO uint32_t SR;
+
1431  __IO uint32_t DR;
+
1432 } RNG_TypeDef;
+
1433 
+
1441 #define FLASH_BASE ((uint32_t)0x08000000)
+
1442 #define CCMDATARAM_BASE ((uint32_t)0x10000000)
+
1443 #define SRAM1_BASE ((uint32_t)0x20000000)
+
1444 #define SRAM2_BASE ((uint32_t)0x2001C000)
+
1445 #define SRAM3_BASE ((uint32_t)0x20020000)
+
1446 #define PERIPH_BASE ((uint32_t)0x40000000)
+
1447 #define BKPSRAM_BASE ((uint32_t)0x40024000)
+
1449 #if defined (STM32F40_41xxx)
+
1450 #define FSMC_R_BASE ((uint32_t)0xA0000000)
+
1451 #endif /* STM32F40_41xxx */
+
1452 
+
1453 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
1454 #define FMC_R_BASE ((uint32_t)0xA0000000)
+
1455 #endif /* STM32F427_437xx || STM32F429_439xx */
+
1456 
+
1457 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000)
+
1458 #define SRAM1_BB_BASE ((uint32_t)0x22000000)
+
1459 #define SRAM2_BB_BASE ((uint32_t)0x2201C000)
+
1460 #define SRAM3_BB_BASE ((uint32_t)0x22400000)
+
1461 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
+
1462 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000)
+
1464 /* Legacy defines */
+
1465 #define SRAM_BASE SRAM1_BASE
+
1466 #define SRAM_BB_BASE SRAM1_BB_BASE
+
1467 
+
1468 
+
1470 #define APB1PERIPH_BASE PERIPH_BASE
+
1471 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+
1472 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+
1473 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
1474 
+
1476 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+
1477 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+
1478 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+
1479 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+
1480 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+
1481 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+
1482 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+
1483 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+
1484 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+
1485 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+
1486 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+
1487 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+
1488 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
+
1489 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+
1490 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+
1491 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
+
1492 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+
1493 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+
1494 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+
1495 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+
1496 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+
1497 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+
1498 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+
1499 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+
1500 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+
1501 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+
1502 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
1503 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+
1504 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+
1505 
+
1507 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
+
1508 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
+
1509 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+
1510 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+
1511 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+
1512 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+
1513 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+
1514 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
+
1515 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+
1516 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+
1517 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+
1518 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
+
1519 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
+
1520 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
+
1521 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
+
1522 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
+
1523 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
+
1524 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
+
1525 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
+
1526 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+
1527 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+
1528 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
+
1529 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
+
1530 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+
1531 
+
1533 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
+
1534 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
+
1535 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
+
1536 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
+
1537 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
+
1538 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
+
1539 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
+
1540 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
+
1541 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
+
1542 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
+
1543 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
+
1544 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
+
1545 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
+
1546 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
+
1547 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
+
1548 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+
1549 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+
1550 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+
1551 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+
1552 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+
1553 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+
1554 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+
1555 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+
1556 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
+
1557 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+
1558 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+
1559 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+
1560 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+
1561 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+
1562 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+
1563 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+
1564 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
1565 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
+
1566 #define ETH_MAC_BASE (ETH_BASE)
+
1567 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
+
1568 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
+
1569 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
1570 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
+
1571 
+
1573 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
+
1574 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
+
1575 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
+
1576 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
+
1577 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
+
1578 
+
1579 #if defined (STM32F40_41xxx)
+
1580 
+
1581 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
+
1582 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
+
1583 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
+
1584 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
+
1585 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
+
1586 #endif /* STM32F40_41xxx */
+
1587 
+
1588 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
1589 
+
1590 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+
1591 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+
1592 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
+
1593 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+
1594 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+
1595 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
1596 #endif /* STM32F427_437xx || STM32F429_439xx */
+
1597 
+
1598 /* Debug MCU registers base address */
+
1599 #define DBGMCU_BASE ((uint32_t )0xE0042000)
+
1600 
+
1608 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+
1609 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+
1610 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+
1611 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+
1612 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+
1613 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+
1614 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+
1615 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+
1616 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+
1617 #define RTC ((RTC_TypeDef *) RTC_BASE)
+
1618 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+
1619 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+
1620 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+
1621 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+
1622 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+
1623 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+
1624 #define USART2 ((USART_TypeDef *) USART2_BASE)
+
1625 #define USART3 ((USART_TypeDef *) USART3_BASE)
+
1626 #define UART4 ((USART_TypeDef *) UART4_BASE)
+
1627 #define UART5 ((USART_TypeDef *) UART5_BASE)
+
1628 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+
1629 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+
1630 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+
1631 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+
1632 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+
1633 #define PWR ((PWR_TypeDef *) PWR_BASE)
+
1634 #define DAC ((DAC_TypeDef *) DAC_BASE)
+
1635 #define UART7 ((USART_TypeDef *) UART7_BASE)
+
1636 #define UART8 ((USART_TypeDef *) UART8_BASE)
+
1637 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+
1638 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+
1639 #define USART1 ((USART_TypeDef *) USART1_BASE)
+
1640 #define USART6 ((USART_TypeDef *) USART6_BASE)
+
1641 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+
1642 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+
1643 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+
1644 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+
1645 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+
1646 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+
1647 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+
1648 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+
1649 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+
1650 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+
1651 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+
1652 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+
1653 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+
1654 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+
1655 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+
1656 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+
1657 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+
1658 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+
1659 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+
1660 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
1661 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+
1662 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+
1663 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+
1664 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+
1665 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+
1666 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+
1667 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+
1668 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
1669 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+
1670 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+
1671 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+
1672 #define CRC ((CRC_TypeDef *) CRC_BASE)
+
1673 #define RCC ((RCC_TypeDef *) RCC_BASE)
+
1674 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+
1675 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+
1676 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+
1677 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+
1678 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+
1679 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+
1680 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+
1681 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+
1682 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+
1683 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
1684 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+
1685 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+
1686 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+
1687 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+
1688 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+
1689 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+
1690 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+
1691 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+
1692 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
1693 #define ETH ((ETH_TypeDef *) ETH_BASE)
+
1694 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+
1695 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+
1696 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+
1697 #define HASH ((HASH_TypeDef *) HASH_BASE)
+
1698 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+
1699 #define RNG ((RNG_TypeDef *) RNG_BASE)
+
1700 
+
1701 #if defined (STM32F40_41xxx)
+
1702 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+
1703 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+
1704 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+
1705 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+
1706 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
1707 #endif /* STM32F40_41xxx */
+
1708 
+
1709 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
1710 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+
1711 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+
1712 #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+
1713 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
1714 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
1715 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
1716 #endif /* STM32F427_437xx || STM32F429_439xx */
+
1717 
+
1718 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
1719 
+
1732 /******************************************************************************/
+
1733 /* Peripheral Registers_Bits_Definition */
+
1734 /******************************************************************************/
+
1735 
+
1736 /******************************************************************************/
+
1737 /* */
+
1738 /* Analog to Digital Converter */
+
1739 /* */
+
1740 /******************************************************************************/
+
1741 /******************** Bit definition for ADC_SR register ********************/
+
1742 #define ADC_SR_AWD ((uint8_t)0x01)
+
1743 #define ADC_SR_EOC ((uint8_t)0x02)
+
1744 #define ADC_SR_JEOC ((uint8_t)0x04)
+
1745 #define ADC_SR_JSTRT ((uint8_t)0x08)
+
1746 #define ADC_SR_STRT ((uint8_t)0x10)
+
1747 #define ADC_SR_OVR ((uint8_t)0x20)
+
1749 /******************* Bit definition for ADC_CR1 register ********************/
+
1750 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
+
1751 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
+
1752 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
+
1753 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
+
1754 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
+
1755 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
+
1756 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
+
1757 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
+
1758 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
+
1759 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
+
1760 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
+
1761 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
+
1762 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
+
1763 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
+
1764 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
+
1765 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
+
1766 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
+
1767 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
+
1768 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
+
1769 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
+
1770 #define ADC_CR1_RES ((uint32_t)0x03000000)
+
1771 #define ADC_CR1_RES_0 ((uint32_t)0x01000000)
+
1772 #define ADC_CR1_RES_1 ((uint32_t)0x02000000)
+
1773 #define ADC_CR1_OVRIE ((uint32_t)0x04000000)
+
1775 /******************* Bit definition for ADC_CR2 register ********************/
+
1776 #define ADC_CR2_ADON ((uint32_t)0x00000001)
+
1777 #define ADC_CR2_CONT ((uint32_t)0x00000002)
+
1778 #define ADC_CR2_DMA ((uint32_t)0x00000100)
+
1779 #define ADC_CR2_DDS ((uint32_t)0x00000200)
+
1780 #define ADC_CR2_EOCS ((uint32_t)0x00000400)
+
1781 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
+
1782 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)
+
1783 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)
+
1784 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)
+
1785 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)
+
1786 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)
+
1787 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000)
+
1788 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)
+
1789 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)
+
1790 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000)
+
1791 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000)
+
1792 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)
+
1793 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)
+
1794 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)
+
1795 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)
+
1796 #define ADC_CR2_EXTEN ((uint32_t)0x30000000)
+
1797 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)
+
1798 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)
+
1799 #define ADC_CR2_SWSTART ((uint32_t)0x40000000)
+
1801 /****************** Bit definition for ADC_SMPR1 register *******************/
+
1802 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
+
1803 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
+
1804 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
+
1805 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
+
1806 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
+
1807 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
+
1808 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
+
1809 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
+
1810 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
+
1811 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
+
1812 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
+
1813 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
+
1814 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
+
1815 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
+
1816 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
+
1817 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
+
1818 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
+
1819 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
+
1820 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
+
1821 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
+
1822 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
+
1823 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
+
1824 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
+
1825 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
+
1826 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
+
1827 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
+
1828 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
+
1829 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
+
1830 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
+
1831 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
+
1832 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
+
1833 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
+
1834 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000)
+
1835 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000)
+
1836 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000)
+
1837 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000)
+
1839 /****************** Bit definition for ADC_SMPR2 register *******************/
+
1840 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
+
1841 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
+
1842 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
+
1843 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
+
1844 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
+
1845 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
+
1846 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
+
1847 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
+
1848 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
+
1849 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
+
1850 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
+
1851 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
+
1852 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
+
1853 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
+
1854 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
+
1855 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
+
1856 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
+
1857 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
+
1858 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
+
1859 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
+
1860 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
+
1861 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
+
1862 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
+
1863 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
+
1864 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
+
1865 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
+
1866 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
+
1867 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
+
1868 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
+
1869 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
+
1870 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
+
1871 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
+
1872 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
+
1873 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
+
1874 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
+
1875 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
+
1876 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
+
1877 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
+
1878 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
+
1879 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
+
1881 /****************** Bit definition for ADC_JOFR1 register *******************/
+
1882 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
+
1884 /****************** Bit definition for ADC_JOFR2 register *******************/
+
1885 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
+
1887 /****************** Bit definition for ADC_JOFR3 register *******************/
+
1888 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
+
1890 /****************** Bit definition for ADC_JOFR4 register *******************/
+
1891 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
+
1893 /******************* Bit definition for ADC_HTR register ********************/
+
1894 #define ADC_HTR_HT ((uint16_t)0x0FFF)
+
1896 /******************* Bit definition for ADC_LTR register ********************/
+
1897 #define ADC_LTR_LT ((uint16_t)0x0FFF)
+
1899 /******************* Bit definition for ADC_SQR1 register *******************/
+
1900 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
+
1901 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
+
1902 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
+
1903 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
+
1904 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
+
1905 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
+
1906 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
+
1907 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
+
1908 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
+
1909 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
+
1910 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
+
1911 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
+
1912 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
+
1913 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
+
1914 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
+
1915 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
+
1916 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
+
1917 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
+
1918 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
+
1919 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
+
1920 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
+
1921 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
+
1922 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
+
1923 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
+
1924 #define ADC_SQR1_L ((uint32_t)0x00F00000)
+
1925 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
+
1926 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
+
1927 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
+
1928 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
+
1930 /******************* Bit definition for ADC_SQR2 register *******************/
+
1931 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
+
1932 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
+
1933 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
+
1934 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
+
1935 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
+
1936 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
+
1937 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
+
1938 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
+
1939 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
+
1940 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
+
1941 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
+
1942 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
+
1943 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
+
1944 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
+
1945 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
+
1946 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
+
1947 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
+
1948 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
+
1949 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
+
1950 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
+
1951 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
+
1952 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
+
1953 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
+
1954 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
+
1955 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
+
1956 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
+
1957 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
+
1958 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
+
1959 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
+
1960 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
+
1961 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
+
1962 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
+
1963 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
+
1964 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
+
1965 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
+
1966 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
+
1968 /******************* Bit definition for ADC_SQR3 register *******************/
+
1969 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
+
1970 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
+
1971 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
+
1972 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
+
1973 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
+
1974 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
+
1975 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
+
1976 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
+
1977 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
+
1978 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
+
1979 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
+
1980 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
+
1981 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
+
1982 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
+
1983 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
+
1984 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
+
1985 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
+
1986 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
+
1987 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
+
1988 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
+
1989 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
+
1990 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
+
1991 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
+
1992 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
+
1993 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
+
1994 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
+
1995 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
+
1996 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
+
1997 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
+
1998 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
+
1999 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
+
2000 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
+
2001 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
+
2002 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
+
2003 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
+
2004 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
+
2006 /******************* Bit definition for ADC_JSQR register *******************/
+
2007 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
+
2008 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
+
2009 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
+
2010 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
+
2011 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
+
2012 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
+
2013 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
+
2014 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
+
2015 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
+
2016 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
+
2017 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
+
2018 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
+
2019 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
+
2020 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
+
2021 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
+
2022 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
+
2023 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
+
2024 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
+
2025 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
+
2026 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
+
2027 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
+
2028 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
+
2029 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
+
2030 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
+
2031 #define ADC_JSQR_JL ((uint32_t)0x00300000)
+
2032 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
+
2033 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
+
2035 /******************* Bit definition for ADC_JDR1 register *******************/
+
2036 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
+
2038 /******************* Bit definition for ADC_JDR2 register *******************/
+
2039 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
+
2041 /******************* Bit definition for ADC_JDR3 register *******************/
+
2042 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
+
2044 /******************* Bit definition for ADC_JDR4 register *******************/
+
2045 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
+
2047 /******************** Bit definition for ADC_DR register ********************/
+
2048 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
+
2049 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
+
2051 /******************* Bit definition for ADC_CSR register ********************/
+
2052 #define ADC_CSR_AWD1 ((uint32_t)0x00000001)
+
2053 #define ADC_CSR_EOC1 ((uint32_t)0x00000002)
+
2054 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004)
+
2055 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008)
+
2056 #define ADC_CSR_STRT1 ((uint32_t)0x00000010)
+
2057 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020)
+
2058 #define ADC_CSR_AWD2 ((uint32_t)0x00000100)
+
2059 #define ADC_CSR_EOC2 ((uint32_t)0x00000200)
+
2060 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400)
+
2061 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800)
+
2062 #define ADC_CSR_STRT2 ((uint32_t)0x00001000)
+
2063 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000)
+
2064 #define ADC_CSR_AWD3 ((uint32_t)0x00010000)
+
2065 #define ADC_CSR_EOC3 ((uint32_t)0x00020000)
+
2066 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000)
+
2067 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000)
+
2068 #define ADC_CSR_STRT3 ((uint32_t)0x00100000)
+
2069 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000)
+
2071 /******************* Bit definition for ADC_CCR register ********************/
+
2072 #define ADC_CCR_MULTI ((uint32_t)0x0000001F)
+
2073 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001)
+
2074 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002)
+
2075 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004)
+
2076 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008)
+
2077 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010)
+
2078 #define ADC_CCR_DELAY ((uint32_t)0x00000F00)
+
2079 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100)
+
2080 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200)
+
2081 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400)
+
2082 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800)
+
2083 #define ADC_CCR_DDS ((uint32_t)0x00002000)
+
2084 #define ADC_CCR_DMA ((uint32_t)0x0000C000)
+
2085 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000)
+
2086 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000)
+
2087 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000)
+
2088 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)
+
2089 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)
+
2090 #define ADC_CCR_VBATE ((uint32_t)0x00400000)
+
2091 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000)
+
2093 /******************* Bit definition for ADC_CDR register ********************/
+
2094 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF)
+
2095 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000)
+
2097 /******************************************************************************/
+
2098 /* */
+
2099 /* Controller Area Network */
+
2100 /* */
+
2101 /******************************************************************************/
+
2103 /******************* Bit definition for CAN_MCR register ********************/
+
2104 #define CAN_MCR_INRQ ((uint16_t)0x0001)
+
2105 #define CAN_MCR_SLEEP ((uint16_t)0x0002)
+
2106 #define CAN_MCR_TXFP ((uint16_t)0x0004)
+
2107 #define CAN_MCR_RFLM ((uint16_t)0x0008)
+
2108 #define CAN_MCR_NART ((uint16_t)0x0010)
+
2109 #define CAN_MCR_AWUM ((uint16_t)0x0020)
+
2110 #define CAN_MCR_ABOM ((uint16_t)0x0040)
+
2111 #define CAN_MCR_TTCM ((uint16_t)0x0080)
+
2112 #define CAN_MCR_RESET ((uint16_t)0x8000)
+
2114 /******************* Bit definition for CAN_MSR register ********************/
+
2115 #define CAN_MSR_INAK ((uint16_t)0x0001)
+
2116 #define CAN_MSR_SLAK ((uint16_t)0x0002)
+
2117 #define CAN_MSR_ERRI ((uint16_t)0x0004)
+
2118 #define CAN_MSR_WKUI ((uint16_t)0x0008)
+
2119 #define CAN_MSR_SLAKI ((uint16_t)0x0010)
+
2120 #define CAN_MSR_TXM ((uint16_t)0x0100)
+
2121 #define CAN_MSR_RXM ((uint16_t)0x0200)
+
2122 #define CAN_MSR_SAMP ((uint16_t)0x0400)
+
2123 #define CAN_MSR_RX ((uint16_t)0x0800)
+
2125 /******************* Bit definition for CAN_TSR register ********************/
+
2126 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001)
+
2127 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002)
+
2128 #define CAN_TSR_ALST0 ((uint32_t)0x00000004)
+
2129 #define CAN_TSR_TERR0 ((uint32_t)0x00000008)
+
2130 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080)
+
2131 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100)
+
2132 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200)
+
2133 #define CAN_TSR_ALST1 ((uint32_t)0x00000400)
+
2134 #define CAN_TSR_TERR1 ((uint32_t)0x00000800)
+
2135 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000)
+
2136 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000)
+
2137 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000)
+
2138 #define CAN_TSR_ALST2 ((uint32_t)0x00040000)
+
2139 #define CAN_TSR_TERR2 ((uint32_t)0x00080000)
+
2140 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
+
2141 #define CAN_TSR_CODE ((uint32_t)0x03000000)
+
2143 #define CAN_TSR_TME ((uint32_t)0x1C000000)
+
2144 #define CAN_TSR_TME0 ((uint32_t)0x04000000)
+
2145 #define CAN_TSR_TME1 ((uint32_t)0x08000000)
+
2146 #define CAN_TSR_TME2 ((uint32_t)0x10000000)
+
2148 #define CAN_TSR_LOW ((uint32_t)0xE0000000)
+
2149 #define CAN_TSR_LOW0 ((uint32_t)0x20000000)
+
2150 #define CAN_TSR_LOW1 ((uint32_t)0x40000000)
+
2151 #define CAN_TSR_LOW2 ((uint32_t)0x80000000)
+
2153 /******************* Bit definition for CAN_RF0R register *******************/
+
2154 #define CAN_RF0R_FMP0 ((uint8_t)0x03)
+
2155 #define CAN_RF0R_FULL0 ((uint8_t)0x08)
+
2156 #define CAN_RF0R_FOVR0 ((uint8_t)0x10)
+
2157 #define CAN_RF0R_RFOM0 ((uint8_t)0x20)
+
2159 /******************* Bit definition for CAN_RF1R register *******************/
+
2160 #define CAN_RF1R_FMP1 ((uint8_t)0x03)
+
2161 #define CAN_RF1R_FULL1 ((uint8_t)0x08)
+
2162 #define CAN_RF1R_FOVR1 ((uint8_t)0x10)
+
2163 #define CAN_RF1R_RFOM1 ((uint8_t)0x20)
+
2165 /******************** Bit definition for CAN_IER register *******************/
+
2166 #define CAN_IER_TMEIE ((uint32_t)0x00000001)
+
2167 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002)
+
2168 #define CAN_IER_FFIE0 ((uint32_t)0x00000004)
+
2169 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008)
+
2170 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010)
+
2171 #define CAN_IER_FFIE1 ((uint32_t)0x00000020)
+
2172 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040)
+
2173 #define CAN_IER_EWGIE ((uint32_t)0x00000100)
+
2174 #define CAN_IER_EPVIE ((uint32_t)0x00000200)
+
2175 #define CAN_IER_BOFIE ((uint32_t)0x00000400)
+
2176 #define CAN_IER_LECIE ((uint32_t)0x00000800)
+
2177 #define CAN_IER_ERRIE ((uint32_t)0x00008000)
+
2178 #define CAN_IER_WKUIE ((uint32_t)0x00010000)
+
2179 #define CAN_IER_SLKIE ((uint32_t)0x00020000)
+
2181 /******************** Bit definition for CAN_ESR register *******************/
+
2182 #define CAN_ESR_EWGF ((uint32_t)0x00000001)
+
2183 #define CAN_ESR_EPVF ((uint32_t)0x00000002)
+
2184 #define CAN_ESR_BOFF ((uint32_t)0x00000004)
+
2186 #define CAN_ESR_LEC ((uint32_t)0x00000070)
+
2187 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010)
+
2188 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020)
+
2189 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040)
+
2191 #define CAN_ESR_TEC ((uint32_t)0x00FF0000)
+
2192 #define CAN_ESR_REC ((uint32_t)0xFF000000)
+
2194 /******************* Bit definition for CAN_BTR register ********************/
+
2195 #define CAN_BTR_BRP ((uint32_t)0x000003FF)
+
2196 #define CAN_BTR_TS1 ((uint32_t)0x000F0000)
+
2197 #define CAN_BTR_TS2 ((uint32_t)0x00700000)
+
2198 #define CAN_BTR_SJW ((uint32_t)0x03000000)
+
2199 #define CAN_BTR_LBKM ((uint32_t)0x40000000)
+
2200 #define CAN_BTR_SILM ((uint32_t)0x80000000)
+
2203 /****************** Bit definition for CAN_TI0R register ********************/
+
2204 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001)
+
2205 #define CAN_TI0R_RTR ((uint32_t)0x00000002)
+
2206 #define CAN_TI0R_IDE ((uint32_t)0x00000004)
+
2207 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8)
+
2208 #define CAN_TI0R_STID ((uint32_t)0xFFE00000)
+
2210 /****************** Bit definition for CAN_TDT0R register *******************/
+
2211 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F)
+
2212 #define CAN_TDT0R_TGT ((uint32_t)0x00000100)
+
2213 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)
+
2215 /****************** Bit definition for CAN_TDL0R register *******************/
+
2216 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)
+
2217 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)
+
2218 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)
+
2219 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)
+
2221 /****************** Bit definition for CAN_TDH0R register *******************/
+
2222 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)
+
2223 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)
+
2224 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)
+
2225 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)
+
2227 /******************* Bit definition for CAN_TI1R register *******************/
+
2228 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001)
+
2229 #define CAN_TI1R_RTR ((uint32_t)0x00000002)
+
2230 #define CAN_TI1R_IDE ((uint32_t)0x00000004)
+
2231 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8)
+
2232 #define CAN_TI1R_STID ((uint32_t)0xFFE00000)
+
2234 /******************* Bit definition for CAN_TDT1R register ******************/
+
2235 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F)
+
2236 #define CAN_TDT1R_TGT ((uint32_t)0x00000100)
+
2237 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)
+
2239 /******************* Bit definition for CAN_TDL1R register ******************/
+
2240 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)
+
2241 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)
+
2242 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)
+
2243 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)
+
2245 /******************* Bit definition for CAN_TDH1R register ******************/
+
2246 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)
+
2247 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)
+
2248 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)
+
2249 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)
+
2251 /******************* Bit definition for CAN_TI2R register *******************/
+
2252 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001)
+
2253 #define CAN_TI2R_RTR ((uint32_t)0x00000002)
+
2254 #define CAN_TI2R_IDE ((uint32_t)0x00000004)
+
2255 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8)
+
2256 #define CAN_TI2R_STID ((uint32_t)0xFFE00000)
+
2258 /******************* Bit definition for CAN_TDT2R register ******************/
+
2259 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F)
+
2260 #define CAN_TDT2R_TGT ((uint32_t)0x00000100)
+
2261 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)
+
2263 /******************* Bit definition for CAN_TDL2R register ******************/
+
2264 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)
+
2265 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)
+
2266 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)
+
2267 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)
+
2269 /******************* Bit definition for CAN_TDH2R register ******************/
+
2270 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)
+
2271 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)
+
2272 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)
+
2273 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)
+
2275 /******************* Bit definition for CAN_RI0R register *******************/
+
2276 #define CAN_RI0R_RTR ((uint32_t)0x00000002)
+
2277 #define CAN_RI0R_IDE ((uint32_t)0x00000004)
+
2278 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8)
+
2279 #define CAN_RI0R_STID ((uint32_t)0xFFE00000)
+
2281 /******************* Bit definition for CAN_RDT0R register ******************/
+
2282 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F)
+
2283 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00)
+
2284 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)
+
2286 /******************* Bit definition for CAN_RDL0R register ******************/
+
2287 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)
+
2288 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)
+
2289 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
+
2290 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)
+
2292 /******************* Bit definition for CAN_RDH0R register ******************/
+
2293 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)
+
2294 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)
+
2295 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)
+
2296 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)
+
2298 /******************* Bit definition for CAN_RI1R register *******************/
+
2299 #define CAN_RI1R_RTR ((uint32_t)0x00000002)
+
2300 #define CAN_RI1R_IDE ((uint32_t)0x00000004)
+
2301 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8)
+
2302 #define CAN_RI1R_STID ((uint32_t)0xFFE00000)
+
2304 /******************* Bit definition for CAN_RDT1R register ******************/
+
2305 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F)
+
2306 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00)
+
2307 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)
+
2309 /******************* Bit definition for CAN_RDL1R register ******************/
+
2310 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)
+
2311 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)
+
2312 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)
+
2313 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)
+
2315 /******************* Bit definition for CAN_RDH1R register ******************/
+
2316 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)
+
2317 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)
+
2318 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)
+
2319 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)
+
2322 /******************* Bit definition for CAN_FMR register ********************/
+
2323 #define CAN_FMR_FINIT ((uint8_t)0x01)
+
2325 /******************* Bit definition for CAN_FM1R register *******************/
+
2326 #define CAN_FM1R_FBM ((uint16_t)0x3FFF)
+
2327 #define CAN_FM1R_FBM0 ((uint16_t)0x0001)
+
2328 #define CAN_FM1R_FBM1 ((uint16_t)0x0002)
+
2329 #define CAN_FM1R_FBM2 ((uint16_t)0x0004)
+
2330 #define CAN_FM1R_FBM3 ((uint16_t)0x0008)
+
2331 #define CAN_FM1R_FBM4 ((uint16_t)0x0010)
+
2332 #define CAN_FM1R_FBM5 ((uint16_t)0x0020)
+
2333 #define CAN_FM1R_FBM6 ((uint16_t)0x0040)
+
2334 #define CAN_FM1R_FBM7 ((uint16_t)0x0080)
+
2335 #define CAN_FM1R_FBM8 ((uint16_t)0x0100)
+
2336 #define CAN_FM1R_FBM9 ((uint16_t)0x0200)
+
2337 #define CAN_FM1R_FBM10 ((uint16_t)0x0400)
+
2338 #define CAN_FM1R_FBM11 ((uint16_t)0x0800)
+
2339 #define CAN_FM1R_FBM12 ((uint16_t)0x1000)
+
2340 #define CAN_FM1R_FBM13 ((uint16_t)0x2000)
+
2342 /******************* Bit definition for CAN_FS1R register *******************/
+
2343 #define CAN_FS1R_FSC ((uint16_t)0x3FFF)
+
2344 #define CAN_FS1R_FSC0 ((uint16_t)0x0001)
+
2345 #define CAN_FS1R_FSC1 ((uint16_t)0x0002)
+
2346 #define CAN_FS1R_FSC2 ((uint16_t)0x0004)
+
2347 #define CAN_FS1R_FSC3 ((uint16_t)0x0008)
+
2348 #define CAN_FS1R_FSC4 ((uint16_t)0x0010)
+
2349 #define CAN_FS1R_FSC5 ((uint16_t)0x0020)
+
2350 #define CAN_FS1R_FSC6 ((uint16_t)0x0040)
+
2351 #define CAN_FS1R_FSC7 ((uint16_t)0x0080)
+
2352 #define CAN_FS1R_FSC8 ((uint16_t)0x0100)
+
2353 #define CAN_FS1R_FSC9 ((uint16_t)0x0200)
+
2354 #define CAN_FS1R_FSC10 ((uint16_t)0x0400)
+
2355 #define CAN_FS1R_FSC11 ((uint16_t)0x0800)
+
2356 #define CAN_FS1R_FSC12 ((uint16_t)0x1000)
+
2357 #define CAN_FS1R_FSC13 ((uint16_t)0x2000)
+
2359 /****************** Bit definition for CAN_FFA1R register *******************/
+
2360 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF)
+
2361 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001)
+
2362 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002)
+
2363 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004)
+
2364 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008)
+
2365 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010)
+
2366 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020)
+
2367 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040)
+
2368 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080)
+
2369 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100)
+
2370 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200)
+
2371 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400)
+
2372 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800)
+
2373 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000)
+
2374 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000)
+
2376 /******************* Bit definition for CAN_FA1R register *******************/
+
2377 #define CAN_FA1R_FACT ((uint16_t)0x3FFF)
+
2378 #define CAN_FA1R_FACT0 ((uint16_t)0x0001)
+
2379 #define CAN_FA1R_FACT1 ((uint16_t)0x0002)
+
2380 #define CAN_FA1R_FACT2 ((uint16_t)0x0004)
+
2381 #define CAN_FA1R_FACT3 ((uint16_t)0x0008)
+
2382 #define CAN_FA1R_FACT4 ((uint16_t)0x0010)
+
2383 #define CAN_FA1R_FACT5 ((uint16_t)0x0020)
+
2384 #define CAN_FA1R_FACT6 ((uint16_t)0x0040)
+
2385 #define CAN_FA1R_FACT7 ((uint16_t)0x0080)
+
2386 #define CAN_FA1R_FACT8 ((uint16_t)0x0100)
+
2387 #define CAN_FA1R_FACT9 ((uint16_t)0x0200)
+
2388 #define CAN_FA1R_FACT10 ((uint16_t)0x0400)
+
2389 #define CAN_FA1R_FACT11 ((uint16_t)0x0800)
+
2390 #define CAN_FA1R_FACT12 ((uint16_t)0x1000)
+
2391 #define CAN_FA1R_FACT13 ((uint16_t)0x2000)
+
2393 /******************* Bit definition for CAN_F0R1 register *******************/
+
2394 #define CAN_F0R1_FB0 ((uint32_t)0x00000001)
+
2395 #define CAN_F0R1_FB1 ((uint32_t)0x00000002)
+
2396 #define CAN_F0R1_FB2 ((uint32_t)0x00000004)
+
2397 #define CAN_F0R1_FB3 ((uint32_t)0x00000008)
+
2398 #define CAN_F0R1_FB4 ((uint32_t)0x00000010)
+
2399 #define CAN_F0R1_FB5 ((uint32_t)0x00000020)
+
2400 #define CAN_F0R1_FB6 ((uint32_t)0x00000040)
+
2401 #define CAN_F0R1_FB7 ((uint32_t)0x00000080)
+
2402 #define CAN_F0R1_FB8 ((uint32_t)0x00000100)
+
2403 #define CAN_F0R1_FB9 ((uint32_t)0x00000200)
+
2404 #define CAN_F0R1_FB10 ((uint32_t)0x00000400)
+
2405 #define CAN_F0R1_FB11 ((uint32_t)0x00000800)
+
2406 #define CAN_F0R1_FB12 ((uint32_t)0x00001000)
+
2407 #define CAN_F0R1_FB13 ((uint32_t)0x00002000)
+
2408 #define CAN_F0R1_FB14 ((uint32_t)0x00004000)
+
2409 #define CAN_F0R1_FB15 ((uint32_t)0x00008000)
+
2410 #define CAN_F0R1_FB16 ((uint32_t)0x00010000)
+
2411 #define CAN_F0R1_FB17 ((uint32_t)0x00020000)
+
2412 #define CAN_F0R1_FB18 ((uint32_t)0x00040000)
+
2413 #define CAN_F0R1_FB19 ((uint32_t)0x00080000)
+
2414 #define CAN_F0R1_FB20 ((uint32_t)0x00100000)
+
2415 #define CAN_F0R1_FB21 ((uint32_t)0x00200000)
+
2416 #define CAN_F0R1_FB22 ((uint32_t)0x00400000)
+
2417 #define CAN_F0R1_FB23 ((uint32_t)0x00800000)
+
2418 #define CAN_F0R1_FB24 ((uint32_t)0x01000000)
+
2419 #define CAN_F0R1_FB25 ((uint32_t)0x02000000)
+
2420 #define CAN_F0R1_FB26 ((uint32_t)0x04000000)
+
2421 #define CAN_F0R1_FB27 ((uint32_t)0x08000000)
+
2422 #define CAN_F0R1_FB28 ((uint32_t)0x10000000)
+
2423 #define CAN_F0R1_FB29 ((uint32_t)0x20000000)
+
2424 #define CAN_F0R1_FB30 ((uint32_t)0x40000000)
+
2425 #define CAN_F0R1_FB31 ((uint32_t)0x80000000)
+
2427 /******************* Bit definition for CAN_F1R1 register *******************/
+
2428 #define CAN_F1R1_FB0 ((uint32_t)0x00000001)
+
2429 #define CAN_F1R1_FB1 ((uint32_t)0x00000002)
+
2430 #define CAN_F1R1_FB2 ((uint32_t)0x00000004)
+
2431 #define CAN_F1R1_FB3 ((uint32_t)0x00000008)
+
2432 #define CAN_F1R1_FB4 ((uint32_t)0x00000010)
+
2433 #define CAN_F1R1_FB5 ((uint32_t)0x00000020)
+
2434 #define CAN_F1R1_FB6 ((uint32_t)0x00000040)
+
2435 #define CAN_F1R1_FB7 ((uint32_t)0x00000080)
+
2436 #define CAN_F1R1_FB8 ((uint32_t)0x00000100)
+
2437 #define CAN_F1R1_FB9 ((uint32_t)0x00000200)
+
2438 #define CAN_F1R1_FB10 ((uint32_t)0x00000400)
+
2439 #define CAN_F1R1_FB11 ((uint32_t)0x00000800)
+
2440 #define CAN_F1R1_FB12 ((uint32_t)0x00001000)
+
2441 #define CAN_F1R1_FB13 ((uint32_t)0x00002000)
+
2442 #define CAN_F1R1_FB14 ((uint32_t)0x00004000)
+
2443 #define CAN_F1R1_FB15 ((uint32_t)0x00008000)
+
2444 #define CAN_F1R1_FB16 ((uint32_t)0x00010000)
+
2445 #define CAN_F1R1_FB17 ((uint32_t)0x00020000)
+
2446 #define CAN_F1R1_FB18 ((uint32_t)0x00040000)
+
2447 #define CAN_F1R1_FB19 ((uint32_t)0x00080000)
+
2448 #define CAN_F1R1_FB20 ((uint32_t)0x00100000)
+
2449 #define CAN_F1R1_FB21 ((uint32_t)0x00200000)
+
2450 #define CAN_F1R1_FB22 ((uint32_t)0x00400000)
+
2451 #define CAN_F1R1_FB23 ((uint32_t)0x00800000)
+
2452 #define CAN_F1R1_FB24 ((uint32_t)0x01000000)
+
2453 #define CAN_F1R1_FB25 ((uint32_t)0x02000000)
+
2454 #define CAN_F1R1_FB26 ((uint32_t)0x04000000)
+
2455 #define CAN_F1R1_FB27 ((uint32_t)0x08000000)
+
2456 #define CAN_F1R1_FB28 ((uint32_t)0x10000000)
+
2457 #define CAN_F1R1_FB29 ((uint32_t)0x20000000)
+
2458 #define CAN_F1R1_FB30 ((uint32_t)0x40000000)
+
2459 #define CAN_F1R1_FB31 ((uint32_t)0x80000000)
+
2461 /******************* Bit definition for CAN_F2R1 register *******************/
+
2462 #define CAN_F2R1_FB0 ((uint32_t)0x00000001)
+
2463 #define CAN_F2R1_FB1 ((uint32_t)0x00000002)
+
2464 #define CAN_F2R1_FB2 ((uint32_t)0x00000004)
+
2465 #define CAN_F2R1_FB3 ((uint32_t)0x00000008)
+
2466 #define CAN_F2R1_FB4 ((uint32_t)0x00000010)
+
2467 #define CAN_F2R1_FB5 ((uint32_t)0x00000020)
+
2468 #define CAN_F2R1_FB6 ((uint32_t)0x00000040)
+
2469 #define CAN_F2R1_FB7 ((uint32_t)0x00000080)
+
2470 #define CAN_F2R1_FB8 ((uint32_t)0x00000100)
+
2471 #define CAN_F2R1_FB9 ((uint32_t)0x00000200)
+
2472 #define CAN_F2R1_FB10 ((uint32_t)0x00000400)
+
2473 #define CAN_F2R1_FB11 ((uint32_t)0x00000800)
+
2474 #define CAN_F2R1_FB12 ((uint32_t)0x00001000)
+
2475 #define CAN_F2R1_FB13 ((uint32_t)0x00002000)
+
2476 #define CAN_F2R1_FB14 ((uint32_t)0x00004000)
+
2477 #define CAN_F2R1_FB15 ((uint32_t)0x00008000)
+
2478 #define CAN_F2R1_FB16 ((uint32_t)0x00010000)
+
2479 #define CAN_F2R1_FB17 ((uint32_t)0x00020000)
+
2480 #define CAN_F2R1_FB18 ((uint32_t)0x00040000)
+
2481 #define CAN_F2R1_FB19 ((uint32_t)0x00080000)
+
2482 #define CAN_F2R1_FB20 ((uint32_t)0x00100000)
+
2483 #define CAN_F2R1_FB21 ((uint32_t)0x00200000)
+
2484 #define CAN_F2R1_FB22 ((uint32_t)0x00400000)
+
2485 #define CAN_F2R1_FB23 ((uint32_t)0x00800000)
+
2486 #define CAN_F2R1_FB24 ((uint32_t)0x01000000)
+
2487 #define CAN_F2R1_FB25 ((uint32_t)0x02000000)
+
2488 #define CAN_F2R1_FB26 ((uint32_t)0x04000000)
+
2489 #define CAN_F2R1_FB27 ((uint32_t)0x08000000)
+
2490 #define CAN_F2R1_FB28 ((uint32_t)0x10000000)
+
2491 #define CAN_F2R1_FB29 ((uint32_t)0x20000000)
+
2492 #define CAN_F2R1_FB30 ((uint32_t)0x40000000)
+
2493 #define CAN_F2R1_FB31 ((uint32_t)0x80000000)
+
2495 /******************* Bit definition for CAN_F3R1 register *******************/
+
2496 #define CAN_F3R1_FB0 ((uint32_t)0x00000001)
+
2497 #define CAN_F3R1_FB1 ((uint32_t)0x00000002)
+
2498 #define CAN_F3R1_FB2 ((uint32_t)0x00000004)
+
2499 #define CAN_F3R1_FB3 ((uint32_t)0x00000008)
+
2500 #define CAN_F3R1_FB4 ((uint32_t)0x00000010)
+
2501 #define CAN_F3R1_FB5 ((uint32_t)0x00000020)
+
2502 #define CAN_F3R1_FB6 ((uint32_t)0x00000040)
+
2503 #define CAN_F3R1_FB7 ((uint32_t)0x00000080)
+
2504 #define CAN_F3R1_FB8 ((uint32_t)0x00000100)
+
2505 #define CAN_F3R1_FB9 ((uint32_t)0x00000200)
+
2506 #define CAN_F3R1_FB10 ((uint32_t)0x00000400)
+
2507 #define CAN_F3R1_FB11 ((uint32_t)0x00000800)
+
2508 #define CAN_F3R1_FB12 ((uint32_t)0x00001000)
+
2509 #define CAN_F3R1_FB13 ((uint32_t)0x00002000)
+
2510 #define CAN_F3R1_FB14 ((uint32_t)0x00004000)
+
2511 #define CAN_F3R1_FB15 ((uint32_t)0x00008000)
+
2512 #define CAN_F3R1_FB16 ((uint32_t)0x00010000)
+
2513 #define CAN_F3R1_FB17 ((uint32_t)0x00020000)
+
2514 #define CAN_F3R1_FB18 ((uint32_t)0x00040000)
+
2515 #define CAN_F3R1_FB19 ((uint32_t)0x00080000)
+
2516 #define CAN_F3R1_FB20 ((uint32_t)0x00100000)
+
2517 #define CAN_F3R1_FB21 ((uint32_t)0x00200000)
+
2518 #define CAN_F3R1_FB22 ((uint32_t)0x00400000)
+
2519 #define CAN_F3R1_FB23 ((uint32_t)0x00800000)
+
2520 #define CAN_F3R1_FB24 ((uint32_t)0x01000000)
+
2521 #define CAN_F3R1_FB25 ((uint32_t)0x02000000)
+
2522 #define CAN_F3R1_FB26 ((uint32_t)0x04000000)
+
2523 #define CAN_F3R1_FB27 ((uint32_t)0x08000000)
+
2524 #define CAN_F3R1_FB28 ((uint32_t)0x10000000)
+
2525 #define CAN_F3R1_FB29 ((uint32_t)0x20000000)
+
2526 #define CAN_F3R1_FB30 ((uint32_t)0x40000000)
+
2527 #define CAN_F3R1_FB31 ((uint32_t)0x80000000)
+
2529 /******************* Bit definition for CAN_F4R1 register *******************/
+
2530 #define CAN_F4R1_FB0 ((uint32_t)0x00000001)
+
2531 #define CAN_F4R1_FB1 ((uint32_t)0x00000002)
+
2532 #define CAN_F4R1_FB2 ((uint32_t)0x00000004)
+
2533 #define CAN_F4R1_FB3 ((uint32_t)0x00000008)
+
2534 #define CAN_F4R1_FB4 ((uint32_t)0x00000010)
+
2535 #define CAN_F4R1_FB5 ((uint32_t)0x00000020)
+
2536 #define CAN_F4R1_FB6 ((uint32_t)0x00000040)
+
2537 #define CAN_F4R1_FB7 ((uint32_t)0x00000080)
+
2538 #define CAN_F4R1_FB8 ((uint32_t)0x00000100)
+
2539 #define CAN_F4R1_FB9 ((uint32_t)0x00000200)
+
2540 #define CAN_F4R1_FB10 ((uint32_t)0x00000400)
+
2541 #define CAN_F4R1_FB11 ((uint32_t)0x00000800)
+
2542 #define CAN_F4R1_FB12 ((uint32_t)0x00001000)
+
2543 #define CAN_F4R1_FB13 ((uint32_t)0x00002000)
+
2544 #define CAN_F4R1_FB14 ((uint32_t)0x00004000)
+
2545 #define CAN_F4R1_FB15 ((uint32_t)0x00008000)
+
2546 #define CAN_F4R1_FB16 ((uint32_t)0x00010000)
+
2547 #define CAN_F4R1_FB17 ((uint32_t)0x00020000)
+
2548 #define CAN_F4R1_FB18 ((uint32_t)0x00040000)
+
2549 #define CAN_F4R1_FB19 ((uint32_t)0x00080000)
+
2550 #define CAN_F4R1_FB20 ((uint32_t)0x00100000)
+
2551 #define CAN_F4R1_FB21 ((uint32_t)0x00200000)
+
2552 #define CAN_F4R1_FB22 ((uint32_t)0x00400000)
+
2553 #define CAN_F4R1_FB23 ((uint32_t)0x00800000)
+
2554 #define CAN_F4R1_FB24 ((uint32_t)0x01000000)
+
2555 #define CAN_F4R1_FB25 ((uint32_t)0x02000000)
+
2556 #define CAN_F4R1_FB26 ((uint32_t)0x04000000)
+
2557 #define CAN_F4R1_FB27 ((uint32_t)0x08000000)
+
2558 #define CAN_F4R1_FB28 ((uint32_t)0x10000000)
+
2559 #define CAN_F4R1_FB29 ((uint32_t)0x20000000)
+
2560 #define CAN_F4R1_FB30 ((uint32_t)0x40000000)
+
2561 #define CAN_F4R1_FB31 ((uint32_t)0x80000000)
+
2563 /******************* Bit definition for CAN_F5R1 register *******************/
+
2564 #define CAN_F5R1_FB0 ((uint32_t)0x00000001)
+
2565 #define CAN_F5R1_FB1 ((uint32_t)0x00000002)
+
2566 #define CAN_F5R1_FB2 ((uint32_t)0x00000004)
+
2567 #define CAN_F5R1_FB3 ((uint32_t)0x00000008)
+
2568 #define CAN_F5R1_FB4 ((uint32_t)0x00000010)
+
2569 #define CAN_F5R1_FB5 ((uint32_t)0x00000020)
+
2570 #define CAN_F5R1_FB6 ((uint32_t)0x00000040)
+
2571 #define CAN_F5R1_FB7 ((uint32_t)0x00000080)
+
2572 #define CAN_F5R1_FB8 ((uint32_t)0x00000100)
+
2573 #define CAN_F5R1_FB9 ((uint32_t)0x00000200)
+
2574 #define CAN_F5R1_FB10 ((uint32_t)0x00000400)
+
2575 #define CAN_F5R1_FB11 ((uint32_t)0x00000800)
+
2576 #define CAN_F5R1_FB12 ((uint32_t)0x00001000)
+
2577 #define CAN_F5R1_FB13 ((uint32_t)0x00002000)
+
2578 #define CAN_F5R1_FB14 ((uint32_t)0x00004000)
+
2579 #define CAN_F5R1_FB15 ((uint32_t)0x00008000)
+
2580 #define CAN_F5R1_FB16 ((uint32_t)0x00010000)
+
2581 #define CAN_F5R1_FB17 ((uint32_t)0x00020000)
+
2582 #define CAN_F5R1_FB18 ((uint32_t)0x00040000)
+
2583 #define CAN_F5R1_FB19 ((uint32_t)0x00080000)
+
2584 #define CAN_F5R1_FB20 ((uint32_t)0x00100000)
+
2585 #define CAN_F5R1_FB21 ((uint32_t)0x00200000)
+
2586 #define CAN_F5R1_FB22 ((uint32_t)0x00400000)
+
2587 #define CAN_F5R1_FB23 ((uint32_t)0x00800000)
+
2588 #define CAN_F5R1_FB24 ((uint32_t)0x01000000)
+
2589 #define CAN_F5R1_FB25 ((uint32_t)0x02000000)
+
2590 #define CAN_F5R1_FB26 ((uint32_t)0x04000000)
+
2591 #define CAN_F5R1_FB27 ((uint32_t)0x08000000)
+
2592 #define CAN_F5R1_FB28 ((uint32_t)0x10000000)
+
2593 #define CAN_F5R1_FB29 ((uint32_t)0x20000000)
+
2594 #define CAN_F5R1_FB30 ((uint32_t)0x40000000)
+
2595 #define CAN_F5R1_FB31 ((uint32_t)0x80000000)
+
2597 /******************* Bit definition for CAN_F6R1 register *******************/
+
2598 #define CAN_F6R1_FB0 ((uint32_t)0x00000001)
+
2599 #define CAN_F6R1_FB1 ((uint32_t)0x00000002)
+
2600 #define CAN_F6R1_FB2 ((uint32_t)0x00000004)
+
2601 #define CAN_F6R1_FB3 ((uint32_t)0x00000008)
+
2602 #define CAN_F6R1_FB4 ((uint32_t)0x00000010)
+
2603 #define CAN_F6R1_FB5 ((uint32_t)0x00000020)
+
2604 #define CAN_F6R1_FB6 ((uint32_t)0x00000040)
+
2605 #define CAN_F6R1_FB7 ((uint32_t)0x00000080)
+
2606 #define CAN_F6R1_FB8 ((uint32_t)0x00000100)
+
2607 #define CAN_F6R1_FB9 ((uint32_t)0x00000200)
+
2608 #define CAN_F6R1_FB10 ((uint32_t)0x00000400)
+
2609 #define CAN_F6R1_FB11 ((uint32_t)0x00000800)
+
2610 #define CAN_F6R1_FB12 ((uint32_t)0x00001000)
+
2611 #define CAN_F6R1_FB13 ((uint32_t)0x00002000)
+
2612 #define CAN_F6R1_FB14 ((uint32_t)0x00004000)
+
2613 #define CAN_F6R1_FB15 ((uint32_t)0x00008000)
+
2614 #define CAN_F6R1_FB16 ((uint32_t)0x00010000)
+
2615 #define CAN_F6R1_FB17 ((uint32_t)0x00020000)
+
2616 #define CAN_F6R1_FB18 ((uint32_t)0x00040000)
+
2617 #define CAN_F6R1_FB19 ((uint32_t)0x00080000)
+
2618 #define CAN_F6R1_FB20 ((uint32_t)0x00100000)
+
2619 #define CAN_F6R1_FB21 ((uint32_t)0x00200000)
+
2620 #define CAN_F6R1_FB22 ((uint32_t)0x00400000)
+
2621 #define CAN_F6R1_FB23 ((uint32_t)0x00800000)
+
2622 #define CAN_F6R1_FB24 ((uint32_t)0x01000000)
+
2623 #define CAN_F6R1_FB25 ((uint32_t)0x02000000)
+
2624 #define CAN_F6R1_FB26 ((uint32_t)0x04000000)
+
2625 #define CAN_F6R1_FB27 ((uint32_t)0x08000000)
+
2626 #define CAN_F6R1_FB28 ((uint32_t)0x10000000)
+
2627 #define CAN_F6R1_FB29 ((uint32_t)0x20000000)
+
2628 #define CAN_F6R1_FB30 ((uint32_t)0x40000000)
+
2629 #define CAN_F6R1_FB31 ((uint32_t)0x80000000)
+
2631 /******************* Bit definition for CAN_F7R1 register *******************/
+
2632 #define CAN_F7R1_FB0 ((uint32_t)0x00000001)
+
2633 #define CAN_F7R1_FB1 ((uint32_t)0x00000002)
+
2634 #define CAN_F7R1_FB2 ((uint32_t)0x00000004)
+
2635 #define CAN_F7R1_FB3 ((uint32_t)0x00000008)
+
2636 #define CAN_F7R1_FB4 ((uint32_t)0x00000010)
+
2637 #define CAN_F7R1_FB5 ((uint32_t)0x00000020)
+
2638 #define CAN_F7R1_FB6 ((uint32_t)0x00000040)
+
2639 #define CAN_F7R1_FB7 ((uint32_t)0x00000080)
+
2640 #define CAN_F7R1_FB8 ((uint32_t)0x00000100)
+
2641 #define CAN_F7R1_FB9 ((uint32_t)0x00000200)
+
2642 #define CAN_F7R1_FB10 ((uint32_t)0x00000400)
+
2643 #define CAN_F7R1_FB11 ((uint32_t)0x00000800)
+
2644 #define CAN_F7R1_FB12 ((uint32_t)0x00001000)
+
2645 #define CAN_F7R1_FB13 ((uint32_t)0x00002000)
+
2646 #define CAN_F7R1_FB14 ((uint32_t)0x00004000)
+
2647 #define CAN_F7R1_FB15 ((uint32_t)0x00008000)
+
2648 #define CAN_F7R1_FB16 ((uint32_t)0x00010000)
+
2649 #define CAN_F7R1_FB17 ((uint32_t)0x00020000)
+
2650 #define CAN_F7R1_FB18 ((uint32_t)0x00040000)
+
2651 #define CAN_F7R1_FB19 ((uint32_t)0x00080000)
+
2652 #define CAN_F7R1_FB20 ((uint32_t)0x00100000)
+
2653 #define CAN_F7R1_FB21 ((uint32_t)0x00200000)
+
2654 #define CAN_F7R1_FB22 ((uint32_t)0x00400000)
+
2655 #define CAN_F7R1_FB23 ((uint32_t)0x00800000)
+
2656 #define CAN_F7R1_FB24 ((uint32_t)0x01000000)
+
2657 #define CAN_F7R1_FB25 ((uint32_t)0x02000000)
+
2658 #define CAN_F7R1_FB26 ((uint32_t)0x04000000)
+
2659 #define CAN_F7R1_FB27 ((uint32_t)0x08000000)
+
2660 #define CAN_F7R1_FB28 ((uint32_t)0x10000000)
+
2661 #define CAN_F7R1_FB29 ((uint32_t)0x20000000)
+
2662 #define CAN_F7R1_FB30 ((uint32_t)0x40000000)
+
2663 #define CAN_F7R1_FB31 ((uint32_t)0x80000000)
+
2665 /******************* Bit definition for CAN_F8R1 register *******************/
+
2666 #define CAN_F8R1_FB0 ((uint32_t)0x00000001)
+
2667 #define CAN_F8R1_FB1 ((uint32_t)0x00000002)
+
2668 #define CAN_F8R1_FB2 ((uint32_t)0x00000004)
+
2669 #define CAN_F8R1_FB3 ((uint32_t)0x00000008)
+
2670 #define CAN_F8R1_FB4 ((uint32_t)0x00000010)
+
2671 #define CAN_F8R1_FB5 ((uint32_t)0x00000020)
+
2672 #define CAN_F8R1_FB6 ((uint32_t)0x00000040)
+
2673 #define CAN_F8R1_FB7 ((uint32_t)0x00000080)
+
2674 #define CAN_F8R1_FB8 ((uint32_t)0x00000100)
+
2675 #define CAN_F8R1_FB9 ((uint32_t)0x00000200)
+
2676 #define CAN_F8R1_FB10 ((uint32_t)0x00000400)
+
2677 #define CAN_F8R1_FB11 ((uint32_t)0x00000800)
+
2678 #define CAN_F8R1_FB12 ((uint32_t)0x00001000)
+
2679 #define CAN_F8R1_FB13 ((uint32_t)0x00002000)
+
2680 #define CAN_F8R1_FB14 ((uint32_t)0x00004000)
+
2681 #define CAN_F8R1_FB15 ((uint32_t)0x00008000)
+
2682 #define CAN_F8R1_FB16 ((uint32_t)0x00010000)
+
2683 #define CAN_F8R1_FB17 ((uint32_t)0x00020000)
+
2684 #define CAN_F8R1_FB18 ((uint32_t)0x00040000)
+
2685 #define CAN_F8R1_FB19 ((uint32_t)0x00080000)
+
2686 #define CAN_F8R1_FB20 ((uint32_t)0x00100000)
+
2687 #define CAN_F8R1_FB21 ((uint32_t)0x00200000)
+
2688 #define CAN_F8R1_FB22 ((uint32_t)0x00400000)
+
2689 #define CAN_F8R1_FB23 ((uint32_t)0x00800000)
+
2690 #define CAN_F8R1_FB24 ((uint32_t)0x01000000)
+
2691 #define CAN_F8R1_FB25 ((uint32_t)0x02000000)
+
2692 #define CAN_F8R1_FB26 ((uint32_t)0x04000000)
+
2693 #define CAN_F8R1_FB27 ((uint32_t)0x08000000)
+
2694 #define CAN_F8R1_FB28 ((uint32_t)0x10000000)
+
2695 #define CAN_F8R1_FB29 ((uint32_t)0x20000000)
+
2696 #define CAN_F8R1_FB30 ((uint32_t)0x40000000)
+
2697 #define CAN_F8R1_FB31 ((uint32_t)0x80000000)
+
2699 /******************* Bit definition for CAN_F9R1 register *******************/
+
2700 #define CAN_F9R1_FB0 ((uint32_t)0x00000001)
+
2701 #define CAN_F9R1_FB1 ((uint32_t)0x00000002)
+
2702 #define CAN_F9R1_FB2 ((uint32_t)0x00000004)
+
2703 #define CAN_F9R1_FB3 ((uint32_t)0x00000008)
+
2704 #define CAN_F9R1_FB4 ((uint32_t)0x00000010)
+
2705 #define CAN_F9R1_FB5 ((uint32_t)0x00000020)
+
2706 #define CAN_F9R1_FB6 ((uint32_t)0x00000040)
+
2707 #define CAN_F9R1_FB7 ((uint32_t)0x00000080)
+
2708 #define CAN_F9R1_FB8 ((uint32_t)0x00000100)
+
2709 #define CAN_F9R1_FB9 ((uint32_t)0x00000200)
+
2710 #define CAN_F9R1_FB10 ((uint32_t)0x00000400)
+
2711 #define CAN_F9R1_FB11 ((uint32_t)0x00000800)
+
2712 #define CAN_F9R1_FB12 ((uint32_t)0x00001000)
+
2713 #define CAN_F9R1_FB13 ((uint32_t)0x00002000)
+
2714 #define CAN_F9R1_FB14 ((uint32_t)0x00004000)
+
2715 #define CAN_F9R1_FB15 ((uint32_t)0x00008000)
+
2716 #define CAN_F9R1_FB16 ((uint32_t)0x00010000)
+
2717 #define CAN_F9R1_FB17 ((uint32_t)0x00020000)
+
2718 #define CAN_F9R1_FB18 ((uint32_t)0x00040000)
+
2719 #define CAN_F9R1_FB19 ((uint32_t)0x00080000)
+
2720 #define CAN_F9R1_FB20 ((uint32_t)0x00100000)
+
2721 #define CAN_F9R1_FB21 ((uint32_t)0x00200000)
+
2722 #define CAN_F9R1_FB22 ((uint32_t)0x00400000)
+
2723 #define CAN_F9R1_FB23 ((uint32_t)0x00800000)
+
2724 #define CAN_F9R1_FB24 ((uint32_t)0x01000000)
+
2725 #define CAN_F9R1_FB25 ((uint32_t)0x02000000)
+
2726 #define CAN_F9R1_FB26 ((uint32_t)0x04000000)
+
2727 #define CAN_F9R1_FB27 ((uint32_t)0x08000000)
+
2728 #define CAN_F9R1_FB28 ((uint32_t)0x10000000)
+
2729 #define CAN_F9R1_FB29 ((uint32_t)0x20000000)
+
2730 #define CAN_F9R1_FB30 ((uint32_t)0x40000000)
+
2731 #define CAN_F9R1_FB31 ((uint32_t)0x80000000)
+
2733 /******************* Bit definition for CAN_F10R1 register ******************/
+
2734 #define CAN_F10R1_FB0 ((uint32_t)0x00000001)
+
2735 #define CAN_F10R1_FB1 ((uint32_t)0x00000002)
+
2736 #define CAN_F10R1_FB2 ((uint32_t)0x00000004)
+
2737 #define CAN_F10R1_FB3 ((uint32_t)0x00000008)
+
2738 #define CAN_F10R1_FB4 ((uint32_t)0x00000010)
+
2739 #define CAN_F10R1_FB5 ((uint32_t)0x00000020)
+
2740 #define CAN_F10R1_FB6 ((uint32_t)0x00000040)
+
2741 #define CAN_F10R1_FB7 ((uint32_t)0x00000080)
+
2742 #define CAN_F10R1_FB8 ((uint32_t)0x00000100)
+
2743 #define CAN_F10R1_FB9 ((uint32_t)0x00000200)
+
2744 #define CAN_F10R1_FB10 ((uint32_t)0x00000400)
+
2745 #define CAN_F10R1_FB11 ((uint32_t)0x00000800)
+
2746 #define CAN_F10R1_FB12 ((uint32_t)0x00001000)
+
2747 #define CAN_F10R1_FB13 ((uint32_t)0x00002000)
+
2748 #define CAN_F10R1_FB14 ((uint32_t)0x00004000)
+
2749 #define CAN_F10R1_FB15 ((uint32_t)0x00008000)
+
2750 #define CAN_F10R1_FB16 ((uint32_t)0x00010000)
+
2751 #define CAN_F10R1_FB17 ((uint32_t)0x00020000)
+
2752 #define CAN_F10R1_FB18 ((uint32_t)0x00040000)
+
2753 #define CAN_F10R1_FB19 ((uint32_t)0x00080000)
+
2754 #define CAN_F10R1_FB20 ((uint32_t)0x00100000)
+
2755 #define CAN_F10R1_FB21 ((uint32_t)0x00200000)
+
2756 #define CAN_F10R1_FB22 ((uint32_t)0x00400000)
+
2757 #define CAN_F10R1_FB23 ((uint32_t)0x00800000)
+
2758 #define CAN_F10R1_FB24 ((uint32_t)0x01000000)
+
2759 #define CAN_F10R1_FB25 ((uint32_t)0x02000000)
+
2760 #define CAN_F10R1_FB26 ((uint32_t)0x04000000)
+
2761 #define CAN_F10R1_FB27 ((uint32_t)0x08000000)
+
2762 #define CAN_F10R1_FB28 ((uint32_t)0x10000000)
+
2763 #define CAN_F10R1_FB29 ((uint32_t)0x20000000)
+
2764 #define CAN_F10R1_FB30 ((uint32_t)0x40000000)
+
2765 #define CAN_F10R1_FB31 ((uint32_t)0x80000000)
+
2767 /******************* Bit definition for CAN_F11R1 register ******************/
+
2768 #define CAN_F11R1_FB0 ((uint32_t)0x00000001)
+
2769 #define CAN_F11R1_FB1 ((uint32_t)0x00000002)
+
2770 #define CAN_F11R1_FB2 ((uint32_t)0x00000004)
+
2771 #define CAN_F11R1_FB3 ((uint32_t)0x00000008)
+
2772 #define CAN_F11R1_FB4 ((uint32_t)0x00000010)
+
2773 #define CAN_F11R1_FB5 ((uint32_t)0x00000020)
+
2774 #define CAN_F11R1_FB6 ((uint32_t)0x00000040)
+
2775 #define CAN_F11R1_FB7 ((uint32_t)0x00000080)
+
2776 #define CAN_F11R1_FB8 ((uint32_t)0x00000100)
+
2777 #define CAN_F11R1_FB9 ((uint32_t)0x00000200)
+
2778 #define CAN_F11R1_FB10 ((uint32_t)0x00000400)
+
2779 #define CAN_F11R1_FB11 ((uint32_t)0x00000800)
+
2780 #define CAN_F11R1_FB12 ((uint32_t)0x00001000)
+
2781 #define CAN_F11R1_FB13 ((uint32_t)0x00002000)
+
2782 #define CAN_F11R1_FB14 ((uint32_t)0x00004000)
+
2783 #define CAN_F11R1_FB15 ((uint32_t)0x00008000)
+
2784 #define CAN_F11R1_FB16 ((uint32_t)0x00010000)
+
2785 #define CAN_F11R1_FB17 ((uint32_t)0x00020000)
+
2786 #define CAN_F11R1_FB18 ((uint32_t)0x00040000)
+
2787 #define CAN_F11R1_FB19 ((uint32_t)0x00080000)
+
2788 #define CAN_F11R1_FB20 ((uint32_t)0x00100000)
+
2789 #define CAN_F11R1_FB21 ((uint32_t)0x00200000)
+
2790 #define CAN_F11R1_FB22 ((uint32_t)0x00400000)
+
2791 #define CAN_F11R1_FB23 ((uint32_t)0x00800000)
+
2792 #define CAN_F11R1_FB24 ((uint32_t)0x01000000)
+
2793 #define CAN_F11R1_FB25 ((uint32_t)0x02000000)
+
2794 #define CAN_F11R1_FB26 ((uint32_t)0x04000000)
+
2795 #define CAN_F11R1_FB27 ((uint32_t)0x08000000)
+
2796 #define CAN_F11R1_FB28 ((uint32_t)0x10000000)
+
2797 #define CAN_F11R1_FB29 ((uint32_t)0x20000000)
+
2798 #define CAN_F11R1_FB30 ((uint32_t)0x40000000)
+
2799 #define CAN_F11R1_FB31 ((uint32_t)0x80000000)
+
2801 /******************* Bit definition for CAN_F12R1 register ******************/
+
2802 #define CAN_F12R1_FB0 ((uint32_t)0x00000001)
+
2803 #define CAN_F12R1_FB1 ((uint32_t)0x00000002)
+
2804 #define CAN_F12R1_FB2 ((uint32_t)0x00000004)
+
2805 #define CAN_F12R1_FB3 ((uint32_t)0x00000008)
+
2806 #define CAN_F12R1_FB4 ((uint32_t)0x00000010)
+
2807 #define CAN_F12R1_FB5 ((uint32_t)0x00000020)
+
2808 #define CAN_F12R1_FB6 ((uint32_t)0x00000040)
+
2809 #define CAN_F12R1_FB7 ((uint32_t)0x00000080)
+
2810 #define CAN_F12R1_FB8 ((uint32_t)0x00000100)
+
2811 #define CAN_F12R1_FB9 ((uint32_t)0x00000200)
+
2812 #define CAN_F12R1_FB10 ((uint32_t)0x00000400)
+
2813 #define CAN_F12R1_FB11 ((uint32_t)0x00000800)
+
2814 #define CAN_F12R1_FB12 ((uint32_t)0x00001000)
+
2815 #define CAN_F12R1_FB13 ((uint32_t)0x00002000)
+
2816 #define CAN_F12R1_FB14 ((uint32_t)0x00004000)
+
2817 #define CAN_F12R1_FB15 ((uint32_t)0x00008000)
+
2818 #define CAN_F12R1_FB16 ((uint32_t)0x00010000)
+
2819 #define CAN_F12R1_FB17 ((uint32_t)0x00020000)
+
2820 #define CAN_F12R1_FB18 ((uint32_t)0x00040000)
+
2821 #define CAN_F12R1_FB19 ((uint32_t)0x00080000)
+
2822 #define CAN_F12R1_FB20 ((uint32_t)0x00100000)
+
2823 #define CAN_F12R1_FB21 ((uint32_t)0x00200000)
+
2824 #define CAN_F12R1_FB22 ((uint32_t)0x00400000)
+
2825 #define CAN_F12R1_FB23 ((uint32_t)0x00800000)
+
2826 #define CAN_F12R1_FB24 ((uint32_t)0x01000000)
+
2827 #define CAN_F12R1_FB25 ((uint32_t)0x02000000)
+
2828 #define CAN_F12R1_FB26 ((uint32_t)0x04000000)
+
2829 #define CAN_F12R1_FB27 ((uint32_t)0x08000000)
+
2830 #define CAN_F12R1_FB28 ((uint32_t)0x10000000)
+
2831 #define CAN_F12R1_FB29 ((uint32_t)0x20000000)
+
2832 #define CAN_F12R1_FB30 ((uint32_t)0x40000000)
+
2833 #define CAN_F12R1_FB31 ((uint32_t)0x80000000)
+
2835 /******************* Bit definition for CAN_F13R1 register ******************/
+
2836 #define CAN_F13R1_FB0 ((uint32_t)0x00000001)
+
2837 #define CAN_F13R1_FB1 ((uint32_t)0x00000002)
+
2838 #define CAN_F13R1_FB2 ((uint32_t)0x00000004)
+
2839 #define CAN_F13R1_FB3 ((uint32_t)0x00000008)
+
2840 #define CAN_F13R1_FB4 ((uint32_t)0x00000010)
+
2841 #define CAN_F13R1_FB5 ((uint32_t)0x00000020)
+
2842 #define CAN_F13R1_FB6 ((uint32_t)0x00000040)
+
2843 #define CAN_F13R1_FB7 ((uint32_t)0x00000080)
+
2844 #define CAN_F13R1_FB8 ((uint32_t)0x00000100)
+
2845 #define CAN_F13R1_FB9 ((uint32_t)0x00000200)
+
2846 #define CAN_F13R1_FB10 ((uint32_t)0x00000400)
+
2847 #define CAN_F13R1_FB11 ((uint32_t)0x00000800)
+
2848 #define CAN_F13R1_FB12 ((uint32_t)0x00001000)
+
2849 #define CAN_F13R1_FB13 ((uint32_t)0x00002000)
+
2850 #define CAN_F13R1_FB14 ((uint32_t)0x00004000)
+
2851 #define CAN_F13R1_FB15 ((uint32_t)0x00008000)
+
2852 #define CAN_F13R1_FB16 ((uint32_t)0x00010000)
+
2853 #define CAN_F13R1_FB17 ((uint32_t)0x00020000)
+
2854 #define CAN_F13R1_FB18 ((uint32_t)0x00040000)
+
2855 #define CAN_F13R1_FB19 ((uint32_t)0x00080000)
+
2856 #define CAN_F13R1_FB20 ((uint32_t)0x00100000)
+
2857 #define CAN_F13R1_FB21 ((uint32_t)0x00200000)
+
2858 #define CAN_F13R1_FB22 ((uint32_t)0x00400000)
+
2859 #define CAN_F13R1_FB23 ((uint32_t)0x00800000)
+
2860 #define CAN_F13R1_FB24 ((uint32_t)0x01000000)
+
2861 #define CAN_F13R1_FB25 ((uint32_t)0x02000000)
+
2862 #define CAN_F13R1_FB26 ((uint32_t)0x04000000)
+
2863 #define CAN_F13R1_FB27 ((uint32_t)0x08000000)
+
2864 #define CAN_F13R1_FB28 ((uint32_t)0x10000000)
+
2865 #define CAN_F13R1_FB29 ((uint32_t)0x20000000)
+
2866 #define CAN_F13R1_FB30 ((uint32_t)0x40000000)
+
2867 #define CAN_F13R1_FB31 ((uint32_t)0x80000000)
+
2869 /******************* Bit definition for CAN_F0R2 register *******************/
+
2870 #define CAN_F0R2_FB0 ((uint32_t)0x00000001)
+
2871 #define CAN_F0R2_FB1 ((uint32_t)0x00000002)
+
2872 #define CAN_F0R2_FB2 ((uint32_t)0x00000004)
+
2873 #define CAN_F0R2_FB3 ((uint32_t)0x00000008)
+
2874 #define CAN_F0R2_FB4 ((uint32_t)0x00000010)
+
2875 #define CAN_F0R2_FB5 ((uint32_t)0x00000020)
+
2876 #define CAN_F0R2_FB6 ((uint32_t)0x00000040)
+
2877 #define CAN_F0R2_FB7 ((uint32_t)0x00000080)
+
2878 #define CAN_F0R2_FB8 ((uint32_t)0x00000100)
+
2879 #define CAN_F0R2_FB9 ((uint32_t)0x00000200)
+
2880 #define CAN_F0R2_FB10 ((uint32_t)0x00000400)
+
2881 #define CAN_F0R2_FB11 ((uint32_t)0x00000800)
+
2882 #define CAN_F0R2_FB12 ((uint32_t)0x00001000)
+
2883 #define CAN_F0R2_FB13 ((uint32_t)0x00002000)
+
2884 #define CAN_F0R2_FB14 ((uint32_t)0x00004000)
+
2885 #define CAN_F0R2_FB15 ((uint32_t)0x00008000)
+
2886 #define CAN_F0R2_FB16 ((uint32_t)0x00010000)
+
2887 #define CAN_F0R2_FB17 ((uint32_t)0x00020000)
+
2888 #define CAN_F0R2_FB18 ((uint32_t)0x00040000)
+
2889 #define CAN_F0R2_FB19 ((uint32_t)0x00080000)
+
2890 #define CAN_F0R2_FB20 ((uint32_t)0x00100000)
+
2891 #define CAN_F0R2_FB21 ((uint32_t)0x00200000)
+
2892 #define CAN_F0R2_FB22 ((uint32_t)0x00400000)
+
2893 #define CAN_F0R2_FB23 ((uint32_t)0x00800000)
+
2894 #define CAN_F0R2_FB24 ((uint32_t)0x01000000)
+
2895 #define CAN_F0R2_FB25 ((uint32_t)0x02000000)
+
2896 #define CAN_F0R2_FB26 ((uint32_t)0x04000000)
+
2897 #define CAN_F0R2_FB27 ((uint32_t)0x08000000)
+
2898 #define CAN_F0R2_FB28 ((uint32_t)0x10000000)
+
2899 #define CAN_F0R2_FB29 ((uint32_t)0x20000000)
+
2900 #define CAN_F0R2_FB30 ((uint32_t)0x40000000)
+
2901 #define CAN_F0R2_FB31 ((uint32_t)0x80000000)
+
2903 /******************* Bit definition for CAN_F1R2 register *******************/
+
2904 #define CAN_F1R2_FB0 ((uint32_t)0x00000001)
+
2905 #define CAN_F1R2_FB1 ((uint32_t)0x00000002)
+
2906 #define CAN_F1R2_FB2 ((uint32_t)0x00000004)
+
2907 #define CAN_F1R2_FB3 ((uint32_t)0x00000008)
+
2908 #define CAN_F1R2_FB4 ((uint32_t)0x00000010)
+
2909 #define CAN_F1R2_FB5 ((uint32_t)0x00000020)
+
2910 #define CAN_F1R2_FB6 ((uint32_t)0x00000040)
+
2911 #define CAN_F1R2_FB7 ((uint32_t)0x00000080)
+
2912 #define CAN_F1R2_FB8 ((uint32_t)0x00000100)
+
2913 #define CAN_F1R2_FB9 ((uint32_t)0x00000200)
+
2914 #define CAN_F1R2_FB10 ((uint32_t)0x00000400)
+
2915 #define CAN_F1R2_FB11 ((uint32_t)0x00000800)
+
2916 #define CAN_F1R2_FB12 ((uint32_t)0x00001000)
+
2917 #define CAN_F1R2_FB13 ((uint32_t)0x00002000)
+
2918 #define CAN_F1R2_FB14 ((uint32_t)0x00004000)
+
2919 #define CAN_F1R2_FB15 ((uint32_t)0x00008000)
+
2920 #define CAN_F1R2_FB16 ((uint32_t)0x00010000)
+
2921 #define CAN_F1R2_FB17 ((uint32_t)0x00020000)
+
2922 #define CAN_F1R2_FB18 ((uint32_t)0x00040000)
+
2923 #define CAN_F1R2_FB19 ((uint32_t)0x00080000)
+
2924 #define CAN_F1R2_FB20 ((uint32_t)0x00100000)
+
2925 #define CAN_F1R2_FB21 ((uint32_t)0x00200000)
+
2926 #define CAN_F1R2_FB22 ((uint32_t)0x00400000)
+
2927 #define CAN_F1R2_FB23 ((uint32_t)0x00800000)
+
2928 #define CAN_F1R2_FB24 ((uint32_t)0x01000000)
+
2929 #define CAN_F1R2_FB25 ((uint32_t)0x02000000)
+
2930 #define CAN_F1R2_FB26 ((uint32_t)0x04000000)
+
2931 #define CAN_F1R2_FB27 ((uint32_t)0x08000000)
+
2932 #define CAN_F1R2_FB28 ((uint32_t)0x10000000)
+
2933 #define CAN_F1R2_FB29 ((uint32_t)0x20000000)
+
2934 #define CAN_F1R2_FB30 ((uint32_t)0x40000000)
+
2935 #define CAN_F1R2_FB31 ((uint32_t)0x80000000)
+
2937 /******************* Bit definition for CAN_F2R2 register *******************/
+
2938 #define CAN_F2R2_FB0 ((uint32_t)0x00000001)
+
2939 #define CAN_F2R2_FB1 ((uint32_t)0x00000002)
+
2940 #define CAN_F2R2_FB2 ((uint32_t)0x00000004)
+
2941 #define CAN_F2R2_FB3 ((uint32_t)0x00000008)
+
2942 #define CAN_F2R2_FB4 ((uint32_t)0x00000010)
+
2943 #define CAN_F2R2_FB5 ((uint32_t)0x00000020)
+
2944 #define CAN_F2R2_FB6 ((uint32_t)0x00000040)
+
2945 #define CAN_F2R2_FB7 ((uint32_t)0x00000080)
+
2946 #define CAN_F2R2_FB8 ((uint32_t)0x00000100)
+
2947 #define CAN_F2R2_FB9 ((uint32_t)0x00000200)
+
2948 #define CAN_F2R2_FB10 ((uint32_t)0x00000400)
+
2949 #define CAN_F2R2_FB11 ((uint32_t)0x00000800)
+
2950 #define CAN_F2R2_FB12 ((uint32_t)0x00001000)
+
2951 #define CAN_F2R2_FB13 ((uint32_t)0x00002000)
+
2952 #define CAN_F2R2_FB14 ((uint32_t)0x00004000)
+
2953 #define CAN_F2R2_FB15 ((uint32_t)0x00008000)
+
2954 #define CAN_F2R2_FB16 ((uint32_t)0x00010000)
+
2955 #define CAN_F2R2_FB17 ((uint32_t)0x00020000)
+
2956 #define CAN_F2R2_FB18 ((uint32_t)0x00040000)
+
2957 #define CAN_F2R2_FB19 ((uint32_t)0x00080000)
+
2958 #define CAN_F2R2_FB20 ((uint32_t)0x00100000)
+
2959 #define CAN_F2R2_FB21 ((uint32_t)0x00200000)
+
2960 #define CAN_F2R2_FB22 ((uint32_t)0x00400000)
+
2961 #define CAN_F2R2_FB23 ((uint32_t)0x00800000)
+
2962 #define CAN_F2R2_FB24 ((uint32_t)0x01000000)
+
2963 #define CAN_F2R2_FB25 ((uint32_t)0x02000000)
+
2964 #define CAN_F2R2_FB26 ((uint32_t)0x04000000)
+
2965 #define CAN_F2R2_FB27 ((uint32_t)0x08000000)
+
2966 #define CAN_F2R2_FB28 ((uint32_t)0x10000000)
+
2967 #define CAN_F2R2_FB29 ((uint32_t)0x20000000)
+
2968 #define CAN_F2R2_FB30 ((uint32_t)0x40000000)
+
2969 #define CAN_F2R2_FB31 ((uint32_t)0x80000000)
+
2971 /******************* Bit definition for CAN_F3R2 register *******************/
+
2972 #define CAN_F3R2_FB0 ((uint32_t)0x00000001)
+
2973 #define CAN_F3R2_FB1 ((uint32_t)0x00000002)
+
2974 #define CAN_F3R2_FB2 ((uint32_t)0x00000004)
+
2975 #define CAN_F3R2_FB3 ((uint32_t)0x00000008)
+
2976 #define CAN_F3R2_FB4 ((uint32_t)0x00000010)
+
2977 #define CAN_F3R2_FB5 ((uint32_t)0x00000020)
+
2978 #define CAN_F3R2_FB6 ((uint32_t)0x00000040)
+
2979 #define CAN_F3R2_FB7 ((uint32_t)0x00000080)
+
2980 #define CAN_F3R2_FB8 ((uint32_t)0x00000100)
+
2981 #define CAN_F3R2_FB9 ((uint32_t)0x00000200)
+
2982 #define CAN_F3R2_FB10 ((uint32_t)0x00000400)
+
2983 #define CAN_F3R2_FB11 ((uint32_t)0x00000800)
+
2984 #define CAN_F3R2_FB12 ((uint32_t)0x00001000)
+
2985 #define CAN_F3R2_FB13 ((uint32_t)0x00002000)
+
2986 #define CAN_F3R2_FB14 ((uint32_t)0x00004000)
+
2987 #define CAN_F3R2_FB15 ((uint32_t)0x00008000)
+
2988 #define CAN_F3R2_FB16 ((uint32_t)0x00010000)
+
2989 #define CAN_F3R2_FB17 ((uint32_t)0x00020000)
+
2990 #define CAN_F3R2_FB18 ((uint32_t)0x00040000)
+
2991 #define CAN_F3R2_FB19 ((uint32_t)0x00080000)
+
2992 #define CAN_F3R2_FB20 ((uint32_t)0x00100000)
+
2993 #define CAN_F3R2_FB21 ((uint32_t)0x00200000)
+
2994 #define CAN_F3R2_FB22 ((uint32_t)0x00400000)
+
2995 #define CAN_F3R2_FB23 ((uint32_t)0x00800000)
+
2996 #define CAN_F3R2_FB24 ((uint32_t)0x01000000)
+
2997 #define CAN_F3R2_FB25 ((uint32_t)0x02000000)
+
2998 #define CAN_F3R2_FB26 ((uint32_t)0x04000000)
+
2999 #define CAN_F3R2_FB27 ((uint32_t)0x08000000)
+
3000 #define CAN_F3R2_FB28 ((uint32_t)0x10000000)
+
3001 #define CAN_F3R2_FB29 ((uint32_t)0x20000000)
+
3002 #define CAN_F3R2_FB30 ((uint32_t)0x40000000)
+
3003 #define CAN_F3R2_FB31 ((uint32_t)0x80000000)
+
3005 /******************* Bit definition for CAN_F4R2 register *******************/
+
3006 #define CAN_F4R2_FB0 ((uint32_t)0x00000001)
+
3007 #define CAN_F4R2_FB1 ((uint32_t)0x00000002)
+
3008 #define CAN_F4R2_FB2 ((uint32_t)0x00000004)
+
3009 #define CAN_F4R2_FB3 ((uint32_t)0x00000008)
+
3010 #define CAN_F4R2_FB4 ((uint32_t)0x00000010)
+
3011 #define CAN_F4R2_FB5 ((uint32_t)0x00000020)
+
3012 #define CAN_F4R2_FB6 ((uint32_t)0x00000040)
+
3013 #define CAN_F4R2_FB7 ((uint32_t)0x00000080)
+
3014 #define CAN_F4R2_FB8 ((uint32_t)0x00000100)
+
3015 #define CAN_F4R2_FB9 ((uint32_t)0x00000200)
+
3016 #define CAN_F4R2_FB10 ((uint32_t)0x00000400)
+
3017 #define CAN_F4R2_FB11 ((uint32_t)0x00000800)
+
3018 #define CAN_F4R2_FB12 ((uint32_t)0x00001000)
+
3019 #define CAN_F4R2_FB13 ((uint32_t)0x00002000)
+
3020 #define CAN_F4R2_FB14 ((uint32_t)0x00004000)
+
3021 #define CAN_F4R2_FB15 ((uint32_t)0x00008000)
+
3022 #define CAN_F4R2_FB16 ((uint32_t)0x00010000)
+
3023 #define CAN_F4R2_FB17 ((uint32_t)0x00020000)
+
3024 #define CAN_F4R2_FB18 ((uint32_t)0x00040000)
+
3025 #define CAN_F4R2_FB19 ((uint32_t)0x00080000)
+
3026 #define CAN_F4R2_FB20 ((uint32_t)0x00100000)
+
3027 #define CAN_F4R2_FB21 ((uint32_t)0x00200000)
+
3028 #define CAN_F4R2_FB22 ((uint32_t)0x00400000)
+
3029 #define CAN_F4R2_FB23 ((uint32_t)0x00800000)
+
3030 #define CAN_F4R2_FB24 ((uint32_t)0x01000000)
+
3031 #define CAN_F4R2_FB25 ((uint32_t)0x02000000)
+
3032 #define CAN_F4R2_FB26 ((uint32_t)0x04000000)
+
3033 #define CAN_F4R2_FB27 ((uint32_t)0x08000000)
+
3034 #define CAN_F4R2_FB28 ((uint32_t)0x10000000)
+
3035 #define CAN_F4R2_FB29 ((uint32_t)0x20000000)
+
3036 #define CAN_F4R2_FB30 ((uint32_t)0x40000000)
+
3037 #define CAN_F4R2_FB31 ((uint32_t)0x80000000)
+
3039 /******************* Bit definition for CAN_F5R2 register *******************/
+
3040 #define CAN_F5R2_FB0 ((uint32_t)0x00000001)
+
3041 #define CAN_F5R2_FB1 ((uint32_t)0x00000002)
+
3042 #define CAN_F5R2_FB2 ((uint32_t)0x00000004)
+
3043 #define CAN_F5R2_FB3 ((uint32_t)0x00000008)
+
3044 #define CAN_F5R2_FB4 ((uint32_t)0x00000010)
+
3045 #define CAN_F5R2_FB5 ((uint32_t)0x00000020)
+
3046 #define CAN_F5R2_FB6 ((uint32_t)0x00000040)
+
3047 #define CAN_F5R2_FB7 ((uint32_t)0x00000080)
+
3048 #define CAN_F5R2_FB8 ((uint32_t)0x00000100)
+
3049 #define CAN_F5R2_FB9 ((uint32_t)0x00000200)
+
3050 #define CAN_F5R2_FB10 ((uint32_t)0x00000400)
+
3051 #define CAN_F5R2_FB11 ((uint32_t)0x00000800)
+
3052 #define CAN_F5R2_FB12 ((uint32_t)0x00001000)
+
3053 #define CAN_F5R2_FB13 ((uint32_t)0x00002000)
+
3054 #define CAN_F5R2_FB14 ((uint32_t)0x00004000)
+
3055 #define CAN_F5R2_FB15 ((uint32_t)0x00008000)
+
3056 #define CAN_F5R2_FB16 ((uint32_t)0x00010000)
+
3057 #define CAN_F5R2_FB17 ((uint32_t)0x00020000)
+
3058 #define CAN_F5R2_FB18 ((uint32_t)0x00040000)
+
3059 #define CAN_F5R2_FB19 ((uint32_t)0x00080000)
+
3060 #define CAN_F5R2_FB20 ((uint32_t)0x00100000)
+
3061 #define CAN_F5R2_FB21 ((uint32_t)0x00200000)
+
3062 #define CAN_F5R2_FB22 ((uint32_t)0x00400000)
+
3063 #define CAN_F5R2_FB23 ((uint32_t)0x00800000)
+
3064 #define CAN_F5R2_FB24 ((uint32_t)0x01000000)
+
3065 #define CAN_F5R2_FB25 ((uint32_t)0x02000000)
+
3066 #define CAN_F5R2_FB26 ((uint32_t)0x04000000)
+
3067 #define CAN_F5R2_FB27 ((uint32_t)0x08000000)
+
3068 #define CAN_F5R2_FB28 ((uint32_t)0x10000000)
+
3069 #define CAN_F5R2_FB29 ((uint32_t)0x20000000)
+
3070 #define CAN_F5R2_FB30 ((uint32_t)0x40000000)
+
3071 #define CAN_F5R2_FB31 ((uint32_t)0x80000000)
+
3073 /******************* Bit definition for CAN_F6R2 register *******************/
+
3074 #define CAN_F6R2_FB0 ((uint32_t)0x00000001)
+
3075 #define CAN_F6R2_FB1 ((uint32_t)0x00000002)
+
3076 #define CAN_F6R2_FB2 ((uint32_t)0x00000004)
+
3077 #define CAN_F6R2_FB3 ((uint32_t)0x00000008)
+
3078 #define CAN_F6R2_FB4 ((uint32_t)0x00000010)
+
3079 #define CAN_F6R2_FB5 ((uint32_t)0x00000020)
+
3080 #define CAN_F6R2_FB6 ((uint32_t)0x00000040)
+
3081 #define CAN_F6R2_FB7 ((uint32_t)0x00000080)
+
3082 #define CAN_F6R2_FB8 ((uint32_t)0x00000100)
+
3083 #define CAN_F6R2_FB9 ((uint32_t)0x00000200)
+
3084 #define CAN_F6R2_FB10 ((uint32_t)0x00000400)
+
3085 #define CAN_F6R2_FB11 ((uint32_t)0x00000800)
+
3086 #define CAN_F6R2_FB12 ((uint32_t)0x00001000)
+
3087 #define CAN_F6R2_FB13 ((uint32_t)0x00002000)
+
3088 #define CAN_F6R2_FB14 ((uint32_t)0x00004000)
+
3089 #define CAN_F6R2_FB15 ((uint32_t)0x00008000)
+
3090 #define CAN_F6R2_FB16 ((uint32_t)0x00010000)
+
3091 #define CAN_F6R2_FB17 ((uint32_t)0x00020000)
+
3092 #define CAN_F6R2_FB18 ((uint32_t)0x00040000)
+
3093 #define CAN_F6R2_FB19 ((uint32_t)0x00080000)
+
3094 #define CAN_F6R2_FB20 ((uint32_t)0x00100000)
+
3095 #define CAN_F6R2_FB21 ((uint32_t)0x00200000)
+
3096 #define CAN_F6R2_FB22 ((uint32_t)0x00400000)
+
3097 #define CAN_F6R2_FB23 ((uint32_t)0x00800000)
+
3098 #define CAN_F6R2_FB24 ((uint32_t)0x01000000)
+
3099 #define CAN_F6R2_FB25 ((uint32_t)0x02000000)
+
3100 #define CAN_F6R2_FB26 ((uint32_t)0x04000000)
+
3101 #define CAN_F6R2_FB27 ((uint32_t)0x08000000)
+
3102 #define CAN_F6R2_FB28 ((uint32_t)0x10000000)
+
3103 #define CAN_F6R2_FB29 ((uint32_t)0x20000000)
+
3104 #define CAN_F6R2_FB30 ((uint32_t)0x40000000)
+
3105 #define CAN_F6R2_FB31 ((uint32_t)0x80000000)
+
3107 /******************* Bit definition for CAN_F7R2 register *******************/
+
3108 #define CAN_F7R2_FB0 ((uint32_t)0x00000001)
+
3109 #define CAN_F7R2_FB1 ((uint32_t)0x00000002)
+
3110 #define CAN_F7R2_FB2 ((uint32_t)0x00000004)
+
3111 #define CAN_F7R2_FB3 ((uint32_t)0x00000008)
+
3112 #define CAN_F7R2_FB4 ((uint32_t)0x00000010)
+
3113 #define CAN_F7R2_FB5 ((uint32_t)0x00000020)
+
3114 #define CAN_F7R2_FB6 ((uint32_t)0x00000040)
+
3115 #define CAN_F7R2_FB7 ((uint32_t)0x00000080)
+
3116 #define CAN_F7R2_FB8 ((uint32_t)0x00000100)
+
3117 #define CAN_F7R2_FB9 ((uint32_t)0x00000200)
+
3118 #define CAN_F7R2_FB10 ((uint32_t)0x00000400)
+
3119 #define CAN_F7R2_FB11 ((uint32_t)0x00000800)
+
3120 #define CAN_F7R2_FB12 ((uint32_t)0x00001000)
+
3121 #define CAN_F7R2_FB13 ((uint32_t)0x00002000)
+
3122 #define CAN_F7R2_FB14 ((uint32_t)0x00004000)
+
3123 #define CAN_F7R2_FB15 ((uint32_t)0x00008000)
+
3124 #define CAN_F7R2_FB16 ((uint32_t)0x00010000)
+
3125 #define CAN_F7R2_FB17 ((uint32_t)0x00020000)
+
3126 #define CAN_F7R2_FB18 ((uint32_t)0x00040000)
+
3127 #define CAN_F7R2_FB19 ((uint32_t)0x00080000)
+
3128 #define CAN_F7R2_FB20 ((uint32_t)0x00100000)
+
3129 #define CAN_F7R2_FB21 ((uint32_t)0x00200000)
+
3130 #define CAN_F7R2_FB22 ((uint32_t)0x00400000)
+
3131 #define CAN_F7R2_FB23 ((uint32_t)0x00800000)
+
3132 #define CAN_F7R2_FB24 ((uint32_t)0x01000000)
+
3133 #define CAN_F7R2_FB25 ((uint32_t)0x02000000)
+
3134 #define CAN_F7R2_FB26 ((uint32_t)0x04000000)
+
3135 #define CAN_F7R2_FB27 ((uint32_t)0x08000000)
+
3136 #define CAN_F7R2_FB28 ((uint32_t)0x10000000)
+
3137 #define CAN_F7R2_FB29 ((uint32_t)0x20000000)
+
3138 #define CAN_F7R2_FB30 ((uint32_t)0x40000000)
+
3139 #define CAN_F7R2_FB31 ((uint32_t)0x80000000)
+
3141 /******************* Bit definition for CAN_F8R2 register *******************/
+
3142 #define CAN_F8R2_FB0 ((uint32_t)0x00000001)
+
3143 #define CAN_F8R2_FB1 ((uint32_t)0x00000002)
+
3144 #define CAN_F8R2_FB2 ((uint32_t)0x00000004)
+
3145 #define CAN_F8R2_FB3 ((uint32_t)0x00000008)
+
3146 #define CAN_F8R2_FB4 ((uint32_t)0x00000010)
+
3147 #define CAN_F8R2_FB5 ((uint32_t)0x00000020)
+
3148 #define CAN_F8R2_FB6 ((uint32_t)0x00000040)
+
3149 #define CAN_F8R2_FB7 ((uint32_t)0x00000080)
+
3150 #define CAN_F8R2_FB8 ((uint32_t)0x00000100)
+
3151 #define CAN_F8R2_FB9 ((uint32_t)0x00000200)
+
3152 #define CAN_F8R2_FB10 ((uint32_t)0x00000400)
+
3153 #define CAN_F8R2_FB11 ((uint32_t)0x00000800)
+
3154 #define CAN_F8R2_FB12 ((uint32_t)0x00001000)
+
3155 #define CAN_F8R2_FB13 ((uint32_t)0x00002000)
+
3156 #define CAN_F8R2_FB14 ((uint32_t)0x00004000)
+
3157 #define CAN_F8R2_FB15 ((uint32_t)0x00008000)
+
3158 #define CAN_F8R2_FB16 ((uint32_t)0x00010000)
+
3159 #define CAN_F8R2_FB17 ((uint32_t)0x00020000)
+
3160 #define CAN_F8R2_FB18 ((uint32_t)0x00040000)
+
3161 #define CAN_F8R2_FB19 ((uint32_t)0x00080000)
+
3162 #define CAN_F8R2_FB20 ((uint32_t)0x00100000)
+
3163 #define CAN_F8R2_FB21 ((uint32_t)0x00200000)
+
3164 #define CAN_F8R2_FB22 ((uint32_t)0x00400000)
+
3165 #define CAN_F8R2_FB23 ((uint32_t)0x00800000)
+
3166 #define CAN_F8R2_FB24 ((uint32_t)0x01000000)
+
3167 #define CAN_F8R2_FB25 ((uint32_t)0x02000000)
+
3168 #define CAN_F8R2_FB26 ((uint32_t)0x04000000)
+
3169 #define CAN_F8R2_FB27 ((uint32_t)0x08000000)
+
3170 #define CAN_F8R2_FB28 ((uint32_t)0x10000000)
+
3171 #define CAN_F8R2_FB29 ((uint32_t)0x20000000)
+
3172 #define CAN_F8R2_FB30 ((uint32_t)0x40000000)
+
3173 #define CAN_F8R2_FB31 ((uint32_t)0x80000000)
+
3175 /******************* Bit definition for CAN_F9R2 register *******************/
+
3176 #define CAN_F9R2_FB0 ((uint32_t)0x00000001)
+
3177 #define CAN_F9R2_FB1 ((uint32_t)0x00000002)
+
3178 #define CAN_F9R2_FB2 ((uint32_t)0x00000004)
+
3179 #define CAN_F9R2_FB3 ((uint32_t)0x00000008)
+
3180 #define CAN_F9R2_FB4 ((uint32_t)0x00000010)
+
3181 #define CAN_F9R2_FB5 ((uint32_t)0x00000020)
+
3182 #define CAN_F9R2_FB6 ((uint32_t)0x00000040)
+
3183 #define CAN_F9R2_FB7 ((uint32_t)0x00000080)
+
3184 #define CAN_F9R2_FB8 ((uint32_t)0x00000100)
+
3185 #define CAN_F9R2_FB9 ((uint32_t)0x00000200)
+
3186 #define CAN_F9R2_FB10 ((uint32_t)0x00000400)
+
3187 #define CAN_F9R2_FB11 ((uint32_t)0x00000800)
+
3188 #define CAN_F9R2_FB12 ((uint32_t)0x00001000)
+
3189 #define CAN_F9R2_FB13 ((uint32_t)0x00002000)
+
3190 #define CAN_F9R2_FB14 ((uint32_t)0x00004000)
+
3191 #define CAN_F9R2_FB15 ((uint32_t)0x00008000)
+
3192 #define CAN_F9R2_FB16 ((uint32_t)0x00010000)
+
3193 #define CAN_F9R2_FB17 ((uint32_t)0x00020000)
+
3194 #define CAN_F9R2_FB18 ((uint32_t)0x00040000)
+
3195 #define CAN_F9R2_FB19 ((uint32_t)0x00080000)
+
3196 #define CAN_F9R2_FB20 ((uint32_t)0x00100000)
+
3197 #define CAN_F9R2_FB21 ((uint32_t)0x00200000)
+
3198 #define CAN_F9R2_FB22 ((uint32_t)0x00400000)
+
3199 #define CAN_F9R2_FB23 ((uint32_t)0x00800000)
+
3200 #define CAN_F9R2_FB24 ((uint32_t)0x01000000)
+
3201 #define CAN_F9R2_FB25 ((uint32_t)0x02000000)
+
3202 #define CAN_F9R2_FB26 ((uint32_t)0x04000000)
+
3203 #define CAN_F9R2_FB27 ((uint32_t)0x08000000)
+
3204 #define CAN_F9R2_FB28 ((uint32_t)0x10000000)
+
3205 #define CAN_F9R2_FB29 ((uint32_t)0x20000000)
+
3206 #define CAN_F9R2_FB30 ((uint32_t)0x40000000)
+
3207 #define CAN_F9R2_FB31 ((uint32_t)0x80000000)
+
3209 /******************* Bit definition for CAN_F10R2 register ******************/
+
3210 #define CAN_F10R2_FB0 ((uint32_t)0x00000001)
+
3211 #define CAN_F10R2_FB1 ((uint32_t)0x00000002)
+
3212 #define CAN_F10R2_FB2 ((uint32_t)0x00000004)
+
3213 #define CAN_F10R2_FB3 ((uint32_t)0x00000008)
+
3214 #define CAN_F10R2_FB4 ((uint32_t)0x00000010)
+
3215 #define CAN_F10R2_FB5 ((uint32_t)0x00000020)
+
3216 #define CAN_F10R2_FB6 ((uint32_t)0x00000040)
+
3217 #define CAN_F10R2_FB7 ((uint32_t)0x00000080)
+
3218 #define CAN_F10R2_FB8 ((uint32_t)0x00000100)
+
3219 #define CAN_F10R2_FB9 ((uint32_t)0x00000200)
+
3220 #define CAN_F10R2_FB10 ((uint32_t)0x00000400)
+
3221 #define CAN_F10R2_FB11 ((uint32_t)0x00000800)
+
3222 #define CAN_F10R2_FB12 ((uint32_t)0x00001000)
+
3223 #define CAN_F10R2_FB13 ((uint32_t)0x00002000)
+
3224 #define CAN_F10R2_FB14 ((uint32_t)0x00004000)
+
3225 #define CAN_F10R2_FB15 ((uint32_t)0x00008000)
+
3226 #define CAN_F10R2_FB16 ((uint32_t)0x00010000)
+
3227 #define CAN_F10R2_FB17 ((uint32_t)0x00020000)
+
3228 #define CAN_F10R2_FB18 ((uint32_t)0x00040000)
+
3229 #define CAN_F10R2_FB19 ((uint32_t)0x00080000)
+
3230 #define CAN_F10R2_FB20 ((uint32_t)0x00100000)
+
3231 #define CAN_F10R2_FB21 ((uint32_t)0x00200000)
+
3232 #define CAN_F10R2_FB22 ((uint32_t)0x00400000)
+
3233 #define CAN_F10R2_FB23 ((uint32_t)0x00800000)
+
3234 #define CAN_F10R2_FB24 ((uint32_t)0x01000000)
+
3235 #define CAN_F10R2_FB25 ((uint32_t)0x02000000)
+
3236 #define CAN_F10R2_FB26 ((uint32_t)0x04000000)
+
3237 #define CAN_F10R2_FB27 ((uint32_t)0x08000000)
+
3238 #define CAN_F10R2_FB28 ((uint32_t)0x10000000)
+
3239 #define CAN_F10R2_FB29 ((uint32_t)0x20000000)
+
3240 #define CAN_F10R2_FB30 ((uint32_t)0x40000000)
+
3241 #define CAN_F10R2_FB31 ((uint32_t)0x80000000)
+
3243 /******************* Bit definition for CAN_F11R2 register ******************/
+
3244 #define CAN_F11R2_FB0 ((uint32_t)0x00000001)
+
3245 #define CAN_F11R2_FB1 ((uint32_t)0x00000002)
+
3246 #define CAN_F11R2_FB2 ((uint32_t)0x00000004)
+
3247 #define CAN_F11R2_FB3 ((uint32_t)0x00000008)
+
3248 #define CAN_F11R2_FB4 ((uint32_t)0x00000010)
+
3249 #define CAN_F11R2_FB5 ((uint32_t)0x00000020)
+
3250 #define CAN_F11R2_FB6 ((uint32_t)0x00000040)
+
3251 #define CAN_F11R2_FB7 ((uint32_t)0x00000080)
+
3252 #define CAN_F11R2_FB8 ((uint32_t)0x00000100)
+
3253 #define CAN_F11R2_FB9 ((uint32_t)0x00000200)
+
3254 #define CAN_F11R2_FB10 ((uint32_t)0x00000400)
+
3255 #define CAN_F11R2_FB11 ((uint32_t)0x00000800)
+
3256 #define CAN_F11R2_FB12 ((uint32_t)0x00001000)
+
3257 #define CAN_F11R2_FB13 ((uint32_t)0x00002000)
+
3258 #define CAN_F11R2_FB14 ((uint32_t)0x00004000)
+
3259 #define CAN_F11R2_FB15 ((uint32_t)0x00008000)
+
3260 #define CAN_F11R2_FB16 ((uint32_t)0x00010000)
+
3261 #define CAN_F11R2_FB17 ((uint32_t)0x00020000)
+
3262 #define CAN_F11R2_FB18 ((uint32_t)0x00040000)
+
3263 #define CAN_F11R2_FB19 ((uint32_t)0x00080000)
+
3264 #define CAN_F11R2_FB20 ((uint32_t)0x00100000)
+
3265 #define CAN_F11R2_FB21 ((uint32_t)0x00200000)
+
3266 #define CAN_F11R2_FB22 ((uint32_t)0x00400000)
+
3267 #define CAN_F11R2_FB23 ((uint32_t)0x00800000)
+
3268 #define CAN_F11R2_FB24 ((uint32_t)0x01000000)
+
3269 #define CAN_F11R2_FB25 ((uint32_t)0x02000000)
+
3270 #define CAN_F11R2_FB26 ((uint32_t)0x04000000)
+
3271 #define CAN_F11R2_FB27 ((uint32_t)0x08000000)
+
3272 #define CAN_F11R2_FB28 ((uint32_t)0x10000000)
+
3273 #define CAN_F11R2_FB29 ((uint32_t)0x20000000)
+
3274 #define CAN_F11R2_FB30 ((uint32_t)0x40000000)
+
3275 #define CAN_F11R2_FB31 ((uint32_t)0x80000000)
+
3277 /******************* Bit definition for CAN_F12R2 register ******************/
+
3278 #define CAN_F12R2_FB0 ((uint32_t)0x00000001)
+
3279 #define CAN_F12R2_FB1 ((uint32_t)0x00000002)
+
3280 #define CAN_F12R2_FB2 ((uint32_t)0x00000004)
+
3281 #define CAN_F12R2_FB3 ((uint32_t)0x00000008)
+
3282 #define CAN_F12R2_FB4 ((uint32_t)0x00000010)
+
3283 #define CAN_F12R2_FB5 ((uint32_t)0x00000020)
+
3284 #define CAN_F12R2_FB6 ((uint32_t)0x00000040)
+
3285 #define CAN_F12R2_FB7 ((uint32_t)0x00000080)
+
3286 #define CAN_F12R2_FB8 ((uint32_t)0x00000100)
+
3287 #define CAN_F12R2_FB9 ((uint32_t)0x00000200)
+
3288 #define CAN_F12R2_FB10 ((uint32_t)0x00000400)
+
3289 #define CAN_F12R2_FB11 ((uint32_t)0x00000800)
+
3290 #define CAN_F12R2_FB12 ((uint32_t)0x00001000)
+
3291 #define CAN_F12R2_FB13 ((uint32_t)0x00002000)
+
3292 #define CAN_F12R2_FB14 ((uint32_t)0x00004000)
+
3293 #define CAN_F12R2_FB15 ((uint32_t)0x00008000)
+
3294 #define CAN_F12R2_FB16 ((uint32_t)0x00010000)
+
3295 #define CAN_F12R2_FB17 ((uint32_t)0x00020000)
+
3296 #define CAN_F12R2_FB18 ((uint32_t)0x00040000)
+
3297 #define CAN_F12R2_FB19 ((uint32_t)0x00080000)
+
3298 #define CAN_F12R2_FB20 ((uint32_t)0x00100000)
+
3299 #define CAN_F12R2_FB21 ((uint32_t)0x00200000)
+
3300 #define CAN_F12R2_FB22 ((uint32_t)0x00400000)
+
3301 #define CAN_F12R2_FB23 ((uint32_t)0x00800000)
+
3302 #define CAN_F12R2_FB24 ((uint32_t)0x01000000)
+
3303 #define CAN_F12R2_FB25 ((uint32_t)0x02000000)
+
3304 #define CAN_F12R2_FB26 ((uint32_t)0x04000000)
+
3305 #define CAN_F12R2_FB27 ((uint32_t)0x08000000)
+
3306 #define CAN_F12R2_FB28 ((uint32_t)0x10000000)
+
3307 #define CAN_F12R2_FB29 ((uint32_t)0x20000000)
+
3308 #define CAN_F12R2_FB30 ((uint32_t)0x40000000)
+
3309 #define CAN_F12R2_FB31 ((uint32_t)0x80000000)
+
3311 /******************* Bit definition for CAN_F13R2 register ******************/
+
3312 #define CAN_F13R2_FB0 ((uint32_t)0x00000001)
+
3313 #define CAN_F13R2_FB1 ((uint32_t)0x00000002)
+
3314 #define CAN_F13R2_FB2 ((uint32_t)0x00000004)
+
3315 #define CAN_F13R2_FB3 ((uint32_t)0x00000008)
+
3316 #define CAN_F13R2_FB4 ((uint32_t)0x00000010)
+
3317 #define CAN_F13R2_FB5 ((uint32_t)0x00000020)
+
3318 #define CAN_F13R2_FB6 ((uint32_t)0x00000040)
+
3319 #define CAN_F13R2_FB7 ((uint32_t)0x00000080)
+
3320 #define CAN_F13R2_FB8 ((uint32_t)0x00000100)
+
3321 #define CAN_F13R2_FB9 ((uint32_t)0x00000200)
+
3322 #define CAN_F13R2_FB10 ((uint32_t)0x00000400)
+
3323 #define CAN_F13R2_FB11 ((uint32_t)0x00000800)
+
3324 #define CAN_F13R2_FB12 ((uint32_t)0x00001000)
+
3325 #define CAN_F13R2_FB13 ((uint32_t)0x00002000)
+
3326 #define CAN_F13R2_FB14 ((uint32_t)0x00004000)
+
3327 #define CAN_F13R2_FB15 ((uint32_t)0x00008000)
+
3328 #define CAN_F13R2_FB16 ((uint32_t)0x00010000)
+
3329 #define CAN_F13R2_FB17 ((uint32_t)0x00020000)
+
3330 #define CAN_F13R2_FB18 ((uint32_t)0x00040000)
+
3331 #define CAN_F13R2_FB19 ((uint32_t)0x00080000)
+
3332 #define CAN_F13R2_FB20 ((uint32_t)0x00100000)
+
3333 #define CAN_F13R2_FB21 ((uint32_t)0x00200000)
+
3334 #define CAN_F13R2_FB22 ((uint32_t)0x00400000)
+
3335 #define CAN_F13R2_FB23 ((uint32_t)0x00800000)
+
3336 #define CAN_F13R2_FB24 ((uint32_t)0x01000000)
+
3337 #define CAN_F13R2_FB25 ((uint32_t)0x02000000)
+
3338 #define CAN_F13R2_FB26 ((uint32_t)0x04000000)
+
3339 #define CAN_F13R2_FB27 ((uint32_t)0x08000000)
+
3340 #define CAN_F13R2_FB28 ((uint32_t)0x10000000)
+
3341 #define CAN_F13R2_FB29 ((uint32_t)0x20000000)
+
3342 #define CAN_F13R2_FB30 ((uint32_t)0x40000000)
+
3343 #define CAN_F13R2_FB31 ((uint32_t)0x80000000)
+
3345 /******************************************************************************/
+
3346 /* */
+
3347 /* CRC calculation unit */
+
3348 /* */
+
3349 /******************************************************************************/
+
3350 /******************* Bit definition for CRC_DR register *********************/
+
3351 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
+
3354 /******************* Bit definition for CRC_IDR register ********************/
+
3355 #define CRC_IDR_IDR ((uint8_t)0xFF)
+
3358 /******************** Bit definition for CRC_CR register ********************/
+
3359 #define CRC_CR_RESET ((uint8_t)0x01)
+
3361 /******************************************************************************/
+
3362 /* */
+
3363 /* Crypto Processor */
+
3364 /* */
+
3365 /******************************************************************************/
+
3366 /******************* Bits definition for CRYP_CR register ********************/
+
3367 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
+
3368 
+
3369 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
+
3370 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
+
3371 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
+
3372 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
+
3373 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
+
3374 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
+
3375 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
+
3376 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
+
3377 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
+
3378 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
+
3379 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
+
3380 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
+
3381 
+
3382 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
+
3383 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
+
3384 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
+
3385 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
+
3386 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
+
3387 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
+
3388 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
+
3389 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
+
3390 
+
3391 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
+
3392 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
+
3393 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
+
3394 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
+
3395 
+
3396 /****************** Bits definition for CRYP_SR register *********************/
+
3397 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
+
3398 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
+
3399 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
+
3400 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
+
3401 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
+
3402 /****************** Bits definition for CRYP_DMACR register ******************/
+
3403 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
+
3404 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
+
3405 /***************** Bits definition for CRYP_IMSCR register ******************/
+
3406 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
+
3407 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
+
3408 /****************** Bits definition for CRYP_RISR register *******************/
+
3409 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
+
3410 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
+
3411 /****************** Bits definition for CRYP_MISR register *******************/
+
3412 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
+
3413 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
+
3414 
+
3415 /******************************************************************************/
+
3416 /* */
+
3417 /* Digital to Analog Converter */
+
3418 /* */
+
3419 /******************************************************************************/
+
3420 /******************** Bit definition for DAC_CR register ********************/
+
3421 #define DAC_CR_EN1 ((uint32_t)0x00000001)
+
3422 #define DAC_CR_BOFF1 ((uint32_t)0x00000002)
+
3423 #define DAC_CR_TEN1 ((uint32_t)0x00000004)
+
3425 #define DAC_CR_TSEL1 ((uint32_t)0x00000038)
+
3426 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
+
3427 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
+
3428 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
+
3430 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0)
+
3431 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
+
3432 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
+
3434 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00)
+
3435 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
+
3436 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
+
3437 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
+
3438 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
+
3440 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000)
+
3441 #define DAC_CR_EN2 ((uint32_t)0x00010000)
+
3442 #define DAC_CR_BOFF2 ((uint32_t)0x00020000)
+
3443 #define DAC_CR_TEN2 ((uint32_t)0x00040000)
+
3445 #define DAC_CR_TSEL2 ((uint32_t)0x00380000)
+
3446 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
+
3447 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
+
3448 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
+
3450 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000)
+
3451 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
+
3452 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
+
3454 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000)
+
3455 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
+
3456 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
+
3457 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
+
3458 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
+
3460 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000)
+
3462 /***************** Bit definition for DAC_SWTRIGR register ******************/
+
3463 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
+
3464 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
+
3466 /***************** Bit definition for DAC_DHR12R1 register ******************/
+
3467 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
+
3469 /***************** Bit definition for DAC_DHR12L1 register ******************/
+
3470 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
+
3472 /****************** Bit definition for DAC_DHR8R1 register ******************/
+
3473 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
+
3475 /***************** Bit definition for DAC_DHR12R2 register ******************/
+
3476 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
+
3478 /***************** Bit definition for DAC_DHR12L2 register ******************/
+
3479 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
+
3481 /****************** Bit definition for DAC_DHR8R2 register ******************/
+
3482 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
+
3484 /***************** Bit definition for DAC_DHR12RD register ******************/
+
3485 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
+
3486 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
+
3488 /***************** Bit definition for DAC_DHR12LD register ******************/
+
3489 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
+
3490 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
+
3492 /****************** Bit definition for DAC_DHR8RD register ******************/
+
3493 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
+
3494 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
+
3496 /******************* Bit definition for DAC_DOR1 register *******************/
+
3497 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
+
3499 /******************* Bit definition for DAC_DOR2 register *******************/
+
3500 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
+
3502 /******************** Bit definition for DAC_SR register ********************/
+
3503 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
+
3504 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
+
3506 /******************************************************************************/
+
3507 /* */
+
3508 /* Debug MCU */
+
3509 /* */
+
3510 /******************************************************************************/
+
3511 
+
3512 /******************************************************************************/
+
3513 /* */
+
3514 /* DCMI */
+
3515 /* */
+
3516 /******************************************************************************/
+
3517 /******************** Bits definition for DCMI_CR register ******************/
+
3518 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
+
3519 #define DCMI_CR_CM ((uint32_t)0x00000002)
+
3520 #define DCMI_CR_CROP ((uint32_t)0x00000004)
+
3521 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
+
3522 #define DCMI_CR_ESS ((uint32_t)0x00000010)
+
3523 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
+
3524 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
+
3525 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
+
3526 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
+
3527 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
+
3528 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
+
3529 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
+
3530 #define DCMI_CR_CRE ((uint32_t)0x00001000)
+
3531 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
+
3532 
+
3533 /******************** Bits definition for DCMI_SR register ******************/
+
3534 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
+
3535 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
+
3536 #define DCMI_SR_FNE ((uint32_t)0x00000004)
+
3537 
+
3538 /******************** Bits definition for DCMI_RISR register ****************/
+
3539 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
+
3540 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
+
3541 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
+
3542 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
+
3543 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
+
3544 
+
3545 /******************** Bits definition for DCMI_IER register *****************/
+
3546 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
+
3547 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
+
3548 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
+
3549 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
+
3550 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
+
3551 
+
3552 /******************** Bits definition for DCMI_MISR register ****************/
+
3553 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
+
3554 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
+
3555 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
+
3556 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
+
3557 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
+
3558 
+
3559 /******************** Bits definition for DCMI_ICR register *****************/
+
3560 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
+
3561 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
+
3562 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
+
3563 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
+
3564 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
+
3565 
+
3566 /******************************************************************************/
+
3567 /* */
+
3568 /* DMA Controller */
+
3569 /* */
+
3570 /******************************************************************************/
+
3571 /******************** Bits definition for DMA_SxCR register *****************/
+
3572 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
+
3573 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
+
3574 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
+
3575 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
+
3576 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
+
3577 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
+
3578 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
+
3579 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
+
3580 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
+
3581 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
+
3582 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
+
3583 #define DMA_SxCR_CT ((uint32_t)0x00080000)
+
3584 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
+
3585 #define DMA_SxCR_PL ((uint32_t)0x00030000)
+
3586 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
+
3587 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
+
3588 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
+
3589 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
+
3590 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
+
3591 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
+
3592 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
+
3593 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
+
3594 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
+
3595 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
+
3596 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
+
3597 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
+
3598 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
+
3599 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
+
3600 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
+
3601 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
+
3602 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
+
3603 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
+
3604 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
+
3605 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
+
3606 #define DMA_SxCR_EN ((uint32_t)0x00000001)
+
3607 
+
3608 /******************** Bits definition for DMA_SxCNDTR register **************/
+
3609 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
+
3610 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
+
3611 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
+
3612 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
+
3613 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
+
3614 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
+
3615 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
+
3616 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
+
3617 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
+
3618 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
+
3619 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
+
3620 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
+
3621 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
+
3622 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
+
3623 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
+
3624 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
+
3625 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
+
3626 
+
3627 /******************** Bits definition for DMA_SxFCR register ****************/
+
3628 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
+
3629 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
+
3630 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
+
3631 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
+
3632 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
+
3633 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
+
3634 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
+
3635 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
+
3636 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
+
3637 
+
3638 /******************** Bits definition for DMA_LISR register *****************/
+
3639 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
+
3640 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
+
3641 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
+
3642 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
+
3643 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
+
3644 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
+
3645 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
+
3646 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
+
3647 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
+
3648 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
+
3649 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
+
3650 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
+
3651 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
+
3652 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
+
3653 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
+
3654 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
+
3655 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
+
3656 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
+
3657 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
+
3658 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
+
3659 
+
3660 /******************** Bits definition for DMA_HISR register *****************/
+
3661 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
+
3662 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
+
3663 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
+
3664 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
+
3665 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
+
3666 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
+
3667 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
+
3668 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
+
3669 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
+
3670 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
+
3671 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
+
3672 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
+
3673 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
+
3674 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
+
3675 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
+
3676 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
+
3677 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
+
3678 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
+
3679 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
+
3680 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
+
3681 
+
3682 /******************** Bits definition for DMA_LIFCR register ****************/
+
3683 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
+
3684 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
+
3685 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
+
3686 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
+
3687 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
+
3688 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
+
3689 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
+
3690 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
+
3691 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
+
3692 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
+
3693 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
+
3694 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
+
3695 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
+
3696 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
+
3697 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
+
3698 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
+
3699 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
+
3700 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
+
3701 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
+
3702 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
+
3703 
+
3704 /******************** Bits definition for DMA_HIFCR register ****************/
+
3705 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
+
3706 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
+
3707 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
+
3708 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
+
3709 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
+
3710 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
+
3711 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
+
3712 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
+
3713 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
+
3714 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
+
3715 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
+
3716 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
+
3717 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
+
3718 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
+
3719 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
+
3720 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
+
3721 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
+
3722 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
+
3723 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
+
3724 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
+
3725 
+
3726 /******************************************************************************/
+
3727 /* */
+
3728 /* AHB Master DMA2D Controller (DMA2D) */
+
3729 /* */
+
3730 /******************************************************************************/
+
3731 
+
3732 /******************** Bit definition for DMA2D_CR register ******************/
+
3733 
+
3734 #define DMA2D_CR_START ((uint32_t)0x00000001)
+
3735 #define DMA2D_CR_SUSP ((uint32_t)0x00000002)
+
3736 #define DMA2D_CR_ABORT ((uint32_t)0x00000004)
+
3737 #define DMA2D_CR_TEIE ((uint32_t)0x00000100)
+
3738 #define DMA2D_CR_TCIE ((uint32_t)0x00000200)
+
3739 #define DMA2D_CR_TWIE ((uint32_t)0x00000400)
+
3740 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800)
+
3741 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000)
+
3742 #define DMA2D_CR_CEIE ((uint32_t)0x00002000)
+
3743 #define DMA2D_CR_MODE ((uint32_t)0x00030000)
+
3745 /******************** Bit definition for DMA2D_ISR register *****************/
+
3746 
+
3747 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001)
+
3748 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002)
+
3749 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004)
+
3750 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008)
+
3751 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010)
+
3752 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020)
+
3754 /******************** Bit definition for DMA2D_IFSR register ****************/
+
3755 
+
3756 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001)
+
3757 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002)
+
3758 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004)
+
3759 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008)
+
3760 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010)
+
3761 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020)
+
3763 /******************** Bit definition for DMA2D_FGMAR register ***************/
+
3764 
+
3765 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF)
+
3767 /******************** Bit definition for DMA2D_FGOR register ****************/
+
3768 
+
3769 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF)
+
3771 /******************** Bit definition for DMA2D_BGMAR register ***************/
+
3772 
+
3773 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF)
+
3775 /******************** Bit definition for DMA2D_BGOR register ****************/
+
3776 
+
3777 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF)
+
3779 /******************** Bit definition for DMA2D_FGPFCCR register *************/
+
3780 
+
3781 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F)
+
3782 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010)
+
3783 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020)
+
3784 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00)
+
3785 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000)
+
3786 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000)
+
3788 /******************** Bit definition for DMA2D_FGCOLR register **************/
+
3789 
+
3790 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF)
+
3791 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00)
+
3792 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000)
+
3794 /******************** Bit definition for DMA2D_BGPFCCR register *************/
+
3795 
+
3796 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F)
+
3797 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010)
+
3798 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020)
+
3799 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00)
+
3800 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000)
+
3801 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000)
+
3803 /******************** Bit definition for DMA2D_BGCOLR register **************/
+
3804 
+
3805 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF)
+
3806 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00)
+
3807 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000)
+
3809 /******************** Bit definition for DMA2D_FGCMAR register **************/
+
3810 
+
3811 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF)
+
3813 /******************** Bit definition for DMA2D_BGCMAR register **************/
+
3814 
+
3815 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF)
+
3817 /******************** Bit definition for DMA2D_OPFCCR register **************/
+
3818 
+
3819 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007)
+
3821 /******************** Bit definition for DMA2D_OCOLR register ***************/
+
3822 
+
3825 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF)
+
3826 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00)
+
3827 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000)
+
3828 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000)
+
3831 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F)
+
3832 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0)
+
3833 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800)
+
3836 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F)
+
3837 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0)
+
3838 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00)
+
3839 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000)
+
3842 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F)
+
3843 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0)
+
3844 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00)
+
3845 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000)
+
3847 /******************** Bit definition for DMA2D_OMAR register ****************/
+
3848 
+
3849 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF)
+
3851 /******************** Bit definition for DMA2D_OOR register *****************/
+
3852 
+
3853 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF)
+
3855 /******************** Bit definition for DMA2D_NLR register *****************/
+
3856 
+
3857 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF)
+
3858 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000)
+
3860 /******************** Bit definition for DMA2D_LWR register *****************/
+
3861 
+
3862 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF)
+
3864 /******************** Bit definition for DMA2D_AMTCR register ***************/
+
3865 
+
3866 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001)
+
3867 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00)
+
3871 /******************** Bit definition for DMA2D_FGCLUT register **************/
+
3872 
+
3873 /******************** Bit definition for DMA2D_BGCLUT register **************/
+
3874 
+
3875 
+
3876 /******************************************************************************/
+
3877 /* */
+
3878 /* External Interrupt/Event Controller */
+
3879 /* */
+
3880 /******************************************************************************/
+
3881 /******************* Bit definition for EXTI_IMR register *******************/
+
3882 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
+
3883 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
+
3884 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
+
3885 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
+
3886 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
+
3887 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
+
3888 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
+
3889 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
+
3890 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
+
3891 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
+
3892 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
+
3893 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
+
3894 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
+
3895 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
+
3896 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
+
3897 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
+
3898 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
+
3899 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
+
3900 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
+
3901 #define EXTI_IMR_MR19 ((uint32_t)0x00080000)
+
3903 /******************* Bit definition for EXTI_EMR register *******************/
+
3904 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
+
3905 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
+
3906 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
+
3907 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
+
3908 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
+
3909 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
+
3910 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
+
3911 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
+
3912 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
+
3913 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
+
3914 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
+
3915 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
+
3916 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
+
3917 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
+
3918 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
+
3919 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
+
3920 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
+
3921 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
+
3922 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
+
3923 #define EXTI_EMR_MR19 ((uint32_t)0x00080000)
+
3925 /****************** Bit definition for EXTI_RTSR register *******************/
+
3926 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
+
3927 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
+
3928 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
+
3929 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
+
3930 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
+
3931 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
+
3932 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
+
3933 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
+
3934 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
+
3935 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
+
3936 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
+
3937 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
+
3938 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
+
3939 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
+
3940 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
+
3941 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
+
3942 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
+
3943 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
+
3944 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
+
3945 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000)
+
3947 /****************** Bit definition for EXTI_FTSR register *******************/
+
3948 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
+
3949 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
+
3950 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
+
3951 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
+
3952 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
+
3953 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
+
3954 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
+
3955 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
+
3956 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
+
3957 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
+
3958 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
+
3959 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
+
3960 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
+
3961 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
+
3962 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
+
3963 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
+
3964 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
+
3965 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
+
3966 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
+
3967 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000)
+
3969 /****************** Bit definition for EXTI_SWIER register ******************/
+
3970 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
+
3971 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
+
3972 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
+
3973 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
+
3974 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
+
3975 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
+
3976 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
+
3977 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
+
3978 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
+
3979 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
+
3980 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
+
3981 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
+
3982 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
+
3983 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
+
3984 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
+
3985 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
+
3986 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
+
3987 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
+
3988 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
+
3989 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
+
3991 /******************* Bit definition for EXTI_PR register ********************/
+
3992 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
+
3993 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
+
3994 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
+
3995 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
+
3996 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
+
3997 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
+
3998 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
+
3999 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
+
4000 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
+
4001 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
+
4002 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
+
4003 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
+
4004 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
+
4005 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
+
4006 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
+
4007 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
+
4008 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
+
4009 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
+
4010 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
+
4011 #define EXTI_PR_PR19 ((uint32_t)0x00080000)
+
4013 /******************************************************************************/
+
4014 /* */
+
4015 /* FLASH */
+
4016 /* */
+
4017 /******************************************************************************/
+
4018 /******************* Bits definition for FLASH_ACR register *****************/
+
4019 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
+
4020 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
+
4021 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
+
4022 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
+
4023 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
+
4024 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
+
4025 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
+
4026 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
+
4027 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
+
4028 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
+
4029 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
+
4030 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
+
4031 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
+
4032 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
+
4033 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
+
4034 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
+
4035 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
+
4036 
+
4037 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
+
4038 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
+
4039 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
+
4040 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
+
4041 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
+
4042 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+
4043 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
+
4044 
+
4045 /******************* Bits definition for FLASH_SR register ******************/
+
4046 #define FLASH_SR_EOP ((uint32_t)0x00000001)
+
4047 #define FLASH_SR_SOP ((uint32_t)0x00000002)
+
4048 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
+
4049 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
+
4050 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
+
4051 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
+
4052 #define FLASH_SR_BSY ((uint32_t)0x00010000)
+
4053 
+
4054 /******************* Bits definition for FLASH_CR register ******************/
+
4055 #define FLASH_CR_PG ((uint32_t)0x00000001)
+
4056 #define FLASH_CR_SER ((uint32_t)0x00000002)
+
4057 #define FLASH_CR_MER ((uint32_t)0x00000004)
+
4058 #define FLASH_CR_MER1 FLASH_CR_MER
+
4059 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
+
4060 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
+
4061 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
+
4062 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
+
4063 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
+
4064 #define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
+
4065 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
+
4066 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
+
4067 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
+
4068 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
+
4069 #define FLASH_CR_STRT ((uint32_t)0x00010000)
+
4070 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
+
4071 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
+
4072 
+
4073 /******************* Bits definition for FLASH_OPTCR register ***************/
+
4074 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
+
4075 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
+
4076 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
+
4077 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
+
4078 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
+
4079 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
+
4080 
+
4081 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
+
4082 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
+
4083 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
+
4084 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
+
4085 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
+
4086 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
+
4087 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
+
4088 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
+
4089 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
+
4090 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
+
4091 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
+
4092 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
+
4093 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
+
4094 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
+
4095 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
+
4096 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
+
4097 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
+
4098 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
+
4099 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
+
4100 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
+
4101 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
+
4102 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
+
4103 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
+
4104 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
+
4105 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
+
4106 
+
4107 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
+
4108 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
+
4109 
+
4110 /****************** Bits definition for FLASH_OPTCR1 register ***************/
+
4111 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
+
4112 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
+
4113 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
+
4114 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
+
4115 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
+
4116 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
+
4117 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
+
4118 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
+
4119 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
+
4120 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
+
4121 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
+
4122 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
+
4123 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
+
4124 
+
4125 #if defined (STM32F40_41xxx)
+
4126 /******************************************************************************/
+
4127 /* */
+
4128 /* Flexible Static Memory Controller */
+
4129 /* */
+
4130 /******************************************************************************/
+
4131 /****************** Bit definition for FSMC_BCR1 register *******************/
+
4132 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
+
4133 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
+
4135 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
+
4136 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
+
4137 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
+
4139 #define FSMC_BCR1_MWID ((uint32_t)0x00000030)
+
4140 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
+
4141 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
+
4143 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
+
4144 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
+
4145 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
+
4146 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
+
4147 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
+
4148 #define FSMC_BCR1_WREN ((uint32_t)0x00001000)
+
4149 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
+
4150 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
+
4151 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
+
4152 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
+
4154 /****************** Bit definition for FSMC_BCR2 register *******************/
+
4155 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
+
4156 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
+
4158 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
+
4159 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
+
4160 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
+
4162 #define FSMC_BCR2_MWID ((uint32_t)0x00000030)
+
4163 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
+
4164 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
+
4166 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
+
4167 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
+
4168 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
+
4169 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
+
4170 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
+
4171 #define FSMC_BCR2_WREN ((uint32_t)0x00001000)
+
4172 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
+
4173 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
+
4174 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
+
4175 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
+
4177 /****************** Bit definition for FSMC_BCR3 register *******************/
+
4178 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
+
4179 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
+
4181 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
+
4182 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
+
4183 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
+
4185 #define FSMC_BCR3_MWID ((uint32_t)0x00000030)
+
4186 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
+
4187 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
+
4189 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
+
4190 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
+
4191 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
+
4192 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
+
4193 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
+
4194 #define FSMC_BCR3_WREN ((uint32_t)0x00001000)
+
4195 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
+
4196 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
+
4197 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
+
4198 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
+
4200 /****************** Bit definition for FSMC_BCR4 register *******************/
+
4201 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
+
4202 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
+
4204 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
+
4205 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
+
4206 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
+
4208 #define FSMC_BCR4_MWID ((uint32_t)0x00000030)
+
4209 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
+
4210 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
+
4212 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
+
4213 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
+
4214 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
+
4215 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
+
4216 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
+
4217 #define FSMC_BCR4_WREN ((uint32_t)0x00001000)
+
4218 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
+
4219 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
+
4220 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
+
4221 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
+
4223 /****************** Bit definition for FSMC_BTR1 register ******************/
+
4224 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
+
4225 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
+
4226 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
+
4227 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
+
4228 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
+
4230 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
+
4231 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
+
4232 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
+
4233 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
+
4234 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
+
4236 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
+
4237 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
+
4238 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
+
4239 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
+
4240 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
+
4242 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
+
4243 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
+
4244 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
+
4245 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
+
4246 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
+
4248 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
+
4249 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
+
4250 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
+
4251 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
+
4252 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
+
4254 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
+
4255 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
+
4256 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
+
4257 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
+
4258 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
+
4260 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
+
4261 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
+
4262 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
+
4264 /****************** Bit definition for FSMC_BTR2 register *******************/
+
4265 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
+
4266 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
+
4267 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
+
4268 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
+
4269 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
+
4271 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
+
4272 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
+
4273 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
+
4274 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
+
4275 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
+
4277 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
+
4278 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
+
4279 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
+
4280 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
+
4281 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
+
4283 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
+
4284 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
+
4285 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
+
4286 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
+
4287 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
+
4289 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
+
4290 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
+
4291 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
+
4292 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
+
4293 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
+
4295 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
+
4296 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
+
4297 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
+
4298 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
+
4299 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
+
4301 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
+
4302 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
+
4303 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
+
4305 /******************* Bit definition for FSMC_BTR3 register *******************/
+
4306 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
+
4307 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
+
4308 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
+
4309 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
+
4310 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
+
4312 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
+
4313 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
+
4314 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
+
4315 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
+
4316 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
+
4318 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
+
4319 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
+
4320 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
+
4321 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
+
4322 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
+
4324 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
+
4325 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
+
4326 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
+
4327 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
+
4328 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
+
4330 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
+
4331 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
+
4332 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
+
4333 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
+
4334 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
+
4336 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
+
4337 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
+
4338 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
+
4339 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
+
4340 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
+
4342 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
+
4343 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
+
4344 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
+
4346 /****************** Bit definition for FSMC_BTR4 register *******************/
+
4347 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
+
4348 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
+
4349 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
+
4350 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
+
4351 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
+
4353 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
+
4354 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
+
4355 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
+
4356 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
+
4357 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
+
4359 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
+
4360 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
+
4361 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
+
4362 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
+
4363 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
+
4365 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
+
4366 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
+
4367 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
+
4368 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
+
4369 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
+
4371 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
+
4372 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
+
4373 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
+
4374 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
+
4375 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
+
4377 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
+
4378 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
+
4379 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
+
4380 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
+
4381 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
+
4383 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
+
4384 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
+
4385 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
+
4387 /****************** Bit definition for FSMC_BWTR1 register ******************/
+
4388 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
+
4389 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
+
4390 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
+
4391 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
+
4392 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
+
4394 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
+
4395 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
+
4396 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
+
4397 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
+
4398 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
+
4400 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
+
4401 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
+
4402 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
+
4403 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
+
4404 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
+
4406 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
+
4407 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
+
4408 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
+
4409 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
+
4410 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
+
4412 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
+
4413 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
+
4414 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
+
4415 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
+
4416 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
+
4418 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
+
4419 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
+
4420 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
+
4422 /****************** Bit definition for FSMC_BWTR2 register ******************/
+
4423 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
+
4424 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
+
4425 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
+
4426 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
+
4427 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
+
4429 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
+
4430 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
+
4431 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
+
4432 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
+
4433 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
+
4435 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
+
4436 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
+
4437 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
+
4438 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
+
4439 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
+
4441 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
+
4442 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
+
4443 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
+
4444 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
+
4445 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
+
4447 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
+
4448 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
+
4449 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
+
4450 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
+
4451 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
+
4453 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
+
4454 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
+
4455 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
+
4457 /****************** Bit definition for FSMC_BWTR3 register ******************/
+
4458 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
+
4459 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
+
4460 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
+
4461 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
+
4462 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
+
4464 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
+
4465 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
+
4466 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
+
4467 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
+
4468 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
+
4470 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
+
4471 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
+
4472 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
+
4473 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
+
4474 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
+
4476 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
+
4477 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
+
4478 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
+
4479 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
+
4480 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
+
4482 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
+
4483 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
+
4484 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
+
4485 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
+
4486 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
+
4488 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
+
4489 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
+
4490 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
+
4492 /****************** Bit definition for FSMC_BWTR4 register ******************/
+
4493 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
+
4494 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
+
4495 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
+
4496 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
+
4497 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
+
4499 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
+
4500 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
+
4501 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
+
4502 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
+
4503 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
+
4505 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
+
4506 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
+
4507 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
+
4508 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
+
4509 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
+
4511 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
+
4512 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
+
4513 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
+
4514 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
+
4515 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
+
4517 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
+
4518 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
+
4519 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
+
4520 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
+
4521 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
+
4523 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
+
4524 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
+
4525 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
+
4527 /****************** Bit definition for FSMC_PCR2 register *******************/
+
4528 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)
+
4529 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004)
+
4530 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008)
+
4532 #define FSMC_PCR2_PWID ((uint32_t)0x00000030)
+
4533 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)
+
4534 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)
+
4536 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040)
+
4538 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00)
+
4539 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
+
4540 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
+
4541 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
+
4542 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
+
4544 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000)
+
4545 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)
+
4546 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)
+
4547 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)
+
4548 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)
+
4550 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)
+
4551 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
+
4552 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
+
4553 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
+
4555 /****************** Bit definition for FSMC_PCR3 register *******************/
+
4556 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)
+
4557 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004)
+
4558 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008)
+
4560 #define FSMC_PCR3_PWID ((uint32_t)0x00000030)
+
4561 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)
+
4562 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)
+
4564 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040)
+
4566 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00)
+
4567 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
+
4568 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
+
4569 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
+
4570 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
+
4572 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000)
+
4573 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)
+
4574 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)
+
4575 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)
+
4576 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)
+
4578 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)
+
4579 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
+
4580 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
+
4581 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
+
4583 /****************** Bit definition for FSMC_PCR4 register *******************/
+
4584 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)
+
4585 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004)
+
4586 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008)
+
4588 #define FSMC_PCR4_PWID ((uint32_t)0x00000030)
+
4589 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)
+
4590 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)
+
4592 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040)
+
4594 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00)
+
4595 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
+
4596 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
+
4597 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
+
4598 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
+
4600 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000)
+
4601 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)
+
4602 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)
+
4603 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)
+
4604 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)
+
4606 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)
+
4607 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
+
4608 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
+
4609 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
+
4611 /******************* Bit definition for FSMC_SR2 register *******************/
+
4612 #define FSMC_SR2_IRS ((uint8_t)0x01)
+
4613 #define FSMC_SR2_ILS ((uint8_t)0x02)
+
4614 #define FSMC_SR2_IFS ((uint8_t)0x04)
+
4615 #define FSMC_SR2_IREN ((uint8_t)0x08)
+
4616 #define FSMC_SR2_ILEN ((uint8_t)0x10)
+
4617 #define FSMC_SR2_IFEN ((uint8_t)0x20)
+
4618 #define FSMC_SR2_FEMPT ((uint8_t)0x40)
+
4620 /******************* Bit definition for FSMC_SR3 register *******************/
+
4621 #define FSMC_SR3_IRS ((uint8_t)0x01)
+
4622 #define FSMC_SR3_ILS ((uint8_t)0x02)
+
4623 #define FSMC_SR3_IFS ((uint8_t)0x04)
+
4624 #define FSMC_SR3_IREN ((uint8_t)0x08)
+
4625 #define FSMC_SR3_ILEN ((uint8_t)0x10)
+
4626 #define FSMC_SR3_IFEN ((uint8_t)0x20)
+
4627 #define FSMC_SR3_FEMPT ((uint8_t)0x40)
+
4629 /******************* Bit definition for FSMC_SR4 register *******************/
+
4630 #define FSMC_SR4_IRS ((uint8_t)0x01)
+
4631 #define FSMC_SR4_ILS ((uint8_t)0x02)
+
4632 #define FSMC_SR4_IFS ((uint8_t)0x04)
+
4633 #define FSMC_SR4_IREN ((uint8_t)0x08)
+
4634 #define FSMC_SR4_ILEN ((uint8_t)0x10)
+
4635 #define FSMC_SR4_IFEN ((uint8_t)0x20)
+
4636 #define FSMC_SR4_FEMPT ((uint8_t)0x40)
+
4638 /****************** Bit definition for FSMC_PMEM2 register ******************/
+
4639 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
+
4640 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
+
4641 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
+
4642 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
+
4643 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
+
4644 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
+
4645 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
+
4646 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
+
4647 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
+
4649 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
+
4650 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
+
4651 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
+
4652 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
+
4653 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
+
4654 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
+
4655 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
+
4656 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
+
4657 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
+
4659 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
+
4660 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
+
4661 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
+
4662 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
+
4663 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
+
4664 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
+
4665 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
+
4666 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
+
4667 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
+
4669 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
+
4670 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
+
4671 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
+
4672 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
+
4673 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
+
4674 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
+
4675 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
+
4676 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
+
4677 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
+
4679 /****************** Bit definition for FSMC_PMEM3 register ******************/
+
4680 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
+
4681 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
+
4682 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
+
4683 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
+
4684 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
+
4685 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
+
4686 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
+
4687 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
+
4688 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
+
4690 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
+
4691 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
+
4692 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
+
4693 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
+
4694 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
+
4695 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
+
4696 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
+
4697 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
+
4698 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
+
4700 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
+
4701 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
+
4702 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
+
4703 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
+
4704 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
+
4705 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
+
4706 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
+
4707 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
+
4708 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
+
4710 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
+
4711 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
+
4712 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
+
4713 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
+
4714 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
+
4715 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
+
4716 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
+
4717 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
+
4718 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
+
4720 /****************** Bit definition for FSMC_PMEM4 register ******************/
+
4721 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
+
4722 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
+
4723 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
+
4724 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
+
4725 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
+
4726 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
+
4727 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
+
4728 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
+
4729 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
+
4731 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
+
4732 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
+
4733 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
+
4734 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
+
4735 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
+
4736 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
+
4737 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
+
4738 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
+
4739 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
+
4741 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
+
4742 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
+
4743 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
+
4744 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
+
4745 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
+
4746 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
+
4747 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
+
4748 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
+
4749 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
+
4751 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
+
4752 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
+
4753 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
+
4754 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
+
4755 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
+
4756 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
+
4757 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
+
4758 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
+
4759 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
+
4761 /****************** Bit definition for FSMC_PATT2 register ******************/
+
4762 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
+
4763 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
+
4764 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
+
4765 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
+
4766 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
+
4767 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
+
4768 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
+
4769 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
+
4770 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
+
4772 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
+
4773 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
+
4774 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
+
4775 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
+
4776 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
+
4777 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
+
4778 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
+
4779 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
+
4780 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
+
4782 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
+
4783 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
+
4784 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
+
4785 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
+
4786 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
+
4787 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
+
4788 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
+
4789 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
+
4790 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
+
4792 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
+
4793 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
+
4794 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
+
4795 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
+
4796 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
+
4797 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
+
4798 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
+
4799 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
+
4800 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
+
4802 /****************** Bit definition for FSMC_PATT3 register ******************/
+
4803 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
+
4804 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
+
4805 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
+
4806 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
+
4807 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
+
4808 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
+
4809 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
+
4810 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
+
4811 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
+
4813 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
+
4814 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
+
4815 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
+
4816 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
+
4817 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
+
4818 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
+
4819 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
+
4820 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
+
4821 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
+
4823 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
+
4824 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
+
4825 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
+
4826 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
+
4827 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
+
4828 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
+
4829 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
+
4830 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
+
4831 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
+
4833 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
+
4834 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
+
4835 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
+
4836 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
+
4837 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
+
4838 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
+
4839 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
+
4840 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
+
4841 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
+
4843 /****************** Bit definition for FSMC_PATT4 register ******************/
+
4844 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
+
4845 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
+
4846 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
+
4847 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
+
4848 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
+
4849 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
+
4850 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
+
4851 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
+
4852 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
+
4854 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
+
4855 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
+
4856 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
+
4857 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
+
4858 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
+
4859 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
+
4860 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
+
4861 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
+
4862 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
+
4864 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
+
4865 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
+
4866 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
+
4867 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
+
4868 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
+
4869 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
+
4870 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
+
4871 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
+
4872 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
+
4874 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
+
4875 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
+
4876 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
+
4877 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
+
4878 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
+
4879 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
+
4880 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
+
4881 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
+
4882 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
+
4884 /****************** Bit definition for FSMC_PIO4 register *******************/
+
4885 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
+
4886 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
+
4887 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
+
4888 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
+
4889 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
+
4890 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
+
4891 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
+
4892 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
+
4893 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
+
4895 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
+
4896 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
+
4897 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
+
4898 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
+
4899 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
+
4900 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
+
4901 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
+
4902 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
+
4903 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
+
4905 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
+
4906 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
+
4907 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
+
4908 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
+
4909 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
+
4910 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
+
4911 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
+
4912 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
+
4913 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
+
4915 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
+
4916 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
+
4917 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
+
4918 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
+
4919 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
+
4920 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
+
4921 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
+
4922 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
+
4923 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
+
4925 /****************** Bit definition for FSMC_ECCR2 register ******************/
+
4926 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
+
4928 /****************** Bit definition for FSMC_ECCR3 register ******************/
+
4929 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
+
4930 #endif /* STM32F40_41xxx */
+
4931 
+
4932 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
4933 /******************************************************************************/
+
4934 /* */
+
4935 /* Flexible Memory Controller */
+
4936 /* */
+
4937 /******************************************************************************/
+
4938 /****************** Bit definition for FMC_BCR1 register *******************/
+
4939 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001)
+
4940 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002)
+
4942 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C)
+
4943 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
+
4944 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
+
4946 #define FMC_BCR1_MWID ((uint32_t)0x00000030)
+
4947 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010)
+
4948 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020)
+
4950 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040)
+
4951 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100)
+
4952 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200)
+
4953 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
+
4954 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800)
+
4955 #define FMC_BCR1_WREN ((uint32_t)0x00001000)
+
4956 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000)
+
4957 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000)
+
4958 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
+
4959 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
+
4960 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000)
+
4962 /****************** Bit definition for FMC_BCR2 register *******************/
+
4963 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001)
+
4964 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002)
+
4966 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C)
+
4967 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
+
4968 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
+
4970 #define FMC_BCR2_MWID ((uint32_t)0x00000030)
+
4971 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010)
+
4972 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020)
+
4974 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040)
+
4975 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100)
+
4976 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200)
+
4977 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
+
4978 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800)
+
4979 #define FMC_BCR2_WREN ((uint32_t)0x00001000)
+
4980 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000)
+
4981 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000)
+
4982 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
+
4983 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
+
4985 /****************** Bit definition for FMC_BCR3 register *******************/
+
4986 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001)
+
4987 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002)
+
4989 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C)
+
4990 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
+
4991 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
+
4993 #define FMC_BCR3_MWID ((uint32_t)0x00000030)
+
4994 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010)
+
4995 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020)
+
4997 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040)
+
4998 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100)
+
4999 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200)
+
5000 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
+
5001 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800)
+
5002 #define FMC_BCR3_WREN ((uint32_t)0x00001000)
+
5003 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000)
+
5004 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000)
+
5005 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
+
5006 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
+
5008 /****************** Bit definition for FMC_BCR4 register *******************/
+
5009 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001)
+
5010 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002)
+
5012 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C)
+
5013 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
+
5014 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
+
5016 #define FMC_BCR4_MWID ((uint32_t)0x00000030)
+
5017 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010)
+
5018 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020)
+
5020 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040)
+
5021 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100)
+
5022 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200)
+
5023 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
+
5024 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800)
+
5025 #define FMC_BCR4_WREN ((uint32_t)0x00001000)
+
5026 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000)
+
5027 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000)
+
5028 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
+
5029 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
+
5031 /****************** Bit definition for FMC_BTR1 register ******************/
+
5032 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F)
+
5033 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
+
5034 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
+
5035 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
+
5036 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
+
5038 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
+
5039 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
+
5040 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
+
5041 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
+
5042 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
+
5044 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00)
+
5045 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
+
5046 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
+
5047 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
+
5048 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
+
5049 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000)
+
5050 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000)
+
5051 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000)
+
5052 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000)
+
5054 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
+
5055 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
+
5056 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
+
5057 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
+
5058 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
+
5060 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
+
5061 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
+
5062 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
+
5063 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
+
5064 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
+
5066 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000)
+
5067 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
+
5068 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
+
5069 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
+
5070 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
+
5072 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000)
+
5073 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
+
5074 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
+
5076 /****************** Bit definition for FMC_BTR2 register *******************/
+
5077 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F)
+
5078 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
+
5079 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
+
5080 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
+
5081 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
+
5083 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
+
5084 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
+
5085 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
+
5086 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
+
5087 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
+
5089 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00)
+
5090 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
+
5091 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
+
5092 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
+
5093 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
+
5094 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000)
+
5095 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000)
+
5096 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000)
+
5097 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000)
+
5099 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
+
5100 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
+
5101 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
+
5102 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
+
5103 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
+
5105 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
+
5106 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
+
5107 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
+
5108 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
+
5109 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
+
5111 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000)
+
5112 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
+
5113 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
+
5114 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
+
5115 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
+
5117 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000)
+
5118 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
+
5119 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
+
5121 /******************* Bit definition for FMC_BTR3 register *******************/
+
5122 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F)
+
5123 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
+
5124 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
+
5125 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
+
5126 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
+
5128 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
+
5129 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
+
5130 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
+
5131 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
+
5132 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
+
5134 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00)
+
5135 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
+
5136 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
+
5137 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
+
5138 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
+
5139 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000)
+
5140 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000)
+
5141 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000)
+
5142 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000)
+
5144 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
+
5145 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
+
5146 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
+
5147 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
+
5148 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
+
5150 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
+
5151 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
+
5152 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
+
5153 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
+
5154 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
+
5156 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000)
+
5157 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
+
5158 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
+
5159 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
+
5160 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
+
5162 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000)
+
5163 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
+
5164 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
+
5166 /****************** Bit definition for FMC_BTR4 register *******************/
+
5167 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F)
+
5168 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
+
5169 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
+
5170 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
+
5171 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
+
5173 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
+
5174 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
+
5175 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
+
5176 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
+
5177 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
+
5179 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00)
+
5180 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
+
5181 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
+
5182 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
+
5183 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
+
5184 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000)
+
5185 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000)
+
5186 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000)
+
5187 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000)
+
5189 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
+
5190 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
+
5191 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
+
5192 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
+
5193 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
+
5195 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
+
5196 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
+
5197 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
+
5198 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
+
5199 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
+
5201 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000)
+
5202 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
+
5203 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
+
5204 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
+
5205 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
+
5207 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000)
+
5208 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
+
5209 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
+
5211 /****************** Bit definition for FMC_BWTR1 register ******************/
+
5212 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
+
5213 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
+
5214 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
+
5215 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
+
5216 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
+
5218 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
+
5219 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
+
5220 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
+
5221 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
+
5222 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
+
5224 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
+
5225 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
+
5226 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
+
5227 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
+
5228 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
+
5229 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000)
+
5230 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000)
+
5231 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000)
+
5232 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000)
+
5234 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
+
5235 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
+
5236 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
+
5237 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
+
5238 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
+
5240 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
+
5241 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
+
5242 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
+
5243 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
+
5244 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
+
5246 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
+
5247 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
+
5248 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
+
5250 /****************** Bit definition for FMC_BWTR2 register ******************/
+
5251 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
+
5252 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
+
5253 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
+
5254 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
+
5255 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
+
5257 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
+
5258 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
+
5259 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
+
5260 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
+
5261 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
+
5263 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
+
5264 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
+
5265 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
+
5266 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
+
5267 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
+
5268 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000)
+
5269 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000)
+
5270 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000)
+
5271 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000)
+
5273 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
+
5274 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
+
5275 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
+
5276 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
+
5277 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
+
5279 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
+
5280 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
+
5281 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
+
5282 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
+
5283 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
+
5285 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
+
5286 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
+
5287 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
+
5289 /****************** Bit definition for FMC_BWTR3 register ******************/
+
5290 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
+
5291 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
+
5292 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
+
5293 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
+
5294 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
+
5296 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
+
5297 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
+
5298 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
+
5299 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
+
5300 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
+
5302 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
+
5303 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
+
5304 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
+
5305 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
+
5306 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
+
5307 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000)
+
5308 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000)
+
5309 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000)
+
5310 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000)
+
5312 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
+
5313 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
+
5314 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
+
5315 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
+
5316 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
+
5318 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
+
5319 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
+
5320 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
+
5321 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
+
5322 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
+
5324 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
+
5325 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
+
5326 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
+
5328 /****************** Bit definition for FMC_BWTR4 register ******************/
+
5329 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
+
5330 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
+
5331 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
+
5332 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
+
5333 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
+
5335 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
+
5336 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
+
5337 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
+
5338 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
+
5339 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
+
5341 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
+
5342 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
+
5343 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
+
5344 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
+
5345 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
+
5346 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000)
+
5347 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000)
+
5348 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000)
+
5349 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000)
+
5351 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
+
5352 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
+
5353 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
+
5354 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
+
5355 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
+
5357 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
+
5358 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
+
5359 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
+
5360 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
+
5361 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
+
5363 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
+
5364 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
+
5365 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
+
5367 /****************** Bit definition for FMC_PCR2 register *******************/
+
5368 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002)
+
5369 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004)
+
5370 #define FMC_PCR2_PTYP ((uint32_t)0x00000008)
+
5372 #define FMC_PCR2_PWID ((uint32_t)0x00000030)
+
5373 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010)
+
5374 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020)
+
5376 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040)
+
5378 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00)
+
5379 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
+
5380 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
+
5381 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
+
5382 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
+
5384 #define FMC_PCR2_TAR ((uint32_t)0x0001E000)
+
5385 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000)
+
5386 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000)
+
5387 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000)
+
5388 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000)
+
5390 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000)
+
5391 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
+
5392 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
+
5393 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
+
5395 /****************** Bit definition for FMC_PCR3 register *******************/
+
5396 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002)
+
5397 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004)
+
5398 #define FMC_PCR3_PTYP ((uint32_t)0x00000008)
+
5400 #define FMC_PCR3_PWID ((uint32_t)0x00000030)
+
5401 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010)
+
5402 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020)
+
5404 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040)
+
5406 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00)
+
5407 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
+
5408 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
+
5409 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
+
5410 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
+
5412 #define FMC_PCR3_TAR ((uint32_t)0x0001E000)
+
5413 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000)
+
5414 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000)
+
5415 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000)
+
5416 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000)
+
5418 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000)
+
5419 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
+
5420 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
+
5421 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
+
5423 /****************** Bit definition for FMC_PCR4 register *******************/
+
5424 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002)
+
5425 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004)
+
5426 #define FMC_PCR4_PTYP ((uint32_t)0x00000008)
+
5428 #define FMC_PCR4_PWID ((uint32_t)0x00000030)
+
5429 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010)
+
5430 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020)
+
5432 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040)
+
5434 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00)
+
5435 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
+
5436 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
+
5437 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
+
5438 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
+
5440 #define FMC_PCR4_TAR ((uint32_t)0x0001E000)
+
5441 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000)
+
5442 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000)
+
5443 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000)
+
5444 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000)
+
5446 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000)
+
5447 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
+
5448 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
+
5449 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
+
5451 /******************* Bit definition for FMC_SR2 register *******************/
+
5452 #define FMC_SR2_IRS ((uint8_t)0x01)
+
5453 #define FMC_SR2_ILS ((uint8_t)0x02)
+
5454 #define FMC_SR2_IFS ((uint8_t)0x04)
+
5455 #define FMC_SR2_IREN ((uint8_t)0x08)
+
5456 #define FMC_SR2_ILEN ((uint8_t)0x10)
+
5457 #define FMC_SR2_IFEN ((uint8_t)0x20)
+
5458 #define FMC_SR2_FEMPT ((uint8_t)0x40)
+
5460 /******************* Bit definition for FMC_SR3 register *******************/
+
5461 #define FMC_SR3_IRS ((uint8_t)0x01)
+
5462 #define FMC_SR3_ILS ((uint8_t)0x02)
+
5463 #define FMC_SR3_IFS ((uint8_t)0x04)
+
5464 #define FMC_SR3_IREN ((uint8_t)0x08)
+
5465 #define FMC_SR3_ILEN ((uint8_t)0x10)
+
5466 #define FMC_SR3_IFEN ((uint8_t)0x20)
+
5467 #define FMC_SR3_FEMPT ((uint8_t)0x40)
+
5469 /******************* Bit definition for FMC_SR4 register *******************/
+
5470 #define FMC_SR4_IRS ((uint8_t)0x01)
+
5471 #define FMC_SR4_ILS ((uint8_t)0x02)
+
5472 #define FMC_SR4_IFS ((uint8_t)0x04)
+
5473 #define FMC_SR4_IREN ((uint8_t)0x08)
+
5474 #define FMC_SR4_ILEN ((uint8_t)0x10)
+
5475 #define FMC_SR4_IFEN ((uint8_t)0x20)
+
5476 #define FMC_SR4_FEMPT ((uint8_t)0x40)
+
5478 /****************** Bit definition for FMC_PMEM2 register ******************/
+
5479 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
+
5480 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
+
5481 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
+
5482 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
+
5483 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
+
5484 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
+
5485 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
+
5486 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
+
5487 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
+
5489 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
+
5490 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
+
5491 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
+
5492 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
+
5493 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
+
5494 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
+
5495 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
+
5496 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
+
5497 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
+
5499 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
+
5500 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
+
5501 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
+
5502 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
+
5503 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
+
5504 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
+
5505 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
+
5506 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
+
5507 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
+
5509 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
+
5510 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
+
5511 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
+
5512 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
+
5513 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
+
5514 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
+
5515 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
+
5516 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
+
5517 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
+
5519 /****************** Bit definition for FMC_PMEM3 register ******************/
+
5520 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
+
5521 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
+
5522 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
+
5523 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
+
5524 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
+
5525 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
+
5526 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
+
5527 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
+
5528 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
+
5530 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
+
5531 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
+
5532 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
+
5533 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
+
5534 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
+
5535 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
+
5536 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
+
5537 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
+
5538 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
+
5540 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
+
5541 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
+
5542 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
+
5543 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
+
5544 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
+
5545 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
+
5546 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
+
5547 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
+
5548 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
+
5550 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
+
5551 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
+
5552 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
+
5553 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
+
5554 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
+
5555 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
+
5556 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
+
5557 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
+
5558 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
+
5560 /****************** Bit definition for FMC_PMEM4 register ******************/
+
5561 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
+
5562 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
+
5563 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
+
5564 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
+
5565 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
+
5566 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
+
5567 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
+
5568 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
+
5569 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
+
5571 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
+
5572 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
+
5573 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
+
5574 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
+
5575 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
+
5576 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
+
5577 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
+
5578 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
+
5579 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
+
5581 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
+
5582 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
+
5583 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
+
5584 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
+
5585 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
+
5586 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
+
5587 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
+
5588 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
+
5589 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
+
5591 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
+
5592 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
+
5593 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
+
5594 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
+
5595 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
+
5596 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
+
5597 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
+
5598 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
+
5599 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
+
5601 /****************** Bit definition for FMC_PATT2 register ******************/
+
5602 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
+
5603 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
+
5604 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
+
5605 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
+
5606 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
+
5607 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
+
5608 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
+
5609 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
+
5610 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
+
5612 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
+
5613 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
+
5614 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
+
5615 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
+
5616 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
+
5617 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
+
5618 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
+
5619 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
+
5620 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
+
5622 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
+
5623 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
+
5624 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
+
5625 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
+
5626 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
+
5627 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
+
5628 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
+
5629 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
+
5630 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
+
5632 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
+
5633 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
+
5634 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
+
5635 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
+
5636 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
+
5637 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
+
5638 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
+
5639 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
+
5640 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
+
5642 /****************** Bit definition for FMC_PATT3 register ******************/
+
5643 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
+
5644 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
+
5645 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
+
5646 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
+
5647 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
+
5648 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
+
5649 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
+
5650 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
+
5651 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
+
5653 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
+
5654 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
+
5655 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
+
5656 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
+
5657 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
+
5658 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
+
5659 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
+
5660 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
+
5661 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
+
5663 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
+
5664 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
+
5665 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
+
5666 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
+
5667 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
+
5668 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
+
5669 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
+
5670 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
+
5671 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
+
5673 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
+
5674 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
+
5675 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
+
5676 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
+
5677 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
+
5678 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
+
5679 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
+
5680 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
+
5681 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
+
5683 /****************** Bit definition for FMC_PATT4 register ******************/
+
5684 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
+
5685 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
+
5686 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
+
5687 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
+
5688 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
+
5689 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
+
5690 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
+
5691 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
+
5692 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
+
5694 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
+
5695 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
+
5696 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
+
5697 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
+
5698 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
+
5699 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
+
5700 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
+
5701 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
+
5702 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
+
5704 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
+
5705 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
+
5706 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
+
5707 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
+
5708 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
+
5709 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
+
5710 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
+
5711 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
+
5712 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
+
5714 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
+
5715 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
+
5716 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
+
5717 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
+
5718 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
+
5719 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
+
5720 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
+
5721 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
+
5722 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
+
5724 /****************** Bit definition for FMC_PIO4 register *******************/
+
5725 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
+
5726 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
+
5727 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
+
5728 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
+
5729 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
+
5730 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
+
5731 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
+
5732 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
+
5733 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
+
5735 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
+
5736 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
+
5737 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
+
5738 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
+
5739 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
+
5740 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
+
5741 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
+
5742 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
+
5743 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
+
5745 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
+
5746 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
+
5747 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
+
5748 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
+
5749 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
+
5750 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
+
5751 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
+
5752 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
+
5753 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
+
5755 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
+
5756 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
+
5757 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
+
5758 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
+
5759 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
+
5760 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
+
5761 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
+
5762 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
+
5763 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
+
5765 /****************** Bit definition for FMC_ECCR2 register ******************/
+
5766 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
+
5768 /****************** Bit definition for FMC_ECCR3 register ******************/
+
5769 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
+
5771 /****************** Bit definition for FMC_SDCR1 register ******************/
+
5772 #define FMC_SDCR1_NC ((uint32_t)0x00000003)
+
5773 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001)
+
5774 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002)
+
5776 #define FMC_SDCR1_NR ((uint32_t)0x0000000C)
+
5777 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004)
+
5778 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008)
+
5780 #define FMC_SDCR1_MWID ((uint32_t)0x00000030)
+
5781 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010)
+
5782 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020)
+
5784 #define FMC_SDCR1_NB ((uint32_t)0x00000040)
+
5786 #define FMC_SDCR1_CAS ((uint32_t)0x00000180)
+
5787 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080)
+
5788 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100)
+
5790 #define FMC_SDCR1_WP ((uint32_t)0x00000200)
+
5792 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00)
+
5793 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400)
+
5794 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800)
+
5796 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000)
+
5798 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000)
+
5799 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000)
+
5800 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000)
+
5802 /****************** Bit definition for FMC_SDCR2 register ******************/
+
5803 #define FMC_SDCR2_NC ((uint32_t)0x00000003)
+
5804 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001)
+
5805 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002)
+
5807 #define FMC_SDCR2_NR ((uint32_t)0x0000000C)
+
5808 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004)
+
5809 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008)
+
5811 #define FMC_SDCR2_MWID ((uint32_t)0x00000030)
+
5812 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010)
+
5813 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020)
+
5815 #define FMC_SDCR2_NB ((uint32_t)0x00000040)
+
5817 #define FMC_SDCR2_CAS ((uint32_t)0x00000180)
+
5818 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080)
+
5819 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100)
+
5821 #define FMC_SDCR2_WP ((uint32_t)0x00000200)
+
5823 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00)
+
5824 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400)
+
5825 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800)
+
5827 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000)
+
5829 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000)
+
5830 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000)
+
5831 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000)
+
5833 /****************** Bit definition for FMC_SDTR1 register ******************/
+
5834 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F)
+
5835 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001)
+
5836 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002)
+
5837 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004)
+
5838 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008)
+
5840 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0)
+
5841 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010)
+
5842 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020)
+
5843 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040)
+
5844 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080)
+
5846 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00)
+
5847 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100)
+
5848 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200)
+
5849 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400)
+
5850 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800)
+
5852 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000)
+
5853 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000)
+
5854 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000)
+
5855 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000)
+
5857 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000)
+
5858 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000)
+
5859 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000)
+
5860 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000)
+
5862 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000)
+
5863 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000)
+
5864 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000)
+
5865 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000)
+
5867 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000)
+
5868 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000)
+
5869 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000)
+
5870 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000)
+
5872 /****************** Bit definition for FMC_SDTR2 register ******************/
+
5873 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F)
+
5874 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001)
+
5875 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002)
+
5876 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004)
+
5877 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008)
+
5879 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0)
+
5880 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010)
+
5881 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020)
+
5882 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040)
+
5883 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080)
+
5885 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00)
+
5886 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100)
+
5887 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200)
+
5888 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400)
+
5889 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800)
+
5891 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000)
+
5892 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000)
+
5893 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000)
+
5894 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000)
+
5896 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000)
+
5897 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000)
+
5898 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000)
+
5899 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000)
+
5901 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000)
+
5902 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000)
+
5903 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000)
+
5904 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000)
+
5906 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000)
+
5907 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000)
+
5908 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000)
+
5909 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000)
+
5911 /****************** Bit definition for FMC_SDCMR register ******************/
+
5912 #define FMC_SDCMR_MODE ((uint32_t)0x00000007)
+
5913 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001)
+
5914 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002)
+
5915 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003)
+
5917 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008)
+
5919 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010)
+
5921 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0)
+
5922 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020)
+
5923 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040)
+
5924 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080)
+
5925 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100)
+
5927 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00)
+
5929 /****************** Bit definition for FMC_SDRTR register ******************/
+
5930 #define FMC_SDRTR_CRE ((uint32_t)0x00000001)
+
5932 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE)
+
5934 #define FMC_SDRTR_REIE ((uint32_t)0x00004000)
+
5936 /****************** Bit definition for FMC_SDSR register ******************/
+
5937 #define FMC_SDSR_RE ((uint32_t)0x00000001)
+
5939 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006)
+
5940 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002)
+
5941 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004)
+
5943 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018)
+
5944 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008)
+
5945 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010)
+
5947 #define FMC_SDSR_BUSY ((uint32_t)0x00000020)
+
5949 #endif /* STM32F427_437xx || STM32F429_439xx */
+
5950 
+
5951 /******************************************************************************/
+
5952 /* */
+
5953 /* General Purpose I/O */
+
5954 /* */
+
5955 /******************************************************************************/
+
5956 /****************** Bits definition for GPIO_MODER register *****************/
+
5957 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+
5958 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+
5959 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+
5960 
+
5961 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+
5962 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+
5963 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+
5964 
+
5965 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+
5966 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+
5967 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+
5968 
+
5969 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+
5970 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+
5971 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+
5972 
+
5973 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+
5974 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+
5975 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+
5976 
+
5977 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+
5978 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+
5979 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+
5980 
+
5981 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+
5982 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+
5983 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+
5984 
+
5985 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+
5986 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+
5987 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+
5988 
+
5989 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+
5990 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+
5991 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+
5992 
+
5993 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+
5994 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+
5995 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+
5996 
+
5997 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+
5998 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+
5999 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+
6000 
+
6001 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+
6002 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+
6003 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+
6004 
+
6005 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+
6006 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+
6007 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+
6008 
+
6009 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+
6010 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+
6011 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+
6012 
+
6013 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+
6014 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+
6015 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+
6016 
+
6017 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+
6018 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+
6019 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
6020 
+
6021 /****************** Bits definition for GPIO_OTYPER register ****************/
+
6022 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+
6023 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+
6024 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+
6025 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+
6026 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+
6027 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+
6028 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+
6029 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+
6030 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+
6031 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+
6032 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+
6033 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+
6034 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+
6035 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+
6036 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+
6037 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
6038 
+
6039 /****************** Bits definition for GPIO_OSPEEDR register ***************/
+
6040 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+
6041 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+
6042 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+
6043 
+
6044 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+
6045 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+
6046 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+
6047 
+
6048 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+
6049 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+
6050 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+
6051 
+
6052 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+
6053 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+
6054 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+
6055 
+
6056 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+
6057 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+
6058 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+
6059 
+
6060 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+
6061 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+
6062 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+
6063 
+
6064 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+
6065 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+
6066 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+
6067 
+
6068 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+
6069 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+
6070 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+
6071 
+
6072 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+
6073 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+
6074 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+
6075 
+
6076 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+
6077 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+
6078 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+
6079 
+
6080 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+
6081 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+
6082 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+
6083 
+
6084 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+
6085 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+
6086 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+
6087 
+
6088 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+
6089 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+
6090 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+
6091 
+
6092 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+
6093 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+
6094 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+
6095 
+
6096 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+
6097 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+
6098 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+
6099 
+
6100 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+
6101 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+
6102 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
6103 
+
6104 /****************** Bits definition for GPIO_PUPDR register *****************/
+
6105 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+
6106 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+
6107 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+
6108 
+
6109 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+
6110 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+
6111 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+
6112 
+
6113 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+
6114 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+
6115 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+
6116 
+
6117 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+
6118 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+
6119 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+
6120 
+
6121 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+
6122 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+
6123 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+
6124 
+
6125 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+
6126 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+
6127 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+
6128 
+
6129 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+
6130 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+
6131 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+
6132 
+
6133 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+
6134 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+
6135 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+
6136 
+
6137 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+
6138 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+
6139 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+
6140 
+
6141 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+
6142 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+
6143 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+
6144 
+
6145 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+
6146 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+
6147 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+
6148 
+
6149 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+
6150 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+
6151 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+
6152 
+
6153 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+
6154 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+
6155 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+
6156 
+
6157 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+
6158 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+
6159 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+
6160 
+
6161 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+
6162 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+
6163 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+
6164 
+
6165 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+
6166 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+
6167 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
6168 
+
6169 /****************** Bits definition for GPIO_IDR register *******************/
+
6170 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+
6171 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+
6172 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+
6173 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+
6174 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+
6175 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+
6176 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+
6177 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+
6178 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+
6179 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+
6180 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+
6181 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+
6182 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+
6183 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+
6184 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+
6185 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+
6186 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+
6187 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+
6188 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+
6189 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+
6190 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+
6191 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+
6192 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+
6193 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+
6194 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+
6195 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+
6196 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+
6197 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+
6198 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+
6199 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+
6200 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+
6201 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+
6202 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
6203 
+
6204 /****************** Bits definition for GPIO_ODR register *******************/
+
6205 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+
6206 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+
6207 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+
6208 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+
6209 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+
6210 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+
6211 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+
6212 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+
6213 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+
6214 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+
6215 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+
6216 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+
6217 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+
6218 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+
6219 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+
6220 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+
6221 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+
6222 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+
6223 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+
6224 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+
6225 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+
6226 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+
6227 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+
6228 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+
6229 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+
6230 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+
6231 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+
6232 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+
6233 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+
6234 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+
6235 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+
6236 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+
6237 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
6238 
+
6239 /****************** Bits definition for GPIO_BSRR register ******************/
+
6240 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+
6241 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+
6242 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+
6243 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+
6244 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+
6245 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+
6246 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+
6247 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+
6248 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+
6249 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+
6250 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+
6251 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+
6252 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+
6253 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+
6254 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+
6255 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+
6256 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+
6257 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+
6258 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+
6259 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+
6260 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+
6261 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+
6262 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+
6263 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+
6264 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+
6265 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+
6266 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+
6267 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+
6268 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+
6269 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+
6270 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+
6271 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
6272 
+
6273 /******************************************************************************/
+
6274 /* */
+
6275 /* HASH */
+
6276 /* */
+
6277 /******************************************************************************/
+
6278 /****************** Bits definition for HASH_CR register ********************/
+
6279 #define HASH_CR_INIT ((uint32_t)0x00000004)
+
6280 #define HASH_CR_DMAE ((uint32_t)0x00000008)
+
6281 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
+
6282 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
+
6283 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
+
6284 #define HASH_CR_MODE ((uint32_t)0x00000040)
+
6285 #define HASH_CR_ALGO ((uint32_t)0x00040080)
+
6286 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
+
6287 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
+
6288 #define HASH_CR_NBW ((uint32_t)0x00000F00)
+
6289 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
+
6290 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
+
6291 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
+
6292 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
+
6293 #define HASH_CR_DINNE ((uint32_t)0x00001000)
+
6294 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
+
6295 #define HASH_CR_LKEY ((uint32_t)0x00010000)
+
6296 
+
6297 /****************** Bits definition for HASH_STR register *******************/
+
6298 #define HASH_STR_NBW ((uint32_t)0x0000001F)
+
6299 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
+
6300 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
+
6301 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
+
6302 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
+
6303 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
+
6304 #define HASH_STR_DCAL ((uint32_t)0x00000100)
+
6305 
+
6306 /****************** Bits definition for HASH_IMR register *******************/
+
6307 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
+
6308 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
+
6309 
+
6310 /****************** Bits definition for HASH_SR register ********************/
+
6311 #define HASH_SR_DINIS ((uint32_t)0x00000001)
+
6312 #define HASH_SR_DCIS ((uint32_t)0x00000002)
+
6313 #define HASH_SR_DMAS ((uint32_t)0x00000004)
+
6314 #define HASH_SR_BUSY ((uint32_t)0x00000008)
+
6315 
+
6316 /******************************************************************************/
+
6317 /* */
+
6318 /* Inter-integrated Circuit Interface */
+
6319 /* */
+
6320 /******************************************************************************/
+
6321 /******************* Bit definition for I2C_CR1 register ********************/
+
6322 #define I2C_CR1_PE ((uint16_t)0x0001)
+
6323 #define I2C_CR1_SMBUS ((uint16_t)0x0002)
+
6324 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008)
+
6325 #define I2C_CR1_ENARP ((uint16_t)0x0010)
+
6326 #define I2C_CR1_ENPEC ((uint16_t)0x0020)
+
6327 #define I2C_CR1_ENGC ((uint16_t)0x0040)
+
6328 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080)
+
6329 #define I2C_CR1_START ((uint16_t)0x0100)
+
6330 #define I2C_CR1_STOP ((uint16_t)0x0200)
+
6331 #define I2C_CR1_ACK ((uint16_t)0x0400)
+
6332 #define I2C_CR1_POS ((uint16_t)0x0800)
+
6333 #define I2C_CR1_PEC ((uint16_t)0x1000)
+
6334 #define I2C_CR1_ALERT ((uint16_t)0x2000)
+
6335 #define I2C_CR1_SWRST ((uint16_t)0x8000)
+
6337 /******************* Bit definition for I2C_CR2 register ********************/
+
6338 #define I2C_CR2_FREQ ((uint16_t)0x003F)
+
6339 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001)
+
6340 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002)
+
6341 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004)
+
6342 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008)
+
6343 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010)
+
6344 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020)
+
6346 #define I2C_CR2_ITERREN ((uint16_t)0x0100)
+
6347 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200)
+
6348 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400)
+
6349 #define I2C_CR2_DMAEN ((uint16_t)0x0800)
+
6350 #define I2C_CR2_LAST ((uint16_t)0x1000)
+
6352 /******************* Bit definition for I2C_OAR1 register *******************/
+
6353 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)
+
6354 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
+
6356 #define I2C_OAR1_ADD0 ((uint16_t)0x0001)
+
6357 #define I2C_OAR1_ADD1 ((uint16_t)0x0002)
+
6358 #define I2C_OAR1_ADD2 ((uint16_t)0x0004)
+
6359 #define I2C_OAR1_ADD3 ((uint16_t)0x0008)
+
6360 #define I2C_OAR1_ADD4 ((uint16_t)0x0010)
+
6361 #define I2C_OAR1_ADD5 ((uint16_t)0x0020)
+
6362 #define I2C_OAR1_ADD6 ((uint16_t)0x0040)
+
6363 #define I2C_OAR1_ADD7 ((uint16_t)0x0080)
+
6364 #define I2C_OAR1_ADD8 ((uint16_t)0x0100)
+
6365 #define I2C_OAR1_ADD9 ((uint16_t)0x0200)
+
6367 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000)
+
6369 /******************* Bit definition for I2C_OAR2 register *******************/
+
6370 #define I2C_OAR2_ENDUAL ((uint8_t)0x01)
+
6371 #define I2C_OAR2_ADD2 ((uint8_t)0xFE)
+
6373 /******************** Bit definition for I2C_DR register ********************/
+
6374 #define I2C_DR_DR ((uint8_t)0xFF)
+
6376 /******************* Bit definition for I2C_SR1 register ********************/
+
6377 #define I2C_SR1_SB ((uint16_t)0x0001)
+
6378 #define I2C_SR1_ADDR ((uint16_t)0x0002)
+
6379 #define I2C_SR1_BTF ((uint16_t)0x0004)
+
6380 #define I2C_SR1_ADD10 ((uint16_t)0x0008)
+
6381 #define I2C_SR1_STOPF ((uint16_t)0x0010)
+
6382 #define I2C_SR1_RXNE ((uint16_t)0x0040)
+
6383 #define I2C_SR1_TXE ((uint16_t)0x0080)
+
6384 #define I2C_SR1_BERR ((uint16_t)0x0100)
+
6385 #define I2C_SR1_ARLO ((uint16_t)0x0200)
+
6386 #define I2C_SR1_AF ((uint16_t)0x0400)
+
6387 #define I2C_SR1_OVR ((uint16_t)0x0800)
+
6388 #define I2C_SR1_PECERR ((uint16_t)0x1000)
+
6389 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000)
+
6390 #define I2C_SR1_SMBALERT ((uint16_t)0x8000)
+
6392 /******************* Bit definition for I2C_SR2 register ********************/
+
6393 #define I2C_SR2_MSL ((uint16_t)0x0001)
+
6394 #define I2C_SR2_BUSY ((uint16_t)0x0002)
+
6395 #define I2C_SR2_TRA ((uint16_t)0x0004)
+
6396 #define I2C_SR2_GENCALL ((uint16_t)0x0010)
+
6397 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)
+
6398 #define I2C_SR2_SMBHOST ((uint16_t)0x0040)
+
6399 #define I2C_SR2_DUALF ((uint16_t)0x0080)
+
6400 #define I2C_SR2_PEC ((uint16_t)0xFF00)
+
6402 /******************* Bit definition for I2C_CCR register ********************/
+
6403 #define I2C_CCR_CCR ((uint16_t)0x0FFF)
+
6404 #define I2C_CCR_DUTY ((uint16_t)0x4000)
+
6405 #define I2C_CCR_FS ((uint16_t)0x8000)
+
6407 /****************** Bit definition for I2C_TRISE register *******************/
+
6408 #define I2C_TRISE_TRISE ((uint8_t)0x3F)
+
6410 /****************** Bit definition for I2C_FLTR register *******************/
+
6411 #define I2C_FLTR_DNF ((uint8_t)0x0F)
+
6412 #define I2C_FLTR_ANOFF ((uint8_t)0x10)
+
6414 /******************************************************************************/
+
6415 /* */
+
6416 /* Independent WATCHDOG */
+
6417 /* */
+
6418 /******************************************************************************/
+
6419 /******************* Bit definition for IWDG_KR register ********************/
+
6420 #define IWDG_KR_KEY ((uint16_t)0xFFFF)
+
6422 /******************* Bit definition for IWDG_PR register ********************/
+
6423 #define IWDG_PR_PR ((uint8_t)0x07)
+
6424 #define IWDG_PR_PR_0 ((uint8_t)0x01)
+
6425 #define IWDG_PR_PR_1 ((uint8_t)0x02)
+
6426 #define IWDG_PR_PR_2 ((uint8_t)0x04)
+
6428 /******************* Bit definition for IWDG_RLR register *******************/
+
6429 #define IWDG_RLR_RL ((uint16_t)0x0FFF)
+
6431 /******************* Bit definition for IWDG_SR register ********************/
+
6432 #define IWDG_SR_PVU ((uint8_t)0x01)
+
6433 #define IWDG_SR_RVU ((uint8_t)0x02)
+
6435 /******************************************************************************/
+
6436 /* */
+
6437 /* LCD-TFT Display Controller (LTDC) */
+
6438 /* */
+
6439 /******************************************************************************/
+
6440 
+
6441 /******************** Bit definition for LTDC_SSCR register *****************/
+
6442 
+
6443 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF)
+
6444 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000)
+
6446 /******************** Bit definition for LTDC_BPCR register *****************/
+
6447 
+
6448 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF)
+
6449 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000)
+
6451 /******************** Bit definition for LTDC_AWCR register *****************/
+
6452 
+
6453 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF)
+
6454 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000)
+
6456 /******************** Bit definition for LTDC_TWCR register *****************/
+
6457 
+
6458 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF)
+
6459 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000)
+
6461 /******************** Bit definition for LTDC_GCR register ******************/
+
6462 
+
6463 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001)
+
6464 #define LTDC_GCR_DBW ((uint32_t)0x00000070)
+
6465 #define LTDC_GCR_DGW ((uint32_t)0x00000700)
+
6466 #define LTDC_GCR_DRW ((uint32_t)0x00007000)
+
6467 #define LTDC_GCR_DTEN ((uint32_t)0x00010000)
+
6468 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000)
+
6469 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000)
+
6470 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000)
+
6471 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000)
+
6473 /******************** Bit definition for LTDC_SRCR register *****************/
+
6474 
+
6475 #define LTDC_SRCR_IMR ((uint32_t)0x00000001)
+
6476 #define LTDC_SRCR_VBR ((uint32_t)0x00000002)
+
6478 /******************** Bit definition for LTDC_BCCR register *****************/
+
6479 
+
6480 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF)
+
6481 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00)
+
6482 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000)
+
6484 /******************** Bit definition for LTDC_IER register ******************/
+
6485 
+
6486 #define LTDC_IER_LIE ((uint32_t)0x00000001)
+
6487 #define LTDC_IER_FUIE ((uint32_t)0x00000002)
+
6488 #define LTDC_IER_TERRIE ((uint32_t)0x00000004)
+
6489 #define LTDC_IER_RRIE ((uint32_t)0x00000008)
+
6491 /******************** Bit definition for LTDC_ISR register ******************/
+
6492 
+
6493 #define LTDC_ISR_LIF ((uint32_t)0x00000001)
+
6494 #define LTDC_ISR_FUIF ((uint32_t)0x00000002)
+
6495 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004)
+
6496 #define LTDC_ISR_RRIF ((uint32_t)0x00000008)
+
6498 /******************** Bit definition for LTDC_ICR register ******************/
+
6499 
+
6500 #define LTDC_ICR_CLIF ((uint32_t)0x00000001)
+
6501 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002)
+
6502 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004)
+
6503 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008)
+
6505 /******************** Bit definition for LTDC_LIPCR register ****************/
+
6506 
+
6507 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF)
+
6509 /******************** Bit definition for LTDC_CPSR register *****************/
+
6510 
+
6511 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF)
+
6512 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000)
+
6514 /******************** Bit definition for LTDC_CDSR register *****************/
+
6515 
+
6516 #define LTDC_CDSR_VDES ((uint32_t)0x00000001)
+
6517 #define LTDC_CDSR_HDES ((uint32_t)0x00000002)
+
6518 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004)
+
6519 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008)
+
6521 /******************** Bit definition for LTDC_LxCR register *****************/
+
6522 
+
6523 #define LTDC_LxCR_LEN ((uint32_t)0x00000001)
+
6524 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002)
+
6525 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010)
+
6527 /******************** Bit definition for LTDC_LxWHPCR register **************/
+
6528 
+
6529 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF)
+
6530 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000)
+
6532 /******************** Bit definition for LTDC_LxWVPCR register **************/
+
6533 
+
6534 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF)
+
6535 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000)
+
6537 /******************** Bit definition for LTDC_LxCKCR register ***************/
+
6538 
+
6539 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF)
+
6540 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00)
+
6541 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000)
+
6543 /******************** Bit definition for LTDC_LxPFCR register ***************/
+
6544 
+
6545 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007)
+
6547 /******************** Bit definition for LTDC_LxCACR register ***************/
+
6548 
+
6549 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF)
+
6551 /******************** Bit definition for LTDC_LxDCCR register ***************/
+
6552 
+
6553 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF)
+
6554 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00)
+
6555 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000)
+
6556 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000)
+
6558 /******************** Bit definition for LTDC_LxBFCR register ***************/
+
6559 
+
6560 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007)
+
6561 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700)
+
6563 /******************** Bit definition for LTDC_LxCFBAR register **************/
+
6564 
+
6565 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF)
+
6567 /******************** Bit definition for LTDC_LxCFBLR register **************/
+
6568 
+
6569 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF)
+
6570 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000)
+
6572 /******************** Bit definition for LTDC_LxCFBLNR register *************/
+
6573 
+
6574 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF)
+
6576 /******************** Bit definition for LTDC_LxCLUTWR register *************/
+
6577 
+
6578 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF)
+
6579 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00)
+
6580 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000)
+
6581 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000)
+
6583 /******************************************************************************/
+
6584 /* */
+
6585 /* Power Control */
+
6586 /* */
+
6587 /******************************************************************************/
+
6588 /******************** Bit definition for PWR_CR register ********************/
+
6589 #define PWR_CR_LPDS ((uint32_t)0x00000001)
+
6590 #define PWR_CR_PDDS ((uint32_t)0x00000002)
+
6591 #define PWR_CR_CWUF ((uint32_t)0x00000004)
+
6592 #define PWR_CR_CSBF ((uint32_t)0x00000008)
+
6593 #define PWR_CR_PVDE ((uint32_t)0x00000010)
+
6595 #define PWR_CR_PLS ((uint32_t)0x000000E0)
+
6596 #define PWR_CR_PLS_0 ((uint32_t)0x00000020)
+
6597 #define PWR_CR_PLS_1 ((uint32_t)0x00000040)
+
6598 #define PWR_CR_PLS_2 ((uint32_t)0x00000080)
+
6601 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000)
+
6602 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020)
+
6603 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040)
+
6604 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060)
+
6605 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080)
+
6606 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0)
+
6607 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0)
+
6608 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0)
+
6610 #define PWR_CR_DBP ((uint32_t)0x00000100)
+
6611 #define PWR_CR_FPDS ((uint32_t)0x00000200)
+
6612 #define PWR_CR_LPUDS ((uint32_t)0x00000400)
+
6613 #define PWR_CR_MRUDS ((uint32_t)0x00000800)
+
6614 #define PWR_CR_LPLVDS ((uint32_t)0x00000400)
+
6615 #define PWR_CR_MRLVDS ((uint32_t)0x00000800)
+
6617 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000)
+
6619 #define PWR_CR_VOS ((uint32_t)0x0000C000)
+
6620 #define PWR_CR_VOS_0 ((uint32_t)0x00004000)
+
6621 #define PWR_CR_VOS_1 ((uint32_t)0x00008000)
+
6623 #define PWR_CR_ODEN ((uint32_t)0x00010000)
+
6624 #define PWR_CR_ODSWEN ((uint32_t)0x00020000)
+
6625 #define PWR_CR_UDEN ((uint32_t)0x000C0000)
+
6626 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000)
+
6627 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000)
+
6629 #define PWR_CR_FMSSR ((uint32_t)0x00100000)
+
6630 #define PWR_CR_FISSR ((uint32_t)0x00200000)
+
6632 /* Legacy define */
+
6633 #define PWR_CR_PMODE PWR_CR_VOS
+
6634 
+
6635 /******************* Bit definition for PWR_CSR register ********************/
+
6636 #define PWR_CSR_WUF ((uint32_t)0x00000001)
+
6637 #define PWR_CSR_SBF ((uint32_t)0x00000002)
+
6638 #define PWR_CSR_PVDO ((uint32_t)0x00000004)
+
6639 #define PWR_CSR_BRR ((uint32_t)0x00000008)
+
6640 #define PWR_CSR_EWUP ((uint32_t)0x00000100)
+
6641 #define PWR_CSR_BRE ((uint32_t)0x00000200)
+
6642 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000)
+
6643 #define PWR_CSR_ODRDY ((uint32_t)0x00010000)
+
6644 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000)
+
6645 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000)
+
6647 /* Legacy define */
+
6648 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
6649 
+
6650 /******************************************************************************/
+
6651 /* */
+
6652 /* Reset and Clock Control */
+
6653 /* */
+
6654 /******************************************************************************/
+
6655 /******************** Bit definition for RCC_CR register ********************/
+
6656 #define RCC_CR_HSION ((uint32_t)0x00000001)
+
6657 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
6658 
+
6659 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+
6660 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)
+
6661 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)
+
6662 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)
+
6663 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)
+
6664 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)
+
6666 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+
6667 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)
+
6668 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)
+
6669 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)
+
6670 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)
+
6671 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)
+
6672 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)
+
6673 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)
+
6674 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)
+
6676 #define RCC_CR_HSEON ((uint32_t)0x00010000)
+
6677 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
+
6678 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+
6679 #define RCC_CR_CSSON ((uint32_t)0x00080000)
+
6680 #define RCC_CR_PLLON ((uint32_t)0x01000000)
+
6681 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
6682 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
+
6683 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
+
6684 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
+
6685 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
+
6686 
+
6687 /******************** Bit definition for RCC_PLLCFGR register ***************/
+
6688 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
+
6689 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
+
6690 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
+
6691 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
+
6692 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
+
6693 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
+
6694 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
+
6695 
+
6696 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
+
6697 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
+
6698 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
+
6699 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
+
6700 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
+
6701 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
+
6702 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
+
6703 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
+
6704 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
+
6705 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
+
6706 
+
6707 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
+
6708 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
+
6709 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
+
6710 
+
6711 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
+
6712 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
+
6713 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
+
6714 
+
6715 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
+
6716 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
+
6717 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
+
6718 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
+
6719 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
+
6720 
+
6721 /******************** Bit definition for RCC_CFGR register ******************/
+
6723 #define RCC_CFGR_SW ((uint32_t)0x00000003)
+
6724 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001)
+
6725 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002)
+
6727 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
+
6728 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
+
6729 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
+
6732 #define RCC_CFGR_SWS ((uint32_t)0x0000000C)
+
6733 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
+
6734 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
+
6736 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
+
6737 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
+
6738 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
+
6741 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0)
+
6742 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
+
6743 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
+
6744 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
+
6745 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
+
6747 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
+
6748 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
+
6749 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
+
6750 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
+
6751 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
+
6752 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
+
6753 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
+
6754 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
+
6755 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
+
6758 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00)
+
6759 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400)
+
6760 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800)
+
6761 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000)
+
6763 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
+
6764 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000)
+
6765 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400)
+
6766 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800)
+
6767 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00)
+
6770 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000)
+
6771 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000)
+
6772 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000)
+
6773 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000)
+
6775 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
+
6776 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000)
+
6777 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000)
+
6778 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000)
+
6779 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000)
+
6782 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
+
6783 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
+
6784 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
+
6785 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
+
6786 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
+
6787 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
+
6788 
+
6790 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
+
6791 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
+
6792 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
+
6793 
+
6794 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
+
6795 
+
6796 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
+
6797 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
+
6798 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
+
6799 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
+
6800 
+
6801 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
+
6802 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
+
6803 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
+
6804 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
+
6805 
+
6806 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
+
6807 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
+
6808 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
+
6809 
+
6810 /******************** Bit definition for RCC_CIR register *******************/
+
6811 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
+
6812 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
+
6813 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
+
6814 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
+
6815 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
+
6816 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
+
6817 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
+
6818 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
+
6819 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
+
6820 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
+
6821 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
+
6822 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
+
6823 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
+
6824 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
+
6825 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
+
6826 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
+
6827 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
+
6828 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
+
6829 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
+
6830 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
+
6831 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
+
6832 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
+
6833 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
+
6834 
+
6835 /******************** Bit definition for RCC_AHB1RSTR register **************/
+
6836 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
+
6837 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
+
6838 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
+
6839 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
+
6840 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
+
6841 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
+
6842 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
+
6843 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
+
6844 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
+
6845 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
+
6846 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
+
6847 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
+
6848 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
+
6849 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
+
6850 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
+
6851 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
+
6852 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
+
6853 
+
6854 /******************** Bit definition for RCC_AHB2RSTR register **************/
+
6855 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
+
6856 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
+
6857 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
+
6858  /* maintained for legacy purpose */
+
6859  #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+
6860 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
+
6861 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
+
6862 
+
6863 /******************** Bit definition for RCC_AHB3RSTR register **************/
+
6864 #if defined(STM32F40_41xxx)
+
6865 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
+
6866 #endif /* STM32F40_41xxx */
+
6867 
+
6868 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
6869 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
+
6870 #endif /* STM32F427_437xx || STM32F429_439xx */
+
6871 /******************** Bit definition for RCC_APB1RSTR register **************/
+
6872 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
+
6873 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
+
6874 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
+
6875 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
+
6876 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
+
6877 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
+
6878 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
+
6879 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
+
6880 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
+
6881 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
+
6882 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
+
6883 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
+
6884 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
+
6885 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
+
6886 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
+
6887 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
+
6888 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
+
6889 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
+
6890 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
+
6891 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
+
6892 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
+
6893 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
+
6894 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
+
6895 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
+
6896 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
+
6897 
+
6898 /******************** Bit definition for RCC_APB2RSTR register **************/
+
6899 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
+
6900 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
+
6901 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
+
6902 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
+
6903 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
+
6904 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
+
6905 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
+
6906 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
+
6907 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
+
6908 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
+
6909 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
+
6910 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
+
6911 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
+
6912 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
+
6913 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
+
6914 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
+
6915 
+
6916 /* Old SPI1RST bit definition, maintained for legacy purpose */
+
6917 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
6918 
+
6919 /******************** Bit definition for RCC_AHB1ENR register ***************/
+
6920 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
+
6921 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
+
6922 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
+
6923 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
+
6924 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
+
6925 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
+
6926 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
+
6927 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
+
6928 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
+
6929 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
+
6930 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
+
6931 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
+
6932 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
+
6933 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
+
6934 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
+
6935 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
+
6936 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
+
6937 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
+
6938 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
+
6939 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
+
6940 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
+
6941 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
+
6942 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
+
6943 
+
6944 /******************** Bit definition for RCC_AHB2ENR register ***************/
+
6945 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
+
6946 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
+
6947 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
+
6948 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
+
6949 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
+
6950 
+
6951 /******************** Bit definition for RCC_AHB3ENR register ***************/
+
6952 
+
6953 #if defined(STM32F40_41xxx)
+
6954 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
+
6955 #endif /* STM32F40_41xxx */
+
6956 
+
6957 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
6958 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
+
6959 #endif /* STM32F427_437xx || STM32F429_439xx */
+
6960 
+
6961 /******************** Bit definition for RCC_APB1ENR register ***************/
+
6962 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
+
6963 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
+
6964 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
+
6965 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
+
6966 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
+
6967 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
+
6968 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
+
6969 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
+
6970 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
+
6971 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
+
6972 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
+
6973 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
+
6974 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
+
6975 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
+
6976 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
+
6977 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
+
6978 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
+
6979 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
+
6980 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
+
6981 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
+
6982 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
+
6983 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
+
6984 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
+
6985 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
+
6986 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
+
6987 
+
6988 /******************** Bit definition for RCC_APB2ENR register ***************/
+
6989 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
+
6990 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
+
6991 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
+
6992 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
+
6993 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
+
6994 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
+
6995 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
+
6996 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
+
6997 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
+
6998 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
+
6999 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
+
7000 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
+
7001 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
+
7002 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
+
7003 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
+
7004 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
+
7005 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
+
7006 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
+
7007 
+
7008 /******************** Bit definition for RCC_AHB1LPENR register *************/
+
7009 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
+
7010 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
+
7011 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
+
7012 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
+
7013 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
+
7014 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
+
7015 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
+
7016 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
+
7017 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
+
7018 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
+
7019 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
+
7020 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
+
7021 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
+
7022 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
+
7023 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
+
7024 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
+
7025 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
+
7026 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
+
7027 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
+
7028 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
+
7029 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
+
7030 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
+
7031 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
+
7032 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
+
7033 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
+
7034 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
+
7035 
+
7036 /******************** Bit definition for RCC_AHB2LPENR register *************/
+
7037 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
+
7038 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
+
7039 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
+
7040 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
+
7041 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
+
7042 
+
7043 /******************** Bit definition for RCC_AHB3LPENR register *************/
+
7044 #if defined(STM32F40_41xxx)
+
7045 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
+
7046 #endif /* STM32F40_41xxx */
+
7047 
+
7048 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
7049 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
+
7050 #endif /* STM32F427_437xx || STM32F429_439xx */
+
7051 
+
7052 /******************** Bit definition for RCC_APB1LPENR register *************/
+
7053 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
+
7054 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
+
7055 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
+
7056 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
+
7057 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
+
7058 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
+
7059 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
+
7060 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
+
7061 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
+
7062 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
+
7063 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
+
7064 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
+
7065 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
+
7066 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
+
7067 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
+
7068 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
+
7069 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
+
7070 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
+
7071 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
+
7072 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
+
7073 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
+
7074 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
+
7075 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
+
7076 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
+
7077 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
+
7078 
+
7079 /******************** Bit definition for RCC_APB2LPENR register *************/
+
7080 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
+
7081 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
+
7082 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
+
7083 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
+
7084 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
+
7085 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
+
7086 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
+
7087 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
+
7088 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
+
7089 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
+
7090 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
+
7091 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
+
7092 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
+
7093 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
+
7094 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
+
7095 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
+
7096 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
+
7097 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
+
7098 
+
7099 /******************** Bit definition for RCC_BDCR register ******************/
+
7100 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
+
7101 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
+
7102 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
+
7103 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
+
7104 
+
7105 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
+
7106 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
+
7107 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
+
7108 
+
7109 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
+
7110 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
+
7111 
+
7112 /******************** Bit definition for RCC_CSR register *******************/
+
7113 #define RCC_CSR_LSION ((uint32_t)0x00000001)
+
7114 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
+
7115 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
+
7116 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
+
7117 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
+
7118 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
+
7119 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
+
7120 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
+
7121 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
+
7122 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
+
7123 
+
7124 /******************** Bit definition for RCC_SSCGR register *****************/
+
7125 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
+
7126 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
+
7127 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
+
7128 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
+
7129 
+
7130 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
+
7131 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
+
7132 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
+
7133 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
+
7134 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
+
7135 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
+
7136 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
+
7137 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
+
7138 
+
7139 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
+
7140 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
+
7141 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
+
7142 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
+
7143 
+
7144 /******************** Bit definition for RCC_PLLSAICFGR register ************/
+
7145 #define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)
+
7146 #define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)
+
7147 #define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)
+
7148 
+
7149 /******************** Bit definition for RCC_DCKCFGR register ***************/
+
7150 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
+
7151 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
+
7152 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
+
7153 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
+
7154 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
+
7155 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
+
7156 
+
7157 
+
7158 /******************************************************************************/
+
7159 /* */
+
7160 /* RNG */
+
7161 /* */
+
7162 /******************************************************************************/
+
7163 /******************** Bits definition for RNG_CR register *******************/
+
7164 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
+
7165 #define RNG_CR_IE ((uint32_t)0x00000008)
+
7166 
+
7167 /******************** Bits definition for RNG_SR register *******************/
+
7168 #define RNG_SR_DRDY ((uint32_t)0x00000001)
+
7169 #define RNG_SR_CECS ((uint32_t)0x00000002)
+
7170 #define RNG_SR_SECS ((uint32_t)0x00000004)
+
7171 #define RNG_SR_CEIS ((uint32_t)0x00000020)
+
7172 #define RNG_SR_SEIS ((uint32_t)0x00000040)
+
7173 
+
7174 /******************************************************************************/
+
7175 /* */
+
7176 /* Real-Time Clock (RTC) */
+
7177 /* */
+
7178 /******************************************************************************/
+
7179 /******************** Bits definition for RTC_TR register *******************/
+
7180 #define RTC_TR_PM ((uint32_t)0x00400000)
+
7181 #define RTC_TR_HT ((uint32_t)0x00300000)
+
7182 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
+
7183 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
+
7184 #define RTC_TR_HU ((uint32_t)0x000F0000)
+
7185 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
+
7186 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
+
7187 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
+
7188 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
+
7189 #define RTC_TR_MNT ((uint32_t)0x00007000)
+
7190 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+
7191 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+
7192 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+
7193 #define RTC_TR_MNU ((uint32_t)0x00000F00)
+
7194 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+
7195 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+
7196 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+
7197 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+
7198 #define RTC_TR_ST ((uint32_t)0x00000070)
+
7199 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
+
7200 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
+
7201 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
+
7202 #define RTC_TR_SU ((uint32_t)0x0000000F)
+
7203 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
+
7204 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
+
7205 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
+
7206 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
7207 
+
7208 /******************** Bits definition for RTC_DR register *******************/
+
7209 #define RTC_DR_YT ((uint32_t)0x00F00000)
+
7210 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
+
7211 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
+
7212 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
+
7213 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
+
7214 #define RTC_DR_YU ((uint32_t)0x000F0000)
+
7215 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
+
7216 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
+
7217 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
+
7218 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
+
7219 #define RTC_DR_WDU ((uint32_t)0x0000E000)
+
7220 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+
7221 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+
7222 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+
7223 #define RTC_DR_MT ((uint32_t)0x00001000)
+
7224 #define RTC_DR_MU ((uint32_t)0x00000F00)
+
7225 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
+
7226 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
+
7227 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
+
7228 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
+
7229 #define RTC_DR_DT ((uint32_t)0x00000030)
+
7230 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
+
7231 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
+
7232 #define RTC_DR_DU ((uint32_t)0x0000000F)
+
7233 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
+
7234 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
+
7235 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
+
7236 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
7237 
+
7238 /******************** Bits definition for RTC_CR register *******************/
+
7239 #define RTC_CR_COE ((uint32_t)0x00800000)
+
7240 #define RTC_CR_OSEL ((uint32_t)0x00600000)
+
7241 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+
7242 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+
7243 #define RTC_CR_POL ((uint32_t)0x00100000)
+
7244 #define RTC_CR_COSEL ((uint32_t)0x00080000)
+
7245 #define RTC_CR_BCK ((uint32_t)0x00040000)
+
7246 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
+
7247 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
+
7248 #define RTC_CR_TSIE ((uint32_t)0x00008000)
+
7249 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
+
7250 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+
7251 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+
7252 #define RTC_CR_TSE ((uint32_t)0x00000800)
+
7253 #define RTC_CR_WUTE ((uint32_t)0x00000400)
+
7254 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
+
7255 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
+
7256 #define RTC_CR_DCE ((uint32_t)0x00000080)
+
7257 #define RTC_CR_FMT ((uint32_t)0x00000040)
+
7258 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+
7259 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
+
7260 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
7261 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+
7262 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+
7263 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+
7264 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
7265 
+
7266 /******************** Bits definition for RTC_ISR register ******************/
+
7267 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+
7268 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+
7269 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+
7270 #define RTC_ISR_TSF ((uint32_t)0x00000800)
+
7271 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
+
7272 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+
7273 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+
7274 #define RTC_ISR_INIT ((uint32_t)0x00000080)
+
7275 #define RTC_ISR_INITF ((uint32_t)0x00000040)
+
7276 #define RTC_ISR_RSF ((uint32_t)0x00000020)
+
7277 #define RTC_ISR_INITS ((uint32_t)0x00000010)
+
7278 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
+
7279 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+
7280 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+
7281 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
7282 
+
7283 /******************** Bits definition for RTC_PRER register *****************/
+
7284 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+
7285 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
+
7286 
+
7287 /******************** Bits definition for RTC_WUTR register *****************/
+
7288 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
7289 
+
7290 /******************** Bits definition for RTC_CALIBR register ***************/
+
7291 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+
7292 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
7293 
+
7294 /******************** Bits definition for RTC_ALRMAR register ***************/
+
7295 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+
7296 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+
7297 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+
7298 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+
7299 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+
7300 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+
7301 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+
7302 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+
7303 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+
7304 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+
7305 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+
7306 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+
7307 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+
7308 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+
7309 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+
7310 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+
7311 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+
7312 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+
7313 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+
7314 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+
7315 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+
7316 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+
7317 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+
7318 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+
7319 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+
7320 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+
7321 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+
7322 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+
7323 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+
7324 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+
7325 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+
7326 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+
7327 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+
7328 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+
7329 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+
7330 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+
7331 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+
7332 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+
7333 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+
7334 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
7335 
+
7336 /******************** Bits definition for RTC_ALRMBR register ***************/
+
7337 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+
7338 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+
7339 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+
7340 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+
7341 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+
7342 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+
7343 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+
7344 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+
7345 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+
7346 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+
7347 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+
7348 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+
7349 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+
7350 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+
7351 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+
7352 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+
7353 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+
7354 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+
7355 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+
7356 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+
7357 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+
7358 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+
7359 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+
7360 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+
7361 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+
7362 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+
7363 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+
7364 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+
7365 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+
7366 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+
7367 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+
7368 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+
7369 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+
7370 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+
7371 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+
7372 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+
7373 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+
7374 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+
7375 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+
7376 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
7377 
+
7378 /******************** Bits definition for RTC_WPR register ******************/
+
7379 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
7380 
+
7381 /******************** Bits definition for RTC_SSR register ******************/
+
7382 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
7383 
+
7384 /******************** Bits definition for RTC_SHIFTR register ***************/
+
7385 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+
7386 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
7387 
+
7388 /******************** Bits definition for RTC_TSTR register *****************/
+
7389 #define RTC_TSTR_PM ((uint32_t)0x00400000)
+
7390 #define RTC_TSTR_HT ((uint32_t)0x00300000)
+
7391 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+
7392 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+
7393 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
+
7394 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+
7395 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+
7396 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+
7397 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+
7398 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
+
7399 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+
7400 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+
7401 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+
7402 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+
7403 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+
7404 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+
7405 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+
7406 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+
7407 #define RTC_TSTR_ST ((uint32_t)0x00000070)
+
7408 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+
7409 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+
7410 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+
7411 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
+
7412 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+
7413 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+
7414 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+
7415 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
7416 
+
7417 /******************** Bits definition for RTC_TSDR register *****************/
+
7418 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+
7419 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+
7420 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+
7421 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+
7422 #define RTC_TSDR_MT ((uint32_t)0x00001000)
+
7423 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
+
7424 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+
7425 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+
7426 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+
7427 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+
7428 #define RTC_TSDR_DT ((uint32_t)0x00000030)
+
7429 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+
7430 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+
7431 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
+
7432 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+
7433 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+
7434 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+
7435 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
7436 
+
7437 /******************** Bits definition for RTC_TSSSR register ****************/
+
7438 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
7439 
+
7440 /******************** Bits definition for RTC_CAL register *****************/
+
7441 #define RTC_CALR_CALP ((uint32_t)0x00008000)
+
7442 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+
7443 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+
7444 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
+
7445 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+
7446 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+
7447 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+
7448 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+
7449 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+
7450 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+
7451 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+
7452 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+
7453 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
7454 
+
7455 /******************** Bits definition for RTC_TAFCR register ****************/
+
7456 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+
7457 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
+
7458 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
+
7459 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+
7460 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+
7461 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+
7462 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+
7463 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+
7464 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+
7465 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+
7466 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+
7467 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+
7468 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+
7469 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+
7470 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+
7471 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+
7472 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+
7473 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
7474 
+
7475 /******************** Bits definition for RTC_ALRMASSR register *************/
+
7476 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+
7477 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+
7478 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+
7479 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+
7480 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+
7481 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
7482 
+
7483 /******************** Bits definition for RTC_ALRMBSSR register *************/
+
7484 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+
7485 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+
7486 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+
7487 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+
7488 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+
7489 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
7490 
+
7491 /******************** Bits definition for RTC_BKP0R register ****************/
+
7492 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
7493 
+
7494 /******************** Bits definition for RTC_BKP1R register ****************/
+
7495 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
7496 
+
7497 /******************** Bits definition for RTC_BKP2R register ****************/
+
7498 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
7499 
+
7500 /******************** Bits definition for RTC_BKP3R register ****************/
+
7501 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
7502 
+
7503 /******************** Bits definition for RTC_BKP4R register ****************/
+
7504 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
7505 
+
7506 /******************** Bits definition for RTC_BKP5R register ****************/
+
7507 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
7508 
+
7509 /******************** Bits definition for RTC_BKP6R register ****************/
+
7510 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
7511 
+
7512 /******************** Bits definition for RTC_BKP7R register ****************/
+
7513 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
7514 
+
7515 /******************** Bits definition for RTC_BKP8R register ****************/
+
7516 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
7517 
+
7518 /******************** Bits definition for RTC_BKP9R register ****************/
+
7519 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
7520 
+
7521 /******************** Bits definition for RTC_BKP10R register ***************/
+
7522 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
7523 
+
7524 /******************** Bits definition for RTC_BKP11R register ***************/
+
7525 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
7526 
+
7527 /******************** Bits definition for RTC_BKP12R register ***************/
+
7528 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
7529 
+
7530 /******************** Bits definition for RTC_BKP13R register ***************/
+
7531 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
7532 
+
7533 /******************** Bits definition for RTC_BKP14R register ***************/
+
7534 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
7535 
+
7536 /******************** Bits definition for RTC_BKP15R register ***************/
+
7537 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
7538 
+
7539 /******************** Bits definition for RTC_BKP16R register ***************/
+
7540 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
7541 
+
7542 /******************** Bits definition for RTC_BKP17R register ***************/
+
7543 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
7544 
+
7545 /******************** Bits definition for RTC_BKP18R register ***************/
+
7546 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
7547 
+
7548 /******************** Bits definition for RTC_BKP19R register ***************/
+
7549 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
7550 
+
7551 /******************************************************************************/
+
7552 /* */
+
7553 /* Serial Audio Interface */
+
7554 /* */
+
7555 /******************************************************************************/
+
7556 /******************** Bit definition for SAI_GCR register *******************/
+
7557 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003)
+
7558 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001)
+
7559 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002)
+
7561 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030)
+
7562 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010)
+
7563 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020)
+
7565 /******************* Bit definition for SAI_xCR1 register *******************/
+
7566 #define SAI_xCR1_MODE ((uint32_t)0x00000003)
+
7567 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001)
+
7568 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002)
+
7570 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C)
+
7571 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004)
+
7572 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008)
+
7574 #define SAI_xCR1_DS ((uint32_t)0x000000E0)
+
7575 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020)
+
7576 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040)
+
7577 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080)
+
7579 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100)
+
7580 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200)
+
7582 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00)
+
7583 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400)
+
7584 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800)
+
7586 #define SAI_xCR1_MONO ((uint32_t)0x00001000)
+
7587 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000)
+
7588 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000)
+
7589 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000)
+
7590 #define SAI_xCR1_NODIV ((uint32_t)0x00080000)
+
7592 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000)
+
7593 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000)
+
7594 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000)
+
7595 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000)
+
7596 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000)
+
7598 /******************* Bit definition for SAI_xCR2 register *******************/
+
7599 #define SAI_xCR2_FTH ((uint32_t)0x00000003)
+
7600 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001)
+
7601 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002)
+
7603 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008)
+
7604 #define SAI_xCR2_TRIS ((uint32_t)0x00000010)
+
7605 #define SAI_xCR2_MUTE ((uint32_t)0x00000020)
+
7606 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040)
+
7608 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80)
+
7609 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080)
+
7610 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100)
+
7611 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200)
+
7612 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400)
+
7613 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800)
+
7614 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000)
+
7616 #define SAI_xCR2_CPL ((uint32_t)0x00080000)
+
7618 #define SAI_xCR2_COMP ((uint32_t)0x0000C000)
+
7619 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000)
+
7620 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000)
+
7622 /****************** Bit definition for SAI_xFRCR register *******************/
+
7623 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF)
+
7624 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001)
+
7625 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002)
+
7626 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004)
+
7627 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008)
+
7628 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010)
+
7629 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020)
+
7630 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040)
+
7631 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080)
+
7633 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00)
+
7634 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100)
+
7635 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200)
+
7636 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400)
+
7637 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800)
+
7638 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000)
+
7639 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000)
+
7640 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000)
+
7642 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000)
+
7643 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000)
+
7644 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000)
+
7646 /****************** Bit definition for SAI_xSLOTR register *******************/
+
7647 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F)
+
7648 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001)
+
7649 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002)
+
7650 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004)
+
7651 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008)
+
7652 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010)
+
7654 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0)
+
7655 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040)
+
7656 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080)
+
7658 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00)
+
7659 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100)
+
7660 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200)
+
7661 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400)
+
7662 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800)
+
7664 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000)
+
7666 /******************* Bit definition for SAI_xIMR register *******************/
+
7667 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001)
+
7668 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002)
+
7669 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004)
+
7670 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008)
+
7671 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010)
+
7672 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020)
+
7673 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040)
+
7675 /******************** Bit definition for SAI_xSR register *******************/
+
7676 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001)
+
7677 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002)
+
7678 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004)
+
7679 #define SAI_xSR_FREQ ((uint32_t)0x00000008)
+
7680 #define SAI_xSR_CNRDY ((uint32_t)0x00000010)
+
7681 #define SAI_xSR_AFSDET ((uint32_t)0x00000020)
+
7682 #define SAI_xSR_LFSDET ((uint32_t)0x00000040)
+
7684 #define SAI_xSR_FLVL ((uint32_t)0x00070000)
+
7685 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000)
+
7686 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000)
+
7687 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000)
+
7689 /****************** Bit definition for SAI_xCLRFR register ******************/
+
7690 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001)
+
7691 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002)
+
7692 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004)
+
7693 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008)
+
7694 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010)
+
7695 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020)
+
7696 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040)
+
7698 /****************** Bit definition for SAI_xDR register ******************/
+
7699 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
+
7700 
+
7701 /******************************************************************************/
+
7702 /* */
+
7703 /* SD host Interface */
+
7704 /* */
+
7705 /******************************************************************************/
+
7706 /****************** Bit definition for SDIO_POWER register ******************/
+
7707 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03)
+
7708 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)
+
7709 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)
+
7711 /****************** Bit definition for SDIO_CLKCR register ******************/
+
7712 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)
+
7713 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100)
+
7714 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)
+
7715 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400)
+
7717 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)
+
7718 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)
+
7719 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)
+
7721 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)
+
7722 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)
+
7724 /******************* Bit definition for SDIO_ARG register *******************/
+
7725 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)
+
7727 /******************* Bit definition for SDIO_CMD register *******************/
+
7728 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F)
+
7730 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0)
+
7731 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)
+
7732 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)
+
7734 #define SDIO_CMD_WAITINT ((uint16_t)0x0100)
+
7735 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200)
+
7736 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400)
+
7737 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
+
7738 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)
+
7739 #define SDIO_CMD_NIEN ((uint16_t)0x2000)
+
7740 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000)
+
7742 /***************** Bit definition for SDIO_RESPCMD register *****************/
+
7743 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)
+
7745 /****************** Bit definition for SDIO_RESP0 register ******************/
+
7746 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)
+
7748 /****************** Bit definition for SDIO_RESP1 register ******************/
+
7749 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)
+
7751 /****************** Bit definition for SDIO_RESP2 register ******************/
+
7752 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)
+
7754 /****************** Bit definition for SDIO_RESP3 register ******************/
+
7755 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)
+
7757 /****************** Bit definition for SDIO_RESP4 register ******************/
+
7758 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)
+
7760 /****************** Bit definition for SDIO_DTIMER register *****************/
+
7761 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)
+
7763 /****************** Bit definition for SDIO_DLEN register *******************/
+
7764 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)
+
7766 /****************** Bit definition for SDIO_DCTRL register ******************/
+
7767 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001)
+
7768 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002)
+
7769 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004)
+
7770 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008)
+
7772 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)
+
7773 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)
+
7774 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)
+
7775 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)
+
7776 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)
+
7778 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100)
+
7779 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)
+
7780 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400)
+
7781 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)
+
7783 /****************** Bit definition for SDIO_DCOUNT register *****************/
+
7784 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)
+
7786 /****************** Bit definition for SDIO_STA register ********************/
+
7787 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)
+
7788 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)
+
7789 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)
+
7790 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)
+
7791 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010)
+
7792 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020)
+
7793 #define SDIO_STA_CMDREND ((uint32_t)0x00000040)
+
7794 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080)
+
7795 #define SDIO_STA_DATAEND ((uint32_t)0x00000100)
+
7796 #define SDIO_STA_STBITERR ((uint32_t)0x00000200)
+
7797 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400)
+
7798 #define SDIO_STA_CMDACT ((uint32_t)0x00000800)
+
7799 #define SDIO_STA_TXACT ((uint32_t)0x00001000)
+
7800 #define SDIO_STA_RXACT ((uint32_t)0x00002000)
+
7801 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)
+
7802 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)
+
7803 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
+
7804 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000)
+
7805 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000)
+
7806 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000)
+
7807 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000)
+
7808 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000)
+
7809 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000)
+
7810 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000)
+
7812 /******************* Bit definition for SDIO_ICR register *******************/
+
7813 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)
+
7814 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)
+
7815 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)
+
7816 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)
+
7817 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)
+
7818 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)
+
7819 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)
+
7820 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)
+
7821 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100)
+
7822 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200)
+
7823 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)
+
7824 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
+
7825 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)
+
7827 /****************** Bit definition for SDIO_MASK register *******************/
+
7828 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)
+
7829 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)
+
7830 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)
+
7831 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)
+
7832 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)
+
7833 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)
+
7834 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)
+
7835 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)
+
7836 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)
+
7837 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)
+
7838 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)
+
7839 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)
+
7840 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000)
+
7841 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000)
+
7842 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)
+
7843 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)
+
7844 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)
+
7845 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)
+
7846 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)
+
7847 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)
+
7848 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)
+
7849 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)
+
7850 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)
+
7851 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)
+
7853 /***************** Bit definition for SDIO_FIFOCNT register *****************/
+
7854 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)
+
7856 /****************** Bit definition for SDIO_FIFO register *******************/
+
7857 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
+
7859 /******************************************************************************/
+
7860 /* */
+
7861 /* Serial Peripheral Interface */
+
7862 /* */
+
7863 /******************************************************************************/
+
7864 /******************* Bit definition for SPI_CR1 register ********************/
+
7865 #define SPI_CR1_CPHA ((uint16_t)0x0001)
+
7866 #define SPI_CR1_CPOL ((uint16_t)0x0002)
+
7867 #define SPI_CR1_MSTR ((uint16_t)0x0004)
+
7869 #define SPI_CR1_BR ((uint16_t)0x0038)
+
7870 #define SPI_CR1_BR_0 ((uint16_t)0x0008)
+
7871 #define SPI_CR1_BR_1 ((uint16_t)0x0010)
+
7872 #define SPI_CR1_BR_2 ((uint16_t)0x0020)
+
7874 #define SPI_CR1_SPE ((uint16_t)0x0040)
+
7875 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080)
+
7876 #define SPI_CR1_SSI ((uint16_t)0x0100)
+
7877 #define SPI_CR1_SSM ((uint16_t)0x0200)
+
7878 #define SPI_CR1_RXONLY ((uint16_t)0x0400)
+
7879 #define SPI_CR1_DFF ((uint16_t)0x0800)
+
7880 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000)
+
7881 #define SPI_CR1_CRCEN ((uint16_t)0x2000)
+
7882 #define SPI_CR1_BIDIOE ((uint16_t)0x4000)
+
7883 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000)
+
7885 /******************* Bit definition for SPI_CR2 register ********************/
+
7886 #define SPI_CR2_RXDMAEN ((uint8_t)0x01)
+
7887 #define SPI_CR2_TXDMAEN ((uint8_t)0x02)
+
7888 #define SPI_CR2_SSOE ((uint8_t)0x04)
+
7889 #define SPI_CR2_ERRIE ((uint8_t)0x20)
+
7890 #define SPI_CR2_RXNEIE ((uint8_t)0x40)
+
7891 #define SPI_CR2_TXEIE ((uint8_t)0x80)
+
7893 /******************** Bit definition for SPI_SR register ********************/
+
7894 #define SPI_SR_RXNE ((uint8_t)0x01)
+
7895 #define SPI_SR_TXE ((uint8_t)0x02)
+
7896 #define SPI_SR_CHSIDE ((uint8_t)0x04)
+
7897 #define SPI_SR_UDR ((uint8_t)0x08)
+
7898 #define SPI_SR_CRCERR ((uint8_t)0x10)
+
7899 #define SPI_SR_MODF ((uint8_t)0x20)
+
7900 #define SPI_SR_OVR ((uint8_t)0x40)
+
7901 #define SPI_SR_BSY ((uint8_t)0x80)
+
7903 /******************** Bit definition for SPI_DR register ********************/
+
7904 #define SPI_DR_DR ((uint16_t)0xFFFF)
+
7906 /******************* Bit definition for SPI_CRCPR register ******************/
+
7907 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)
+
7909 /****************** Bit definition for SPI_RXCRCR register ******************/
+
7910 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)
+
7912 /****************** Bit definition for SPI_TXCRCR register ******************/
+
7913 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)
+
7915 /****************** Bit definition for SPI_I2SCFGR register *****************/
+
7916 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)
+
7918 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)
+
7919 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)
+
7920 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)
+
7922 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)
+
7924 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)
+
7925 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)
+
7926 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)
+
7928 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)
+
7930 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)
+
7931 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)
+
7932 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
+
7934 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400)
+
7935 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)
+
7937 /****************** Bit definition for SPI_I2SPR register *******************/
+
7938 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)
+
7939 #define SPI_I2SPR_ODD ((uint16_t)0x0100)
+
7940 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200)
+
7942 /******************************************************************************/
+
7943 /* */
+
7944 /* SYSCFG */
+
7945 /* */
+
7946 /******************************************************************************/
+
7947 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
+
7948 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007)
+
7949 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
+
7950 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
+
7951 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
+
7953 #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100)
+
7955 #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00)
+
7956 #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
+
7957 #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
+
7960 /****************** Bit definition for SYSCFG_PMC register ******************/
+
7961 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000)
+
7962 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000)
+
7963 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000)
+
7964 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000)
+
7966 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000)
+
7967 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+
7968 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
7969 
+
7970 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+
7971 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F)
+
7972 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0)
+
7973 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00)
+
7974 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000)
+
7978 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
+
7979 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
+
7980 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
+
7981 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
+
7982 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
+
7983 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005)
+
7984 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006)
+
7985 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007)
+
7986 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008)
+
7987 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009)
+
7988 #define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A)
+
7993 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
+
7994 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
+
7995 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
+
7996 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
+
7997 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
+
7998 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050)
+
7999 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060)
+
8000 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070)
+
8001 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080)
+
8002 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090)
+
8003 #define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0)
+
8008 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
+
8009 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
+
8010 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
+
8011 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
+
8012 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
+
8013 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500)
+
8014 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600)
+
8015 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700)
+
8016 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800)
+
8017 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900)
+
8018 #define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00)
+
8023 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
+
8024 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
+
8025 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
+
8026 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
+
8027 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
+
8028 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000)
+
8029 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000)
+
8030 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000)
+
8031 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000)
+
8032 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000)
+
8033 #define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000)
+
8035 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+
8036 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F)
+
8037 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0)
+
8038 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00)
+
8039 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000)
+
8043 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
+
8044 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
+
8045 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
+
8046 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
+
8047 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
+
8048 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005)
+
8049 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006)
+
8050 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007)
+
8051 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008)
+
8052 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009)
+
8053 #define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A)
+
8058 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
+
8059 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
+
8060 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
+
8061 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
+
8062 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
+
8063 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050)
+
8064 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060)
+
8065 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070)
+
8066 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080)
+
8067 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090)
+
8068 #define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0)
+
8073 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
+
8074 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
+
8075 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
+
8076 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
+
8077 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
+
8078 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500)
+
8079 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600)
+
8080 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700)
+
8081 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800)
+
8082 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900)
+
8083 #define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00)
+
8088 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
+
8089 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
+
8090 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
+
8091 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
+
8092 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
+
8093 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000)
+
8094 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000)
+
8095 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000)
+
8096 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000)
+
8097 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000)
+
8098 #define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000)
+
8100 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+
8101 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F)
+
8102 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0)
+
8103 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00)
+
8104 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000)
+
8109 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
+
8110 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
+
8111 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
+
8112 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
+
8113 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
+
8114 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005)
+
8115 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006)
+
8116 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007)
+
8117 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008)
+
8118 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009)
+
8123 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
+
8124 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
+
8125 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
+
8126 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
+
8127 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
+
8128 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050)
+
8129 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060)
+
8130 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070)
+
8131 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080)
+
8132 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090)
+
8137 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
+
8138 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
+
8139 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
+
8140 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
+
8141 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
+
8142 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500)
+
8143 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600)
+
8144 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700)
+
8145 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800)
+
8146 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900)
+
8151 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
+
8152 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
+
8153 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
+
8154 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
+
8155 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
+
8156 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000)
+
8157 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000)
+
8158 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000)
+
8159 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000)
+
8160 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000)
+
8162 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+
8163 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F)
+
8164 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0)
+
8165 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00)
+
8166 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)
+
8170 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
+
8171 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
+
8172 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
+
8173 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
+
8174 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
+
8175 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005)
+
8176 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006)
+
8177 #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007)
+
8178 #define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008)
+
8179 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009)
+
8184 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
+
8185 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
+
8186 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
+
8187 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
+
8188 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
+
8189 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050)
+
8190 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060)
+
8191 #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070)
+
8192 #define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008)
+
8193 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009)
+
8198 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
+
8199 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
+
8200 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
+
8201 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
+
8202 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
+
8203 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500)
+
8204 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600)
+
8205 #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700)
+
8206 #define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800)
+
8207 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900)
+
8212 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
+
8213 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
+
8214 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
+
8215 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
+
8216 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
+
8217 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000)
+
8218 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000)
+
8219 #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000)
+
8220 #define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000)
+
8221 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000)
+
8223 /****************** Bit definition for SYSCFG_CMPCR register ****************/
+
8224 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001)
+
8225 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100)
+
8227 /******************************************************************************/
+
8228 /* */
+
8229 /* TIM */
+
8230 /* */
+
8231 /******************************************************************************/
+
8232 /******************* Bit definition for TIM_CR1 register ********************/
+
8233 #define TIM_CR1_CEN ((uint16_t)0x0001)
+
8234 #define TIM_CR1_UDIS ((uint16_t)0x0002)
+
8235 #define TIM_CR1_URS ((uint16_t)0x0004)
+
8236 #define TIM_CR1_OPM ((uint16_t)0x0008)
+
8237 #define TIM_CR1_DIR ((uint16_t)0x0010)
+
8239 #define TIM_CR1_CMS ((uint16_t)0x0060)
+
8240 #define TIM_CR1_CMS_0 ((uint16_t)0x0020)
+
8241 #define TIM_CR1_CMS_1 ((uint16_t)0x0040)
+
8243 #define TIM_CR1_ARPE ((uint16_t)0x0080)
+
8245 #define TIM_CR1_CKD ((uint16_t)0x0300)
+
8246 #define TIM_CR1_CKD_0 ((uint16_t)0x0100)
+
8247 #define TIM_CR1_CKD_1 ((uint16_t)0x0200)
+
8249 /******************* Bit definition for TIM_CR2 register ********************/
+
8250 #define TIM_CR2_CCPC ((uint16_t)0x0001)
+
8251 #define TIM_CR2_CCUS ((uint16_t)0x0004)
+
8252 #define TIM_CR2_CCDS ((uint16_t)0x0008)
+
8254 #define TIM_CR2_MMS ((uint16_t)0x0070)
+
8255 #define TIM_CR2_MMS_0 ((uint16_t)0x0010)
+
8256 #define TIM_CR2_MMS_1 ((uint16_t)0x0020)
+
8257 #define TIM_CR2_MMS_2 ((uint16_t)0x0040)
+
8259 #define TIM_CR2_TI1S ((uint16_t)0x0080)
+
8260 #define TIM_CR2_OIS1 ((uint16_t)0x0100)
+
8261 #define TIM_CR2_OIS1N ((uint16_t)0x0200)
+
8262 #define TIM_CR2_OIS2 ((uint16_t)0x0400)
+
8263 #define TIM_CR2_OIS2N ((uint16_t)0x0800)
+
8264 #define TIM_CR2_OIS3 ((uint16_t)0x1000)
+
8265 #define TIM_CR2_OIS3N ((uint16_t)0x2000)
+
8266 #define TIM_CR2_OIS4 ((uint16_t)0x4000)
+
8268 /******************* Bit definition for TIM_SMCR register *******************/
+
8269 #define TIM_SMCR_SMS ((uint16_t)0x0007)
+
8270 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001)
+
8271 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002)
+
8272 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004)
+
8274 #define TIM_SMCR_TS ((uint16_t)0x0070)
+
8275 #define TIM_SMCR_TS_0 ((uint16_t)0x0010)
+
8276 #define TIM_SMCR_TS_1 ((uint16_t)0x0020)
+
8277 #define TIM_SMCR_TS_2 ((uint16_t)0x0040)
+
8279 #define TIM_SMCR_MSM ((uint16_t)0x0080)
+
8281 #define TIM_SMCR_ETF ((uint16_t)0x0F00)
+
8282 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100)
+
8283 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200)
+
8284 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400)
+
8285 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800)
+
8287 #define TIM_SMCR_ETPS ((uint16_t)0x3000)
+
8288 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
+
8289 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
+
8291 #define TIM_SMCR_ECE ((uint16_t)0x4000)
+
8292 #define TIM_SMCR_ETP ((uint16_t)0x8000)
+
8294 /******************* Bit definition for TIM_DIER register *******************/
+
8295 #define TIM_DIER_UIE ((uint16_t)0x0001)
+
8296 #define TIM_DIER_CC1IE ((uint16_t)0x0002)
+
8297 #define TIM_DIER_CC2IE ((uint16_t)0x0004)
+
8298 #define TIM_DIER_CC3IE ((uint16_t)0x0008)
+
8299 #define TIM_DIER_CC4IE ((uint16_t)0x0010)
+
8300 #define TIM_DIER_COMIE ((uint16_t)0x0020)
+
8301 #define TIM_DIER_TIE ((uint16_t)0x0040)
+
8302 #define TIM_DIER_BIE ((uint16_t)0x0080)
+
8303 #define TIM_DIER_UDE ((uint16_t)0x0100)
+
8304 #define TIM_DIER_CC1DE ((uint16_t)0x0200)
+
8305 #define TIM_DIER_CC2DE ((uint16_t)0x0400)
+
8306 #define TIM_DIER_CC3DE ((uint16_t)0x0800)
+
8307 #define TIM_DIER_CC4DE ((uint16_t)0x1000)
+
8308 #define TIM_DIER_COMDE ((uint16_t)0x2000)
+
8309 #define TIM_DIER_TDE ((uint16_t)0x4000)
+
8311 /******************** Bit definition for TIM_SR register ********************/
+
8312 #define TIM_SR_UIF ((uint16_t)0x0001)
+
8313 #define TIM_SR_CC1IF ((uint16_t)0x0002)
+
8314 #define TIM_SR_CC2IF ((uint16_t)0x0004)
+
8315 #define TIM_SR_CC3IF ((uint16_t)0x0008)
+
8316 #define TIM_SR_CC4IF ((uint16_t)0x0010)
+
8317 #define TIM_SR_COMIF ((uint16_t)0x0020)
+
8318 #define TIM_SR_TIF ((uint16_t)0x0040)
+
8319 #define TIM_SR_BIF ((uint16_t)0x0080)
+
8320 #define TIM_SR_CC1OF ((uint16_t)0x0200)
+
8321 #define TIM_SR_CC2OF ((uint16_t)0x0400)
+
8322 #define TIM_SR_CC3OF ((uint16_t)0x0800)
+
8323 #define TIM_SR_CC4OF ((uint16_t)0x1000)
+
8325 /******************* Bit definition for TIM_EGR register ********************/
+
8326 #define TIM_EGR_UG ((uint8_t)0x01)
+
8327 #define TIM_EGR_CC1G ((uint8_t)0x02)
+
8328 #define TIM_EGR_CC2G ((uint8_t)0x04)
+
8329 #define TIM_EGR_CC3G ((uint8_t)0x08)
+
8330 #define TIM_EGR_CC4G ((uint8_t)0x10)
+
8331 #define TIM_EGR_COMG ((uint8_t)0x20)
+
8332 #define TIM_EGR_TG ((uint8_t)0x40)
+
8333 #define TIM_EGR_BG ((uint8_t)0x80)
+
8335 /****************** Bit definition for TIM_CCMR1 register *******************/
+
8336 #define TIM_CCMR1_CC1S ((uint16_t)0x0003)
+
8337 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
+
8338 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
+
8340 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004)
+
8341 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008)
+
8343 #define TIM_CCMR1_OC1M ((uint16_t)0x0070)
+
8344 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
+
8345 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
+
8346 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
+
8348 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080)
+
8350 #define TIM_CCMR1_CC2S ((uint16_t)0x0300)
+
8351 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
+
8352 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
+
8354 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400)
+
8355 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800)
+
8357 #define TIM_CCMR1_OC2M ((uint16_t)0x7000)
+
8358 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
+
8359 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
+
8360 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
+
8362 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000)
+
8364 /*----------------------------------------------------------------------------*/
+
8365 
+
8366 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
+
8367 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
+
8368 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
+
8370 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0)
+
8371 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
+
8372 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
+
8373 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
+
8374 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
+
8376 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
+
8377 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
+
8378 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
+
8380 #define TIM_CCMR1_IC2F ((uint16_t)0xF000)
+
8381 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
+
8382 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
+
8383 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
+
8384 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
+
8386 /****************** Bit definition for TIM_CCMR2 register *******************/
+
8387 #define TIM_CCMR2_CC3S ((uint16_t)0x0003)
+
8388 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
+
8389 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
+
8391 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004)
+
8392 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008)
+
8394 #define TIM_CCMR2_OC3M ((uint16_t)0x0070)
+
8395 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
+
8396 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
+
8397 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
+
8399 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080)
+
8401 #define TIM_CCMR2_CC4S ((uint16_t)0x0300)
+
8402 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
+
8403 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
+
8405 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400)
+
8406 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800)
+
8408 #define TIM_CCMR2_OC4M ((uint16_t)0x7000)
+
8409 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
+
8410 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
+
8411 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
+
8413 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000)
+
8415 /*----------------------------------------------------------------------------*/
+
8416 
+
8417 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
+
8418 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
+
8419 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
+
8421 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0)
+
8422 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
+
8423 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
+
8424 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
+
8425 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
+
8427 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
+
8428 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
+
8429 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
+
8431 #define TIM_CCMR2_IC4F ((uint16_t)0xF000)
+
8432 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
+
8433 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
+
8434 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
+
8435 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
+
8437 /******************* Bit definition for TIM_CCER register *******************/
+
8438 #define TIM_CCER_CC1E ((uint16_t)0x0001)
+
8439 #define TIM_CCER_CC1P ((uint16_t)0x0002)
+
8440 #define TIM_CCER_CC1NE ((uint16_t)0x0004)
+
8441 #define TIM_CCER_CC1NP ((uint16_t)0x0008)
+
8442 #define TIM_CCER_CC2E ((uint16_t)0x0010)
+
8443 #define TIM_CCER_CC2P ((uint16_t)0x0020)
+
8444 #define TIM_CCER_CC2NE ((uint16_t)0x0040)
+
8445 #define TIM_CCER_CC2NP ((uint16_t)0x0080)
+
8446 #define TIM_CCER_CC3E ((uint16_t)0x0100)
+
8447 #define TIM_CCER_CC3P ((uint16_t)0x0200)
+
8448 #define TIM_CCER_CC3NE ((uint16_t)0x0400)
+
8449 #define TIM_CCER_CC3NP ((uint16_t)0x0800)
+
8450 #define TIM_CCER_CC4E ((uint16_t)0x1000)
+
8451 #define TIM_CCER_CC4P ((uint16_t)0x2000)
+
8452 #define TIM_CCER_CC4NP ((uint16_t)0x8000)
+
8454 /******************* Bit definition for TIM_CNT register ********************/
+
8455 #define TIM_CNT_CNT ((uint16_t)0xFFFF)
+
8457 /******************* Bit definition for TIM_PSC register ********************/
+
8458 #define TIM_PSC_PSC ((uint16_t)0xFFFF)
+
8460 /******************* Bit definition for TIM_ARR register ********************/
+
8461 #define TIM_ARR_ARR ((uint16_t)0xFFFF)
+
8463 /******************* Bit definition for TIM_RCR register ********************/
+
8464 #define TIM_RCR_REP ((uint8_t)0xFF)
+
8466 /******************* Bit definition for TIM_CCR1 register *******************/
+
8467 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
+
8469 /******************* Bit definition for TIM_CCR2 register *******************/
+
8470 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
+
8472 /******************* Bit definition for TIM_CCR3 register *******************/
+
8473 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
+
8475 /******************* Bit definition for TIM_CCR4 register *******************/
+
8476 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
+
8478 /******************* Bit definition for TIM_BDTR register *******************/
+
8479 #define TIM_BDTR_DTG ((uint16_t)0x00FF)
+
8480 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001)
+
8481 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002)
+
8482 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004)
+
8483 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008)
+
8484 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010)
+
8485 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020)
+
8486 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040)
+
8487 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080)
+
8489 #define TIM_BDTR_LOCK ((uint16_t)0x0300)
+
8490 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100)
+
8491 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200)
+
8493 #define TIM_BDTR_OSSI ((uint16_t)0x0400)
+
8494 #define TIM_BDTR_OSSR ((uint16_t)0x0800)
+
8495 #define TIM_BDTR_BKE ((uint16_t)0x1000)
+
8496 #define TIM_BDTR_BKP ((uint16_t)0x2000)
+
8497 #define TIM_BDTR_AOE ((uint16_t)0x4000)
+
8498 #define TIM_BDTR_MOE ((uint16_t)0x8000)
+
8500 /******************* Bit definition for TIM_DCR register ********************/
+
8501 #define TIM_DCR_DBA ((uint16_t)0x001F)
+
8502 #define TIM_DCR_DBA_0 ((uint16_t)0x0001)
+
8503 #define TIM_DCR_DBA_1 ((uint16_t)0x0002)
+
8504 #define TIM_DCR_DBA_2 ((uint16_t)0x0004)
+
8505 #define TIM_DCR_DBA_3 ((uint16_t)0x0008)
+
8506 #define TIM_DCR_DBA_4 ((uint16_t)0x0010)
+
8508 #define TIM_DCR_DBL ((uint16_t)0x1F00)
+
8509 #define TIM_DCR_DBL_0 ((uint16_t)0x0100)
+
8510 #define TIM_DCR_DBL_1 ((uint16_t)0x0200)
+
8511 #define TIM_DCR_DBL_2 ((uint16_t)0x0400)
+
8512 #define TIM_DCR_DBL_3 ((uint16_t)0x0800)
+
8513 #define TIM_DCR_DBL_4 ((uint16_t)0x1000)
+
8515 /******************* Bit definition for TIM_DMAR register *******************/
+
8516 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF)
+
8518 /******************* Bit definition for TIM_OR register *********************/
+
8519 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0)
+
8520 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040)
+
8521 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080)
+
8522 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00)
+
8523 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400)
+
8524 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800)
+
8527 /******************************************************************************/
+
8528 /* */
+
8529 /* Universal Synchronous Asynchronous Receiver Transmitter */
+
8530 /* */
+
8531 /******************************************************************************/
+
8532 /******************* Bit definition for USART_SR register *******************/
+
8533 #define USART_SR_PE ((uint16_t)0x0001)
+
8534 #define USART_SR_FE ((uint16_t)0x0002)
+
8535 #define USART_SR_NE ((uint16_t)0x0004)
+
8536 #define USART_SR_ORE ((uint16_t)0x0008)
+
8537 #define USART_SR_IDLE ((uint16_t)0x0010)
+
8538 #define USART_SR_RXNE ((uint16_t)0x0020)
+
8539 #define USART_SR_TC ((uint16_t)0x0040)
+
8540 #define USART_SR_TXE ((uint16_t)0x0080)
+
8541 #define USART_SR_LBD ((uint16_t)0x0100)
+
8542 #define USART_SR_CTS ((uint16_t)0x0200)
+
8544 /******************* Bit definition for USART_DR register *******************/
+
8545 #define USART_DR_DR ((uint16_t)0x01FF)
+
8547 /****************** Bit definition for USART_BRR register *******************/
+
8548 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F)
+
8549 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)
+
8551 /****************** Bit definition for USART_CR1 register *******************/
+
8552 #define USART_CR1_SBK ((uint16_t)0x0001)
+
8553 #define USART_CR1_RWU ((uint16_t)0x0002)
+
8554 #define USART_CR1_RE ((uint16_t)0x0004)
+
8555 #define USART_CR1_TE ((uint16_t)0x0008)
+
8556 #define USART_CR1_IDLEIE ((uint16_t)0x0010)
+
8557 #define USART_CR1_RXNEIE ((uint16_t)0x0020)
+
8558 #define USART_CR1_TCIE ((uint16_t)0x0040)
+
8559 #define USART_CR1_TXEIE ((uint16_t)0x0080)
+
8560 #define USART_CR1_PEIE ((uint16_t)0x0100)
+
8561 #define USART_CR1_PS ((uint16_t)0x0200)
+
8562 #define USART_CR1_PCE ((uint16_t)0x0400)
+
8563 #define USART_CR1_WAKE ((uint16_t)0x0800)
+
8564 #define USART_CR1_M ((uint16_t)0x1000)
+
8565 #define USART_CR1_UE ((uint16_t)0x2000)
+
8566 #define USART_CR1_OVER8 ((uint16_t)0x8000)
+
8568 /****************** Bit definition for USART_CR2 register *******************/
+
8569 #define USART_CR2_ADD ((uint16_t)0x000F)
+
8570 #define USART_CR2_LBDL ((uint16_t)0x0020)
+
8571 #define USART_CR2_LBDIE ((uint16_t)0x0040)
+
8572 #define USART_CR2_LBCL ((uint16_t)0x0100)
+
8573 #define USART_CR2_CPHA ((uint16_t)0x0200)
+
8574 #define USART_CR2_CPOL ((uint16_t)0x0400)
+
8575 #define USART_CR2_CLKEN ((uint16_t)0x0800)
+
8577 #define USART_CR2_STOP ((uint16_t)0x3000)
+
8578 #define USART_CR2_STOP_0 ((uint16_t)0x1000)
+
8579 #define USART_CR2_STOP_1 ((uint16_t)0x2000)
+
8581 #define USART_CR2_LINEN ((uint16_t)0x4000)
+
8583 /****************** Bit definition for USART_CR3 register *******************/
+
8584 #define USART_CR3_EIE ((uint16_t)0x0001)
+
8585 #define USART_CR3_IREN ((uint16_t)0x0002)
+
8586 #define USART_CR3_IRLP ((uint16_t)0x0004)
+
8587 #define USART_CR3_HDSEL ((uint16_t)0x0008)
+
8588 #define USART_CR3_NACK ((uint16_t)0x0010)
+
8589 #define USART_CR3_SCEN ((uint16_t)0x0020)
+
8590 #define USART_CR3_DMAR ((uint16_t)0x0040)
+
8591 #define USART_CR3_DMAT ((uint16_t)0x0080)
+
8592 #define USART_CR3_RTSE ((uint16_t)0x0100)
+
8593 #define USART_CR3_CTSE ((uint16_t)0x0200)
+
8594 #define USART_CR3_CTSIE ((uint16_t)0x0400)
+
8595 #define USART_CR3_ONEBIT ((uint16_t)0x0800)
+
8597 /****************** Bit definition for USART_GTPR register ******************/
+
8598 #define USART_GTPR_PSC ((uint16_t)0x00FF)
+
8599 #define USART_GTPR_PSC_0 ((uint16_t)0x0001)
+
8600 #define USART_GTPR_PSC_1 ((uint16_t)0x0002)
+
8601 #define USART_GTPR_PSC_2 ((uint16_t)0x0004)
+
8602 #define USART_GTPR_PSC_3 ((uint16_t)0x0008)
+
8603 #define USART_GTPR_PSC_4 ((uint16_t)0x0010)
+
8604 #define USART_GTPR_PSC_5 ((uint16_t)0x0020)
+
8605 #define USART_GTPR_PSC_6 ((uint16_t)0x0040)
+
8606 #define USART_GTPR_PSC_7 ((uint16_t)0x0080)
+
8608 #define USART_GTPR_GT ((uint16_t)0xFF00)
+
8610 /******************************************************************************/
+
8611 /* */
+
8612 /* Window WATCHDOG */
+
8613 /* */
+
8614 /******************************************************************************/
+
8615 /******************* Bit definition for WWDG_CR register ********************/
+
8616 #define WWDG_CR_T ((uint8_t)0x7F)
+
8617 #define WWDG_CR_T0 ((uint8_t)0x01)
+
8618 #define WWDG_CR_T1 ((uint8_t)0x02)
+
8619 #define WWDG_CR_T2 ((uint8_t)0x04)
+
8620 #define WWDG_CR_T3 ((uint8_t)0x08)
+
8621 #define WWDG_CR_T4 ((uint8_t)0x10)
+
8622 #define WWDG_CR_T5 ((uint8_t)0x20)
+
8623 #define WWDG_CR_T6 ((uint8_t)0x40)
+
8625 #define WWDG_CR_WDGA ((uint8_t)0x80)
+
8627 /******************* Bit definition for WWDG_CFR register *******************/
+
8628 #define WWDG_CFR_W ((uint16_t)0x007F)
+
8629 #define WWDG_CFR_W0 ((uint16_t)0x0001)
+
8630 #define WWDG_CFR_W1 ((uint16_t)0x0002)
+
8631 #define WWDG_CFR_W2 ((uint16_t)0x0004)
+
8632 #define WWDG_CFR_W3 ((uint16_t)0x0008)
+
8633 #define WWDG_CFR_W4 ((uint16_t)0x0010)
+
8634 #define WWDG_CFR_W5 ((uint16_t)0x0020)
+
8635 #define WWDG_CFR_W6 ((uint16_t)0x0040)
+
8637 #define WWDG_CFR_WDGTB ((uint16_t)0x0180)
+
8638 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
+
8639 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
+
8641 #define WWDG_CFR_EWI ((uint16_t)0x0200)
+
8643 /******************* Bit definition for WWDG_SR register ********************/
+
8644 #define WWDG_SR_EWIF ((uint8_t)0x01)
+
8647 /******************************************************************************/
+
8648 /* */
+
8649 /* DBG */
+
8650 /* */
+
8651 /******************************************************************************/
+
8652 /******************** Bit definition for DBGMCU_IDCODE register *************/
+
8653 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+
8654 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
8655 
+
8656 /******************** Bit definition for DBGMCU_CR register *****************/
+
8657 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+
8658 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+
8659 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+
8660 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
8661 
+
8662 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+
8663 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)
+
8664 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)
+
8666 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
+
8667 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+
8668 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+
8669 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+
8670 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
+
8671 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+
8672 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+
8673 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
+
8674 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
+
8675 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
+
8676 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+
8677 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+
8678 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+
8679 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+
8680 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+
8681 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+
8682 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
+
8683 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
+
8684 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
+
8685 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
8686 
+
8687 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
+
8688 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+
8689 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+
8690 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
+
8691 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
+
8692 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
+
8693 
+
8694 /******************************************************************************/
+
8695 /* */
+
8696 /* Ethernet MAC Registers bits definitions */
+
8697 /* */
+
8698 /******************************************************************************/
+
8699 /* Bit definition for Ethernet MAC Control Register register */
+
8700 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+
8701 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+
8702 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+
8703 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+
8704  #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+
8705  #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+
8706  #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+
8707  #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+
8708  #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+
8709  #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+
8710  #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+
8711 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+
8712 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+
8713 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+
8714 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+
8715 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+
8716 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+
8717 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+
8718 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+
8719 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+
8720  a transmission attempt during retries after a collision: 0 =< r <2^k */
+
8721  #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+
8722  #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+
8723  #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+
8724  #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+
8725 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+
8726 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+
8727 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
8728 
+
8729 /* Bit definition for Ethernet MAC Frame Filter Register */
+
8730 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+
8731 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+
8732 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+
8733 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+
8734 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+
8735  #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+
8736  #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+
8737  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+
8738 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+
8739 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+
8740 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+
8741 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+
8742 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+
8743 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
8744 
+
8745 /* Bit definition for Ethernet MAC Hash Table High Register */
+
8746 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
8747 
+
8748 /* Bit definition for Ethernet MAC Hash Table Low Register */
+
8749 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
8750 
+
8751 /* Bit definition for Ethernet MAC MII Address Register */
+
8752 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+
8753 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+
8754 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+
8755  #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+
8756  #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+
8757  #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+
8758  #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+
8759  #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+
8760 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+
8761 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
8762 
+
8763 /* Bit definition for Ethernet MAC MII Data Register */
+
8764 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
8765 
+
8766 /* Bit definition for Ethernet MAC Flow Control Register */
+
8767 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+
8768 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+
8769 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+
8770  #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+
8771  #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+
8772  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+
8773  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+
8774 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+
8775 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+
8776 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+
8777 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
8778 
+
8779 /* Bit definition for Ethernet MAC VLAN Tag Register */
+
8780 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+
8781 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
8782 
+
8783 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+
8784 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+
8785 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+
8786  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+
8787 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+
8788  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+
8789  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+
8790  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+
8791  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+
8792  RSVD - Filter1 Command - RSVD - Filter0 Command
+
8793  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+
8794  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+
8795  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
8796 
+
8797 /* Bit definition for Ethernet MAC PMT Control and Status Register */
+
8798 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+
8799 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+
8800 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+
8801 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+
8802 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+
8803 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+
8804 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
8805 
+
8806 /* Bit definition for Ethernet MAC Status Register */
+
8807 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+
8808 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+
8809 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+
8810 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+
8811 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
8812 
+
8813 /* Bit definition for Ethernet MAC Interrupt Mask Register */
+
8814 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+
8815 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
8816 
+
8817 /* Bit definition for Ethernet MAC Address0 High Register */
+
8818 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
8819 
+
8820 /* Bit definition for Ethernet MAC Address0 Low Register */
+
8821 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
8822 
+
8823 /* Bit definition for Ethernet MAC Address1 High Register */
+
8824 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+
8825 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+
8826 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+
8827  #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+
8828  #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+
8829  #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+
8830  #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+
8831  #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+
8832  #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+
8833 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
8834 
+
8835 /* Bit definition for Ethernet MAC Address1 Low Register */
+
8836 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
8837 
+
8838 /* Bit definition for Ethernet MAC Address2 High Register */
+
8839 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+
8840 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+
8841 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+
8842  #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+
8843  #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+
8844  #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+
8845  #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+
8846  #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+
8847  #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+
8848 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
8849 
+
8850 /* Bit definition for Ethernet MAC Address2 Low Register */
+
8851 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
8852 
+
8853 /* Bit definition for Ethernet MAC Address3 High Register */
+
8854 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+
8855 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+
8856 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+
8857  #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+
8858  #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+
8859  #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+
8860  #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+
8861  #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+
8862  #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+
8863 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
8864 
+
8865 /* Bit definition for Ethernet MAC Address3 Low Register */
+
8866 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
8867 
+
8868 /******************************************************************************/
+
8869 /* Ethernet MMC Registers bits definition */
+
8870 /******************************************************************************/
+
8871 
+
8872 /* Bit definition for Ethernet MMC Contol Register */
+
8873 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
+
8874 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
+
8875 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+
8876 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+
8877 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+
8878 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
8879 
+
8880 /* Bit definition for Ethernet MMC Receive Interrupt Register */
+
8881 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+
8882 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+
8883 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
8884 
+
8885 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
+
8886 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+
8887 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+
8888 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
8889 
+
8890 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+
8891 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+
8892 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+
8893 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
8894 
+
8895 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+
8896 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+
8897 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+
8898 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
8899 
+
8900 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+
8901 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
8902 
+
8903 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+
8904 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
8905 
+
8906 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+
8907 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
8908 
+
8909 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+
8910 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
8911 
+
8912 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+
8913 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
8914 
+
8915 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+
8916 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
8917 
+
8918 /******************************************************************************/
+
8919 /* Ethernet PTP Registers bits definition */
+
8920 /******************************************************************************/
+
8921 
+
8922 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
+
8923 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
+
8924 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
+
8925 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
+
8926 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
+
8927 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
+
8928 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
+
8929 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
+
8930 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
+
8931 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
+
8932 
+
8933 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+
8934 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+
8935 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+
8936 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+
8937 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+
8938 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
8939 
+
8940 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
+
8941 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
8942 
+
8943 /* Bit definition for Ethernet PTP Time Stamp High Register */
+
8944 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
8945 
+
8946 /* Bit definition for Ethernet PTP Time Stamp Low Register */
+
8947 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+
8948 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
8949 
+
8950 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
+
8951 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
8952 
+
8953 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+
8954 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+
8955 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
8956 
+
8957 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
+
8958 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
8959 
+
8960 /* Bit definition for Ethernet PTP Target Time High Register */
+
8961 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
8962 
+
8963 /* Bit definition for Ethernet PTP Target Time Low Register */
+
8964 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
8965 
+
8966 /* Bit definition for Ethernet PTP Time Stamp Status Register */
+
8967 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
+
8968 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
+
8969 
+
8970 /******************************************************************************/
+
8971 /* Ethernet DMA Registers bits definition */
+
8972 /******************************************************************************/
+
8973 
+
8974 /* Bit definition for Ethernet DMA Bus Mode Register */
+
8975 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+
8976 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+
8977 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+
8978 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+
8979  #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+
8980  #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+
8981  #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+
8982  #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+
8983  #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+
8984  #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+
8985  #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+
8986  #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+
8987  #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+
8988  #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+
8989  #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+
8990  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
8991 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+
8992 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+
8993  #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+
8994  #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+
8995  #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+
8996  #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+
8997 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+
8998  #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+
8999  #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+
9000  #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+
9001  #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+
9002  #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+
9003  #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+
9004  #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+
9005  #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+
9006  #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+
9007  #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+
9008  #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+
9009  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
9010 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
+
9011 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+
9012 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+
9013 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
9014 
+
9015 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+
9016 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
9017 
+
9018 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
+
9019 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
9020 
+
9021 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+
9022 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
9023 
+
9024 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+
9025 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
9026 
+
9027 /* Bit definition for Ethernet DMA Status Register */
+
9028 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+
9029 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+
9030 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+
9031 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+
9032  /* combination with EBS[2:0] for GetFlagStatus function */
+
9033  #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+
9034  #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+
9035  #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+
9036 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+
9037  #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+
9038  #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+
9039  #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+
9040  #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+
9041  #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+
9042  #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+
9043 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+
9044  #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+
9045  #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+
9046  #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+
9047  #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+
9048  #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+
9049  #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+
9050 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+
9051 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+
9052 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+
9053 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+
9054 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+
9055 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+
9056 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+
9057 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+
9058 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+
9059 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+
9060 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+
9061 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+
9062 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+
9063 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+
9064 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
9065 
+
9066 /* Bit definition for Ethernet DMA Operation Mode Register */
+
9067 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+
9068 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+
9069 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+
9070 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+
9071 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+
9072 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+
9073  #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+
9074  #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+
9075  #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+
9076  #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+
9077  #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+
9078  #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+
9079  #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+
9080  #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+
9081 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+
9082 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+
9083 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+
9084 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+
9085  #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+
9086  #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+
9087  #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+
9088  #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+
9089 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+
9090 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
9091 
+
9092 /* Bit definition for Ethernet DMA Interrupt Enable Register */
+
9093 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+
9094 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+
9095 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+
9096 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+
9097 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+
9098 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+
9099 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+
9100 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+
9101 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+
9102 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+
9103 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+
9104 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+
9105 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+
9106 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+
9107 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
9108 
+
9109 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+
9110 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+
9111 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+
9112 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+
9113 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
9114 
+
9115 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+
9116 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
9117 
+
9118 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+
9119 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
9120 
+
9121 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+
9122 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
9123 
+
9124 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+
9125 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+
9126 
+
9135 #ifdef USE_STDPERIPH_DRIVER
+
9136  #include "stm32f4xx_conf.h"
+
9137 #endif /* USE_STDPERIPH_DRIVER */
+
9138 
+
9143 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
9144 
+
9145 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
9146 
+
9147 #define READ_BIT(REG, BIT) ((REG) & (BIT))
+
9148 
+
9149 #define CLEAR_REG(REG) ((REG) = (0x0))
+
9150 
+
9151 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
9152 
+
9153 #define READ_REG(REG) ((REG))
+
9154 
+
9155 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
9156 
+
9161 #ifdef __cplusplus
+
9162 }
+
9163 #endif /* __cplusplus */
+
9164 
+
9165 #endif /* __STM32F4xx_H */
+
9166 
+
9175 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
vuc32
__I uint32_t vuc32
Definition: stm32f4xx.h:508
+
I2C2_ER_IRQn
Definition: stm32f4xx.h:222
+
TIM7_IRQn
Definition: stm32f4xx.h:243
+
TIM8_CC_IRQn
Definition: stm32f4xx.h:234
+
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f4xx.h:1060
+
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f4xx.h:580
+
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f4xx.h:1007
+
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f4xx.h:1257
+
SDIO_IRQn
Definition: stm32f4xx.h:237
+
vsc8
__I int8_t vsc8
Definition: stm32f4xx.h:494
+
DMA2_Stream5_IRQn
Definition: stm32f4xx.h:256
+
CAN1_RX0_IRQn
Definition: stm32f4xx.h:208
+
TIM4_IRQn
Definition: stm32f4xx.h:218
+
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f4xx.h:855
+
DCMI_IRQn
Definition: stm32f4xx.h:266
+
TIM1_UP_TIM10_IRQn
Definition: stm32f4xx.h:213
+
RTC_Alarm_IRQn
Definition: stm32f4xx.h:229
+
MemoryManagement_IRQn
Definition: stm32f4xx.h:178
+
s32
int32_t s32
Definition: stm32f4xx.h:480
+
DMA1_Stream7_IRQn
Definition: stm32f4xx.h:235
+
TIM8_UP_TIM13_IRQn
Definition: stm32f4xx.h:232
+
UART5_IRQn
Definition: stm32f4xx.h:241
+
__I
#define __I
Definition: core_cm4.h:219
+
DMA1_Stream1_IRQn
Definition: stm32f4xx.h:198
+
ETH_IRQn
Definition: stm32f4xx.h:249
+
USART6_IRQn
Definition: stm32f4xx.h:259
+
PVD_IRQn
Definition: stm32f4xx.h:187
+
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f4xx.h:825
+
USART1_IRQn
Definition: stm32f4xx.h:225
+
FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3.
Definition: stm32f4xx.h:887
+
ETH_WKUP_IRQn
Definition: stm32f4xx.h:250
+
EXTI0_IRQn
Definition: stm32f4xx.h:192
+
I2C1_EV_IRQn
Definition: stm32f4xx.h:219
+
FPU_IRQn
Definition: stm32f4xx.h:269
+
CRC_TypeDef
CRC calculation unit.
Definition: stm32f4xx.h:632
+
DMA2_Stream2_IRQn
Definition: stm32f4xx.h:246
+
TIM1_BRK_TIM9_IRQn
Definition: stm32f4xx.h:212
+
SPI2_IRQn
Definition: stm32f4xx.h:224
+
DMA2_Stream4_IRQn
Definition: stm32f4xx.h:248
+
DMA1_Stream6_IRQn
Definition: stm32f4xx.h:203
+
HASH_RNG_IRQn
Definition: stm32f4xx.h:268
+
DMA2_Stream7_IRQn
Definition: stm32f4xx.h:258
+
__IO
#define __IO
Definition: core_cm4.h:222
+
FSMC_IRQn
Definition: stm32f4xx.h:236
+
OTG_HS_EP1_OUT_IRQn
Definition: stm32f4xx.h:262
+
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
+
CAN2_TX_IRQn
Definition: stm32f4xx.h:251
+
DMA_TypeDef
Definition: stm32f4xx.h:708
+
OTG_FS_WKUP_IRQn
Definition: stm32f4xx.h:230
+
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f4xx.h:1349
+
OTG_HS_WKUP_IRQn
Definition: stm32f4xx.h:264
+
USART2_IRQn
Definition: stm32f4xx.h:226
+
CAN1_RX1_IRQn
Definition: stm32f4xx.h:209
+
CAN1_SCE_IRQn
Definition: stm32f4xx.h:210
+
DebugMonitor_IRQn
Definition: stm32f4xx.h:182
+
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f4xx.h:1085
+
SPI3_IRQn
Definition: stm32f4xx.h:239
+
CAN2_RX0_IRQn
Definition: stm32f4xx.h:252
+
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f4xx.h:1420
+
DMA1_Stream2_IRQn
Definition: stm32f4xx.h:199
+
DMA1_Stream4_IRQn
Definition: stm32f4xx.h:201
+
sc16
const int16_t sc16
Definition: stm32f4xx.h:485
+
OTG_FS_IRQn
Definition: stm32f4xx.h:255
+
UsageFault_IRQn
Definition: stm32f4xx.h:180
+
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f4xx.h:989
+
USART3_IRQn
Definition: stm32f4xx.h:227
+
TIM8_BRK_TIM12_IRQn
Definition: stm32f4xx.h:231
+
vsc32
__I int32_t vsc32
Definition: stm32f4xx.h:492
+
SVCall_IRQn
Definition: stm32f4xx.h:181
+
BusFault_IRQn
Definition: stm32f4xx.h:179
+
PendSV_IRQn
Definition: stm32f4xx.h:183
+
CAN_TypeDef
Controller Area Network.
Definition: stm32f4xx.h:602
+
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f4xx.h:233
+
I2C3_EV_IRQn
Definition: stm32f4xx.h:260
+
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f4xx.h:720
+
FLASH_IRQn
Definition: stm32f4xx.h:190
+
DMA1_Stream3_IRQn
Definition: stm32f4xx.h:200
+
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:531
+
CAN2_RX1_IRQn
Definition: stm32f4xx.h:253
+
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f4xx.h:1208
+
DMA2_Stream6_IRQn
Definition: stm32f4xx.h:257
+
uc8
const uint8_t uc8
Definition: stm32f4xx.h:502
+
FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f4xx.h:873
+
DMA2_Stream1_IRQn
Definition: stm32f4xx.h:245
+
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
+
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f4xx.h:568
+
ETH_TypeDef
Ethernet MAC.
Definition: stm32f4xx.h:751
+
CAN2_SCE_IRQn
Definition: stm32f4xx.h:254
+
uc32
const uint32_t uc32
Definition: stm32f4xx.h:500
+
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f4xx.h:1327
+
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:1283
+
OTG_HS_EP1_IN_IRQn
Definition: stm32f4xx.h:263
+
CAN1_TX_IRQn
Definition: stm32f4xx.h:207
+
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f4xx.h:698
+
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f4xx.h:645
+
FLASH_TypeDef
FLASH Registers.
Definition: stm32f4xx.h:839
+
PWR_TypeDef
Power Control.
Definition: stm32f4xx.h:1108
+
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f4xx.h:1048
+
EXTI2_IRQn
Definition: stm32f4xx.h:194
+
EXTI4_IRQn
Definition: stm32f4xx.h:196
+
RTC_WKUP_IRQn
Definition: stm32f4xx.h:189
+
uc16
const uint16_t uc16
Definition: stm32f4xx.h:501
+
ADC_Common_TypeDef
Definition: stm32f4xx.h:555
+
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f4xx.h:1118
+
SPI1_IRQn
Definition: stm32f4xx.h:223
+
DMA2_Stream3_IRQn
Definition: stm32f4xx.h:247
+
vuc16
__I uint16_t vuc16
Definition: stm32f4xx.h:509
+
I2C1_ER_IRQn
Definition: stm32f4xx.h:220
+
TIM2_IRQn
Definition: stm32f4xx.h:216
+
RCC_IRQn
Definition: stm32f4xx.h:191
+
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f4xx.h:592
+
vsc16
__I int16_t vsc16
Definition: stm32f4xx.h:493
+
EXTI1_IRQn
Definition: stm32f4xx.h:193
+
CRYP_IRQn
Definition: stm32f4xx.h:267
+
EXTI3_IRQn
Definition: stm32f4xx.h:195
+
DMA1_Stream5_IRQn
Definition: stm32f4xx.h:202
+
RTC_TypeDef
Real-Time Clock.
Definition: stm32f4xx.h:1159
+
DCMI_TypeDef
DCMI.
Definition: stm32f4xx.h:679
+
UART4_IRQn
Definition: stm32f4xx.h:240
+
WWDG_IRQn
Definition: stm32f4xx.h:186
+
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f4xx.h:864
+
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1020
+
ADC_IRQn
Definition: stm32f4xx.h:204
+
DMA1_Stream0_IRQn
Definition: stm32f4xx.h:197
+
RNG_TypeDef
RNG.
Definition: stm32f4xx.h:1429
+
HASH_TypeDef
HASH.
Definition: stm32f4xx.h:1404
+
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f4xx.h:667
+
TIM5_IRQn
Definition: stm32f4xx.h:238
+
TIM1_CC_IRQn
Definition: stm32f4xx.h:215
+
sc8
const int8_t sc8
Definition: stm32f4xx.h:486
+
SAI_Block_TypeDef
Definition: stm32f4xx.h:1213
+
EXTI9_5_IRQn
Definition: stm32f4xx.h:211
+
TAMP_STAMP_IRQn
Definition: stm32f4xx.h:188
+
EXTI15_10_IRQn
Definition: stm32f4xx.h:228
+
CRYP_TypeDef
Crypto Processor.
Definition: stm32f4xx.h:1360
+
TIM3_IRQn
Definition: stm32f4xx.h:217
+
I2C2_EV_IRQn
Definition: stm32f4xx.h:221
+
vuc8
__I uint8_t vuc8
Definition: stm32f4xx.h:510
+
SDIO_TypeDef
SD host Interface.
Definition: stm32f4xx.h:1229
+
I2C3_ER_IRQn
Definition: stm32f4xx.h:261
+
OTG_HS_IRQn
Definition: stm32f4xx.h:265
+
NonMaskableInt_IRQn
Definition: stm32f4xx.h:177
+
TIM6_DAC_IRQn
Definition: stm32f4xx.h:242
+
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f4xx.h:214
+
DMA2_Stream0_IRQn
Definition: stm32f4xx.h:244
+
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f4xx.h:901
+
SysTick_IRQn
Definition: stm32f4xx.h:184
+
sc32
const int32_t sc32
Definition: stm32f4xx.h:484
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__adc_8c.html b/stm32f4xx__adc_8c.html new file mode 100644 index 0000000..7b44981 --- /dev/null +++ b/stm32f4xx__adc_8c.html @@ -0,0 +1,377 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_adc.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_adc.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: +More...

+
#include "stm32f4xx_adc.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_adc.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define CR1_DISCNUM_RESET   ((uint32_t)0xFFFF1FFF)
 
+#define CR1_AWDCH_RESET   ((uint32_t)0xFFFFFFE0)
 
+#define CR1_AWDMode_RESET   ((uint32_t)0xFF3FFDFF)
 
+#define CR1_CLEAR_MASK   ((uint32_t)0xFCFFFEFF)
 
+#define CR2_EXTEN_RESET   ((uint32_t)0xCFFFFFFF)
 
+#define CR2_JEXTEN_RESET   ((uint32_t)0xFFCFFFFF)
 
+#define CR2_JEXTSEL_RESET   ((uint32_t)0xFFF0FFFF)
 
+#define CR2_CLEAR_MASK   ((uint32_t)0xC0FFF7FD)
 
+#define SQR3_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR2_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR1_SQ_SET   ((uint32_t)0x0000001F)
 
+#define SQR1_L_RESET   ((uint32_t)0xFF0FFFFF)
 
+#define JSQR_JSQ_SET   ((uint32_t)0x0000001F)
 
+#define JSQR_JL_SET   ((uint32_t)0x00300000)
 
+#define JSQR_JL_RESET   ((uint32_t)0xFFCFFFFF)
 
+#define SMPR1_SMP_SET   ((uint32_t)0x00000007)
 
+#define SMPR2_SMP_SET   ((uint32_t)0x00000007)
 
+#define JDR_OFFSET   ((uint8_t)0x28)
 
+#define CDR_ADDRESS   ((uint32_t)0x40012308)
 
+#define CR_CLEAR_MASK   ((uint32_t)0xFFFC30E0)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_DeInit (void)
 Deinitializes all ADCs peripherals registers to their default reset values. More...
 
void ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
 Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct. More...
 
void ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
 Fills each ADC_InitStruct member with its default value. More...
 
void ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct. More...
 
void ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Fills each ADC_CommonInitStruct member with its default value. More...
 
void ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC peripheral. More...
 
void ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
 Enables or disables the analog watchdog on single/all regular or injected channels. More...
 
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
 Configures the high and low thresholds of the analog watchdog. More...
 
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
 Configures the analog watchdog guarded single channel. More...
 
void ADC_TempSensorVrefintCmd (FunctionalState NewState)
 Enables or disables the temperature sensor and Vrefint channels. More...
 
void ADC_VBATCmd (FunctionalState NewState)
 Enables or disables the VBAT (Voltage Battery) channel. More...
 
void ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the regular channels. More...
 
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start regular conversion Status. More...
 
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the EOC on each regular channel conversion. More...
 
void ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC continuous conversion mode. More...
 
void ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
 Configures the discontinuous mode for the selected ADC regular group channel. More...
 
void ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode on regular group channel for the specified ADC. More...
 
uint16_t ADC_GetConversionValue (ADC_TypeDef *ADCx)
 Returns the last ADCx conversion result data for regular channel. More...
 
uint32_t ADC_GetMultiModeConversionValue (void)
 Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode. More...
 
void ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC DMA request. More...
 
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer (Single-ADC mode) More...
 
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer in multi ADC mode. More...
 
void ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
 Configures the sequencer length for injected channels. More...
 
void ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
 Set the injected channels conversion value offset. More...
 
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
 Configures the ADCx external trigger for injected channels conversion. More...
 
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
 Configures the ADCx external trigger edge for injected channels conversion. More...
 
void ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the injected channels. More...
 
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start injected conversion Status. More...
 
void ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the selected ADC automatic injected group conversion after regular one. More...
 
void ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode for injected group channel for the specified ADC. More...
 
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
 Returns the ADC injected channel conversion result. More...
 
void ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
 Enables or disables the specified ADC interrupts. More...
 
FlagStatus ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Checks whether the specified ADC flag is set or not. More...
 
void ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Clears the ADCx's pending flags. More...
 
ITStatus ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Checks whether the specified ADC interrupt has occurred or not. More...
 
void ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Clears the ADCx's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration (in addition to ADC multi mode selection)
    • +
  • Analog Watchdog configuration
    • +
  • Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT management
    • +
  • Regular Channels Configuration
    • +
  • Regular Channels DMA Configuration
    • +
  • Injected channels Configuration
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                    ##### How to use this driver #####
+===============================================================================
+   [..]
+   (#) Enable the ADC interface clock using 
+       RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); 
+      
+   (#) ADC pins configuration
+        (++) Enable the clock for the ADC GPIOs using the following function:
+            RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+        (++) Configure these ADC pins in analog mode using GPIO_Init();  
+ 
+    (#) Configure the ADC Prescaler, conversion resolution and data 
+        alignment using the ADC_Init() function.
+    (#) Activate the ADC peripheral using ADC_Cmd() function.
+ 
+    *** Regular channels group configuration ***
+    ============================================
+    [..]    
+      (+) To configure the ADC regular channels group features, use 
+          ADC_Init() and ADC_RegularChannelConfig() functions.
+      (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+          function.
+      (+) To configurate and activate the Discontinuous mode, use the 
+          ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
+      (+) To read the ADC converted values, use the ADC_GetConversionValue()
+          function.
+ 
+    *** Multi mode ADCs Regular channels configuration ***
+    ======================================================
+    [..]
+      (+) Refer to "Regular channels group configuration" description to
+          configure the ADC1, ADC2 and ADC3 regular channels.        
+      (+) Select the Multi mode ADC regular channels features (dual or 
+          triple mode) using ADC_CommonInit() function and configure 
+          the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() 
+          functions.        
+      (+) Read the ADCs converted values using the 
+          ADC_GetMultiModeConversionValue() function.
+ 
+    *** DMA for Regular channels group features configuration ***
+    ============================================================= 
+    [..]
+      (+) To enable the DMA mode for regular channels group, use the 
+          ADC_DMACmd() function.
+      (+) To enable the generation of DMA requests continuously at the end
+          of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() 
+          function.
+ 
+    *** Injected channels group configuration ***
+    =============================================    
+    [..]
+      (+) To configure the ADC Injected channels group features, use 
+          ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
+          functions.
+      (+) To activate the continuous mode, use the ADC_continuousModeCmd()
+          function.
+      (+) To activate the Injected Discontinuous mode, use the 
+          ADC_InjectedDiscModeCmd() function.  
+      (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+          function.        
+      (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() 
+          function.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__adc_8c__incl.map b/stm32f4xx__adc_8c__incl.map new file mode 100644 index 0000000..731c674 --- /dev/null +++ b/stm32f4xx__adc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__adc_8c__incl.md5 b/stm32f4xx__adc_8c__incl.md5 new file mode 100644 index 0000000..3bb9c78 --- /dev/null +++ b/stm32f4xx__adc_8c__incl.md5 @@ -0,0 +1 @@ +d3239b65b21fae00686759750de0d4eb \ No newline at end of file diff --git a/stm32f4xx__adc_8c__incl.png b/stm32f4xx__adc_8c__incl.png new file mode 100644 index 0000000..b85b9f3 Binary files /dev/null and b/stm32f4xx__adc_8c__incl.png differ diff --git a/stm32f4xx__adc_8h.html b/stm32f4xx__adc_8h.html new file mode 100644 index 0000000..fee43cc --- /dev/null +++ b/stm32f4xx__adc_8h.html @@ -0,0 +1,724 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_adc.h File Reference + + + + + + + + + + +
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stm32f4xx_adc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the ADC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_adc.h:
+
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

+ + + + + + + + +

+Classes

struct  ADC_InitTypeDef
 ADC Init structure definition. More...
 
struct  ADC_CommonInitTypeDef
 ADC Common Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_ADC_ALL_PERIPH(PERIPH)
 
+#define ADC_Mode_Independent   ((uint32_t)0x00000000)
 
+#define ADC_DualMode_RegSimult_InjecSimult   ((uint32_t)0x00000001)
 
+#define ADC_DualMode_RegSimult_AlterTrig   ((uint32_t)0x00000002)
 
+#define ADC_DualMode_InjecSimult   ((uint32_t)0x00000005)
 
+#define ADC_DualMode_RegSimult   ((uint32_t)0x00000006)
 
+#define ADC_DualMode_Interl   ((uint32_t)0x00000007)
 
+#define ADC_DualMode_AlterTrig   ((uint32_t)0x00000009)
 
+#define ADC_TripleMode_RegSimult_InjecSimult   ((uint32_t)0x00000011)
 
+#define ADC_TripleMode_RegSimult_AlterTrig   ((uint32_t)0x00000012)
 
+#define ADC_TripleMode_InjecSimult   ((uint32_t)0x00000015)
 
+#define ADC_TripleMode_RegSimult   ((uint32_t)0x00000016)
 
+#define ADC_TripleMode_Interl   ((uint32_t)0x00000017)
 
+#define ADC_TripleMode_AlterTrig   ((uint32_t)0x00000019)
 
#define IS_ADC_MODE(MODE)
 
+#define ADC_Prescaler_Div2   ((uint32_t)0x00000000)
 
+#define ADC_Prescaler_Div4   ((uint32_t)0x00010000)
 
+#define ADC_Prescaler_Div6   ((uint32_t)0x00020000)
 
+#define ADC_Prescaler_Div8   ((uint32_t)0x00030000)
 
#define IS_ADC_PRESCALER(PRESCALER)
 
+#define ADC_DMAAccessMode_Disabled   ((uint32_t)0x00000000) /* DMA mode disabled */
 
+#define ADC_DMAAccessMode_1   ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
 
+#define ADC_DMAAccessMode_2   ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
 
+#define ADC_DMAAccessMode_3   ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
 
#define IS_ADC_DMA_ACCESS_MODE(MODE)
 
+#define ADC_TwoSamplingDelay_5Cycles   ((uint32_t)0x00000000)
 
+#define ADC_TwoSamplingDelay_6Cycles   ((uint32_t)0x00000100)
 
+#define ADC_TwoSamplingDelay_7Cycles   ((uint32_t)0x00000200)
 
+#define ADC_TwoSamplingDelay_8Cycles   ((uint32_t)0x00000300)
 
+#define ADC_TwoSamplingDelay_9Cycles   ((uint32_t)0x00000400)
 
+#define ADC_TwoSamplingDelay_10Cycles   ((uint32_t)0x00000500)
 
+#define ADC_TwoSamplingDelay_11Cycles   ((uint32_t)0x00000600)
 
+#define ADC_TwoSamplingDelay_12Cycles   ((uint32_t)0x00000700)
 
+#define ADC_TwoSamplingDelay_13Cycles   ((uint32_t)0x00000800)
 
+#define ADC_TwoSamplingDelay_14Cycles   ((uint32_t)0x00000900)
 
+#define ADC_TwoSamplingDelay_15Cycles   ((uint32_t)0x00000A00)
 
+#define ADC_TwoSamplingDelay_16Cycles   ((uint32_t)0x00000B00)
 
+#define ADC_TwoSamplingDelay_17Cycles   ((uint32_t)0x00000C00)
 
+#define ADC_TwoSamplingDelay_18Cycles   ((uint32_t)0x00000D00)
 
+#define ADC_TwoSamplingDelay_19Cycles   ((uint32_t)0x00000E00)
 
+#define ADC_TwoSamplingDelay_20Cycles   ((uint32_t)0x00000F00)
 
#define IS_ADC_SAMPLING_DELAY(DELAY)
 
+#define ADC_Resolution_12b   ((uint32_t)0x00000000)
 
+#define ADC_Resolution_10b   ((uint32_t)0x01000000)
 
+#define ADC_Resolution_8b   ((uint32_t)0x02000000)
 
+#define ADC_Resolution_6b   ((uint32_t)0x03000000)
 
#define IS_ADC_RESOLUTION(RESOLUTION)
 
+#define ADC_ExternalTrigConvEdge_None   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConvEdge_Rising   ((uint32_t)0x10000000)
 
+#define ADC_ExternalTrigConvEdge_Falling   ((uint32_t)0x20000000)
 
+#define ADC_ExternalTrigConvEdge_RisingFalling   ((uint32_t)0x30000000)
 
#define IS_ADC_EXT_TRIG_EDGE(EDGE)
 
+#define ADC_ExternalTrigConv_T1_CC1   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigConv_T1_CC2   ((uint32_t)0x01000000)
 
+#define ADC_ExternalTrigConv_T1_CC3   ((uint32_t)0x02000000)
 
+#define ADC_ExternalTrigConv_T2_CC2   ((uint32_t)0x03000000)
 
+#define ADC_ExternalTrigConv_T2_CC3   ((uint32_t)0x04000000)
 
+#define ADC_ExternalTrigConv_T2_CC4   ((uint32_t)0x05000000)
 
+#define ADC_ExternalTrigConv_T2_TRGO   ((uint32_t)0x06000000)
 
+#define ADC_ExternalTrigConv_T3_CC1   ((uint32_t)0x07000000)
 
+#define ADC_ExternalTrigConv_T3_TRGO   ((uint32_t)0x08000000)
 
+#define ADC_ExternalTrigConv_T4_CC4   ((uint32_t)0x09000000)
 
+#define ADC_ExternalTrigConv_T5_CC1   ((uint32_t)0x0A000000)
 
+#define ADC_ExternalTrigConv_T5_CC2   ((uint32_t)0x0B000000)
 
+#define ADC_ExternalTrigConv_T5_CC3   ((uint32_t)0x0C000000)
 
+#define ADC_ExternalTrigConv_T8_CC1   ((uint32_t)0x0D000000)
 
+#define ADC_ExternalTrigConv_T8_TRGO   ((uint32_t)0x0E000000)
 
+#define ADC_ExternalTrigConv_Ext_IT11   ((uint32_t)0x0F000000)
 
#define IS_ADC_EXT_TRIG(REGTRIG)
 
+#define ADC_DataAlign_Right   ((uint32_t)0x00000000)
 
+#define ADC_DataAlign_Left   ((uint32_t)0x00000800)
 
#define IS_ADC_DATA_ALIGN(ALIGN)
 
+#define ADC_Channel_0   ((uint8_t)0x00)
 
+#define ADC_Channel_1   ((uint8_t)0x01)
 
+#define ADC_Channel_2   ((uint8_t)0x02)
 
+#define ADC_Channel_3   ((uint8_t)0x03)
 
+#define ADC_Channel_4   ((uint8_t)0x04)
 
+#define ADC_Channel_5   ((uint8_t)0x05)
 
+#define ADC_Channel_6   ((uint8_t)0x06)
 
+#define ADC_Channel_7   ((uint8_t)0x07)
 
+#define ADC_Channel_8   ((uint8_t)0x08)
 
+#define ADC_Channel_9   ((uint8_t)0x09)
 
+#define ADC_Channel_10   ((uint8_t)0x0A)
 
+#define ADC_Channel_11   ((uint8_t)0x0B)
 
+#define ADC_Channel_12   ((uint8_t)0x0C)
 
+#define ADC_Channel_13   ((uint8_t)0x0D)
 
+#define ADC_Channel_14   ((uint8_t)0x0E)
 
+#define ADC_Channel_15   ((uint8_t)0x0F)
 
+#define ADC_Channel_16   ((uint8_t)0x10)
 
+#define ADC_Channel_17   ((uint8_t)0x11)
 
+#define ADC_Channel_18   ((uint8_t)0x12)
 
+#define ADC_Channel_TempSensor   ((uint8_t)ADC_Channel_16)
 
+#define ADC_Channel_Vrefint   ((uint8_t)ADC_Channel_17)
 
+#define ADC_Channel_Vbat   ((uint8_t)ADC_Channel_18)
 
#define IS_ADC_CHANNEL(CHANNEL)
 
+#define ADC_SampleTime_3Cycles   ((uint8_t)0x00)
 
+#define ADC_SampleTime_15Cycles   ((uint8_t)0x01)
 
+#define ADC_SampleTime_28Cycles   ((uint8_t)0x02)
 
+#define ADC_SampleTime_56Cycles   ((uint8_t)0x03)
 
+#define ADC_SampleTime_84Cycles   ((uint8_t)0x04)
 
+#define ADC_SampleTime_112Cycles   ((uint8_t)0x05)
 
+#define ADC_SampleTime_144Cycles   ((uint8_t)0x06)
 
+#define ADC_SampleTime_480Cycles   ((uint8_t)0x07)
 
#define IS_ADC_SAMPLE_TIME(TIME)
 
+#define ADC_ExternalTrigInjecConvEdge_None   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConvEdge_Rising   ((uint32_t)0x00100000)
 
+#define ADC_ExternalTrigInjecConvEdge_Falling   ((uint32_t)0x00200000)
 
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling   ((uint32_t)0x00300000)
 
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE)
 
+#define ADC_ExternalTrigInjecConv_T1_CC4   ((uint32_t)0x00000000)
 
+#define ADC_ExternalTrigInjecConv_T1_TRGO   ((uint32_t)0x00010000)
 
+#define ADC_ExternalTrigInjecConv_T2_CC1   ((uint32_t)0x00020000)
 
+#define ADC_ExternalTrigInjecConv_T2_TRGO   ((uint32_t)0x00030000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC2   ((uint32_t)0x00040000)
 
+#define ADC_ExternalTrigInjecConv_T3_CC4   ((uint32_t)0x00050000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC1   ((uint32_t)0x00060000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC2   ((uint32_t)0x00070000)
 
+#define ADC_ExternalTrigInjecConv_T4_CC3   ((uint32_t)0x00080000)
 
+#define ADC_ExternalTrigInjecConv_T4_TRGO   ((uint32_t)0x00090000)
 
+#define ADC_ExternalTrigInjecConv_T5_CC4   ((uint32_t)0x000A0000)
 
+#define ADC_ExternalTrigInjecConv_T5_TRGO   ((uint32_t)0x000B0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC2   ((uint32_t)0x000C0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC3   ((uint32_t)0x000D0000)
 
+#define ADC_ExternalTrigInjecConv_T8_CC4   ((uint32_t)0x000E0000)
 
+#define ADC_ExternalTrigInjecConv_Ext_IT15   ((uint32_t)0x000F0000)
 
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG)
 
+#define ADC_InjectedChannel_1   ((uint8_t)0x14)
 
+#define ADC_InjectedChannel_2   ((uint8_t)0x18)
 
+#define ADC_InjectedChannel_3   ((uint8_t)0x1C)
 
+#define ADC_InjectedChannel_4   ((uint8_t)0x20)
 
#define IS_ADC_INJECTED_CHANNEL(CHANNEL)
 
+#define ADC_AnalogWatchdog_SingleRegEnable   ((uint32_t)0x00800200)
 
+#define ADC_AnalogWatchdog_SingleInjecEnable   ((uint32_t)0x00400200)
 
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable   ((uint32_t)0x00C00200)
 
+#define ADC_AnalogWatchdog_AllRegEnable   ((uint32_t)0x00800000)
 
+#define ADC_AnalogWatchdog_AllInjecEnable   ((uint32_t)0x00400000)
 
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable   ((uint32_t)0x00C00000)
 
+#define ADC_AnalogWatchdog_None   ((uint32_t)0x00000000)
 
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
 
+#define ADC_IT_EOC   ((uint16_t)0x0205)
 
+#define ADC_IT_AWD   ((uint16_t)0x0106)
 
+#define ADC_IT_JEOC   ((uint16_t)0x0407)
 
+#define ADC_IT_OVR   ((uint16_t)0x201A)
 
#define IS_ADC_IT(IT)
 
+#define ADC_FLAG_AWD   ((uint8_t)0x01)
 
+#define ADC_FLAG_EOC   ((uint8_t)0x02)
 
+#define ADC_FLAG_JEOC   ((uint8_t)0x04)
 
+#define ADC_FLAG_JSTRT   ((uint8_t)0x08)
 
+#define ADC_FLAG_STRT   ((uint8_t)0x10)
 
+#define ADC_FLAG_OVR   ((uint8_t)0x20)
 
+#define IS_ADC_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
 
#define IS_ADC_GET_FLAG(FLAG)
 
+#define IS_ADC_THRESHOLD(THRESHOLD)   ((THRESHOLD) <= 0xFFF)
 
+#define IS_ADC_OFFSET(OFFSET)   ((OFFSET) <= 0xFFF)
 
+#define IS_ADC_INJECTED_LENGTH(LENGTH)   (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
 
+#define IS_ADC_INJECTED_RANK(RANK)   (((RANK) >= 0x1) && ((RANK) <= 0x4))
 
+#define IS_ADC_REGULAR_LENGTH(LENGTH)   (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
 
+#define IS_ADC_REGULAR_RANK(RANK)   (((RANK) >= 0x1) && ((RANK) <= 0x10))
 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER)   (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void ADC_DeInit (void)
 Deinitializes all ADCs peripherals registers to their default reset values. More...
 
void ADC_Init (ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
 Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct. More...
 
void ADC_StructInit (ADC_InitTypeDef *ADC_InitStruct)
 Fills each ADC_InitStruct member with its default value. More...
 
void ADC_CommonInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct. More...
 
void ADC_CommonStructInit (ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 Fills each ADC_CommonInitStruct member with its default value. More...
 
void ADC_Cmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC peripheral. More...
 
void ADC_AnalogWatchdogCmd (ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
 Enables or disables the analog watchdog on single/all regular or injected channels. More...
 
void ADC_AnalogWatchdogThresholdsConfig (ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
 Configures the high and low thresholds of the analog watchdog. More...
 
void ADC_AnalogWatchdogSingleChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel)
 Configures the analog watchdog guarded single channel. More...
 
void ADC_TempSensorVrefintCmd (FunctionalState NewState)
 Enables or disables the temperature sensor and Vrefint channels. More...
 
void ADC_VBATCmd (FunctionalState NewState)
 Enables or disables the VBAT (Voltage Battery) channel. More...
 
void ADC_RegularChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_SoftwareStartConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the regular channels. More...
 
FlagStatus ADC_GetSoftwareStartConvStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start regular conversion Status. More...
 
void ADC_EOCOnEachRegularChannelCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the EOC on each regular channel conversion. More...
 
void ADC_ContinuousModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC continuous conversion mode. More...
 
void ADC_DiscModeChannelCountConfig (ADC_TypeDef *ADCx, uint8_t Number)
 Configures the discontinuous mode for the selected ADC regular group channel. More...
 
void ADC_DiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode on regular group channel for the specified ADC. More...
 
uint16_t ADC_GetConversionValue (ADC_TypeDef *ADCx)
 Returns the last ADCx conversion result data for regular channel. More...
 
uint32_t ADC_GetMultiModeConversionValue (void)
 Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode. More...
 
void ADC_DMACmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the specified ADC DMA request. More...
 
void ADC_DMARequestAfterLastTransferCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer (Single-ADC mode) More...
 
void ADC_MultiModeDMARequestAfterLastTransferCmd (FunctionalState NewState)
 Enables or disables the ADC DMA request after last transfer in multi ADC mode. More...
 
void ADC_InjectedChannelConfig (ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
 Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time. More...
 
void ADC_InjectedSequencerLengthConfig (ADC_TypeDef *ADCx, uint8_t Length)
 Configures the sequencer length for injected channels. More...
 
void ADC_SetInjectedOffset (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
 Set the injected channels conversion value offset. More...
 
void ADC_ExternalTrigInjectedConvConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
 Configures the ADCx external trigger for injected channels conversion. More...
 
void ADC_ExternalTrigInjectedConvEdgeConfig (ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
 Configures the ADCx external trigger edge for injected channels conversion. More...
 
void ADC_SoftwareStartInjectedConv (ADC_TypeDef *ADCx)
 Enables the selected ADC software start conversion of the injected channels. More...
 
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus (ADC_TypeDef *ADCx)
 Gets the selected ADC Software start injected conversion Status. More...
 
void ADC_AutoInjectedConvCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the selected ADC automatic injected group conversion after regular one. More...
 
void ADC_InjectedDiscModeCmd (ADC_TypeDef *ADCx, FunctionalState NewState)
 Enables or disables the discontinuous mode for injected group channel for the specified ADC. More...
 
uint16_t ADC_GetInjectedConversionValue (ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
 Returns the ADC injected channel conversion result. More...
 
void ADC_ITConfig (ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
 Enables or disables the specified ADC interrupts. More...
 
FlagStatus ADC_GetFlagStatus (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Checks whether the specified ADC flag is set or not. More...
 
void ADC_ClearFlag (ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
 Clears the ADCx's pending flags. More...
 
ITStatus ADC_GetITStatus (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Checks whether the specified ADC interrupt has occurred or not. More...
 
void ADC_ClearITPendingBit (ADC_TypeDef *ADCx, uint16_t ADC_IT)
 Clears the ADCx's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the ADC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
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+ + diff --git a/stm32f4xx__adc_8h__dep__incl.map b/stm32f4xx__adc_8h__dep__incl.map new file mode 100644 index 0000000..9111a2e --- /dev/null +++ b/stm32f4xx__adc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__adc_8h__dep__incl.md5 b/stm32f4xx__adc_8h__dep__incl.md5 new file mode 100644 index 0000000..ad85683 --- /dev/null +++ b/stm32f4xx__adc_8h__dep__incl.md5 @@ -0,0 +1 @@ +3f4a0da5909f46bd55899c2260f8bf73 \ No newline at end of file diff --git a/stm32f4xx__adc_8h__dep__incl.png b/stm32f4xx__adc_8h__dep__incl.png new file mode 100644 index 0000000..e2dee62 Binary files /dev/null and b/stm32f4xx__adc_8h__dep__incl.png differ diff --git a/stm32f4xx__adc_8h__incl.map b/stm32f4xx__adc_8h__incl.map new file mode 100644 index 0000000..67992bf --- /dev/null +++ b/stm32f4xx__adc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__adc_8h__incl.md5 b/stm32f4xx__adc_8h__incl.md5 new file mode 100644 index 0000000..75d13ca --- /dev/null +++ b/stm32f4xx__adc_8h__incl.md5 @@ -0,0 +1 @@ +86c377c8336eaa3c3d3cd6f9991b83d8 \ No newline at end of file diff --git a/stm32f4xx__adc_8h__incl.png b/stm32f4xx__adc_8h__incl.png new file mode 100644 index 0000000..391f38b Binary files /dev/null and b/stm32f4xx__adc_8h__incl.png differ diff --git a/stm32f4xx__adc_8h_source.html b/stm32f4xx__adc_8h_source.html new file mode 100644 index 0000000..5d2e56f --- /dev/null +++ b/stm32f4xx__adc_8h_source.html @@ -0,0 +1,562 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_adc.h Source File + + + + + + + + + + +
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stm32f4xx_adc.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_ADC_H
+
31 #define __STM32F4xx_ADC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
53 typedef struct
+
54 {
+
55  uint32_t ADC_Resolution;
+
57  FunctionalState ADC_ScanConvMode;
+
61  FunctionalState ADC_ContinuousConvMode;
+
64  uint32_t ADC_ExternalTrigConvEdge;
+
68  uint32_t ADC_ExternalTrigConv;
+
72  uint32_t ADC_DataAlign;
+
75  uint8_t ADC_NbrOfConversion;
+
79 }ADC_InitTypeDef;
+
80 
+
84 typedef struct
+
85 {
+
86  uint32_t ADC_Mode;
+
89  uint32_t ADC_Prescaler;
+
92  uint32_t ADC_DMAAccessMode;
+
96  uint32_t ADC_TwoSamplingDelay;
+
100 }ADC_CommonInitTypeDef;
+
101 
+
102 
+
103 /* Exported constants --------------------------------------------------------*/
+
104 
+
108 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+
109  ((PERIPH) == ADC2) || \
+
110  ((PERIPH) == ADC3))
+
111 
+
115 #define ADC_Mode_Independent ((uint32_t)0x00000000)
+
116 #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
+
117 #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
+
118 #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005)
+
119 #define ADC_DualMode_RegSimult ((uint32_t)0x00000006)
+
120 #define ADC_DualMode_Interl ((uint32_t)0x00000007)
+
121 #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009)
+
122 #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
+
123 #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
+
124 #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
+
125 #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
+
126 #define ADC_TripleMode_Interl ((uint32_t)0x00000017)
+
127 #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
+
128 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+
129  ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+
130  ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+
131  ((MODE) == ADC_DualMode_InjecSimult) || \
+
132  ((MODE) == ADC_DualMode_RegSimult) || \
+
133  ((MODE) == ADC_DualMode_Interl) || \
+
134  ((MODE) == ADC_DualMode_AlterTrig) || \
+
135  ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+
136  ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+
137  ((MODE) == ADC_TripleMode_InjecSimult) || \
+
138  ((MODE) == ADC_TripleMode_RegSimult) || \
+
139  ((MODE) == ADC_TripleMode_Interl) || \
+
140  ((MODE) == ADC_TripleMode_AlterTrig))
+
141 
+
149 #define ADC_Prescaler_Div2 ((uint32_t)0x00000000)
+
150 #define ADC_Prescaler_Div4 ((uint32_t)0x00010000)
+
151 #define ADC_Prescaler_Div6 ((uint32_t)0x00020000)
+
152 #define ADC_Prescaler_Div8 ((uint32_t)0x00030000)
+
153 #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
+
154  ((PRESCALER) == ADC_Prescaler_Div4) || \
+
155  ((PRESCALER) == ADC_Prescaler_Div6) || \
+
156  ((PRESCALER) == ADC_Prescaler_Div8))
+
157 
+
165 #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */
+
166 #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+
167 #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+
168 #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+
169 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+
170  ((MODE) == ADC_DMAAccessMode_1) || \
+
171  ((MODE) == ADC_DMAAccessMode_2) || \
+
172  ((MODE) == ADC_DMAAccessMode_3))
+
173 
+
182 #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
+
183 #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
+
184 #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
+
185 #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
+
186 #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
+
187 #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
+
188 #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
+
189 #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
+
190 #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
+
191 #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
+
192 #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
+
193 #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
+
194 #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
+
195 #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
+
196 #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
+
197 #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
+
198 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+
199  ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+
200  ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+
201  ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+
202  ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+
203  ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+
204  ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+
205  ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+
206  ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+
207  ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+
208  ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+
209  ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+
210  ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+
211  ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+
212  ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+
213  ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+
214 
+
223 #define ADC_Resolution_12b ((uint32_t)0x00000000)
+
224 #define ADC_Resolution_10b ((uint32_t)0x01000000)
+
225 #define ADC_Resolution_8b ((uint32_t)0x02000000)
+
226 #define ADC_Resolution_6b ((uint32_t)0x03000000)
+
227 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+
228  ((RESOLUTION) == ADC_Resolution_10b) || \
+
229  ((RESOLUTION) == ADC_Resolution_8b) || \
+
230  ((RESOLUTION) == ADC_Resolution_6b))
+
231 
+
240 #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
+
241 #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
+
242 #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
+
243 #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+
244 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+
245  ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+
246  ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+
247  ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+
248 
+
256 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
+
257 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000)
+
258 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000)
+
259 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
+
260 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000)
+
261 #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000)
+
262 #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
+
263 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
+
264 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000)
+
265 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000)
+
266 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000)
+
267 #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000)
+
268 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000)
+
269 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000)
+
270 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000)
+
271 #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
+
272 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+
273  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+
274  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+
275  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+
276  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+
277  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+
278  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+
279  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+
280  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+
281  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+
282  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+
283  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+
284  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+
285  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+
286  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+
287  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+
288 
+
296 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
+
297 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
+
298 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+
299  ((ALIGN) == ADC_DataAlign_Left))
+
300 
+
308 #define ADC_Channel_0 ((uint8_t)0x00)
+
309 #define ADC_Channel_1 ((uint8_t)0x01)
+
310 #define ADC_Channel_2 ((uint8_t)0x02)
+
311 #define ADC_Channel_3 ((uint8_t)0x03)
+
312 #define ADC_Channel_4 ((uint8_t)0x04)
+
313 #define ADC_Channel_5 ((uint8_t)0x05)
+
314 #define ADC_Channel_6 ((uint8_t)0x06)
+
315 #define ADC_Channel_7 ((uint8_t)0x07)
+
316 #define ADC_Channel_8 ((uint8_t)0x08)
+
317 #define ADC_Channel_9 ((uint8_t)0x09)
+
318 #define ADC_Channel_10 ((uint8_t)0x0A)
+
319 #define ADC_Channel_11 ((uint8_t)0x0B)
+
320 #define ADC_Channel_12 ((uint8_t)0x0C)
+
321 #define ADC_Channel_13 ((uint8_t)0x0D)
+
322 #define ADC_Channel_14 ((uint8_t)0x0E)
+
323 #define ADC_Channel_15 ((uint8_t)0x0F)
+
324 #define ADC_Channel_16 ((uint8_t)0x10)
+
325 #define ADC_Channel_17 ((uint8_t)0x11)
+
326 #define ADC_Channel_18 ((uint8_t)0x12)
+
327 
+
328 #if defined (STM32F40_41xxx)
+
329 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+
330 #endif /* STM32F40_41xxx */
+
331 
+
332 #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
+
333 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
+
334 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
335 
+
336 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
+
337 #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
+
338 
+
339 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
+
340  ((CHANNEL) == ADC_Channel_1) || \
+
341  ((CHANNEL) == ADC_Channel_2) || \
+
342  ((CHANNEL) == ADC_Channel_3) || \
+
343  ((CHANNEL) == ADC_Channel_4) || \
+
344  ((CHANNEL) == ADC_Channel_5) || \
+
345  ((CHANNEL) == ADC_Channel_6) || \
+
346  ((CHANNEL) == ADC_Channel_7) || \
+
347  ((CHANNEL) == ADC_Channel_8) || \
+
348  ((CHANNEL) == ADC_Channel_9) || \
+
349  ((CHANNEL) == ADC_Channel_10) || \
+
350  ((CHANNEL) == ADC_Channel_11) || \
+
351  ((CHANNEL) == ADC_Channel_12) || \
+
352  ((CHANNEL) == ADC_Channel_13) || \
+
353  ((CHANNEL) == ADC_Channel_14) || \
+
354  ((CHANNEL) == ADC_Channel_15) || \
+
355  ((CHANNEL) == ADC_Channel_16) || \
+
356  ((CHANNEL) == ADC_Channel_17) || \
+
357  ((CHANNEL) == ADC_Channel_18))
+
358 
+
366 #define ADC_SampleTime_3Cycles ((uint8_t)0x00)
+
367 #define ADC_SampleTime_15Cycles ((uint8_t)0x01)
+
368 #define ADC_SampleTime_28Cycles ((uint8_t)0x02)
+
369 #define ADC_SampleTime_56Cycles ((uint8_t)0x03)
+
370 #define ADC_SampleTime_84Cycles ((uint8_t)0x04)
+
371 #define ADC_SampleTime_112Cycles ((uint8_t)0x05)
+
372 #define ADC_SampleTime_144Cycles ((uint8_t)0x06)
+
373 #define ADC_SampleTime_480Cycles ((uint8_t)0x07)
+
374 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
+
375  ((TIME) == ADC_SampleTime_15Cycles) || \
+
376  ((TIME) == ADC_SampleTime_28Cycles) || \
+
377  ((TIME) == ADC_SampleTime_56Cycles) || \
+
378  ((TIME) == ADC_SampleTime_84Cycles) || \
+
379  ((TIME) == ADC_SampleTime_112Cycles) || \
+
380  ((TIME) == ADC_SampleTime_144Cycles) || \
+
381  ((TIME) == ADC_SampleTime_480Cycles))
+
382 
+
390 #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
+
391 #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
+
392 #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
+
393 #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+
394 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+
395  ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+
396  ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+
397  ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+
398 
+
407 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000)
+
408 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000)
+
409 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000)
+
410 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000)
+
411 #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000)
+
412 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000)
+
413 #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
+
414 #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
+
415 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
+
416 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000)
+
417 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000)
+
418 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000)
+
419 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000)
+
420 #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000)
+
421 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000)
+
422 #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
+
423 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+
424  ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+
425  ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+
426  ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+
427  ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+
428  ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+
429  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+
430  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+
431  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+
432  ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+
433  ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+
434  ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+
435  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+
436  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+
437  ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+
438  ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+
439 
+
447 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
+
448 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
+
449 #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+
450 #define ADC_InjectedChannel_4 ((uint8_t)0x20)
+
451 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+
452  ((CHANNEL) == ADC_InjectedChannel_2) || \
+
453  ((CHANNEL) == ADC_InjectedChannel_3) || \
+
454  ((CHANNEL) == ADC_InjectedChannel_4))
+
455 
+
463 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+
464 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+
465 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+
466 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+
467 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+
468 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+
469 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
470 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+
471  ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+
472  ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+
473  ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+
474  ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+
475  ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+
476  ((WATCHDOG) == ADC_AnalogWatchdog_None))
+
477 
+
485 #define ADC_IT_EOC ((uint16_t)0x0205)
+
486 #define ADC_IT_AWD ((uint16_t)0x0106)
+
487 #define ADC_IT_JEOC ((uint16_t)0x0407)
+
488 #define ADC_IT_OVR ((uint16_t)0x201A)
+
489 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+
490  ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
+
491 
+
499 #define ADC_FLAG_AWD ((uint8_t)0x01)
+
500 #define ADC_FLAG_EOC ((uint8_t)0x02)
+
501 #define ADC_FLAG_JEOC ((uint8_t)0x04)
+
502 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
+
503 #define ADC_FLAG_STRT ((uint8_t)0x10)
+
504 #define ADC_FLAG_OVR ((uint8_t)0x20)
+
505 
+
506 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))
+
507 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
+
508  ((FLAG) == ADC_FLAG_EOC) || \
+
509  ((FLAG) == ADC_FLAG_JEOC) || \
+
510  ((FLAG)== ADC_FLAG_JSTRT) || \
+
511  ((FLAG) == ADC_FLAG_STRT) || \
+
512  ((FLAG)== ADC_FLAG_OVR))
+
513 
+
521 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
522 
+
530 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
531 
+
539 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
540 
+
548 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
549 
+
557 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+
558 
+
566 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
567 
+
575 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
576 
+
585 /* Exported macro ------------------------------------------------------------*/
+
586 /* Exported functions --------------------------------------------------------*/
+
587 
+
588 /* Function used to set the ADC configuration to the default reset state *****/
+
589 void ADC_DeInit(void);
+
590 
+
591 /* Initialization and Configuration functions *********************************/
+
592 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+
593 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+
594 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+
595 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+
596 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
597 
+
598 /* Analog Watchdog configuration functions ************************************/
+
599 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+
600 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+
601 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
602 
+
603 /* Temperature Sensor, Vrefint and VBAT management functions ******************/
+
604 void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+
605 void ADC_VBATCmd(FunctionalState NewState);
+
606 
+
607 /* Regular Channels Configuration functions ***********************************/
+
608 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+
609 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+
610 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+
611 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
612 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
613 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+
614 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
615 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
616 uint32_t ADC_GetMultiModeConversionValue(void);
+
617 
+
618 /* Regular Channels DMA Configuration functions *******************************/
+
619 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
620 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
621 void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
+
622 
+
623 /* Injected channels Configuration functions **********************************/
+
624 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+
625 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+
626 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+
627 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+
628 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+
629 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+
630 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+
631 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
632 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
633 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
634 
+
635 /* Interrupts and flags management functions **********************************/
+
636 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+
637 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+
638 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+
639 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
640 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
641 
+
642 #ifdef __cplusplus
+
643 }
+
644 #endif
+
645 
+
646 #endif /*__STM32F4xx_ADC_H */
+
647 
+
656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
ADC_EOCOnEachRegularChannelCmd
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the EOC on each regular channel conversion.
Definition: stm32f4xx_adc.c:879
+
ADC_GetSoftwareStartInjectedConvCmdStatus
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start injected conversion Status.
Definition: stm32f4xx_adc.c:1394
+
ADC_ClearITPendingBit
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Clears the ADCx's interrupt pending bits.
Definition: stm32f4xx_adc.c:1718
+
ADC_TempSensorVrefintCmd
void ADC_TempSensorVrefintCmd(FunctionalState NewState)
Enables or disables the temperature sensor and Vrefint channels.
Definition: stm32f4xx_adc.c:589
+
ADC_DiscModeChannelCountConfig
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
Configures the discontinuous mode for the selected ADC regular group channel.
Definition: stm32f4xx_adc.c:930
+
ADC_CommonInitTypeDef::ADC_DMAAccessMode
uint32_t ADC_DMAAccessMode
Definition: stm32f4xx_adc.h:92
+
ADC_VBATCmd
void ADC_VBATCmd(FunctionalState NewState)
Enables or disables the VBAT (Voltage Battery) channel.
Definition: stm32f4xx_adc.c:615
+
ADC_InitTypeDef::ADC_NbrOfConversion
uint8_t ADC_NbrOfConversion
Definition: stm32f4xx_adc.h:75
+
ADC_Cmd
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC peripheral.
Definition: stm32f4xx_adc.c:399
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
ADC_DeInit
void ADC_DeInit(void)
Deinitializes all ADCs peripherals registers to their default reset values.
Definition: stm32f4xx_adc.c:213
+
ADC_ExternalTrigInjectedConvEdgeConfig
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
Configures the ADCx external trigger edge for injected channels conversion.
Definition: stm32f4xx_adc.c:1360
+
ADC_GetITStatus
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
Checks whether the specified ADC interrupt has occurred or not.
Definition: stm32f4xx_adc.c:1677
+
ADC_InitTypeDef
ADC Init structure definition.
Definition: stm32f4xx_adc.h:53
+
ADC_SoftwareStartInjectedConv
void ADC_SoftwareStartInjectedConv(ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the injected channels.
Definition: stm32f4xx_adc.c:1381
+
ADC_AnalogWatchdogSingleChannelConfig
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
Configures the analog watchdog guarded single channel.
Definition: stm32f4xx_adc.c:525
+
ADC_CommonInitTypeDef::ADC_Prescaler
uint32_t ADC_Prescaler
Definition: stm32f4xx_adc.h:89
+
ADC_AnalogWatchdogThresholdsConfig
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
Configures the high and low thresholds of the analog watchdog.
Definition: stm32f4xx_adc.c:484
+
ADC_InitTypeDef::ADC_ExternalTrigConvEdge
uint32_t ADC_ExternalTrigConvEdge
Definition: stm32f4xx_adc.h:64
+
ADC_GetSoftwareStartConvStatus
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
Gets the selected ADC Software start regular conversion Status.
Definition: stm32f4xx_adc.c:849
+
ADC_ContinuousModeCmd
void ADC_ContinuousModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC continuous conversion mode.
Definition: stm32f4xx_adc.c:904
+
ADC_AnalogWatchdogCmd
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
Enables or disables the analog watchdog on single/all regular or injected channels.
Definition: stm32f4xx_adc.c:455
+
ADC_InjectedChannelConfig
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC injected channel its corresponding rank in the sequencer and its samp...
Definition: stm32f4xx_adc.c:1190
+
ADC_DMACmd
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the specified ADC DMA request.
Definition: stm32f4xx_adc.c:1052
+
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:531
+
ADC_Init
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct.
Definition: stm32f4xx_adc.c:235
+
ADC_CommonInitTypeDef::ADC_Mode
uint32_t ADC_Mode
Definition: stm32f4xx_adc.h:86
+
ADC_DiscModeCmd
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode on regular group channel for the specified ADC...
Definition: stm32f4xx_adc.c:962
+
ADC_MultiModeDMARequestAfterLastTransferCmd
void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer in multi ADC mode.
Definition: stm32f4xx_adc.c:1103
+
ADC_GetConversionValue
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
Returns the last ADCx conversion result data for regular channel.
Definition: stm32f4xx_adc.c:985
+
ADC_InitTypeDef::ADC_DataAlign
uint32_t ADC_DataAlign
Definition: stm32f4xx_adc.h:72
+
ADC_CommonInit
void ADC_CommonInit(ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initializes the ADCs peripherals according to the specified parameters in the ADC_CommonInitStruct.
Definition: stm32f4xx_adc.c:341
+
ADC_InjectedDiscModeCmd
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the discontinuous mode for injected group channel for the specified ADC...
Definition: stm32f4xx_adc.c:1449
+
ADC_GetMultiModeConversionValue
uint32_t ADC_GetMultiModeConversionValue(void)
Returns the last ADC1, ADC2 and ADC3 regular conversions results data in the selected multi mode...
Definition: stm32f4xx_adc.c:1006
+
ADC_ExternalTrigInjectedConvConfig
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
Configures the ADCx external trigger for injected channels conversion.
Definition: stm32f4xx_adc.c:1326
+
ADC_ITConfig
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
Enables or disables the specified ADC interrupts.
Definition: stm32f4xx_adc.c:1584
+
ADC_InjectedSequencerLengthConfig
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
Configures the sequencer length for injected channels.
Definition: stm32f4xx_adc.c:1253
+
ADC_InitTypeDef::ADC_ScanConvMode
FunctionalState ADC_ScanConvMode
Definition: stm32f4xx_adc.h:57
+
ADC_GetFlagStatus
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Checks whether the specified ADC flag is set or not.
Definition: stm32f4xx_adc.c:1621
+
ADC_SoftwareStartConv
void ADC_SoftwareStartConv(ADC_TypeDef *ADCx)
Enables the selected ADC software start conversion of the regular channels.
Definition: stm32f4xx_adc.c:835
+
ADC_StructInit
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
Fills each ADC_InitStruct member with its default value.
Definition: stm32f4xx_adc.c:310
+
ADC_InitTypeDef::ADC_Resolution
uint32_t ADC_Resolution
Definition: stm32f4xx_adc.h:55
+
ADC_CommonInitTypeDef
ADC Common Init structure definition.
Definition: stm32f4xx_adc.h:84
+
ADC_DMARequestAfterLastTransferCmd
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
Definition: stm32f4xx_adc.c:1076
+
ADC_GetInjectedConversionValue
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
Returns the ADC injected channel conversion result.
Definition: stm32f4xx_adc.c:1477
+
ADC_InitTypeDef::ADC_ExternalTrigConv
uint32_t ADC_ExternalTrigConv
Definition: stm32f4xx_adc.h:68
+
ADC_InitTypeDef::ADC_ContinuousConvMode
FunctionalState ADC_ContinuousConvMode
Definition: stm32f4xx_adc.h:61
+
ADC_RegularChannelConfig
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sampl...
Definition: stm32f4xx_adc.c:715
+
ADC_SetInjectedOffset
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
Set the injected channels conversion value offset.
Definition: stm32f4xx_adc.c:1288
+
ADC_CommonStructInit
void ADC_CommonStructInit(ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Fills each ADC_CommonInitStruct member with its default value.
Definition: stm32f4xx_adc.c:377
+
ADC_CommonInitTypeDef::ADC_TwoSamplingDelay
uint32_t ADC_TwoSamplingDelay
Definition: stm32f4xx_adc.h:96
+
ADC_AutoInjectedConvCmd
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
Enables or disables the selected ADC automatic injected group conversion after regular one...
Definition: stm32f4xx_adc.c:1423
+
ADC_ClearFlag
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
Clears the ADCx's pending flags.
Definition: stm32f4xx_adc.c:1656
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__can_8c.html b/stm32f4xx__can_8c.html new file mode 100644 index 0000000..88a3db8 --- /dev/null +++ b/stm32f4xx__can_8c.html @@ -0,0 +1,306 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_can.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions
+
+
stm32f4xx_can.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Controller area network (CAN) peripheral: +More...

+
#include "stm32f4xx_can.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_can.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define MCR_DBF   ((uint32_t)0x00010000) /* software master reset */
 
+#define TMIDxR_TXRQ   ((uint32_t)0x00000001) /* Transmit mailbox request */
 
+#define FMR_FINIT   ((uint32_t)0x00000001) /* Filter init mode */
 
+#define INAK_TIMEOUT   ((uint32_t)0x0000FFFF)
 
+#define SLAK_TIMEOUT   ((uint32_t)0x0000FFFF)
 
+#define CAN_FLAGS_TSR   ((uint32_t)0x08000000)
 
+#define CAN_FLAGS_RF1R   ((uint32_t)0x04000000)
 
+#define CAN_FLAGS_RF0R   ((uint32_t)0x02000000)
 
+#define CAN_FLAGS_MSR   ((uint32_t)0x01000000)
 
+#define CAN_FLAGS_ESR   ((uint32_t)0x00F00000)
 
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
 
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
 
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
 
+#define CAN_MODE_MASK   ((uint32_t) 0x00000003)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CAN_DeInit (CAN_TypeDef *CANx)
 Deinitializes the CAN peripheral registers to their default reset values. More...
 
uint8_t CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
 Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct. More...
 
void CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
 Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct. More...
 
void CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
 Fills each CAN_InitStruct member with its default value. More...
 
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
 Select the start bank filter for slave CAN. More...
 
void CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the DBG Freeze for CAN. More...
 
void CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the CAN Time TriggerOperation communication mode. More...
 
uint8_t CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
 Initiates and transmits a CAN frame message. More...
 
uint8_t CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
 Checks the transmission status of a CAN Frame. More...
 
void CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
 Cancels a transmit request. More...
 
void CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
 Receives a correct CAN frame. More...
 
void CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Releases the specified receive FIFO. More...
 
uint8_t CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Returns the number of pending received messages. More...
 
uint8_t CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
 Selects the CAN Operation mode. More...
 
uint8_t CAN_Sleep (CAN_TypeDef *CANx)
 Enters the Sleep (low power) mode. More...
 
uint8_t CAN_WakeUp (CAN_TypeDef *CANx)
 Wakes up the CAN peripheral from sleep mode . More...
 
uint8_t CAN_GetLastErrorCode (CAN_TypeDef *CANx)
 Returns the CANx's last error code (LEC). More...
 
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
 Returns the CANx Receive Error Counter (REC). More...
 
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
 Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). More...
 
void CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
 Enables or disables the specified CANx interrupts. More...
 
FlagStatus CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Checks whether the specified CAN flag is set or not. More...
 
void CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Clears the CAN's pending flags. More...
 
ITStatus CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Checks whether the specified CANx interrupt has occurred or not. More...
 
void CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Clears the CANx's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Controller area network (CAN) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • CAN Frames Transmission
    • +
  • CAN Frames Reception
    • +
  • Operation modes switch
    • +
  • Error management
    • +
  • Interrupts and flags
    • +
+
+
 ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+      (#) Enable the CAN controller interface clock using 
+          RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 
+          and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
+      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+       
+      (#) CAN pins configuration
+        (++) Enable the clock for the CAN GPIOs using the following function:
+             RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+        (++) Connect the involved CAN pins to AF9 using the following function 
+             GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); 
+        (++) Configure these CAN pins in alternate function mode by calling
+             the function  GPIO_Init();
+      
+      (#) Initialise and configure the CAN using CAN_Init() and 
+          CAN_FilterInit() functions.   
+                 
+      (#) Transmit the desired CAN frame using CAN_Transmit() function.
+           
+      (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
+          function.
+                 
+      (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
+          function.  
+              
+      (#) Receive a CAN frame using CAN_Recieve() function.
+           
+      (#) Release the receive FIFOs using CAN_FIFORelease() function.
+                 
+      (#) Return the number of pending received frames using 
+          CAN_MessagePending() function.            
+                     
+      (#) To control CAN events you can use one of the following two methods:
+        (++) Check on CAN flags using the CAN_GetFlagStatus() function.  
+        (++) Use CAN interrupts through the function CAN_ITConfig() at 
+             initialization phase and CAN_GetITStatus() function into 
+             interrupt routines to check if the event has occurred or not.
+             After checking on a flag you should clear it using CAN_ClearFlag()
+             function. And after checking on an interrupt event you should 
+             clear it using CAN_ClearITPendingBit() function.            
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__can_8c__incl.map b/stm32f4xx__can_8c__incl.map new file mode 100644 index 0000000..fff8932 --- /dev/null +++ b/stm32f4xx__can_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__can_8c__incl.md5 b/stm32f4xx__can_8c__incl.md5 new file mode 100644 index 0000000..793a255 --- /dev/null +++ b/stm32f4xx__can_8c__incl.md5 @@ -0,0 +1 @@ +2c3f2a78abf0b58b2be6f2ece1c9b96d \ No newline at end of file diff --git a/stm32f4xx__can_8c__incl.png b/stm32f4xx__can_8c__incl.png new file mode 100644 index 0000000..ca33550 Binary files /dev/null and b/stm32f4xx__can_8c__incl.png differ diff --git a/stm32f4xx__can_8h.html b/stm32f4xx__can_8h.html new file mode 100644 index 0000000..048a463 --- /dev/null +++ b/stm32f4xx__can_8h.html @@ -0,0 +1,534 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_can.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_can.h File Reference
+
+
+ +

This file contains all the functions prototypes for the CAN firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_can.h:
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+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Classes

struct  CAN_InitTypeDef
 CAN init structure definition. More...
 
struct  CAN_FilterInitTypeDef
 CAN filter init structure definition. More...
 
struct  CanTxMsg
 CAN Tx message structure definition. More...
 
struct  CanRxMsg
 CAN Rx message structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_CAN_ALL_PERIPH(PERIPH)
 
#define CAN_InitStatus_Failed   ((uint8_t)0x00)
 
#define CAN_InitStatus_Success   ((uint8_t)0x01)
 
+#define CANINITFAILED   CAN_InitStatus_Failed
 
+#define CANINITOK   CAN_InitStatus_Success
 
#define CAN_Mode_Normal   ((uint8_t)0x00)
 
#define CAN_Mode_LoopBack   ((uint8_t)0x01)
 
#define CAN_Mode_Silent   ((uint8_t)0x02)
 
#define CAN_Mode_Silent_LoopBack   ((uint8_t)0x03)
 
#define IS_CAN_MODE(MODE)
 
#define CAN_OperatingMode_Initialization   ((uint8_t)0x00)
 
#define CAN_OperatingMode_Normal   ((uint8_t)0x01)
 
#define CAN_OperatingMode_Sleep   ((uint8_t)0x02)
 
#define IS_CAN_OPERATING_MODE(MODE)
 
#define CAN_ModeStatus_Failed   ((uint8_t)0x00)
 
#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)
 
#define CAN_SJW_1tq   ((uint8_t)0x00)
 
#define CAN_SJW_2tq   ((uint8_t)0x01)
 
#define CAN_SJW_3tq   ((uint8_t)0x02)
 
#define CAN_SJW_4tq   ((uint8_t)0x03)
 
#define IS_CAN_SJW(SJW)
 
#define CAN_BS1_1tq   ((uint8_t)0x00)
 
#define CAN_BS1_2tq   ((uint8_t)0x01)
 
#define CAN_BS1_3tq   ((uint8_t)0x02)
 
#define CAN_BS1_4tq   ((uint8_t)0x03)
 
#define CAN_BS1_5tq   ((uint8_t)0x04)
 
#define CAN_BS1_6tq   ((uint8_t)0x05)
 
#define CAN_BS1_7tq   ((uint8_t)0x06)
 
#define CAN_BS1_8tq   ((uint8_t)0x07)
 
#define CAN_BS1_9tq   ((uint8_t)0x08)
 
#define CAN_BS1_10tq   ((uint8_t)0x09)
 
#define CAN_BS1_11tq   ((uint8_t)0x0A)
 
#define CAN_BS1_12tq   ((uint8_t)0x0B)
 
#define CAN_BS1_13tq   ((uint8_t)0x0C)
 
#define CAN_BS1_14tq   ((uint8_t)0x0D)
 
#define CAN_BS1_15tq   ((uint8_t)0x0E)
 
#define CAN_BS1_16tq   ((uint8_t)0x0F)
 
+#define IS_CAN_BS1(BS1)   ((BS1) <= CAN_BS1_16tq)
 
#define CAN_BS2_1tq   ((uint8_t)0x00)
 
#define CAN_BS2_2tq   ((uint8_t)0x01)
 
#define CAN_BS2_3tq   ((uint8_t)0x02)
 
#define CAN_BS2_4tq   ((uint8_t)0x03)
 
#define CAN_BS2_5tq   ((uint8_t)0x04)
 
#define CAN_BS2_6tq   ((uint8_t)0x05)
 
#define CAN_BS2_7tq   ((uint8_t)0x06)
 
#define CAN_BS2_8tq   ((uint8_t)0x07)
 
+#define IS_CAN_BS2(BS2)   ((BS2) <= CAN_BS2_8tq)
 
+#define IS_CAN_PRESCALER(PRESCALER)   (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
 
+#define IS_CAN_FILTER_NUMBER(NUMBER)   ((NUMBER) <= 27)
 
#define CAN_FilterMode_IdMask   ((uint8_t)0x00)
 
#define CAN_FilterMode_IdList   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_MODE(MODE)
 
#define CAN_FilterScale_16bit   ((uint8_t)0x00)
 
#define CAN_FilterScale_32bit   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_SCALE(SCALE)
 
#define CAN_Filter_FIFO0   ((uint8_t)0x00)
 
#define CAN_Filter_FIFO1   ((uint8_t)0x01)
 
#define IS_CAN_FILTER_FIFO(FIFO)
 
+#define CAN_FilterFIFO0   CAN_Filter_FIFO0
 
+#define CAN_FilterFIFO1   CAN_Filter_FIFO1
 
+#define IS_CAN_BANKNUMBER(BANKNUMBER)   (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
 
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX)   ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
 
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
 
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
 
+#define IS_CAN_DLC(DLC)   ((DLC) <= ((uint8_t)0x08))
 
#define CAN_Id_Standard   ((uint32_t)0x00000000)
 
#define CAN_Id_Extended   ((uint32_t)0x00000004)
 
#define IS_CAN_IDTYPE(IDTYPE)
 
+#define CAN_ID_STD   CAN_Id_Standard
 
+#define CAN_ID_EXT   CAN_Id_Extended
 
#define CAN_RTR_Data   ((uint32_t)0x00000000)
 
#define CAN_RTR_Remote   ((uint32_t)0x00000002)
 
+#define IS_CAN_RTR(RTR)   (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
 
+#define CAN_RTR_DATA   CAN_RTR_Data
 
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
 
#define CAN_TxStatus_Failed   ((uint8_t)0x00)
 
#define CAN_TxStatus_Ok   ((uint8_t)0x01)
 
#define CAN_TxStatus_Pending   ((uint8_t)0x02)
 
#define CAN_TxStatus_NoMailBox   ((uint8_t)0x04)
 
+#define CANTXFAILED   CAN_TxStatus_Failed
 
+#define CANTXOK   CAN_TxStatus_Ok
 
+#define CANTXPENDING   CAN_TxStatus_Pending
 
+#define CAN_NO_MB   CAN_TxStatus_NoMailBox
 
#define CAN_FIFO0   ((uint8_t)0x00)
 
#define CAN_FIFO1   ((uint8_t)0x01)
 
+#define IS_CAN_FIFO(FIFO)   (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
 
#define CAN_Sleep_Failed   ((uint8_t)0x00)
 
#define CAN_Sleep_Ok   ((uint8_t)0x01)
 
+#define CANSLEEPFAILED   CAN_Sleep_Failed
 
+#define CANSLEEPOK   CAN_Sleep_Ok
 
#define CAN_WakeUp_Failed   ((uint8_t)0x00)
 
#define CAN_WakeUp_Ok   ((uint8_t)0x01)
 
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed
 
+#define CANWAKEUPOK   CAN_WakeUp_Ok
 
#define CAN_ErrorCode_NoErr   ((uint8_t)0x00)
 
#define CAN_ErrorCode_StuffErr   ((uint8_t)0x10)
 
#define CAN_ErrorCode_FormErr   ((uint8_t)0x20)
 
#define CAN_ErrorCode_ACKErr   ((uint8_t)0x30)
 
#define CAN_ErrorCode_BitRecessiveErr   ((uint8_t)0x40)
 
#define CAN_ErrorCode_BitDominantErr   ((uint8_t)0x50)
 
#define CAN_ErrorCode_CRCErr   ((uint8_t)0x60)
 
#define CAN_ErrorCode_SoftwareSetErr   ((uint8_t)0x70)
 
#define CAN_FLAG_RQCP0   ((uint32_t)0x38000001)
 
#define CAN_FLAG_RQCP1   ((uint32_t)0x38000100)
 
#define CAN_FLAG_RQCP2   ((uint32_t)0x38010000)
 
#define CAN_FLAG_FMP0   ((uint32_t)0x12000003)
 
#define CAN_FLAG_FF0   ((uint32_t)0x32000008)
 
#define CAN_FLAG_FOV0   ((uint32_t)0x32000010)
 
#define CAN_FLAG_FMP1   ((uint32_t)0x14000003)
 
#define CAN_FLAG_FF1   ((uint32_t)0x34000008)
 
#define CAN_FLAG_FOV1   ((uint32_t)0x34000010)
 
#define CAN_FLAG_WKU   ((uint32_t)0x31000008)
 
#define CAN_FLAG_SLAK   ((uint32_t)0x31000012)
 
#define CAN_FLAG_EWG   ((uint32_t)0x10F00001)
 
#define CAN_FLAG_EPV   ((uint32_t)0x10F00002)
 
#define CAN_FLAG_BOF   ((uint32_t)0x10F00004)
 
#define CAN_FLAG_LEC   ((uint32_t)0x30F00070)
 
#define IS_CAN_GET_FLAG(FLAG)
 
#define IS_CAN_CLEAR_FLAG(FLAG)
 
#define CAN_IT_TME   ((uint32_t)0x00000001)
 
#define CAN_IT_FMP0   ((uint32_t)0x00000002)
 
#define CAN_IT_FF0   ((uint32_t)0x00000004)
 
#define CAN_IT_FOV0   ((uint32_t)0x00000008)
 
#define CAN_IT_FMP1   ((uint32_t)0x00000010)
 
#define CAN_IT_FF1   ((uint32_t)0x00000020)
 
#define CAN_IT_FOV1   ((uint32_t)0x00000040)
 
#define CAN_IT_WKU   ((uint32_t)0x00010000)
 
#define CAN_IT_SLK   ((uint32_t)0x00020000)
 
#define CAN_IT_EWG   ((uint32_t)0x00000100)
 
#define CAN_IT_EPV   ((uint32_t)0x00000200)
 
#define CAN_IT_BOF   ((uint32_t)0x00000400)
 
#define CAN_IT_LEC   ((uint32_t)0x00000800)
 
#define CAN_IT_ERR   ((uint32_t)0x00008000)
 
+#define CAN_IT_RQCP0   CAN_IT_TME
 
+#define CAN_IT_RQCP1   CAN_IT_TME
 
+#define CAN_IT_RQCP2   CAN_IT_TME
 
#define IS_CAN_IT(IT)
 
#define IS_CAN_CLEAR_IT(IT)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CAN_DeInit (CAN_TypeDef *CANx)
 Deinitializes the CAN peripheral registers to their default reset values. More...
 
uint8_t CAN_Init (CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
 Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct. More...
 
void CAN_FilterInit (CAN_FilterInitTypeDef *CAN_FilterInitStruct)
 Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct. More...
 
void CAN_StructInit (CAN_InitTypeDef *CAN_InitStruct)
 Fills each CAN_InitStruct member with its default value. More...
 
void CAN_SlaveStartBank (uint8_t CAN_BankNumber)
 Select the start bank filter for slave CAN. More...
 
void CAN_DBGFreeze (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the DBG Freeze for CAN. More...
 
void CAN_TTComModeCmd (CAN_TypeDef *CANx, FunctionalState NewState)
 Enables or disables the CAN Time TriggerOperation communication mode. More...
 
uint8_t CAN_Transmit (CAN_TypeDef *CANx, CanTxMsg *TxMessage)
 Initiates and transmits a CAN frame message. More...
 
uint8_t CAN_TransmitStatus (CAN_TypeDef *CANx, uint8_t TransmitMailbox)
 Checks the transmission status of a CAN Frame. More...
 
void CAN_CancelTransmit (CAN_TypeDef *CANx, uint8_t Mailbox)
 Cancels a transmit request. More...
 
void CAN_Receive (CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
 Receives a correct CAN frame. More...
 
void CAN_FIFORelease (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Releases the specified receive FIFO. More...
 
uint8_t CAN_MessagePending (CAN_TypeDef *CANx, uint8_t FIFONumber)
 Returns the number of pending received messages. More...
 
uint8_t CAN_OperatingModeRequest (CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
 Selects the CAN Operation mode. More...
 
uint8_t CAN_Sleep (CAN_TypeDef *CANx)
 Enters the Sleep (low power) mode. More...
 
uint8_t CAN_WakeUp (CAN_TypeDef *CANx)
 Wakes up the CAN peripheral from sleep mode . More...
 
uint8_t CAN_GetLastErrorCode (CAN_TypeDef *CANx)
 Returns the CANx's last error code (LEC). More...
 
uint8_t CAN_GetReceiveErrorCounter (CAN_TypeDef *CANx)
 Returns the CANx Receive Error Counter (REC). More...
 
uint8_t CAN_GetLSBTransmitErrorCounter (CAN_TypeDef *CANx)
 Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). More...
 
void CAN_ITConfig (CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
 Enables or disables the specified CANx interrupts. More...
 
FlagStatus CAN_GetFlagStatus (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Checks whether the specified CAN flag is set or not. More...
 
void CAN_ClearFlag (CAN_TypeDef *CANx, uint32_t CAN_FLAG)
 Clears the CAN's pending flags. More...
 
ITStatus CAN_GetITStatus (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Checks whether the specified CANx interrupt has occurred or not. More...
 
void CAN_ClearITPendingBit (CAN_TypeDef *CANx, uint32_t CAN_IT)
 Clears the CANx's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the CAN firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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+ + diff --git a/stm32f4xx__can_8h__dep__incl.map b/stm32f4xx__can_8h__dep__incl.map new file mode 100644 index 0000000..fcbf93c --- /dev/null +++ b/stm32f4xx__can_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__can_8h__dep__incl.md5 b/stm32f4xx__can_8h__dep__incl.md5 new file mode 100644 index 0000000..51def86 --- /dev/null +++ b/stm32f4xx__can_8h__dep__incl.md5 @@ -0,0 +1 @@ +53eaf4a09b340e066275fc98c4f1d17a \ No newline at end of file diff --git a/stm32f4xx__can_8h__dep__incl.png b/stm32f4xx__can_8h__dep__incl.png new file mode 100644 index 0000000..3a1076d Binary files /dev/null and b/stm32f4xx__can_8h__dep__incl.png differ diff --git a/stm32f4xx__can_8h__incl.map b/stm32f4xx__can_8h__incl.map new file mode 100644 index 0000000..b10e7e1 --- /dev/null +++ b/stm32f4xx__can_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__can_8h__incl.md5 b/stm32f4xx__can_8h__incl.md5 new file mode 100644 index 0000000..e4a5794 --- /dev/null +++ b/stm32f4xx__can_8h__incl.md5 @@ -0,0 +1 @@ +e5aee0e25d43874e347a7d9e4d70506d \ No newline at end of file diff --git a/stm32f4xx__can_8h__incl.png b/stm32f4xx__can_8h__incl.png new file mode 100644 index 0000000..f2b6a8d Binary files /dev/null and b/stm32f4xx__can_8h__incl.png differ diff --git a/stm32f4xx__can_8h_source.html b/stm32f4xx__can_8h_source.html new file mode 100644 index 0000000..b27122f --- /dev/null +++ b/stm32f4xx__can_8h_source.html @@ -0,0 +1,498 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_can.h Source File + + + + + + + + + + +
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stm32f4xx_can.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_CAN_H
+
31 #define __STM32F4xx_CAN_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
50 #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+
51  ((PERIPH) == CAN2))
+
52 
+
56 typedef struct
+
57 {
+
58  uint16_t CAN_Prescaler;
+
61  uint8_t CAN_Mode;
+
64  uint8_t CAN_SJW;
+
69  uint8_t CAN_BS1;
+
73  uint8_t CAN_BS2;
+
76  FunctionalState CAN_TTCM;
+
79  FunctionalState CAN_ABOM;
+
82  FunctionalState CAN_AWUM;
+
85  FunctionalState CAN_NART;
+
88  FunctionalState CAN_RFLM;
+
91  FunctionalState CAN_TXFP;
+
93 } CAN_InitTypeDef;
+
94 
+
98 typedef struct
+
99 {
+
100  uint16_t CAN_FilterIdHigh;
+
104  uint16_t CAN_FilterIdLow;
+
108  uint16_t CAN_FilterMaskIdHigh;
+
113  uint16_t CAN_FilterMaskIdLow;
+
118  uint16_t CAN_FilterFIFOAssignment;
+
121  uint8_t CAN_FilterNumber;
+
123  uint8_t CAN_FilterMode;
+
126  uint8_t CAN_FilterScale;
+
129  FunctionalState CAN_FilterActivation;
+
131 } CAN_FilterInitTypeDef;
+
132 
+
136 typedef struct
+
137 {
+
138  uint32_t StdId;
+
141  uint32_t ExtId;
+
144  uint8_t IDE;
+
148  uint8_t RTR;
+
152  uint8_t DLC;
+
156  uint8_t Data[8];
+
158 } CanTxMsg;
+
159 
+
163 typedef struct
+
164 {
+
165  uint32_t StdId;
+
168  uint32_t ExtId;
+
171  uint8_t IDE;
+
175  uint8_t RTR;
+
179  uint8_t DLC;
+
182  uint8_t Data[8];
+
185  uint8_t FMI;
+
188 } CanRxMsg;
+
189 
+
190 /* Exported constants --------------------------------------------------------*/
+
191 
+
200 #define CAN_InitStatus_Failed ((uint8_t)0x00)
+
201 #define CAN_InitStatus_Success ((uint8_t)0x01)
+
204 /* Legacy defines */
+
205 #define CANINITFAILED CAN_InitStatus_Failed
+
206 #define CANINITOK CAN_InitStatus_Success
+
207 
+
215 #define CAN_Mode_Normal ((uint8_t)0x00)
+
216 #define CAN_Mode_LoopBack ((uint8_t)0x01)
+
217 #define CAN_Mode_Silent ((uint8_t)0x02)
+
218 #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03)
+
220 #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+
221  ((MODE) == CAN_Mode_LoopBack)|| \
+
222  ((MODE) == CAN_Mode_Silent) || \
+
223  ((MODE) == CAN_Mode_Silent_LoopBack))
+
224 
+
233 #define CAN_OperatingMode_Initialization ((uint8_t)0x00)
+
234 #define CAN_OperatingMode_Normal ((uint8_t)0x01)
+
235 #define CAN_OperatingMode_Sleep ((uint8_t)0x02)
+
238 #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+
239  ((MODE) == CAN_OperatingMode_Normal)|| \
+
240  ((MODE) == CAN_OperatingMode_Sleep))
+
241 
+
250 #define CAN_ModeStatus_Failed ((uint8_t)0x00)
+
251 #define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed)
+
259 #define CAN_SJW_1tq ((uint8_t)0x00)
+
260 #define CAN_SJW_2tq ((uint8_t)0x01)
+
261 #define CAN_SJW_3tq ((uint8_t)0x02)
+
262 #define CAN_SJW_4tq ((uint8_t)0x03)
+
264 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+
265  ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+
266 
+
273 #define CAN_BS1_1tq ((uint8_t)0x00)
+
274 #define CAN_BS1_2tq ((uint8_t)0x01)
+
275 #define CAN_BS1_3tq ((uint8_t)0x02)
+
276 #define CAN_BS1_4tq ((uint8_t)0x03)
+
277 #define CAN_BS1_5tq ((uint8_t)0x04)
+
278 #define CAN_BS1_6tq ((uint8_t)0x05)
+
279 #define CAN_BS1_7tq ((uint8_t)0x06)
+
280 #define CAN_BS1_8tq ((uint8_t)0x07)
+
281 #define CAN_BS1_9tq ((uint8_t)0x08)
+
282 #define CAN_BS1_10tq ((uint8_t)0x09)
+
283 #define CAN_BS1_11tq ((uint8_t)0x0A)
+
284 #define CAN_BS1_12tq ((uint8_t)0x0B)
+
285 #define CAN_BS1_13tq ((uint8_t)0x0C)
+
286 #define CAN_BS1_14tq ((uint8_t)0x0D)
+
287 #define CAN_BS1_15tq ((uint8_t)0x0E)
+
288 #define CAN_BS1_16tq ((uint8_t)0x0F)
+
290 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+
291 
+
298 #define CAN_BS2_1tq ((uint8_t)0x00)
+
299 #define CAN_BS2_2tq ((uint8_t)0x01)
+
300 #define CAN_BS2_3tq ((uint8_t)0x02)
+
301 #define CAN_BS2_4tq ((uint8_t)0x03)
+
302 #define CAN_BS2_5tq ((uint8_t)0x04)
+
303 #define CAN_BS2_6tq ((uint8_t)0x05)
+
304 #define CAN_BS2_7tq ((uint8_t)0x06)
+
305 #define CAN_BS2_8tq ((uint8_t)0x07)
+
307 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
308 
+
315 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
316 
+
323 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+
324 
+
331 #define CAN_FilterMode_IdMask ((uint8_t)0x00)
+
332 #define CAN_FilterMode_IdList ((uint8_t)0x01)
+
334 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+
335  ((MODE) == CAN_FilterMode_IdList))
+
336 
+
343 #define CAN_FilterScale_16bit ((uint8_t)0x00)
+
344 #define CAN_FilterScale_32bit ((uint8_t)0x01)
+
346 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+
347  ((SCALE) == CAN_FilterScale_32bit))
+
348 
+
355 #define CAN_Filter_FIFO0 ((uint8_t)0x00)
+
356 #define CAN_Filter_FIFO1 ((uint8_t)0x01)
+
357 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+
358  ((FIFO) == CAN_FilterFIFO1))
+
359 
+
360 /* Legacy defines */
+
361 #define CAN_FilterFIFO0 CAN_Filter_FIFO0
+
362 #define CAN_FilterFIFO1 CAN_Filter_FIFO1
+
363 
+
370 #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+
371 
+
378 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+
379 #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+
380 #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+
381 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
382 
+
389 #define CAN_Id_Standard ((uint32_t)0x00000000)
+
390 #define CAN_Id_Extended ((uint32_t)0x00000004)
+
391 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+
392  ((IDTYPE) == CAN_Id_Extended))
+
393 
+
394 /* Legacy defines */
+
395 #define CAN_ID_STD CAN_Id_Standard
+
396 #define CAN_ID_EXT CAN_Id_Extended
+
397 
+
404 #define CAN_RTR_Data ((uint32_t)0x00000000)
+
405 #define CAN_RTR_Remote ((uint32_t)0x00000002)
+
406 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
407 
+
408 /* Legacy defines */
+
409 #define CAN_RTR_DATA CAN_RTR_Data
+
410 #define CAN_RTR_REMOTE CAN_RTR_Remote
+
411 
+
418 #define CAN_TxStatus_Failed ((uint8_t)0x00)
+
419 #define CAN_TxStatus_Ok ((uint8_t)0x01)
+
420 #define CAN_TxStatus_Pending ((uint8_t)0x02)
+
421 #define CAN_TxStatus_NoMailBox ((uint8_t)0x04)
+
423 /* Legacy defines */
+
424 #define CANTXFAILED CAN_TxStatus_Failed
+
425 #define CANTXOK CAN_TxStatus_Ok
+
426 #define CANTXPENDING CAN_TxStatus_Pending
+
427 #define CAN_NO_MB CAN_TxStatus_NoMailBox
+
428 
+
435 #define CAN_FIFO0 ((uint8_t)0x00)
+
436 #define CAN_FIFO1 ((uint8_t)0x01)
+
438 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
439 
+
446 #define CAN_Sleep_Failed ((uint8_t)0x00)
+
447 #define CAN_Sleep_Ok ((uint8_t)0x01)
+
449 /* Legacy defines */
+
450 #define CANSLEEPFAILED CAN_Sleep_Failed
+
451 #define CANSLEEPOK CAN_Sleep_Ok
+
452 
+
459 #define CAN_WakeUp_Failed ((uint8_t)0x00)
+
460 #define CAN_WakeUp_Ok ((uint8_t)0x01)
+
462 /* Legacy defines */
+
463 #define CANWAKEUPFAILED CAN_WakeUp_Failed
+
464 #define CANWAKEUPOK CAN_WakeUp_Ok
+
465 
+
473 #define CAN_ErrorCode_NoErr ((uint8_t)0x00)
+
474 #define CAN_ErrorCode_StuffErr ((uint8_t)0x10)
+
475 #define CAN_ErrorCode_FormErr ((uint8_t)0x20)
+
476 #define CAN_ErrorCode_ACKErr ((uint8_t)0x30)
+
477 #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40)
+
478 #define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50)
+
479 #define CAN_ErrorCode_CRCErr ((uint8_t)0x60)
+
480 #define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70)
+
488 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+
489  and CAN_ClearFlag() functions. */
+
490 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
+
491  CAN_GetFlagStatus() function. */
+
492 
+
493 /* Transmit Flags */
+
494 #define CAN_FLAG_RQCP0 ((uint32_t)0x38000001)
+
495 #define CAN_FLAG_RQCP1 ((uint32_t)0x38000100)
+
496 #define CAN_FLAG_RQCP2 ((uint32_t)0x38010000)
+
498 /* Receive Flags */
+
499 #define CAN_FLAG_FMP0 ((uint32_t)0x12000003)
+
500 #define CAN_FLAG_FF0 ((uint32_t)0x32000008)
+
501 #define CAN_FLAG_FOV0 ((uint32_t)0x32000010)
+
502 #define CAN_FLAG_FMP1 ((uint32_t)0x14000003)
+
503 #define CAN_FLAG_FF1 ((uint32_t)0x34000008)
+
504 #define CAN_FLAG_FOV1 ((uint32_t)0x34000010)
+
506 /* Operating Mode Flags */
+
507 #define CAN_FLAG_WKU ((uint32_t)0x31000008)
+
508 #define CAN_FLAG_SLAK ((uint32_t)0x31000012)
+
509 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+
510  In this case the SLAK bit can be polled.*/
+
511 
+
512 /* Error Flags */
+
513 #define CAN_FLAG_EWG ((uint32_t)0x10F00001)
+
514 #define CAN_FLAG_EPV ((uint32_t)0x10F00002)
+
515 #define CAN_FLAG_BOF ((uint32_t)0x10F00004)
+
516 #define CAN_FLAG_LEC ((uint32_t)0x30F00070)
+
518 #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+
519  ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+
520  ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+
521  ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+
522  ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+
523  ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+
524  ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+
525  ((FLAG) == CAN_FLAG_SLAK ))
+
526 
+
527 #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+
528  ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+
529  ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+
530  ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+
531  ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+
532 
+
540 #define CAN_IT_TME ((uint32_t)0x00000001)
+
542 /* Receive Interrupts */
+
543 #define CAN_IT_FMP0 ((uint32_t)0x00000002)
+
544 #define CAN_IT_FF0 ((uint32_t)0x00000004)
+
545 #define CAN_IT_FOV0 ((uint32_t)0x00000008)
+
546 #define CAN_IT_FMP1 ((uint32_t)0x00000010)
+
547 #define CAN_IT_FF1 ((uint32_t)0x00000020)
+
548 #define CAN_IT_FOV1 ((uint32_t)0x00000040)
+
550 /* Operating Mode Interrupts */
+
551 #define CAN_IT_WKU ((uint32_t)0x00010000)
+
552 #define CAN_IT_SLK ((uint32_t)0x00020000)
+
554 /* Error Interrupts */
+
555 #define CAN_IT_EWG ((uint32_t)0x00000100)
+
556 #define CAN_IT_EPV ((uint32_t)0x00000200)
+
557 #define CAN_IT_BOF ((uint32_t)0x00000400)
+
558 #define CAN_IT_LEC ((uint32_t)0x00000800)
+
559 #define CAN_IT_ERR ((uint32_t)0x00008000)
+
561 /* Flags named as Interrupts : kept only for FW compatibility */
+
562 #define CAN_IT_RQCP0 CAN_IT_TME
+
563 #define CAN_IT_RQCP1 CAN_IT_TME
+
564 #define CAN_IT_RQCP2 CAN_IT_TME
+
565 
+
566 
+
567 #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+
568  ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+
569  ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+
570  ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+
571  ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+
572  ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+
573  ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
574 
+
575 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+
576  ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+
577  ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+
578  ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+
579  ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+
580  ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
581 
+
589 /* Exported macro ------------------------------------------------------------*/
+
590 /* Exported functions --------------------------------------------------------*/
+
591 
+
592 /* Function used to set the CAN configuration to the default reset state *****/
+
593 void CAN_DeInit(CAN_TypeDef* CANx);
+
594 
+
595 /* Initialization and Configuration functions *********************************/
+
596 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+
597 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+
598 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+
599 void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+
600 void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+
601 void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
602 
+
603 /* CAN Frames Transmission functions ******************************************/
+
604 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+
605 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+
606 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
607 
+
608 /* CAN Frames Reception functions *********************************************/
+
609 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+
610 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
611 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
612 
+
613 /* Operation modes functions **************************************************/
+
614 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+
615 uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+
616 uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
617 
+
618 /* CAN Bus Error management functions *****************************************/
+
619 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+
620 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+
621 uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
622 
+
623 /* Interrupts and flags management functions **********************************/
+
624 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+
625 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+
626 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+
627 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
628 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
629 
+
630 #ifdef __cplusplus
+
631 }
+
632 #endif
+
633 
+
634 #endif /* __STM32F4xx_CAN_H */
+
635 
+
644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
CAN_FIFORelease
void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber)
Releases the specified receive FIFO.
Definition: stm32f4xx_can.c:798
+
CAN_FilterInit
void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct...
Definition: stm32f4xx_can.c:333
+
CAN_WakeUp
uint8_t CAN_WakeUp(CAN_TypeDef *CANx)
Wakes up the CAN peripheral from sleep mode .
Definition: stm32f4xx_can.c:977
+
CAN_FilterInitTypeDef::CAN_FilterIdHigh
uint16_t CAN_FilterIdHigh
Definition: stm32f4xx_can.h:100
+
CAN_GetReceiveErrorCounter
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx)
Returns the CANx Receive Error Counter (REC).
Definition: stm32f4xx_can.c:1064
+
CAN_GetITStatus
ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT)
Checks whether the specified CANx interrupt has occurred or not.
Definition: stm32f4xx_can.c:1489
+
CAN_TransmitStatus
uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox)
Checks the transmission status of a CAN Frame.
Definition: stm32f4xx_can.c:648
+
CAN_FilterInitTypeDef::CAN_FilterMode
uint8_t CAN_FilterMode
Definition: stm32f4xx_can.h:123
+
CAN_ITConfig
void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
Enables or disables the specified CANx interrupts.
Definition: stm32f4xx_can.c:1289
+
CanTxMsg::RTR
uint8_t RTR
Definition: stm32f4xx_can.h:148
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
CAN_Receive
void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
Receives a correct CAN frame.
Definition: stm32f4xx_can.c:749
+
CanRxMsg::IDE
uint8_t IDE
Definition: stm32f4xx_can.h:171
+
CAN_FilterInitTypeDef::CAN_FilterIdLow
uint16_t CAN_FilterIdLow
Definition: stm32f4xx_can.h:104
+
CAN_CancelTransmit
void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox)
Cancels a transmit request.
Definition: stm32f4xx_can.c:702
+
CanTxMsg
CAN Tx message structure definition.
Definition: stm32f4xx_can.h:136
+
CanRxMsg::RTR
uint8_t RTR
Definition: stm32f4xx_can.h:175
+
CAN_InitTypeDef::CAN_BS2
uint8_t CAN_BS2
Definition: stm32f4xx_can.h:73
+
CAN_FilterInitTypeDef::CAN_FilterScale
uint8_t CAN_FilterScale
Definition: stm32f4xx_can.h:126
+
CAN_ClearFlag
void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Clears the CAN's pending flags.
Definition: stm32f4xx_can.c:1429
+
CAN_OperatingModeRequest
uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
Selects the CAN Operation mode.
Definition: stm32f4xx_can.c:871
+
CAN_Init
uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
Definition: stm32f4xx_can.c:196
+
CAN_TypeDef
Controller Area Network.
Definition: stm32f4xx.h:602
+
CanRxMsg
CAN Rx message structure definition.
Definition: stm32f4xx_can.h:163
+
CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment
uint16_t CAN_FilterFIFOAssignment
Definition: stm32f4xx_can.h:118
+
CAN_InitTypeDef::CAN_SJW
uint8_t CAN_SJW
Definition: stm32f4xx_can.h:64
+
CAN_InitTypeDef
CAN init structure definition.
Definition: stm32f4xx_can.h:56
+
CAN_FilterInitTypeDef
CAN filter init structure definition.
Definition: stm32f4xx_can.h:98
+
CAN_InitTypeDef::CAN_Prescaler
uint16_t CAN_Prescaler
Definition: stm32f4xx_can.h:58
+
CanRxMsg::ExtId
uint32_t ExtId
Definition: stm32f4xx_can.h:168
+
CAN_InitTypeDef::CAN_TXFP
FunctionalState CAN_TXFP
Definition: stm32f4xx_can.h:91
+
CAN_ClearITPendingBit
void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT)
Clears the CANx's interrupt pending bits.
Definition: stm32f4xx_can.c:1593
+
CAN_DeInit
void CAN_DeInit(CAN_TypeDef *CANx)
Deinitializes the CAN peripheral registers to their default reset values.
Definition: stm32f4xx_can.c:166
+
CAN_MessagePending
uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber)
Returns the number of pending received messages.
Definition: stm32f4xx_can.c:821
+
CAN_FilterInitTypeDef::CAN_FilterActivation
FunctionalState CAN_FilterActivation
Definition: stm32f4xx_can.h:129
+
CanRxMsg::FMI
uint8_t FMI
Definition: stm32f4xx_can.h:185
+
CAN_InitTypeDef::CAN_Mode
uint8_t CAN_Mode
Definition: stm32f4xx_can.h:61
+
CAN_FilterInitTypeDef::CAN_FilterNumber
uint8_t CAN_FilterNumber
Definition: stm32f4xx_can.h:121
+
CAN_FilterInitTypeDef::CAN_FilterMaskIdLow
uint16_t CAN_FilterMaskIdLow
Definition: stm32f4xx_can.h:113
+
CanTxMsg::DLC
uint8_t DLC
Definition: stm32f4xx_can.h:152
+
CAN_GetLSBTransmitErrorCounter
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx)
Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
Definition: stm32f4xx_can.c:1084
+
CAN_TTComModeCmd
void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the CAN Time TriggerOperation communication mode.
Definition: stm32f4xx_can.c:522
+
CAN_InitTypeDef::CAN_ABOM
FunctionalState CAN_ABOM
Definition: stm32f4xx_can.h:79
+
CAN_Transmit
uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage)
Initiates and transmits a CAN frame message.
Definition: stm32f4xx_can.c:576
+
CAN_GetFlagStatus
FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
Checks whether the specified CAN flag is set or not.
Definition: stm32f4xx_can.c:1329
+
CAN_InitTypeDef::CAN_RFLM
FunctionalState CAN_RFLM
Definition: stm32f4xx_can.h:88
+
CAN_Sleep
uint8_t CAN_Sleep(CAN_TypeDef *CANx)
Enters the Sleep (low power) mode.
Definition: stm32f4xx_can.c:952
+
CanTxMsg::IDE
uint8_t IDE
Definition: stm32f4xx_can.h:144
+
CAN_SlaveStartBank
void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
Select the start bank filter for slave CAN.
Definition: stm32f4xx_can.c:467
+
CAN_InitTypeDef::CAN_TTCM
FunctionalState CAN_TTCM
Definition: stm32f4xx_can.h:76
+
CanRxMsg::StdId
uint32_t StdId
Definition: stm32f4xx_can.h:165
+
CAN_InitTypeDef::CAN_BS1
uint8_t CAN_BS1
Definition: stm32f4xx_can.h:69
+
CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh
uint16_t CAN_FilterMaskIdHigh
Definition: stm32f4xx_can.h:108
+
CAN_DBGFreeze
void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState)
Enables or disables the DBG Freeze for CAN.
Definition: stm32f4xx_can.c:492
+
CAN_StructInit
void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct)
Fills each CAN_InitStruct member with its default value.
Definition: stm32f4xx_can.c:424
+
CAN_GetLastErrorCode
uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx)
Returns the CANx's last error code (LEC).
Definition: stm32f4xx_can.c:1039
+
CanTxMsg::StdId
uint32_t StdId
Definition: stm32f4xx_can.h:138
+
CanRxMsg::DLC
uint8_t DLC
Definition: stm32f4xx_can.h:179
+
CAN_InitTypeDef::CAN_NART
FunctionalState CAN_NART
Definition: stm32f4xx_can.h:85
+
CanTxMsg::ExtId
uint32_t ExtId
Definition: stm32f4xx_can.h:141
+
CAN_InitTypeDef::CAN_AWUM
FunctionalState CAN_AWUM
Definition: stm32f4xx_can.h:82
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__conf_8h_source.html b/stm32f4xx__conf_8h_source.html new file mode 100644 index 0000000..d64918d --- /dev/null +++ b/stm32f4xx__conf_8h_source.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_conf.h Source File + + + + + + + + + + +
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+
stm32f4xx_conf.h
+
+
+
1 
+
28 /* Define to prevent recursive inclusion -------------------------------------*/
+
29 #ifndef __STM32F4xx_CONF_H
+
30 #define __STM32F4xx_CONF_H
+
31 
+
32 /* Includes ------------------------------------------------------------------*/
+
33 /* Uncomment the line below to enable peripheral header file inclusion */
+
34 #include "stm32f4xx_adc.h"
+
35 #include "stm32f4xx_crc.h"
+
36 #include "stm32f4xx_dbgmcu.h"
+
37 #include "stm32f4xx_dma.h"
+
38 #include "stm32f4xx_exti.h"
+
39 #include "stm32f4xx_flash.h"
+
40 #include "stm32f4xx_gpio.h"
+
41 #include "stm32f4xx_i2c.h"
+
42 #include "stm32f4xx_iwdg.h"
+
43 #include "stm32f4xx_pwr.h"
+
44 #include "stm32f4xx_rcc.h"
+
45 #include "stm32f4xx_rtc.h"
+
46 #include "stm32f4xx_sdio.h"
+
47 #include "stm32f4xx_spi.h"
+
48 #include "stm32f4xx_syscfg.h"
+
49 #include "stm32f4xx_tim.h"
+
50 #include "stm32f4xx_usart.h"
+
51 #include "stm32f4xx_wwdg.h"
+
52 #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
53 
+
54 #if defined (STM32F429_439xx)
+
55 #include "stm32f4xx_cryp.h"
+
56 #include "stm32f4xx_hash.h"
+
57 #include "stm32f4xx_rng.h"
+
58 #include "stm32f4xx_can.h"
+
59 #include "stm32f4xx_dac.h"
+
60 #include "stm32f4xx_dcmi.h"
+
61 #include "stm32f4xx_dma2d.h"
+
62 #include "stm32f4xx_fmc.h"
+
63 #include "stm32f4xx_ltdc.h"
+
64 #include "stm32f4xx_sai.h"
+
65 #endif /* STM32F429_439xx */
+
66 
+
67 #if defined (STM32F427_437xx)
+
68 #include "stm32f4xx_cryp.h"
+
69 #include "stm32f4xx_hash.h"
+
70 #include "stm32f4xx_rng.h"
+
71 #include "stm32f4xx_can.h"
+
72 #include "stm32f4xx_dac.h"
+
73 #include "stm32f4xx_dcmi.h"
+
74 #include "stm32f4xx_dma2d.h"
+
75 #include "stm32f4xx_fmc.h"
+
76 #include "stm32f4xx_sai.h"
+
77 #endif /* STM32F427_437xx */
+
78 
+
79 #if defined (STM32F40_41xxx)
+
80 #include "stm32f4xx_cryp.h"
+
81 #include "stm32f4xx_hash.h"
+
82 #include "stm32f4xx_rng.h"
+
83 #include "stm32f4xx_can.h"
+
84 #include "stm32f4xx_dac.h"
+
85 #include "stm32f4xx_dcmi.h"
+
86 #include "stm32f4xx_fsmc.h"
+
87 #endif /* STM32F40_41xxx */
+
88 
+
89 #if defined (STM32F411xE)
+
90 #include "stm32f4xx_flash_ramfunc.h"
+
91 #endif /* STM32F411xE */
+
92 /* Exported types ------------------------------------------------------------*/
+
93 /* Exported constants --------------------------------------------------------*/
+
94 
+
95 /* If an external clock source is used, then the value of the following define
+
96  should be set to the value of the external clock source, else, if no external
+
97  clock is used, keep this define commented */
+
98 /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
+
99 
+
100 
+
101 /* Uncomment the line below to expanse the "assert_param" macro in the
+
102  Standard Peripheral Library drivers code */
+
103 /* #define USE_FULL_ASSERT 1 */
+
104 
+
105 /* Exported macro ------------------------------------------------------------*/
+
106 #ifdef USE_FULL_ASSERT
+
107 
+
116  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+
117 /* Exported functions ------------------------------------------------------- */
+
118  void assert_failed(uint8_t* file, uint32_t line);
+
119 #else
+
120  #define assert_param(expr) ((void)0)
+
121 #endif /* USE_FULL_ASSERT */
+
122 
+
123 #endif /* __STM32F4xx_CONF_H */
+
124 
+
125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
stm32f4xx_rcc.h
This file contains all the functions prototypes for the RCC firmware library.
+
stm32f4xx_gpio.h
This file contains all the functions prototypes for the GPIO firmware library.
+
stm32f4xx_flash_ramfunc.h
Header file of FLASH RAMFUNC driver.
+
stm32f4xx_dbgmcu.h
This file contains all the functions prototypes for the DBGMCU firmware library.
+
stm32f4xx_dma2d.h
This file contains all the functions prototypes for the DMA2D firmware library.
+
misc.h
This file contains all the functions prototypes for the miscellaneous firmware library functions (add...
+
stm32f4xx_sai.h
This file contains all the functions prototypes for the SAI firmware library.
+
stm32f4xx_crc.h
This file contains all the functions prototypes for the CRC firmware library.
+
stm32f4xx_spi.h
This file contains all the functions prototypes for the SPI firmware library.
+
stm32f4xx_tim.h
This file contains all the functions prototypes for the TIM firmware library.
+
stm32f4xx_rtc.h
This file contains all the functions prototypes for the RTC firmware library.
+
stm32f4xx_ltdc.h
This file contains all the functions prototypes for the LTDC firmware library.
+
stm32f4xx_pwr.h
This file contains all the functions prototypes for the PWR firmware library.
+
stm32f4xx_flash.h
This file contains all the functions prototypes for the FLASH firmware library.
+
stm32f4xx_adc.h
This file contains all the functions prototypes for the ADC firmware library.
+
stm32f4xx_syscfg.h
This file contains all the functions prototypes for the SYSCFG firmware library.
+
stm32f4xx_dac.h
This file contains all the functions prototypes for the DAC firmware library.
+
stm32f4xx_can.h
This file contains all the functions prototypes for the CAN firmware library.
+
stm32f4xx_hash.h
This file contains all the functions prototypes for the HASH firmware library.
+
stm32f4xx_i2c.h
This file contains all the functions prototypes for the I2C firmware library.
+
stm32f4xx_dma.h
This file contains all the functions prototypes for the DMA firmware library.
+
stm32f4xx_usart.h
This file contains all the functions prototypes for the USART firmware library.
+
stm32f4xx_rng.h
This file contains all the functions prototypes for the Random Number Generator(RNG) firmware library...
+
stm32f4xx_wwdg.h
This file contains all the functions prototypes for the WWDG firmware library.
+
stm32f4xx_sdio.h
This file contains all the functions prototypes for the SDIO firmware library.
+
stm32f4xx_fsmc.h
This file contains all the functions prototypes for the FSMC firmware library.
+
stm32f4xx_dcmi.h
This file contains all the functions prototypes for the DCMI firmware library.
+
stm32f4xx_iwdg.h
This file contains all the functions prototypes for the IWDG firmware library.
+
stm32f4xx_cryp.h
This file contains all the functions prototypes for the Cryptographic processor(CRYP) firmware librar...
+
stm32f4xx_exti.h
This file contains all the functions prototypes for the EXTI firmware library.
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__crc_8c.html b/stm32f4xx__crc_8c.html new file mode 100644 index 0000000..12f4b7f --- /dev/null +++ b/stm32f4xx__crc_8c.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_crc.c File Reference + + + + + + + + + + +
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+Functions
+
+
stm32f4xx_crc.c File Reference
+
+
+ +

This file provides all the CRC firmware functions. +More...

+
#include "stm32f4xx_crc.h"
+
+Include dependency graph for stm32f4xx_crc.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +

+Functions

void CRC_ResetDR (void)
 Resets the CRC Data register (DR). More...
 
uint32_t CRC_CalcCRC (uint32_t Data)
 Computes the 32-bit CRC of a given data word(32-bit). More...
 
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
 Computes the 32-bit CRC of a given buffer of data word(32-bit). More...
 
uint32_t CRC_GetCRC (void)
 Returns the current CRC value. More...
 
void CRC_SetIDRegister (uint8_t IDValue)
 Stores a 8-bit data in the Independent Data(ID) register. More...
 
uint8_t CRC_GetIDRegister (void)
 Returns the 8-bit data stored in the Independent Data(ID) register. More...
 
+

Detailed Description

+

This file provides all the CRC firmware functions.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__crc_8c__incl.map b/stm32f4xx__crc_8c__incl.map new file mode 100644 index 0000000..3ef9ff6 --- /dev/null +++ b/stm32f4xx__crc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__crc_8c__incl.md5 b/stm32f4xx__crc_8c__incl.md5 new file mode 100644 index 0000000..7061bcb --- /dev/null +++ b/stm32f4xx__crc_8c__incl.md5 @@ -0,0 +1 @@ +b040f0121f8022af9bf0382a1488523a \ No newline at end of file diff --git a/stm32f4xx__crc_8c__incl.png b/stm32f4xx__crc_8c__incl.png new file mode 100644 index 0000000..e3f22bb Binary files /dev/null and b/stm32f4xx__crc_8c__incl.png differ diff --git a/stm32f4xx__crc_8h.html b/stm32f4xx__crc_8h.html new file mode 100644 index 0000000..bc99bd5 --- /dev/null +++ b/stm32f4xx__crc_8h.html @@ -0,0 +1,154 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_crc.h File Reference + + + + + + + + + + +
+
+ + + + + + +
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+Functions
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+
stm32f4xx_crc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the CRC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_crc.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Functions

void CRC_ResetDR (void)
 Resets the CRC Data register (DR). More...
 
uint32_t CRC_CalcCRC (uint32_t Data)
 Computes the 32-bit CRC of a given data word(32-bit). More...
 
uint32_t CRC_CalcBlockCRC (uint32_t pBuffer[], uint32_t BufferLength)
 Computes the 32-bit CRC of a given buffer of data word(32-bit). More...
 
uint32_t CRC_GetCRC (void)
 Returns the current CRC value. More...
 
void CRC_SetIDRegister (uint8_t IDValue)
 Stores a 8-bit data in the Independent Data(ID) register. More...
 
uint8_t CRC_GetIDRegister (void)
 Returns the 8-bit data stored in the Independent Data(ID) register. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the CRC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__crc_8h__dep__incl.map b/stm32f4xx__crc_8h__dep__incl.map new file mode 100644 index 0000000..4ff2fc5 --- /dev/null +++ b/stm32f4xx__crc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__crc_8h__dep__incl.md5 b/stm32f4xx__crc_8h__dep__incl.md5 new file mode 100644 index 0000000..ae36eb4 --- /dev/null +++ b/stm32f4xx__crc_8h__dep__incl.md5 @@ -0,0 +1 @@ +1e92c889397f8de9a1db9b65ab62a58b \ No newline at end of file diff --git a/stm32f4xx__crc_8h__dep__incl.png b/stm32f4xx__crc_8h__dep__incl.png new file mode 100644 index 0000000..ee2f375 Binary files /dev/null and b/stm32f4xx__crc_8h__dep__incl.png differ diff --git a/stm32f4xx__crc_8h__incl.map b/stm32f4xx__crc_8h__incl.map new file mode 100644 index 0000000..0c4cdfc --- /dev/null +++ b/stm32f4xx__crc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__crc_8h__incl.md5 b/stm32f4xx__crc_8h__incl.md5 new file mode 100644 index 0000000..d69da42 --- /dev/null +++ b/stm32f4xx__crc_8h__incl.md5 @@ -0,0 +1 @@ +a6e5b543e5b42cc0baa6e08bdff24753 \ No newline at end of file diff --git a/stm32f4xx__crc_8h__incl.png b/stm32f4xx__crc_8h__incl.png new file mode 100644 index 0000000..e491b97 Binary files /dev/null and b/stm32f4xx__crc_8h__incl.png differ diff --git a/stm32f4xx__crc_8h_source.html b/stm32f4xx__crc_8h_source.html new file mode 100644 index 0000000..1be88a6 --- /dev/null +++ b/stm32f4xx__crc_8h_source.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_crc.h Source File + + + + + + + + + + +
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stm32f4xx_crc.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_CRC_H
+
31 #define __STM32F4xx_CRC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
59 /* Exported macro ------------------------------------------------------------*/
+
60 /* Exported functions --------------------------------------------------------*/
+
61 
+
62 void CRC_ResetDR(void);
+
63 uint32_t CRC_CalcCRC(uint32_t Data);
+
64 uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+
65 uint32_t CRC_GetCRC(void);
+
66 void CRC_SetIDRegister(uint8_t IDValue);
+
67 uint8_t CRC_GetIDRegister(void);
+
68 
+
69 #ifdef __cplusplus
+
70 }
+
71 #endif
+
72 
+
73 #endif /* __STM32F4xx_CRC_H */
+
74 
+
83 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
CRC_CalcBlockCRC
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of a given buffer of data word(32-bit).
Definition: stm32f4xx_crc.c:80
+
CRC_CalcCRC
uint32_t CRC_CalcCRC(uint32_t Data)
Computes the 32-bit CRC of a given data word(32-bit).
Definition: stm32f4xx_crc.c:67
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
CRC_GetIDRegister
uint8_t CRC_GetIDRegister(void)
Returns the 8-bit data stored in the Independent Data(ID) register.
Definition: stm32f4xx_crc.c:116
+
CRC_SetIDRegister
void CRC_SetIDRegister(uint8_t IDValue)
Stores a 8-bit data in the Independent Data(ID) register.
Definition: stm32f4xx_crc.c:106
+
CRC_GetCRC
uint32_t CRC_GetCRC(void)
Returns the current CRC value.
Definition: stm32f4xx_crc.c:96
+
CRC_ResetDR
void CRC_ResetDR(void)
Resets the CRC Data register (DR).
Definition: stm32f4xx_crc.c:56
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp_8c.html b/stm32f4xx__cryp_8c.html new file mode 100644 index 0000000..4fe6d9f --- /dev/null +++ b/stm32f4xx__cryp_8c.html @@ -0,0 +1,335 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_cryp.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_cryp.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Cryptographic processor (CRYP) peripheral: +More...

+
#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_cryp.c:
+
+
+ + +
+
+ + + + + +

+Macros

+#define FLAG_MASK   ((uint8_t)0x20)
 
+#define MAX_TIMEOUT   ((uint16_t)0xFFFF)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CRYP_DeInit (void)
 Deinitializes the CRYP peripheral registers to their default reset values. More...
 
void CRYP_Init (CRYP_InitTypeDef *CRYP_InitStruct)
 Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct. More...
 
void CRYP_StructInit (CRYP_InitTypeDef *CRYP_InitStruct)
 Fills each CRYP_InitStruct member with its default value. More...
 
void CRYP_KeyInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct. More...
 
void CRYP_KeyStructInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Fills each CRYP_KeyInitStruct member with its default value. More...
 
void CRYP_IVInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct. More...
 
void CRYP_IVStructInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Fills each CRYP_IVInitStruct member with its default value. More...
 
void CRYP_PhaseConfig (uint32_t CRYP_Phase)
 Configures the AES-CCM and AES-GCM phases. More...
 
void CRYP_FIFOFlush (void)
 Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset) More...
 
void CRYP_Cmd (FunctionalState NewState)
 Enables or disables the CRYP peripheral. More...
 
void CRYP_DataIn (uint32_t Data)
 Writes data in the Data Input register (DIN). More...
 
uint32_t CRYP_DataOut (void)
 Returns the last data entered into the output FIFO. More...
 
ErrorStatus CRYP_SaveContext (CRYP_Context *CRYP_ContextSave, CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Saves the CRYP peripheral Context. More...
 
void CRYP_RestoreContext (CRYP_Context *CRYP_ContextRestore)
 Restores the CRYP peripheral Context. More...
 
void CRYP_DMACmd (uint8_t CRYP_DMAReq, FunctionalState NewState)
 Enables or disables the CRYP DMA interface. More...
 
void CRYP_ITConfig (uint8_t CRYP_IT, FunctionalState NewState)
 Enables or disables the specified CRYP interrupts. More...
 
ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
 Checks whether the specified CRYP interrupt has occurred or not. More...
 
FunctionalState CRYP_GetCmdStatus (void)
 Returns whether CRYP peripheral is enabled or disabled. More...
 
FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
 Checks whether the specified CRYP flag is set or not. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Cryptographic processor (CRYP) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration functions
    • +
  • Data treatment functions
    • +
  • Context swapping functions
    • +
  • DMA interface function
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================      
+                 ##### How to use this driver #####
+ =================================================================== 
+ [..]
+   (#) Enable the CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed 
+       CRYP_IVInit(). 
+  
+   (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
+  
+   (#) Enable the CRYP controller using the CRYP_Cmd() function. 
+  
+   (#) If using DMA for Data input and output transfer, activate the needed DMA 
+       Requests using CRYP_DMACmd() function 
+  
+   (#) If DMA is not used for data transfer, use CRYP_DataIn() and  CRYP_DataOut() 
+       functions to enter data to IN FIFO and get result from OUT FIFO.
+  
+   (#) To control CRYP events you can use one of the following two methods:
+       (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.  
+       (++) Use CRYP interrupts through the function CRYP_ITConfig() at 
+            initialization phase and CRYP_GetITStatus() function into interrupt 
+            routines in processing phase.
+         
+   (#) Save and restore Cryptographic processor context using CRYP_SaveContext() 
+       and CRYP_RestoreContext() functions.     
+  
+  
+ *** Procedure to perform an encryption or a decryption ***
+ ========================================================== 
+  
+ *** Initialization ***
+ ====================== 
+ [..] 
+   (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit 
+       functions:
+       (++) Configure the key size (128-, 192- or 256-bit, in the AES only) 
+       (++) Enter the symmetric key 
+       (++) Configure the data type
+       (++) In case of decryption in AES-ECB or AES-CBC, you must prepare 
+            the key: configure the key preparation mode. Then Enable the CRYP 
+            peripheral using CRYP_Cmd() function: the BUSY flag is set. 
+            Wait until BUSY flag is reset : the key is prepared for decryption
+       (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the 
+            AES in ECB/CBC/CTR) 
+       (++) Configure the direction (encryption/decryption).
+       (++) Write the initialization vectors (in CBC or CTR modes only)
+  
+   (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
+  
+  
+  *** Basic Processing mode (polling mode) *** 
+  ============================================  
+  [..]
+    (#) Enable the cryptographic processor using CRYP_Cmd() function.
+  
+    (#) Write the first blocks in the input FIFO (2 to 8 words) using 
+        CRYP_DataIn() function.
+  
+    (#) Repeat the following sequence until the complete message has been 
+        processed:
+  
+        (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() 
+            function), then read the OUT-FIFO using CRYP_DataOut() function
+            (1 block or until the FIFO is empty)
+  
+         (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() 
+            function then write the IN FIFO using CRYP_DataIn() function 
+            (1 block or until the FIFO is full)
+  
+    (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and 
+          both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is 
+          reset). You can disable the peripheral using CRYP_Cmd() function.
+  
+ *** Interrupts Processing mode *** 
+ ==================================
+ [..] In this mode, Processing is done when the data are transferred by the 
+      CPU during interrupts.
+  
+    (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
+        function.
+  
+    (#) Enable the cryptographic processor using CRYP_Cmd() function.
+  
+    (#) In the CRYP_IT_INI interrupt handler : load the input message into the 
+         IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a 
+         time, or load data until the IN FIFO is full. When the last word of
+         the message has been entered into the IN FIFO, disable the CRYP_IT_INI 
+         interrupt (using CRYP_ITConfig() function).
+  
+    (#) In the CRYP_IT_OUTI interrupt handler : read the output message from 
+         the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 
+         4 words) at a time or read data until the FIFO is empty.
+         When the last word has been read, INIM=0, BUSY=0 and both FIFOs are 
+         empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). 
+         You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() 
+         function) and you can disable the peripheral using CRYP_Cmd() function.
+  
+ *** DMA Processing mode *** 
+ ===========================
+ [..] In this mode, Processing is done when the DMA is used to transfer the 
+      data from/to the memory.
+  
+    (#) Configure the DMA controller to transfer the input data from the 
+         memory using DMA_Init() function. 
+         The transfer length is the length of the message. 
+         As message padding is not managed by the peripheral, the message 
+         length must be an entire number of blocks. The data are transferred 
+         in burst mode. The burst length is 4 words in the AES and 2 or 4 
+         words in the DES/TDES. The DMA should be configured to set an 
+         interrupt on transfer completion of the output data to indicate that 
+         the processing is finished. 
+         Refer to DMA peripheral driver for more details.  
+  
+     (#) Enable the cryptographic processor using CRYP_Cmd() function. 
+         Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT 
+         using CRYP_DMACmd() function.
+  
+     (#) All the transfers and processing are managed by the DMA and the 
+         cryptographic processor. The DMA transfer complete interrupt indicates 
+         that the processing is complete. Both FIFOs are normally empty and 
+         CRYP_FLAG_BUSY flag is reset.
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp_8c__incl.map b/stm32f4xx__cryp_8c__incl.map new file mode 100644 index 0000000..c48c83b --- /dev/null +++ b/stm32f4xx__cryp_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp_8c__incl.md5 b/stm32f4xx__cryp_8c__incl.md5 new file mode 100644 index 0000000..746fcc7 --- /dev/null +++ b/stm32f4xx__cryp_8c__incl.md5 @@ -0,0 +1 @@ +180b5ae233c3647afec3bc57bdddb007 \ No newline at end of file diff --git a/stm32f4xx__cryp_8c__incl.png b/stm32f4xx__cryp_8c__incl.png new file mode 100644 index 0000000..295bfbc Binary files /dev/null and b/stm32f4xx__cryp_8c__incl.png differ diff --git a/stm32f4xx__cryp_8h.html b/stm32f4xx__cryp_8h.html new file mode 100644 index 0000000..7880374 --- /dev/null +++ b/stm32f4xx__cryp_8h.html @@ -0,0 +1,356 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_cryp.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_cryp.h File Reference
+
+
+ +

This file contains all the functions prototypes for the Cryptographic processor(CRYP) firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_cryp.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Classes

struct  CRYP_InitTypeDef
 CRYP Init structure definition. More...
 
struct  CRYP_KeyInitTypeDef
 CRYP Key(s) structure definition. More...
 
struct  CRYP_IVInitTypeDef
 CRYP Initialization Vectors (IV) structure definition. More...
 
struct  CRYP_Context
 CRYP context swapping structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define CRYP_AlgoDir_Encrypt   ((uint16_t)0x0000)
 
+#define CRYP_AlgoDir_Decrypt   ((uint16_t)0x0004)
 
#define IS_CRYP_ALGODIR(ALGODIR)
 
#define CRYP_AlgoMode_TDES_ECB   ((uint32_t)0x00000000)
 
#define CRYP_AlgoMode_TDES_CBC   ((uint32_t)0x00000008)
 
+#define CRYP_AlgoMode_DES_ECB   ((uint32_t)0x00000010)
 
#define CRYP_AlgoMode_DES_CBC   ((uint32_t)0x00000018)
 
+#define CRYP_AlgoMode_AES_ECB   ((uint32_t)0x00000020)
 
+#define CRYP_AlgoMode_AES_CBC   ((uint32_t)0x00000028)
 
+#define CRYP_AlgoMode_AES_CTR   ((uint32_t)0x00000030)
 
+#define CRYP_AlgoMode_AES_Key   ((uint32_t)0x00000038)
 
+#define CRYP_AlgoMode_AES_GCM   ((uint32_t)0x00080000)
 
+#define CRYP_AlgoMode_AES_CCM   ((uint32_t)0x00080008)
 
#define IS_CRYP_ALGOMODE(ALGOMODE)
 
#define CRYP_Phase_Init   ((uint32_t)0x00000000)
 
+#define CRYP_Phase_Header   CRYP_CR_GCM_CCMPH_0
 
+#define CRYP_Phase_Payload   CRYP_CR_GCM_CCMPH_1
 
+#define CRYP_Phase_Final   CRYP_CR_GCM_CCMPH
 
#define IS_CRYP_PHASE(PHASE)
 
+#define CRYP_DataType_32b   ((uint16_t)0x0000)
 
+#define CRYP_DataType_16b   ((uint16_t)0x0040)
 
+#define CRYP_DataType_8b   ((uint16_t)0x0080)
 
+#define CRYP_DataType_1b   ((uint16_t)0x00C0)
 
#define IS_CRYP_DATATYPE(DATATYPE)
 
+#define CRYP_KeySize_128b   ((uint16_t)0x0000)
 
+#define CRYP_KeySize_192b   ((uint16_t)0x0100)
 
+#define CRYP_KeySize_256b   ((uint16_t)0x0200)
 
#define IS_CRYP_KEYSIZE(KEYSIZE)
 
#define CRYP_FLAG_BUSY   ((uint8_t)0x10)
 
#define CRYP_FLAG_IFEM   ((uint8_t)0x01)
 
#define CRYP_FLAG_IFNF   ((uint8_t)0x02)
 
#define CRYP_FLAG_INRIS   ((uint8_t)0x22)
 
#define CRYP_FLAG_OFNE   ((uint8_t)0x04)
 
#define CRYP_FLAG_OFFU   ((uint8_t)0x08)
 
#define CRYP_FLAG_OUTRIS   ((uint8_t)0x21)
 
#define IS_CRYP_GET_FLAG(FLAG)
 
#define CRYP_IT_INI   ((uint8_t)0x01)
 
#define CRYP_IT_OUTI   ((uint8_t)0x02)
 
+#define IS_CRYP_CONFIG_IT(IT)   ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
 
+#define IS_CRYP_GET_IT(IT)   (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
 
+#define MODE_ENCRYPT   ((uint8_t)0x01)
 
+#define MODE_DECRYPT   ((uint8_t)0x00)
 
+#define CRYP_DMAReq_DataIN   ((uint8_t)0x01)
 
+#define CRYP_DMAReq_DataOUT   ((uint8_t)0x02)
 
+#define IS_CRYP_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void CRYP_DeInit (void)
 Deinitializes the CRYP peripheral registers to their default reset values. More...
 
void CRYP_Init (CRYP_InitTypeDef *CRYP_InitStruct)
 Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct. More...
 
void CRYP_StructInit (CRYP_InitTypeDef *CRYP_InitStruct)
 Fills each CRYP_InitStruct member with its default value. More...
 
void CRYP_KeyInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct. More...
 
void CRYP_KeyStructInit (CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Fills each CRYP_KeyInitStruct member with its default value. More...
 
void CRYP_IVInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVInitStruct. More...
 
void CRYP_IVStructInit (CRYP_IVInitTypeDef *CRYP_IVInitStruct)
 Fills each CRYP_IVInitStruct member with its default value. More...
 
void CRYP_Cmd (FunctionalState NewState)
 Enables or disables the CRYP peripheral. More...
 
void CRYP_PhaseConfig (uint32_t CRYP_Phase)
 Configures the AES-CCM and AES-GCM phases. More...
 
void CRYP_FIFOFlush (void)
 Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset) More...
 
void CRYP_DataIn (uint32_t Data)
 Writes data in the Data Input register (DIN). More...
 
uint32_t CRYP_DataOut (void)
 Returns the last data entered into the output FIFO. More...
 
ErrorStatus CRYP_SaveContext (CRYP_Context *CRYP_ContextSave, CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
 Saves the CRYP peripheral Context. More...
 
void CRYP_RestoreContext (CRYP_Context *CRYP_ContextRestore)
 Restores the CRYP peripheral Context. More...
 
void CRYP_DMACmd (uint8_t CRYP_DMAReq, FunctionalState NewState)
 Enables or disables the CRYP DMA interface. More...
 
void CRYP_ITConfig (uint8_t CRYP_IT, FunctionalState NewState)
 Enables or disables the specified CRYP interrupts. More...
 
ITStatus CRYP_GetITStatus (uint8_t CRYP_IT)
 Checks whether the specified CRYP interrupt has occurred or not. More...
 
FunctionalState CRYP_GetCmdStatus (void)
 Returns whether CRYP peripheral is enabled or disabled. More...
 
FlagStatus CRYP_GetFlagStatus (uint8_t CRYP_FLAG)
 Checks whether the specified CRYP flag is set or not. More...
 
ErrorStatus CRYP_AES_ECB (uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in ECB Mode. More...
 
ErrorStatus CRYP_AES_CBC (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CBC Mode. More...
 
ErrorStatus CRYP_AES_CTR (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CTR Mode. More...
 
ErrorStatus CRYP_AES_GCM (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG)
 Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_AES_CCM (uint8_t Mode, uint8_t *Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize)
 Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_TDES_ECB (uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in ECB Mode. More...
 
ErrorStatus CRYP_TDES_CBC (uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in CBC Mode. More...
 
ErrorStatus CRYP_DES_ECB (uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in ECB Mode. More...
 
ErrorStatus CRYP_DES_CBC (uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in CBC Mode. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the Cryptographic processor(CRYP) firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp_8h__dep__incl.map b/stm32f4xx__cryp_8h__dep__incl.map new file mode 100644 index 0000000..a814fbd --- /dev/null +++ b/stm32f4xx__cryp_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp_8h__dep__incl.md5 b/stm32f4xx__cryp_8h__dep__incl.md5 new file mode 100644 index 0000000..7be22e5 --- /dev/null +++ b/stm32f4xx__cryp_8h__dep__incl.md5 @@ -0,0 +1 @@ +2542de7d1d481d41c6af4a544ae170ac \ No newline at end of file diff --git a/stm32f4xx__cryp_8h__dep__incl.png b/stm32f4xx__cryp_8h__dep__incl.png new file mode 100644 index 0000000..7a319a1 Binary files /dev/null and b/stm32f4xx__cryp_8h__dep__incl.png differ diff --git a/stm32f4xx__cryp_8h__incl.map b/stm32f4xx__cryp_8h__incl.map new file mode 100644 index 0000000..1cb2d67 --- /dev/null +++ b/stm32f4xx__cryp_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp_8h__incl.md5 b/stm32f4xx__cryp_8h__incl.md5 new file mode 100644 index 0000000..b5bfe92 --- /dev/null +++ b/stm32f4xx__cryp_8h__incl.md5 @@ -0,0 +1 @@ +31f2ab49e06d03288c83ba9f260a16e4 \ No newline at end of file diff --git a/stm32f4xx__cryp_8h__incl.png b/stm32f4xx__cryp_8h__incl.png new file mode 100644 index 0000000..6aa7330 Binary files /dev/null and b/stm32f4xx__cryp_8h__incl.png differ diff --git a/stm32f4xx__cryp_8h_source.html b/stm32f4xx__cryp_8h_source.html new file mode 100644 index 0000000..17c3488 --- /dev/null +++ b/stm32f4xx__cryp_8h_source.html @@ -0,0 +1,394 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_cryp.h Source File + + + + + + + + + + +
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stm32f4xx_cryp.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_CRYP_H
+
31 #define __STM32F4xx_CRYP_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
53 typedef struct
+
54 {
+
55  uint32_t CRYP_AlgoDir;
+
57  uint32_t CRYP_AlgoMode;
+
60  uint32_t CRYP_DataType;
+
62  uint32_t CRYP_KeySize;
+
65 }CRYP_InitTypeDef;
+
66 
+
70 typedef struct
+
71 {
+
72  uint32_t CRYP_Key0Left;
+
73  uint32_t CRYP_Key0Right;
+
74  uint32_t CRYP_Key1Left;
+
75  uint32_t CRYP_Key1Right;
+
76  uint32_t CRYP_Key2Left;
+
77  uint32_t CRYP_Key2Right;
+
78  uint32_t CRYP_Key3Left;
+
79  uint32_t CRYP_Key3Right;
+
80 }CRYP_KeyInitTypeDef;
+
84 typedef struct
+
85 {
+
86  uint32_t CRYP_IV0Left;
+
87  uint32_t CRYP_IV0Right;
+
88  uint32_t CRYP_IV1Left;
+
89  uint32_t CRYP_IV1Right;
+
90 }CRYP_IVInitTypeDef;
+
91 
+
95 typedef struct
+
96 {
+
98  uint32_t CR_CurrentConfig;
+
100  uint32_t CRYP_IV0LR;
+
101  uint32_t CRYP_IV0RR;
+
102  uint32_t CRYP_IV1LR;
+
103  uint32_t CRYP_IV1RR;
+
105  uint32_t CRYP_K0LR;
+
106  uint32_t CRYP_K0RR;
+
107  uint32_t CRYP_K1LR;
+
108  uint32_t CRYP_K1RR;
+
109  uint32_t CRYP_K2LR;
+
110  uint32_t CRYP_K2RR;
+
111  uint32_t CRYP_K3LR;
+
112  uint32_t CRYP_K3RR;
+
113  uint32_t CRYP_CSGCMCCMR[8];
+
114  uint32_t CRYP_CSGCMR[8];
+
115 }CRYP_Context;
+
116 
+
117 
+
118 /* Exported constants --------------------------------------------------------*/
+
119 
+
127 #define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)
+
128 #define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)
+
129 #define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
+
130  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
+
131 
+
141 #define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000)
+
142 #define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008)
+
143 
+
145 #define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010)
+
146 #define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018)
+
147 
+
149 #define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020)
+
150 #define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028)
+
151 #define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030)
+
152 #define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038)
+
153 #define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000)
+
154 #define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008)
+
155 
+
156 #define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
+
157  ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
+
158  ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
+
159  ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
+
160  ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
+
161  ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
+
162  ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
+
163  ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
+
164  ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
+
165  ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
+
166 
+
175 #define CRYP_Phase_Init ((uint32_t)0x00000000)
+
176 #define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0
+
177 #define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1
+
178 #define CRYP_Phase_Final CRYP_CR_GCM_CCMPH
+
179 
+
180 #define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \
+
181  ((PHASE) == CRYP_Phase_Header) || \
+
182  ((PHASE) == CRYP_Phase_Payload) || \
+
183  ((PHASE) == CRYP_Phase_Final))
+
184 
+
192 #define CRYP_DataType_32b ((uint16_t)0x0000)
+
193 #define CRYP_DataType_16b ((uint16_t)0x0040)
+
194 #define CRYP_DataType_8b ((uint16_t)0x0080)
+
195 #define CRYP_DataType_1b ((uint16_t)0x00C0)
+
196 #define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
+
197  ((DATATYPE) == CRYP_DataType_16b)|| \
+
198  ((DATATYPE) == CRYP_DataType_8b)|| \
+
199  ((DATATYPE) == CRYP_DataType_1b))
+
200 
+
207 #define CRYP_KeySize_128b ((uint16_t)0x0000)
+
208 #define CRYP_KeySize_192b ((uint16_t)0x0100)
+
209 #define CRYP_KeySize_256b ((uint16_t)0x0200)
+
210 #define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
+
211  ((KEYSIZE) == CRYP_KeySize_192b)|| \
+
212  ((KEYSIZE) == CRYP_KeySize_256b))
+
213 
+
220 #define CRYP_FLAG_BUSY ((uint8_t)0x10)
+
224 #define CRYP_FLAG_IFEM ((uint8_t)0x01)
+
225 #define CRYP_FLAG_IFNF ((uint8_t)0x02)
+
226 #define CRYP_FLAG_INRIS ((uint8_t)0x22)
+
227 #define CRYP_FLAG_OFNE ((uint8_t)0x04)
+
229 #define CRYP_FLAG_OFFU ((uint8_t)0x08)
+
230 #define CRYP_FLAG_OUTRIS ((uint8_t)0x21)
+
233 #define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \
+
234  ((FLAG) == CRYP_FLAG_IFNF) || \
+
235  ((FLAG) == CRYP_FLAG_OFNE) || \
+
236  ((FLAG) == CRYP_FLAG_OFFU) || \
+
237  ((FLAG) == CRYP_FLAG_BUSY) || \
+
238  ((FLAG) == CRYP_FLAG_OUTRIS)|| \
+
239  ((FLAG) == CRYP_FLAG_INRIS))
+
240 
+
247 #define CRYP_IT_INI ((uint8_t)0x01)
+
248 #define CRYP_IT_OUTI ((uint8_t)0x02)
+
249 #define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
+
250 #define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
+
251 
+
259 #define MODE_ENCRYPT ((uint8_t)0x01)
+
260 #define MODE_DECRYPT ((uint8_t)0x00)
+
261 
+
269 #define CRYP_DMAReq_DataIN ((uint8_t)0x01)
+
270 #define CRYP_DMAReq_DataOUT ((uint8_t)0x02)
+
271 #define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
+
272 
+
280 /* Exported macro ------------------------------------------------------------*/
+
281 /* Exported functions --------------------------------------------------------*/
+
282 
+
283 /* Function used to set the CRYP configuration to the default reset state ****/
+
284 void CRYP_DeInit(void);
+
285 
+
286 /* CRYP Initialization and Configuration functions ****************************/
+
287 void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
+
288 void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
+
289 void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+
290 void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+
291 void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+
292 void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+
293 void CRYP_Cmd(FunctionalState NewState);
+
294 void CRYP_PhaseConfig(uint32_t CRYP_Phase);
+
295 void CRYP_FIFOFlush(void);
+
296 /* CRYP Data processing functions *********************************************/
+
297 void CRYP_DataIn(uint32_t Data);
+
298 uint32_t CRYP_DataOut(void);
+
299 
+
300 /* CRYP Context swapping functions ********************************************/
+
301 ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
+
302  CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+
303 void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
+
304 
+
305 /* CRYP DMA interface function ************************************************/
+
306 void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
+
307 
+
308 /* Interrupts and flags management functions **********************************/
+
309 void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
+
310 ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
+
311 FunctionalState CRYP_GetCmdStatus(void);
+
312 FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
+
313 
+
314 /* High Level AES functions **************************************************/
+
315 ErrorStatus CRYP_AES_ECB(uint8_t Mode,
+
316  uint8_t *Key, uint16_t Keysize,
+
317  uint8_t *Input, uint32_t Ilength,
+
318  uint8_t *Output);
+
319 
+
320 ErrorStatus CRYP_AES_CBC(uint8_t Mode,
+
321  uint8_t InitVectors[16],
+
322  uint8_t *Key, uint16_t Keysize,
+
323  uint8_t *Input, uint32_t Ilength,
+
324  uint8_t *Output);
+
325 
+
326 ErrorStatus CRYP_AES_CTR(uint8_t Mode,
+
327  uint8_t InitVectors[16],
+
328  uint8_t *Key, uint16_t Keysize,
+
329  uint8_t *Input, uint32_t Ilength,
+
330  uint8_t *Output);
+
331 
+
332 ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
+
333  uint8_t *Key, uint16_t Keysize,
+
334  uint8_t *Input, uint32_t ILength,
+
335  uint8_t *Header, uint32_t HLength,
+
336  uint8_t *Output, uint8_t *AuthTAG);
+
337 
+
338 ErrorStatus CRYP_AES_CCM(uint8_t Mode,
+
339  uint8_t* Nonce, uint32_t NonceSize,
+
340  uint8_t* Key, uint16_t Keysize,
+
341  uint8_t* Input, uint32_t ILength,
+
342  uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
+
343  uint8_t* Output,
+
344  uint8_t* AuthTAG, uint32_t TAGSize);
+
345 
+
346 /* High Level TDES functions **************************************************/
+
347 ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
+
348  uint8_t Key[24],
+
349  uint8_t *Input, uint32_t Ilength,
+
350  uint8_t *Output);
+
351 
+
352 ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
+
353  uint8_t Key[24],
+
354  uint8_t InitVectors[8],
+
355  uint8_t *Input, uint32_t Ilength,
+
356  uint8_t *Output);
+
357 
+
358 /* High Level DES functions **************************************************/
+
359 ErrorStatus CRYP_DES_ECB(uint8_t Mode,
+
360  uint8_t Key[8],
+
361  uint8_t *Input, uint32_t Ilength,
+
362  uint8_t *Output);
+
363 
+
364 ErrorStatus CRYP_DES_CBC(uint8_t Mode,
+
365  uint8_t Key[8],
+
366  uint8_t InitVectors[8],
+
367  uint8_t *Input,uint32_t Ilength,
+
368  uint8_t *Output);
+
369 
+
370 #ifdef __cplusplus
+
371 }
+
372 #endif
+
373 
+
374 #endif /*__STM32F4xx_CRYP_H */
+
375 
+
384 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
CRYP_Context
CRYP context swapping structure definition.
Definition: stm32f4xx_cryp.h:95
+
CRYP_IVStructInit
void CRYP_IVStructInit(CRYP_IVInitTypeDef *CRYP_IVInitStruct)
Fills each CRYP_IVInitStruct member with its default value.
Definition: stm32f4xx_cryp.c:347
+
CRYP_KeyInitTypeDef
CRYP Key(s) structure definition.
Definition: stm32f4xx_cryp.h:70
+
CRYP_KeyInit
void CRYP_KeyInit(CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
Initializes the CRYP Keys according to the specified parameters in the CRYP_KeyInitStruct.
Definition: stm32f4xx_cryp.c:296
+
CRYP_KeyInitTypeDef::CRYP_Key2Left
uint32_t CRYP_Key2Left
Definition: stm32f4xx_cryp.h:76
+
CRYP_InitTypeDef::CRYP_AlgoMode
uint32_t CRYP_AlgoMode
Definition: stm32f4xx_cryp.h:57
+
CRYP_IVInitTypeDef::CRYP_IV0Right
uint32_t CRYP_IV0Right
Definition: stm32f4xx_cryp.h:87
+
CRYP_KeyInitTypeDef::CRYP_Key1Left
uint32_t CRYP_Key1Left
Definition: stm32f4xx_cryp.h:74
+
CRYP_AES_CCM
ErrorStatus CRYP_AES_CCM(uint8_t Mode, uint8_t *Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize)
Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Dev...
Definition: stm32f4xx_cryp_aes.c:1135
+
CRYP_DES_ECB
ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using DES in ECB Mode.
Definition: stm32f4xx_cryp_des.c:99
+
CRYP_ITConfig
void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
Enables or disables the specified CRYP interrupts.
Definition: stm32f4xx_cryp.c:799
+
CRYP_GetITStatus
ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
Checks whether the specified CRYP interrupt has occurred or not.
Definition: stm32f4xx_cryp.c:827
+
CRYP_DMACmd
void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
Enables or disables the CRYP DMA interface.
Definition: stm32f4xx_cryp.c:681
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
CRYP_DeInit
void CRYP_DeInit(void)
Deinitializes the CRYP peripheral registers to their default reset values.
Definition: stm32f4xx_cryp.c:219
+
CRYP_PhaseConfig
void CRYP_PhaseConfig(uint32_t CRYP_Phase)
Configures the AES-CCM and AES-GCM phases.
Definition: stm32f4xx_cryp.c:366
+
CRYP_InitTypeDef::CRYP_AlgoDir
uint32_t CRYP_AlgoDir
Definition: stm32f4xx_cryp.h:55
+
CRYP_AES_GCM
ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG)
Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Dev...
Definition: stm32f4xx_cryp_aes.c:670
+
CRYP_IVInitTypeDef::CRYP_IV1Right
uint32_t CRYP_IV1Right
Definition: stm32f4xx_cryp.h:89
+
CRYP_Cmd
void CRYP_Cmd(FunctionalState NewState)
Enables or disables the CRYP peripheral.
Definition: stm32f4xx_cryp.c:403
+
CRYP_KeyInitTypeDef::CRYP_Key3Right
uint32_t CRYP_Key3Right
Definition: stm32f4xx_cryp.h:79
+
CRYP_DataOut
uint32_t CRYP_DataOut(void)
Returns the last data entered into the output FIFO.
Definition: stm32f4xx_cryp.c:456
+
CRYP_IVInit
void CRYP_IVInit(CRYP_IVInitTypeDef *CRYP_IVInitStruct)
Initializes the CRYP Initialization Vectors(IV) according to the specified parameters in the CRYP_IVI...
Definition: stm32f4xx_cryp.c:333
+
CRYP_TDES_CBC
ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using TDES in CBC Mode.
Definition: stm32f4xx_cryp_tdes.c:208
+
CRYP_InitTypeDef::CRYP_DataType
uint32_t CRYP_DataType
Definition: stm32f4xx_cryp.h:60
+
CRYP_KeyStructInit
void CRYP_KeyStructInit(CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
Fills each CRYP_KeyInitStruct member with its default value.
Definition: stm32f4xx_cryp.c:315
+
CRYP_DataIn
void CRYP_DataIn(uint32_t Data)
Writes data in the Data Input register (DIN).
Definition: stm32f4xx_cryp.c:446
+
CRYP_KeyInitTypeDef::CRYP_Key1Right
uint32_t CRYP_Key1Right
Definition: stm32f4xx_cryp.h:75
+
CRYP_KeyInitTypeDef::CRYP_Key0Right
uint32_t CRYP_Key0Right
Definition: stm32f4xx_cryp.h:73
+
CRYP_AES_CTR
ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using AES in CTR Mode.
Definition: stm32f4xx_cryp_aes.c:496
+
CRYP_KeyInitTypeDef::CRYP_Key2Right
uint32_t CRYP_Key2Right
Definition: stm32f4xx_cryp.h:77
+
CRYP_RestoreContext
void CRYP_RestoreContext(CRYP_Context *CRYP_ContextRestore)
Restores the CRYP peripheral Context.
Definition: stm32f4xx_cryp.c:602
+
CRYP_GetFlagStatus
FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
Checks whether the specified CRYP flag is set or not.
Definition: stm32f4xx_cryp.c:883
+
CRYP_Init
void CRYP_Init(CRYP_InitTypeDef *CRYP_InitStruct)
Initializes the CRYP peripheral according to the specified parameters in the CRYP_InitStruct.
Definition: stm32f4xx_cryp.c:235
+
CRYP_DES_CBC
ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using DES in CBC Mode.
Definition: stm32f4xx_cryp_des.c:200
+
CRYP_IVInitTypeDef::CRYP_IV0Left
uint32_t CRYP_IV0Left
Definition: stm32f4xx_cryp.h:86
+
CRYP_IVInitTypeDef
CRYP Initialization Vectors (IV) structure definition.
Definition: stm32f4xx_cryp.h:84
+
CRYP_KeyInitTypeDef::CRYP_Key0Left
uint32_t CRYP_Key0Left
Definition: stm32f4xx_cryp.h:72
+
CRYP_Context::CR_CurrentConfig
uint32_t CR_CurrentConfig
Definition: stm32f4xx_cryp.h:98
+
CRYP_KeyInitTypeDef::CRYP_Key3Left
uint32_t CRYP_Key3Left
Definition: stm32f4xx_cryp.h:78
+
CRYP_AES_ECB
ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using AES in ECB Mode.
Definition: stm32f4xx_cryp_aes.c:106
+
CRYP_AES_CBC
ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using AES in CBC Mode.
Definition: stm32f4xx_cryp_aes.c:294
+
CRYP_IVInitTypeDef::CRYP_IV1Left
uint32_t CRYP_IV1Left
Definition: stm32f4xx_cryp.h:88
+
CRYP_TDES_ECB
ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
Encrypt and decrypt using TDES in ECB Mode.
Definition: stm32f4xx_cryp_tdes.c:100
+
CRYP_FIFOFlush
void CRYP_FIFOFlush(void)
Flushes the IN and OUT FIFOs (that is read and write pointers of the FIFOs are reset) ...
Definition: stm32f4xx_cryp.c:391
+
CRYP_StructInit
void CRYP_StructInit(CRYP_InitTypeDef *CRYP_InitStruct)
Fills each CRYP_InitStruct member with its default value.
Definition: stm32f4xx_cryp.c:274
+
CRYP_InitTypeDef::CRYP_KeySize
uint32_t CRYP_KeySize
Definition: stm32f4xx_cryp.h:62
+
CRYP_InitTypeDef
CRYP Init structure definition.
Definition: stm32f4xx_cryp.h:53
+
CRYP_GetCmdStatus
FunctionalState CRYP_GetCmdStatus(void)
Returns whether CRYP peripheral is enabled or disabled.
Definition: stm32f4xx_cryp.c:853
+
CRYP_SaveContext
ErrorStatus CRYP_SaveContext(CRYP_Context *CRYP_ContextSave, CRYP_KeyInitTypeDef *CRYP_KeyInitStruct)
Saves the CRYP peripheral Context.
Definition: stm32f4xx_cryp.c:497
+
CRYP_Context::CRYP_IV1RR
uint32_t CRYP_IV1RR
Definition: stm32f4xx_cryp.h:103
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp__aes_8c.html b/stm32f4xx__cryp__aes_8c.html new file mode 100644 index 0000000..07a19a4 --- /dev/null +++ b/stm32f4xx__cryp__aes_8c.html @@ -0,0 +1,174 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_cryp_aes.c File Reference + + + + + + + + + + +
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discoverpixy +
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+Macros | +Functions
+
+
stm32f4xx_cryp_aes.c File Reference
+
+
+ +

This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR/GCM/CCM modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral. AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. +More...

+
#include "stm32f4xx_cryp.h"
+
+Include dependency graph for stm32f4xx_cryp_aes.c:
+
+
+ + +
+
+ + + +

+Macros

+#define AESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + + + + + + + + + + +

+Functions

ErrorStatus CRYP_AES_ECB (uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in ECB Mode. More...
 
ErrorStatus CRYP_AES_CBC (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CBC Mode. More...
 
ErrorStatus CRYP_AES_CTR (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using AES in CTR Mode. More...
 
ErrorStatus CRYP_AES_GCM (uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG)
 Encrypt and decrypt using AES in GCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
ErrorStatus CRYP_AES_CCM (uint8_t Mode, uint8_t *Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize)
 Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes are available only on STM32F437x Devices. More...
 
+

Detailed Description

+

This file provides high level functions to encrypt and decrypt an input message using AES in ECB/CBC/CTR/GCM/CCM modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral. AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
 ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable The CRYP controller clock using 
+      RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function.
+  
+   (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function.
+  
+   (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function.
+
+   (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function.
+   
+   (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function.
+
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp__aes_8c__incl.map b/stm32f4xx__cryp__aes_8c__incl.map new file mode 100644 index 0000000..31ce4c6 --- /dev/null +++ b/stm32f4xx__cryp__aes_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp__aes_8c__incl.md5 b/stm32f4xx__cryp__aes_8c__incl.md5 new file mode 100644 index 0000000..3056d3d --- /dev/null +++ b/stm32f4xx__cryp__aes_8c__incl.md5 @@ -0,0 +1 @@ +b276b2a5f2d27c6defbc14aefcd9df06 \ No newline at end of file diff --git a/stm32f4xx__cryp__aes_8c__incl.png b/stm32f4xx__cryp__aes_8c__incl.png new file mode 100644 index 0000000..6fc54f3 Binary files /dev/null and b/stm32f4xx__cryp__aes_8c__incl.png differ diff --git a/stm32f4xx__cryp__des_8c.html b/stm32f4xx__cryp__des_8c.html new file mode 100644 index 0000000..0d09ff2 --- /dev/null +++ b/stm32f4xx__cryp__des_8c.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_cryp_des.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_cryp_des.c File Reference
+
+
+ +

This file provides high level functions to encrypt and decrypt an input message using DES in ECB/CBC modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral. +More...

+
#include "stm32f4xx_cryp.h"
+
+Include dependency graph for stm32f4xx_cryp_des.c:
+
+
+ + +
+
+ + + +

+Macros

+#define DESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + +

+Functions

ErrorStatus CRYP_DES_ECB (uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in ECB Mode. More...
 
ErrorStatus CRYP_DES_CBC (uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using DES in CBC Mode. More...
 
+

Detailed Description

+

This file provides high level functions to encrypt and decrypt an input message using DES in ECB/CBC modes. It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
 ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..] 
+   (#) Enable The CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function.
+  
+   (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function.
+
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp__des_8c__incl.map b/stm32f4xx__cryp__des_8c__incl.map new file mode 100644 index 0000000..6ed3b1b --- /dev/null +++ b/stm32f4xx__cryp__des_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp__des_8c__incl.md5 b/stm32f4xx__cryp__des_8c__incl.md5 new file mode 100644 index 0000000..5edee78 --- /dev/null +++ b/stm32f4xx__cryp__des_8c__incl.md5 @@ -0,0 +1 @@ +2993711cd6d3fdd68edfc54c57c314cd \ No newline at end of file diff --git a/stm32f4xx__cryp__des_8c__incl.png b/stm32f4xx__cryp__des_8c__incl.png new file mode 100644 index 0000000..f46de15 Binary files /dev/null and b/stm32f4xx__cryp__des_8c__incl.png differ diff --git a/stm32f4xx__cryp__tdes_8c.html b/stm32f4xx__cryp__tdes_8c.html new file mode 100644 index 0000000..2e4595c --- /dev/null +++ b/stm32f4xx__cryp__tdes_8c.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_cryp_tdes.c File Reference + + + + + + + + + + +
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stm32f4xx_cryp_tdes.c File Reference
+
+
+ +

This file provides high level functions to encrypt and decrypt an input message using TDES in ECB/CBC modes . It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral. +More...

+
#include "stm32f4xx_cryp.h"
+
+Include dependency graph for stm32f4xx_cryp_tdes.c:
+
+
+ + +
+
+ + + +

+Macros

+#define TDESBUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + +

+Functions

ErrorStatus CRYP_TDES_ECB (uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in ECB Mode. More...
 
ErrorStatus CRYP_TDES_CBC (uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output)
 Encrypt and decrypt using TDES in CBC Mode. More...
 
+

Detailed Description

+

This file provides high level functions to encrypt and decrypt an input message using TDES in ECB/CBC modes . It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP peripheral.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
 ===============================================================================
+                           ##### How to use this driver #####
+ ===============================================================================
+ [..]
+   (#) Enable The CRYP controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  
+   (#) Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB() function.
+  
+   (#) Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC() function.
+
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__cryp__tdes_8c__incl.map b/stm32f4xx__cryp__tdes_8c__incl.map new file mode 100644 index 0000000..cc82d4f --- /dev/null +++ b/stm32f4xx__cryp__tdes_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__cryp__tdes_8c__incl.md5 b/stm32f4xx__cryp__tdes_8c__incl.md5 new file mode 100644 index 0000000..d9bdfda --- /dev/null +++ b/stm32f4xx__cryp__tdes_8c__incl.md5 @@ -0,0 +1 @@ +9e5c0042cd9a9eddb577ddfc2d9a2ac6 \ No newline at end of file diff --git a/stm32f4xx__cryp__tdes_8c__incl.png b/stm32f4xx__cryp__tdes_8c__incl.png new file mode 100644 index 0000000..3d1cecc Binary files /dev/null and b/stm32f4xx__cryp__tdes_8c__incl.png differ diff --git a/stm32f4xx__dac_8c.html b/stm32f4xx__dac_8c.html new file mode 100644 index 0000000..3883f16 --- /dev/null +++ b/stm32f4xx__dac_8c.html @@ -0,0 +1,301 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_dac.c File Reference + + + + + + + + + + +
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+Macros | +Functions
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+
stm32f4xx_dac.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral: +More...

+
#include "stm32f4xx_dac.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_dac.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + +

+Macros

+#define CR_CLEAR_MASK   ((uint32_t)0x00000FFE)
 
+#define DUAL_SWTRIG_SET   ((uint32_t)0x00000003)
 
+#define DUAL_SWTRIG_RESET   ((uint32_t)0xFFFFFFFC)
 
+#define DHR12R1_OFFSET   ((uint32_t)0x00000008)
 
+#define DHR12R2_OFFSET   ((uint32_t)0x00000014)
 
+#define DHR12RD_OFFSET   ((uint32_t)0x00000020)
 
+#define DOR_OFFSET   ((uint32_t)0x0000002C)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DAC_DeInit (void)
 Deinitializes the DAC peripheral registers to their default reset values. More...
 
void DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
 Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. More...
 
void DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
 Fills each DAC_InitStruct member with its default value. More...
 
void DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel. More...
 
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the selected DAC channel software trigger. More...
 
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
 Enables or disables simultaneously the two DAC channels software triggers. More...
 
void DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
 Enables or disables the selected DAC channel wave generation. More...
 
void DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel1. More...
 
void DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel2. More...
 
void DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
 Set the specified data holding register value for dual channel DAC. More...
 
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
 Returns the last data output value of the selected DAC channel. More...
 
void DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel DMA request. More...
 
void DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
 Enables or disables the specified DAC interrupts. More...
 
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Checks whether the specified DAC flag is set or not. More...
 
void DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Clears the DAC channel's pending flags. More...
 
ITStatus DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
 Checks whether the specified DAC interrupt has occurred or not. More...
 
void DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
 Clears the DAC channel's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Digital-to-Analog Converter (DAC) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • DAC channels configuration: trigger, output buffer, data format
    • +
  • DMA management
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                     ##### DAC Peripheral features #####
+===============================================================================
+   [..]        
+     *** DAC Channels ***
+     ====================  
+   [..]  
+   The device integrates two 12-bit Digital Analog Converters that can 
+   be used independently or simultaneously (dual mode):
+     (#) DAC channel1 with DAC_OUT1 (PA4) as output
+     (#) DAC channel2 with DAC_OUT2 (PA5) as output
+ 
+     *** DAC Triggers ***
+     ====================
+   [..]
+   Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+   and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
+   using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
+   [..] 
+   Digital to Analog conversion can be triggered by:
+     (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+         The used pin (GPIOx_Pin9) must be configured in input mode.
+ 
+     (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+         (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+         The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+ 
+     (#) Software using DAC_Trigger_Software
+ 
+     *** DAC Buffer mode feature ***
+     =============================== 
+     [..] 
+     Each DAC channel integrates an output buffer that can be used to 
+     reduce the output impedance, and to drive external loads directly
+     without having to add an external operational amplifier.
+     To enable, the output buffer use  
+     DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+     [..]           
+     (@) Refer to the device datasheet for more details about output 
+         impedance value with and without output buffer.
+           
+      *** DAC wave generation feature ***
+      =================================== 
+      [..]     
+      Both DAC channels can be used to generate
+        (#) Noise wave using DAC_WaveGeneration_Noise
+        (#) Triangle wave using DAC_WaveGeneration_Triangle
+         
+         -@-  Wave generation can be disabled using DAC_WaveGeneration_None
+ 
+      *** DAC data format ***
+      =======================
+      [..]   
+      The DAC data format can be:
+        (#) 8-bit right alignment using DAC_Align_8b_R
+        (#) 12-bit left alignment using DAC_Align_12b_L
+        (#) 12-bit right alignment using DAC_Align_12b_R
+ 
+      *** DAC data value to voltage correspondence ***  
+      ================================================ 
+      [..] 
+      The analog output voltage on each DAC channel pin is determined
+      by the following equation: 
+      DAC_OUTx = VREF+ * DOR / 4095
+      with  DOR is the Data Output Register
+         VEF+ is the input voltage reference (refer to the device datasheet)
+       e.g. To set DAC_OUT1 to 0.7V, use
+         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+         Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+ 
+      *** DMA requests  ***
+      =====================
+      [..]    
+      A DMA1 request can be generated when an external trigger (but not
+      a software trigger) occurs if DMA1 requests are enabled using
+      DAC_DMACmd()
+      [..]
+      DMA1 requests are mapped as following:
+        (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
+            already configured
+        (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
+            already configured
+ 
+     
+                     ##### How to use this driver #####
+===============================================================================
+   [..]          
+     (+) DAC APB clock must be enabled to get write access to DAC
+         registers using
+         RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+     (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
+     (+) Configure the DAC channel using DAC_Init() function
+     (+) Enable the DAC channel using DAC_Cmd() function
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dac_8c__incl.map b/stm32f4xx__dac_8c__incl.map new file mode 100644 index 0000000..8d3ee32 --- /dev/null +++ b/stm32f4xx__dac_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dac_8c__incl.md5 b/stm32f4xx__dac_8c__incl.md5 new file mode 100644 index 0000000..d1d37b1 --- /dev/null +++ b/stm32f4xx__dac_8c__incl.md5 @@ -0,0 +1 @@ +fed6fc036285802e9cc60c0f3d8437fc \ No newline at end of file diff --git a/stm32f4xx__dac_8c__incl.png b/stm32f4xx__dac_8c__incl.png new file mode 100644 index 0000000..cd11518 Binary files /dev/null and b/stm32f4xx__dac_8c__incl.png differ diff --git a/stm32f4xx__dac_8h.html b/stm32f4xx__dac_8h.html new file mode 100644 index 0000000..69800a9 --- /dev/null +++ b/stm32f4xx__dac_8h.html @@ -0,0 +1,329 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dac.h File Reference + + + + + + + + + + +
+
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+
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+
stm32f4xx_dac.h File Reference
+
+
+ +

This file contains all the functions prototypes for the DAC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_dac.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + +

+Classes

struct  DAC_InitTypeDef
 DAC Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DAC_Trigger_None   ((uint32_t)0x00000000)
 
#define DAC_Trigger_T2_TRGO   ((uint32_t)0x00000024)
 
#define DAC_Trigger_T4_TRGO   ((uint32_t)0x0000002C)
 
#define DAC_Trigger_T5_TRGO   ((uint32_t)0x0000001C)
 
#define DAC_Trigger_T6_TRGO   ((uint32_t)0x00000004)
 
#define DAC_Trigger_T7_TRGO   ((uint32_t)0x00000014)
 
#define DAC_Trigger_T8_TRGO   ((uint32_t)0x0000000C)
 
#define DAC_Trigger_Ext_IT9   ((uint32_t)0x00000034)
 
#define DAC_Trigger_Software   ((uint32_t)0x0000003C)
 
#define IS_DAC_TRIGGER(TRIGGER)
 
+#define DAC_WaveGeneration_None   ((uint32_t)0x00000000)
 
+#define DAC_WaveGeneration_Noise   ((uint32_t)0x00000040)
 
+#define DAC_WaveGeneration_Triangle   ((uint32_t)0x00000080)
 
#define IS_DAC_GENERATE_WAVE(WAVE)
 
#define DAC_LFSRUnmask_Bit0   ((uint32_t)0x00000000)
 
#define DAC_LFSRUnmask_Bits1_0   ((uint32_t)0x00000100)
 
#define DAC_LFSRUnmask_Bits2_0   ((uint32_t)0x00000200)
 
#define DAC_LFSRUnmask_Bits3_0   ((uint32_t)0x00000300)
 
#define DAC_LFSRUnmask_Bits4_0   ((uint32_t)0x00000400)
 
#define DAC_LFSRUnmask_Bits5_0   ((uint32_t)0x00000500)
 
#define DAC_LFSRUnmask_Bits6_0   ((uint32_t)0x00000600)
 
#define DAC_LFSRUnmask_Bits7_0   ((uint32_t)0x00000700)
 
#define DAC_LFSRUnmask_Bits8_0   ((uint32_t)0x00000800)
 
#define DAC_LFSRUnmask_Bits9_0   ((uint32_t)0x00000900)
 
#define DAC_LFSRUnmask_Bits10_0   ((uint32_t)0x00000A00)
 
#define DAC_LFSRUnmask_Bits11_0   ((uint32_t)0x00000B00)
 
#define DAC_TriangleAmplitude_1   ((uint32_t)0x00000000)
 
#define DAC_TriangleAmplitude_3   ((uint32_t)0x00000100)
 
#define DAC_TriangleAmplitude_7   ((uint32_t)0x00000200)
 
#define DAC_TriangleAmplitude_15   ((uint32_t)0x00000300)
 
#define DAC_TriangleAmplitude_31   ((uint32_t)0x00000400)
 
#define DAC_TriangleAmplitude_63   ((uint32_t)0x00000500)
 
#define DAC_TriangleAmplitude_127   ((uint32_t)0x00000600)
 
#define DAC_TriangleAmplitude_255   ((uint32_t)0x00000700)
 
#define DAC_TriangleAmplitude_511   ((uint32_t)0x00000800)
 
#define DAC_TriangleAmplitude_1023   ((uint32_t)0x00000900)
 
#define DAC_TriangleAmplitude_2047   ((uint32_t)0x00000A00)
 
#define DAC_TriangleAmplitude_4095   ((uint32_t)0x00000B00)
 
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)
 
+#define DAC_OutputBuffer_Enable   ((uint32_t)0x00000000)
 
+#define DAC_OutputBuffer_Disable   ((uint32_t)0x00000002)
 
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE)
 
+#define DAC_Channel_1   ((uint32_t)0x00000000)
 
+#define DAC_Channel_2   ((uint32_t)0x00000010)
 
#define IS_DAC_CHANNEL(CHANNEL)
 
+#define DAC_Align_12b_R   ((uint32_t)0x00000000)
 
+#define DAC_Align_12b_L   ((uint32_t)0x00000004)
 
+#define DAC_Align_8b_R   ((uint32_t)0x00000008)
 
#define IS_DAC_ALIGN(ALIGN)
 
+#define DAC_Wave_Noise   ((uint32_t)0x00000040)
 
+#define DAC_Wave_Triangle   ((uint32_t)0x00000080)
 
#define IS_DAC_WAVE(WAVE)
 
+#define IS_DAC_DATA(DATA)   ((DATA) <= 0xFFF0)
 
+#define DAC_IT_DMAUDR   ((uint32_t)0x00002000)
 
+#define IS_DAC_IT(IT)   (((IT) == DAC_IT_DMAUDR))
 
+#define DAC_FLAG_DMAUDR   ((uint32_t)0x00002000)
 
+#define IS_DAC_FLAG(FLAG)   (((FLAG) == DAC_FLAG_DMAUDR))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DAC_DeInit (void)
 Deinitializes the DAC peripheral registers to their default reset values. More...
 
void DAC_Init (uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
 Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct. More...
 
void DAC_StructInit (DAC_InitTypeDef *DAC_InitStruct)
 Fills each DAC_InitStruct member with its default value. More...
 
void DAC_Cmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel. More...
 
void DAC_SoftwareTriggerCmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the selected DAC channel software trigger. More...
 
void DAC_DualSoftwareTriggerCmd (FunctionalState NewState)
 Enables or disables simultaneously the two DAC channels software triggers. More...
 
void DAC_WaveGenerationCmd (uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
 Enables or disables the selected DAC channel wave generation. More...
 
void DAC_SetChannel1Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel1. More...
 
void DAC_SetChannel2Data (uint32_t DAC_Align, uint16_t Data)
 Set the specified data holding register value for DAC channel2. More...
 
void DAC_SetDualChannelData (uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
 Set the specified data holding register value for dual channel DAC. More...
 
uint16_t DAC_GetDataOutputValue (uint32_t DAC_Channel)
 Returns the last data output value of the selected DAC channel. More...
 
void DAC_DMACmd (uint32_t DAC_Channel, FunctionalState NewState)
 Enables or disables the specified DAC channel DMA request. More...
 
void DAC_ITConfig (uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
 Enables or disables the specified DAC interrupts. More...
 
FlagStatus DAC_GetFlagStatus (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Checks whether the specified DAC flag is set or not. More...
 
void DAC_ClearFlag (uint32_t DAC_Channel, uint32_t DAC_FLAG)
 Clears the DAC channel's pending flags. More...
 
ITStatus DAC_GetITStatus (uint32_t DAC_Channel, uint32_t DAC_IT)
 Checks whether the specified DAC interrupt has occurred or not. More...
 
void DAC_ClearITPendingBit (uint32_t DAC_Channel, uint32_t DAC_IT)
 Clears the DAC channel's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the DAC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dac_8h__dep__incl.map b/stm32f4xx__dac_8h__dep__incl.map new file mode 100644 index 0000000..2990a82 --- /dev/null +++ b/stm32f4xx__dac_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dac_8h__dep__incl.md5 b/stm32f4xx__dac_8h__dep__incl.md5 new file mode 100644 index 0000000..99ae1c5 --- /dev/null +++ b/stm32f4xx__dac_8h__dep__incl.md5 @@ -0,0 +1 @@ +27c92a942fc4341e5a913b309d21f0d6 \ No newline at end of file diff --git a/stm32f4xx__dac_8h__dep__incl.png b/stm32f4xx__dac_8h__dep__incl.png new file mode 100644 index 0000000..c101dcd Binary files /dev/null and b/stm32f4xx__dac_8h__dep__incl.png differ diff --git a/stm32f4xx__dac_8h__incl.map b/stm32f4xx__dac_8h__incl.map new file mode 100644 index 0000000..df3ea74 --- /dev/null +++ b/stm32f4xx__dac_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dac_8h__incl.md5 b/stm32f4xx__dac_8h__incl.md5 new file mode 100644 index 0000000..189f559 --- /dev/null +++ b/stm32f4xx__dac_8h__incl.md5 @@ -0,0 +1 @@ +aefc22fbd7d982d979e15cf27d08fcfa \ No newline at end of file diff --git a/stm32f4xx__dac_8h__incl.png b/stm32f4xx__dac_8h__incl.png new file mode 100644 index 0000000..2149187 Binary files /dev/null and b/stm32f4xx__dac_8h__incl.png differ diff --git a/stm32f4xx__dac_8h_source.html b/stm32f4xx__dac_8h_source.html new file mode 100644 index 0000000..d6bd981 --- /dev/null +++ b/stm32f4xx__dac_8h_source.html @@ -0,0 +1,288 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dac.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + + + +
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+ + +
+ +
+ + +
+
+
+
stm32f4xx_dac.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_DAC_H
+
31 #define __STM32F4xx_DAC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t DAC_Trigger;
+
59  uint32_t DAC_WaveGeneration;
+
63  uint32_t DAC_LFSRUnmask_TriangleAmplitude;
+
67  uint32_t DAC_OutputBuffer;
+
69 }DAC_InitTypeDef;
+
70 
+
71 /* Exported constants --------------------------------------------------------*/
+
72 
+
81 #define DAC_Trigger_None ((uint32_t)0x00000000)
+
83 #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
+
84 #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
+
85 #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
+
86 #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
+
87 #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
+
88 #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
+
90 #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
+
91 #define DAC_Trigger_Software ((uint32_t)0x0000003C)
+
93 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+
94  ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+
95  ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+
96  ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+
97  ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+
98  ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+
99  ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+
100  ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+
101  ((TRIGGER) == DAC_Trigger_Software))
+
102 
+
111 #define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+
112 #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+
113 #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+
114 #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+
115  ((WAVE) == DAC_WaveGeneration_Noise) || \
+
116  ((WAVE) == DAC_WaveGeneration_Triangle))
+
117 
+
125 #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
+
126 #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
+
127 #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
+
128 #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
+
129 #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
+
130 #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
+
131 #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
+
132 #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
+
133 #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
+
134 #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
+
135 #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
+
136 #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
+
137 #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
+
138 #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
+
139 #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
+
140 #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
+
141 #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
+
142 #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
+
143 #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
+
144 #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
+
145 #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
+
146 #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
+
147 #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
+
148 #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
+
150 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+
151  ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+
152  ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+
153  ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+
154  ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+
155  ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+
156  ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+
157  ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+
158  ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+
159  ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+
160  ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+
161  ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+
162  ((VALUE) == DAC_TriangleAmplitude_1) || \
+
163  ((VALUE) == DAC_TriangleAmplitude_3) || \
+
164  ((VALUE) == DAC_TriangleAmplitude_7) || \
+
165  ((VALUE) == DAC_TriangleAmplitude_15) || \
+
166  ((VALUE) == DAC_TriangleAmplitude_31) || \
+
167  ((VALUE) == DAC_TriangleAmplitude_63) || \
+
168  ((VALUE) == DAC_TriangleAmplitude_127) || \
+
169  ((VALUE) == DAC_TriangleAmplitude_255) || \
+
170  ((VALUE) == DAC_TriangleAmplitude_511) || \
+
171  ((VALUE) == DAC_TriangleAmplitude_1023) || \
+
172  ((VALUE) == DAC_TriangleAmplitude_2047) || \
+
173  ((VALUE) == DAC_TriangleAmplitude_4095))
+
174 
+
182 #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+
183 #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
+
184 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+
185  ((STATE) == DAC_OutputBuffer_Disable))
+
186 
+
194 #define DAC_Channel_1 ((uint32_t)0x00000000)
+
195 #define DAC_Channel_2 ((uint32_t)0x00000010)
+
196 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+
197  ((CHANNEL) == DAC_Channel_2))
+
198 
+
206 #define DAC_Align_12b_R ((uint32_t)0x00000000)
+
207 #define DAC_Align_12b_L ((uint32_t)0x00000004)
+
208 #define DAC_Align_8b_R ((uint32_t)0x00000008)
+
209 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+
210  ((ALIGN) == DAC_Align_12b_L) || \
+
211  ((ALIGN) == DAC_Align_8b_R))
+
212 
+
220 #define DAC_Wave_Noise ((uint32_t)0x00000040)
+
221 #define DAC_Wave_Triangle ((uint32_t)0x00000080)
+
222 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+
223  ((WAVE) == DAC_Wave_Triangle))
+
224 
+
232 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
233 
+
240 #define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+
241 #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
242 
+
251 #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+
252 #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
253 
+
262 /* Exported macro ------------------------------------------------------------*/
+
263 /* Exported functions --------------------------------------------------------*/
+
264 
+
265 /* Function used to set the DAC configuration to the default reset state *****/
+
266 void DAC_DeInit(void);
+
267 
+
268 /* DAC channels configuration: trigger, output buffer, data format functions */
+
269 void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+
270 void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+
271 void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+
272 void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+
273 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+
274 void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+
275 void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+
276 void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+
277 void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+
278 uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
279 
+
280 /* DMA management functions ***************************************************/
+
281 void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
282 
+
283 /* Interrupts and flags management functions **********************************/
+
284 void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+
285 FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+
286 void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+
287 ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+
288 void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
289 
+
290 #ifdef __cplusplus
+
291 }
+
292 #endif
+
293 
+
294 #endif /*__STM32F4xx_DAC_H */
+
295 
+
304 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
DAC_ClearFlag
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Clears the DAC channel's pending flags.
Definition: stm32f4xx_dac.c:625
+
DAC_ClearITPendingBit
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
Clears the DAC channel's interrupt pending bits.
Definition: stm32f4xx_dac.c:688
+
DAC_SetChannel1Data
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel1.
Definition: stm32f4xx_dac.c:378
+
DAC_Cmd
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel.
Definition: stm32f4xx_dac.c:266
+
DAC_SoftwareTriggerCmd
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the selected DAC channel software trigger.
Definition: stm32f4xx_dac.c:294
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
DAC_InitTypeDef::DAC_WaveGeneration
uint32_t DAC_WaveGeneration
Definition: stm32f4xx_dac.h:59
+
DAC_DMACmd
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
Enables or disables the specified DAC channel DMA request.
Definition: stm32f4xx_dac.c:510
+
DAC_WaveGenerationCmd
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
Enables or disables the selected DAC channel wave generation.
Definition: stm32f4xx_dac.c:349
+
DAC_GetITStatus
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
Checks whether the specified DAC interrupt has occurred or not.
Definition: stm32f4xx_dac.c:648
+
DAC_SetChannel2Data
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
Set the specified data holding register value for DAC channel2.
Definition: stm32f4xx_dac.c:403
+
DAC_DeInit
void DAC_DeInit(void)
Deinitializes the DAC peripheral registers to their default reset values.
Definition: stm32f4xx_dac.c:187
+
DAC_Init
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
Definition: stm32f4xx_dac.c:206
+
DAC_StructInit
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
Fills each DAC_InitStruct member with its default value.
Definition: stm32f4xx_dac.c:242
+
DAC_InitTypeDef
DAC Init structure definition.
Definition: stm32f4xx_dac.h:54
+
DAC_GetDataOutputValue
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
Returns the last data output value of the selected DAC channel.
Definition: stm32f4xx_dac.c:465
+
DAC_InitTypeDef::DAC_Trigger
uint32_t DAC_Trigger
Definition: stm32f4xx_dac.h:56
+
DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude
uint32_t DAC_LFSRUnmask_TriangleAmplitude
Definition: stm32f4xx_dac.h:63
+
DAC_DualSoftwareTriggerCmd
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
Enables or disables simultaneously the two DAC channels software triggers.
Definition: stm32f4xx_dac.c:318
+
DAC_ITConfig
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
Enables or disables the specified DAC interrupts.
Definition: stm32f4xx_dac.c:558
+
DAC_InitTypeDef::DAC_OutputBuffer
uint32_t DAC_OutputBuffer
Definition: stm32f4xx_dac.h:67
+
DAC_SetDualChannelData
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
Set the specified data holding register value for dual channel DAC.
Definition: stm32f4xx_dac.c:431
+
DAC_GetFlagStatus
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
Checks whether the specified DAC flag is set or not.
Definition: stm32f4xx_dac.c:590
+
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+ + diff --git a/stm32f4xx__dbgmcu_8c.html b/stm32f4xx__dbgmcu_8c.html new file mode 100644 index 0000000..e3da075 --- /dev/null +++ b/stm32f4xx__dbgmcu_8c.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_dbgmcu.c File Reference + + + + + + + + + + +
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+Macros | +Functions
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+
stm32f4xx_dbgmcu.c File Reference
+
+
+ +

This file provides all the DBGMCU firmware functions. +More...

+
#include "stm32f4xx_dbgmcu.h"
+
+Include dependency graph for stm32f4xx_dbgmcu.c:
+
+
+ + +
+
+ + + +

+Macros

+#define IDCODE_DEVID_MASK   ((uint32_t)0x00000FFF)
 
+ + + + + + + + + + + + + + + + +

+Functions

uint32_t DBGMCU_GetREVID (void)
 Returns the device revision identifier. More...
 
uint32_t DBGMCU_GetDEVID (void)
 Returns the device identifier. More...
 
void DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures low power mode behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB1 peripheral behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB2 peripheral behavior when the MCU is in Debug mode. More...
 
+

Detailed Description

+

This file provides all the DBGMCU firmware functions.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dbgmcu_8c__incl.map b/stm32f4xx__dbgmcu_8c__incl.map new file mode 100644 index 0000000..0849593 --- /dev/null +++ b/stm32f4xx__dbgmcu_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dbgmcu_8c__incl.md5 b/stm32f4xx__dbgmcu_8c__incl.md5 new file mode 100644 index 0000000..4f7874f --- /dev/null +++ b/stm32f4xx__dbgmcu_8c__incl.md5 @@ -0,0 +1 @@ +1932a2aff4f0a7ca8f0b23e2d069d311 \ No newline at end of file diff --git a/stm32f4xx__dbgmcu_8c__incl.png b/stm32f4xx__dbgmcu_8c__incl.png new file mode 100644 index 0000000..1067edb Binary files /dev/null and b/stm32f4xx__dbgmcu_8c__incl.png differ diff --git a/stm32f4xx__dbgmcu_8h.html b/stm32f4xx__dbgmcu_8h.html new file mode 100644 index 0000000..7bc9463 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h.html @@ -0,0 +1,239 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dbgmcu.h File Reference + + + + + + + + + + +
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stm32f4xx_dbgmcu.h File Reference
+
+
+ +

This file contains all the functions prototypes for the DBGMCU firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_dbgmcu.h:
+
+
+ + +
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+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

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+Macros

+#define DBGMCU_SLEEP   ((uint32_t)0x00000001)
 
+#define DBGMCU_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_STANDBY   ((uint32_t)0x00000004)
 
+#define IS_DBGMCU_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
 
+#define DBGMCU_TIM2_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM3_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM4_STOP   ((uint32_t)0x00000004)
 
+#define DBGMCU_TIM5_STOP   ((uint32_t)0x00000008)
 
+#define DBGMCU_TIM6_STOP   ((uint32_t)0x00000010)
 
+#define DBGMCU_TIM7_STOP   ((uint32_t)0x00000020)
 
+#define DBGMCU_TIM12_STOP   ((uint32_t)0x00000040)
 
+#define DBGMCU_TIM13_STOP   ((uint32_t)0x00000080)
 
+#define DBGMCU_TIM14_STOP   ((uint32_t)0x00000100)
 
+#define DBGMCU_RTC_STOP   ((uint32_t)0x00000400)
 
+#define DBGMCU_WWDG_STOP   ((uint32_t)0x00000800)
 
+#define DBGMCU_IWDG_STOP   ((uint32_t)0x00001000)
 
+#define DBGMCU_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
 
+#define DBGMCU_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
 
+#define DBGMCU_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
 
+#define DBGMCU_CAN1_STOP   ((uint32_t)0x02000000)
 
+#define DBGMCU_CAN2_STOP   ((uint32_t)0x04000000)
 
+#define IS_DBGMCU_APB1PERIPH(PERIPH)   ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
 
+#define DBGMCU_TIM1_STOP   ((uint32_t)0x00000001)
 
+#define DBGMCU_TIM8_STOP   ((uint32_t)0x00000002)
 
+#define DBGMCU_TIM9_STOP   ((uint32_t)0x00010000)
 
+#define DBGMCU_TIM10_STOP   ((uint32_t)0x00020000)
 
+#define DBGMCU_TIM11_STOP   ((uint32_t)0x00040000)
 
+#define IS_DBGMCU_APB2PERIPH(PERIPH)   ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
 
+ + + + + + + + + + + + + + + + +

+Functions

uint32_t DBGMCU_GetREVID (void)
 Returns the device revision identifier. More...
 
uint32_t DBGMCU_GetDEVID (void)
 Returns the device identifier. More...
 
void DBGMCU_Config (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures low power mode behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB1PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB1 peripheral behavior when the MCU is in Debug mode. More...
 
void DBGMCU_APB2PeriphConfig (uint32_t DBGMCU_Periph, FunctionalState NewState)
 Configures APB2 peripheral behavior when the MCU is in Debug mode. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the DBGMCU firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dbgmcu_8h__dep__incl.map b/stm32f4xx__dbgmcu_8h__dep__incl.map new file mode 100644 index 0000000..1d60b72 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dbgmcu_8h__dep__incl.md5 b/stm32f4xx__dbgmcu_8h__dep__incl.md5 new file mode 100644 index 0000000..5f062c0 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h__dep__incl.md5 @@ -0,0 +1 @@ +99046d52119abec39dbda1e8738d7633 \ No newline at end of file diff --git a/stm32f4xx__dbgmcu_8h__dep__incl.png b/stm32f4xx__dbgmcu_8h__dep__incl.png new file mode 100644 index 0000000..1e27e9f Binary files /dev/null and b/stm32f4xx__dbgmcu_8h__dep__incl.png differ diff --git a/stm32f4xx__dbgmcu_8h__incl.map b/stm32f4xx__dbgmcu_8h__incl.map new file mode 100644 index 0000000..55dc254 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dbgmcu_8h__incl.md5 b/stm32f4xx__dbgmcu_8h__incl.md5 new file mode 100644 index 0000000..67036a8 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h__incl.md5 @@ -0,0 +1 @@ +dfdec94cfae6070200cd8162be400c00 \ No newline at end of file diff --git a/stm32f4xx__dbgmcu_8h__incl.png b/stm32f4xx__dbgmcu_8h__incl.png new file mode 100644 index 0000000..4e6494b Binary files /dev/null and b/stm32f4xx__dbgmcu_8h__incl.png differ diff --git a/stm32f4xx__dbgmcu_8h_source.html b/stm32f4xx__dbgmcu_8h_source.html new file mode 100644 index 0000000..b599e28 --- /dev/null +++ b/stm32f4xx__dbgmcu_8h_source.html @@ -0,0 +1,168 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dbgmcu.h Source File + + + + + + + + + + +
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stm32f4xx_dbgmcu.h
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1 
+
28 /* Define to prevent recursive inclusion -------------------------------------*/
+
29 #ifndef __STM32F4xx_DBGMCU_H
+
30 #define __STM32F4xx_DBGMCU_H
+
31 
+
32 #ifdef __cplusplus
+
33  extern "C" {
+
34 #endif
+
35 
+
36 /* Includes ------------------------------------------------------------------*/
+
37 #include "stm32f4xx.h"
+
38 
+
47 /* Exported types ------------------------------------------------------------*/
+
48 /* Exported constants --------------------------------------------------------*/
+
49 
+
53 #define DBGMCU_SLEEP ((uint32_t)0x00000001)
+
54 #define DBGMCU_STOP ((uint32_t)0x00000002)
+
55 #define DBGMCU_STANDBY ((uint32_t)0x00000004)
+
56 #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
57 
+
58 #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
+
59 #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
+
60 #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
+
61 #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
+
62 #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
+
63 #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
+
64 #define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
+
65 #define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)
+
66 #define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)
+
67 #define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
+
68 #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
+
69 #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
+
70 #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+
71 #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+
72 #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
+
73 #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
+
74 #define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)
+
75 #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
+
76 
+
77 #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
+
78 #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
+
79 #define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)
+
80 #define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)
+
81 #define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)
+
82 #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
+
83 
+
87 /* Exported macro ------------------------------------------------------------*/
+
88 /* Exported functions --------------------------------------------------------*/
+
89 uint32_t DBGMCU_GetREVID(void);
+
90 uint32_t DBGMCU_GetDEVID(void);
+
91 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
92 void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
93 void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
94 
+
95 #ifdef __cplusplus
+
96 }
+
97 #endif
+
98 
+
99 #endif /* __STM32F4xx_DBGMCU_H */
+
100 
+
109 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
DBGMCU_APB1PeriphConfig
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB1 peripheral behavior when the MCU is in Debug mode.
Definition: stm32f4xx_dbgmcu.c:123
+
DBGMCU_APB2PeriphConfig
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures APB2 peripheral behavior when the MCU is in Debug mode.
Definition: stm32f4xx_dbgmcu.c:152
+
DBGMCU_GetDEVID
uint32_t DBGMCU_GetDEVID(void)
Returns the device identifier.
Definition: stm32f4xx_dbgmcu.c:68
+
DBGMCU_GetREVID
uint32_t DBGMCU_GetREVID(void)
Returns the device revision identifier.
Definition: stm32f4xx_dbgmcu.c:58
+
DBGMCU_Config
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
Configures low power mode behavior when the MCU is in Debug mode.
Definition: stm32f4xx_dbgmcu.c:84
+
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+ + diff --git a/stm32f4xx__dcmi_8c.html b/stm32f4xx__dcmi_8c.html new file mode 100644 index 0000000..c3d4197 --- /dev/null +++ b/stm32f4xx__dcmi_8c.html @@ -0,0 +1,226 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_dcmi.c File Reference + + + + + + + + + + +
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+
stm32f4xx_dcmi.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the DCMI peripheral: +More...

+
#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_dcmi.c:
+
+
+ + +
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+Functions

void DCMI_DeInit (void)
 Deinitializes the DCMI registers to their default reset values. More...
 
void DCMI_Init (DCMI_InitTypeDef *DCMI_InitStruct)
 Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. More...
 
void DCMI_StructInit (DCMI_InitTypeDef *DCMI_InitStruct)
 Fills each DCMI_InitStruct member with its default value. More...
 
void DCMI_CROPConfig (DCMI_CROPInitTypeDef *DCMI_CROPInitStruct)
 Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct. More...
 
void DCMI_CROPCmd (FunctionalState NewState)
 Enables or disables the DCMI Crop feature. More...
 
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef *DCMI_CodesInitStruct)
 Sets the embedded synchronization codes. More...
 
void DCMI_JPEGCmd (FunctionalState NewState)
 Enables or disables the DCMI JPEG format. More...
 
void DCMI_Cmd (FunctionalState NewState)
 Enables or disables the DCMI interface. More...
 
void DCMI_CaptureCmd (FunctionalState NewState)
 Enables or disables the DCMI Capture. More...
 
uint32_t DCMI_ReadData (void)
 Reads the data stored in the DR register. More...
 
void DCMI_ITConfig (uint16_t DCMI_IT, FunctionalState NewState)
 Enables or disables the DCMI interface interrupts. More...
 
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
 Checks whether the DCMI interface flag is set or not. More...
 
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
 Clears the DCMI's pending flags. More...
 
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
 Checks whether the DCMI interrupt has occurred or not. More...
 
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
 Clears the DCMI's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the DCMI peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Image capture functions
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                       ##### How to use this driver #####
+===============================================================================  
+   [..]       
+     The sequence below describes how to use this driver to capture image
+     from a camera module connected to the DCMI Interface.
+     This sequence does not take into account the configuration of the  
+     camera module, which should be made before to configure and enable
+     the DCMI to capture images.
+            
+     (#) Enable the clock for the DCMI and associated GPIOs using the following 
+         functions:
+         RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
+         RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+ 
+     (#) DCMI pins configuration 
+       (++) Connect the involved DCMI pins to AF13 using the following function 
+           GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); 
+       (++) Configure these DCMI pins in alternate function mode by calling 
+           the function GPIO_Init();
+     
+     (#) Declare a DCMI_InitTypeDef structure, for example:
+         DCMI_InitTypeDef  DCMI_InitStructure;
+         and fill the DCMI_InitStructure variable with the allowed values
+         of the structure member.
+   
+     (#) Initialize the DCMI interface by calling the function
+         DCMI_Init(&DCMI_InitStructure); 
+   
+     (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+         register to the destination memory buffer.
+   
+     (#) Enable DCMI interface using the function
+         DCMI_Cmd(ENABLE);
+                  
+     (#) Start the image capture using the function
+         DCMI_CaptureCmd(ENABLE);
+                  
+     (#) At this stage the DCMI interface waits for the first start of frame,
+         then a DMA request is generated continuously/once (depending on the
+         mode used, Continuous/Snapshot) to transfer the received data into
+         the destination memory. 
+    
+     -@-  If you need to capture only a rectangular window from the received
+          image, you have to use the DCMI_CROPConfig() function to configure 
+          the coordinates and size of the window to be captured, then enable 
+          the Crop feature using DCMI_CROPCmd(ENABLE);  
+          In this case, the Crop configuration should be made before to enable
+          and start the DCMI interface.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
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stm32f4xx_dcmi.h File Reference
+
+
+ +

This file contains all the functions prototypes for the DCMI firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_dcmi.h:
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+ + + + + + + + + + + +

+Classes

struct  DCMI_InitTypeDef
 DCMI Init structure definition. More...
 
struct  DCMI_CROPInitTypeDef
 DCMI CROP Init structure definition. More...
 
struct  DCMI_CodesInitTypeDef
 DCMI Embedded Synchronisation CODE Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DCMI_CaptureMode_Continuous   ((uint16_t)0x0000)
 
#define DCMI_CaptureMode_SnapShot   ((uint16_t)0x0002)
 
#define IS_DCMI_CAPTURE_MODE(MODE)
 
#define DCMI_SynchroMode_Hardware   ((uint16_t)0x0000)
 
#define DCMI_SynchroMode_Embedded   ((uint16_t)0x0010)
 
#define IS_DCMI_SYNCHRO(MODE)
 
#define DCMI_PCKPolarity_Falling   ((uint16_t)0x0000)
 
#define DCMI_PCKPolarity_Rising   ((uint16_t)0x0020)
 
#define IS_DCMI_PCKPOLARITY(POLARITY)
 
#define DCMI_VSPolarity_Low   ((uint16_t)0x0000)
 
#define DCMI_VSPolarity_High   ((uint16_t)0x0080)
 
#define IS_DCMI_VSPOLARITY(POLARITY)
 
#define DCMI_HSPolarity_Low   ((uint16_t)0x0000)
 
#define DCMI_HSPolarity_High   ((uint16_t)0x0040)
 
#define IS_DCMI_HSPOLARITY(POLARITY)
 
#define DCMI_CaptureRate_All_Frame   ((uint16_t)0x0000)
 
#define DCMI_CaptureRate_1of2_Frame   ((uint16_t)0x0100)
 
#define DCMI_CaptureRate_1of4_Frame   ((uint16_t)0x0200)
 
#define IS_DCMI_CAPTURE_RATE(RATE)
 
#define DCMI_ExtendedDataMode_8b   ((uint16_t)0x0000)
 
#define DCMI_ExtendedDataMode_10b   ((uint16_t)0x0400)
 
#define DCMI_ExtendedDataMode_12b   ((uint16_t)0x0800)
 
#define DCMI_ExtendedDataMode_14b   ((uint16_t)0x0C00)
 
#define IS_DCMI_EXTENDED_DATA(DATA)
 
+#define DCMI_IT_FRAME   ((uint16_t)0x0001)
 
+#define DCMI_IT_OVF   ((uint16_t)0x0002)
 
+#define DCMI_IT_ERR   ((uint16_t)0x0004)
 
+#define DCMI_IT_VSYNC   ((uint16_t)0x0008)
 
+#define DCMI_IT_LINE   ((uint16_t)0x0010)
 
+#define IS_DCMI_CONFIG_IT(IT)   ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
 
#define IS_DCMI_GET_IT(IT)
 
+#define DCMI_FLAG_HSYNC   ((uint16_t)0x2001)
 DCMI SR register.
 
+#define DCMI_FLAG_VSYNC   ((uint16_t)0x2002)
 
+#define DCMI_FLAG_FNE   ((uint16_t)0x2004)
 
+#define DCMI_FLAG_FRAMERI   ((uint16_t)0x0001)
 DCMI RISR register.
 
+#define DCMI_FLAG_OVFRI   ((uint16_t)0x0002)
 
+#define DCMI_FLAG_ERRRI   ((uint16_t)0x0004)
 
+#define DCMI_FLAG_VSYNCRI   ((uint16_t)0x0008)
 
+#define DCMI_FLAG_LINERI   ((uint16_t)0x0010)
 
+#define DCMI_FLAG_FRAMEMI   ((uint16_t)0x1001)
 DCMI MISR register.
 
+#define DCMI_FLAG_OVFMI   ((uint16_t)0x1002)
 
+#define DCMI_FLAG_ERRMI   ((uint16_t)0x1004)
 
+#define DCMI_FLAG_VSYNCMI   ((uint16_t)0x1008)
 
+#define DCMI_FLAG_LINEMI   ((uint16_t)0x1010)
 
#define IS_DCMI_GET_FLAG(FLAG)
 
+#define IS_DCMI_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DCMI_DeInit (void)
 Deinitializes the DCMI registers to their default reset values. More...
 
void DCMI_Init (DCMI_InitTypeDef *DCMI_InitStruct)
 Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. More...
 
void DCMI_StructInit (DCMI_InitTypeDef *DCMI_InitStruct)
 Fills each DCMI_InitStruct member with its default value. More...
 
void DCMI_CROPConfig (DCMI_CROPInitTypeDef *DCMI_CROPInitStruct)
 Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitStruct. More...
 
void DCMI_CROPCmd (FunctionalState NewState)
 Enables or disables the DCMI Crop feature. More...
 
void DCMI_SetEmbeddedSynchroCodes (DCMI_CodesInitTypeDef *DCMI_CodesInitStruct)
 Sets the embedded synchronization codes. More...
 
void DCMI_JPEGCmd (FunctionalState NewState)
 Enables or disables the DCMI JPEG format. More...
 
void DCMI_Cmd (FunctionalState NewState)
 Enables or disables the DCMI interface. More...
 
void DCMI_CaptureCmd (FunctionalState NewState)
 Enables or disables the DCMI Capture. More...
 
uint32_t DCMI_ReadData (void)
 Reads the data stored in the DR register. More...
 
void DCMI_ITConfig (uint16_t DCMI_IT, FunctionalState NewState)
 Enables or disables the DCMI interface interrupts. More...
 
FlagStatus DCMI_GetFlagStatus (uint16_t DCMI_FLAG)
 Checks whether the DCMI interface flag is set or not. More...
 
void DCMI_ClearFlag (uint16_t DCMI_FLAG)
 Clears the DCMI's pending flags. More...
 
ITStatus DCMI_GetITStatus (uint16_t DCMI_IT)
 Checks whether the DCMI interrupt has occurred or not. More...
 
void DCMI_ClearITPendingBit (uint16_t DCMI_IT)
 Clears the DCMI's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the DCMI firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dcmi_8h__dep__incl.map b/stm32f4xx__dcmi_8h__dep__incl.map new file mode 100644 index 0000000..67b2a5f --- /dev/null +++ b/stm32f4xx__dcmi_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dcmi_8h__dep__incl.md5 b/stm32f4xx__dcmi_8h__dep__incl.md5 new file mode 100644 index 0000000..8e04872 --- /dev/null +++ b/stm32f4xx__dcmi_8h__dep__incl.md5 @@ -0,0 +1 @@ +85e503d1ee59c90d073bd2c7fa185345 \ No newline at end of file diff --git a/stm32f4xx__dcmi_8h__dep__incl.png b/stm32f4xx__dcmi_8h__dep__incl.png new file mode 100644 index 0000000..4e12c03 Binary files /dev/null and b/stm32f4xx__dcmi_8h__dep__incl.png differ diff --git a/stm32f4xx__dcmi_8h__incl.map b/stm32f4xx__dcmi_8h__incl.map new file mode 100644 index 0000000..71b2149 --- /dev/null +++ b/stm32f4xx__dcmi_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dcmi_8h__incl.md5 b/stm32f4xx__dcmi_8h__incl.md5 new file mode 100644 index 0000000..bb4ecd3 --- /dev/null +++ b/stm32f4xx__dcmi_8h__incl.md5 @@ -0,0 +1 @@ +1e9383bf2200f6ae0f33ad9f92ecb2f5 \ No newline at end of file diff --git a/stm32f4xx__dcmi_8h__incl.png b/stm32f4xx__dcmi_8h__incl.png new file mode 100644 index 0000000..6a8a983 Binary files /dev/null and b/stm32f4xx__dcmi_8h__incl.png differ diff --git a/stm32f4xx__dcmi_8h_source.html b/stm32f4xx__dcmi_8h_source.html new file mode 100644 index 0000000..badee5f --- /dev/null +++ b/stm32f4xx__dcmi_8h_source.html @@ -0,0 +1,294 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dcmi.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx_dcmi.h
+
+
+Go to the documentation of this file.
1 
+
28 /* Define to prevent recursive inclusion -------------------------------------*/
+
29 #ifndef __STM32F4xx_DCMI_H
+
30 #define __STM32F4xx_DCMI_H
+
31 
+
32 #ifdef __cplusplus
+
33  extern "C" {
+
34 #endif
+
35 
+
36 /* Includes ------------------------------------------------------------------*/
+
37 #include "stm32f4xx.h"
+
38 
+
47 /* Exported types ------------------------------------------------------------*/
+
51 typedef struct
+
52 {
+
53  uint16_t DCMI_CaptureMode;
+
56  uint16_t DCMI_SynchroMode;
+
59  uint16_t DCMI_PCKPolarity;
+
62  uint16_t DCMI_VSPolarity;
+
65  uint16_t DCMI_HSPolarity;
+
68  uint16_t DCMI_CaptureRate;
+
71  uint16_t DCMI_ExtendedDataMode;
+
73 } DCMI_InitTypeDef;
+
74 
+
78 typedef struct
+
79 {
+
80  uint16_t DCMI_VerticalStartLine;
+
83  uint16_t DCMI_HorizontalOffsetCount;
+
86  uint16_t DCMI_VerticalLineCount;
+
89  uint16_t DCMI_CaptureCount;
+
92 } DCMI_CROPInitTypeDef;
+
93 
+
97 typedef struct
+
98 {
+
99  uint8_t DCMI_FrameStartCode;
+
100  uint8_t DCMI_LineStartCode;
+
101  uint8_t DCMI_LineEndCode;
+
102  uint8_t DCMI_FrameEndCode;
+
103 } DCMI_CodesInitTypeDef;
+
104 
+
105 /* Exported constants --------------------------------------------------------*/
+
106 
+
114 #define DCMI_CaptureMode_Continuous ((uint16_t)0x0000)
+
116 #define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002)
+
118 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
+
119  ((MODE) == DCMI_CaptureMode_SnapShot))
+
120 
+
128 #define DCMI_SynchroMode_Hardware ((uint16_t)0x0000)
+
130 #define DCMI_SynchroMode_Embedded ((uint16_t)0x0010)
+
132 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
+
133  ((MODE) == DCMI_SynchroMode_Embedded))
+
134 
+
142 #define DCMI_PCKPolarity_Falling ((uint16_t)0x0000)
+
143 #define DCMI_PCKPolarity_Rising ((uint16_t)0x0020)
+
144 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
+
145  ((POLARITY) == DCMI_PCKPolarity_Rising))
+
146 
+
154 #define DCMI_VSPolarity_Low ((uint16_t)0x0000)
+
155 #define DCMI_VSPolarity_High ((uint16_t)0x0080)
+
156 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
+
157  ((POLARITY) == DCMI_VSPolarity_High))
+
158 
+
166 #define DCMI_HSPolarity_Low ((uint16_t)0x0000)
+
167 #define DCMI_HSPolarity_High ((uint16_t)0x0040)
+
168 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
+
169  ((POLARITY) == DCMI_HSPolarity_High))
+
170 
+
178 #define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000)
+
179 #define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100)
+
180 #define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200)
+
181 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
+
182  ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
+
183  ((RATE) == DCMI_CaptureRate_1of4_Frame))
+
184 
+
192 #define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000)
+
193 #define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400)
+
194 #define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800)
+
195 #define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00)
+
196 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
+
197  ((DATA) == DCMI_ExtendedDataMode_10b) ||\
+
198  ((DATA) == DCMI_ExtendedDataMode_12b) ||\
+
199  ((DATA) == DCMI_ExtendedDataMode_14b))
+
200 
+
208 #define DCMI_IT_FRAME ((uint16_t)0x0001)
+
209 #define DCMI_IT_OVF ((uint16_t)0x0002)
+
210 #define DCMI_IT_ERR ((uint16_t)0x0004)
+
211 #define DCMI_IT_VSYNC ((uint16_t)0x0008)
+
212 #define DCMI_IT_LINE ((uint16_t)0x0010)
+
213 #define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+
214 #define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+
215  ((IT) == DCMI_IT_OVF) || \
+
216  ((IT) == DCMI_IT_ERR) || \
+
217  ((IT) == DCMI_IT_VSYNC) || \
+
218  ((IT) == DCMI_IT_LINE))
+
219 
+
230 #define DCMI_FLAG_HSYNC ((uint16_t)0x2001)
+
231 #define DCMI_FLAG_VSYNC ((uint16_t)0x2002)
+
232 #define DCMI_FLAG_FNE ((uint16_t)0x2004)
+
233 
+
236 #define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
+
237 #define DCMI_FLAG_OVFRI ((uint16_t)0x0002)
+
238 #define DCMI_FLAG_ERRRI ((uint16_t)0x0004)
+
239 #define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
+
240 #define DCMI_FLAG_LINERI ((uint16_t)0x0010)
+
241 
+
244 #define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
+
245 #define DCMI_FLAG_OVFMI ((uint16_t)0x1002)
+
246 #define DCMI_FLAG_ERRMI ((uint16_t)0x1004)
+
247 #define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
+
248 #define DCMI_FLAG_LINEMI ((uint16_t)0x1010)
+
249 #define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
+
250  ((FLAG) == DCMI_FLAG_VSYNC) || \
+
251  ((FLAG) == DCMI_FLAG_FNE) || \
+
252  ((FLAG) == DCMI_FLAG_FRAMERI) || \
+
253  ((FLAG) == DCMI_FLAG_OVFRI) || \
+
254  ((FLAG) == DCMI_FLAG_ERRRI) || \
+
255  ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+
256  ((FLAG) == DCMI_FLAG_LINERI) || \
+
257  ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+
258  ((FLAG) == DCMI_FLAG_OVFMI) || \
+
259  ((FLAG) == DCMI_FLAG_ERRMI) || \
+
260  ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+
261  ((FLAG) == DCMI_FLAG_LINEMI))
+
262 
+
263 #define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+
264 
+
272 /* Exported macro ------------------------------------------------------------*/
+
273 /* Exported functions --------------------------------------------------------*/
+
274 
+
275 /* Function used to set the DCMI configuration to the default reset state ****/
+
276 void DCMI_DeInit(void);
+
277 
+
278 /* Initialization and Configuration functions *********************************/
+
279 void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
+
280 void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
+
281 void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
+
282 void DCMI_CROPCmd(FunctionalState NewState);
+
283 void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
+
284 void DCMI_JPEGCmd(FunctionalState NewState);
+
285 
+
286 /* Image capture functions ****************************************************/
+
287 void DCMI_Cmd(FunctionalState NewState);
+
288 void DCMI_CaptureCmd(FunctionalState NewState);
+
289 uint32_t DCMI_ReadData(void);
+
290 
+
291 /* Interrupts and flags management functions **********************************/
+
292 void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
+
293 FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
+
294 void DCMI_ClearFlag(uint16_t DCMI_FLAG);
+
295 ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
+
296 void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
+
297 
+
298 #ifdef __cplusplus
+
299 }
+
300 #endif
+
301 
+
302 #endif /*__STM32F4xx_DCMI_H */
+
303 
+
312 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
DCMI_InitTypeDef::DCMI_CaptureMode
uint16_t DCMI_CaptureMode
Definition: stm32f4xx_dcmi.h:53
+
DCMI_GetFlagStatus
FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
Checks whether the DCMI interface flag is set or not.
Definition: stm32f4xx_dcmi.c:414
+
DCMI_Cmd
void DCMI_Cmd(FunctionalState NewState)
Enables or disables the DCMI interface.
Definition: stm32f4xx_dcmi.c:299
+
DCMI_InitTypeDef::DCMI_CaptureRate
uint16_t DCMI_CaptureRate
Definition: stm32f4xx_dcmi.h:68
+
DCMI_InitTypeDef
DCMI Init structure definition.
Definition: stm32f4xx_dcmi.h:51
+
DCMI_CodesInitTypeDef::DCMI_FrameStartCode
uint8_t DCMI_FrameStartCode
Definition: stm32f4xx_dcmi.h:99
+
DCMI_CROPInitTypeDef::DCMI_VerticalLineCount
uint16_t DCMI_VerticalLineCount
Definition: stm32f4xx_dcmi.h:86
+
DCMI_CROPConfig
void DCMI_CROPConfig(DCMI_CROPInitTypeDef *DCMI_CROPInitStruct)
Initializes the DCMI peripheral CROP mode according to the specified parameters in the DCMI_CROPInitS...
Definition: stm32f4xx_dcmi.c:205
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
DCMI_ReadData
uint32_t DCMI_ReadData(void)
Reads the data stored in the DR register.
Definition: stm32f4xx_dcmi.c:344
+
DCMI_CodesInitTypeDef
DCMI Embedded Synchronisation CODE Init structure definition.
Definition: stm32f4xx_dcmi.h:97
+
DCMI_ClearFlag
void DCMI_ClearFlag(uint16_t DCMI_FLAG)
Clears the DCMI's pending flags.
Definition: stm32f4xx_dcmi.c:461
+
DCMI_InitTypeDef::DCMI_PCKPolarity
uint16_t DCMI_PCKPolarity
Definition: stm32f4xx_dcmi.h:59
+
DCMI_DeInit
void DCMI_DeInit(void)
Deinitializes the DCMI registers to their default reset values.
Definition: stm32f4xx_dcmi.c:126
+
DCMI_InitTypeDef::DCMI_VSPolarity
uint16_t DCMI_VSPolarity
Definition: stm32f4xx_dcmi.h:62
+
DCMI_SetEmbeddedSynchroCodes
void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef *DCMI_CodesInitStruct)
Sets the embedded synchronization codes.
Definition: stm32f4xx_dcmi.c:246
+
DCMI_GetITStatus
ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
Checks whether the DCMI interrupt has occurred or not.
Definition: stm32f4xx_dcmi.c:483
+
DCMI_Init
void DCMI_Init(DCMI_InitTypeDef *DCMI_InitStruct)
Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
Definition: stm32f4xx_dcmi.c:143
+
DCMI_CROPInitTypeDef::DCMI_VerticalStartLine
uint16_t DCMI_VerticalStartLine
Definition: stm32f4xx_dcmi.h:80
+
DCMI_StructInit
void DCMI_StructInit(DCMI_InitTypeDef *DCMI_InitStruct)
Fills each DCMI_InitStruct member with its default value.
Definition: stm32f4xx_dcmi.c:185
+
DCMI_CaptureCmd
void DCMI_CaptureCmd(FunctionalState NewState)
Enables or disables the DCMI Capture.
Definition: stm32f4xx_dcmi.c:322
+
DCMI_InitTypeDef::DCMI_SynchroMode
uint16_t DCMI_SynchroMode
Definition: stm32f4xx_dcmi.h:56
+
DCMI_InitTypeDef::DCMI_HSPolarity
uint16_t DCMI_HSPolarity
Definition: stm32f4xx_dcmi.h:65
+
DCMI_JPEGCmd
void DCMI_JPEGCmd(FunctionalState NewState)
Enables or disables the DCMI JPEG format.
Definition: stm32f4xx_dcmi.c:261
+
DCMI_InitTypeDef::DCMI_ExtendedDataMode
uint16_t DCMI_ExtendedDataMode
Definition: stm32f4xx_dcmi.h:71
+
DCMI_ClearITPendingBit
void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
Clears the DCMI's interrupt pending bits.
Definition: stm32f4xx_dcmi.c:515
+
DCMI_CodesInitTypeDef::DCMI_FrameEndCode
uint8_t DCMI_FrameEndCode
Definition: stm32f4xx_dcmi.h:102
+
DCMI_CROPInitTypeDef
DCMI CROP Init structure definition.
Definition: stm32f4xx_dcmi.h:78
+
DCMI_CodesInitTypeDef::DCMI_LineStartCode
uint8_t DCMI_LineStartCode
Definition: stm32f4xx_dcmi.h:100
+
DCMI_CodesInitTypeDef::DCMI_LineEndCode
uint8_t DCMI_LineEndCode
Definition: stm32f4xx_dcmi.h:101
+
DCMI_CROPInitTypeDef::DCMI_HorizontalOffsetCount
uint16_t DCMI_HorizontalOffsetCount
Definition: stm32f4xx_dcmi.h:83
+
DCMI_ITConfig
void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
Enables or disables the DCMI interface interrupts.
Definition: stm32f4xx_dcmi.c:377
+
DCMI_CROPInitTypeDef::DCMI_CaptureCount
uint16_t DCMI_CaptureCount
Definition: stm32f4xx_dcmi.h:89
+
DCMI_CROPCmd
void DCMI_CROPCmd(FunctionalState NewState)
Enables or disables the DCMI Crop feature.
Definition: stm32f4xx_dcmi.c:223
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dma2d_8c.html b/stm32f4xx__dma2d_8c.html new file mode 100644 index 0000000..e630b08 --- /dev/null +++ b/stm32f4xx__dma2d_8c.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_dma2d.c File Reference + + + + + + + + + + +
+
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discoverpixy +
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+Macros | +Functions
+
+
stm32f4xx_dma2d.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the DMA2D controller (DMA2D) peripheral: +More...

+
#include "stm32f4xx_dma2d.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_dma2d.c:
+
+
+ + +
+
+ + + + + + + +

+Macros

+#define CR_MASK   ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */
 
+#define PFCCR_MASK   ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */
 
+#define DEAD_MASK   ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA2D_DeInit (void)
 Deinitializes the DMA2D peripheral registers to their default reset values. More...
 
void DMA2D_Init (DMA2D_InitTypeDef *DMA2D_InitStruct)
 Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct. More...
 
+void DMA2D_StructInit (DMA2D_InitTypeDef *DMA2D_InitStruct)
 
void DMA2D_StartTransfer (void)
 Start the DMA2D transfer. More...
 
void DMA2D_AbortTransfer (void)
 Aboart the DMA2D transfer. More...
 
void DMA2D_Suspend (FunctionalState NewState)
 Stop or continue the DMA2D transfer. More...
 
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Configures the Foreground according to the specified parameters in the DMA2D_FGStruct. More...
 
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Fills each DMA2D_FGStruct member with its default value. More...
 
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Configures the Background according to the specified parameters in the DMA2D_BGStruct. More...
 
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Fills each DMA2D_BGStruct member with its default value. More...
 
void DMA2D_FGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_BGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime, FunctionalState NewState)
 Configures the DMA2D dead time. More...
 
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
 Define the configuration of the line watermark . More...
 
void DMA2D_ITConfig (uint32_t DMA2D_IT, FunctionalState NewState)
 Enables or disables the specified DMA2D's interrupts. More...
 
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
 Checks whether the specified DMA2D's flag is set or not. More...
 
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
 Clears the DMA2D's pending flags. More...
 
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
 Checks whether the specified DMA2D's interrupt has occurred or not. More...
 
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
 Clears the DMA2D's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the DMA2D controller (DMA2D) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and configuration
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                     ##### How to use this driver #####
+===============================================================================
+   [..]
+       (#) Enable DMA2D clock using 
+           RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function.
+           
+       (#) Configures DMA2D
+         (++) transfer mode 
+         (++) pixel format, line_number, pixel_per_line
+         (++) output memory address
+         (++) alpha value
+         (++) output offset
+         (++) Default color (RGB)
+          
+       (#) Configures Foreground or/and background
+         (++) memory address
+         (++) alpha value
+         (++) offset and default color
+ 
+       (#) Call the DMA2D_Start() to enable the DMA2D controller.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dma2d_8c__incl.map b/stm32f4xx__dma2d_8c__incl.map new file mode 100644 index 0000000..60130be --- /dev/null +++ b/stm32f4xx__dma2d_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dma2d_8c__incl.md5 b/stm32f4xx__dma2d_8c__incl.md5 new file mode 100644 index 0000000..6091797 --- /dev/null +++ b/stm32f4xx__dma2d_8c__incl.md5 @@ -0,0 +1 @@ +6b890d57b41f51e638475c291c48c752 \ No newline at end of file diff --git a/stm32f4xx__dma2d_8c__incl.png b/stm32f4xx__dma2d_8c__incl.png new file mode 100644 index 0000000..205d304 Binary files /dev/null and b/stm32f4xx__dma2d_8c__incl.png differ diff --git a/stm32f4xx__dma2d_8h.html b/stm32f4xx__dma2d_8h.html new file mode 100644 index 0000000..679e34b --- /dev/null +++ b/stm32f4xx__dma2d_8h.html @@ -0,0 +1,428 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dma2d.h File Reference + + + + + + + + + + +
+
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+Classes | +Macros | +Functions
+
+
stm32f4xx_dma2d.h File Reference
+
+
+ +

This file contains all the functions prototypes for the DMA2D firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_dma2d.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+

Go to the source code of this file.

+ + + + + + + + + +

+Classes

struct  DMA2D_InitTypeDef
 DMA2D Init structure definition. More...
 
struct  DMA2D_FG_InitTypeDef
 
struct  DMA2D_BG_InitTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define DMA2D_M2M   ((uint32_t)0x00000000)
 
+#define DMA2D_M2M_PFC   ((uint32_t)0x00010000)
 
+#define DMA2D_M2M_BLEND   ((uint32_t)0x00020000)
 
+#define DMA2D_R2M   ((uint32_t)0x00030000)
 
#define IS_DMA2D_MODE(MODE)
 
+#define DMA2D_ARGB8888   ((uint32_t)0x00000000)
 
+#define DMA2D_RGB888   ((uint32_t)0x00000001)
 
+#define DMA2D_RGB565   ((uint32_t)0x00000002)
 
+#define DMA2D_ARGB1555   ((uint32_t)0x00000003)
 
+#define DMA2D_ARGB4444   ((uint32_t)0x00000004)
 
#define IS_DMA2D_CMODE(MODE_ARGB)
 
+#define DMA2D_Output_Color   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_OGREEN(OGREEN)   ((OGREEN) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_ORED(ORED)   ((ORED) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_OBLUE(OBLUE)   ((OBLUE) <= DMA2D_Output_Color)
 
+#define IS_DMA2D_OALPHA(OALPHA)   ((OALPHA) <= DMA2D_Output_Color)
 
+#define DMA2D_OUTPUT_OFFSET   ((uint32_t)0x00003FFF)
 
+#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET)   ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
 
+#define DMA2D_pixel   ((uint32_t)0x00003FFF)
 
+#define DMA2D_Line   ((uint32_t)0x0000FFFF)
 
+#define IS_DMA2D_LINE(LINE)   ((LINE) <= DMA2D_Line)
 
+#define IS_DMA2D_PIXEL(PIXEL)   ((PIXEL) <= DMA2D_pixel)
 
+#define OFFSET   ((uint32_t)0x00003FFF)
 
+#define IS_DMA2D_FGO(FGO)   ((FGO) <= OFFSET)
 
+#define IS_DMA2D_BGO(BGO)   ((BGO) <= OFFSET)
 
+#define CM_ARGB8888   ((uint32_t)0x00000000)
 
+#define CM_RGB888   ((uint32_t)0x00000001)
 
+#define CM_RGB565   ((uint32_t)0x00000002)
 
+#define CM_ARGB1555   ((uint32_t)0x00000003)
 
+#define CM_ARGB4444   ((uint32_t)0x00000004)
 
+#define CM_L8   ((uint32_t)0x00000005)
 
+#define CM_AL44   ((uint32_t)0x00000006)
 
+#define CM_AL88   ((uint32_t)0x00000007)
 
+#define CM_L4   ((uint32_t)0x00000008)
 
+#define CM_A8   ((uint32_t)0x00000009)
 
+#define CM_A4   ((uint32_t)0x0000000A)
 
#define IS_DMA2D_FGCM(FGCM)
 
#define IS_DMA2D_BGCM(BGCM)
 
+#define CLUT_CM_ARGB8888   ((uint32_t)0x00000000)
 
+#define CLUT_CM_RGB888   ((uint32_t)0x00000001)
 
+#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM)   (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
 
+#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM)   (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
 
+#define COLOR_VALUE   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE)   ((FG_CLUT_SIZE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE)   ((FG_ALPHA_VALUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_BLUE(FGC_BLUE)   ((FGC_BLUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_GREEN(FGC_GREEN)   ((FGC_GREEN) <= COLOR_VALUE)
 
+#define IS_DMA2D_FGC_RED(FGC_RED)   ((FGC_RED) <= COLOR_VALUE)
 
+#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE)   ((BG_CLUT_SIZE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE)   ((BG_ALPHA_VALUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_BLUE(BGC_BLUE)   ((BGC_BLUE) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_GREEN(BGC_GREEN)   ((BGC_GREEN) <= COLOR_VALUE)
 
+#define IS_DMA2D_BGC_RED(BGC_RED)   ((BGC_RED) <= COLOR_VALUE)
 
+#define DMA2D_IT_CE   DMA2D_CR_CEIE
 
+#define DMA2D_IT_CTC   DMA2D_CR_CTCIE
 
+#define DMA2D_IT_CAE   DMA2D_CR_CAEIE
 
+#define DMA2D_IT_TW   DMA2D_CR_TWIE
 
+#define DMA2D_IT_TC   DMA2D_CR_TCIE
 
+#define DMA2D_IT_TE   DMA2D_CR_TEIE
 
#define IS_DMA2D_IT(IT)
 
+#define DMA2D_FLAG_CE   DMA2D_ISR_CEIF
 
+#define DMA2D_FLAG_CTC   DMA2D_ISR_CTCIF
 
+#define DMA2D_FLAG_CAE   DMA2D_ISR_CAEIF
 
+#define DMA2D_FLAG_TW   DMA2D_ISR_TWIF
 
+#define DMA2D_FLAG_TC   DMA2D_ISR_TCIF
 
+#define DMA2D_FLAG_TE   DMA2D_ISR_TEIF
 
#define IS_DMA2D_GET_FLAG(FLAG)
 
+#define DEADTIME   ((uint32_t)0x000000FF)
 
+#define IS_DMA2D_DEAD_TIME(DEAD_TIME)   ((DEAD_TIME) <= DEADTIME)
 
+#define LINE_WATERMARK   DMA2D_LWR_LW
 
+#define IS_DMA2D_LineWatermark(LineWatermark)   ((LineWatermark) <= LINE_WATERMARK)
 
#define NO_MODIF_ALPHA_VALUE   ((uint32_t)0x00000000)
 
+#define REPLACE_ALPHA_VALUE   ((uint32_t)0x00000001)
 
+#define COMBINE_ALPHA_VALUE   ((uint32_t)0x00000002)
 
#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE)
 
#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA2D_DeInit (void)
 Deinitializes the DMA2D peripheral registers to their default reset values. More...
 
void DMA2D_Init (DMA2D_InitTypeDef *DMA2D_InitStruct)
 Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct. More...
 
+void DMA2D_StructInit (DMA2D_InitTypeDef *DMA2D_InitStruct)
 
void DMA2D_StartTransfer (void)
 Start the DMA2D transfer. More...
 
void DMA2D_AbortTransfer (void)
 Aboart the DMA2D transfer. More...
 
void DMA2D_Suspend (FunctionalState NewState)
 Stop or continue the DMA2D transfer. More...
 
void DMA2D_FGConfig (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Configures the Foreground according to the specified parameters in the DMA2D_FGStruct. More...
 
void DMA2D_FG_StructInit (DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
 Fills each DMA2D_FGStruct member with its default value. More...
 
void DMA2D_BGConfig (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Configures the Background according to the specified parameters in the DMA2D_BGStruct. More...
 
void DMA2D_BG_StructInit (DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
 Fills each DMA2D_BGStruct member with its default value. More...
 
void DMA2D_FGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_BGStart (FunctionalState NewState)
 Start the automatic loading of the CLUT or abort the transfer. More...
 
void DMA2D_DeadTimeConfig (uint32_t DMA2D_DeadTime, FunctionalState NewState)
 Configures the DMA2D dead time. More...
 
void DMA2D_LineWatermarkConfig (uint32_t DMA2D_LWatermarkConfig)
 Define the configuration of the line watermark . More...
 
void DMA2D_ITConfig (uint32_t DMA2D_IT, FunctionalState NewState)
 Enables or disables the specified DMA2D's interrupts. More...
 
FlagStatus DMA2D_GetFlagStatus (uint32_t DMA2D_FLAG)
 Checks whether the specified DMA2D's flag is set or not. More...
 
void DMA2D_ClearFlag (uint32_t DMA2D_FLAG)
 Clears the DMA2D's pending flags. More...
 
ITStatus DMA2D_GetITStatus (uint32_t DMA2D_IT)
 Checks whether the specified DMA2D's interrupt has occurred or not. More...
 
void DMA2D_ClearITPendingBit (uint32_t DMA2D_IT)
 Clears the DMA2D's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the DMA2D firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dma2d_8h__dep__incl.map b/stm32f4xx__dma2d_8h__dep__incl.map new file mode 100644 index 0000000..2fa79d8 --- /dev/null +++ b/stm32f4xx__dma2d_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/stm32f4xx__dma2d_8h__dep__incl.md5 b/stm32f4xx__dma2d_8h__dep__incl.md5 new file mode 100644 index 0000000..29f754f --- /dev/null +++ b/stm32f4xx__dma2d_8h__dep__incl.md5 @@ -0,0 +1 @@ +50f88ada2e5d7e22daf17bfd040e1682 \ No newline at end of file diff --git a/stm32f4xx__dma2d_8h__dep__incl.png b/stm32f4xx__dma2d_8h__dep__incl.png new file mode 100644 index 0000000..f625db3 Binary files /dev/null and b/stm32f4xx__dma2d_8h__dep__incl.png differ diff --git a/stm32f4xx__dma2d_8h__incl.map b/stm32f4xx__dma2d_8h__incl.map new file mode 100644 index 0000000..fe4285b --- /dev/null +++ b/stm32f4xx__dma2d_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dma2d_8h__incl.md5 b/stm32f4xx__dma2d_8h__incl.md5 new file mode 100644 index 0000000..fb5e365 --- /dev/null +++ b/stm32f4xx__dma2d_8h__incl.md5 @@ -0,0 +1 @@ +f5b8e7c3924d6dc3e16c10f93aed7eae \ No newline at end of file diff --git a/stm32f4xx__dma2d_8h__incl.png b/stm32f4xx__dma2d_8h__incl.png new file mode 100644 index 0000000..6cc0e24 Binary files /dev/null and b/stm32f4xx__dma2d_8h__incl.png differ diff --git a/stm32f4xx__dma2d_8h_source.html b/stm32f4xx__dma2d_8h_source.html new file mode 100644 index 0000000..7a3cf99 --- /dev/null +++ b/stm32f4xx__dma2d_8h_source.html @@ -0,0 +1,394 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dma2d.h Source File + + + + + + + + + + +
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stm32f4xx_dma2d.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_DMA2D_H
+
31 #define __STM32F4xx_DMA2D_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t DMA2D_Mode;
+
59  uint32_t DMA2D_CMode;
+
62  uint32_t DMA2D_OutputBlue;
+
70  uint32_t DMA2D_OutputGreen;
+
78  uint32_t DMA2D_OutputRed;
+
86  uint32_t DMA2D_OutputAlpha;
+
92  uint32_t DMA2D_OutputMemoryAdd;
+
95  uint32_t DMA2D_OutputOffset;
+
98  uint32_t DMA2D_NumberOfLine;
+
101  uint32_t DMA2D_PixelPerLine;
+
103 } DMA2D_InitTypeDef;
+
104 
+
105 
+
106 
+
107 typedef struct
+
108 {
+
109  uint32_t DMA2D_FGMA;
+
112  uint32_t DMA2D_FGO;
+
115  uint32_t DMA2D_FGCM;
+
118  uint32_t DMA2D_FG_CLUT_CM;
+
121  uint32_t DMA2D_FG_CLUT_SIZE;
+
124  uint32_t DMA2D_FGPFC_ALPHA_MODE;
+
127  uint32_t DMA2D_FGPFC_ALPHA_VALUE;
+
130  uint32_t DMA2D_FGC_BLUE;
+
133  uint32_t DMA2D_FGC_GREEN;
+
136  uint32_t DMA2D_FGC_RED;
+
139  uint32_t DMA2D_FGCMAR;
+
141 } DMA2D_FG_InitTypeDef;
+
142 
+
143 
+
144 typedef struct
+
145 {
+
146  uint32_t DMA2D_BGMA;
+
149  uint32_t DMA2D_BGO;
+
152  uint32_t DMA2D_BGCM;
+
155  uint32_t DMA2D_BG_CLUT_CM;
+
158  uint32_t DMA2D_BG_CLUT_SIZE;
+
161  uint32_t DMA2D_BGPFC_ALPHA_MODE;
+
164  uint32_t DMA2D_BGPFC_ALPHA_VALUE;
+
167  uint32_t DMA2D_BGC_BLUE;
+
170  uint32_t DMA2D_BGC_GREEN;
+
173  uint32_t DMA2D_BGC_RED;
+
176  uint32_t DMA2D_BGCMAR;
+
178 } DMA2D_BG_InitTypeDef;
+
179 
+
180 
+
181 
+
182 /* Exported constants --------------------------------------------------------*/
+
183 
+
193 #define DMA2D_M2M ((uint32_t)0x00000000)
+
194 #define DMA2D_M2M_PFC ((uint32_t)0x00010000)
+
195 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000)
+
196 #define DMA2D_R2M ((uint32_t)0x00030000)
+
197 
+
198 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
+
199  ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+
200 
+
201 
+
209 #define DMA2D_ARGB8888 ((uint32_t)0x00000000)
+
210 #define DMA2D_RGB888 ((uint32_t)0x00000001)
+
211 #define DMA2D_RGB565 ((uint32_t)0x00000002)
+
212 #define DMA2D_ARGB1555 ((uint32_t)0x00000003)
+
213 #define DMA2D_ARGB4444 ((uint32_t)0x00000004)
+
214 
+
215 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
+
216  ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
+
217  ((MODE_ARGB) == DMA2D_ARGB4444))
+
218 
+
219 
+
227 #define DMA2D_Output_Color ((uint32_t)0x000000FF)
+
228 
+
229 #define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
+
230 #define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color)
+
231 #define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color)
+
232 #define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
+
233 
+
241 #define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF)
+
242 
+
243 #define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
+
244 
+
245 
+
254 #define DMA2D_pixel ((uint32_t)0x00003FFF)
+
255 #define DMA2D_Line ((uint32_t)0x0000FFFF)
+
256 
+
257 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line)
+
258 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
+
259 
+
260 
+
268 #define OFFSET ((uint32_t)0x00003FFF)
+
269 
+
270 #define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET)
+
271 
+
272 #define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET)
+
273 
+
283 #define CM_ARGB8888 ((uint32_t)0x00000000)
+
284 #define CM_RGB888 ((uint32_t)0x00000001)
+
285 #define CM_RGB565 ((uint32_t)0x00000002)
+
286 #define CM_ARGB1555 ((uint32_t)0x00000003)
+
287 #define CM_ARGB4444 ((uint32_t)0x00000004)
+
288 #define CM_L8 ((uint32_t)0x00000005)
+
289 #define CM_AL44 ((uint32_t)0x00000006)
+
290 #define CM_AL88 ((uint32_t)0x00000007)
+
291 #define CM_L4 ((uint32_t)0x00000008)
+
292 #define CM_A8 ((uint32_t)0x00000009)
+
293 #define CM_A4 ((uint32_t)0x0000000A)
+
294 
+
295 #define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
+
296  ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
+
297  ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
+
298  ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
+
299  ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
+
300  ((FGCM) == CM_A4))
+
301 
+
302 #define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
+
303  ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
+
304  ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
+
305  ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
+
306  ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
+
307  ((BGCM) == CM_A4))
+
308 
+
317 #define CLUT_CM_ARGB8888 ((uint32_t)0x00000000)
+
318 #define CLUT_CM_RGB888 ((uint32_t)0x00000001)
+
319 
+
320 #define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
+
321 
+
322 #define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
+
323 
+
332 #define COLOR_VALUE ((uint32_t)0x000000FF)
+
333 
+
334 #define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
+
335 
+
336 #define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
+
337 #define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
+
338 #define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
+
339 #define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
+
340 
+
341 #define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
+
342 
+
343 #define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
+
344 #define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
+
345 #define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
+
346 #define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
+
347 
+
356 #define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000)
+
357 #define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001)
+
358 #define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002)
+
359 
+
360 #define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
+
361  ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+
362  ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
363 
+
364 #define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
+
365  ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
+
366  ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
+
367 
+
376 #define DMA2D_IT_CE DMA2D_CR_CEIE
+
377 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
+
378 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
+
379 #define DMA2D_IT_TW DMA2D_CR_TWIE
+
380 #define DMA2D_IT_TC DMA2D_CR_TCIE
+
381 #define DMA2D_IT_TE DMA2D_CR_TEIE
+
382 
+
383 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
+
384  ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
+
385  ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
+
386 
+
395 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
+
396 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
+
397 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
+
398 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
+
399 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
+
400 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
+
401 
+
402 
+
403 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
+
404  ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
+
405  ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
+
406 
+
407 
+
416 #define DEADTIME ((uint32_t)0x000000FF)
+
417 
+
418 #define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
+
419 
+
420 
+
421 #define LINE_WATERMARK DMA2D_LWR_LW
+
422 
+
423 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
+
424 
+
433 /* Exported macro ------------------------------------------------------------*/
+
434 /* Exported functions ------------------------------------------------------- */
+
435 
+
436 /* Function used to set the DMA2D configuration to the default reset state *****/
+
437 void DMA2D_DeInit(void);
+
438 
+
439 /* Initialization and Configuration functions *********************************/
+
440 void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
+
441 void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
+
442 void DMA2D_StartTransfer(void);
+
443 void DMA2D_AbortTransfer(void);
+
444 void DMA2D_Suspend(FunctionalState NewState);
+
445 void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
+
446 void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
+
447 void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
+
448 void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
+
449 void DMA2D_FGStart(FunctionalState NewState);
+
450 void DMA2D_BGStart(FunctionalState NewState);
+
451 void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
+
452 void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
+
453 
+
454 /* Interrupts and flags management functions **********************************/
+
455 void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
+
456 FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
+
457 void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
+
458 ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
+
459 void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
+
460 
+
461 #ifdef __cplusplus
+
462 }
+
463 #endif
+
464 
+
465 #endif /* __STM32F4xx_DMA2D_H */
+
466 
+
475 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
DMA2D_FG_InitTypeDef::DMA2D_FG_CLUT_CM
uint32_t DMA2D_FG_CLUT_CM
Definition: stm32f4xx_dma2d.h:118
+
DMA2D_BGConfig
void DMA2D_BGConfig(DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
Configures the Background according to the specified parameters in the DMA2D_BGStruct.
Definition: stm32f4xx_dma2d.c:395
+
DMA2D_FG_InitTypeDef
Definition: stm32f4xx_dma2d.h:107
+
DMA2D_ClearITPendingBit
void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT)
Clears the DMA2D's interrupt pending bits.
Definition: stm32f4xx_dma2d.c:758
+
DMA2D_InitTypeDef::DMA2D_OutputMemoryAdd
uint32_t DMA2D_OutputMemoryAdd
Definition: stm32f4xx_dma2d.h:92
+
DMA2D_FG_InitTypeDef::DMA2D_FGC_RED
uint32_t DMA2D_FGC_RED
Definition: stm32f4xx_dma2d.h:136
+
DMA2D_LineWatermarkConfig
void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig)
Define the configuration of the line watermark .
Definition: stm32f4xx_dma2d.c:565
+
DMA2D_BG_InitTypeDef
Definition: stm32f4xx_dma2d.h:144
+
DMA2D_InitTypeDef::DMA2D_OutputRed
uint32_t DMA2D_OutputRed
Definition: stm32f4xx_dma2d.h:78
+
DMA2D_FG_InitTypeDef::DMA2D_FGMA
uint32_t DMA2D_FGMA
Definition: stm32f4xx_dma2d.h:109
+
DMA2D_Suspend
void DMA2D_Suspend(FunctionalState NewState)
Stop or continue the DMA2D transfer.
Definition: stm32f4xx_dma2d.c:273
+
DMA2D_BG_InitTypeDef::DMA2D_BGCMAR
uint32_t DMA2D_BGCMAR
Definition: stm32f4xx_dma2d.h:176
+
DMA2D_FG_InitTypeDef::DMA2D_FGC_GREEN
uint32_t DMA2D_FGC_GREEN
Definition: stm32f4xx_dma2d.h:133
+
DMA2D_BG_InitTypeDef::DMA2D_BGC_RED
uint32_t DMA2D_BGC_RED
Definition: stm32f4xx_dma2d.h:173
+
DMA2D_FGStart
void DMA2D_FGStart(FunctionalState NewState)
Start the automatic loading of the CLUT or abort the transfer.
Definition: stm32f4xx_dma2d.c:491
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
DMA2D_Init
void DMA2D_Init(DMA2D_InitTypeDef *DMA2D_InitStruct)
Initializes the DMA2D peripheral according to the specified parameters in the DMA2D_InitStruct.
Definition: stm32f4xx_dma2d.c:128
+
DMA2D_FGConfig
void DMA2D_FGConfig(DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
Configures the Foreground according to the specified parameters in the DMA2D_FGStruct.
Definition: stm32f4xx_dma2d.c:298
+
DMA2D_BG_InitTypeDef::DMA2D_BGCM
uint32_t DMA2D_BGCM
Definition: stm32f4xx_dma2d.h:152
+
DMA2D_InitTypeDef
DMA2D Init structure definition.
Definition: stm32f4xx_dma2d.h:54
+
DMA2D_InitTypeDef::DMA2D_Mode
uint32_t DMA2D_Mode
Definition: stm32f4xx_dma2d.h:56
+
DMA2D_FG_InitTypeDef::DMA2D_FGPFC_ALPHA_MODE
uint32_t DMA2D_FGPFC_ALPHA_MODE
Definition: stm32f4xx_dma2d.h:124
+
DMA2D_ClearFlag
void DMA2D_ClearFlag(uint32_t DMA2D_FLAG)
Clears the DMA2D's pending flags.
Definition: stm32f4xx_dma2d.c:697
+
DMA2D_BG_InitTypeDef::DMA2D_BGC_GREEN
uint32_t DMA2D_BGC_GREEN
Definition: stm32f4xx_dma2d.h:170
+
DMA2D_FG_InitTypeDef::DMA2D_FGC_BLUE
uint32_t DMA2D_FGC_BLUE
Definition: stm32f4xx_dma2d.h:130
+
DMA2D_FG_InitTypeDef::DMA2D_FGPFC_ALPHA_VALUE
uint32_t DMA2D_FGPFC_ALPHA_VALUE
Definition: stm32f4xx_dma2d.h:127
+
DMA2D_BG_InitTypeDef::DMA2D_BGPFC_ALPHA_MODE
uint32_t DMA2D_BGPFC_ALPHA_MODE
Definition: stm32f4xx_dma2d.h:161
+
DMA2D_FG_InitTypeDef::DMA2D_FGCM
uint32_t DMA2D_FGCM
Definition: stm32f4xx_dma2d.h:115
+
DMA2D_InitTypeDef::DMA2D_OutputOffset
uint32_t DMA2D_OutputOffset
Definition: stm32f4xx_dma2d.h:95
+
DMA2D_AbortTransfer
void DMA2D_AbortTransfer(void)
Aboart the DMA2D transfer.
Definition: stm32f4xx_dma2d.c:260
+
DMA2D_ITConfig
void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState)
Enables or disables the specified DMA2D's interrupts.
Definition: stm32f4xx_dma2d.c:632
+
DMA2D_InitTypeDef::DMA2D_PixelPerLine
uint32_t DMA2D_PixelPerLine
Definition: stm32f4xx_dma2d.h:101
+
DMA2D_StartTransfer
void DMA2D_StartTransfer(void)
Start the DMA2D transfer.
Definition: stm32f4xx_dma2d.c:248
+
DMA2D_BGStart
void DMA2D_BGStart(FunctionalState NewState)
Start the automatic loading of the CLUT or abort the transfer.
Definition: stm32f4xx_dma2d.c:515
+
DMA2D_FG_InitTypeDef::DMA2D_FGCMAR
uint32_t DMA2D_FGCMAR
Definition: stm32f4xx_dma2d.h:139
+
DMA2D_InitTypeDef::DMA2D_CMode
uint32_t DMA2D_CMode
Definition: stm32f4xx_dma2d.h:59
+
DMA2D_BG_InitTypeDef::DMA2D_BG_CLUT_SIZE
uint32_t DMA2D_BG_CLUT_SIZE
Definition: stm32f4xx_dma2d.h:158
+
DMA2D_BG_InitTypeDef::DMA2D_BGPFC_ALPHA_VALUE
uint32_t DMA2D_BGPFC_ALPHA_VALUE
Definition: stm32f4xx_dma2d.h:164
+
DMA2D_FG_InitTypeDef::DMA2D_FGO
uint32_t DMA2D_FGO
Definition: stm32f4xx_dma2d.h:112
+
DMA2D_InitTypeDef::DMA2D_OutputAlpha
uint32_t DMA2D_OutputAlpha
Definition: stm32f4xx_dma2d.h:86
+
DMA2D_BG_StructInit
void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef *DMA2D_BG_InitStruct)
Fills each DMA2D_BGStruct member with its default value.
Definition: stm32f4xx_dma2d.c:448
+
DMA2D_FG_InitTypeDef::DMA2D_FG_CLUT_SIZE
uint32_t DMA2D_FG_CLUT_SIZE
Definition: stm32f4xx_dma2d.h:121
+
DMA2D_BG_InitTypeDef::DMA2D_BG_CLUT_CM
uint32_t DMA2D_BG_CLUT_CM
Definition: stm32f4xx_dma2d.h:155
+
DMA2D_BG_InitTypeDef::DMA2D_BGC_BLUE
uint32_t DMA2D_BGC_BLUE
Definition: stm32f4xx_dma2d.h:167
+
DMA2D_BG_InitTypeDef::DMA2D_BGMA
uint32_t DMA2D_BGMA
Definition: stm32f4xx_dma2d.h:146
+
DMA2D_FG_StructInit
void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef *DMA2D_FG_InitStruct)
Fills each DMA2D_FGStruct member with its default value.
Definition: stm32f4xx_dma2d.c:350
+
DMA2D_GetFlagStatus
FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG)
Checks whether the specified DMA2D's flag is set or not.
Definition: stm32f4xx_dma2d.c:663
+
DMA2D_InitTypeDef::DMA2D_OutputGreen
uint32_t DMA2D_OutputGreen
Definition: stm32f4xx_dma2d.h:70
+
DMA2D_DeInit
void DMA2D_DeInit(void)
Deinitializes the DMA2D peripheral registers to their default reset values.
Definition: stm32f4xx_dma2d.c:111
+
DMA2D_BG_InitTypeDef::DMA2D_BGO
uint32_t DMA2D_BGO
Definition: stm32f4xx_dma2d.h:149
+
DMA2D_InitTypeDef::DMA2D_OutputBlue
uint32_t DMA2D_OutputBlue
Definition: stm32f4xx_dma2d.h:62
+
DMA2D_DeadTimeConfig
void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState)
Configures the DMA2D dead time.
Definition: stm32f4xx_dma2d.c:538
+
DMA2D_InitTypeDef::DMA2D_NumberOfLine
uint32_t DMA2D_NumberOfLine
Definition: stm32f4xx_dma2d.h:98
+
DMA2D_GetITStatus
ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT)
Checks whether the specified DMA2D's interrupt has occurred or not.
Definition: stm32f4xx_dma2d.c:718
+
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+Macros | +Functions
+
+
stm32f4xx_dma.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA): +More...

+
#include "stm32f4xx_dma.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_dma.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define TRANSFER_IT_ENABLE_MASK
 
#define DMA_Stream0_IT_MASK
 
+#define DMA_Stream1_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 6)
 
+#define DMA_Stream2_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 16)
 
+#define DMA_Stream3_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK << 22)
 
+#define DMA_Stream4_IT_MASK   (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream5_IT_MASK   (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream6_IT_MASK   (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
 
+#define DMA_Stream7_IT_MASK   (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
 
+#define TRANSFER_IT_MASK   (uint32_t)0x0F3C0F3C
 
+#define HIGH_ISR_MASK   (uint32_t)0x20000000
 
+#define RESERVED_MASK   (uint32_t)0x0F7D0F7D
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA_DeInit (DMA_Stream_TypeDef *DMAy_Streamx)
 Deinitialize the DMAy Streamx registers to their default reset values. More...
 
void DMA_Init (DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
 Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure. More...
 
void DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
 Fills each DMA_InitStruct member with its default value. More...
 
void DMA_Cmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx. More...
 
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
 Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses). More...
 
void DMA_FlowControllerConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
 Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory). More...
 
void DMA_SetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
 Writes the number of data units to be transferred on the DMAy Streamx. More...
 
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the number of remaining data units in the current DMAy Streamx transfer. More...
 
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
 Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target. More...
 
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the double buffer mode for the selected DMA stream. More...
 
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
 Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing. More...
 
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current memory target used by double buffer transfer. More...
 
FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the status of EN bit for the specified DMAy Streamx. More...
 
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current DMAy Streamx FIFO filled level. More...
 
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Checks whether the specified DMAy Streamx flag is set or not. More...
 
void DMA_ClearFlag (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Clears the DMAy Streamx's pending flags. More...
 
void DMA_ITConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx interrupts. More...
 
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Checks whether the specified DMAy Streamx interrupt has occurred or not. More...
 
void DMA_ClearITPendingBit (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Clears the DMAy Streamx's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Direct Memory Access controller (DMA):

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Data Counter
    • +
  • Double Buffer mode configuration and command
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================      
+                      ##### How to use this driver #####
+===============================================================================
+   [..] 
+     (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
+         function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
+         function for DMA2.
+ 
+     (#) Enable and configure the peripheral to be connected to the DMA Stream
+         (except for internal SRAM / FLASH memories: no initialization is 
+         necessary). 
+         
+     (#) For a given Stream, program the required configuration through following parameters:   
+         Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination 
+         data formats, Circular or Normal mode, Stream Priority level, Source and Destination 
+         Incrementation mode, FIFO mode and its Threshold (if needed), Burst 
+         mode for Source and/or Destination (if needed) using the DMA_Init() function.
+         To avoid filling unneccessary fields, you can call DMA_StructInit() function
+         to initialize a given structure with default values (reset values), the modify
+         only necessary fields 
+         (ie. Source and Destination addresses, Transfer size and Data Formats).
+ 
+     (#) Enable the NVIC and the corresponding interrupt(s) using the function 
+         DMA_ITConfig() if you need to use DMA interrupts. 
+ 
+     (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring 
+         the second Memory address and the first Memory to be used through the function 
+         DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
+         DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
+     
+     (#) Enable the DMA stream using the DMA_Cmd() function. 
+                 
+     (#) Activate the needed Stream Request using PPP_DMACmd() function for
+         any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+         The function allowing this operation is provided in each PPP peripheral
+         driver (ie. SPI_DMACmd for SPI peripheral).
+         Once the Stream is enabled, it is not possible to modify its configuration
+         unless the stream is stopped and disabled.
+         After enabling the Stream, it is advised to monitor the EN bit status using
+         the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
+         this bit will remain reset and all transfers on this Stream will remain on hold.      
+ 
+     (#) Optionally, you can configure the number of data to be transferred
+         when the Stream is disabled (ie. after each Transfer Complete event
+         or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+         And you can get the number of remaining data to be transferred using 
+         the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
+         enabled and running).  
+                    
+     (#) To control DMA events you can use one of the following two methods:
+       (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().  
+       (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+            phase and DMA_GetITStatus() function into interrupt routines in
+            communication phase.
+   [..]     
+         After checking on a flag you should clear it using DMA_ClearFlag()
+         function. And after checking on an interrupt event you should 
+         clear it using DMA_ClearITPendingBit() function.    
+               
+     (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
+         the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
+         the Memory Address to be modified is not the one currently in use by DMA Stream.
+         This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
+               
+     (#) Optionally, Pause-Resume operations may be performed:
+         The DMA_Cmd() function may be used to perform Pause-Resume operation. 
+         When a transfer is ongoing, calling this function to disable the 
+         Stream will cause the transfer to be paused. All configuration registers 
+         and the number of remaining data will be preserved. When calling again 
+         this function to re-enable the Stream, the transfer will be resumed from 
+         the point where it was paused.          
+                  
+     -@- Memory-to-Memory transfer is possible by setting the address of the memory into
+          the Peripheral registers. In this mode, Circular mode and Double Buffer mode
+          are not allowed.
+   
+     -@- The FIFO is used mainly to reduce bus usage and to allow data 
+          packing/unpacking: it is possible to set different Data Sizes for 
+          the Peripheral and the Memory (ie. you can set Half-Word data size 
+          for the peripheral to access its data register and set Word data size
+          for the Memory to gain in access time. Each two Half-words will be 
+          packed and written in a single access to a Word in the Memory).
+     
+     -@- When FIFO is disabled, it is not allowed to configure different 
+          Data Sizes for Source and Destination. In this case the Peripheral 
+          Data Size will be applied to both Source and Destination.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
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+ + diff --git a/stm32f4xx__dma_8c__incl.map b/stm32f4xx__dma_8c__incl.map new file mode 100644 index 0000000..608d30d --- /dev/null +++ b/stm32f4xx__dma_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dma_8c__incl.md5 b/stm32f4xx__dma_8c__incl.md5 new file mode 100644 index 0000000..4ed6f9e --- /dev/null +++ b/stm32f4xx__dma_8c__incl.md5 @@ -0,0 +1 @@ +939ab6b611fa523495909a0728c745ca \ No newline at end of file diff --git a/stm32f4xx__dma_8c__incl.png b/stm32f4xx__dma_8c__incl.png new file mode 100644 index 0000000..22c9c79 Binary files /dev/null and b/stm32f4xx__dma_8c__incl.png differ diff --git a/stm32f4xx__dma_8h.html b/stm32f4xx__dma_8h.html new file mode 100644 index 0000000..e9b9d9b --- /dev/null +++ b/stm32f4xx__dma_8h.html @@ -0,0 +1,669 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dma.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_dma.h File Reference
+
+
+ +

This file contains all the functions prototypes for the DMA firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_dma.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + +

+Classes

struct  DMA_InitTypeDef
 DMA Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_DMA_ALL_PERIPH(PERIPH)
 
#define IS_DMA_ALL_CONTROLLER(CONTROLLER)
 
+#define DMA_Channel_0   ((uint32_t)0x00000000)
 
+#define DMA_Channel_1   ((uint32_t)0x02000000)
 
+#define DMA_Channel_2   ((uint32_t)0x04000000)
 
+#define DMA_Channel_3   ((uint32_t)0x06000000)
 
+#define DMA_Channel_4   ((uint32_t)0x08000000)
 
+#define DMA_Channel_5   ((uint32_t)0x0A000000)
 
+#define DMA_Channel_6   ((uint32_t)0x0C000000)
 
+#define DMA_Channel_7   ((uint32_t)0x0E000000)
 
#define IS_DMA_CHANNEL(CHANNEL)
 
+#define DMA_DIR_PeripheralToMemory   ((uint32_t)0x00000000)
 
+#define DMA_DIR_MemoryToPeripheral   ((uint32_t)0x00000040)
 
+#define DMA_DIR_MemoryToMemory   ((uint32_t)0x00000080)
 
#define IS_DMA_DIRECTION(DIRECTION)
 
+#define IS_DMA_BUFFER_SIZE(SIZE)   (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 
+#define DMA_PeripheralInc_Enable   ((uint32_t)0x00000200)
 
+#define DMA_PeripheralInc_Disable   ((uint32_t)0x00000000)
 
#define IS_DMA_PERIPHERAL_INC_STATE(STATE)
 
+#define DMA_MemoryInc_Enable   ((uint32_t)0x00000400)
 
+#define DMA_MemoryInc_Disable   ((uint32_t)0x00000000)
 
#define IS_DMA_MEMORY_INC_STATE(STATE)
 
+#define DMA_PeripheralDataSize_Byte   ((uint32_t)0x00000000)
 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800)
 
+#define DMA_PeripheralDataSize_Word   ((uint32_t)0x00001000)
 
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
 
+#define DMA_MemoryDataSize_Byte   ((uint32_t)0x00000000)
 
+#define DMA_MemoryDataSize_HalfWord   ((uint32_t)0x00002000)
 
+#define DMA_MemoryDataSize_Word   ((uint32_t)0x00004000)
 
#define IS_DMA_MEMORY_DATA_SIZE(SIZE)
 
+#define DMA_Mode_Normal   ((uint32_t)0x00000000)
 
+#define DMA_Mode_Circular   ((uint32_t)0x00000100)
 
#define IS_DMA_MODE(MODE)
 
+#define DMA_Priority_Low   ((uint32_t)0x00000000)
 
+#define DMA_Priority_Medium   ((uint32_t)0x00010000)
 
+#define DMA_Priority_High   ((uint32_t)0x00020000)
 
+#define DMA_Priority_VeryHigh   ((uint32_t)0x00030000)
 
#define IS_DMA_PRIORITY(PRIORITY)
 
+#define DMA_FIFOMode_Disable   ((uint32_t)0x00000000)
 
+#define DMA_FIFOMode_Enable   ((uint32_t)0x00000004)
 
#define IS_DMA_FIFO_MODE_STATE(STATE)
 
+#define DMA_FIFOThreshold_1QuarterFull   ((uint32_t)0x00000000)
 
+#define DMA_FIFOThreshold_HalfFull   ((uint32_t)0x00000001)
 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
 
+#define DMA_FIFOThreshold_Full   ((uint32_t)0x00000003)
 
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD)
 
+#define DMA_MemoryBurst_Single   ((uint32_t)0x00000000)
 
+#define DMA_MemoryBurst_INC4   ((uint32_t)0x00800000)
 
+#define DMA_MemoryBurst_INC8   ((uint32_t)0x01000000)
 
+#define DMA_MemoryBurst_INC16   ((uint32_t)0x01800000)
 
#define IS_DMA_MEMORY_BURST(BURST)
 
+#define DMA_PeripheralBurst_Single   ((uint32_t)0x00000000)
 
+#define DMA_PeripheralBurst_INC4   ((uint32_t)0x00200000)
 
+#define DMA_PeripheralBurst_INC8   ((uint32_t)0x00400000)
 
+#define DMA_PeripheralBurst_INC16   ((uint32_t)0x00600000)
 
#define IS_DMA_PERIPHERAL_BURST(BURST)
 
+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
 
+#define DMA_FIFOStatus_1QuarterFull   ((uint32_t)0x00000001 << 3)
 
+#define DMA_FIFOStatus_HalfFull   ((uint32_t)0x00000002 << 3)
 
+#define DMA_FIFOStatus_3QuartersFull   ((uint32_t)0x00000003 << 3)
 
+#define DMA_FIFOStatus_Empty   ((uint32_t)0x00000004 << 3)
 
+#define DMA_FIFOStatus_Full   ((uint32_t)0x00000005 << 3)
 
#define IS_DMA_FIFO_STATUS(STATUS)
 
+#define DMA_FLAG_FEIF0   ((uint32_t)0x10800001)
 
+#define DMA_FLAG_DMEIF0   ((uint32_t)0x10800004)
 
+#define DMA_FLAG_TEIF0   ((uint32_t)0x10000008)
 
+#define DMA_FLAG_HTIF0   ((uint32_t)0x10000010)
 
+#define DMA_FLAG_TCIF0   ((uint32_t)0x10000020)
 
+#define DMA_FLAG_FEIF1   ((uint32_t)0x10000040)
 
+#define DMA_FLAG_DMEIF1   ((uint32_t)0x10000100)
 
+#define DMA_FLAG_TEIF1   ((uint32_t)0x10000200)
 
+#define DMA_FLAG_HTIF1   ((uint32_t)0x10000400)
 
+#define DMA_FLAG_TCIF1   ((uint32_t)0x10000800)
 
+#define DMA_FLAG_FEIF2   ((uint32_t)0x10010000)
 
+#define DMA_FLAG_DMEIF2   ((uint32_t)0x10040000)
 
+#define DMA_FLAG_TEIF2   ((uint32_t)0x10080000)
 
+#define DMA_FLAG_HTIF2   ((uint32_t)0x10100000)
 
+#define DMA_FLAG_TCIF2   ((uint32_t)0x10200000)
 
+#define DMA_FLAG_FEIF3   ((uint32_t)0x10400000)
 
+#define DMA_FLAG_DMEIF3   ((uint32_t)0x11000000)
 
+#define DMA_FLAG_TEIF3   ((uint32_t)0x12000000)
 
+#define DMA_FLAG_HTIF3   ((uint32_t)0x14000000)
 
+#define DMA_FLAG_TCIF3   ((uint32_t)0x18000000)
 
+#define DMA_FLAG_FEIF4   ((uint32_t)0x20000001)
 
+#define DMA_FLAG_DMEIF4   ((uint32_t)0x20000004)
 
+#define DMA_FLAG_TEIF4   ((uint32_t)0x20000008)
 
+#define DMA_FLAG_HTIF4   ((uint32_t)0x20000010)
 
+#define DMA_FLAG_TCIF4   ((uint32_t)0x20000020)
 
+#define DMA_FLAG_FEIF5   ((uint32_t)0x20000040)
 
+#define DMA_FLAG_DMEIF5   ((uint32_t)0x20000100)
 
+#define DMA_FLAG_TEIF5   ((uint32_t)0x20000200)
 
+#define DMA_FLAG_HTIF5   ((uint32_t)0x20000400)
 
+#define DMA_FLAG_TCIF5   ((uint32_t)0x20000800)
 
+#define DMA_FLAG_FEIF6   ((uint32_t)0x20010000)
 
+#define DMA_FLAG_DMEIF6   ((uint32_t)0x20040000)
 
+#define DMA_FLAG_TEIF6   ((uint32_t)0x20080000)
 
+#define DMA_FLAG_HTIF6   ((uint32_t)0x20100000)
 
+#define DMA_FLAG_TCIF6   ((uint32_t)0x20200000)
 
+#define DMA_FLAG_FEIF7   ((uint32_t)0x20400000)
 
+#define DMA_FLAG_DMEIF7   ((uint32_t)0x21000000)
 
+#define DMA_FLAG_TEIF7   ((uint32_t)0x22000000)
 
+#define DMA_FLAG_HTIF7   ((uint32_t)0x24000000)
 
+#define DMA_FLAG_TCIF7   ((uint32_t)0x28000000)
 
#define IS_DMA_CLEAR_FLAG(FLAG)
 
#define IS_DMA_GET_FLAG(FLAG)
 
+#define DMA_IT_TC   ((uint32_t)0x00000010)
 
+#define DMA_IT_HT   ((uint32_t)0x00000008)
 
+#define DMA_IT_TE   ((uint32_t)0x00000004)
 
+#define DMA_IT_DME   ((uint32_t)0x00000002)
 
+#define DMA_IT_FE   ((uint32_t)0x00000080)
 
+#define IS_DMA_CONFIG_IT(IT)   ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
 
+#define DMA_IT_FEIF0   ((uint32_t)0x90000001)
 
+#define DMA_IT_DMEIF0   ((uint32_t)0x10001004)
 
+#define DMA_IT_TEIF0   ((uint32_t)0x10002008)
 
+#define DMA_IT_HTIF0   ((uint32_t)0x10004010)
 
+#define DMA_IT_TCIF0   ((uint32_t)0x10008020)
 
+#define DMA_IT_FEIF1   ((uint32_t)0x90000040)
 
+#define DMA_IT_DMEIF1   ((uint32_t)0x10001100)
 
+#define DMA_IT_TEIF1   ((uint32_t)0x10002200)
 
+#define DMA_IT_HTIF1   ((uint32_t)0x10004400)
 
+#define DMA_IT_TCIF1   ((uint32_t)0x10008800)
 
+#define DMA_IT_FEIF2   ((uint32_t)0x90010000)
 
+#define DMA_IT_DMEIF2   ((uint32_t)0x10041000)
 
+#define DMA_IT_TEIF2   ((uint32_t)0x10082000)
 
+#define DMA_IT_HTIF2   ((uint32_t)0x10104000)
 
+#define DMA_IT_TCIF2   ((uint32_t)0x10208000)
 
+#define DMA_IT_FEIF3   ((uint32_t)0x90400000)
 
+#define DMA_IT_DMEIF3   ((uint32_t)0x11001000)
 
+#define DMA_IT_TEIF3   ((uint32_t)0x12002000)
 
+#define DMA_IT_HTIF3   ((uint32_t)0x14004000)
 
+#define DMA_IT_TCIF3   ((uint32_t)0x18008000)
 
+#define DMA_IT_FEIF4   ((uint32_t)0xA0000001)
 
+#define DMA_IT_DMEIF4   ((uint32_t)0x20001004)
 
+#define DMA_IT_TEIF4   ((uint32_t)0x20002008)
 
+#define DMA_IT_HTIF4   ((uint32_t)0x20004010)
 
+#define DMA_IT_TCIF4   ((uint32_t)0x20008020)
 
+#define DMA_IT_FEIF5   ((uint32_t)0xA0000040)
 
+#define DMA_IT_DMEIF5   ((uint32_t)0x20001100)
 
+#define DMA_IT_TEIF5   ((uint32_t)0x20002200)
 
+#define DMA_IT_HTIF5   ((uint32_t)0x20004400)
 
+#define DMA_IT_TCIF5   ((uint32_t)0x20008800)
 
+#define DMA_IT_FEIF6   ((uint32_t)0xA0010000)
 
+#define DMA_IT_DMEIF6   ((uint32_t)0x20041000)
 
+#define DMA_IT_TEIF6   ((uint32_t)0x20082000)
 
+#define DMA_IT_HTIF6   ((uint32_t)0x20104000)
 
+#define DMA_IT_TCIF6   ((uint32_t)0x20208000)
 
+#define DMA_IT_FEIF7   ((uint32_t)0xA0400000)
 
+#define DMA_IT_DMEIF7   ((uint32_t)0x21001000)
 
+#define DMA_IT_TEIF7   ((uint32_t)0x22002000)
 
+#define DMA_IT_HTIF7   ((uint32_t)0x24004000)
 
+#define DMA_IT_TCIF7   ((uint32_t)0x28008000)
 
#define IS_DMA_CLEAR_IT(IT)
 
#define IS_DMA_GET_IT(IT)
 
+#define DMA_PINCOS_Psize   ((uint32_t)0x00000000)
 
+#define DMA_PINCOS_WordAligned   ((uint32_t)0x00008000)
 
#define IS_DMA_PINCOS_SIZE(SIZE)
 
+#define DMA_FlowCtrl_Memory   ((uint32_t)0x00000000)
 
+#define DMA_FlowCtrl_Peripheral   ((uint32_t)0x00000020)
 
#define IS_DMA_FLOW_CTRL(CTRL)
 
+#define DMA_Memory_0   ((uint32_t)0x00000000)
 
+#define DMA_Memory_1   ((uint32_t)0x00080000)
 
+#define IS_DMA_CURRENT_MEM(MEM)   (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void DMA_DeInit (DMA_Stream_TypeDef *DMAy_Streamx)
 Deinitialize the DMAy Streamx registers to their default reset values. More...
 
void DMA_Init (DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
 Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure. More...
 
void DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct)
 Fills each DMA_InitStruct member with its default value. More...
 
void DMA_Cmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx. More...
 
void DMA_PeriphIncOffsetSizeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
 Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address should be incremented with the data size (configured with PSIZE bits) or by a fixed offset equal to 4 (32-bit aligned addresses). More...
 
void DMA_FlowControllerConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
 Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Peripheral or Memory). More...
 
void DMA_SetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
 Writes the number of data units to be transferred on the DMAy Streamx. More...
 
uint16_t DMA_GetCurrDataCounter (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the number of remaining data units in the current DMAy Streamx transfer. More...
 
void DMA_DoubleBufferModeConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
 Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target. More...
 
void DMA_DoubleBufferModeCmd (DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
 Enables or disables the double buffer mode for the selected DMA stream. More...
 
void DMA_MemoryTargetConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
 Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use). This function can be called when the DMA Stream is enabled and when the transfer is ongoing. More...
 
uint32_t DMA_GetCurrentMemoryTarget (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current memory target used by double buffer transfer. More...
 
FunctionalState DMA_GetCmdStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the status of EN bit for the specified DMAy Streamx. More...
 
uint32_t DMA_GetFIFOStatus (DMA_Stream_TypeDef *DMAy_Streamx)
 Returns the current DMAy Streamx FIFO filled level. More...
 
FlagStatus DMA_GetFlagStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Checks whether the specified DMAy Streamx flag is set or not. More...
 
void DMA_ClearFlag (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
 Clears the DMAy Streamx's pending flags. More...
 
void DMA_ITConfig (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
 Enables or disables the specified DMAy Streamx interrupts. More...
 
ITStatus DMA_GetITStatus (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Checks whether the specified DMAy Streamx interrupt has occurred or not. More...
 
void DMA_ClearITPendingBit (DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
 Clears the DMAy Streamx's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the DMA firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__dma_8h__dep__incl.map b/stm32f4xx__dma_8h__dep__incl.map new file mode 100644 index 0000000..2c79233 --- /dev/null +++ b/stm32f4xx__dma_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dma_8h__dep__incl.md5 b/stm32f4xx__dma_8h__dep__incl.md5 new file mode 100644 index 0000000..1aafde9 --- /dev/null +++ b/stm32f4xx__dma_8h__dep__incl.md5 @@ -0,0 +1 @@ +b3ece615eb39f710bd6f2e0aedeff9d7 \ No newline at end of file diff --git a/stm32f4xx__dma_8h__dep__incl.png b/stm32f4xx__dma_8h__dep__incl.png new file mode 100644 index 0000000..bb2d967 Binary files /dev/null and b/stm32f4xx__dma_8h__dep__incl.png differ diff --git a/stm32f4xx__dma_8h__incl.map b/stm32f4xx__dma_8h__incl.map new file mode 100644 index 0000000..a0bb7d9 --- /dev/null +++ b/stm32f4xx__dma_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__dma_8h__incl.md5 b/stm32f4xx__dma_8h__incl.md5 new file mode 100644 index 0000000..1a79258 --- /dev/null +++ b/stm32f4xx__dma_8h__incl.md5 @@ -0,0 +1 @@ +d4c1350b4279f88a0358cc219804aa38 \ No newline at end of file diff --git a/stm32f4xx__dma_8h__incl.png b/stm32f4xx__dma_8h__incl.png new file mode 100644 index 0000000..b1f1533 Binary files /dev/null and b/stm32f4xx__dma_8h__incl.png differ diff --git a/stm32f4xx__dma_8h_source.html b/stm32f4xx__dma_8h_source.html new file mode 100644 index 0000000..0d37c95 --- /dev/null +++ b/stm32f4xx__dma_8h_source.html @@ -0,0 +1,514 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_dma.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx_dma.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_DMA_H
+
31 #define __STM32F4xx_DMA_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t DMA_Channel;
+
59  uint32_t DMA_PeripheralBaseAddr;
+
61  uint32_t DMA_Memory0BaseAddr;
+
65  uint32_t DMA_DIR;
+
69  uint32_t DMA_BufferSize;
+
73  uint32_t DMA_PeripheralInc;
+
76  uint32_t DMA_MemoryInc;
+
79  uint32_t DMA_PeripheralDataSize;
+
82  uint32_t DMA_MemoryDataSize;
+
85  uint32_t DMA_Mode;
+
90  uint32_t DMA_Priority;
+
93  uint32_t DMA_FIFOMode;
+
98  uint32_t DMA_FIFOThreshold;
+
101  uint32_t DMA_MemoryBurst;
+
106  uint32_t DMA_PeripheralBurst;
+
110 }DMA_InitTypeDef;
+
111 
+
112 /* Exported constants --------------------------------------------------------*/
+
113 
+
118 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
+
119  ((PERIPH) == DMA1_Stream1) || \
+
120  ((PERIPH) == DMA1_Stream2) || \
+
121  ((PERIPH) == DMA1_Stream3) || \
+
122  ((PERIPH) == DMA1_Stream4) || \
+
123  ((PERIPH) == DMA1_Stream5) || \
+
124  ((PERIPH) == DMA1_Stream6) || \
+
125  ((PERIPH) == DMA1_Stream7) || \
+
126  ((PERIPH) == DMA2_Stream0) || \
+
127  ((PERIPH) == DMA2_Stream1) || \
+
128  ((PERIPH) == DMA2_Stream2) || \
+
129  ((PERIPH) == DMA2_Stream3) || \
+
130  ((PERIPH) == DMA2_Stream4) || \
+
131  ((PERIPH) == DMA2_Stream5) || \
+
132  ((PERIPH) == DMA2_Stream6) || \
+
133  ((PERIPH) == DMA2_Stream7))
+
134 
+
135 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
+
136  ((CONTROLLER) == DMA2))
+
137 
+
141 #define DMA_Channel_0 ((uint32_t)0x00000000)
+
142 #define DMA_Channel_1 ((uint32_t)0x02000000)
+
143 #define DMA_Channel_2 ((uint32_t)0x04000000)
+
144 #define DMA_Channel_3 ((uint32_t)0x06000000)
+
145 #define DMA_Channel_4 ((uint32_t)0x08000000)
+
146 #define DMA_Channel_5 ((uint32_t)0x0A000000)
+
147 #define DMA_Channel_6 ((uint32_t)0x0C000000)
+
148 #define DMA_Channel_7 ((uint32_t)0x0E000000)
+
149 
+
150 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
+
151  ((CHANNEL) == DMA_Channel_1) || \
+
152  ((CHANNEL) == DMA_Channel_2) || \
+
153  ((CHANNEL) == DMA_Channel_3) || \
+
154  ((CHANNEL) == DMA_Channel_4) || \
+
155  ((CHANNEL) == DMA_Channel_5) || \
+
156  ((CHANNEL) == DMA_Channel_6) || \
+
157  ((CHANNEL) == DMA_Channel_7))
+
158 
+
166 #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
+
167 #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
+
168 #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
+
169 
+
170 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+
171  ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
+
172  ((DIRECTION) == DMA_DIR_MemoryToMemory))
+
173 
+
181 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
182 
+
190 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
+
191 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+
192 
+
193 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+
194  ((STATE) == DMA_PeripheralInc_Disable))
+
195 
+
203 #define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
+
204 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+
205 
+
206 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+
207  ((STATE) == DMA_MemoryInc_Disable))
+
208 
+
216 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+
217 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
+
218 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
+
219 
+
220 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+
221  ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+
222  ((SIZE) == DMA_PeripheralDataSize_Word))
+
223 
+
231 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+
232 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
+
233 #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
+
234 
+
235 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+
236  ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+
237  ((SIZE) == DMA_MemoryDataSize_Word ))
+
238 
+
246 #define DMA_Mode_Normal ((uint32_t)0x00000000)
+
247 #define DMA_Mode_Circular ((uint32_t)0x00000100)
+
248 
+
249 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
+
250  ((MODE) == DMA_Mode_Circular))
+
251 
+
259 #define DMA_Priority_Low ((uint32_t)0x00000000)
+
260 #define DMA_Priority_Medium ((uint32_t)0x00010000)
+
261 #define DMA_Priority_High ((uint32_t)0x00020000)
+
262 #define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
+
263 
+
264 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
+
265  ((PRIORITY) == DMA_Priority_Medium) || \
+
266  ((PRIORITY) == DMA_Priority_High) || \
+
267  ((PRIORITY) == DMA_Priority_VeryHigh))
+
268 
+
276 #define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
+
277 #define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
+
278 
+
279 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
+
280  ((STATE) == DMA_FIFOMode_Enable))
+
281 
+
289 #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
+
290 #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
+
291 #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
+
292 #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
+
293 
+
294 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+
295  ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
+
296  ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+
297  ((THRESHOLD) == DMA_FIFOThreshold_Full))
+
298 
+
306 #define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
+
307 #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
+
308 #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
+
309 #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
+
310 
+
311 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
+
312  ((BURST) == DMA_MemoryBurst_INC4) || \
+
313  ((BURST) == DMA_MemoryBurst_INC8) || \
+
314  ((BURST) == DMA_MemoryBurst_INC16))
+
315 
+
323 #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
+
324 #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
+
325 #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
+
326 #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
+
327 
+
328 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
+
329  ((BURST) == DMA_PeripheralBurst_INC4) || \
+
330  ((BURST) == DMA_PeripheralBurst_INC8) || \
+
331  ((BURST) == DMA_PeripheralBurst_INC16))
+
332 
+
340 #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
+
341 #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
+
342 #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
+
343 #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
+
344 #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
+
345 #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
+
346 
+
347 #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+
348  ((STATUS) == DMA_FIFOStatus_HalfFull) || \
+
349  ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
+
350  ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
+
351  ((STATUS) == DMA_FIFOStatus_Full) || \
+
352  ((STATUS) == DMA_FIFOStatus_Empty))
+
353 
+
360 #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
+
361 #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
+
362 #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
+
363 #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
+
364 #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
+
365 #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
+
366 #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
+
367 #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
+
368 #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
+
369 #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
+
370 #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
+
371 #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
+
372 #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
+
373 #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
+
374 #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
+
375 #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
+
376 #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
+
377 #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
+
378 #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
+
379 #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
+
380 #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
+
381 #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
+
382 #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
+
383 #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
+
384 #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
+
385 #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
+
386 #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
+
387 #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
+
388 #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
+
389 #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
+
390 #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
+
391 #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
+
392 #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
+
393 #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
+
394 #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
+
395 #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
+
396 #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
+
397 #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
+
398 #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
+
399 #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
+
400 
+
401 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+
402  (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
+
403 
+
404 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
+
405  ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
+
406  ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
+
407  ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
+
408  ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
+
409  ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
+
410  ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
+
411  ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
+
412  ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
+
413  ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
+
414  ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
+
415  ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
+
416  ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
+
417  ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
+
418  ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
+
419  ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
+
420  ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
+
421  ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
+
422  ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
+
423  ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+
424 
+
432 #define DMA_IT_TC ((uint32_t)0x00000010)
+
433 #define DMA_IT_HT ((uint32_t)0x00000008)
+
434 #define DMA_IT_TE ((uint32_t)0x00000004)
+
435 #define DMA_IT_DME ((uint32_t)0x00000002)
+
436 #define DMA_IT_FE ((uint32_t)0x00000080)
+
437 
+
438 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
+
439 
+
447 #define DMA_IT_FEIF0 ((uint32_t)0x90000001)
+
448 #define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
+
449 #define DMA_IT_TEIF0 ((uint32_t)0x10002008)
+
450 #define DMA_IT_HTIF0 ((uint32_t)0x10004010)
+
451 #define DMA_IT_TCIF0 ((uint32_t)0x10008020)
+
452 #define DMA_IT_FEIF1 ((uint32_t)0x90000040)
+
453 #define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
+
454 #define DMA_IT_TEIF1 ((uint32_t)0x10002200)
+
455 #define DMA_IT_HTIF1 ((uint32_t)0x10004400)
+
456 #define DMA_IT_TCIF1 ((uint32_t)0x10008800)
+
457 #define DMA_IT_FEIF2 ((uint32_t)0x90010000)
+
458 #define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
+
459 #define DMA_IT_TEIF2 ((uint32_t)0x10082000)
+
460 #define DMA_IT_HTIF2 ((uint32_t)0x10104000)
+
461 #define DMA_IT_TCIF2 ((uint32_t)0x10208000)
+
462 #define DMA_IT_FEIF3 ((uint32_t)0x90400000)
+
463 #define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
+
464 #define DMA_IT_TEIF3 ((uint32_t)0x12002000)
+
465 #define DMA_IT_HTIF3 ((uint32_t)0x14004000)
+
466 #define DMA_IT_TCIF3 ((uint32_t)0x18008000)
+
467 #define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
+
468 #define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
+
469 #define DMA_IT_TEIF4 ((uint32_t)0x20002008)
+
470 #define DMA_IT_HTIF4 ((uint32_t)0x20004010)
+
471 #define DMA_IT_TCIF4 ((uint32_t)0x20008020)
+
472 #define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
+
473 #define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
+
474 #define DMA_IT_TEIF5 ((uint32_t)0x20002200)
+
475 #define DMA_IT_HTIF5 ((uint32_t)0x20004400)
+
476 #define DMA_IT_TCIF5 ((uint32_t)0x20008800)
+
477 #define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
+
478 #define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
+
479 #define DMA_IT_TEIF6 ((uint32_t)0x20082000)
+
480 #define DMA_IT_HTIF6 ((uint32_t)0x20104000)
+
481 #define DMA_IT_TCIF6 ((uint32_t)0x20208000)
+
482 #define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
+
483 #define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
+
484 #define DMA_IT_TEIF7 ((uint32_t)0x22002000)
+
485 #define DMA_IT_HTIF7 ((uint32_t)0x24004000)
+
486 #define DMA_IT_TCIF7 ((uint32_t)0x28008000)
+
487 
+
488 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
+
489  (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+
490  (((IT) & 0x40820082) == 0x00))
+
491 
+
492 #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
+
493  ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+
494  ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
+
495  ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
+
496  ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
+
497  ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
+
498  ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+
499  ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
+
500  ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
+
501  ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
+
502  ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
+
503  ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+
504  ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
+
505  ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
+
506  ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
+
507  ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
+
508  ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+
509  ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
+
510  ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
+
511  ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+
512 
+
520 #define DMA_PINCOS_Psize ((uint32_t)0x00000000)
+
521 #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
+
522 
+
523 #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
+
524  ((SIZE) == DMA_PINCOS_WordAligned))
+
525 
+
533 #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
+
534 #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
+
535 
+
536 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
+
537  ((CTRL) == DMA_FlowCtrl_Peripheral))
+
538 
+
546 #define DMA_Memory_0 ((uint32_t)0x00000000)
+
547 #define DMA_Memory_1 ((uint32_t)0x00080000)
+
548 
+
549 #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
+
550 
+
558 /* Exported macro ------------------------------------------------------------*/
+
559 /* Exported functions --------------------------------------------------------*/
+
560 
+
561 /* Function used to set the DMA configuration to the default reset state *****/
+
562 void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
+
563 
+
564 /* Initialization and Configuration functions *********************************/
+
565 void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
+
566 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+
567 void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+
568 
+
569 /* Optional Configuration functions *******************************************/
+
570 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
+
571 void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
+
572 
+
573 /* Data Counter functions *****************************************************/
+
574 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+
575 uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
+
576 
+
577 /* Double Buffer mode functions ***********************************************/
+
578 void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+
579  uint32_t DMA_CurrentMemory);
+
580 void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+
581 void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+
582  uint32_t DMA_MemoryTarget);
+
583 uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+
584 
+
585 /* Interrupts and flags management functions **********************************/
+
586 FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+
587 uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+
588 FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+
589 void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+
590 void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+
591 ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
592 void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
593 
+
594 #ifdef __cplusplus
+
595 }
+
596 #endif
+
597 
+
598 #endif /*__STM32F4xx_DMA_H */
+
599 
+
609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
DMA_FlowControllerConfig
void DMA_FlowControllerConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FlowCtrl)
Configures, when the DMAy Streamx is disabled, the flow controller for the next transactions (Periphe...
Definition: stm32f4xx_dma.c:550
+
DMA_InitTypeDef::DMA_PeripheralDataSize
uint32_t DMA_PeripheralDataSize
Definition: stm32f4xx_dma.h:79
+
DMA_InitTypeDef::DMA_MemoryInc
uint32_t DMA_MemoryInc
Definition: stm32f4xx_dma.h:76
+
DMA_PeriphIncOffsetSizeConfig
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_Pincos)
Configures, when the PINC (Peripheral Increment address mode) bit is set, if the peripheral address s...
Definition: stm32f4xx_dma.c:514
+
DMA_DeInit
void DMA_DeInit(DMA_Stream_TypeDef *DMAy_Streamx)
Deinitialize the DMAy Streamx registers to their default reset values.
Definition: stm32f4xx_dma.c:196
+
DMA_ClearFlag
void DMA_ClearFlag(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
Clears the DMAy Streamx's pending flags.
Definition: stm32f4xx_dma.c:1071
+
DMA_InitTypeDef::DMA_MemoryBurst
uint32_t DMA_MemoryBurst
Definition: stm32f4xx_dma.h:101
+
DMA_ITConfig
void DMA_ITConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
Enables or disables the specified DMAy Streamx interrupts.
Definition: stm32f4xx_dma.c:1118
+
DMA_DoubleBufferModeCmd
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
Enables or disables the double buffer mode for the selected DMA stream.
Definition: stm32f4xx_dma.c:761
+
DMA_MemoryTargetConfig
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget)
Configures the Memory address for the next buffer transfer in double buffer mode (for dynamic use)...
Definition: stm32f4xx_dma.c:802
+
DMA_GetCurrDataCounter
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the number of remaining data units in the current DMAy Streamx transfer.
Definition: stm32f4xx_dma.c:647
+
DMA_InitTypeDef::DMA_BufferSize
uint32_t DMA_BufferSize
Definition: stm32f4xx_dma.h:69
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
DMA_GetCmdStatus
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the status of EN bit for the specified DMAy Streamx.
Definition: stm32f4xx_dma.c:943
+
DMA_SetCurrDataCounter
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef *DMAy_Streamx, uint16_t Counter)
Writes the number of data units to be transferred on the DMAy Streamx.
Definition: stm32f4xx_dma.c:632
+
DMA_InitTypeDef
DMA Init structure definition.
Definition: stm32f4xx_dma.h:54
+
DMA_InitTypeDef::DMA_Memory0BaseAddr
uint32_t DMA_Memory0BaseAddr
Definition: stm32f4xx_dma.h:61
+
DMA_InitTypeDef::DMA_Channel
uint32_t DMA_Channel
Definition: stm32f4xx_dma.h:56
+
DMA_InitTypeDef::DMA_FIFOThreshold
uint32_t DMA_FIFOThreshold
Definition: stm32f4xx_dma.h:98
+
DMA_InitTypeDef::DMA_Mode
uint32_t DMA_Mode
Definition: stm32f4xx_dma.h:85
+
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f4xx.h:698
+
DMA_Cmd
void DMA_Cmd(DMA_Stream_TypeDef *DMAy_Streamx, FunctionalState NewState)
Enables or disables the specified DMAy Streamx.
Definition: stm32f4xx_dma.c:478
+
DMA_GetFIFOStatus
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the current DMAy Streamx FIFO filled level.
Definition: stm32f4xx_dma.c:977
+
DMA_StructInit
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
Fills each DMA_InitStruct member with its default value.
Definition: stm32f4xx_dma.c:403
+
DMA_InitTypeDef::DMA_PeripheralBaseAddr
uint32_t DMA_PeripheralBaseAddr
Definition: stm32f4xx_dma.h:59
+
DMA_Init
void DMA_Init(DMA_Stream_TypeDef *DMAy_Streamx, DMA_InitTypeDef *DMA_InitStruct)
Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure...
Definition: stm32f4xx_dma.c:319
+
DMA_DoubleBufferModeConfig
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory)
Configures, when the DMAy Streamx is disabled, the double buffer mode and the current memory target...
Definition: stm32f4xx_dma.c:730
+
DMA_InitTypeDef::DMA_MemoryDataSize
uint32_t DMA_MemoryDataSize
Definition: stm32f4xx_dma.h:82
+
DMA_GetCurrentMemoryTarget
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef *DMAy_Streamx)
Returns the current memory target used by double buffer transfer.
Definition: stm32f4xx_dma.c:828
+
DMA_InitTypeDef::DMA_DIR
uint32_t DMA_DIR
Definition: stm32f4xx_dma.h:65
+
DMA_InitTypeDef::DMA_FIFOMode
uint32_t DMA_FIFOMode
Definition: stm32f4xx_dma.h:93
+
DMA_InitTypeDef::DMA_Priority
uint32_t DMA_Priority
Definition: stm32f4xx_dma.h:90
+
DMA_GetFlagStatus
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_FLAG)
Checks whether the specified DMAy Streamx flag is set or not.
Definition: stm32f4xx_dma.c:1004
+
DMA_InitTypeDef::DMA_PeripheralBurst
uint32_t DMA_PeripheralBurst
Definition: stm32f4xx_dma.h:106
+
DMA_ClearITPendingBit
void DMA_ClearITPendingBit(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
Clears the DMAy Streamx's interrupt pending bits.
Definition: stm32f4xx_dma.c:1252
+
DMA_GetITStatus
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef *DMAy_Streamx, uint32_t DMA_IT)
Checks whether the specified DMAy Streamx interrupt has occurred or not.
Definition: stm32f4xx_dma.c:1170
+
DMA_InitTypeDef::DMA_PeripheralInc
uint32_t DMA_PeripheralInc
Definition: stm32f4xx_dma.h:73
+
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+Macros | +Functions
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stm32f4xx_exti.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the EXTI peripheral: +More...

+
#include "stm32f4xx_exti.h"
+
+Include dependency graph for stm32f4xx_exti.c:
+
+
+ + +
+
+ + + +

+Macros

+#define EXTI_LINENONE   ((uint32_t)0x00000) /* No interrupt selected */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void EXTI_DeInit (void)
 Deinitializes the EXTI peripheral registers to their default reset values. More...
 
void EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
 Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct. More...
 
void EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
 Fills each EXTI_InitStruct member with its reset value. More...
 
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
 Generates a Software interrupt on selected EXTI line. More...
 
FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line flag is set or not. More...
 
void EXTI_ClearFlag (uint32_t EXTI_Line)
 Clears the EXTI's line pending flags. More...
 
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line is asserted or not. More...
 
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
 Clears the EXTI's line pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the EXTI peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Interrupts and flags management
    • +
+
+
 ===============================================================================
+                              ##### EXTI features #####
+ ===============================================================================
+
+ [..] External interrupt/event lines are mapped as following:
+   (#) All available GPIO pins are connected to the 16 external 
+       interrupt/event lines from EXTI0 to EXTI15.
+   (#) EXTI line 16 is connected to the PVD Output
+   (#) EXTI line 17 is connected to the RTC Alarm event
+   (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
+   (#) EXTI line 19 is connected to the Ethernet Wakeup event
+   (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+   (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
+   (#) EXTI line 22 is connected to the RTC Wakeup event
+
+                       ##### How to use this driver #####
+ ===============================================================================
+ 
+ [..] In order to use an I/O pin as an external interrupt source, follow steps 
+      below:
+   (#) Configure the I/O in input mode using GPIO_Init()
+   (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
+   (#) Select the mode(interrupt, event) and configure the trigger 
+       selection (Rising, falling or both) using EXTI_Init()
+   (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+
+ [..]     
+   (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+       registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
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+Classes | +Macros | +Enumerations | +Functions
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+
stm32f4xx_exti.h File Reference
+
+
+ +

This file contains all the functions prototypes for the EXTI firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_exti.h:
+
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+
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Go to the source code of this file.

+ + + + + +

+Classes

struct  EXTI_InitTypeDef
 EXTI Init Structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define IS_EXTI_MODE(MODE)   (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
 
#define IS_EXTI_TRIGGER(TRIGGER)
 
#define EXTI_Line0   ((uint32_t)0x00001)
 
#define EXTI_Line1   ((uint32_t)0x00002)
 
#define EXTI_Line2   ((uint32_t)0x00004)
 
#define EXTI_Line3   ((uint32_t)0x00008)
 
#define EXTI_Line4   ((uint32_t)0x00010)
 
#define EXTI_Line5   ((uint32_t)0x00020)
 
#define EXTI_Line6   ((uint32_t)0x00040)
 
#define EXTI_Line7   ((uint32_t)0x00080)
 
#define EXTI_Line8   ((uint32_t)0x00100)
 
#define EXTI_Line9   ((uint32_t)0x00200)
 
#define EXTI_Line10   ((uint32_t)0x00400)
 
#define EXTI_Line11   ((uint32_t)0x00800)
 
#define EXTI_Line12   ((uint32_t)0x01000)
 
#define EXTI_Line13   ((uint32_t)0x02000)
 
#define EXTI_Line14   ((uint32_t)0x04000)
 
#define EXTI_Line15   ((uint32_t)0x08000)
 
#define EXTI_Line16   ((uint32_t)0x10000)
 
#define EXTI_Line17   ((uint32_t)0x20000)
 
#define EXTI_Line18   ((uint32_t)0x40000)
 
#define EXTI_Line19   ((uint32_t)0x80000)
 
#define EXTI_Line20   ((uint32_t)0x00100000)
 
#define EXTI_Line21   ((uint32_t)0x00200000)
 
#define EXTI_Line22   ((uint32_t)0x00400000)
 
+#define IS_EXTI_LINE(LINE)   ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
 
#define IS_GET_EXTI_LINE(LINE)
 
+ + + + + + + +

+Enumerations

enum  EXTIMode_TypeDef { EXTI_Mode_Interrupt = 0x00, +EXTI_Mode_Event = 0x04 + }
 EXTI mode enumeration.
 
enum  EXTITrigger_TypeDef { EXTI_Trigger_Rising = 0x08, +EXTI_Trigger_Falling = 0x0C, +EXTI_Trigger_Rising_Falling = 0x10 + }
 EXTI Trigger enumeration.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void EXTI_DeInit (void)
 Deinitializes the EXTI peripheral registers to their default reset values. More...
 
void EXTI_Init (EXTI_InitTypeDef *EXTI_InitStruct)
 Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct. More...
 
void EXTI_StructInit (EXTI_InitTypeDef *EXTI_InitStruct)
 Fills each EXTI_InitStruct member with its reset value. More...
 
void EXTI_GenerateSWInterrupt (uint32_t EXTI_Line)
 Generates a Software interrupt on selected EXTI line. More...
 
FlagStatus EXTI_GetFlagStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line flag is set or not. More...
 
void EXTI_ClearFlag (uint32_t EXTI_Line)
 Clears the EXTI's line pending flags. More...
 
ITStatus EXTI_GetITStatus (uint32_t EXTI_Line)
 Checks whether the specified EXTI line is asserted or not. More...
 
void EXTI_ClearITPendingBit (uint32_t EXTI_Line)
 Clears the EXTI's line pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the EXTI firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__exti_8h__dep__incl.map b/stm32f4xx__exti_8h__dep__incl.map new file mode 100644 index 0000000..6880f86 --- /dev/null +++ b/stm32f4xx__exti_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__exti_8h__dep__incl.md5 b/stm32f4xx__exti_8h__dep__incl.md5 new file mode 100644 index 0000000..5141f68 --- /dev/null +++ b/stm32f4xx__exti_8h__dep__incl.md5 @@ -0,0 +1 @@ +bbe83fda3479b18f68d3fe7de1be0c74 \ No newline at end of file diff --git a/stm32f4xx__exti_8h__dep__incl.png b/stm32f4xx__exti_8h__dep__incl.png new file mode 100644 index 0000000..584a1fa Binary files /dev/null and b/stm32f4xx__exti_8h__dep__incl.png differ diff --git a/stm32f4xx__exti_8h__incl.map b/stm32f4xx__exti_8h__incl.map new file mode 100644 index 0000000..f652a2f --- /dev/null +++ b/stm32f4xx__exti_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__exti_8h__incl.md5 b/stm32f4xx__exti_8h__incl.md5 new file mode 100644 index 0000000..e1389c8 --- /dev/null +++ b/stm32f4xx__exti_8h__incl.md5 @@ -0,0 +1 @@ +d7c942a08aab2425bfd51b39d971e297 \ No newline at end of file diff --git a/stm32f4xx__exti_8h__incl.png b/stm32f4xx__exti_8h__incl.png new file mode 100644 index 0000000..12dc2cd Binary files /dev/null and b/stm32f4xx__exti_8h__incl.png differ diff --git a/stm32f4xx__exti_8h_source.html b/stm32f4xx__exti_8h_source.html new file mode 100644 index 0000000..26bd360 --- /dev/null +++ b/stm32f4xx__exti_8h_source.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_exti.h Source File + + + + + + + + + + +
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stm32f4xx_exti.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_EXTI_H
+
31 #define __STM32F4xx_EXTI_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef enum
+
55 {
+
56  EXTI_Mode_Interrupt = 0x00,
+
57  EXTI_Mode_Event = 0x04
+
58 }EXTIMode_TypeDef;
+
59 
+
60 #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
61 
+
66 typedef enum
+
67 {
+
68  EXTI_Trigger_Rising = 0x08,
+
69  EXTI_Trigger_Falling = 0x0C,
+
70  EXTI_Trigger_Rising_Falling = 0x10
+
71 }EXTITrigger_TypeDef;
+
72 
+
73 #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+
74  ((TRIGGER) == EXTI_Trigger_Falling) || \
+
75  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+
76 
+
80 typedef struct
+
81 {
+
82  uint32_t EXTI_Line;
+
85  EXTIMode_TypeDef EXTI_Mode;
+
88  EXTITrigger_TypeDef EXTI_Trigger;
+
91  FunctionalState EXTI_LineCmd;
+
93 }EXTI_InitTypeDef;
+
94 
+
95 /* Exported constants --------------------------------------------------------*/
+
96 
+
105 #define EXTI_Line0 ((uint32_t)0x00001)
+
106 #define EXTI_Line1 ((uint32_t)0x00002)
+
107 #define EXTI_Line2 ((uint32_t)0x00004)
+
108 #define EXTI_Line3 ((uint32_t)0x00008)
+
109 #define EXTI_Line4 ((uint32_t)0x00010)
+
110 #define EXTI_Line5 ((uint32_t)0x00020)
+
111 #define EXTI_Line6 ((uint32_t)0x00040)
+
112 #define EXTI_Line7 ((uint32_t)0x00080)
+
113 #define EXTI_Line8 ((uint32_t)0x00100)
+
114 #define EXTI_Line9 ((uint32_t)0x00200)
+
115 #define EXTI_Line10 ((uint32_t)0x00400)
+
116 #define EXTI_Line11 ((uint32_t)0x00800)
+
117 #define EXTI_Line12 ((uint32_t)0x01000)
+
118 #define EXTI_Line13 ((uint32_t)0x02000)
+
119 #define EXTI_Line14 ((uint32_t)0x04000)
+
120 #define EXTI_Line15 ((uint32_t)0x08000)
+
121 #define EXTI_Line16 ((uint32_t)0x10000)
+
122 #define EXTI_Line17 ((uint32_t)0x20000)
+
123 #define EXTI_Line18 ((uint32_t)0x40000)
+
124 #define EXTI_Line19 ((uint32_t)0x80000)
+
125 #define EXTI_Line20 ((uint32_t)0x00100000)
+
126 #define EXTI_Line21 ((uint32_t)0x00200000)
+
127 #define EXTI_Line22 ((uint32_t)0x00400000)
+
129 #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
130 
+
131 #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+
132  ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+
133  ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+
134  ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+
135  ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+
136  ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+
137  ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+
138  ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+
139  ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+
140  ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+
141  ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
+
142  ((LINE) == EXTI_Line22))
+
143 
+
152 /* Exported macro ------------------------------------------------------------*/
+
153 /* Exported functions --------------------------------------------------------*/
+
154 
+
155 /* Function used to set the EXTI configuration to the default reset state *****/
+
156 void EXTI_DeInit(void);
+
157 
+
158 /* Initialization and Configuration functions *********************************/
+
159 void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+
160 void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+
161 void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
162 
+
163 /* Interrupts and flags management functions **********************************/
+
164 FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+
165 void EXTI_ClearFlag(uint32_t EXTI_Line);
+
166 ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+
167 void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
168 
+
169 #ifdef __cplusplus
+
170 }
+
171 #endif
+
172 
+
173 #endif /* __STM32F4xx_EXTI_H */
+
174 
+
183 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
EXTI_DeInit
void EXTI_DeInit(void)
Deinitializes the EXTI peripheral registers to their default reset values.
Definition: stm32f4xx_exti.c:109
+
EXTIMode_TypeDef
EXTIMode_TypeDef
EXTI mode enumeration.
Definition: stm32f4xx_exti.h:54
+
EXTITrigger_TypeDef
EXTITrigger_TypeDef
EXTI Trigger enumeration.
Definition: stm32f4xx_exti.h:66
+
EXTI_GetFlagStatus
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
Checks whether the specified EXTI line flag is set or not.
Definition: stm32f4xx_exti.c:226
+
EXTI_ClearFlag
void EXTI_ClearFlag(uint32_t EXTI_Line)
Clears the EXTI's line pending flags.
Definition: stm32f4xx_exti.c:249
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
EXTI_Init
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
Initializes the EXTI peripheral according to the specified parameters in the EXTI_InitStruct.
Definition: stm32f4xx_exti.c:125
+
EXTI_GetITStatus
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
Checks whether the specified EXTI line is asserted or not.
Definition: stm32f4xx_exti.c:263
+
EXTI_InitTypeDef
EXTI Init Structure definition.
Definition: stm32f4xx_exti.h:80
+
EXTI_ClearITPendingBit
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
Clears the EXTI's line pending bits.
Definition: stm32f4xx_exti.c:287
+
EXTI_InitTypeDef::EXTI_LineCmd
FunctionalState EXTI_LineCmd
Definition: stm32f4xx_exti.h:91
+
EXTI_InitTypeDef::EXTI_Line
uint32_t EXTI_Line
Definition: stm32f4xx_exti.h:82
+
EXTI_GenerateSWInterrupt
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
Generates a Software interrupt on selected EXTI line.
Definition: stm32f4xx_exti.c:196
+
EXTI_InitTypeDef::EXTI_Trigger
EXTITrigger_TypeDef EXTI_Trigger
Definition: stm32f4xx_exti.h:88
+
EXTI_StructInit
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
Fills each EXTI_InitStruct member with its reset value.
Definition: stm32f4xx_exti.c:181
+
EXTI_InitTypeDef::EXTI_Mode
EXTIMode_TypeDef EXTI_Mode
Definition: stm32f4xx_exti.h:85
+
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+ + diff --git a/stm32f4xx__flash_8c.html b/stm32f4xx__flash_8c.html new file mode 100644 index 0000000..19474ef --- /dev/null +++ b/stm32f4xx__flash_8c.html @@ -0,0 +1,295 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_flash.c File Reference + + + + + + + + + + +
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stm32f4xx_flash.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the FLASH peripheral: +More...

+
#include "stm32f4xx_flash.h"
+
+Include dependency graph for stm32f4xx_flash.c:
+
+
+ + +
+
+ + + +

+Macros

+#define SECTOR_MASK   ((uint32_t)0xFFFFFF07)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FLASH_SetLatency (uint32_t FLASH_Latency)
 Sets the code latency value. More...
 
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
 Enables or disables the Prefetch Buffer. More...
 
void FLASH_InstructionCacheCmd (FunctionalState NewState)
 Enables or disables the Instruction Cache feature. More...
 
void FLASH_DataCacheCmd (FunctionalState NewState)
 Enables or disables the Data Cache feature. More...
 
void FLASH_InstructionCacheReset (void)
 Resets the Instruction Cache. More...
 
void FLASH_DataCacheReset (void)
 Resets the Data Cache. More...
 
void FLASH_Unlock (void)
 Unlocks the FLASH control register access. More...
 
void FLASH_Lock (void)
 Locks the FLASH control register access. More...
 
FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector, uint8_t VoltageRange)
 Erases a specified FLASH Sector. More...
 
FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
 Erases all FLASH Sectors. More...
 
FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 1. More...
 
FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 2. More...
 
FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address, uint64_t Data)
 Programs a double word (64-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramWord (uint32_t Address, uint32_t Data)
 Programs a word (32-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
 Programs a half word (16-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramByte (uint32_t Address, uint8_t Data)
 Programs a byte (8-bit) at a specified address. More...
 
void FLASH_OB_Unlock (void)
 Unlocks the FLASH Option Control Registers access. More...
 
void FLASH_OB_Lock (void)
 Locks the FLASH Option Control Registers access. More...
 
void FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash. More...
 
void FLASH_OB_WRP1Config (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash. More...
 
void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
 Select the Protection Mode (SPRMOD). More...
 
void FLASH_OB_PCROPConfig (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash. More...
 
void FLASH_OB_PCROP1Config (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors. More...
 
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
 Sets the read protection level. More...
 
void FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. More...
 
void FLASH_OB_BootConfig (uint8_t OB_BOOT)
 Configure the Dual Bank Boot. More...
 
void FLASH_OB_BORConfig (uint8_t OB_BOR)
 Sets the BOR Level. More...
 
FLASH_Status FLASH_OB_Launch (void)
 Launch the option byte loading. More...
 
uint8_t FLASH_OB_GetUser (void)
 Returns the FLASH User Option Bytes values. More...
 
uint16_t FLASH_OB_GetWRP (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetWRP1 (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP1 (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
FlagStatus FLASH_OB_GetRDP (void)
 Returns the FLASH Read Protection level. More...
 
uint8_t FLASH_OB_GetBOR (void)
 Returns the FLASH BOR level. More...
 
void FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
 Enables or disables the specified FLASH interrupts. More...
 
FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
 Checks whether the specified FLASH flag is set or not. More...
 
void FLASH_ClearFlag (uint32_t FLASH_FLAG)
 Clears the FLASH's pending flags. More...
 
FLASH_Status FLASH_GetStatus (void)
 Returns the FLASH Status. More...
 
FLASH_Status FLASH_WaitForLastOperation (void)
 Waits for a FLASH operation to complete. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the FLASH peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • FLASH Interface configuration
    • +
  • FLASH Memory Programming
    • +
  • Option Bytes Programming
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                       ##### How to use this driver #####
+===============================================================================
+   [..]                             
+     This driver provides functions to configure and program the FLASH memory 
+     of all STM32F4xx devices. These functions are split in 4 groups:
+  
+     (#) FLASH Interface configuration functions: this group includes the
+         management of the following features:
+       (++) Set the latency
+       (++) Enable/Disable the prefetch buffer
+       (++) Enable/Disable the Instruction cache and the Data cache
+       (++) Reset the Instruction cache and the Data cache
+   
+     (#) FLASH Memory Programming functions: this group includes all needed
+         functions to erase and program the main memory:
+       (++) Lock and Unlock the FLASH interface
+       (++) Erase function: Erase sector, erase all sectors
+       (++) Program functions: byte, half word, word and double word
+   
+     (#) Option Bytes Programming functions: this group includes all needed
+         functions to manage the Option Bytes:
+       (++) Set/Reset the write protection
+       (++) Set the Read protection Level
+       (++) Set the BOR level
+       (++) Program the user Option Bytes
+       (++) Launch the Option Bytes loader
+   
+     (#) Interrupts and flags management functions: this group 
+         includes all needed functions to:
+       (++) Enable/Disable the FLASH interrupt sources
+       (++) Get flags status
+       (++) Clear flags
+       (++) Get FLASH operation status
+       (++) Wait for last FLASH operation   
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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stm32f4xx_flash.h File Reference
+
+
+ +

This file contains all the functions prototypes for the FLASH firmware library. +More...

+
#include "stm32f4xx.h"
+
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+Macros

#define FLASH_Latency_0   ((uint8_t)0x0000)
 
#define FLASH_Latency_1   ((uint8_t)0x0001)
 
#define FLASH_Latency_2   ((uint8_t)0x0002)
 
#define FLASH_Latency_3   ((uint8_t)0x0003)
 
#define FLASH_Latency_4   ((uint8_t)0x0004)
 
#define FLASH_Latency_5   ((uint8_t)0x0005)
 
#define FLASH_Latency_6   ((uint8_t)0x0006)
 
#define FLASH_Latency_7   ((uint8_t)0x0007)
 
#define FLASH_Latency_8   ((uint8_t)0x0008)
 
#define FLASH_Latency_9   ((uint8_t)0x0009)
 
#define FLASH_Latency_10   ((uint8_t)0x000A)
 
#define FLASH_Latency_11   ((uint8_t)0x000B)
 
#define FLASH_Latency_12   ((uint8_t)0x000C)
 
#define FLASH_Latency_13   ((uint8_t)0x000D)
 
#define FLASH_Latency_14   ((uint8_t)0x000E)
 
#define FLASH_Latency_15   ((uint8_t)0x000F)
 
#define IS_FLASH_LATENCY(LATENCY)
 
#define VoltageRange_1   ((uint8_t)0x00)
 
#define VoltageRange_2   ((uint8_t)0x01)
 
#define VoltageRange_3   ((uint8_t)0x02)
 
#define VoltageRange_4   ((uint8_t)0x03)
 
#define IS_VOLTAGERANGE(RANGE)
 
#define FLASH_Sector_0   ((uint16_t)0x0000)
 
#define FLASH_Sector_1   ((uint16_t)0x0008)
 
#define FLASH_Sector_2   ((uint16_t)0x0010)
 
#define FLASH_Sector_3   ((uint16_t)0x0018)
 
#define FLASH_Sector_4   ((uint16_t)0x0020)
 
#define FLASH_Sector_5   ((uint16_t)0x0028)
 
#define FLASH_Sector_6   ((uint16_t)0x0030)
 
#define FLASH_Sector_7   ((uint16_t)0x0038)
 
#define FLASH_Sector_8   ((uint16_t)0x0040)
 
#define FLASH_Sector_9   ((uint16_t)0x0048)
 
#define FLASH_Sector_10   ((uint16_t)0x0050)
 
#define FLASH_Sector_11   ((uint16_t)0x0058)
 
#define FLASH_Sector_12   ((uint16_t)0x0080)
 
#define FLASH_Sector_13   ((uint16_t)0x0088)
 
#define FLASH_Sector_14   ((uint16_t)0x0090)
 
#define FLASH_Sector_15   ((uint16_t)0x0098)
 
#define FLASH_Sector_16   ((uint16_t)0x00A0)
 
#define FLASH_Sector_17   ((uint16_t)0x00A8)
 
#define FLASH_Sector_18   ((uint16_t)0x00B0)
 
#define FLASH_Sector_19   ((uint16_t)0x00B8)
 
#define FLASH_Sector_20   ((uint16_t)0x00C0)
 
#define FLASH_Sector_21   ((uint16_t)0x00C8)
 
#define FLASH_Sector_22   ((uint16_t)0x00D0)
 
#define FLASH_Sector_23   ((uint16_t)0x00D8)
 
#define IS_FLASH_SECTOR(SECTOR)
 
#define IS_FLASH_ADDRESS(ADDRESS)
 
#define OB_WRP_Sector_0   ((uint32_t)0x00000001)
 
#define OB_WRP_Sector_1   ((uint32_t)0x00000002)
 
#define OB_WRP_Sector_2   ((uint32_t)0x00000004)
 
#define OB_WRP_Sector_3   ((uint32_t)0x00000008)
 
#define OB_WRP_Sector_4   ((uint32_t)0x00000010)
 
#define OB_WRP_Sector_5   ((uint32_t)0x00000020)
 
#define OB_WRP_Sector_6   ((uint32_t)0x00000040)
 
#define OB_WRP_Sector_7   ((uint32_t)0x00000080)
 
#define OB_WRP_Sector_8   ((uint32_t)0x00000100)
 
#define OB_WRP_Sector_9   ((uint32_t)0x00000200)
 
#define OB_WRP_Sector_10   ((uint32_t)0x00000400)
 
#define OB_WRP_Sector_11   ((uint32_t)0x00000800)
 
#define OB_WRP_Sector_12   ((uint32_t)0x00000001)
 
#define OB_WRP_Sector_13   ((uint32_t)0x00000002)
 
#define OB_WRP_Sector_14   ((uint32_t)0x00000004)
 
#define OB_WRP_Sector_15   ((uint32_t)0x00000008)
 
#define OB_WRP_Sector_16   ((uint32_t)0x00000010)
 
#define OB_WRP_Sector_17   ((uint32_t)0x00000020)
 
#define OB_WRP_Sector_18   ((uint32_t)0x00000040)
 
#define OB_WRP_Sector_19   ((uint32_t)0x00000080)
 
#define OB_WRP_Sector_20   ((uint32_t)0x00000100)
 
#define OB_WRP_Sector_21   ((uint32_t)0x00000200)
 
#define OB_WRP_Sector_22   ((uint32_t)0x00000400)
 
#define OB_WRP_Sector_23   ((uint32_t)0x00000800)
 
#define OB_WRP_Sector_All   ((uint32_t)0x00000FFF)
 
+#define IS_OB_WRP(SECTOR)   ((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
#define OB_PcROP_Disable   ((uint8_t)0x00)
 
#define OB_PcROP_Enable   ((uint8_t)0x80)
 
+#define IS_OB_PCROP_SELECT(PCROP)   (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
 
#define OB_PCROP_Sector_0   ((uint32_t)0x00000001)
 
#define OB_PCROP_Sector_1   ((uint32_t)0x00000002)
 
#define OB_PCROP_Sector_2   ((uint32_t)0x00000004)
 
#define OB_PCROP_Sector_3   ((uint32_t)0x00000008)
 
#define OB_PCROP_Sector_4   ((uint32_t)0x00000010)
 
#define OB_PCROP_Sector_5   ((uint32_t)0x00000020)
 
#define OB_PCROP_Sector_6   ((uint32_t)0x00000040)
 
#define OB_PCROP_Sector_7   ((uint32_t)0x00000080)
 
#define OB_PCROP_Sector_8   ((uint32_t)0x00000100)
 
#define OB_PCROP_Sector_9   ((uint32_t)0x00000200)
 
#define OB_PCROP_Sector_10   ((uint32_t)0x00000400)
 
#define OB_PCROP_Sector_11   ((uint32_t)0x00000800)
 
#define OB_PCROP_Sector_12   ((uint32_t)0x00000001)
 
#define OB_PCROP_Sector_13   ((uint32_t)0x00000002)
 
#define OB_PCROP_Sector_14   ((uint32_t)0x00000004)
 
#define OB_PCROP_Sector_15   ((uint32_t)0x00000008)
 
#define OB_PCROP_Sector_16   ((uint32_t)0x00000010)
 
#define OB_PCROP_Sector_17   ((uint32_t)0x00000020)
 
#define OB_PCROP_Sector_18   ((uint32_t)0x00000040)
 
#define OB_PCROP_Sector_19   ((uint32_t)0x00000080)
 
#define OB_PCROP_Sector_20   ((uint32_t)0x00000100)
 
#define OB_PCROP_Sector_21   ((uint32_t)0x00000200)
 
#define OB_PCROP_Sector_22   ((uint32_t)0x00000400)
 
#define OB_PCROP_Sector_23   ((uint32_t)0x00000800)
 
#define OB_PCROP_Sector_All   ((uint32_t)0x00000FFF)
 
+#define IS_OB_PCROP(SECTOR)   ((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
 
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
 
+#define OB_RDP_Level_1   ((uint8_t)0x55)
 
#define IS_OB_RDP(LEVEL)
 
#define OB_IWDG_SW   ((uint8_t)0x20)
 
#define OB_IWDG_HW   ((uint8_t)0x00)
 
+#define IS_OB_IWDG_SOURCE(SOURCE)   (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
 
#define OB_STOP_NoRST   ((uint8_t)0x40)
 
#define OB_STOP_RST   ((uint8_t)0x00)
 
+#define IS_OB_STOP_SOURCE(SOURCE)   (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
 
#define OB_STDBY_NoRST   ((uint8_t)0x80)
 
#define OB_STDBY_RST   ((uint8_t)0x00)
 
+#define IS_OB_STDBY_SOURCE(SOURCE)   (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
 
#define OB_BOR_LEVEL3   ((uint8_t)0x00)
 
#define OB_BOR_LEVEL2   ((uint8_t)0x04)
 
#define OB_BOR_LEVEL1   ((uint8_t)0x08)
 
#define OB_BOR_OFF   ((uint8_t)0x0C)
 
#define IS_OB_BOR(LEVEL)
 
#define OB_Dual_BootEnabled   ((uint8_t)0x10)
 
#define OB_Dual_BootDisabled   ((uint8_t)0x00)
 
+#define IS_OB_BOOT(BOOT)   (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
 
#define FLASH_IT_EOP   ((uint32_t)0x01000000)
 
#define FLASH_IT_ERR   ((uint32_t)0x02000000)
 
+#define IS_FLASH_IT(IT)   ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
 
#define FLASH_FLAG_EOP   ((uint32_t)0x00000001)
 
#define FLASH_FLAG_OPERR   ((uint32_t)0x00000002)
 
#define FLASH_FLAG_WRPERR   ((uint32_t)0x00000010)
 
#define FLASH_FLAG_PGAERR   ((uint32_t)0x00000020)
 
#define FLASH_FLAG_PGPERR   ((uint32_t)0x00000040)
 
#define FLASH_FLAG_PGSERR   ((uint32_t)0x00000080)
 
#define FLASH_FLAG_RDERR   ((uint32_t)0x00000100)
 
#define FLASH_FLAG_BSY   ((uint32_t)0x00010000)
 
+#define IS_FLASH_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
 
#define IS_FLASH_GET_FLAG(FLAG)
 
+#define FLASH_PSIZE_BYTE   ((uint32_t)0x00000000)
 
+#define FLASH_PSIZE_HALF_WORD   ((uint32_t)0x00000100)
 
+#define FLASH_PSIZE_WORD   ((uint32_t)0x00000200)
 
+#define FLASH_PSIZE_DOUBLE_WORD   ((uint32_t)0x00000300)
 
+#define CR_PSIZE_MASK   ((uint32_t)0xFFFFFCFF)
 
+#define RDP_KEY   ((uint16_t)0x00A5)
 
+#define FLASH_KEY1   ((uint32_t)0x45670123)
 
+#define FLASH_KEY2   ((uint32_t)0xCDEF89AB)
 
+#define FLASH_OPT_KEY1   ((uint32_t)0x08192A3B)
 
+#define FLASH_OPT_KEY2   ((uint32_t)0x4C5D6E7F)
 
+#define ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
 ACR register byte 0 (Bits[7:0]) base address.
 
+#define OPTCR_BYTE0_ADDRESS   ((uint32_t)0x40023C14)
 OPTCR register byte 0 (Bits[7:0]) base address.
 
+#define OPTCR_BYTE1_ADDRESS   ((uint32_t)0x40023C15)
 OPTCR register byte 1 (Bits[15:8]) base address.
 
+#define OPTCR_BYTE2_ADDRESS   ((uint32_t)0x40023C16)
 OPTCR register byte 2 (Bits[23:16]) base address.
 
+#define OPTCR_BYTE3_ADDRESS   ((uint32_t)0x40023C17)
 OPTCR register byte 3 (Bits[31:24]) base address.
 
+#define OPTCR1_BYTE2_ADDRESS   ((uint32_t)0x40023C1A)
 OPTCR1 register byte 0 (Bits[7:0]) base address.
 
+ + + + +

+Enumerations

enum  FLASH_Status {
+  FLASH_BUSY = 1, +FLASH_ERROR_RD, +FLASH_ERROR_PGS, +FLASH_ERROR_PGP, +
+  FLASH_ERROR_PGA, +FLASH_ERROR_WRP, +FLASH_ERROR_PROGRAM, +FLASH_ERROR_OPERATION, +
+  FLASH_COMPLETE +
+ }
 FLASH Status.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FLASH_SetLatency (uint32_t FLASH_Latency)
 Sets the code latency value. More...
 
void FLASH_PrefetchBufferCmd (FunctionalState NewState)
 Enables or disables the Prefetch Buffer. More...
 
void FLASH_InstructionCacheCmd (FunctionalState NewState)
 Enables or disables the Instruction Cache feature. More...
 
void FLASH_DataCacheCmd (FunctionalState NewState)
 Enables or disables the Data Cache feature. More...
 
void FLASH_InstructionCacheReset (void)
 Resets the Instruction Cache. More...
 
void FLASH_DataCacheReset (void)
 Resets the Data Cache. More...
 
void FLASH_Unlock (void)
 Unlocks the FLASH control register access. More...
 
void FLASH_Lock (void)
 Locks the FLASH control register access. More...
 
FLASH_Status FLASH_EraseSector (uint32_t FLASH_Sector, uint8_t VoltageRange)
 Erases a specified FLASH Sector. More...
 
FLASH_Status FLASH_EraseAllSectors (uint8_t VoltageRange)
 Erases all FLASH Sectors. More...
 
FLASH_Status FLASH_EraseAllBank1Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 1. More...
 
FLASH_Status FLASH_EraseAllBank2Sectors (uint8_t VoltageRange)
 Erases all FLASH Sectors in Bank 2. More...
 
FLASH_Status FLASH_ProgramDoubleWord (uint32_t Address, uint64_t Data)
 Programs a double word (64-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramWord (uint32_t Address, uint32_t Data)
 Programs a word (32-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramHalfWord (uint32_t Address, uint16_t Data)
 Programs a half word (16-bit) at a specified address. More...
 
FLASH_Status FLASH_ProgramByte (uint32_t Address, uint8_t Data)
 Programs a byte (8-bit) at a specified address. More...
 
void FLASH_OB_Unlock (void)
 Unlocks the FLASH Option Control Registers access. More...
 
void FLASH_OB_Lock (void)
 Locks the FLASH Option Control Registers access. More...
 
void FLASH_OB_WRPConfig (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash. More...
 
void FLASH_OB_WRP1Config (uint32_t OB_WRP, FunctionalState NewState)
 Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash. More...
 
void FLASH_OB_PCROPSelectionConfig (uint8_t OB_PcROP)
 Select the Protection Mode (SPRMOD). More...
 
void FLASH_OB_PCROPConfig (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of the Flash. More...
 
void FLASH_OB_PCROP1Config (uint32_t OB_PCROP, FunctionalState NewState)
 Enables or disables the read/write protection (PCROP) of the desired sectors. More...
 
void FLASH_OB_RDPConfig (uint8_t OB_RDP)
 Sets the read protection level. More...
 
void FLASH_OB_UserConfig (uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. More...
 
void FLASH_OB_BORConfig (uint8_t OB_BOR)
 Sets the BOR Level. More...
 
void FLASH_OB_BootConfig (uint8_t OB_BOOT)
 Configure the Dual Bank Boot. More...
 
FLASH_Status FLASH_OB_Launch (void)
 Launch the option byte loading. More...
 
uint8_t FLASH_OB_GetUser (void)
 Returns the FLASH User Option Bytes values. More...
 
uint16_t FLASH_OB_GetWRP (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetWRP1 (void)
 Returns the FLASH Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
uint16_t FLASH_OB_GetPCROP1 (void)
 Returns the FLASH PC Read/Write Protection Option Bytes value. More...
 
FlagStatus FLASH_OB_GetRDP (void)
 Returns the FLASH Read Protection level. More...
 
uint8_t FLASH_OB_GetBOR (void)
 Returns the FLASH BOR level. More...
 
void FLASH_ITConfig (uint32_t FLASH_IT, FunctionalState NewState)
 Enables or disables the specified FLASH interrupts. More...
 
FlagStatus FLASH_GetFlagStatus (uint32_t FLASH_FLAG)
 Checks whether the specified FLASH flag is set or not. More...
 
void FLASH_ClearFlag (uint32_t FLASH_FLAG)
 Clears the FLASH's pending flags. More...
 
FLASH_Status FLASH_GetStatus (void)
 Returns the FLASH Status. More...
 
FLASH_Status FLASH_WaitForLastOperation (void)
 Waits for a FLASH operation to complete. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the FLASH firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
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+
stm32f4xx_flash.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_FLASH_H
+
31 #define __STM32F4xx_FLASH_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
52 typedef enum
+
53 {
+
54  FLASH_BUSY = 1,
+
55  FLASH_ERROR_RD,
+
56  FLASH_ERROR_PGS,
+
57  FLASH_ERROR_PGP,
+
58  FLASH_ERROR_PGA,
+
59  FLASH_ERROR_WRP,
+
60  FLASH_ERROR_PROGRAM,
+
61  FLASH_ERROR_OPERATION,
+
62  FLASH_COMPLETE
+
63 }FLASH_Status;
+
64 
+
65 /* Exported constants --------------------------------------------------------*/
+
66 
+
74 #define FLASH_Latency_0 ((uint8_t)0x0000)
+
75 #define FLASH_Latency_1 ((uint8_t)0x0001)
+
76 #define FLASH_Latency_2 ((uint8_t)0x0002)
+
77 #define FLASH_Latency_3 ((uint8_t)0x0003)
+
78 #define FLASH_Latency_4 ((uint8_t)0x0004)
+
79 #define FLASH_Latency_5 ((uint8_t)0x0005)
+
80 #define FLASH_Latency_6 ((uint8_t)0x0006)
+
81 #define FLASH_Latency_7 ((uint8_t)0x0007)
+
82 #define FLASH_Latency_8 ((uint8_t)0x0008)
+
83 #define FLASH_Latency_9 ((uint8_t)0x0009)
+
84 #define FLASH_Latency_10 ((uint8_t)0x000A)
+
85 #define FLASH_Latency_11 ((uint8_t)0x000B)
+
86 #define FLASH_Latency_12 ((uint8_t)0x000C)
+
87 #define FLASH_Latency_13 ((uint8_t)0x000D)
+
88 #define FLASH_Latency_14 ((uint8_t)0x000E)
+
89 #define FLASH_Latency_15 ((uint8_t)0x000F)
+
92 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+
93  ((LATENCY) == FLASH_Latency_1) || \
+
94  ((LATENCY) == FLASH_Latency_2) || \
+
95  ((LATENCY) == FLASH_Latency_3) || \
+
96  ((LATENCY) == FLASH_Latency_4) || \
+
97  ((LATENCY) == FLASH_Latency_5) || \
+
98  ((LATENCY) == FLASH_Latency_6) || \
+
99  ((LATENCY) == FLASH_Latency_7) || \
+
100  ((LATENCY) == FLASH_Latency_8) || \
+
101  ((LATENCY) == FLASH_Latency_9) || \
+
102  ((LATENCY) == FLASH_Latency_10) || \
+
103  ((LATENCY) == FLASH_Latency_11) || \
+
104  ((LATENCY) == FLASH_Latency_12) || \
+
105  ((LATENCY) == FLASH_Latency_13) || \
+
106  ((LATENCY) == FLASH_Latency_14) || \
+
107  ((LATENCY) == FLASH_Latency_15))
+
108 
+
115 #define VoltageRange_1 ((uint8_t)0x00)
+
116 #define VoltageRange_2 ((uint8_t)0x01)
+
117 #define VoltageRange_3 ((uint8_t)0x02)
+
118 #define VoltageRange_4 ((uint8_t)0x03)
+
120 #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
+
121  ((RANGE) == VoltageRange_2) || \
+
122  ((RANGE) == VoltageRange_3) || \
+
123  ((RANGE) == VoltageRange_4))
+
124 
+
131 #define FLASH_Sector_0 ((uint16_t)0x0000)
+
132 #define FLASH_Sector_1 ((uint16_t)0x0008)
+
133 #define FLASH_Sector_2 ((uint16_t)0x0010)
+
134 #define FLASH_Sector_3 ((uint16_t)0x0018)
+
135 #define FLASH_Sector_4 ((uint16_t)0x0020)
+
136 #define FLASH_Sector_5 ((uint16_t)0x0028)
+
137 #define FLASH_Sector_6 ((uint16_t)0x0030)
+
138 #define FLASH_Sector_7 ((uint16_t)0x0038)
+
139 #define FLASH_Sector_8 ((uint16_t)0x0040)
+
140 #define FLASH_Sector_9 ((uint16_t)0x0048)
+
141 #define FLASH_Sector_10 ((uint16_t)0x0050)
+
142 #define FLASH_Sector_11 ((uint16_t)0x0058)
+
143 #define FLASH_Sector_12 ((uint16_t)0x0080)
+
144 #define FLASH_Sector_13 ((uint16_t)0x0088)
+
145 #define FLASH_Sector_14 ((uint16_t)0x0090)
+
146 #define FLASH_Sector_15 ((uint16_t)0x0098)
+
147 #define FLASH_Sector_16 ((uint16_t)0x00A0)
+
148 #define FLASH_Sector_17 ((uint16_t)0x00A8)
+
149 #define FLASH_Sector_18 ((uint16_t)0x00B0)
+
150 #define FLASH_Sector_19 ((uint16_t)0x00B8)
+
151 #define FLASH_Sector_20 ((uint16_t)0x00C0)
+
152 #define FLASH_Sector_21 ((uint16_t)0x00C8)
+
153 #define FLASH_Sector_22 ((uint16_t)0x00D0)
+
154 #define FLASH_Sector_23 ((uint16_t)0x00D8)
+
156 #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
+
157  ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
+
158  ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
+
159  ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
+
160  ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
+
161  ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\
+
162  ((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\
+
163  ((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\
+
164  ((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\
+
165  ((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\
+
166  ((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
+
167  ((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
+
168 
+
169 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
170 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
+
171  (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+
172 #endif /* STM32F427_437xx || STM32F429_439xx */
+
173 
+
174 #if defined (STM32F40_41xxx)
+
175 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
+
176  (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+
177 #endif /* STM32F40_41xxx */
+
178 
+
179 #if defined (STM32F401xx)
+
180 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
+
181  (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+
182 #endif /* STM32F401xx */
+
183 
+
184 #if defined (STM32F411xE)
+
185 #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
+
186  (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+
187 #endif /* STM32F411xE */
+
188 
+
196 #define OB_WRP_Sector_0 ((uint32_t)0x00000001)
+
197 #define OB_WRP_Sector_1 ((uint32_t)0x00000002)
+
198 #define OB_WRP_Sector_2 ((uint32_t)0x00000004)
+
199 #define OB_WRP_Sector_3 ((uint32_t)0x00000008)
+
200 #define OB_WRP_Sector_4 ((uint32_t)0x00000010)
+
201 #define OB_WRP_Sector_5 ((uint32_t)0x00000020)
+
202 #define OB_WRP_Sector_6 ((uint32_t)0x00000040)
+
203 #define OB_WRP_Sector_7 ((uint32_t)0x00000080)
+
204 #define OB_WRP_Sector_8 ((uint32_t)0x00000100)
+
205 #define OB_WRP_Sector_9 ((uint32_t)0x00000200)
+
206 #define OB_WRP_Sector_10 ((uint32_t)0x00000400)
+
207 #define OB_WRP_Sector_11 ((uint32_t)0x00000800)
+
208 #define OB_WRP_Sector_12 ((uint32_t)0x00000001)
+
209 #define OB_WRP_Sector_13 ((uint32_t)0x00000002)
+
210 #define OB_WRP_Sector_14 ((uint32_t)0x00000004)
+
211 #define OB_WRP_Sector_15 ((uint32_t)0x00000008)
+
212 #define OB_WRP_Sector_16 ((uint32_t)0x00000010)
+
213 #define OB_WRP_Sector_17 ((uint32_t)0x00000020)
+
214 #define OB_WRP_Sector_18 ((uint32_t)0x00000040)
+
215 #define OB_WRP_Sector_19 ((uint32_t)0x00000080)
+
216 #define OB_WRP_Sector_20 ((uint32_t)0x00000100)
+
217 #define OB_WRP_Sector_21 ((uint32_t)0x00000200)
+
218 #define OB_WRP_Sector_22 ((uint32_t)0x00000400)
+
219 #define OB_WRP_Sector_23 ((uint32_t)0x00000800)
+
220 #define OB_WRP_Sector_All ((uint32_t)0x00000FFF)
+
222 #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+
223 
+
230 #define OB_PcROP_Disable ((uint8_t)0x00)
+
231 #define OB_PcROP_Enable ((uint8_t)0x80)
+
232 #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
+
233 
+
240 #define OB_PCROP_Sector_0 ((uint32_t)0x00000001)
+
241 #define OB_PCROP_Sector_1 ((uint32_t)0x00000002)
+
242 #define OB_PCROP_Sector_2 ((uint32_t)0x00000004)
+
243 #define OB_PCROP_Sector_3 ((uint32_t)0x00000008)
+
244 #define OB_PCROP_Sector_4 ((uint32_t)0x00000010)
+
245 #define OB_PCROP_Sector_5 ((uint32_t)0x00000020)
+
246 #define OB_PCROP_Sector_6 ((uint32_t)0x00000040)
+
247 #define OB_PCROP_Sector_7 ((uint32_t)0x00000080)
+
248 #define OB_PCROP_Sector_8 ((uint32_t)0x00000100)
+
249 #define OB_PCROP_Sector_9 ((uint32_t)0x00000200)
+
250 #define OB_PCROP_Sector_10 ((uint32_t)0x00000400)
+
251 #define OB_PCROP_Sector_11 ((uint32_t)0x00000800)
+
252 #define OB_PCROP_Sector_12 ((uint32_t)0x00000001)
+
253 #define OB_PCROP_Sector_13 ((uint32_t)0x00000002)
+
254 #define OB_PCROP_Sector_14 ((uint32_t)0x00000004)
+
255 #define OB_PCROP_Sector_15 ((uint32_t)0x00000008)
+
256 #define OB_PCROP_Sector_16 ((uint32_t)0x00000010)
+
257 #define OB_PCROP_Sector_17 ((uint32_t)0x00000020)
+
258 #define OB_PCROP_Sector_18 ((uint32_t)0x00000040)
+
259 #define OB_PCROP_Sector_19 ((uint32_t)0x00000080)
+
260 #define OB_PCROP_Sector_20 ((uint32_t)0x00000100)
+
261 #define OB_PCROP_Sector_21 ((uint32_t)0x00000200)
+
262 #define OB_PCROP_Sector_22 ((uint32_t)0x00000400)
+
263 #define OB_PCROP_Sector_23 ((uint32_t)0x00000800)
+
264 #define OB_PCROP_Sector_All ((uint32_t)0x00000FFF)
+
266 #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+
267 
+
274 #define OB_RDP_Level_0 ((uint8_t)0xAA)
+
275 #define OB_RDP_Level_1 ((uint8_t)0x55)
+
276 /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/
+
278 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+
279  ((LEVEL) == OB_RDP_Level_1))/*||\
+
280  ((LEVEL) == OB_RDP_Level_2))*/
+
281 
+
288 #define OB_IWDG_SW ((uint8_t)0x20)
+
289 #define OB_IWDG_HW ((uint8_t)0x00)
+
290 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
291 
+
298 #define OB_STOP_NoRST ((uint8_t)0x40)
+
299 #define OB_STOP_RST ((uint8_t)0x00)
+
300 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
301 
+
309 #define OB_STDBY_NoRST ((uint8_t)0x80)
+
310 #define OB_STDBY_RST ((uint8_t)0x00)
+
311 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
312 
+
319 #define OB_BOR_LEVEL3 ((uint8_t)0x00)
+
320 #define OB_BOR_LEVEL2 ((uint8_t)0x04)
+
321 #define OB_BOR_LEVEL1 ((uint8_t)0x08)
+
322 #define OB_BOR_OFF ((uint8_t)0x0C)
+
323 #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+
324  ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
325 
+
332 #define OB_Dual_BootEnabled ((uint8_t)0x10)
+
333 #define OB_Dual_BootDisabled ((uint8_t)0x00)
+
334 #define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
+
335 
+
342 #define FLASH_IT_EOP ((uint32_t)0x01000000)
+
343 #define FLASH_IT_ERR ((uint32_t)0x02000000)
+
344 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
+
345 
+
352 #define FLASH_FLAG_EOP ((uint32_t)0x00000001)
+
353 #define FLASH_FLAG_OPERR ((uint32_t)0x00000002)
+
354 #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010)
+
355 #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020)
+
356 #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040)
+
357 #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080)
+
358 #define FLASH_FLAG_RDERR ((uint32_t)0x00000100)
+
359 #define FLASH_FLAG_BSY ((uint32_t)0x00010000)
+
360 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
+
361 #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
+
362  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
+
363  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
+
364  ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
+
365 
+
372 #define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
+
373 #define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
+
374 #define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
+
375 #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
+
376 #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
+
377 
+
384 #define RDP_KEY ((uint16_t)0x00A5)
+
385 #define FLASH_KEY1 ((uint32_t)0x45670123)
+
386 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
387 #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
+
388 #define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
+
389 
+
396 #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
+
397 
+
400 #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
+
401 
+
404 #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
+
405 
+
408 #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
+
409 
+
412 #define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
+
413 
+
417 #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
+
418 
+
423 /* Exported macro ------------------------------------------------------------*/
+
424 /* Exported functions --------------------------------------------------------*/
+
425 
+
426 /* FLASH Interface configuration functions ************************************/
+
427 void FLASH_SetLatency(uint32_t FLASH_Latency);
+
428 void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+
429 void FLASH_InstructionCacheCmd(FunctionalState NewState);
+
430 void FLASH_DataCacheCmd(FunctionalState NewState);
+
431 void FLASH_InstructionCacheReset(void);
+
432 void FLASH_DataCacheReset(void);
+
433 
+
434 /* FLASH Memory Programming functions *****************************************/
+
435 void FLASH_Unlock(void);
+
436 void FLASH_Lock(void);
+
437 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
+
438 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
+
439 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
+
440 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
+
441 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
+
442 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+
443 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
444 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+
445 
+
446 /* Option Bytes Programming functions *****************************************/
+
447 void FLASH_OB_Unlock(void);
+
448 void FLASH_OB_Lock(void);
+
449 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+
450 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
+
451 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
+
452 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
+
453 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
+
454 void FLASH_OB_RDPConfig(uint8_t OB_RDP);
+
455 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+
456 void FLASH_OB_BORConfig(uint8_t OB_BOR);
+
457 void FLASH_OB_BootConfig(uint8_t OB_BOOT);
+
458 FLASH_Status FLASH_OB_Launch(void);
+
459 uint8_t FLASH_OB_GetUser(void);
+
460 uint16_t FLASH_OB_GetWRP(void);
+
461 uint16_t FLASH_OB_GetWRP1(void);
+
462 uint16_t FLASH_OB_GetPCROP(void);
+
463 uint16_t FLASH_OB_GetPCROP1(void);
+
464 FlagStatus FLASH_OB_GetRDP(void);
+
465 uint8_t FLASH_OB_GetBOR(void);
+
466 
+
467 /* Interrupts and flags management functions **********************************/
+
468 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+
469 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+
470 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+
471 FLASH_Status FLASH_GetStatus(void);
+
472 FLASH_Status FLASH_WaitForLastOperation(void);
+
473 
+
474 #ifdef __cplusplus
+
475 }
+
476 #endif
+
477 
+
478 #endif /* __STM32F4xx_FLASH_H */
+
479 
+
488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
FLASH_OB_WRP1Config
void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
Enables or disables the write protection of the desired sectors, for the second 1 Mb of the Flash...
Definition: stm32f4xx_flash.c:1048
+
FLASH_ProgramHalfWord
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
Programs a half word (16-bit) at a specified address.
Definition: stm32f4xx_flash.c:827
+
FLASH_ITConfig
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
Enables or disables the specified FLASH interrupts.
Definition: stm32f4xx_flash.c:1450
+
FLASH_EraseAllBank1Sectors
FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
Erases all FLASH Sectors in Bank 1.
Definition: stm32f4xx_flash.c:618
+
FLASH_OB_RDPConfig
void FLASH_OB_RDPConfig(uint8_t OB_RDP)
Sets the read protection level.
Definition: stm32f4xx_flash.c:1201
+
FLASH_EraseAllBank2Sectors
FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
Erases all FLASH Sectors in Bank 2.
Definition: stm32f4xx_flash.c:685
+
FLASH_WaitForLastOperation
FLASH_Status FLASH_WaitForLastOperation(void)
Waits for a FLASH operation to complete.
Definition: stm32f4xx_flash.c:1578
+
FLASH_EraseSector
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
Erases a specified FLASH Sector.
Definition: stm32f4xx_flash.c:469
+
FLASH_OB_GetWRP1
uint16_t FLASH_OB_GetWRP1(void)
Returns the FLASH Write Protection Option Bytes value.
Definition: stm32f4xx_flash.c:1356
+
FLASH_OB_GetWRP
uint16_t FLASH_OB_GetWRP(void)
Returns the FLASH Write Protection Option Bytes value.
Definition: stm32f4xx_flash.c:1342
+
FLASH_ClearFlag
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
Clears the FLASH's pending flags.
Definition: stm32f4xx_flash.c:1513
+
FLASH_OB_Lock
void FLASH_OB_Lock(void)
Locks the FLASH Option Control Registers access.
Definition: stm32f4xx_flash.c:983
+
FLASH_EraseAllSectors
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
Erases all FLASH Sectors.
Definition: stm32f4xx_flash.c:537
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
FLASH_OB_PCROPConfig
void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
Enables or disables the read/write protection (PCROP) of the desired sectors, for the first 1 MB of t...
Definition: stm32f4xx_flash.c:1128
+
FLASH_OB_BORConfig
void FLASH_OB_BORConfig(uint8_t OB_BOR)
Sets the BOR Level.
Definition: stm32f4xx_flash.c:1295
+
FLASH_DataCacheCmd
void FLASH_DataCacheCmd(FunctionalState NewState)
Enables or disables the Data Cache feature.
Definition: stm32f4xx_flash.c:335
+
FLASH_InstructionCacheReset
void FLASH_InstructionCacheReset(void)
Resets the Instruction Cache.
Definition: stm32f4xx_flash.c:356
+
FLASH_InstructionCacheCmd
void FLASH_InstructionCacheCmd(FunctionalState NewState)
Enables or disables the Instruction Cache feature.
Definition: stm32f4xx_flash.c:314
+
FLASH_ProgramDoubleWord
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
Programs a double word (64-bit) at a specified address.
Definition: stm32f4xx_flash.c:742
+
FLASH_Unlock
void FLASH_Unlock(void)
Unlocks the FLASH control register access.
Definition: stm32f4xx_flash.c:414
+
FLASH_OB_WRPConfig
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
Enables or disables the write protection of the desired sectors, for the first 1 Mb of the Flash...
Definition: stm32f4xx_flash.c:1006
+
FLASH_GetFlagStatus
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
Checks whether the specified FLASH flag is set or not.
Definition: stm32f4xx_flash.c:1482
+
FLASH_OB_Unlock
void FLASH_OB_Unlock(void)
Unlocks the FLASH Option Control Registers access.
Definition: stm32f4xx_flash.c:968
+
FLASH_DataCacheReset
void FLASH_DataCacheReset(void)
Resets the Data Cache.
Definition: stm32f4xx_flash.c:367
+
FLASH_OB_GetPCROP1
uint16_t FLASH_OB_GetPCROP1(void)
Returns the FLASH PC Read/Write Protection Option Bytes value.
Definition: stm32f4xx_flash.c:1384
+
FLASH_OB_PCROPSelectionConfig
void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
Select the Protection Mode (SPRMOD).
Definition: stm32f4xx_flash.c:1098
+
FLASH_OB_GetRDP
FlagStatus FLASH_OB_GetRDP(void)
Returns the FLASH Read Protection level.
Definition: stm32f4xx_flash.c:1397
+
FLASH_OB_GetUser
uint8_t FLASH_OB_GetUser(void)
Returns the FLASH User Option Bytes values.
Definition: stm32f4xx_flash.c:1331
+
FLASH_PrefetchBufferCmd
void FLASH_PrefetchBufferCmd(FunctionalState NewState)
Enables or disables the Prefetch Buffer.
Definition: stm32f4xx_flash.c:292
+
FLASH_OB_GetBOR
uint8_t FLASH_OB_GetBOR(void)
Returns the FLASH BOR level.
Definition: stm32f4xx_flash.c:1421
+
FLASH_ProgramByte
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
Programs a byte (8-bit) at a specified address.
Definition: stm32f4xx_flash.c:869
+
FLASH_OB_PCROP1Config
void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
Enables or disables the read/write protection (PCROP) of the desired sectors.
Definition: stm32f4xx_flash.c:1165
+
FLASH_SetLatency
void FLASH_SetLatency(uint32_t FLASH_Latency)
Sets the code latency value.
Definition: stm32f4xx_flash.c:277
+
FLASH_OB_Launch
FLASH_Status FLASH_OB_Launch(void)
Launch the option byte loading.
Definition: stm32f4xx_flash.c:1312
+
FLASH_GetStatus
FLASH_Status FLASH_GetStatus(void)
Returns the FLASH Status.
Definition: stm32f4xx_flash.c:1528
+
FLASH_OB_BootConfig
void FLASH_OB_BootConfig(uint8_t OB_BOOT)
Configure the Dual Bank Boot.
Definition: stm32f4xx_flash.c:1274
+
FLASH_OB_UserConfig
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
Definition: stm32f4xx_flash.c:1233
+
FLASH_Lock
void FLASH_Lock(void)
Locks the FLASH control register access.
Definition: stm32f4xx_flash.c:429
+
FLASH_Status
FLASH_Status
FLASH Status.
Definition: stm32f4xx_flash.h:52
+
FLASH_OB_GetPCROP
uint16_t FLASH_OB_GetPCROP(void)
Returns the FLASH PC Read/Write Protection Option Bytes value.
Definition: stm32f4xx_flash.c:1370
+
FLASH_ProgramWord
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
Programs a word (32-bit) at a specified address.
Definition: stm32f4xx_flash.c:785
+
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+ + diff --git a/stm32f4xx__flash__ramfunc_8c.html b/stm32f4xx__flash__ramfunc_8c.html new file mode 100644 index 0000000..c5e0721 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8c.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_flash_ramfunc.c File Reference + + + + + + + + + + +
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stm32f4xx_flash_ramfunc.c File Reference
+
+
+ +

FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM. +More...

+
#include "stm32f4xx_flash_ramfunc.h"
+
+Include dependency graph for stm32f4xx_flash_ramfunc.c:
+
+
+ + +
+
+ + + + + + + +

+Functions

__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
 Start/Stop the flash interface while System Run. More...
 
__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
 Enable/Disable the flash sleep while System Run. More...
 
+

Detailed Description

+

FLASH RAMFUNC module driver. This file provides a FLASH firmware functions which should be executed from internal SRAM.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Stop/Start the flash interface while System Run
    • +
  • Enable/Disable the flash sleep while System Run
    • +
+
+
==============================================================================
+                   ##### APIs executed from Internal RAM #####
+ ==============================================================================
+ [..]
+   *** ARM Compiler ***
+   --------------------
+   [..] RAM functions are defined using the toolchain options. 
+        Functions that are be executed in RAM should reside in a separate
+        source module. Using the 'Options for File' dialog you can simply change
+        the 'Code / Const' area of a module to a memory space in physical RAM.
+        Available memory areas are declared in the 'Target' tab of the 
+        Options for Target' dialog.
+
+   *** ICCARM Compiler ***
+   -----------------------
+   [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+   *** GNU Compiler ***
+   --------------------
+   [..] RAM functions are defined using a specific toolchain attribute
+        "__attribute__((section(".RamFunc")))".
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
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+ + diff --git a/stm32f4xx__flash__ramfunc_8c__incl.map b/stm32f4xx__flash__ramfunc_8c__incl.map new file mode 100644 index 0000000..d13e699 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__flash__ramfunc_8c__incl.md5 b/stm32f4xx__flash__ramfunc_8c__incl.md5 new file mode 100644 index 0000000..dfac891 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8c__incl.md5 @@ -0,0 +1 @@ +241ff293ce5fc06873767d2341cdcf63 \ No newline at end of file diff --git a/stm32f4xx__flash__ramfunc_8c__incl.png b/stm32f4xx__flash__ramfunc_8c__incl.png new file mode 100644 index 0000000..68df831 Binary files /dev/null and b/stm32f4xx__flash__ramfunc_8c__incl.png differ diff --git a/stm32f4xx__flash__ramfunc_8h.html b/stm32f4xx__flash__ramfunc_8h.html new file mode 100644 index 0000000..dd28890 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h.html @@ -0,0 +1,142 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_flash_ramfunc.h File Reference + + + + + + + + + + +
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stm32f4xx_flash_ramfunc.h File Reference
+
+
+ +

Header file of FLASH RAMFUNC driver. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_flash_ramfunc.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + +

+Functions

__RAM_FUNC FLASH_FlashInterfaceCmd (FunctionalState NewState)
 __RAM_FUNC definition More...
 
__RAM_FUNC FLASH_FlashSleepModeCmd (FunctionalState NewState)
 Enable/Disable the flash sleep while System Run. More...
 
+

Detailed Description

+

Header file of FLASH RAMFUNC driver.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__flash__ramfunc_8h__dep__incl.map b/stm32f4xx__flash__ramfunc_8h__dep__incl.map new file mode 100644 index 0000000..3e1237b --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/stm32f4xx__flash__ramfunc_8h__dep__incl.md5 b/stm32f4xx__flash__ramfunc_8h__dep__incl.md5 new file mode 100644 index 0000000..6e54459 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h__dep__incl.md5 @@ -0,0 +1 @@ +354c461f8297c83bca09fa78dd2e03e0 \ No newline at end of file diff --git a/stm32f4xx__flash__ramfunc_8h__dep__incl.png b/stm32f4xx__flash__ramfunc_8h__dep__incl.png new file mode 100644 index 0000000..b54cf46 Binary files /dev/null and b/stm32f4xx__flash__ramfunc_8h__dep__incl.png differ diff --git a/stm32f4xx__flash__ramfunc_8h__incl.map b/stm32f4xx__flash__ramfunc_8h__incl.map new file mode 100644 index 0000000..3bf4435 --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__flash__ramfunc_8h__incl.md5 b/stm32f4xx__flash__ramfunc_8h__incl.md5 new file mode 100644 index 0000000..bd0c74d --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h__incl.md5 @@ -0,0 +1 @@ +997c792888a53eb6cfe42f660adae868 \ No newline at end of file diff --git a/stm32f4xx__flash__ramfunc_8h__incl.png b/stm32f4xx__flash__ramfunc_8h__incl.png new file mode 100644 index 0000000..4f20a67 Binary files /dev/null and b/stm32f4xx__flash__ramfunc_8h__incl.png differ diff --git a/stm32f4xx__flash__ramfunc_8h_source.html b/stm32f4xx__flash__ramfunc_8h_source.html new file mode 100644 index 0000000..819f03d --- /dev/null +++ b/stm32f4xx__flash__ramfunc_8h_source.html @@ -0,0 +1,161 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_flash_ramfunc.h Source File + + + + + + + + + + +
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stm32f4xx_flash_ramfunc.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_FLASH_RAMFUNC_H
+
31 #define __STM32F4xx_FLASH_RAMFUNC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Private define ------------------------------------------------------------*/
+
53 #if defined ( __CC_ARM )
+
54 /* ARM Compiler
+
55  ------------
+
56  RAM functions are defined using the toolchain options.
+
57  Functions that are executed in RAM should reside in a separate source module.
+
58  Using the 'Options for File' dialog you can simply change the 'Code / Const'
+
59  area of a module to a memory space in physical RAM.
+
60  Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+
61  dialog.
+
62 */
+
63 #define __RAM_FUNC void
+
64 
+
65 #elif defined ( __ICCARM__ )
+
66 /* ICCARM Compiler
+
67  ---------------
+
68  RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
69 */
+
70 #define __RAM_FUNC __ramfunc void
+
71 
+
72 #elif defined ( __GNUC__ )
+
73 /* GNU Compiler
+
74  ------------
+
75  RAM functions are defined using a specific toolchain attribute
+
76  "__attribute__((section(".RamFunc")))".
+
77 */
+
78 #define __RAM_FUNC void __attribute__((section(".RamFunc")))
+
79 
+
80 #endif
+
81 /* Exported constants --------------------------------------------------------*/
+
82 /* Exported macro ------------------------------------------------------------*/
+
83 /* Exported functions --------------------------------------------------------*/
+
84 __RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
+
85 __RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
+
86 
+
87 
+
88 #ifdef __cplusplus
+
89 }
+
90 #endif
+
91 
+
92 #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
+
93 
+
102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
103 
+
FLASH_FlashSleepModeCmd
__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState)
Enable/Disable the flash sleep while System Run.
Definition: stm32f4xx_flash_ramfunc.c:128
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
FLASH_FlashInterfaceCmd
__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState)
__RAM_FUNC definition
Definition: stm32f4xx_flash_ramfunc.c:105
+
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+ + diff --git a/stm32f4xx__fsmc_8c.html b/stm32f4xx__fsmc_8c.html new file mode 100644 index 0000000..a2cd244 --- /dev/null +++ b/stm32f4xx__fsmc_8c.html @@ -0,0 +1,225 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_fsmc.c File Reference + + + + + + + + + + +
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+
stm32f4xx_fsmc.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the FSMC peripheral: +More...

+
#include "stm32f4xx_fsmc.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_fsmc.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + +

+Macros

+#define BCR_MBKEN_SET   ((uint32_t)0x00000001)
 
+#define BCR_MBKEN_RESET   ((uint32_t)0x000FFFFE)
 
+#define BCR_FACCEN_SET   ((uint32_t)0x00000040)
 
+#define PCR_PBKEN_SET   ((uint32_t)0x00000004)
 
+#define PCR_PBKEN_RESET   ((uint32_t)0x000FFFFB)
 
+#define PCR_ECCEN_SET   ((uint32_t)0x00000040)
 
+#define PCR_ECCEN_RESET   ((uint32_t)0x000FFFBF)
 
+#define PCR_MEMORYTYPE_NAND   ((uint32_t)0x00000008)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NOR/SRAM Banks registers to their default reset values. More...
 
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct. More...
 
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Fills each FSMC_NORSRAMInitStruct member with its default value. More...
 
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NOR/SRAM Memory Bank. More...
 
void FSMC_NANDDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NAND Banks registers to their default reset values. More...
 
void FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct. More...
 
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Fills each FSMC_NANDInitStruct member with its default value. More...
 
void FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NAND Memory Bank. More...
 
void FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the FSMC NAND ECC feature. More...
 
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
 Returns the error correction code register value. More...
 
void FSMC_PCCARDDeInit (void)
 De-initializes the FSMC PCCARD Bank registers to their default reset values. More...
 
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct. More...
 
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Fills each FSMC_PCCARDInitStruct member with its default value. More...
 
void FSMC_PCCARDCmd (FunctionalState NewState)
 Enables or disables the PCCARD Memory Bank. More...
 
void FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
 Enables or disables the specified FSMC interrupts. More...
 
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Checks whether the specified FSMC flag is set or not. More...
 
void FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Clears the FSMC's pending flags. More...
 
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Checks whether the specified FSMC interrupt has occurred or not. More...
 
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Clears the FSMC's interrupt pending bits. More...
 
+ + + +

+Variables

const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the FSMC peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Interface with SRAM, PSRAM, NOR and OneNAND memories
    • +
  • Interface with NAND memories
    • +
  • Interface with 16-bit PC Card compatible memories
    • +
  • Interrupts and flags management
    • +
+
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__fsmc_8c__incl.map b/stm32f4xx__fsmc_8c__incl.map new file mode 100644 index 0000000..8367279 --- /dev/null +++ b/stm32f4xx__fsmc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__fsmc_8c__incl.md5 b/stm32f4xx__fsmc_8c__incl.md5 new file mode 100644 index 0000000..b3a747c --- /dev/null +++ b/stm32f4xx__fsmc_8c__incl.md5 @@ -0,0 +1 @@ +2fc0a9b210c89d1ac34160ff99bbca05 \ No newline at end of file diff --git a/stm32f4xx__fsmc_8c__incl.png b/stm32f4xx__fsmc_8c__incl.png new file mode 100644 index 0000000..ed1f78a Binary files /dev/null and b/stm32f4xx__fsmc_8c__incl.png differ diff --git a/stm32f4xx__fsmc_8h.html b/stm32f4xx__fsmc_8h.html new file mode 100644 index 0000000..6a08c49 --- /dev/null +++ b/stm32f4xx__fsmc_8h.html @@ -0,0 +1,461 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_fsmc.h File Reference + + + + + + + + + + +
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stm32f4xx_fsmc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the FSMC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_fsmc.h:
+
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+ + + + + + + + + + + + + + + + + +

+Classes

struct  FSMC_NORSRAMTimingInitTypeDef
 Timing parameters For NOR/SRAM Banks. More...
 
struct  FSMC_NORSRAMInitTypeDef
 FSMC NOR/SRAM Init structure definition. More...
 
struct  FSMC_NAND_PCCARDTimingInitTypeDef
 Timing parameters For FSMC NAND and PCCARD Banks. More...
 
struct  FSMC_NANDInitTypeDef
 FSMC NAND Init structure definition. More...
 
struct  FSMC_PCCARDInitTypeDef
 FSMC PCCARD Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define FSMC_Bank1_NORSRAM1   ((uint32_t)0x00000000)
 
+#define FSMC_Bank1_NORSRAM2   ((uint32_t)0x00000002)
 
+#define FSMC_Bank1_NORSRAM3   ((uint32_t)0x00000004)
 
+#define FSMC_Bank1_NORSRAM4   ((uint32_t)0x00000006)
 
+#define FSMC_Bank2_NAND   ((uint32_t)0x00000010)
 
+#define FSMC_Bank3_NAND   ((uint32_t)0x00000100)
 
+#define FSMC_Bank4_PCCARD   ((uint32_t)0x00001000)
 
#define IS_FSMC_NORSRAM_BANK(BANK)
 
#define IS_FSMC_NAND_BANK(BANK)
 
#define IS_FSMC_GETFLAG_BANK(BANK)
 
#define IS_FSMC_IT_BANK(BANK)
 
+#define FSMC_DataAddressMux_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_DataAddressMux_Enable   ((uint32_t)0x00000002)
 
#define IS_FSMC_MUX(MUX)
 
+#define FSMC_MemoryType_SRAM   ((uint32_t)0x00000000)
 
+#define FSMC_MemoryType_PSRAM   ((uint32_t)0x00000004)
 
+#define FSMC_MemoryType_NOR   ((uint32_t)0x00000008)
 
#define IS_FSMC_MEMORY(MEMORY)
 
+#define FSMC_MemoryDataWidth_8b   ((uint32_t)0x00000000)
 
+#define FSMC_MemoryDataWidth_16b   ((uint32_t)0x00000010)
 
#define IS_FSMC_MEMORY_WIDTH(WIDTH)
 
+#define FSMC_BurstAccessMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_BurstAccessMode_Enable   ((uint32_t)0x00000100)
 
#define IS_FSMC_BURSTMODE(STATE)
 
+#define FSMC_AsynchronousWait_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_AsynchronousWait_Enable   ((uint32_t)0x00008000)
 
#define IS_FSMC_ASYNWAIT(STATE)
 
+#define FSMC_WaitSignalPolarity_Low   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalPolarity_High   ((uint32_t)0x00000200)
 
#define IS_FSMC_WAIT_POLARITY(POLARITY)
 
+#define FSMC_WrapMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WrapMode_Enable   ((uint32_t)0x00000400)
 
#define IS_FSMC_WRAP_MODE(MODE)
 
+#define FSMC_WaitSignalActive_BeforeWaitState   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignalActive_DuringWaitState   ((uint32_t)0x00000800)
 
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE)
 
+#define FSMC_WriteOperation_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WriteOperation_Enable   ((uint32_t)0x00001000)
 
#define IS_FSMC_WRITE_OPERATION(OPERATION)
 
+#define FSMC_WaitSignal_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WaitSignal_Enable   ((uint32_t)0x00002000)
 
#define IS_FSMC_WAITE_SIGNAL(SIGNAL)
 
+#define FSMC_ExtendedMode_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_ExtendedMode_Enable   ((uint32_t)0x00004000)
 
#define IS_FSMC_EXTENDED_MODE(MODE)
 
+#define FSMC_WriteBurst_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_WriteBurst_Enable   ((uint32_t)0x00080000)
 
#define IS_FSMC_WRITE_BURST(BURST)
 
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME)   ((TIME) <= 0xF)
 
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME)   ((TIME) <= 0xF)
 
+#define IS_FSMC_DATASETUP_TIME(TIME)   (((TIME) > 0) && ((TIME) <= 0xFF))
 
+#define IS_FSMC_TURNAROUND_TIME(TIME)   ((TIME) <= 0xF)
 
+#define IS_FSMC_CLK_DIV(DIV)   ((DIV) <= 0xF)
 
+#define IS_FSMC_DATA_LATENCY(LATENCY)   ((LATENCY) <= 0xF)
 
+#define FSMC_AccessMode_A   ((uint32_t)0x00000000)
 
+#define FSMC_AccessMode_B   ((uint32_t)0x10000000)
 
+#define FSMC_AccessMode_C   ((uint32_t)0x20000000)
 
+#define FSMC_AccessMode_D   ((uint32_t)0x30000000)
 
#define IS_FSMC_ACCESS_MODE(MODE)
 
+#define FSMC_Waitfeature_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_Waitfeature_Enable   ((uint32_t)0x00000002)
 
#define IS_FSMC_WAIT_FEATURE(FEATURE)
 
+#define FSMC_ECC_Disable   ((uint32_t)0x00000000)
 
+#define FSMC_ECC_Enable   ((uint32_t)0x00000040)
 
#define IS_FSMC_ECC_STATE(STATE)
 
+#define FSMC_ECCPageSize_256Bytes   ((uint32_t)0x00000000)
 
+#define FSMC_ECCPageSize_512Bytes   ((uint32_t)0x00020000)
 
+#define FSMC_ECCPageSize_1024Bytes   ((uint32_t)0x00040000)
 
+#define FSMC_ECCPageSize_2048Bytes   ((uint32_t)0x00060000)
 
+#define FSMC_ECCPageSize_4096Bytes   ((uint32_t)0x00080000)
 
+#define FSMC_ECCPageSize_8192Bytes   ((uint32_t)0x000A0000)
 
#define IS_FSMC_ECCPAGE_SIZE(SIZE)
 
+#define IS_FSMC_TCLR_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define IS_FSMC_TAR_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define IS_FSMC_SETUP_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define IS_FSMC_WAIT_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define IS_FSMC_HOLD_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define IS_FSMC_HIZ_TIME(TIME)   ((TIME) <= 0xFF)
 
+#define FSMC_IT_RisingEdge   ((uint32_t)0x00000008)
 
+#define FSMC_IT_Level   ((uint32_t)0x00000010)
 
+#define FSMC_IT_FallingEdge   ((uint32_t)0x00000020)
 
+#define IS_FSMC_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
 
#define IS_FSMC_GET_IT(IT)
 
+#define FSMC_FLAG_RisingEdge   ((uint32_t)0x00000001)
 
+#define FSMC_FLAG_Level   ((uint32_t)0x00000002)
 
+#define FSMC_FLAG_FallingEdge   ((uint32_t)0x00000004)
 
+#define FSMC_FLAG_FEMPT   ((uint32_t)0x00000040)
 
#define IS_FSMC_GET_FLAG(FLAG)
 
+#define IS_FSMC_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void FSMC_NORSRAMDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NOR/SRAM Banks registers to their default reset values. More...
 
void FSMC_NORSRAMInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStruct. More...
 
void FSMC_NORSRAMStructInit (FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
 Fills each FSMC_NORSRAMInitStruct member with its default value. More...
 
void FSMC_NORSRAMCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NOR/SRAM Memory Bank. More...
 
void FSMC_NANDDeInit (uint32_t FSMC_Bank)
 De-initializes the FSMC NAND Banks registers to their default reset values. More...
 
void FSMC_NANDInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct. More...
 
void FSMC_NANDStructInit (FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
 Fills each FSMC_NANDInitStruct member with its default value. More...
 
void FSMC_NANDCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the specified NAND Memory Bank. More...
 
void FSMC_NANDECCCmd (uint32_t FSMC_Bank, FunctionalState NewState)
 Enables or disables the FSMC NAND ECC feature. More...
 
uint32_t FSMC_GetECC (uint32_t FSMC_Bank)
 Returns the error correction code register value. More...
 
void FSMC_PCCARDDeInit (void)
 De-initializes the FSMC PCCARD Bank registers to their default reset values. More...
 
void FSMC_PCCARDInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct. More...
 
void FSMC_PCCARDStructInit (FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
 Fills each FSMC_PCCARDInitStruct member with its default value. More...
 
void FSMC_PCCARDCmd (FunctionalState NewState)
 Enables or disables the PCCARD Memory Bank. More...
 
void FSMC_ITConfig (uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
 Enables or disables the specified FSMC interrupts. More...
 
FlagStatus FSMC_GetFlagStatus (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Checks whether the specified FSMC flag is set or not. More...
 
void FSMC_ClearFlag (uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
 Clears the FSMC's pending flags. More...
 
ITStatus FSMC_GetITStatus (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Checks whether the specified FSMC interrupt has occurred or not. More...
 
void FSMC_ClearITPendingBit (uint32_t FSMC_Bank, uint32_t FSMC_IT)
 Clears the FSMC's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the FSMC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
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+ + diff --git a/stm32f4xx__fsmc_8h__dep__incl.map b/stm32f4xx__fsmc_8h__dep__incl.map new file mode 100644 index 0000000..6f8d8c3 --- /dev/null +++ b/stm32f4xx__fsmc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__fsmc_8h__dep__incl.md5 b/stm32f4xx__fsmc_8h__dep__incl.md5 new file mode 100644 index 0000000..937a2e5 --- /dev/null +++ b/stm32f4xx__fsmc_8h__dep__incl.md5 @@ -0,0 +1 @@ +39d096d434b499ff0c9754fabe1b67db \ No newline at end of file diff --git a/stm32f4xx__fsmc_8h__dep__incl.png b/stm32f4xx__fsmc_8h__dep__incl.png new file mode 100644 index 0000000..9360440 Binary files /dev/null and b/stm32f4xx__fsmc_8h__dep__incl.png differ diff --git a/stm32f4xx__fsmc_8h__incl.map b/stm32f4xx__fsmc_8h__incl.map new file mode 100644 index 0000000..4897d92 --- /dev/null +++ b/stm32f4xx__fsmc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__fsmc_8h__incl.md5 b/stm32f4xx__fsmc_8h__incl.md5 new file mode 100644 index 0000000..7d31f1a --- /dev/null +++ b/stm32f4xx__fsmc_8h__incl.md5 @@ -0,0 +1 @@ +f0f1ba238281110a2555f2fa233b6b5b \ No newline at end of file diff --git a/stm32f4xx__fsmc_8h__incl.png b/stm32f4xx__fsmc_8h__incl.png new file mode 100644 index 0000000..0636eae Binary files /dev/null and b/stm32f4xx__fsmc_8h__incl.png differ diff --git a/stm32f4xx__fsmc_8h_source.html b/stm32f4xx__fsmc_8h_source.html new file mode 100644 index 0000000..84332b3 --- /dev/null +++ b/stm32f4xx__fsmc_8h_source.html @@ -0,0 +1,445 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_fsmc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + + + +
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+
stm32f4xx_fsmc.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_FSMC_H
+
31 #define __STM32F4xx_FSMC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
53 typedef struct
+
54 {
+
55  uint32_t FSMC_AddressSetupTime;
+
60  uint32_t FSMC_AddressHoldTime;
+
65  uint32_t FSMC_DataSetupTime;
+
70  uint32_t FSMC_BusTurnAroundDuration;
+
75  uint32_t FSMC_CLKDivision;
+
79  uint32_t FSMC_DataLatency;
+
87  uint32_t FSMC_AccessMode;
+
89 }FSMC_NORSRAMTimingInitTypeDef;
+
90 
+
94 typedef struct
+
95 {
+
96  uint32_t FSMC_Bank;
+
99  uint32_t FSMC_DataAddressMux;
+
103  uint32_t FSMC_MemoryType;
+
107  uint32_t FSMC_MemoryDataWidth;
+
110  uint32_t FSMC_BurstAccessMode;
+
114  uint32_t FSMC_AsynchronousWait;
+
118  uint32_t FSMC_WaitSignalPolarity;
+
122  uint32_t FSMC_WrapMode;
+
126  uint32_t FSMC_WaitSignalActive;
+
131  uint32_t FSMC_WriteOperation;
+
134  uint32_t FSMC_WaitSignal;
+
138  uint32_t FSMC_ExtendedMode;
+
141  uint32_t FSMC_WriteBurst;
+
144  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct;
+
146  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;
+
147 }FSMC_NORSRAMInitTypeDef;
+
148 
+
152 typedef struct
+
153 {
+
154  uint32_t FSMC_SetupTime;
+
160  uint32_t FSMC_WaitSetupTime;
+
166  uint32_t FSMC_HoldSetupTime;
+
173  uint32_t FSMC_HiZSetupTime;
+
178 }FSMC_NAND_PCCARDTimingInitTypeDef;
+
179 
+
183 typedef struct
+
184 {
+
185  uint32_t FSMC_Bank;
+
188  uint32_t FSMC_Waitfeature;
+
191  uint32_t FSMC_MemoryDataWidth;
+
194  uint32_t FSMC_ECC;
+
197  uint32_t FSMC_ECCPageSize;
+
200  uint32_t FSMC_TCLRSetupTime;
+
204  uint32_t FSMC_TARSetupTime;
+
208  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
+
210  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
+
211 }FSMC_NANDInitTypeDef;
+
212 
+
217 typedef struct
+
218 {
+
219  uint32_t FSMC_Waitfeature;
+
222  uint32_t FSMC_TCLRSetupTime;
+
226  uint32_t FSMC_TARSetupTime;
+
231  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct;
+
233  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct;
+
235  FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct;
+
236 }FSMC_PCCARDInitTypeDef;
+
237 
+
238 /* Exported constants --------------------------------------------------------*/
+
239 
+
247 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+
248 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+
249 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+
250 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+
251 
+
258 #define FSMC_Bank2_NAND ((uint32_t)0x00000010)
+
259 #define FSMC_Bank3_NAND ((uint32_t)0x00000100)
+
260 
+
267 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
+
268 
+
272 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+
273  ((BANK) == FSMC_Bank1_NORSRAM2) || \
+
274  ((BANK) == FSMC_Bank1_NORSRAM3) || \
+
275  ((BANK) == FSMC_Bank1_NORSRAM4))
+
276 
+
277 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+
278  ((BANK) == FSMC_Bank3_NAND))
+
279 
+
280 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+
281  ((BANK) == FSMC_Bank3_NAND) || \
+
282  ((BANK) == FSMC_Bank4_PCCARD))
+
283 
+
284 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+
285  ((BANK) == FSMC_Bank3_NAND) || \
+
286  ((BANK) == FSMC_Bank4_PCCARD))
+
287 
+
296 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+
297 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+
298 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+
299  ((MUX) == FSMC_DataAddressMux_Enable))
+
300 
+
308 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+
309 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+
310 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
+
311 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+
312  ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+
313  ((MEMORY) == FSMC_MemoryType_NOR))
+
314 
+
322 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+
323 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
+
324 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+
325  ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
326 
+
334 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+
335 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+
336 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+
337  ((STATE) == FSMC_BurstAccessMode_Enable))
+
338 
+
345 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
+
346 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
+
347 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+
348  ((STATE) == FSMC_AsynchronousWait_Enable))
+
349 
+
356 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+
357 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+
358 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+
359  ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
360 
+
367 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+
368 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
+
369 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+
370  ((MODE) == FSMC_WrapMode_Enable))
+
371 
+
378 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+
379 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+
380 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+
381  ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
382 
+
389 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+
390 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
+
391 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+
392  ((OPERATION) == FSMC_WriteOperation_Enable))
+
393 
+
400 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+
401 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
+
402 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+
403  ((SIGNAL) == FSMC_WaitSignal_Enable))
+
404 
+
411 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+
412 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
413 
+
414 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+
415  ((MODE) == FSMC_ExtendedMode_Enable))
+
416 
+
424 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+
425 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
+
426 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+
427  ((BURST) == FSMC_WriteBurst_Enable))
+
428 
+
435 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
436 
+
443 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
444 
+
451 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
452 
+
459 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
460 
+
467 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
468 
+
475 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
476 
+
483 #define FSMC_AccessMode_A ((uint32_t)0x00000000)
+
484 #define FSMC_AccessMode_B ((uint32_t)0x10000000)
+
485 #define FSMC_AccessMode_C ((uint32_t)0x20000000)
+
486 #define FSMC_AccessMode_D ((uint32_t)0x30000000)
+
487 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+
488  ((MODE) == FSMC_AccessMode_B) || \
+
489  ((MODE) == FSMC_AccessMode_C) || \
+
490  ((MODE) == FSMC_AccessMode_D))
+
491 
+
506 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
+
507 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
+
508 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+
509  ((FEATURE) == FSMC_Waitfeature_Enable))
+
510 
+
518 #define FSMC_ECC_Disable ((uint32_t)0x00000000)
+
519 #define FSMC_ECC_Enable ((uint32_t)0x00000040)
+
520 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+
521  ((STATE) == FSMC_ECC_Enable))
+
522 
+
529 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+
530 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+
531 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+
532 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+
533 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+
534 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
+
535 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+
536  ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+
537  ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+
538  ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+
539  ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+
540  ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
541 
+
548 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
549 
+
556 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
557 
+
564 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
565 
+
572 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
573 
+
580 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
581 
+
588 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
589 
+
596 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
+
597 #define FSMC_IT_Level ((uint32_t)0x00000010)
+
598 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
+
599 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+
600 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+
601  ((IT) == FSMC_IT_Level) || \
+
602  ((IT) == FSMC_IT_FallingEdge))
+
603 
+
610 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+
611 #define FSMC_FLAG_Level ((uint32_t)0x00000002)
+
612 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+
613 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+
614 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+
615  ((FLAG) == FSMC_FLAG_Level) || \
+
616  ((FLAG) == FSMC_FLAG_FallingEdge) || \
+
617  ((FLAG) == FSMC_FLAG_FEMPT))
+
618 
+
619 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
620 
+
632 /* Exported macro ------------------------------------------------------------*/
+
633 /* Exported functions --------------------------------------------------------*/
+
634 
+
635 /* NOR/SRAM Controller functions **********************************************/
+
636 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+
637 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+
638 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+
639 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
640 
+
641 /* NAND Controller functions **************************************************/
+
642 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+
643 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+
644 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+
645 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
646 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
647 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+
648 
+
649 /* PCCARD Controller functions ************************************************/
+
650 void FSMC_PCCARDDeInit(void);
+
651 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+
652 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+
653 void FSMC_PCCARDCmd(FunctionalState NewState);
+
654 
+
655 /* Interrupts and flags management functions **********************************/
+
656 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+
657 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+
658 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+
659 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
660 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
661 
+
662 #ifdef __cplusplus
+
663 }
+
664 #endif
+
665 
+
666 #endif /*__STM32F4xx_FSMC_H */
+
667 
+
675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime
uint32_t FSMC_DataSetupTime
Definition: stm32f4xx_fsmc.h:65
+
FSMC_GetFlagStatus
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Checks whether the specified FSMC flag is set or not.
Definition: stm32f4xx_fsmc.c:812
+
FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal
uint32_t FSMC_WaitSignal
Definition: stm32f4xx_fsmc.h:134
+
FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime
uint32_t FSMC_TCLRSetupTime
Definition: stm32f4xx_fsmc.h:222
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime
uint32_t FSMC_AddressSetupTime
Definition: stm32f4xx_fsmc.h:55
+
FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct
Definition: stm32f4xx_fsmc.h:146
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration
uint32_t FSMC_BusTurnAroundDuration
Definition: stm32f4xx_fsmc.h:70
+
FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth
uint32_t FSMC_MemoryDataWidth
Definition: stm32f4xx_fsmc.h:191
+
FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
Definition: stm32f4xx_fsmc.h:235
+
FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst
uint32_t FSMC_WriteBurst
Definition: stm32f4xx_fsmc.h:141
+
FSMC_NANDDeInit
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NAND Banks registers to their default reset values.
Definition: stm32f4xx_fsmc.c:342
+
FSMC_NANDInit
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Initializes the FSMC NAND Banks according to the specified parameters in the FSMC_NANDInitStruct.
Definition: stm32f4xx_fsmc.c:373
+
FSMC_NANDInitTypeDef
FSMC NAND Init structure definition.
Definition: stm32f4xx_fsmc.h:183
+
FSMC_NANDInitTypeDef::FSMC_ECCPageSize
uint32_t FSMC_ECCPageSize
Definition: stm32f4xx_fsmc.h:197
+
FSMC_NORSRAMInitTypeDef::FSMC_WrapMode
uint32_t FSMC_WrapMode
Definition: stm32f4xx_fsmc.h:122
+
FSMC_NORSRAMInitTypeDef::FSMC_Bank
uint32_t FSMC_Bank
Definition: stm32f4xx_fsmc.h:96
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode
uint32_t FSMC_AccessMode
Definition: stm32f4xx_fsmc.h:87
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency
uint32_t FSMC_DataLatency
Definition: stm32f4xx_fsmc.h:79
+
FSMC_ClearFlag
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
Clears the FSMC's pending flags.
Definition: stm32f4xx_fsmc.c:862
+
FSMC_GetITStatus
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Checks whether the specified FSMC interrupt has occurred or not.
Definition: stm32f4xx_fsmc.c:897
+
FSMC_NORSRAMInitTypeDef
FSMC NOR/SRAM Init structure definition.
Definition: stm32f4xx_fsmc.h:94
+
FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime
uint32_t FSMC_SetupTime
Definition: stm32f4xx_fsmc.h:154
+
FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait
uint32_t FSMC_AsynchronousWait
Definition: stm32f4xx_fsmc.h:114
+
FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
Definition: stm32f4xx_fsmc.h:144
+
FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode
uint32_t FSMC_BurstAccessMode
Definition: stm32f4xx_fsmc.h:110
+
FSMC_NANDECCCmd
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the FSMC NAND ECC feature.
Definition: stm32f4xx_fsmc.c:507
+
FSMC_NORSRAMInit
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Initializes the FSMC NOR/SRAM Banks according to the specified parameters in the FSMC_NORSRAMInitStru...
Definition: stm32f4xx_fsmc.c:156
+
FSMC_GetECC
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
Returns the error correction code register value.
Definition: stm32f4xx_fsmc.c:546
+
FSMC_PCCARDInitTypeDef
FSMC PCCARD Init structure definition.
Definition: stm32f4xx_fsmc.h:217
+
FSMC_PCCARDStructInit
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Fills each FSMC_PCCARDInitStruct member with its default value.
Definition: stm32f4xx_fsmc.c:679
+
FSMC_NORSRAMStructInit
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
Fills each FSMC_NORSRAMInitStruct member with its default value.
Definition: stm32f4xx_fsmc.c:238
+
FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime
uint32_t FSMC_TARSetupTime
Definition: stm32f4xx_fsmc.h:226
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision
uint32_t FSMC_CLKDivision
Definition: stm32f4xx_fsmc.h:75
+
FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime
uint32_t FSMC_HiZSetupTime
Definition: stm32f4xx_fsmc.h:173
+
FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime
uint32_t FSMC_AddressHoldTime
Definition: stm32f4xx_fsmc.h:60
+
FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
Definition: stm32f4xx_fsmc.h:231
+
FSMC_NORSRAMDeInit
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
De-initializes the FSMC NOR/SRAM Banks registers to their default reset values.
Definition: stm32f4xx_fsmc.c:129
+
FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime
uint32_t FSMC_TCLRSetupTime
Definition: stm32f4xx_fsmc.h:200
+
FSMC_NANDInitTypeDef::FSMC_TARSetupTime
uint32_t FSMC_TARSetupTime
Definition: stm32f4xx_fsmc.h:204
+
FSMC_PCCARDDeInit
void FSMC_PCCARDDeInit(void)
De-initializes the FSMC PCCARD Bank registers to their default reset values.
Definition: stm32f4xx_fsmc.c:610
+
FSMC_PCCARDCmd
void FSMC_PCCARDCmd(FunctionalState NewState)
Enables or disables the PCCARD Memory Bank.
Definition: stm32f4xx_fsmc.c:705
+
FSMC_NANDInitTypeDef::FSMC_ECC
uint32_t FSMC_ECC
Definition: stm32f4xx_fsmc.h:194
+
FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation
uint32_t FSMC_WriteOperation
Definition: stm32f4xx_fsmc.h:131
+
FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive
uint32_t FSMC_WaitSignalActive
Definition: stm32f4xx_fsmc.h:126
+
FSMC_NANDInitTypeDef::FSMC_Waitfeature
uint32_t FSMC_Waitfeature
Definition: stm32f4xx_fsmc.h:188
+
FSMC_PCCARDInit
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef *FSMC_PCCARDInitStruct)
Initializes the FSMC PCCARD Bank according to the specified parameters in the FSMC_PCCARDInitStruct.
Definition: stm32f4xx_fsmc.c:627
+
FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime
uint32_t FSMC_WaitSetupTime
Definition: stm32f4xx_fsmc.h:160
+
FSMC_NAND_PCCARDTimingInitTypeDef
Timing parameters For FSMC NAND and PCCARD Banks.
Definition: stm32f4xx_fsmc.h:152
+
FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime
uint32_t FSMC_HoldSetupTime
Definition: stm32f4xx_fsmc.h:166
+
FSMC_NORSRAMCmd
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NOR/SRAM Memory Bank.
Definition: stm32f4xx_fsmc.c:269
+
FSMC_NORSRAMTimingInitTypeDef
Timing parameters For NOR/SRAM Banks.
Definition: stm32f4xx_fsmc.h:53
+
FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode
uint32_t FSMC_ExtendedMode
Definition: stm32f4xx_fsmc.h:138
+
FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
Definition: stm32f4xx_fsmc.h:210
+
FSMC_NORSRAMInitTypeDef::FSMC_MemoryType
uint32_t FSMC_MemoryType
Definition: stm32f4xx_fsmc.h:103
+
FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity
uint32_t FSMC_WaitSignalPolarity
Definition: stm32f4xx_fsmc.h:118
+
FSMC_ClearITPendingBit
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
Clears the FSMC's interrupt pending bits.
Definition: stm32f4xx_fsmc.c:948
+
FSMC_NANDInitTypeDef::FSMC_Bank
uint32_t FSMC_Bank
Definition: stm32f4xx_fsmc.h:185
+
FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux
uint32_t FSMC_DataAddressMux
Definition: stm32f4xx_fsmc.h:99
+
FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
Definition: stm32f4xx_fsmc.h:208
+
FSMC_NANDCmd
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
Enables or disables the specified NAND Memory Bank.
Definition: stm32f4xx_fsmc.c:467
+
FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth
uint32_t FSMC_MemoryDataWidth
Definition: stm32f4xx_fsmc.h:107
+
FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
Definition: stm32f4xx_fsmc.h:233
+
FSMC_PCCARDInitTypeDef::FSMC_Waitfeature
uint32_t FSMC_Waitfeature
Definition: stm32f4xx_fsmc.h:219
+
FSMC_ITConfig
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
Enables or disables the specified FSMC interrupts.
Definition: stm32f4xx_fsmc.c:752
+
FSMC_NANDStructInit
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
Fills each FSMC_NANDInitStruct member with its default value.
Definition: stm32f4xx_fsmc.c:438
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__gpio_8c.html b/stm32f4xx__gpio_8c.html new file mode 100644 index 0000000..43d8841 --- /dev/null +++ b/stm32f4xx__gpio_8c.html @@ -0,0 +1,230 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_gpio.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
stm32f4xx_gpio.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the GPIO peripheral: +More...

+
#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_gpio.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void GPIO_DeInit (GPIO_TypeDef *GPIOx)
 De-initializes the GPIOx peripheral registers to their default reset values. More...
 
void GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
 Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. More...
 
void GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
 Fills each GPIO_InitStruct member with its default value. More...
 
void GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Locks GPIO Pins configuration registers. More...
 
uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified input port pin. More...
 
uint16_t GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO input data port. More...
 
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified output data port bit. More...
 
uint16_t GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO output data port. More...
 
void GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Sets the selected data port bits. More...
 
void GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Clears the selected data port bits. More...
 
void GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 Sets or clears the selected data port bit. More...
 
void GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
 Writes data to the specified GPIO data port. More...
 
void GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Toggles the specified GPIO pins.. More...
 
void GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 Changes the mapping of the specified pin. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the GPIO peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • GPIO Read and Write
    • +
  • GPIO Alternate functions configuration
    • +
+
+
 ===============================================================================
+                      ##### How to use this driver #####
+ ===============================================================================       
+ [..]             
+   (#) Enable the GPIO AHB clock using the following function
+       RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+               
+   (#) Configure the GPIO pin(s) using GPIO_Init()
+       Four possible configuration are available for each pin:
+       (++) Input: Floating, Pull-up, Pull-down.
+       (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
+            Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed 
+            is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
+       (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open 
+            Drain (Pull-up, Pull-down or no Pull).
+       (++) Analog: required mode when a pin is to be used as ADC channel or DAC 
+            output.
+   
+   (#) Peripherals alternate function:
+       (++) For ADC and DAC, configure the desired pin in analog mode using 
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
+            (+++) For other peripherals (TIM, USART...):
+            (+++) Connect the pin to the desired peripherals' Alternate 
+                     Function (AF) using GPIO_PinAFConfig() function
+            (+++) Configure the desired pin in alternate function mode using
+                     GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+            (+++) Select the type, pull-up/pull-down and output speed via 
+                     GPIO_PuPd, GPIO_OType and GPIO_Speed members
+            (+++) Call GPIO_Init() function
+          
+   (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+            
+   (#) To set/reset the level of a pin configured in output mode use 
+       GPIO_SetBits()/GPIO_ResetBits()
+                 
+   (#) During and just after reset, the alternate functions are not 
+       active and the GPIO pins are configured in input floating mode (except JTAG
+       pins).
+  
+   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
+       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
+       priority over the GPIO function.
+  
+   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+       general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
+       The HSE has priority over the GPIO function.
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__gpio_8c__incl.map b/stm32f4xx__gpio_8c__incl.map new file mode 100644 index 0000000..024c5f6 --- /dev/null +++ b/stm32f4xx__gpio_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__gpio_8c__incl.md5 b/stm32f4xx__gpio_8c__incl.md5 new file mode 100644 index 0000000..495929e --- /dev/null +++ b/stm32f4xx__gpio_8c__incl.md5 @@ -0,0 +1 @@ +eccf55a166c00b5cb4f99660e18cafd0 \ No newline at end of file diff --git a/stm32f4xx__gpio_8c__incl.png b/stm32f4xx__gpio_8c__incl.png new file mode 100644 index 0000000..b3d7974 Binary files /dev/null and b/stm32f4xx__gpio_8c__incl.png differ diff --git a/stm32f4xx__gpio_8h.html b/stm32f4xx__gpio_8h.html new file mode 100644 index 0000000..9c77df4 --- /dev/null +++ b/stm32f4xx__gpio_8h.html @@ -0,0 +1,551 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_gpio.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Enumerations | +Functions
+
+
stm32f4xx_gpio.h File Reference
+
+
+ +

This file contains all the functions prototypes for the GPIO firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_gpio.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + +

+Classes

struct  GPIO_InitTypeDef
 GPIO Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_GPIO_ALL_PERIPH(PERIPH)
 
#define IS_GPIO_MODE(MODE)
 
+#define IS_GPIO_OTYPE(OTYPE)   (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
 
+#define GPIO_Speed_2MHz   GPIO_Low_Speed
 
+#define GPIO_Speed_25MHz   GPIO_Medium_Speed
 
+#define GPIO_Speed_50MHz   GPIO_Fast_Speed
 
+#define GPIO_Speed_100MHz   GPIO_High_Speed
 
#define IS_GPIO_SPEED(SPEED)
 
#define IS_GPIO_PUPD(PUPD)
 
+#define IS_GPIO_BIT_ACTION(ACTION)   (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
 
+#define GPIO_Pin_0   ((uint16_t)0x0001) /* Pin 0 selected */
 
+#define GPIO_Pin_1   ((uint16_t)0x0002) /* Pin 1 selected */
 
+#define GPIO_Pin_2   ((uint16_t)0x0004) /* Pin 2 selected */
 
+#define GPIO_Pin_3   ((uint16_t)0x0008) /* Pin 3 selected */
 
+#define GPIO_Pin_4   ((uint16_t)0x0010) /* Pin 4 selected */
 
+#define GPIO_Pin_5   ((uint16_t)0x0020) /* Pin 5 selected */
 
+#define GPIO_Pin_6   ((uint16_t)0x0040) /* Pin 6 selected */
 
+#define GPIO_Pin_7   ((uint16_t)0x0080) /* Pin 7 selected */
 
+#define GPIO_Pin_8   ((uint16_t)0x0100) /* Pin 8 selected */
 
+#define GPIO_Pin_9   ((uint16_t)0x0200) /* Pin 9 selected */
 
+#define GPIO_Pin_10   ((uint16_t)0x0400) /* Pin 10 selected */
 
+#define GPIO_Pin_11   ((uint16_t)0x0800) /* Pin 11 selected */
 
+#define GPIO_Pin_12   ((uint16_t)0x1000) /* Pin 12 selected */
 
+#define GPIO_Pin_13   ((uint16_t)0x2000) /* Pin 13 selected */
 
+#define GPIO_Pin_14   ((uint16_t)0x4000) /* Pin 14 selected */
 
+#define GPIO_Pin_15   ((uint16_t)0x8000) /* Pin 15 selected */
 
+#define GPIO_Pin_All   ((uint16_t)0xFFFF) /* All pins selected */
 
+#define GPIO_PIN_MASK   ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
 
+#define IS_GPIO_PIN(PIN)   (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
 
#define IS_GET_GPIO_PIN(PIN)
 
+#define GPIO_PinSource0   ((uint8_t)0x00)
 
+#define GPIO_PinSource1   ((uint8_t)0x01)
 
+#define GPIO_PinSource2   ((uint8_t)0x02)
 
+#define GPIO_PinSource3   ((uint8_t)0x03)
 
+#define GPIO_PinSource4   ((uint8_t)0x04)
 
+#define GPIO_PinSource5   ((uint8_t)0x05)
 
+#define GPIO_PinSource6   ((uint8_t)0x06)
 
+#define GPIO_PinSource7   ((uint8_t)0x07)
 
+#define GPIO_PinSource8   ((uint8_t)0x08)
 
+#define GPIO_PinSource9   ((uint8_t)0x09)
 
+#define GPIO_PinSource10   ((uint8_t)0x0A)
 
+#define GPIO_PinSource11   ((uint8_t)0x0B)
 
+#define GPIO_PinSource12   ((uint8_t)0x0C)
 
+#define GPIO_PinSource13   ((uint8_t)0x0D)
 
+#define GPIO_PinSource14   ((uint8_t)0x0E)
 
+#define GPIO_PinSource15   ((uint8_t)0x0F)
 
#define IS_GPIO_PIN_SOURCE(PINSOURCE)
 
+#define GPIO_AF_RTC_50Hz   ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
 AF 0 selection.
 
+#define GPIO_AF_MCO   ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
 
+#define GPIO_AF_TAMPER   ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
 
+#define GPIO_AF_SWJ   ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
 
+#define GPIO_AF_TRACE   ((uint8_t)0x00) /* TRACE Alternate Function mapping */
 
+#define GPIO_AF_TIM1   ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
 AF 1 selection.
 
+#define GPIO_AF_TIM2   ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
 
+#define GPIO_AF_TIM3   ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
 AF 2 selection.
 
+#define GPIO_AF_TIM4   ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
 
+#define GPIO_AF_TIM5   ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
 
+#define GPIO_AF_TIM8   ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
 AF 3 selection.
 
+#define GPIO_AF_TIM9   ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
 
+#define GPIO_AF_TIM10   ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
 
+#define GPIO_AF_TIM11   ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
 
+#define GPIO_AF_I2C1   ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
 AF 4 selection.
 
+#define GPIO_AF_I2C2   ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
 
+#define GPIO_AF_I2C3   ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
 
+#define GPIO_AF_SPI1   ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
 AF 5 selection.
 
+#define GPIO_AF_SPI2   ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
 
+#define GPIO_AF5_SPI3   ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF_SPI4   ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
 
+#define GPIO_AF_SPI5   ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
 
+#define GPIO_AF_SPI6   ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
 
+#define GPIO_AF_SPI3   ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
 AF 6 selection.
 
+#define GPIO_AF6_SPI2   ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF6_SPI4   ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF6_SPI5   ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
 
+#define GPIO_AF_SAI1   ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
 
+#define GPIO_AF_USART1   ((uint8_t)0x07) /* USART1 Alternate Function mapping */
 AF 7 selection.
 
+#define GPIO_AF_USART2   ((uint8_t)0x07) /* USART2 Alternate Function mapping */
 
+#define GPIO_AF_USART3   ((uint8_t)0x07) /* USART3 Alternate Function mapping */
 
+#define GPIO_AF7_SPI3   ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
 
+#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
 AF 7 selection Legacy.
 
+#define GPIO_AF_UART4   ((uint8_t)0x08) /* UART4 Alternate Function mapping */
 AF 8 selection.
 
+#define GPIO_AF_UART5   ((uint8_t)0x08) /* UART5 Alternate Function mapping */
 
+#define GPIO_AF_USART6   ((uint8_t)0x08) /* USART6 Alternate Function mapping */
 
+#define GPIO_AF_UART7   ((uint8_t)0x08) /* UART7 Alternate Function mapping */
 
+#define GPIO_AF_UART8   ((uint8_t)0x08) /* UART8 Alternate Function mapping */
 
+#define GPIO_AF_CAN1   ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
 AF 9 selection.
 
+#define GPIO_AF_CAN2   ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
 
+#define GPIO_AF_TIM12   ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
 
+#define GPIO_AF_TIM13   ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
 
+#define GPIO_AF_TIM14   ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
 
+#define GPIO_AF9_I2C2   ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
 
+#define GPIO_AF9_I2C3   ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
 
+#define GPIO_AF_OTG_FS   ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
 AF 10 selection.
 
+#define GPIO_AF_OTG_HS   ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
 
+#define GPIO_AF_ETH   ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
 AF 11 selection.
 
+#define GPIO_AF_FSMC   ((uint8_t)0xC) /* FSMC Alternate Function mapping */
 AF 12 selection.
 
+#define GPIO_AF_OTG_HS_FS   ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
 
+#define GPIO_AF_SDIO   ((uint8_t)0xC) /* SDIO Alternate Function mapping */
 
+#define GPIO_AF_DCMI   ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
 AF 13 selection.
 
+#define GPIO_AF_LTDC   ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
 AF 14 selection.
 
+#define GPIO_AF_EVENTOUT   ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
 AF 15 selection.
 
#define IS_GPIO_AF(AF)
 
+#define GPIO_Mode_AIN   GPIO_Mode_AN
 
+#define GPIO_AF_OTG1_FS   GPIO_AF_OTG_FS
 
+#define GPIO_AF_OTG2_HS   GPIO_AF_OTG_HS
 
+#define GPIO_AF_OTG2_FS   GPIO_AF_OTG_HS_FS
 
+ + + + + + + + + + + + + + + + +

+Enumerations

enum  GPIOMode_TypeDef { GPIO_Mode_IN = 0x00, +GPIO_Mode_OUT = 0x01, +GPIO_Mode_AF = 0x02, +GPIO_Mode_AN = 0x03 + }
 GPIO Configuration Mode enumeration. More...
 
enum  GPIOOType_TypeDef { GPIO_OType_PP = 0x00, +GPIO_OType_OD = 0x01 + }
 GPIO Output type enumeration.
 
enum  GPIOSpeed_TypeDef { GPIO_Low_Speed = 0x00, +GPIO_Medium_Speed = 0x01, +GPIO_Fast_Speed = 0x02, +GPIO_High_Speed = 0x03 + }
 GPIO Output Maximum frequency enumeration. More...
 
enum  GPIOPuPd_TypeDef { GPIO_PuPd_NOPULL = 0x00, +GPIO_PuPd_UP = 0x01, +GPIO_PuPd_DOWN = 0x02 + }
 GPIO Configuration PullUp PullDown enumeration.
 
enum  BitAction { Bit_RESET = 0, +Bit_SET + }
 GPIO Bit SET and Bit RESET enumeration.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void GPIO_DeInit (GPIO_TypeDef *GPIOx)
 De-initializes the GPIOx peripheral registers to their default reset values. More...
 
void GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
 Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. More...
 
void GPIO_StructInit (GPIO_InitTypeDef *GPIO_InitStruct)
 Fills each GPIO_InitStruct member with its default value. More...
 
void GPIO_PinLockConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Locks GPIO Pins configuration registers. More...
 
uint8_t GPIO_ReadInputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified input port pin. More...
 
uint16_t GPIO_ReadInputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO input data port. More...
 
uint8_t GPIO_ReadOutputDataBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Reads the specified output data port bit. More...
 
uint16_t GPIO_ReadOutputData (GPIO_TypeDef *GPIOx)
 Reads the specified GPIO output data port. More...
 
void GPIO_SetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Sets the selected data port bits. More...
 
void GPIO_ResetBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Clears the selected data port bits. More...
 
void GPIO_WriteBit (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 Sets or clears the selected data port bit. More...
 
void GPIO_Write (GPIO_TypeDef *GPIOx, uint16_t PortVal)
 Writes data to the specified GPIO data port. More...
 
void GPIO_ToggleBits (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 Toggles the specified GPIO pins.. More...
 
void GPIO_PinAFConfig (GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 Changes the mapping of the specified pin. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the GPIO firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__gpio_8h__dep__incl.map b/stm32f4xx__gpio_8h__dep__incl.map new file mode 100644 index 0000000..bb163dc --- /dev/null +++ b/stm32f4xx__gpio_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__gpio_8h__dep__incl.md5 b/stm32f4xx__gpio_8h__dep__incl.md5 new file mode 100644 index 0000000..e190ff5 --- /dev/null +++ b/stm32f4xx__gpio_8h__dep__incl.md5 @@ -0,0 +1 @@ +651cf835c8279b68652b7366d59cda43 \ No newline at end of file diff --git a/stm32f4xx__gpio_8h__dep__incl.png b/stm32f4xx__gpio_8h__dep__incl.png new file mode 100644 index 0000000..86feb0d Binary files /dev/null and b/stm32f4xx__gpio_8h__dep__incl.png differ diff --git a/stm32f4xx__gpio_8h__incl.map b/stm32f4xx__gpio_8h__incl.map new file mode 100644 index 0000000..b817392 --- /dev/null +++ b/stm32f4xx__gpio_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__gpio_8h__incl.md5 b/stm32f4xx__gpio_8h__incl.md5 new file mode 100644 index 0000000..7d8a0cc --- /dev/null +++ b/stm32f4xx__gpio_8h__incl.md5 @@ -0,0 +1 @@ +1b18f8d4e55055088d6609e8f6aae32e \ No newline at end of file diff --git a/stm32f4xx__gpio_8h__incl.png b/stm32f4xx__gpio_8h__incl.png new file mode 100644 index 0000000..9a3f4db Binary files /dev/null and b/stm32f4xx__gpio_8h__incl.png differ diff --git a/stm32f4xx__gpio_8h_source.html b/stm32f4xx__gpio_8h_source.html new file mode 100644 index 0000000..7588a8f --- /dev/null +++ b/stm32f4xx__gpio_8h_source.html @@ -0,0 +1,480 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_gpio.h Source File + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+
stm32f4xx_gpio.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_GPIO_H
+
31 #define __STM32F4xx_GPIO_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
50 #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+
51  ((PERIPH) == GPIOB) || \
+
52  ((PERIPH) == GPIOC) || \
+
53  ((PERIPH) == GPIOD) || \
+
54  ((PERIPH) == GPIOE) || \
+
55  ((PERIPH) == GPIOF) || \
+
56  ((PERIPH) == GPIOG) || \
+
57  ((PERIPH) == GPIOH) || \
+
58  ((PERIPH) == GPIOI) || \
+
59  ((PERIPH) == GPIOJ) || \
+
60  ((PERIPH) == GPIOK))
+
61 
+
65 typedef enum
+
66 {
+
67  GPIO_Mode_IN = 0x00,
+
68  GPIO_Mode_OUT = 0x01,
+
69  GPIO_Mode_AF = 0x02,
+
70  GPIO_Mode_AN = 0x03
+
71 }GPIOMode_TypeDef;
+
72 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
+
73  ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
74 
+
78 typedef enum
+
79 {
+
80  GPIO_OType_PP = 0x00,
+
81  GPIO_OType_OD = 0x01
+
82 }GPIOOType_TypeDef;
+
83 #define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
84 
+
85 
+
89 typedef enum
+
90 {
+
91  GPIO_Low_Speed = 0x00,
+
92  GPIO_Medium_Speed = 0x01,
+
93  GPIO_Fast_Speed = 0x02,
+
94  GPIO_High_Speed = 0x03
+
95 }GPIOSpeed_TypeDef;
+
96 
+
97 /* Add legacy definition */
+
98 #define GPIO_Speed_2MHz GPIO_Low_Speed
+
99 #define GPIO_Speed_25MHz GPIO_Medium_Speed
+
100 #define GPIO_Speed_50MHz GPIO_Fast_Speed
+
101 #define GPIO_Speed_100MHz GPIO_High_Speed
+
102 
+
103 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
+
104  ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
+
105 
+
109 typedef enum
+
110 {
+
111  GPIO_PuPd_NOPULL = 0x00,
+
112  GPIO_PuPd_UP = 0x01,
+
113  GPIO_PuPd_DOWN = 0x02
+
114 }GPIOPuPd_TypeDef;
+
115 #define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+
116  ((PUPD) == GPIO_PuPd_DOWN))
+
117 
+
121 typedef enum
+
122 {
+
123  Bit_RESET = 0,
+
124  Bit_SET
+
125 }BitAction;
+
126 #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
127 
+
128 
+
132 typedef struct
+
133 {
+
134  uint32_t GPIO_Pin;
+
137  GPIOMode_TypeDef GPIO_Mode;
+
140  GPIOSpeed_TypeDef GPIO_Speed;
+
143  GPIOOType_TypeDef GPIO_OType;
+
146  GPIOPuPd_TypeDef GPIO_PuPd;
+
148 }GPIO_InitTypeDef;
+
149 
+
150 /* Exported constants --------------------------------------------------------*/
+
151 
+
159 #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
+
160 #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
+
161 #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
+
162 #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
+
163 #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
+
164 #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
+
165 #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
+
166 #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
+
167 #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
+
168 #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
+
169 #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
+
170 #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
+
171 #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
+
172 #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
+
173 #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
+
174 #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
+
175 #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
+
176 
+
177 #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+
178 #define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+
179 #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+
180  ((PIN) == GPIO_Pin_1) || \
+
181  ((PIN) == GPIO_Pin_2) || \
+
182  ((PIN) == GPIO_Pin_3) || \
+
183  ((PIN) == GPIO_Pin_4) || \
+
184  ((PIN) == GPIO_Pin_5) || \
+
185  ((PIN) == GPIO_Pin_6) || \
+
186  ((PIN) == GPIO_Pin_7) || \
+
187  ((PIN) == GPIO_Pin_8) || \
+
188  ((PIN) == GPIO_Pin_9) || \
+
189  ((PIN) == GPIO_Pin_10) || \
+
190  ((PIN) == GPIO_Pin_11) || \
+
191  ((PIN) == GPIO_Pin_12) || \
+
192  ((PIN) == GPIO_Pin_13) || \
+
193  ((PIN) == GPIO_Pin_14) || \
+
194  ((PIN) == GPIO_Pin_15))
+
195 
+
203 #define GPIO_PinSource0 ((uint8_t)0x00)
+
204 #define GPIO_PinSource1 ((uint8_t)0x01)
+
205 #define GPIO_PinSource2 ((uint8_t)0x02)
+
206 #define GPIO_PinSource3 ((uint8_t)0x03)
+
207 #define GPIO_PinSource4 ((uint8_t)0x04)
+
208 #define GPIO_PinSource5 ((uint8_t)0x05)
+
209 #define GPIO_PinSource6 ((uint8_t)0x06)
+
210 #define GPIO_PinSource7 ((uint8_t)0x07)
+
211 #define GPIO_PinSource8 ((uint8_t)0x08)
+
212 #define GPIO_PinSource9 ((uint8_t)0x09)
+
213 #define GPIO_PinSource10 ((uint8_t)0x0A)
+
214 #define GPIO_PinSource11 ((uint8_t)0x0B)
+
215 #define GPIO_PinSource12 ((uint8_t)0x0C)
+
216 #define GPIO_PinSource13 ((uint8_t)0x0D)
+
217 #define GPIO_PinSource14 ((uint8_t)0x0E)
+
218 #define GPIO_PinSource15 ((uint8_t)0x0F)
+
219 
+
220 #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+
221  ((PINSOURCE) == GPIO_PinSource1) || \
+
222  ((PINSOURCE) == GPIO_PinSource2) || \
+
223  ((PINSOURCE) == GPIO_PinSource3) || \
+
224  ((PINSOURCE) == GPIO_PinSource4) || \
+
225  ((PINSOURCE) == GPIO_PinSource5) || \
+
226  ((PINSOURCE) == GPIO_PinSource6) || \
+
227  ((PINSOURCE) == GPIO_PinSource7) || \
+
228  ((PINSOURCE) == GPIO_PinSource8) || \
+
229  ((PINSOURCE) == GPIO_PinSource9) || \
+
230  ((PINSOURCE) == GPIO_PinSource10) || \
+
231  ((PINSOURCE) == GPIO_PinSource11) || \
+
232  ((PINSOURCE) == GPIO_PinSource12) || \
+
233  ((PINSOURCE) == GPIO_PinSource13) || \
+
234  ((PINSOURCE) == GPIO_PinSource14) || \
+
235  ((PINSOURCE) == GPIO_PinSource15))
+
236 
+
246 #define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+
247 #define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+
248 #define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+
249 #define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+
250 #define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+
251 
+
255 #define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+
256 #define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+
257 
+
261 #define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+
262 #define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+
263 #define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+
264 
+
268 #define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+
269 #define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
+
270 #define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
+
271 #define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
+
272 
+
276 #define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+
277 #define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+
278 #define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+
279 
+
283 #define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
+
284 #define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
+
285 #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
+
286 #define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
+
287 #define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+
288 #define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+
289 
+
293 #define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+
294 #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
+
295 #define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
+
296 #define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
+
297 #define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+
298 
+
302 #define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+
303 #define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+
304 #define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+
305 #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
+
306 
+
310 #define GPIO_AF_I2S3ext GPIO_AF7_SPI3
+
311 
+
315 #define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+
316 #define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+
317 #define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
+
318 #define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
+
319 #define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+
320 
+
324 #define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
+
325 #define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
+
326 #define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
+
327 #define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+
328 #define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+
329 
+
330 #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
+
331 #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
+
332 
+
336 #define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
+
337 #define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
+
338 
+
342 #define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+
343 
+
347 #if defined (STM32F40_41xxx)
+
348 #define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
+
349 #endif /* STM32F40_41xxx */
+
350 
+
351 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
352 #define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+
353 #endif /* STM32F427_437xx || STM32F429_439xx */
+
354 
+
355 #define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
+
356 #define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+
357 
+
361 #define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+
362 
+
367 #define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+
368 
+
372 #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
373 
+
374 #if defined (STM32F40_41xxx)
+
375 #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+
376  ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+
377  ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+
378  ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+
379  ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+
380  ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+
381  ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+
382  ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+
383  ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+
384  ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+
385  ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+
386  ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
+
387  ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
+
388  ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
+
389  ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+
390  ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
+
391  ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
+
392  ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
+
393 #endif /* STM32F40_41xxx */
+
394 
+
395 #if defined (STM32F401xx)
+
396 #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+
397  ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+
398  ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+
399  ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+
400  ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+
401  ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+
402  ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+
403  ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+
404  ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+
405  ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+
406  ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+
407  ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
+
408  ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+
409  ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
+
410 #endif /* STM32F401xx */
+
411 
+
412 #if defined (STM32F411xE)
+
413 #define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
+
414 #endif /* STM32F411xE */
+
415 
+
416 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
417 #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
+
418  ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
+
419  ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
+
420  ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
+
421  ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
+
422  ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
+
423  ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
+
424  ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
+
425  ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
+
426  ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
+
427  ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
+
428  ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
+
429  ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
+
430  ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
+
431  ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
+
432  ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
+
433  ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
+
434  ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
+
435  ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
+
436  ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
+
437  ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
+
438  ((AF) == GPIO_AF_LTDC))
+
439 #endif /* STM32F427_437xx || STM32F429_439xx */
+
440 
+
449 #define GPIO_Mode_AIN GPIO_Mode_AN
+
450 
+
451 #define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
+
452 #define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
+
453 #define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
+
454 
+
463 /* Exported macro ------------------------------------------------------------*/
+
464 /* Exported functions --------------------------------------------------------*/
+
465 
+
466 /* Function used to set the GPIO configuration to the default reset state ****/
+
467 void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
468 
+
469 /* Initialization and Configuration functions *********************************/
+
470 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+
471 void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+
472 void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
473 
+
474 /* GPIO Read and Write functions **********************************************/
+
475 uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
476 uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+
477 uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
478 uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+
479 void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
480 void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
481 void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+
482 void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
483 void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
484 
+
485 /* GPIO Alternate functions configuration function ****************************/
+
486 void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
487 
+
488 #ifdef __cplusplus
+
489 }
+
490 #endif
+
491 
+
492 #endif /*__STM32F4xx_GPIO_H */
+
493 
+
502 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
GPIOOType_TypeDef
GPIOOType_TypeDef
GPIO Output type enumeration.
Definition: stm32f4xx_gpio.h:78
+
GPIO_Fast_Speed
Definition: stm32f4xx_gpio.h:93
+
GPIO_ReadInputDataBit
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
Definition: stm32f4xx_gpio.c:323
+
GPIO_Medium_Speed
Definition: stm32f4xx_gpio.h:92
+
GPIO_InitTypeDef::GPIO_PuPd
GPIOPuPd_TypeDef GPIO_PuPd
Definition: stm32f4xx_gpio.h:146
+
GPIOSpeed_TypeDef
GPIOSpeed_TypeDef
GPIO Output Maximum frequency enumeration.
Definition: stm32f4xx_gpio.h:89
+
GPIOPuPd_TypeDef
GPIOPuPd_TypeDef
GPIO Configuration PullUp PullDown enumeration.
Definition: stm32f4xx_gpio.h:109
+
GPIO_PinAFConfig
void GPIO_PinAFConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
Changes the mapping of the specified pin.
Definition: stm32f4xx_gpio.c:579
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
GPIO_ToggleBits
void GPIO_ToggleBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pins..
Definition: stm32f4xx_gpio.c:496
+
GPIO_ReadOutputDataBit
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified output data port bit.
Definition: stm32f4xx_gpio.c:366
+
GPIO_ReadOutputData
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
Reads the specified GPIO output data port.
Definition: stm32f4xx_gpio.c:392
+
GPIOMode_TypeDef
GPIOMode_TypeDef
GPIO Configuration Mode enumeration.
Definition: stm32f4xx_gpio.h:65
+
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f4xx.h:989
+
GPIO_PinLockConfig
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
Definition: stm32f4xx_gpio.c:277
+
GPIO_InitTypeDef::GPIO_Pin
uint32_t GPIO_Pin
Definition: stm32f4xx_gpio.h:134
+
GPIO_Mode_IN
Definition: stm32f4xx_gpio.h:67
+
GPIO_InitTypeDef::GPIO_Mode
GPIOMode_TypeDef GPIO_Mode
Definition: stm32f4xx_gpio.h:137
+
GPIO_StructInit
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
Fills each GPIO_InitStruct member with its default value.
Definition: stm32f4xx_gpio.c:254
+
GPIO_WriteBit
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
Sets or clears the selected data port bit.
Definition: stm32f4xx_gpio.c:455
+
GPIO_Init
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
Definition: stm32f4xx_gpio.c:202
+
GPIO_SetBits
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Sets the selected data port bits.
Definition: stm32f4xx_gpio.c:412
+
GPIO_InitTypeDef
GPIO Init structure definition.
Definition: stm32f4xx_gpio.h:132
+
GPIO_Mode_AF
Definition: stm32f4xx_gpio.h:69
+
GPIO_Write
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
Writes data to the specified GPIO data port.
Definition: stm32f4xx_gpio.c:480
+
GPIO_ResetBits
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Clears the selected data port bits.
Definition: stm32f4xx_gpio.c:433
+
GPIO_InitTypeDef::GPIO_OType
GPIOOType_TypeDef GPIO_OType
Definition: stm32f4xx_gpio.h:143
+
GPIO_Low_Speed
Definition: stm32f4xx_gpio.h:91
+
GPIO_InitTypeDef::GPIO_Speed
GPIOSpeed_TypeDef GPIO_Speed
Definition: stm32f4xx_gpio.h:140
+
GPIO_Mode_AN
Definition: stm32f4xx_gpio.h:70
+
GPIO_High_Speed
Definition: stm32f4xx_gpio.h:94
+
BitAction
BitAction
GPIO Bit SET and Bit RESET enumeration.
Definition: stm32f4xx_gpio.h:121
+
GPIO_ReadInputData
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
Reads the specified GPIO input data port.
Definition: stm32f4xx_gpio.c:349
+
GPIO_DeInit
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
De-initializes the GPIOx peripheral registers to their default reset values.
Definition: stm32f4xx_gpio.c:127
+
GPIO_Mode_OUT
Definition: stm32f4xx_gpio.h:68
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash_8c.html b/stm32f4xx__hash_8c.html new file mode 100644 index 0000000..b75c1ca --- /dev/null +++ b/stm32f4xx__hash_8c.html @@ -0,0 +1,281 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_hash.c File Reference + + + + + + + + + + +
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+Functions
+
+
stm32f4xx_hash.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the HASH / HMAC Processor (HASH) peripheral: +More...

+
#include "stm32f4xx_hash.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_hash.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void HASH_DeInit (void)
 De-initializes the HASH peripheral registers to their default reset values. More...
 
void HASH_Init (HASH_InitTypeDef *HASH_InitStruct)
 Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure. More...
 
void HASH_StructInit (HASH_InitTypeDef *HASH_InitStruct)
 Fills each HASH_InitStruct member with its default value. More...
 
void HASH_Reset (void)
 Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message. More...
 
void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
 Configure the Number of valid bits in last word of the message. More...
 
void HASH_DataIn (uint32_t Data)
 Writes data in the Data Input FIFO. More...
 
uint8_t HASH_GetInFIFOWordsNbr (void)
 Returns the number of words already pushed into the IN FIFO. More...
 
void HASH_GetDigest (HASH_MsgDigest *HASH_MessageDigest)
 Provides the message digest result. More...
 
void HASH_StartDigest (void)
 Starts the message padding and calculation of the final message. More...
 
void HASH_SaveContext (HASH_Context *HASH_ContextSave)
 Save the Hash peripheral Context. More...
 
void HASH_RestoreContext (HASH_Context *HASH_ContextRestore)
 Restore the Hash peripheral Context. More...
 
void HASH_AutoStartDigest (FunctionalState NewState)
 Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer. More...
 
void HASH_DMACmd (FunctionalState NewState)
 Enables or disables the HASH DMA interface. More...
 
void HASH_ITConfig (uint32_t HASH_IT, FunctionalState NewState)
 Enables or disables the specified HASH interrupts. More...
 
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
 Checks whether the specified HASH flag is set or not. More...
 
void HASH_ClearFlag (uint32_t HASH_FLAG)
 Clears the HASH flags. More...
 
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
 Checks whether the specified HASH interrupt has occurred or not. More...
 
void HASH_ClearITPendingBit (uint32_t HASH_IT)
 Clears the HASH interrupt pending bit(s). More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the HASH / HMAC Processor (HASH) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration functions
    • +
  • Message Digest generation functions
    • +
  • context swapping functions
    • +
  • DMA interface function
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================      
+                 ##### How to use this driver #####
+ ===================================================================
+            
+ *** HASH operation : *** 
+ ========================                 
+ [..]
+   (#) Enable the HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
+             
+   (#) Initialise the HASH using HASH_Init() function. 
+                 
+   (#) Reset the HASH processor core, so that the HASH will be ready 
+       to compute he message digest of a new message by using HASH_Reset() function.
+  
+   (#) Enable the HASH controller using the HASH_Cmd() function. 
+                  
+   (#) if using DMA for Data input transfer, Activate the DMA Request 
+       using HASH_DMACmd() function 
+                      
+   (#) if DMA is not used for data transfer, use HASH_DataIn() function 
+       to enter data to IN FIFO.
+               
+            
+   (#) Configure the Number of valid bits in last word of the message 
+       using HASH_SetLastWordValidBitsNbr() function.
+               
+   (#) if the message length is not an exact multiple of 512 bits, 
+       then the function HASH_StartDigest() must be called to launch the computation
+       of the final digest.     
+               
+   (#) Once computed, the digest can be read using HASH_GetDigest() function.         
+                     
+   (#) To control HASH events you can use one of the following wo methods:
+       (++) Check on HASH flags using the HASH_GetFlagStatus() function.  
+       (++) Use HASH interrupts through the function HASH_ITConfig() at 
+            initialization phase and HASH_GetITStatus() function into 
+            interrupt routines in hashing phase.
+            After checking on a flag you should clear it using HASH_ClearFlag()
+            function. And after checking on an interrupt event you should 
+            clear it using HASH_ClearITPendingBit() function.     
+                       
+   (#) Save and restore hash processor context using 
+       HASH_SaveContext() and HASH_RestoreContext() functions.     
+                
+  
+              
+ *** HMAC operation : *** 
+ ========================
+ [..] The HMAC algorithm is used for message authentication, by 
+      irreversibly binding the message being processed to a key chosen 
+      by the user. 
+      For HMAC specifications, refer to "HMAC: keyed-hashing for message 
+      authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
+            
+ [..] Basically, the HMAC algorithm consists of two nested hash operations:
+      HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
+      where:
+      (+) "pad" is a sequence of zeroes needed to extend the key to the 
+          length of the underlying hash function data block (that is 
+          512 bits for both the SHA-1 and MD5 hash algorithms)
+      (+) "|"   represents the concatenation operator 
+            
+           
+ [..]To compute the HMAC, four different phases are required:                  
+   (#) Initialise the HASH using HASH_Init() function to do HMAC 
+       operation. 
+                  
+   (#) The key (to be used for the inner hash function) is then given to the core. 
+       This operation follows the same mechanism as the one used to send the 
+       message in the hash operation (that is, by HASH_DataIn() function and, 
+       finally, HASH_StartDigest() function.
+            
+   (#) Once the last word has been entered and computation has started, 
+       the hash processor elaborates the key. It is then ready to accept the message
+       text using the same mechanism as the one used to send the message in the
+       hash operation.
+         
+   (#) After the first hash round, the hash processor returns "ready" to indicate 
+       that it is ready to receive the key to be used for the outer hash function 
+       (normally, this key is the same as the one used for the inner hash function). 
+       When the last word of the key is entered and computation starts, the HMAC 
+       result is made available using HASH_GetDigest() function.
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash_8c__incl.map b/stm32f4xx__hash_8c__incl.map new file mode 100644 index 0000000..d0be065 --- /dev/null +++ b/stm32f4xx__hash_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__hash_8c__incl.md5 b/stm32f4xx__hash_8c__incl.md5 new file mode 100644 index 0000000..2a9c99c --- /dev/null +++ b/stm32f4xx__hash_8c__incl.md5 @@ -0,0 +1 @@ +ff07e55eb8e8876397ecce7719fee5b2 \ No newline at end of file diff --git a/stm32f4xx__hash_8c__incl.png b/stm32f4xx__hash_8c__incl.png new file mode 100644 index 0000000..0879580 Binary files /dev/null and b/stm32f4xx__hash_8c__incl.png differ diff --git a/stm32f4xx__hash_8h.html b/stm32f4xx__hash_8h.html new file mode 100644 index 0000000..1c4604f --- /dev/null +++ b/stm32f4xx__hash_8h.html @@ -0,0 +1,278 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_hash.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Functions
+
+
stm32f4xx_hash.h File Reference
+
+
+ +

This file contains all the functions prototypes for the HASH firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_hash.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Classes

struct  HASH_InitTypeDef
 HASH Init structure definition. More...
 
struct  HASH_MsgDigest
 HASH message digest result structure definition. More...
 
struct  HASH_Context
 HASH context swapping structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define HASH_AlgoSelection_SHA1   ((uint32_t)0x0000)
 
#define HASH_AlgoSelection_SHA224   HASH_CR_ALGO_1
 
#define HASH_AlgoSelection_SHA256   HASH_CR_ALGO
 
#define HASH_AlgoSelection_MD5   HASH_CR_ALGO_0
 
#define IS_HASH_ALGOSELECTION(ALGOSELECTION)
 
#define HASH_AlgoMode_HASH   ((uint32_t)0x00000000)
 
#define HASH_AlgoMode_HMAC   HASH_CR_MODE
 
#define IS_HASH_ALGOMODE(ALGOMODE)
 
#define HASH_DataType_32b   ((uint32_t)0x0000)
 
#define HASH_DataType_16b   HASH_CR_DATATYPE_0
 
#define HASH_DataType_8b   HASH_CR_DATATYPE_1
 
#define HASH_DataType_1b   HASH_CR_DATATYPE
 
#define IS_HASH_DATATYPE(DATATYPE)
 
#define HASH_HMACKeyType_ShortKey   ((uint32_t)0x00000000)
 
#define HASH_HMACKeyType_LongKey   HASH_CR_LKEY
 
#define IS_HASH_HMAC_KEYTYPE(KEYTYPE)
 
+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS)   ((VALIDBITS) <= 0x1F)
 
#define HASH_IT_DINI   HASH_IMR_DINIM
 
#define HASH_IT_DCI   HASH_IMR_DCIM
 
+#define IS_HASH_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
 
+#define IS_HASH_GET_IT(IT)   (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
 
#define HASH_FLAG_DINIS   HASH_SR_DINIS
 
#define HASH_FLAG_DCIS   HASH_SR_DCIS
 
#define HASH_FLAG_DMAS   HASH_SR_DMAS
 
#define HASH_FLAG_BUSY   HASH_SR_BUSY
 
#define HASH_FLAG_DINNE   HASH_CR_DINNE
 
#define IS_HASH_GET_FLAG(FLAG)
 
#define IS_HASH_CLEAR_FLAG(FLAG)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void HASH_DeInit (void)
 De-initializes the HASH peripheral registers to their default reset values. More...
 
void HASH_Init (HASH_InitTypeDef *HASH_InitStruct)
 Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structure. More...
 
void HASH_StructInit (HASH_InitTypeDef *HASH_InitStruct)
 Fills each HASH_InitStruct member with its default value. More...
 
void HASH_Reset (void)
 Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new message. More...
 
void HASH_DataIn (uint32_t Data)
 Writes data in the Data Input FIFO. More...
 
uint8_t HASH_GetInFIFOWordsNbr (void)
 Returns the number of words already pushed into the IN FIFO. More...
 
void HASH_SetLastWordValidBitsNbr (uint16_t ValidNumber)
 Configure the Number of valid bits in last word of the message. More...
 
void HASH_StartDigest (void)
 Starts the message padding and calculation of the final message. More...
 
void HASH_AutoStartDigest (FunctionalState NewState)
 Enables or disables auto-start message padding and calculation of the final message digest at the end of DMA transfer. More...
 
void HASH_GetDigest (HASH_MsgDigest *HASH_MessageDigest)
 Provides the message digest result. More...
 
void HASH_SaveContext (HASH_Context *HASH_ContextSave)
 Save the Hash peripheral Context. More...
 
void HASH_RestoreContext (HASH_Context *HASH_ContextRestore)
 Restore the Hash peripheral Context. More...
 
void HASH_DMACmd (FunctionalState NewState)
 Enables or disables the HASH DMA interface. More...
 
void HASH_ITConfig (uint32_t HASH_IT, FunctionalState NewState)
 Enables or disables the specified HASH interrupts. More...
 
FlagStatus HASH_GetFlagStatus (uint32_t HASH_FLAG)
 Checks whether the specified HASH flag is set or not. More...
 
void HASH_ClearFlag (uint32_t HASH_FLAG)
 Clears the HASH flags. More...
 
ITStatus HASH_GetITStatus (uint32_t HASH_IT)
 Checks whether the specified HASH interrupt has occurred or not. More...
 
void HASH_ClearITPendingBit (uint32_t HASH_IT)
 Clears the HASH interrupt pending bit(s). More...
 
ErrorStatus HASH_SHA1 (uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HASH SHA1 digest. More...
 
ErrorStatus HMAC_SHA1 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HMAC SHA1 digest. More...
 
ErrorStatus HASH_MD5 (uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HASH MD5 digest. More...
 
ErrorStatus HMAC_MD5 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HMAC MD5 digest. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the HASH firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash_8h__dep__incl.map b/stm32f4xx__hash_8h__dep__incl.map new file mode 100644 index 0000000..04605cd --- /dev/null +++ b/stm32f4xx__hash_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__hash_8h__dep__incl.md5 b/stm32f4xx__hash_8h__dep__incl.md5 new file mode 100644 index 0000000..d447fcd --- /dev/null +++ b/stm32f4xx__hash_8h__dep__incl.md5 @@ -0,0 +1 @@ +6670b8e8ceb6da89850ffe78a6ea2643 \ No newline at end of file diff --git a/stm32f4xx__hash_8h__dep__incl.png b/stm32f4xx__hash_8h__dep__incl.png new file mode 100644 index 0000000..b9d8d45 Binary files /dev/null and b/stm32f4xx__hash_8h__dep__incl.png differ diff --git a/stm32f4xx__hash_8h__incl.map b/stm32f4xx__hash_8h__incl.map new file mode 100644 index 0000000..9695e93 --- /dev/null +++ b/stm32f4xx__hash_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__hash_8h__incl.md5 b/stm32f4xx__hash_8h__incl.md5 new file mode 100644 index 0000000..6c66a41 --- /dev/null +++ b/stm32f4xx__hash_8h__incl.md5 @@ -0,0 +1 @@ +e839a26f9c3dd9819a9ff8d912d53f3e \ No newline at end of file diff --git a/stm32f4xx__hash_8h__incl.png b/stm32f4xx__hash_8h__incl.png new file mode 100644 index 0000000..783c1ab Binary files /dev/null and b/stm32f4xx__hash_8h__incl.png differ diff --git a/stm32f4xx__hash_8h_source.html b/stm32f4xx__hash_8h_source.html new file mode 100644 index 0000000..7cea353 --- /dev/null +++ b/stm32f4xx__hash_8h_source.html @@ -0,0 +1,269 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_hash.h Source File + + + + + + + + + + +
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stm32f4xx_hash.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_HASH_H
+
31 #define __STM32F4xx_HASH_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
53 typedef struct
+
54 {
+
55  uint32_t HASH_AlgoSelection;
+
57  uint32_t HASH_AlgoMode;
+
59  uint32_t HASH_DataType;
+
62  uint32_t HASH_HMACKeyType;
+
64 }HASH_InitTypeDef;
+
65 
+
69 typedef struct
+
70 {
+
71  uint32_t Data[8];
+
75 } HASH_MsgDigest;
+
76 
+
80 typedef struct
+
81 {
+
82  uint32_t HASH_IMR;
+
83  uint32_t HASH_STR;
+
84  uint32_t HASH_CR;
+
85  uint32_t HASH_CSR[54];
+
86 }HASH_Context;
+
87 
+
88 /* Exported constants --------------------------------------------------------*/
+
89 
+
97 #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000)
+
98 #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1
+
99 #define HASH_AlgoSelection_SHA256 HASH_CR_ALGO
+
100 #define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0
+
102 #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+
103  ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
+
104  ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
+
105  ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+
106 
+
113 #define HASH_AlgoMode_HASH ((uint32_t)0x00000000)
+
114 #define HASH_AlgoMode_HMAC HASH_CR_MODE
+
116 #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+
117  ((ALGOMODE) == HASH_AlgoMode_HMAC))
+
118 
+
125 #define HASH_DataType_32b ((uint32_t)0x0000)
+
126 #define HASH_DataType_16b HASH_CR_DATATYPE_0
+
127 #define HASH_DataType_8b HASH_CR_DATATYPE_1
+
128 #define HASH_DataType_1b HASH_CR_DATATYPE
+
130 #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
+
131  ((DATATYPE) == HASH_DataType_16b)|| \
+
132  ((DATATYPE) == HASH_DataType_8b) || \
+
133  ((DATATYPE) == HASH_DataType_1b))
+
134 
+
141 #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000)
+
142 #define HASH_HMACKeyType_LongKey HASH_CR_LKEY
+
144 #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+
145  ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+
146 
+
153 #define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
+
154 
+
162 #define HASH_IT_DINI HASH_IMR_DINIM
+
163 #define HASH_IT_DCI HASH_IMR_DCIM
+
165 #define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
+
166 #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
+
167 
+
175 #define HASH_FLAG_DINIS HASH_SR_DINIS
+
176 #define HASH_FLAG_DCIS HASH_SR_DCIS
+
177 #define HASH_FLAG_DMAS HASH_SR_DMAS
+
178 #define HASH_FLAG_BUSY HASH_SR_BUSY
+
179 #define HASH_FLAG_DINNE HASH_CR_DINNE
+
181 #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
+
182  ((FLAG) == HASH_FLAG_DCIS) || \
+
183  ((FLAG) == HASH_FLAG_DMAS) || \
+
184  ((FLAG) == HASH_FLAG_BUSY) || \
+
185  ((FLAG) == HASH_FLAG_DINNE))
+
186 
+
187 #define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
+
188  ((FLAG) == HASH_FLAG_DCIS))
+
189 
+
198 /* Exported macro ------------------------------------------------------------*/
+
199 /* Exported functions --------------------------------------------------------*/
+
200 
+
201 /* Function used to set the HASH configuration to the default reset state ****/
+
202 void HASH_DeInit(void);
+
203 
+
204 /* HASH Configuration function ************************************************/
+
205 void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
+
206 void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
+
207 void HASH_Reset(void);
+
208 
+
209 /* HASH Message Digest generation functions ***********************************/
+
210 void HASH_DataIn(uint32_t Data);
+
211 uint8_t HASH_GetInFIFOWordsNbr(void);
+
212 void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
+
213 void HASH_StartDigest(void);
+
214 void HASH_AutoStartDigest(FunctionalState NewState);
+
215 void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
+
216 
+
217 /* HASH Context swapping functions ********************************************/
+
218 void HASH_SaveContext(HASH_Context* HASH_ContextSave);
+
219 void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
+
220 
+
221 /* HASH DMA interface function ************************************************/
+
222 void HASH_DMACmd(FunctionalState NewState);
+
223 
+
224 /* HASH Interrupts and flags management functions *****************************/
+
225 void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
+
226 FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
+
227 void HASH_ClearFlag(uint32_t HASH_FLAG);
+
228 ITStatus HASH_GetITStatus(uint32_t HASH_IT);
+
229 void HASH_ClearITPendingBit(uint32_t HASH_IT);
+
230 
+
231 /* High Level SHA1 functions **************************************************/
+
232 ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
+
233 ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
+
234  uint8_t *Input, uint32_t Ilen,
+
235  uint8_t Output[20]);
+
236 
+
237 /* High Level MD5 functions ***************************************************/
+
238 ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
+
239 ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
+
240  uint8_t *Input, uint32_t Ilen,
+
241  uint8_t Output[16]);
+
242 
+
243 #ifdef __cplusplus
+
244 }
+
245 #endif
+
246 
+
247 #endif /*__STM32F4xx_HASH_H */
+
248 
+
257 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
HASH_GetFlagStatus
FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
Checks whether the specified HASH flag is set or not.
Definition: stm32f4xx_hash.c:610
+
HASH_InitTypeDef::HASH_HMACKeyType
uint32_t HASH_HMACKeyType
Definition: stm32f4xx_hash.h:62
+
HASH_SHA1
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
Compute the HASH SHA1 digest.
Definition: stm32f4xx_hash_sha1.c:93
+
HASH_MD5
ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
Compute the HASH MD5 digest.
Definition: stm32f4xx_hash_md5.c:93
+
HASH_ITConfig
void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
Enables or disables the specified HASH interrupts.
Definition: stm32f4xx_hash.c:581
+
HASH_StructInit
void HASH_StructInit(HASH_InitTypeDef *HASH_InitStruct)
Fills each HASH_InitStruct member with its default value.
Definition: stm32f4xx_hash.c:225
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
HASH_SaveContext
void HASH_SaveContext(HASH_Context *HASH_ContextSave)
Save the Hash peripheral Context.
Definition: stm32f4xx_hash.c:396
+
HASH_DeInit
void HASH_DeInit(void)
De-initializes the HASH peripheral registers to their default reset values.
Definition: stm32f4xx_hash.c:171
+
HASH_AutoStartDigest
void HASH_AutoStartDigest(FunctionalState NewState)
Enables or disables auto-start message padding and calculation of the final message digest at the end...
Definition: stm32f4xx_hash.c:465
+
HASH_Context
HASH context swapping structure definition.
Definition: stm32f4xx_hash.h:80
+
HMAC_SHA1
ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
Compute the HMAC SHA1 digest.
Definition: stm32f4xx_hash_sha1.c:169
+
HASH_MsgDigest
HASH message digest result structure definition.
Definition: stm32f4xx_hash.h:69
+
HASH_Init
void HASH_Init(HASH_InitTypeDef *HASH_InitStruct)
Initializes the HASH peripheral according to the specified parameters in the HASH_InitStruct structur...
Definition: stm32f4xx_hash.c:191
+
HASH_ClearITPendingBit
void HASH_ClearITPendingBit(uint32_t HASH_IT)
Clears the HASH interrupt pending bit(s).
Definition: stm32f4xx_hash.c:701
+
HASH_Reset
void HASH_Reset(void)
Resets the HASH processor core, so that the HASH will be ready to compute the message digest of a new...
Definition: stm32f4xx_hash.c:249
+
HASH_DMACmd
void HASH_DMACmd(FunctionalState NewState)
Enables or disables the HASH DMA interface.
Definition: stm32f4xx_hash.c:489
+
HASH_InitTypeDef::HASH_DataType
uint32_t HASH_DataType
Definition: stm32f4xx_hash.h:59
+
HASH_StartDigest
void HASH_StartDigest(void)
Starts the message padding and calculation of the final message.
Definition: stm32f4xx_hash.c:353
+
HASH_RestoreContext
void HASH_RestoreContext(HASH_Context *HASH_ContextRestore)
Restore the Hash peripheral Context.
Definition: stm32f4xx_hash.c:418
+
HASH_DataIn
void HASH_DataIn(uint32_t Data)
Writes data in the Data Input FIFO.
Definition: stm32f4xx_hash.c:306
+
HASH_InitTypeDef::HASH_AlgoSelection
uint32_t HASH_AlgoSelection
Definition: stm32f4xx_hash.h:55
+
HASH_GetInFIFOWordsNbr
uint8_t HASH_GetInFIFOWordsNbr(void)
Returns the number of words already pushed into the IN FIFO.
Definition: stm32f4xx_hash.c:317
+
HASH_GetDigest
void HASH_GetDigest(HASH_MsgDigest *HASH_MessageDigest)
Provides the message digest result.
Definition: stm32f4xx_hash.c:335
+
HASH_ClearFlag
void HASH_ClearFlag(uint32_t HASH_FLAG)
Clears the HASH flags.
Definition: stm32f4xx_hash.c:651
+
HASH_InitTypeDef
HASH Init structure definition.
Definition: stm32f4xx_hash.h:53
+
HASH_GetITStatus
ITStatus HASH_GetITStatus(uint32_t HASH_IT)
Checks whether the specified HASH interrupt has occurred or not.
Definition: stm32f4xx_hash.c:667
+
HMAC_MD5
ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
Compute the HMAC MD5 digest.
Definition: stm32f4xx_hash_md5.c:168
+
HASH_SetLastWordValidBitsNbr
void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
Configure the Number of valid bits in last word of the message.
Definition: stm32f4xx_hash.c:291
+
HASH_InitTypeDef::HASH_AlgoMode
uint32_t HASH_AlgoMode
Definition: stm32f4xx_hash.h:57
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash__md5_8c.html b/stm32f4xx__hash__md5_8c.html new file mode 100644 index 0000000..9905dd0 --- /dev/null +++ b/stm32f4xx__hash__md5_8c.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_hash_md5.c File Reference + + + + + + + + + + +
+
+ + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_hash_md5.c File Reference
+
+
+ +

This file provides high level functions to compute the HASH MD5 and HMAC MD5 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral. +More...

+
#include "stm32f4xx_hash.h"
+
+Include dependency graph for stm32f4xx_hash_md5.c:
+
+
+ + +
+
+ + + +

+Macros

+#define MD5BUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + +

+Functions

ErrorStatus HASH_MD5 (uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HASH MD5 digest. More...
 
ErrorStatus HMAC_MD5 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
 Compute the HMAC MD5 digest. More...
 
+

Detailed Description

+

This file provides high level functions to compute the HASH MD5 and HMAC MD5 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
 ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable The HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
+  
+   (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
+  
+   (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
+
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash__md5_8c__incl.map b/stm32f4xx__hash__md5_8c__incl.map new file mode 100644 index 0000000..c292a1c --- /dev/null +++ b/stm32f4xx__hash__md5_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__hash__md5_8c__incl.md5 b/stm32f4xx__hash__md5_8c__incl.md5 new file mode 100644 index 0000000..605bbe6 --- /dev/null +++ b/stm32f4xx__hash__md5_8c__incl.md5 @@ -0,0 +1 @@ +053cc92d9656ad0cdc570c5f18c9f0e5 \ No newline at end of file diff --git a/stm32f4xx__hash__md5_8c__incl.png b/stm32f4xx__hash__md5_8c__incl.png new file mode 100644 index 0000000..b6e137d Binary files /dev/null and b/stm32f4xx__hash__md5_8c__incl.png differ diff --git a/stm32f4xx__hash__sha1_8c.html b/stm32f4xx__hash__sha1_8c.html new file mode 100644 index 0000000..b3e8935 --- /dev/null +++ b/stm32f4xx__hash__sha1_8c.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_hash_sha1.c File Reference + + + + + + + + + + +
+
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+Macros | +Functions
+
+
stm32f4xx_hash_sha1.c File Reference
+
+
+ +

This file provides high level functions to compute the HASH SHA1 and HMAC SHA1 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral. +More...

+
#include "stm32f4xx_hash.h"
+
+Include dependency graph for stm32f4xx_hash_sha1.c:
+
+
+ + +
+
+ + + +

+Macros

+#define SHA1BUSY_TIMEOUT   ((uint32_t) 0x00010000)
 
+ + + + + + + +

+Functions

ErrorStatus HASH_SHA1 (uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HASH SHA1 digest. More...
 
ErrorStatus HMAC_SHA1 (uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
 Compute the HMAC SHA1 digest. More...
 
+

Detailed Description

+

This file provides high level functions to compute the HASH SHA1 and HMAC SHA1 Digest of an input message. It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH peripheral.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
 ===================================================================
+                 ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable The HASH controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
+  
+   (#) Calculate the HASH SHA1 Digest using HASH_SHA1() function.
+  
+   (#) Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
+
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__hash__sha1_8c__incl.map b/stm32f4xx__hash__sha1_8c__incl.map new file mode 100644 index 0000000..a8a44ab --- /dev/null +++ b/stm32f4xx__hash__sha1_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__hash__sha1_8c__incl.md5 b/stm32f4xx__hash__sha1_8c__incl.md5 new file mode 100644 index 0000000..591a66c --- /dev/null +++ b/stm32f4xx__hash__sha1_8c__incl.md5 @@ -0,0 +1 @@ +2a672d1e34ca9893482a85bfdda2d5d4 \ No newline at end of file diff --git a/stm32f4xx__hash__sha1_8c__incl.png b/stm32f4xx__hash__sha1_8c__incl.png new file mode 100644 index 0000000..f918b8f Binary files /dev/null and b/stm32f4xx__hash__sha1_8c__incl.png differ diff --git a/stm32f4xx__i2c_8c.html b/stm32f4xx__i2c_8c.html new file mode 100644 index 0000000..1c774f7 --- /dev/null +++ b/stm32f4xx__i2c_8c.html @@ -0,0 +1,305 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_i2c.c File Reference + + + + + + + + + + +
+
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+Macros | +Functions
+
+
stm32f4xx_i2c.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C) +More...

+
#include "stm32f4xx_i2c.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_i2c.c:
+
+
+ + +
+
+ + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint16_t)0xFBF5) /*<! I2C registers Masks */
 
+#define FLAG_MASK   ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */
 
+#define ITEN_MASK   ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void I2C_DeInit (I2C_TypeDef *I2Cx)
 Deinitialize the I2Cx peripheral registers to their default reset values. More...
 
void I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
 Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. More...
 
void I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
 Fills each I2C_InitStruct member with its default value. More...
 
void I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C peripheral. More...
 
void I2C_AnalogFilterCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the Analog filter of I2C peripheral. More...
 
void I2C_DigitalFilterConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DigitalFilter)
 Configures the Digital noise filter of I2C peripheral. More...
 
void I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication START condition. More...
 
void I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication STOP condition. More...
 
void I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
 Transmits the address byte to select the slave device. More...
 
void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C acknowledge feature. More...
 
void I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
 Configures the specified I2C own address2. More...
 
void I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C dual addressing mode. More...
 
void I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C general call feature. More...
 
void I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C software reset. More...
 
void I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C Clock stretching. More...
 
void I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
 Selects the specified I2C fast mode duty cycle. More...
 
void I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
 Selects the specified I2C NACK position in master receiver mode. More...
 
void I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
 Drives the SMBusAlert pin high or low for the specified I2C. More...
 
void I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C ARP. More...
 
void I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
 Sends a data byte through the I2Cx peripheral. More...
 
uint8_t I2C_ReceiveData (I2C_TypeDef *I2Cx)
 Returns the most recent received data by the I2Cx peripheral. More...
 
void I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C PEC transfer. More...
 
void I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
 Selects the specified I2C PEC position. More...
 
void I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the PEC value calculation of the transferred bytes. More...
 
uint8_t I2C_GetPEC (I2C_TypeDef *I2Cx)
 Returns the PEC value for the specified I2C. More...
 
void I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C DMA requests. More...
 
void I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Specifies that the next DMA transfer is the last one. More...
 
uint16_t I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
 Reads the specified I2C register and returns its value. More...
 
void I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
 Enables or disables the specified I2C interrupts. More...
 
ErrorStatus I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 Checks whether the last I2Cx Event is equal to the one passed as parameter. More...
 
uint32_t I2C_GetLastEvent (I2C_TypeDef *I2Cx)
 Returns the last I2Cx Event. More...
 
FlagStatus I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Checks whether the specified I2C flag is set or not. More...
 
void I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Clears the I2Cx's pending flags. More...
 
ITStatus I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Checks whether the specified I2C interrupt has occurred or not. More...
 
void I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Clears the I2Cx's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Inter-integrated circuit (I2C)

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Data transfers
    • +
  • PEC management
    • +
  • DMA transfers management
    • +
  • Interrupts, events and flags management
    • +
+
+
===============================================================================
+                   ##### How to use this driver #####
+===============================================================================
+   [..]
+     (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+         function for I2C1, I2C2 or I2C3.
+ 
+     (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
+         RCC_AHBPeriphClockCmd() function. 
+ 
+     (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+            Function (AF) using GPIO_PinAFConfig() function
+       (++) Configure the desired pin in alternate function by:
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, pull-up/pull-down and output speed via 
+            GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function
+            Recommended configuration is Push-Pull, Pull-up, Open-Drain.
+            Add an external pull up if necessary (typically 4.7 KOhm).      
+         
+     (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
+         Address using the I2C_Init() function.
+ 
+     (#) Optionally you can enable/configure the following parameters without
+         re-initialization (i.e there is no need to call again I2C_Init() function):
+       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
+       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
+       (++) Enable the general call using the I2C_GeneralCallCmd() function
+       (++) Enable the clock stretching using I2C_StretchClockCmd() function
+       (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
+            function.
+       (++) Configure the NACK position for Master Receiver mode in case of 
+            2 bytes reception using the function I2C_NACKPositionConfig().  
+       (++) Enable the PEC Calculation using I2C_CalculatePEC() function
+       (++) For SMBus Mode: 
+         (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
+         (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
+ 
+     (#) Enable the NVIC and the corresponding interrupt using the function 
+         I2C_ITConfig() if you need to use interrupt mode. 
+ 
+     (#) When using the DMA mode 
+       (++) Configure the DMA using DMA_Init() function
+       (++) Active the needed channel Request using I2C_DMACmd() or
+            I2C_DMALastTransferCmd() function.
+       -@@- When using DMA mode, I2C interrupts may be used at the same time to
+            control the communication flow (Start/Stop/Ack... events and errors).
+  
+     (#) Enable the I2C using the I2C_Cmd() function.
+  
+     (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+         transfers.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__i2c_8c__incl.map b/stm32f4xx__i2c_8c__incl.map new file mode 100644 index 0000000..7052454 --- /dev/null +++ b/stm32f4xx__i2c_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__i2c_8c__incl.md5 b/stm32f4xx__i2c_8c__incl.md5 new file mode 100644 index 0000000..d549020 --- /dev/null +++ b/stm32f4xx__i2c_8c__incl.md5 @@ -0,0 +1 @@ +98fa5df68e59a4f9cc9e92a62a7c0c10 \ No newline at end of file diff --git a/stm32f4xx__i2c_8c__incl.png b/stm32f4xx__i2c_8c__incl.png new file mode 100644 index 0000000..f41347a Binary files /dev/null and b/stm32f4xx__i2c_8c__incl.png differ diff --git a/stm32f4xx__i2c_8h.html b/stm32f4xx__i2c_8h.html new file mode 100644 index 0000000..8b3a730 --- /dev/null +++ b/stm32f4xx__i2c_8h.html @@ -0,0 +1,539 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_i2c.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_i2c.h File Reference
+
+
+ +

This file contains all the functions prototypes for the I2C firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_i2c.h:
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

+ + + + + +

+Classes

struct  I2C_InitTypeDef
 I2C Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_I2C_ALL_PERIPH(PERIPH)
 
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
 
+#define I2C_Mode_I2C   ((uint16_t)0x0000)
 
+#define I2C_Mode_SMBusDevice   ((uint16_t)0x0002)
 
+#define I2C_Mode_SMBusHost   ((uint16_t)0x000A)
 
#define IS_I2C_MODE(MODE)
 
#define I2C_DutyCycle_16_9   ((uint16_t)0x4000)
 
#define I2C_DutyCycle_2   ((uint16_t)0xBFFF)
 
#define IS_I2C_DUTY_CYCLE(CYCLE)
 
+#define I2C_Ack_Enable   ((uint16_t)0x0400)
 
+#define I2C_Ack_Disable   ((uint16_t)0x0000)
 
#define IS_I2C_ACK_STATE(STATE)
 
+#define I2C_Direction_Transmitter   ((uint8_t)0x00)
 
+#define I2C_Direction_Receiver   ((uint8_t)0x01)
 
#define IS_I2C_DIRECTION(DIRECTION)
 
+#define I2C_AcknowledgedAddress_7bit   ((uint16_t)0x4000)
 
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
 
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)
 
+#define I2C_Register_CR1   ((uint8_t)0x00)
 
+#define I2C_Register_CR2   ((uint8_t)0x04)
 
+#define I2C_Register_OAR1   ((uint8_t)0x08)
 
+#define I2C_Register_OAR2   ((uint8_t)0x0C)
 
+#define I2C_Register_DR   ((uint8_t)0x10)
 
+#define I2C_Register_SR1   ((uint8_t)0x14)
 
+#define I2C_Register_SR2   ((uint8_t)0x18)
 
+#define I2C_Register_CCR   ((uint8_t)0x1C)
 
+#define I2C_Register_TRISE   ((uint8_t)0x20)
 
#define IS_I2C_REGISTER(REGISTER)
 
+#define I2C_NACKPosition_Next   ((uint16_t)0x0800)
 
+#define I2C_NACKPosition_Current   ((uint16_t)0xF7FF)
 
#define IS_I2C_NACK_POSITION(POSITION)
 
+#define I2C_SMBusAlert_Low   ((uint16_t)0x2000)
 
+#define I2C_SMBusAlert_High   ((uint16_t)0xDFFF)
 
#define IS_I2C_SMBUS_ALERT(ALERT)
 
+#define I2C_PECPosition_Next   ((uint16_t)0x0800)
 
+#define I2C_PECPosition_Current   ((uint16_t)0xF7FF)
 
#define IS_I2C_PEC_POSITION(POSITION)
 
+#define I2C_IT_BUF   ((uint16_t)0x0400)
 
+#define I2C_IT_EVT   ((uint16_t)0x0200)
 
+#define I2C_IT_ERR   ((uint16_t)0x0100)
 
+#define IS_I2C_CONFIG_IT(IT)   ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
 
+#define I2C_IT_SMBALERT   ((uint32_t)0x01008000)
 
+#define I2C_IT_TIMEOUT   ((uint32_t)0x01004000)
 
+#define I2C_IT_PECERR   ((uint32_t)0x01001000)
 
+#define I2C_IT_OVR   ((uint32_t)0x01000800)
 
+#define I2C_IT_AF   ((uint32_t)0x01000400)
 
+#define I2C_IT_ARLO   ((uint32_t)0x01000200)
 
+#define I2C_IT_BERR   ((uint32_t)0x01000100)
 
+#define I2C_IT_TXE   ((uint32_t)0x06000080)
 
+#define I2C_IT_RXNE   ((uint32_t)0x06000040)
 
+#define I2C_IT_STOPF   ((uint32_t)0x02000010)
 
+#define I2C_IT_ADD10   ((uint32_t)0x02000008)
 
+#define I2C_IT_BTF   ((uint32_t)0x02000004)
 
+#define I2C_IT_ADDR   ((uint32_t)0x02000002)
 
+#define I2C_IT_SB   ((uint32_t)0x02000001)
 
+#define IS_I2C_CLEAR_IT(IT)   ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
 
#define IS_I2C_GET_IT(IT)
 
+#define I2C_FLAG_DUALF   ((uint32_t)0x00800000)
 SR2 register flags.
 
+#define I2C_FLAG_SMBHOST   ((uint32_t)0x00400000)
 
+#define I2C_FLAG_SMBDEFAULT   ((uint32_t)0x00200000)
 
+#define I2C_FLAG_GENCALL   ((uint32_t)0x00100000)
 
+#define I2C_FLAG_TRA   ((uint32_t)0x00040000)
 
+#define I2C_FLAG_BUSY   ((uint32_t)0x00020000)
 
+#define I2C_FLAG_MSL   ((uint32_t)0x00010000)
 
+#define I2C_FLAG_SMBALERT   ((uint32_t)0x10008000)
 SR1 register flags.
 
+#define I2C_FLAG_TIMEOUT   ((uint32_t)0x10004000)
 
+#define I2C_FLAG_PECERR   ((uint32_t)0x10001000)
 
+#define I2C_FLAG_OVR   ((uint32_t)0x10000800)
 
+#define I2C_FLAG_AF   ((uint32_t)0x10000400)
 
+#define I2C_FLAG_ARLO   ((uint32_t)0x10000200)
 
+#define I2C_FLAG_BERR   ((uint32_t)0x10000100)
 
+#define I2C_FLAG_TXE   ((uint32_t)0x10000080)
 
+#define I2C_FLAG_RXNE   ((uint32_t)0x10000040)
 
+#define I2C_FLAG_STOPF   ((uint32_t)0x10000010)
 
+#define I2C_FLAG_ADD10   ((uint32_t)0x10000008)
 
+#define I2C_FLAG_BTF   ((uint32_t)0x10000004)
 
+#define I2C_FLAG_ADDR   ((uint32_t)0x10000002)
 
+#define I2C_FLAG_SB   ((uint32_t)0x10000001)
 
+#define IS_I2C_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
#define IS_I2C_GET_FLAG(FLAG)
 
#define I2C_EVENT_MASTER_MODE_SELECT   ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
 Communication start. More...
 
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED   ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
 Address Acknowledge. More...
 
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED   ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
 
+#define I2C_EVENT_MASTER_MODE_ADDRESS10   ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
 
#define I2C_EVENT_MASTER_BYTE_RECEIVED   ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
 Communication events. More...
 
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING   ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
 
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED   ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
 
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED   ((uint32_t)0x00020002) /* BUSY and ADDR flags */
 Communication start events. More...
 
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED   ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
 
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED   ((uint32_t)0x00820000) /* DUALF and BUSY flags */
 
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED   ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
 
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED   ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
 
#define I2C_EVENT_SLAVE_BYTE_RECEIVED   ((uint32_t)0x00020040) /* BUSY and RXNE flags */
 Communication events. More...
 
+#define I2C_EVENT_SLAVE_STOP_DETECTED   ((uint32_t)0x00000010) /* STOPF flag */
 
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED   ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
 
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING   ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
 
+#define I2C_EVENT_SLAVE_ACK_FAILURE   ((uint32_t)0x00000400) /* AF flag */
 
#define IS_I2C_EVENT(EVENT)
 
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= 0x3FF)
 
+#define IS_I2C_CLOCK_SPEED(SPEED)   (((SPEED) >= 0x1) && ((SPEED) <= 400000))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void I2C_DeInit (I2C_TypeDef *I2Cx)
 Deinitialize the I2Cx peripheral registers to their default reset values. More...
 
void I2C_Init (I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
 Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct. More...
 
void I2C_StructInit (I2C_InitTypeDef *I2C_InitStruct)
 Fills each I2C_InitStruct member with its default value. More...
 
void I2C_Cmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C peripheral. More...
 
void I2C_DigitalFilterConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DigitalFilter)
 Configures the Digital noise filter of I2C peripheral. More...
 
void I2C_AnalogFilterCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the Analog filter of I2C peripheral. More...
 
void I2C_GenerateSTART (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication START condition. More...
 
void I2C_GenerateSTOP (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Generates I2Cx communication STOP condition. More...
 
void I2C_Send7bitAddress (I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
 Transmits the address byte to select the slave device. More...
 
void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C acknowledge feature. More...
 
void I2C_OwnAddress2Config (I2C_TypeDef *I2Cx, uint8_t Address)
 Configures the specified I2C own address2. More...
 
void I2C_DualAddressCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C dual addressing mode. More...
 
void I2C_GeneralCallCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C general call feature. More...
 
void I2C_SoftwareResetCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C software reset. More...
 
void I2C_StretchClockCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C Clock stretching. More...
 
void I2C_FastModeDutyCycleConfig (I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
 Selects the specified I2C fast mode duty cycle. More...
 
void I2C_NACKPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
 Selects the specified I2C NACK position in master receiver mode. More...
 
void I2C_SMBusAlertConfig (I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
 Drives the SMBusAlert pin high or low for the specified I2C. More...
 
void I2C_ARPCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C ARP. More...
 
void I2C_SendData (I2C_TypeDef *I2Cx, uint8_t Data)
 Sends a data byte through the I2Cx peripheral. More...
 
uint8_t I2C_ReceiveData (I2C_TypeDef *I2Cx)
 Returns the most recent received data by the I2Cx peripheral. More...
 
void I2C_TransmitPEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C PEC transfer. More...
 
void I2C_PECPositionConfig (I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
 Selects the specified I2C PEC position. More...
 
void I2C_CalculatePEC (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the PEC value calculation of the transferred bytes. More...
 
uint8_t I2C_GetPEC (I2C_TypeDef *I2Cx)
 Returns the PEC value for the specified I2C. More...
 
void I2C_DMACmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Enables or disables the specified I2C DMA requests. More...
 
void I2C_DMALastTransferCmd (I2C_TypeDef *I2Cx, FunctionalState NewState)
 Specifies that the next DMA transfer is the last one. More...
 
uint16_t I2C_ReadRegister (I2C_TypeDef *I2Cx, uint8_t I2C_Register)
 Reads the specified I2C register and returns its value. More...
 
void I2C_ITConfig (I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
 Enables or disables the specified I2C interrupts. More...
 
ErrorStatus I2C_CheckEvent (I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
 Checks whether the last I2Cx Event is equal to the one passed as parameter. More...
 
uint32_t I2C_GetLastEvent (I2C_TypeDef *I2Cx)
 Returns the last I2Cx Event. More...
 
FlagStatus I2C_GetFlagStatus (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Checks whether the specified I2C flag is set or not. More...
 
void I2C_ClearFlag (I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
 Clears the I2Cx's pending flags. More...
 
ITStatus I2C_GetITStatus (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Checks whether the specified I2C interrupt has occurred or not. More...
 
void I2C_ClearITPendingBit (I2C_TypeDef *I2Cx, uint32_t I2C_IT)
 Clears the I2Cx's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the I2C firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__i2c_8h__dep__incl.map b/stm32f4xx__i2c_8h__dep__incl.map new file mode 100644 index 0000000..8c53f21 --- /dev/null +++ b/stm32f4xx__i2c_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__i2c_8h__dep__incl.md5 b/stm32f4xx__i2c_8h__dep__incl.md5 new file mode 100644 index 0000000..2e3a7cd --- /dev/null +++ b/stm32f4xx__i2c_8h__dep__incl.md5 @@ -0,0 +1 @@ +175d2d252e8c4bfdce7d43b507d7a687 \ No newline at end of file diff --git a/stm32f4xx__i2c_8h__dep__incl.png b/stm32f4xx__i2c_8h__dep__incl.png new file mode 100644 index 0000000..50f8eec Binary files /dev/null and b/stm32f4xx__i2c_8h__dep__incl.png differ diff --git a/stm32f4xx__i2c_8h__incl.map b/stm32f4xx__i2c_8h__incl.map new file mode 100644 index 0000000..36e6128 --- /dev/null +++ b/stm32f4xx__i2c_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__i2c_8h__incl.md5 b/stm32f4xx__i2c_8h__incl.md5 new file mode 100644 index 0000000..018819c --- /dev/null +++ b/stm32f4xx__i2c_8h__incl.md5 @@ -0,0 +1 @@ +88d4aff8a1405ec18d9aaef7ad5006fb \ No newline at end of file diff --git a/stm32f4xx__i2c_8h__incl.png b/stm32f4xx__i2c_8h__incl.png new file mode 100644 index 0000000..7c2bdc9 Binary files /dev/null and b/stm32f4xx__i2c_8h__incl.png differ diff --git a/stm32f4xx__i2c_8h_source.html b/stm32f4xx__i2c_8h_source.html new file mode 100644 index 0000000..9c59b7e --- /dev/null +++ b/stm32f4xx__i2c_8h_source.html @@ -0,0 +1,542 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_i2c.h Source File + + + + + + + + + + +
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stm32f4xx_i2c.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_I2C_H
+
31 #define __STM32F4xx_I2C_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t I2C_ClockSpeed;
+
59  uint16_t I2C_Mode;
+
62  uint16_t I2C_DutyCycle;
+
65  uint16_t I2C_OwnAddress1;
+
68  uint16_t I2C_Ack;
+
71  uint16_t I2C_AcknowledgedAddress;
+
73 }I2C_InitTypeDef;
+
74 
+
75 /* Exported constants --------------------------------------------------------*/
+
76 
+
77 
+
82 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+
83  ((PERIPH) == I2C2) || \
+
84  ((PERIPH) == I2C3))
+
85 
+
90 #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+
91 
+
100 #define I2C_Mode_I2C ((uint16_t)0x0000)
+
101 #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+
102 #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
+
103 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+
104  ((MODE) == I2C_Mode_SMBusDevice) || \
+
105  ((MODE) == I2C_Mode_SMBusHost))
+
106 
+
114 #define I2C_DutyCycle_16_9 ((uint16_t)0x4000)
+
115 #define I2C_DutyCycle_2 ((uint16_t)0xBFFF)
+
116 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+
117  ((CYCLE) == I2C_DutyCycle_2))
+
118 
+
126 #define I2C_Ack_Enable ((uint16_t)0x0400)
+
127 #define I2C_Ack_Disable ((uint16_t)0x0000)
+
128 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+
129  ((STATE) == I2C_Ack_Disable))
+
130 
+
138 #define I2C_Direction_Transmitter ((uint8_t)0x00)
+
139 #define I2C_Direction_Receiver ((uint8_t)0x01)
+
140 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+
141  ((DIRECTION) == I2C_Direction_Receiver))
+
142 
+
150 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+
151 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+
152 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+
153  ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+
154 
+
162 #define I2C_Register_CR1 ((uint8_t)0x00)
+
163 #define I2C_Register_CR2 ((uint8_t)0x04)
+
164 #define I2C_Register_OAR1 ((uint8_t)0x08)
+
165 #define I2C_Register_OAR2 ((uint8_t)0x0C)
+
166 #define I2C_Register_DR ((uint8_t)0x10)
+
167 #define I2C_Register_SR1 ((uint8_t)0x14)
+
168 #define I2C_Register_SR2 ((uint8_t)0x18)
+
169 #define I2C_Register_CCR ((uint8_t)0x1C)
+
170 #define I2C_Register_TRISE ((uint8_t)0x20)
+
171 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+
172  ((REGISTER) == I2C_Register_CR2) || \
+
173  ((REGISTER) == I2C_Register_OAR1) || \
+
174  ((REGISTER) == I2C_Register_OAR2) || \
+
175  ((REGISTER) == I2C_Register_DR) || \
+
176  ((REGISTER) == I2C_Register_SR1) || \
+
177  ((REGISTER) == I2C_Register_SR2) || \
+
178  ((REGISTER) == I2C_Register_CCR) || \
+
179  ((REGISTER) == I2C_Register_TRISE))
+
180 
+
188 #define I2C_NACKPosition_Next ((uint16_t)0x0800)
+
189 #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+
190 #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
+
191  ((POSITION) == I2C_NACKPosition_Current))
+
192 
+
200 #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+
201 #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
+
202 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+
203  ((ALERT) == I2C_SMBusAlert_High))
+
204 
+
212 #define I2C_PECPosition_Next ((uint16_t)0x0800)
+
213 #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+
214 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+
215  ((POSITION) == I2C_PECPosition_Current))
+
216 
+
224 #define I2C_IT_BUF ((uint16_t)0x0400)
+
225 #define I2C_IT_EVT ((uint16_t)0x0200)
+
226 #define I2C_IT_ERR ((uint16_t)0x0100)
+
227 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+
228 
+
236 #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+
237 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+
238 #define I2C_IT_PECERR ((uint32_t)0x01001000)
+
239 #define I2C_IT_OVR ((uint32_t)0x01000800)
+
240 #define I2C_IT_AF ((uint32_t)0x01000400)
+
241 #define I2C_IT_ARLO ((uint32_t)0x01000200)
+
242 #define I2C_IT_BERR ((uint32_t)0x01000100)
+
243 #define I2C_IT_TXE ((uint32_t)0x06000080)
+
244 #define I2C_IT_RXNE ((uint32_t)0x06000040)
+
245 #define I2C_IT_STOPF ((uint32_t)0x02000010)
+
246 #define I2C_IT_ADD10 ((uint32_t)0x02000008)
+
247 #define I2C_IT_BTF ((uint32_t)0x02000004)
+
248 #define I2C_IT_ADDR ((uint32_t)0x02000002)
+
249 #define I2C_IT_SB ((uint32_t)0x02000001)
+
250 
+
251 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
252 
+
253 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+
254  ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+
255  ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+
256  ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+
257  ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+
258  ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+
259  ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+
260 
+
272 #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+
273 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+
274 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+
275 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+
276 #define I2C_FLAG_TRA ((uint32_t)0x00040000)
+
277 #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+
278 #define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
279 
+
284 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+
285 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+
286 #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+
287 #define I2C_FLAG_OVR ((uint32_t)0x10000800)
+
288 #define I2C_FLAG_AF ((uint32_t)0x10000400)
+
289 #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+
290 #define I2C_FLAG_BERR ((uint32_t)0x10000100)
+
291 #define I2C_FLAG_TXE ((uint32_t)0x10000080)
+
292 #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+
293 #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+
294 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+
295 #define I2C_FLAG_BTF ((uint32_t)0x10000004)
+
296 #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+
297 #define I2C_FLAG_SB ((uint32_t)0x10000001)
+
298 
+
299 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
300 
+
301 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+
302  ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+
303  ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+
304  ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+
305  ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+
306  ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+
307  ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+
308  ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+
309  ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+
310  ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+
311  ((FLAG) == I2C_FLAG_SB))
+
312 
+
334 /* --EV5 */
+
335 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
336 
+
362 /* --EV6 */
+
363 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+
364 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+
365 /* --EV9 */
+
366 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
367 
+
397 /* Master RECEIVER mode -----------------------------*/
+
398 /* --EV7 */
+
399 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
400 
+
401 /* Master TRANSMITTER mode --------------------------*/
+
402 /* --EV8 */
+
403 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+
404 /* --EV8_2 */
+
405 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
406 
+
407 
+
440 /* --EV1 (all the events below are variants of EV1) */
+
441 /* 1) Case of One Single Address managed by the slave */
+
442 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+
443 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
444 
+
445 /* 2) Case of Dual address managed by the slave */
+
446 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+
447 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
448 
+
449 /* 3) Case of General Call enabled for the slave */
+
450 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
451 
+
479 /* Slave RECEIVER mode --------------------------*/
+
480 /* --EV2 */
+
481 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+
482 /* --EV4 */
+
483 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
484 
+
485 /* Slave TRANSMITTER mode -----------------------*/
+
486 /* --EV3 */
+
487 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+
488 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+
489 /* --EV3_2 */
+
490 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
491 
+
492 /*
+
493  ===============================================================================
+
494  End of Events Description
+
495  ===============================================================================
+
496  */
+
497 
+
498 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+
499  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+
500  ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+
501  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+
502  ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+
503  ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+
504  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+
505  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+
506  ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+
507  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+
508  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+
509  ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+
510  ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+
511  ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+
512  ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+
513  ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+
514  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+
515  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+
516  ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+
517  ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+
518 
+
526 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+
527 
+
535 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+
536 
+
544 /* Exported macro ------------------------------------------------------------*/
+
545 /* Exported functions --------------------------------------------------------*/
+
546 
+
547 /* Function used to set the I2C configuration to the default reset state *****/
+
548 void I2C_DeInit(I2C_TypeDef* I2Cx);
+
549 
+
550 /* Initialization and Configuration functions *********************************/
+
551 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+
552 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+
553 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
554 void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
+
555 void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
556 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
557 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
558 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+
559 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
560 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+
561 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
562 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
563 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
564 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
565 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
566 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+
567 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+
568 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
569 
+
570 /* Data transfers functions ***************************************************/
+
571 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+
572 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
573 
+
574 /* PEC management functions ***************************************************/
+
575 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
576 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+
577 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
578 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
579 
+
580 /* DMA transfers management functions *****************************************/
+
581 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
582 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
583 
+
584 /* Interrupts, events and flags management functions **************************/
+
585 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
586 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
587 
+
588 /*
+
589  ===============================================================================
+
590  I2C State Monitoring Functions
+
591  ===============================================================================
+
592  This I2C driver provides three different ways for I2C state monitoring
+
593  depending on the application requirements and constraints:
+
594 
+
595 
+
596  1. Basic state monitoring (Using I2C_CheckEvent() function)
+
597  -----------------------------------------------------------
+
598  It compares the status registers (SR1 and SR2) content to a given event
+
599  (can be the combination of one or more flags).
+
600  It returns SUCCESS if the current status includes the given flags
+
601  and returns ERROR if one or more flags are missing in the current status.
+
602 
+
603  - When to use
+
604  - This function is suitable for most applications as well as for startup
+
605  activity since the events are fully described in the product reference
+
606  manual (RM0090).
+
607  - It is also suitable for users who need to define their own events.
+
608 
+
609  - Limitations
+
610  - If an error occurs (ie. error flags are set besides to the monitored
+
611  flags), the I2C_CheckEvent() function may return SUCCESS despite
+
612  the communication hold or corrupted real state.
+
613  In this case, it is advised to use error interrupts to monitor
+
614  the error events and handle them in the interrupt IRQ handler.
+
615 
+
616  Note
+
617  For error management, it is advised to use the following functions:
+
618  - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+
619  - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+
620  Where x is the peripheral instance (I2C1, I2C2 ...)
+
621  - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
+
622  I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+
623  - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+
624  and/or I2C_GenerateStop() in order to clear the error flag and source
+
625  and return to correct communication status.
+
626 
+
627 
+
628  2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+
629  --------------------------------------------------------------------
+
630  Using the function I2C_GetLastEvent() which returns the image of both status
+
631  registers in a single word (uint32_t) (Status Register 2 value is shifted left
+
632  by 16 bits and concatenated to Status Register 1).
+
633 
+
634  - When to use
+
635  - This function is suitable for the same applications above but it
+
636  allows to overcome the mentioned limitation of I2C_GetFlagStatus()
+
637  function.
+
638  - The returned value could be compared to events already defined in
+
639  this file or to custom values defined by user.
+
640  This function is suitable when multiple flags are monitored at the
+
641  same time.
+
642  - At the opposite of I2C_CheckEvent() function, this function allows
+
643  user to choose when an event is accepted (when all events flags are
+
644  set and no other flags are set or just when the needed flags are set
+
645  like I2C_CheckEvent() function.
+
646 
+
647  - Limitations
+
648  - User may need to define his own events.
+
649  - Same remark concerning the error management is applicable for this
+
650  function if user decides to check only regular communication flags
+
651  (and ignores error flags).
+
652 
+
653 
+
654  3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+
655  -----------------------------------------------------------------------
+
656 
+
657  Using the function I2C_GetFlagStatus() which simply returns the status of
+
658  one single flag (ie. I2C_FLAG_RXNE ...).
+
659 
+
660  - When to use
+
661  - This function could be used for specific applications or in debug
+
662  phase.
+
663  - It is suitable when only one flag checking is needed (most I2C
+
664  events are monitored through multiple flags).
+
665  - Limitations:
+
666  - When calling this function, the Status register is accessed.
+
667  Some flags are cleared when the status register is accessed.
+
668  So checking the status of one Flag, may clear other ones.
+
669  - Function may need to be called twice or more in order to monitor
+
670  one single event.
+
671  */
+
672 
+
673 /*
+
674  ===============================================================================
+
675  1. Basic state monitoring
+
676  ===============================================================================
+
677  */
+
678 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+
679 /*
+
680  ===============================================================================
+
681  2. Advanced state monitoring
+
682  ===============================================================================
+
683  */
+
684 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+
685 /*
+
686  ===============================================================================
+
687  3. Flag-based state monitoring
+
688  ===============================================================================
+
689  */
+
690 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
691 
+
692 
+
693 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
694 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
695 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
696 
+
697 #ifdef __cplusplus
+
698 }
+
699 #endif
+
700 
+
701 #endif /*__STM32F4xx_I2C_H */
+
702 
+
711 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
I2C_GeneralCallCmd
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
Definition: stm32f4xx_i2c.c:552
+
I2C_TransmitPEC
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.
Definition: stm32f4xx_i2c.c:800
+
I2C_Send7bitAddress
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
Definition: stm32f4xx_i2c.c:451
+
I2C_InitTypeDef::I2C_AcknowledgedAddress
uint16_t I2C_AcknowledgedAddress
Definition: stm32f4xx_i2c.h:71
+
I2C_InitTypeDef::I2C_OwnAddress1
uint16_t I2C_OwnAddress1
Definition: stm32f4xx_i2c.h:65
+
I2C_GetLastEvent
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
Definition: stm32f4xx_i2c.c:1206
+
I2C_DualAddressCmd
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
Definition: stm32f4xx_i2c.c:528
+
I2C_CheckEvent
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
Checks whether the last I2Cx Event is equal to the one passed as parameter.
Definition: stm32f4xx_i2c.c:1158
+
I2C_PECPositionConfig
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
Definition: stm32f4xx_i2c.c:831
+
I2C_DigitalFilterConfig
void I2C_DigitalFilterConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DigitalFilter)
Configures the Digital noise filter of I2C peripheral.
Definition: stm32f4xx_i2c.c:371
+
I2C_Init
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
Definition: stm32f4xx_i2c.c:180
+
I2C_NACKPositionConfig
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
Definition: stm32f4xx_i2c.c:666
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
I2C_ARPCmd
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
Definition: stm32f4xx_i2c.c:718
+
I2C_GetITStatus
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
Definition: stm32f4xx_i2c.c:1372
+
I2C_InitTypeDef::I2C_DutyCycle
uint16_t I2C_DutyCycle
Definition: stm32f4xx_i2c.h:62
+
I2C_SMBusAlertConfig
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
Definition: stm32f4xx_i2c.c:694
+
I2C_GenerateSTOP
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
Definition: stm32f4xx_i2c.c:423
+
I2C_InitTypeDef::I2C_Ack
uint16_t I2C_Ack
Definition: stm32f4xx_i2c.h:68
+
I2C_ClearITPendingBit
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx's interrupt pending bits.
Definition: stm32f4xx_i2c.c:1432
+
I2C_DeInit
void I2C_DeInit(I2C_TypeDef *I2Cx)
Deinitialize the I2Cx peripheral registers to their default reset values.
Definition: stm32f4xx_i2c.c:137
+
I2C_Cmd
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
Definition: stm32f4xx_i2c.c:313
+
I2C_GetFlagStatus
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
Definition: stm32f4xx_i2c.c:1261
+
I2C_FastModeDutyCycleConfig
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
Definition: stm32f4xx_i2c.c:628
+
I2C_InitTypeDef::I2C_Mode
uint16_t I2C_Mode
Definition: stm32f4xx_i2c.h:59
+
I2C_SoftwareResetCmd
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
Definition: stm32f4xx_i2c.c:578
+
I2C_CalculatePEC
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
Definition: stm32f4xx_i2c.c:855
+
I2C_StretchClockCmd
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
Definition: stm32f4xx_i2c.c:602
+
I2C_InitTypeDef::I2C_ClockSpeed
uint32_t I2C_ClockSpeed
Definition: stm32f4xx_i2c.h:56
+
I2C_DMALastTransferCmd
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.
Definition: stm32f4xx_i2c.c:934
+
I2C_ITConfig
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
Definition: stm32f4xx_i2c.c:1099
+
I2C_AcknowledgeConfig
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
Definition: stm32f4xx_i2c.c:478
+
I2C_ClearFlag
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx's pending flags.
Definition: stm32f4xx_i2c.c:1338
+
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1020
+
I2C_ReadRegister
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
Definition: stm32f4xx_i2c.c:1072
+
I2C_ReceiveData
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
Definition: stm32f4xx_i2c.c:769
+
I2C_GetPEC
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
Definition: stm32f4xx_i2c.c:877
+
I2C_AnalogFilterCmd
void I2C_AnalogFilterCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the Analog filter of I2C peripheral.
Definition: stm32f4xx_i2c.c:342
+
I2C_StructInit
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
Definition: stm32f4xx_i2c.c:289
+
I2C_InitTypeDef
I2C Init structure definition.
Definition: stm32f4xx_i2c.h:54
+
I2C_DMACmd
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
Definition: stm32f4xx_i2c.c:910
+
I2C_SendData
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
Definition: stm32f4xx_i2c.c:756
+
I2C_OwnAddress2Config
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
Definition: stm32f4xx_i2c.c:501
+
I2C_GenerateSTART
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
Definition: stm32f4xx_i2c.c:399
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__iwdg_8c.html b/stm32f4xx__iwdg_8c.html new file mode 100644 index 0000000..3a9524d --- /dev/null +++ b/stm32f4xx__iwdg_8c.html @@ -0,0 +1,207 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_iwdg.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_iwdg.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral: +More...

+
#include "stm32f4xx_iwdg.h"
+
+Include dependency graph for stm32f4xx_iwdg.c:
+
+
+ + +
+
+ + + + + +

+Macros

+#define KR_KEY_RELOAD   ((uint16_t)0xAAAA)
 
+#define KR_KEY_ENABLE   ((uint16_t)0xCCCC)
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
 Enables or disables write access to IWDG_PR and IWDG_RLR registers. More...
 
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
 Sets IWDG Prescaler value. More...
 
void IWDG_SetReload (uint16_t Reload)
 Sets IWDG Reload value. More...
 
void IWDG_ReloadCounter (void)
 Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
void IWDG_Enable (void)
 Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
 Checks whether the specified IWDG flag is set or not. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Independent watchdog (IWDG) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Prescaler and Counter configuration
    • +
  • IWDG activation
    • +
  • Flag management
    • +
+
+
===============================================================================
+                         ##### IWDG features #####
+===============================================================================
+   [..]  
+     The IWDG can be started by either software or hardware (configurable
+     through option byte).
+             
+     The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+     thus stays active even if the main clock fails.
+     Once the IWDG is started, the LSI is forced ON and cannot be disabled
+     (LSI cannot be disabled too), and the counter starts counting down from 
+     the reset value of 0xFFF. When it reaches the end of count value (0x000)
+     a system reset is generated.
+     The IWDG counter should be reloaded at regular intervals to prevent
+     an MCU reset.
+                            
+     The IWDG is implemented in the VDD voltage domain that is still functional
+     in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).          
+             
+     IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+     reset occurs.
+             
+     Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+     The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
+     devices provide the capability to measure the LSI frequency (LSI clock
+     connected internally to TIM5 CH4 input capture). The measured value
+     can be used to have an IWDG timeout with an acceptable accuracy. 
+     For more information, please refer to the STM32F4xx Reference manual
+           
+                    ##### How to use this driver #####
+===============================================================================
+   [..]
+     (#) Enable write access to IWDG_PR and IWDG_RLR registers using
+         IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
+                
+     (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
+             
+     (#) Configure the IWDG counter value using IWDG_SetReload() function.
+         This value will be loaded in the IWDG counter each time the counter
+         is reloaded, then the IWDG will start counting down from this value.
+             
+     (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+         in software mode (no need to enable the LSI, it will be enabled
+         by hardware)
+              
+     (#) Then the application program must reload the IWDG counter at regular
+         intervals during normal operation to prevent an MCU reset, using
+         IWDG_ReloadCounter() function.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__iwdg_8c__incl.map b/stm32f4xx__iwdg_8c__incl.map new file mode 100644 index 0000000..5cfca14 --- /dev/null +++ b/stm32f4xx__iwdg_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__iwdg_8c__incl.md5 b/stm32f4xx__iwdg_8c__incl.md5 new file mode 100644 index 0000000..ce39213 --- /dev/null +++ b/stm32f4xx__iwdg_8c__incl.md5 @@ -0,0 +1 @@ +37768bc21e0fe4a1ab59dc6297a8c09c \ No newline at end of file diff --git a/stm32f4xx__iwdg_8c__incl.png b/stm32f4xx__iwdg_8c__incl.png new file mode 100644 index 0000000..b97360d Binary files /dev/null and b/stm32f4xx__iwdg_8c__incl.png differ diff --git a/stm32f4xx__iwdg_8h.html b/stm32f4xx__iwdg_8h.html new file mode 100644 index 0000000..69cdc34 --- /dev/null +++ b/stm32f4xx__iwdg_8h.html @@ -0,0 +1,201 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_iwdg.h File Reference + + + + + + + + + + +
+
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+Macros | +Functions
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+
stm32f4xx_iwdg.h File Reference
+
+
+ +

This file contains all the functions prototypes for the IWDG firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_iwdg.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define IWDG_WriteAccess_Enable   ((uint16_t)0x5555)
 
+#define IWDG_WriteAccess_Disable   ((uint16_t)0x0000)
 
#define IS_IWDG_WRITE_ACCESS(ACCESS)
 
+#define IWDG_Prescaler_4   ((uint8_t)0x00)
 
+#define IWDG_Prescaler_8   ((uint8_t)0x01)
 
+#define IWDG_Prescaler_16   ((uint8_t)0x02)
 
+#define IWDG_Prescaler_32   ((uint8_t)0x03)
 
+#define IWDG_Prescaler_64   ((uint8_t)0x04)
 
+#define IWDG_Prescaler_128   ((uint8_t)0x05)
 
+#define IWDG_Prescaler_256   ((uint8_t)0x06)
 
#define IS_IWDG_PRESCALER(PRESCALER)
 
+#define IWDG_FLAG_PVU   ((uint16_t)0x0001)
 
+#define IWDG_FLAG_RVU   ((uint16_t)0x0002)
 
+#define IS_IWDG_FLAG(FLAG)   (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
 
+#define IS_IWDG_RELOAD(RELOAD)   ((RELOAD) <= 0xFFF)
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

void IWDG_WriteAccessCmd (uint16_t IWDG_WriteAccess)
 Enables or disables write access to IWDG_PR and IWDG_RLR registers. More...
 
void IWDG_SetPrescaler (uint8_t IWDG_Prescaler)
 Sets IWDG Prescaler value. More...
 
void IWDG_SetReload (uint16_t Reload)
 Sets IWDG Reload value. More...
 
void IWDG_ReloadCounter (void)
 Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
void IWDG_Enable (void)
 Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). More...
 
FlagStatus IWDG_GetFlagStatus (uint16_t IWDG_FLAG)
 Checks whether the specified IWDG flag is set or not. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the IWDG firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__iwdg_8h__dep__incl.map b/stm32f4xx__iwdg_8h__dep__incl.map new file mode 100644 index 0000000..dca60c2 --- /dev/null +++ b/stm32f4xx__iwdg_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__iwdg_8h__dep__incl.md5 b/stm32f4xx__iwdg_8h__dep__incl.md5 new file mode 100644 index 0000000..4c56ec0 --- /dev/null +++ b/stm32f4xx__iwdg_8h__dep__incl.md5 @@ -0,0 +1 @@ +986dfe28929700021db008f14da889fb \ No newline at end of file diff --git a/stm32f4xx__iwdg_8h__dep__incl.png b/stm32f4xx__iwdg_8h__dep__incl.png new file mode 100644 index 0000000..6ae4744 Binary files /dev/null and b/stm32f4xx__iwdg_8h__dep__incl.png differ diff --git a/stm32f4xx__iwdg_8h__incl.map b/stm32f4xx__iwdg_8h__incl.map new file mode 100644 index 0000000..83f3e6a --- /dev/null +++ b/stm32f4xx__iwdg_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__iwdg_8h__incl.md5 b/stm32f4xx__iwdg_8h__incl.md5 new file mode 100644 index 0000000..400183b --- /dev/null +++ b/stm32f4xx__iwdg_8h__incl.md5 @@ -0,0 +1 @@ +89868e11001d12e628bfdd60748238b2 \ No newline at end of file diff --git a/stm32f4xx__iwdg_8h__incl.png b/stm32f4xx__iwdg_8h__incl.png new file mode 100644 index 0000000..bb29e06 Binary files /dev/null and b/stm32f4xx__iwdg_8h__incl.png differ diff --git a/stm32f4xx__iwdg_8h_source.html b/stm32f4xx__iwdg_8h_source.html new file mode 100644 index 0000000..1c1bd66 --- /dev/null +++ b/stm32f4xx__iwdg_8h_source.html @@ -0,0 +1,170 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_iwdg.h Source File + + + + + + + + + + +
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stm32f4xx_iwdg.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_IWDG_H
+
31 #define __STM32F4xx_IWDG_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
58 #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+
59 #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+
60 #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+
61  ((ACCESS) == IWDG_WriteAccess_Disable))
+
62 
+
69 #define IWDG_Prescaler_4 ((uint8_t)0x00)
+
70 #define IWDG_Prescaler_8 ((uint8_t)0x01)
+
71 #define IWDG_Prescaler_16 ((uint8_t)0x02)
+
72 #define IWDG_Prescaler_32 ((uint8_t)0x03)
+
73 #define IWDG_Prescaler_64 ((uint8_t)0x04)
+
74 #define IWDG_Prescaler_128 ((uint8_t)0x05)
+
75 #define IWDG_Prescaler_256 ((uint8_t)0x06)
+
76 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+
77  ((PRESCALER) == IWDG_Prescaler_8) || \
+
78  ((PRESCALER) == IWDG_Prescaler_16) || \
+
79  ((PRESCALER) == IWDG_Prescaler_32) || \
+
80  ((PRESCALER) == IWDG_Prescaler_64) || \
+
81  ((PRESCALER) == IWDG_Prescaler_128)|| \
+
82  ((PRESCALER) == IWDG_Prescaler_256))
+
83 
+
90 #define IWDG_FLAG_PVU ((uint16_t)0x0001)
+
91 #define IWDG_FLAG_RVU ((uint16_t)0x0002)
+
92 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+
93 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
94 
+
102 /* Exported macro ------------------------------------------------------------*/
+
103 /* Exported functions --------------------------------------------------------*/
+
104 
+
105 /* Prescaler and Counter configuration functions ******************************/
+
106 void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+
107 void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+
108 void IWDG_SetReload(uint16_t Reload);
+
109 void IWDG_ReloadCounter(void);
+
110 
+
111 /* IWDG activation function ***************************************************/
+
112 void IWDG_Enable(void);
+
113 
+
114 /* Flag management function ***************************************************/
+
115 FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
116 
+
117 #ifdef __cplusplus
+
118 }
+
119 #endif
+
120 
+
121 #endif /* __STM32F4xx_IWDG_H */
+
122 
+
131 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
IWDG_SetPrescaler
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
Sets IWDG Prescaler value.
Definition: stm32f4xx_iwdg.c:152
+
IWDG_Enable
void IWDG_Enable(void)
Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
Definition: stm32f4xx_iwdg.c:204
+
IWDG_SetReload
void IWDG_SetReload(uint16_t Reload)
Sets IWDG Reload value.
Definition: stm32f4xx_iwdg.c:165
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
IWDG_WriteAccessCmd
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
Enables or disables write access to IWDG_PR and IWDG_RLR registers.
Definition: stm32f4xx_iwdg.c:132
+
IWDG_ReloadCounter
void IWDG_ReloadCounter(void)
Reloads IWDG counter with value defined in the reload register (write access to IWDG_PR and IWDG_RLR ...
Definition: stm32f4xx_iwdg.c:178
+
IWDG_GetFlagStatus
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
Checks whether the specified IWDG flag is set or not.
Definition: stm32f4xx_iwdg.c:233
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__ltdc_8c.html b/stm32f4xx__ltdc_8c.html new file mode 100644 index 0000000..f10831f --- /dev/null +++ b/stm32f4xx__ltdc_8c.html @@ -0,0 +1,266 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_ltdc.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_ltdc.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the LTDC controller (LTDC) peripheral: +More...

+
#include "stm32f4xx_ltdc.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_ltdc.c:
+
+
+ + +
+
+ + + +

+Macros

+#define GCR_MASK   ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LTDC_DeInit (void)
 Deinitializes the LTDC peripheral registers to their default reset values. More...
 
void LTDC_Init (LTDC_InitTypeDef *LTDC_InitStruct)
 Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct. More...
 
void LTDC_StructInit (LTDC_InitTypeDef *LTDC_InitStruct)
 Fills each LTDC_InitStruct member with its default value. More...
 
void LTDC_Cmd (FunctionalState NewState)
 Enables or disables the LTDC Controller. More...
 
void LTDC_DitherCmd (FunctionalState NewState)
 Enables or disables Dither. More...
 
LTDC_RGBTypeDef LTDC_GetRGBWidth (void)
 Get the dither RGB width. More...
 
void LTDC_RGBStructInit (LTDC_RGBTypeDef *LTDC_RGB_InitStruct)
 Fills each LTDC_RGBStruct member with its default value. More...
 
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
 Define the position of the line interrupt . More...
 
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
 reload layers registers with new parameters More...
 
void LTDC_LayerInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct. More...
 
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Fills each LTDC_Layer_InitStruct member with its default value. More...
 
void LTDC_LayerCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables the LTDC_Layer Controller. More...
 
LTDC_PosTypeDef LTDC_GetPosStatus (void)
 Get the current position. More...
 
void LTDC_PosStructInit (LTDC_PosTypeDef *LTDC_Pos_InitStruct)
 Fills each LTDC_Pos_InitStruct member with its default value. More...
 
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct, FunctionalState NewState)
 Set and configure the color keying. More...
 
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct)
 Fills each LTDC_colorkeying_InitStruct member with its default value. More...
 
void LTDC_CLUTCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables CLUT. More...
 
void LTDC_CLUTInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 configure the CLUT. More...
 
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 Fills each LTDC_CLUT_InitStruct member with its default value. More...
 
void LTDC_LayerPosition (LTDC_Layer_TypeDef *LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
 reconfigure the layer position. More...
 
void LTDC_LayerAlpha (LTDC_Layer_TypeDef *LTDC_Layerx, uint8_t ConstantAlpha)
 reconfigure constant alpha. More...
 
void LTDC_LayerAddress (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Address)
 reconfigure layer address. More...
 
void LTDC_LayerSize (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Width, uint32_t Height)
 reconfigure layer size. More...
 
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t PixelFormat)
 reconfigure layer pixel format. More...
 
void LTDC_ITConfig (uint32_t LTDC_IT, FunctionalState NewState)
 Enables or disables the specified LTDC's interrupts. More...
 
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
 Clears the LTDC's pending flags. More...
 
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
 Checks whether the specified LTDC's interrupt has occurred or not. More...
 
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
 Clears the LTDC's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the LTDC controller (LTDC) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and configuration
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                     ##### How to use this driver #####
+===============================================================================
+   [..]
+       (#) Enable LTDC clock using 
+           RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function.
+       (#) Configures LTDC
+         (++) Configure the required Pixel clock following the panel datasheet
+         (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and 
+             Horizontal back proch, active data area and the front proch 
+             timings 
+         (++) Configure the synchronous signals and clock polarity in the 
+             LTDC_GCR register
+       (#) Configures Layer1/2 parameters
+         (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and 
+              LTDC_WVPCR registers. The layer window must be in the active data area.
+         (++) The pixel input format in the LTDC_LxPFCR register
+         (++) The color frame buffer start address in the LTDC_LxCFBAR register
+         (++) The line length and pitch of the color frame buffer in the 
+              LTDC_LxCFBLR register
+         (++) The number of lines of the color frame buffer in 
+              the LTDC_LxCFBLNR register
+         (++) if needed, load the CLUT with the RGB values and the address 
+              in the LTDC_LxCLUTWR register
+         (++) If needed, configure the default color and the blending factors 
+              respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers 
+
+         (++) If needed, Dithering and color keying can be be enabled respectively 
+              in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled 
+              on the fly.    
+       (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register 
+ 
+       (#) Reload the shadow registers to active register through 
+           the LTDC_SRCR register.
+         -@- All layer parameters can be be modified on the fly except the CLUT. 
+             The new configuration has to be either reloaded immediately 
+             or during vertical blanking period by configuring the LTDC_SRCR register.
+       (#) Call the LTDC_Cmd() to enable the LTDC controller.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__ltdc_8c__incl.map b/stm32f4xx__ltdc_8c__incl.map new file mode 100644 index 0000000..fcdbe0a --- /dev/null +++ b/stm32f4xx__ltdc_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__ltdc_8c__incl.md5 b/stm32f4xx__ltdc_8c__incl.md5 new file mode 100644 index 0000000..1254b27 --- /dev/null +++ b/stm32f4xx__ltdc_8c__incl.md5 @@ -0,0 +1 @@ +e4c11f339e7359dacc623e1dc6e7a092 \ No newline at end of file diff --git a/stm32f4xx__ltdc_8c__incl.png b/stm32f4xx__ltdc_8c__incl.png new file mode 100644 index 0000000..e937818 Binary files /dev/null and b/stm32f4xx__ltdc_8c__incl.png differ diff --git a/stm32f4xx__ltdc_8h.html b/stm32f4xx__ltdc_8h.html new file mode 100644 index 0000000..6423cbb --- /dev/null +++ b/stm32f4xx__ltdc_8h.html @@ -0,0 +1,471 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_ltdc.h File Reference + + + + + + + + + + +
+
+ + + + + + +
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discoverpixy +
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+ + +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_ltdc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the LTDC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_ltdc.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Classes

struct  LTDC_InitTypeDef
 LTDC Init structure definition. More...
 
struct  LTDC_Layer_InitTypeDef
 LTDC Layer structure definition. More...
 
struct  LTDC_PosTypeDef
 LTDC Position structure definition. More...
 
struct  LTDC_RGBTypeDef
 
struct  LTDC_ColorKeying_InitTypeDef
 
struct  LTDC_CLUT_InitTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define LTDC_HorizontalSYNC   ((uint32_t)0x00000FFF)
 
+#define LTDC_VerticalSYNC   ((uint32_t)0x000007FF)
 
+#define IS_LTDC_HSYNC(HSYNC)   ((HSYNC) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_VSYNC(VSYNC)   ((VSYNC) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_AHBP(AHBP)   ((AHBP) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_AVBP(AVBP)   ((AVBP) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_AAW(AAW)   ((AAW) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_AAH(AAH)   ((AAH) <= LTDC_VerticalSYNC)
 
+#define IS_LTDC_TOTALW(TOTALW)   ((TOTALW) <= LTDC_HorizontalSYNC)
 
+#define IS_LTDC_TOTALH(TOTALH)   ((TOTALH) <= LTDC_VerticalSYNC)
 
#define LTDC_HSPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_HSPolarity_AH   LTDC_GCR_HSPOL
 
#define IS_LTDC_HSPOL(HSPOL)
 
#define LTDC_VSPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_VSPolarity_AH   LTDC_GCR_VSPOL
 
#define IS_LTDC_VSPOL(VSPOL)
 
#define LTDC_DEPolarity_AL   ((uint32_t)0x00000000)
 
#define LTDC_DEPolarity_AH   LTDC_GCR_DEPOL
 
#define IS_LTDC_DEPOL(DEPOL)
 
#define LTDC_PCPolarity_IPC   ((uint32_t)0x00000000)
 
#define LTDC_PCPolarity_IIPC   LTDC_GCR_PCPOL
 
#define IS_LTDC_PCPOL(PCPOL)
 
#define LTDC_IMReload   LTDC_SRCR_IMR
 
#define LTDC_VBReload   LTDC_SRCR_VBR
 
#define IS_LTDC_RELOAD(RELOAD)
 
+#define LTDC_Back_Color   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_BackBlueValue(BBLUE)   ((BBLUE) <= LTDC_Back_Color)
 
+#define IS_LTDC_BackGreenValue(BGREEN)   ((BGREEN) <= LTDC_Back_Color)
 
+#define IS_LTDC_BackRedValue(BRED)   ((BRED) <= LTDC_Back_Color)
 
+#define LTDC_POS_CY   LTDC_CPSR_CYPOS
 
+#define LTDC_POS_CX   LTDC_CPSR_CXPOS
 
+#define IS_LTDC_GET_POS(POS)   (((POS) <= LTDC_POS_CY))
 
+#define IS_LTDC_LIPOS(LIPOS)   ((LIPOS) <= 0x7FF)
 
+#define LTDC_CD_VDES   LTDC_CDSR_VDES
 
+#define LTDC_CD_HDES   LTDC_CDSR_HDES
 
+#define LTDC_CD_VSYNC   LTDC_CDSR_VSYNCS
 
+#define LTDC_CD_HSYNC   LTDC_CDSR_HSYNCS
 
#define IS_LTDC_GET_CD(CD)
 
+#define LTDC_IT_LI   LTDC_IER_LIE
 
+#define LTDC_IT_FU   LTDC_IER_FUIE
 
+#define LTDC_IT_TERR   LTDC_IER_TERRIE
 
+#define LTDC_IT_RR   LTDC_IER_RRIE
 
+#define IS_LTDC_IT(IT)   ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
 
+#define LTDC_FLAG_LI   LTDC_ISR_LIF
 
+#define LTDC_FLAG_FU   LTDC_ISR_FUIF
 
+#define LTDC_FLAG_TERR   LTDC_ISR_TERRIF
 
+#define LTDC_FLAG_RR   LTDC_ISR_RRIF
 
#define IS_LTDC_FLAG(FLAG)
 
+#define LTDC_Pixelformat_ARGB8888   ((uint32_t)0x00000000)
 
+#define LTDC_Pixelformat_RGB888   ((uint32_t)0x00000001)
 
+#define LTDC_Pixelformat_RGB565   ((uint32_t)0x00000002)
 
+#define LTDC_Pixelformat_ARGB1555   ((uint32_t)0x00000003)
 
+#define LTDC_Pixelformat_ARGB4444   ((uint32_t)0x00000004)
 
+#define LTDC_Pixelformat_L8   ((uint32_t)0x00000005)
 
+#define LTDC_Pixelformat_AL44   ((uint32_t)0x00000006)
 
+#define LTDC_Pixelformat_AL88   ((uint32_t)0x00000007)
 
#define IS_LTDC_Pixelformat(Pixelformat)
 
+#define LTDC_BlendingFactor1_CA   ((uint32_t)0x00000400)
 
+#define LTDC_BlendingFactor1_PAxCA   ((uint32_t)0x00000600)
 
+#define IS_LTDC_BlendingFactor1(BlendingFactor1)   (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
 
+#define LTDC_BlendingFactor2_CA   ((uint32_t)0x00000005)
 
+#define LTDC_BlendingFactor2_PAxCA   ((uint32_t)0x00000007)
 
+#define IS_LTDC_BlendingFactor2(BlendingFactor2)   (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
 
+#define LTDC_STOPPosition   ((uint32_t)0x0000FFFF)
 
+#define LTDC_STARTPosition   ((uint32_t)0x00000FFF)
 
+#define LTDC_DefaultColorConfig   ((uint32_t)0x000000FF)
 
+#define LTDC_ColorFrameBuffer   ((uint32_t)0x00001FFF)
 
+#define LTDC_LineNumber   ((uint32_t)0x000007FF)
 
+#define IS_LTDC_HCONFIGST(HCONFIGST)   ((HCONFIGST) <= LTDC_STARTPosition)
 
+#define IS_LTDC_HCONFIGSP(HCONFIGSP)   ((HCONFIGSP) <= LTDC_STOPPosition)
 
+#define IS_LTDC_VCONFIGST(VCONFIGST)   ((VCONFIGST) <= LTDC_STARTPosition)
 
+#define IS_LTDC_VCONFIGSP(VCONFIGSP)   ((VCONFIGSP) <= LTDC_STOPPosition)
 
+#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR)   ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
 
+#define IS_LTDC_CFBP(CFBP)   ((CFBP) <= LTDC_ColorFrameBuffer)
 
+#define IS_LTDC_CFBLL(CFBLL)   ((CFBLL) <= LTDC_ColorFrameBuffer)
 
+#define IS_LTDC_CFBLNBR(CFBLNBR)   ((CFBLNBR) <= LTDC_LineNumber)
 
+#define LTDC_colorkeyingConfig   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_CKEYING(CKEYING)   ((CKEYING) <= LTDC_colorkeyingConfig)
 
+#define LTDC_CLUTWR   ((uint32_t)0x000000FF)
 
+#define IS_LTDC_CLUTWR(CLUTWR)   ((CLUTWR) <= LTDC_CLUTWR)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void LTDC_DeInit (void)
 Deinitializes the LTDC peripheral registers to their default reset values. More...
 
void LTDC_Init (LTDC_InitTypeDef *LTDC_InitStruct)
 Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct. More...
 
void LTDC_StructInit (LTDC_InitTypeDef *LTDC_InitStruct)
 Fills each LTDC_InitStruct member with its default value. More...
 
void LTDC_Cmd (FunctionalState NewState)
 Enables or disables the LTDC Controller. More...
 
void LTDC_DitherCmd (FunctionalState NewState)
 Enables or disables Dither. More...
 
LTDC_RGBTypeDef LTDC_GetRGBWidth (void)
 Get the dither RGB width. More...
 
void LTDC_RGBStructInit (LTDC_RGBTypeDef *LTDC_RGB_InitStruct)
 Fills each LTDC_RGBStruct member with its default value. More...
 
void LTDC_LIPConfig (uint32_t LTDC_LIPositionConfig)
 Define the position of the line interrupt . More...
 
void LTDC_ReloadConfig (uint32_t LTDC_Reload)
 reload layers registers with new parameters More...
 
void LTDC_LayerInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct. More...
 
void LTDC_LayerStructInit (LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
 Fills each LTDC_Layer_InitStruct member with its default value. More...
 
void LTDC_LayerCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables the LTDC_Layer Controller. More...
 
LTDC_PosTypeDef LTDC_GetPosStatus (void)
 Get the current position. More...
 
void LTDC_PosStructInit (LTDC_PosTypeDef *LTDC_Pos_InitStruct)
 Fills each LTDC_Pos_InitStruct member with its default value. More...
 
FlagStatus LTDC_GetCDStatus (uint32_t LTDC_CD)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ColorKeyingConfig (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct, FunctionalState NewState)
 Set and configure the color keying. More...
 
void LTDC_ColorKeyingStructInit (LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct)
 Fills each LTDC_colorkeying_InitStruct member with its default value. More...
 
void LTDC_CLUTCmd (LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
 Enables or disables CLUT. More...
 
void LTDC_CLUTInit (LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 configure the CLUT. More...
 
void LTDC_CLUTStructInit (LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
 Fills each LTDC_CLUT_InitStruct member with its default value. More...
 
void LTDC_LayerPosition (LTDC_Layer_TypeDef *LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
 reconfigure the layer position. More...
 
void LTDC_LayerAlpha (LTDC_Layer_TypeDef *LTDC_Layerx, uint8_t ConstantAlpha)
 reconfigure constant alpha. More...
 
void LTDC_LayerAddress (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Address)
 reconfigure layer address. More...
 
void LTDC_LayerSize (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Width, uint32_t Height)
 reconfigure layer size. More...
 
void LTDC_LayerPixelFormat (LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t PixelFormat)
 reconfigure layer pixel format. More...
 
void LTDC_ITConfig (uint32_t LTDC_IT, FunctionalState NewState)
 Enables or disables the specified LTDC's interrupts. More...
 
FlagStatus LTDC_GetFlagStatus (uint32_t LTDC_FLAG)
 Checks whether the specified LTDC's flag is set or not. More...
 
void LTDC_ClearFlag (uint32_t LTDC_FLAG)
 Clears the LTDC's pending flags. More...
 
ITStatus LTDC_GetITStatus (uint32_t LTDC_IT)
 Checks whether the specified LTDC's interrupt has occurred or not. More...
 
void LTDC_ClearITPendingBit (uint32_t LTDC_IT)
 Clears the LTDC's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the LTDC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__ltdc_8h__dep__incl.map b/stm32f4xx__ltdc_8h__dep__incl.map new file mode 100644 index 0000000..9a37cb1 --- /dev/null +++ b/stm32f4xx__ltdc_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/stm32f4xx__ltdc_8h__dep__incl.md5 b/stm32f4xx__ltdc_8h__dep__incl.md5 new file mode 100644 index 0000000..09b35ec --- /dev/null +++ b/stm32f4xx__ltdc_8h__dep__incl.md5 @@ -0,0 +1 @@ +acde907ae556974cd5ec969fa2d95bba \ No newline at end of file diff --git a/stm32f4xx__ltdc_8h__dep__incl.png b/stm32f4xx__ltdc_8h__dep__incl.png new file mode 100644 index 0000000..a3b57e3 Binary files /dev/null and b/stm32f4xx__ltdc_8h__dep__incl.png differ diff --git a/stm32f4xx__ltdc_8h__incl.map b/stm32f4xx__ltdc_8h__incl.map new file mode 100644 index 0000000..b583e37 --- /dev/null +++ b/stm32f4xx__ltdc_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__ltdc_8h__incl.md5 b/stm32f4xx__ltdc_8h__incl.md5 new file mode 100644 index 0000000..a841b7f --- /dev/null +++ b/stm32f4xx__ltdc_8h__incl.md5 @@ -0,0 +1 @@ +04d94363bd3376aeb99df283f49aa4b3 \ No newline at end of file diff --git a/stm32f4xx__ltdc_8h__incl.png b/stm32f4xx__ltdc_8h__incl.png new file mode 100644 index 0000000..be60836 Binary files /dev/null and b/stm32f4xx__ltdc_8h__incl.png differ diff --git a/stm32f4xx__ltdc_8h_source.html b/stm32f4xx__ltdc_8h_source.html new file mode 100644 index 0000000..3059be6 --- /dev/null +++ b/stm32f4xx__ltdc_8h_source.html @@ -0,0 +1,443 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_ltdc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx_ltdc.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_LTDC_H
+
31 #define __STM32F4xx_LTDC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t LTDC_HSPolarity;
+
59  uint32_t LTDC_VSPolarity;
+
62  uint32_t LTDC_DEPolarity;
+
65  uint32_t LTDC_PCPolarity;
+
68  uint32_t LTDC_HorizontalSync;
+
71  uint32_t LTDC_VerticalSync;
+
74  uint32_t LTDC_AccumulatedHBP;
+
77  uint32_t LTDC_AccumulatedVBP;
+
80  uint32_t LTDC_AccumulatedActiveW;
+
83  uint32_t LTDC_AccumulatedActiveH;
+
86  uint32_t LTDC_TotalWidth;
+
89  uint32_t LTDC_TotalHeigh;
+
92  uint32_t LTDC_BackgroundRedValue;
+
95  uint32_t LTDC_BackgroundGreenValue;
+
98  uint32_t LTDC_BackgroundBlueValue;
+
100 } LTDC_InitTypeDef;
+
101 
+
106 typedef struct
+
107 {
+
108  uint32_t LTDC_HorizontalStart;
+
111  uint32_t LTDC_HorizontalStop;
+
114  uint32_t LTDC_VerticalStart;
+
117  uint32_t LTDC_VerticalStop;
+
120  uint32_t LTDC_PixelFormat;
+
123  uint32_t LTDC_ConstantAlpha;
+
126  uint32_t LTDC_DefaultColorBlue;
+
129  uint32_t LTDC_DefaultColorGreen;
+
132  uint32_t LTDC_DefaultColorRed;
+
135  uint32_t LTDC_DefaultColorAlpha;
+
138  uint32_t LTDC_BlendingFactor_1;
+
141  uint32_t LTDC_BlendingFactor_2;
+
144  uint32_t LTDC_CFBStartAdress;
+
146  uint32_t LTDC_CFBLineLength;
+
149  uint32_t LTDC_CFBPitch;
+
152  uint32_t LTDC_CFBLineNumber;
+
154 } LTDC_Layer_InitTypeDef;
+
155 
+
160 typedef struct
+
161 {
+
162  uint32_t LTDC_POSX;
+
163  uint32_t LTDC_POSY;
+
164 } LTDC_PosTypeDef;
+
165 
+
166 typedef struct
+
167 {
+
168  uint32_t LTDC_BlueWidth;
+
169  uint32_t LTDC_GreenWidth;
+
170  uint32_t LTDC_RedWidth;
+
171 } LTDC_RGBTypeDef;
+
172 
+
173 typedef struct
+
174 {
+
175  uint32_t LTDC_ColorKeyBlue;
+
178  uint32_t LTDC_ColorKeyGreen;
+
181  uint32_t LTDC_ColorKeyRed;
+
183 } LTDC_ColorKeying_InitTypeDef;
+
184 
+
185 typedef struct
+
186 {
+
187  uint32_t LTDC_CLUTAdress;
+
190  uint32_t LTDC_BlueValue;
+
193  uint32_t LTDC_GreenValue;
+
196  uint32_t LTDC_RedValue;
+
198 } LTDC_CLUT_InitTypeDef;
+
199 
+
200 /* Exported constants --------------------------------------------------------*/
+
201 
+
210 #define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF)
+
211 #define LTDC_VerticalSYNC ((uint32_t)0x000007FF)
+
212 
+
213 #define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
+
214 #define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
+
215 #define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC)
+
216 #define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
+
217 #define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC)
+
218 #define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
+
219 #define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
+
220 #define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
+
221 
+
229 #define LTDC_HSPolarity_AL ((uint32_t)0x00000000)
+
230 #define LTDC_HSPolarity_AH LTDC_GCR_HSPOL
+
232 #define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
+
233  ((HSPOL) == LTDC_HSPolarity_AH))
+
234 
+
242 #define LTDC_VSPolarity_AL ((uint32_t)0x00000000)
+
243 #define LTDC_VSPolarity_AH LTDC_GCR_VSPOL
+
245 #define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
+
246  ((VSPOL) == LTDC_VSPolarity_AH))
+
247 
+
255 #define LTDC_DEPolarity_AL ((uint32_t)0x00000000)
+
256 #define LTDC_DEPolarity_AH LTDC_GCR_DEPOL
+
258 #define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
+
259  ((DEPOL) == LTDC_DEPolarity_AH))
+
260 
+
268 #define LTDC_PCPolarity_IPC ((uint32_t)0x00000000)
+
269 #define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL
+
271 #define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
+
272  ((PCPOL) == LTDC_PCPolarity_IIPC))
+
273 
+
281 #define LTDC_IMReload LTDC_SRCR_IMR
+
282 #define LTDC_VBReload LTDC_SRCR_VBR
+
284 #define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
+
285  ((RELOAD) == LTDC_VBReload))
+
286 
+
295 #define LTDC_Back_Color ((uint32_t)0x000000FF)
+
296 
+
297 #define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
+
298 #define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
+
299 #define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
+
300 
+
309 #define LTDC_POS_CY LTDC_CPSR_CYPOS
+
310 #define LTDC_POS_CX LTDC_CPSR_CXPOS
+
311 
+
312 #define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
+
313 
+
314 
+
323 #define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
+
324 
+
333 #define LTDC_CD_VDES LTDC_CDSR_VDES
+
334 #define LTDC_CD_HDES LTDC_CDSR_HDES
+
335 #define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
+
336 #define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
+
337 
+
338 
+
339 #define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
+
340  ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
+
341 
+
342 
+
351 #define LTDC_IT_LI LTDC_IER_LIE
+
352 #define LTDC_IT_FU LTDC_IER_FUIE
+
353 #define LTDC_IT_TERR LTDC_IER_TERRIE
+
354 #define LTDC_IT_RR LTDC_IER_RRIE
+
355 
+
356 #define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
+
357 
+
366 #define LTDC_FLAG_LI LTDC_ISR_LIF
+
367 #define LTDC_FLAG_FU LTDC_ISR_FUIF
+
368 #define LTDC_FLAG_TERR LTDC_ISR_TERRIF
+
369 #define LTDC_FLAG_RR LTDC_ISR_RRIF
+
370 
+
371 
+
372 #define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
+
373  ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
+
374 
+
382 #define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000)
+
383 #define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001)
+
384 #define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002)
+
385 #define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003)
+
386 #define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004)
+
387 #define LTDC_Pixelformat_L8 ((uint32_t)0x00000005)
+
388 #define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006)
+
389 #define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007)
+
390 
+
391 #define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \
+
392  ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
+
393  ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \
+
394  ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88))
+
395 
+
404 #define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
+
405 #define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
+
406 
+
407 #define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
+
408 
+
417 #define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
+
418 #define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
+
419 
+
420 #define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
+
421 
+
422 
+
432 #define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
+
433 #define LTDC_STARTPosition ((uint32_t)0x00000FFF)
+
434 
+
435 #define LTDC_DefaultColorConfig ((uint32_t)0x000000FF)
+
436 #define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF)
+
437 #define LTDC_LineNumber ((uint32_t)0x000007FF)
+
438 
+
439 #define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
+
440 #define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
+
441 #define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition)
+
442 #define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
+
443 
+
444 #define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
+
445 
+
446 #define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
+
447 #define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
+
448 
+
449 #define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
+
450 
+
451 
+
452 
+
461 #define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
+
462 
+
463 #define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
+
464 
+
465 
+
474 #define LTDC_CLUTWR ((uint32_t)0x000000FF)
+
475 
+
476 #define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR)
+
477 
+
478 /* Exported macro ------------------------------------------------------------*/
+
479 /* Exported functions ------------------------------------------------------- */
+
480 
+
481 /* Function used to set the LTDC configuration to the default reset state *****/
+
482 void LTDC_DeInit(void);
+
483 
+
484 /* Initialization and Configuration functions *********************************/
+
485 void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
+
486 void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
+
487 void LTDC_Cmd(FunctionalState NewState);
+
488 void LTDC_DitherCmd(FunctionalState NewState);
+
489 LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
+
490 void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
+
491 void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
+
492 void LTDC_ReloadConfig(uint32_t LTDC_Reload);
+
493 void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
+
494 void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
+
495 void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
+
496 LTDC_PosTypeDef LTDC_GetPosStatus(void);
+
497 void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
+
498 FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
+
499 void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
+
500 void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
+
501 void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
+
502 void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
+
503 void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
+
504 void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
+
505 void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
+
506 void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
+
507 void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
+
508 void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
+
509 
+
510 /* Interrupts and flags management functions **********************************/
+
511 void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
+
512 FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
+
513 void LTDC_ClearFlag(uint32_t LTDC_FLAG);
+
514 ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
+
515 void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
+
516 
+
517 #ifdef __cplusplus
+
518 }
+
519 #endif
+
520 
+
521 #endif /* __STM32F4xx_LTDC_H */
+
522 
+
531 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
LTDC_GetFlagStatus
FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG)
Checks whether the specified LTDC's flag is set or not.
Definition: stm32f4xx_ltdc.c:1001
+
LTDC_DeInit
void LTDC_DeInit(void)
Deinitializes the LTDC peripheral registers to their default reset values.
Definition: stm32f4xx_ltdc.c:129
+
LTDC_GetITStatus
ITStatus LTDC_GetITStatus(uint32_t LTDC_IT)
Checks whether the specified LTDC's interrupt has occurred or not.
Definition: stm32f4xx_ltdc.c:1048
+
LTDC_Layer_InitTypeDef::LTDC_VerticalStop
uint32_t LTDC_VerticalStop
Definition: stm32f4xx_ltdc.h:117
+
LTDC_CLUTStructInit
void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
Fills each LTDC_CLUT_InitStruct member with its default value.
Definition: stm32f4xx_ltdc.c:687
+
LTDC_ColorKeyingStructInit
void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct)
Fills each LTDC_colorkeying_InitStruct member with its default value.
Definition: stm32f4xx_ltdc.c:613
+
LTDC_Layer_InitTypeDef::LTDC_CFBLineNumber
uint32_t LTDC_CFBLineNumber
Definition: stm32f4xx_ltdc.h:152
+
LTDC_RGBTypeDef::LTDC_BlueWidth
uint32_t LTDC_BlueWidth
Definition: stm32f4xx_ltdc.h:168
+
LTDC_CLUTCmd
void LTDC_CLUTCmd(LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
Enables or disables CLUT.
Definition: stm32f4xx_ltdc.c:631
+
LTDC_ClearITPendingBit
void LTDC_ClearITPendingBit(uint32_t LTDC_IT)
Clears the LTDC's interrupt pending bits.
Definition: stm32f4xx_ltdc.c:1086
+
LTDC_InitTypeDef::LTDC_TotalWidth
uint32_t LTDC_TotalWidth
Definition: stm32f4xx_ltdc.h:86
+
LTDC_LIPConfig
void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig)
Define the position of the line interrupt .
Definition: stm32f4xx_ltdc.c:320
+
LTDC_Layer_InitTypeDef::LTDC_ConstantAlpha
uint32_t LTDC_ConstantAlpha
Definition: stm32f4xx_ltdc.h:123
+
LTDC_PosTypeDef::LTDC_POSX
uint32_t LTDC_POSX
Definition: stm32f4xx_ltdc.h:162
+
LTDC_PosTypeDef
LTDC Position structure definition.
Definition: stm32f4xx_ltdc.h:160
+
LTDC_RGBTypeDef
Definition: stm32f4xx_ltdc.h:166
+
LTDC_InitTypeDef::LTDC_AccumulatedActiveW
uint32_t LTDC_AccumulatedActiveW
Definition: stm32f4xx_ltdc.h:80
+
LTDC_ColorKeyingConfig
void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_ColorKeying_InitTypeDef *LTDC_colorkeying_InitStruct, FunctionalState NewState)
Set and configure the color keying.
Definition: stm32f4xx_ltdc.c:574
+
LTDC_Cmd
void LTDC_Cmd(FunctionalState NewState)
Enables or disables the LTDC Controller.
Definition: stm32f4xx_ltdc.c:238
+
LTDC_Layer_InitTypeDef::LTDC_DefaultColorRed
uint32_t LTDC_DefaultColorRed
Definition: stm32f4xx_ltdc.h:132
+
LTDC_InitTypeDef::LTDC_BackgroundGreenValue
uint32_t LTDC_BackgroundGreenValue
Definition: stm32f4xx_ltdc.h:95
+
LTDC_LayerCmd
void LTDC_LayerCmd(LTDC_Layer_TypeDef *LTDC_Layerx, FunctionalState NewState)
Enables or disables the LTDC_Layer Controller.
Definition: stm32f4xx_ltdc.c:486
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
LTDC_InitTypeDef::LTDC_AccumulatedHBP
uint32_t LTDC_AccumulatedHBP
Definition: stm32f4xx_ltdc.h:74
+
LTDC_InitTypeDef
LTDC Init structure definition.
Definition: stm32f4xx_ltdc.h:54
+
LTDC_Layer_InitTypeDef::LTDC_HorizontalStop
uint32_t LTDC_HorizontalStop
Definition: stm32f4xx_ltdc.h:111
+
LTDC_Init
void LTDC_Init(LTDC_InitTypeDef *LTDC_InitStruct)
Initializes the LTDC peripheral according to the specified parameters in the LTDC_InitStruct.
Definition: stm32f4xx_ltdc.c:146
+
LTDC_CLUTInit
void LTDC_CLUTInit(LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_CLUT_InitTypeDef *LTDC_CLUT_InitStruct)
configure the CLUT.
Definition: stm32f4xx_ltdc.c:660
+
LTDC_ITConfig
void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState)
Enables or disables the specified LTDC's interrupts.
Definition: stm32f4xx_ltdc.c:975
+
LTDC_LayerAddress
void LTDC_LayerAddress(LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Address)
reconfigure layer address.
Definition: stm32f4xx_ltdc.c:783
+
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f4xx.h:1085
+
LTDC_Layer_InitTypeDef::LTDC_CFBPitch
uint32_t LTDC_CFBPitch
Definition: stm32f4xx_ltdc.h:149
+
LTDC_Layer_InitTypeDef::LTDC_BlendingFactor_1
uint32_t LTDC_BlendingFactor_1
Definition: stm32f4xx_ltdc.h:138
+
LTDC_CLUT_InitTypeDef::LTDC_GreenValue
uint32_t LTDC_GreenValue
Definition: stm32f4xx_ltdc.h:193
+
LTDC_LayerStructInit
void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
Fills each LTDC_Layer_InitStruct member with its default value.
Definition: stm32f4xx_ltdc.c:437
+
LTDC_InitTypeDef::LTDC_HSPolarity
uint32_t LTDC_HSPolarity
Definition: stm32f4xx_ltdc.h:56
+
LTDC_LayerSize
void LTDC_LayerSize(LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t Width, uint32_t Height)
reconfigure layer size.
Definition: stm32f4xx_ltdc.c:799
+
LTDC_CLUT_InitTypeDef::LTDC_BlueValue
uint32_t LTDC_BlueValue
Definition: stm32f4xx_ltdc.h:190
+
LTDC_Layer_InitTypeDef::LTDC_BlendingFactor_2
uint32_t LTDC_BlendingFactor_2
Definition: stm32f4xx_ltdc.h:141
+
LTDC_StructInit
void LTDC_StructInit(LTDC_InitTypeDef *LTDC_InitStruct)
Fills each LTDC_InitStruct member with its default value.
Definition: stm32f4xx_ltdc.c:211
+
LTDC_CLUT_InitTypeDef::LTDC_RedValue
uint32_t LTDC_RedValue
Definition: stm32f4xx_ltdc.h:196
+
LTDC_GetCDStatus
FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD)
Checks whether the specified LTDC's flag is set or not.
Definition: stm32f4xx_ltdc.c:547
+
LTDC_RGBStructInit
void LTDC_RGBStructInit(LTDC_RGBTypeDef *LTDC_RGB_InitStruct)
Fills each LTDC_RGBStruct member with its default value.
Definition: stm32f4xx_ltdc.c:306
+
LTDC_InitTypeDef::LTDC_AccumulatedActiveH
uint32_t LTDC_AccumulatedActiveH
Definition: stm32f4xx_ltdc.h:83
+
LTDC_Layer_InitTypeDef::LTDC_CFBStartAdress
uint32_t LTDC_CFBStartAdress
Definition: stm32f4xx_ltdc.h:144
+
LTDC_InitTypeDef::LTDC_BackgroundRedValue
uint32_t LTDC_BackgroundRedValue
Definition: stm32f4xx_ltdc.h:92
+
LTDC_ColorKeying_InitTypeDef
Definition: stm32f4xx_ltdc.h:173
+
LTDC_Layer_InitTypeDef::LTDC_PixelFormat
uint32_t LTDC_PixelFormat
Definition: stm32f4xx_ltdc.h:120
+
LTDC_GetRGBWidth
LTDC_RGBTypeDef LTDC_GetRGBWidth(void)
Get the dither RGB width.
Definition: stm32f4xx_ltdc.c:286
+
LTDC_LayerPixelFormat
void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef *LTDC_Layerx, uint32_t PixelFormat)
reconfigure layer pixel format.
Definition: stm32f4xx_ltdc.c:861
+
LTDC_RGBTypeDef::LTDC_RedWidth
uint32_t LTDC_RedWidth
Definition: stm32f4xx_ltdc.h:170
+
LTDC_Layer_InitTypeDef::LTDC_VerticalStart
uint32_t LTDC_VerticalStart
Definition: stm32f4xx_ltdc.h:114
+
LTDC_InitTypeDef::LTDC_BackgroundBlueValue
uint32_t LTDC_BackgroundBlueValue
Definition: stm32f4xx_ltdc.h:98
+
LTDC_PosTypeDef::LTDC_POSY
uint32_t LTDC_POSY
Definition: stm32f4xx_ltdc.h:163
+
LTDC_PosStructInit
void LTDC_PosStructInit(LTDC_PosTypeDef *LTDC_Pos_InitStruct)
Fills each LTDC_Pos_InitStruct member with its default value.
Definition: stm32f4xx_ltdc.c:530
+
LTDC_LayerPosition
void LTDC_LayerPosition(LTDC_Layer_TypeDef *LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY)
reconfigure the layer position.
Definition: stm32f4xx_ltdc.c:707
+
LTDC_Layer_InitTypeDef::LTDC_DefaultColorAlpha
uint32_t LTDC_DefaultColorAlpha
Definition: stm32f4xx_ltdc.h:135
+
LTDC_DitherCmd
void LTDC_DitherCmd(FunctionalState NewState)
Enables or disables Dither.
Definition: stm32f4xx_ltdc.c:262
+
LTDC_InitTypeDef::LTDC_PCPolarity
uint32_t LTDC_PCPolarity
Definition: stm32f4xx_ltdc.h:65
+
LTDC_InitTypeDef::LTDC_VSPolarity
uint32_t LTDC_VSPolarity
Definition: stm32f4xx_ltdc.h:59
+
LTDC_Layer_InitTypeDef::LTDC_HorizontalStart
uint32_t LTDC_HorizontalStart
Definition: stm32f4xx_ltdc.h:108
+
LTDC_ReloadConfig
void LTDC_ReloadConfig(uint32_t LTDC_Reload)
reload layers registers with new parameters
Definition: stm32f4xx_ltdc.c:338
+
LTDC_InitTypeDef::LTDC_HorizontalSync
uint32_t LTDC_HorizontalSync
Definition: stm32f4xx_ltdc.h:68
+
LTDC_InitTypeDef::LTDC_AccumulatedVBP
uint32_t LTDC_AccumulatedVBP
Definition: stm32f4xx_ltdc.h:77
+
LTDC_Layer_InitTypeDef
LTDC Layer structure definition.
Definition: stm32f4xx_ltdc.h:106
+
LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyRed
uint32_t LTDC_ColorKeyRed
Definition: stm32f4xx_ltdc.h:181
+
LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyBlue
uint32_t LTDC_ColorKeyBlue
Definition: stm32f4xx_ltdc.h:175
+
LTDC_CLUT_InitTypeDef
Definition: stm32f4xx_ltdc.h:185
+
LTDC_LayerInit
void LTDC_LayerInit(LTDC_Layer_TypeDef *LTDC_Layerx, LTDC_Layer_InitTypeDef *LTDC_Layer_InitStruct)
Initializes the LTDC Layer according to the specified parameters in the LTDC_LayerStruct.
Definition: stm32f4xx_ltdc.c:359
+
LTDC_InitTypeDef::LTDC_TotalHeigh
uint32_t LTDC_TotalHeigh
Definition: stm32f4xx_ltdc.h:89
+
LTDC_ClearFlag
void LTDC_ClearFlag(uint32_t LTDC_FLAG)
Clears the LTDC's pending flags.
Definition: stm32f4xx_ltdc.c:1029
+
LTDC_GetPosStatus
LTDC_PosTypeDef LTDC_GetPosStatus(void)
Get the current position.
Definition: stm32f4xx_ltdc.c:511
+
LTDC_Layer_InitTypeDef::LTDC_CFBLineLength
uint32_t LTDC_CFBLineLength
Definition: stm32f4xx_ltdc.h:146
+
LTDC_LayerAlpha
void LTDC_LayerAlpha(LTDC_Layer_TypeDef *LTDC_Layerx, uint8_t ConstantAlpha)
reconfigure constant alpha.
Definition: stm32f4xx_ltdc.c:768
+
LTDC_Layer_InitTypeDef::LTDC_DefaultColorBlue
uint32_t LTDC_DefaultColorBlue
Definition: stm32f4xx_ltdc.h:126
+
LTDC_InitTypeDef::LTDC_VerticalSync
uint32_t LTDC_VerticalSync
Definition: stm32f4xx_ltdc.h:71
+
LTDC_RGBTypeDef::LTDC_GreenWidth
uint32_t LTDC_GreenWidth
Definition: stm32f4xx_ltdc.h:169
+
LTDC_CLUT_InitTypeDef::LTDC_CLUTAdress
uint32_t LTDC_CLUTAdress
Definition: stm32f4xx_ltdc.h:187
+
LTDC_Layer_InitTypeDef::LTDC_DefaultColorGreen
uint32_t LTDC_DefaultColorGreen
Definition: stm32f4xx_ltdc.h:129
+
LTDC_InitTypeDef::LTDC_DEPolarity
uint32_t LTDC_DEPolarity
Definition: stm32f4xx_ltdc.h:62
+
LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyGreen
uint32_t LTDC_ColorKeyGreen
Definition: stm32f4xx_ltdc.h:178
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__pwr_8c.html b/stm32f4xx__pwr_8c.html new file mode 100644 index 0000000..07e8545 --- /dev/null +++ b/stm32f4xx__pwr_8c.html @@ -0,0 +1,273 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_pwr.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_pwr.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: +More...

+
#include "stm32f4xx_pwr.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_pwr.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define PWR_OFFSET   (PWR_BASE - PERIPH_BASE)
 
+#define CR_OFFSET   (PWR_OFFSET + 0x00)
 
+#define DBP_BitNumber   0x08
 
+#define CR_DBP_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
 
+#define PVDE_BitNumber   0x04
 
+#define CR_PVDE_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
 
+#define FPDS_BitNumber   0x09
 
+#define CR_FPDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
 
+#define PMODE_BitNumber   0x0E
 
+#define CR_PMODE_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
 
+#define ODEN_BitNumber   0x10
 
+#define CR_ODEN_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
 
+#define ODSWEN_BitNumber   0x11
 
+#define CR_ODSWEN_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
 
+#define MRLVDS_BitNumber   0x0B
 
+#define CR_MRLVDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
 
+#define LPLVDS_BitNumber   0x0A
 
+#define CR_LPLVDS_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
 
+#define CSR_OFFSET   (PWR_OFFSET + 0x04)
 
+#define EWUP_BitNumber   0x08
 
+#define CSR_EWUP_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
 
+#define BRE_BitNumber   0x09
 
+#define CSR_BRE_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
 
+#define CR_DS_MASK   ((uint32_t)0xFFFFF3FC)
 
+#define CR_PLS_MASK   ((uint32_t)0xFFFFFF1F)
 
+#define CR_VOS_MASK   ((uint32_t)0xFFFF3FFF)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void PWR_DeInit (void)
 Deinitializes the PWR peripheral registers to their default reset values. More...
 
void PWR_BackupAccessCmd (FunctionalState NewState)
 Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM). More...
 
void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
 Configures the voltage threshold detected by the Power Voltage Detector(PVD). More...
 
void PWR_PVDCmd (FunctionalState NewState)
 Enables or disables the Power Voltage Detector(PVD). More...
 
void PWR_WakeUpPinCmd (FunctionalState NewState)
 Enables or disables the WakeUp Pin functionality. More...
 
void PWR_BackupRegulatorCmd (FunctionalState NewState)
 Enables or disables the Backup Regulator. More...
 
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
 Configures the main internal regulator output voltage. More...
 
void PWR_OverDriveCmd (FunctionalState NewState)
 Enables or disables the Over-Drive. More...
 
void PWR_OverDriveSWCmd (FunctionalState NewState)
 Enables or disables the Over-Drive switching. More...
 
void PWR_UnderDriveCmd (FunctionalState NewState)
 Enables or disables the Under-Drive mode. More...
 
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Main Regulator low voltage mode. More...
 
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Low Power Regulator low voltage mode. More...
 
void PWR_FlashPowerDownCmd (FunctionalState NewState)
 Enables or disables the Flash Power Down in STOP mode. More...
 
void PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters STOP mode. More...
 
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters in Under-Drive STOP mode. More...
 
void PWR_EnterSTANDBYMode (void)
 Enters STANDBY mode. More...
 
FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
 Checks whether the specified PWR flag is set or not. More...
 
void PWR_ClearFlag (uint32_t PWR_FLAG)
 Clears the PWR's pending flags. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Backup Domain Access
    • +
  • PVD configuration
    • +
  • WakeUp pin configuration
    • +
  • Main and Backup Regulators configuration
    • +
  • FLASH Power Down configuration
    • +
  • Low Power modes configuration
    • +
  • Flags management
    • +
+
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__pwr_8c__incl.map b/stm32f4xx__pwr_8c__incl.map new file mode 100644 index 0000000..ecea144 --- /dev/null +++ b/stm32f4xx__pwr_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__pwr_8c__incl.md5 b/stm32f4xx__pwr_8c__incl.md5 new file mode 100644 index 0000000..731cae5 --- /dev/null +++ b/stm32f4xx__pwr_8c__incl.md5 @@ -0,0 +1 @@ +3931cf4de810e06053914f05a84a7e67 \ No newline at end of file diff --git a/stm32f4xx__pwr_8c__incl.png b/stm32f4xx__pwr_8c__incl.png new file mode 100644 index 0000000..551b185 Binary files /dev/null and b/stm32f4xx__pwr_8c__incl.png differ diff --git a/stm32f4xx__pwr_8h.html b/stm32f4xx__pwr_8h.html new file mode 100644 index 0000000..bb32906 --- /dev/null +++ b/stm32f4xx__pwr_8h.html @@ -0,0 +1,293 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_pwr.h File Reference + + + + + + + + + + +
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discoverpixy +
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+Macros | +Functions
+
+
stm32f4xx_pwr.h File Reference
+
+
+ +

This file contains all the functions prototypes for the PWR firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_pwr.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define PWR_PVDLevel_0   PWR_CR_PLS_LEV0
 
+#define PWR_PVDLevel_1   PWR_CR_PLS_LEV1
 
+#define PWR_PVDLevel_2   PWR_CR_PLS_LEV2
 
+#define PWR_PVDLevel_3   PWR_CR_PLS_LEV3
 
+#define PWR_PVDLevel_4   PWR_CR_PLS_LEV4
 
+#define PWR_PVDLevel_5   PWR_CR_PLS_LEV5
 
+#define PWR_PVDLevel_6   PWR_CR_PLS_LEV6
 
+#define PWR_PVDLevel_7   PWR_CR_PLS_LEV7
 
#define IS_PWR_PVD_LEVEL(LEVEL)
 
+#define PWR_MainRegulator_ON   ((uint32_t)0x00000000)
 
+#define PWR_LowPowerRegulator_ON   PWR_CR_LPDS
 
+#define PWR_Regulator_ON   PWR_MainRegulator_ON
 
+#define PWR_Regulator_LowPower   PWR_LowPowerRegulator_ON
 
#define IS_PWR_REGULATOR(REGULATOR)
 
+#define PWR_MainRegulator_UnderDrive_ON   PWR_CR_MRUDS
 
+#define PWR_LowPowerRegulator_UnderDrive_ON   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
 
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR)
 
+#define PWR_STOPEntry_WFI   ((uint8_t)0x01)
 
+#define PWR_STOPEntry_WFE   ((uint8_t)0x02)
 
+#define IS_PWR_STOP_ENTRY(ENTRY)   (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
 
+#define PWR_Regulator_Voltage_Scale1   ((uint32_t)0x0000C000)
 
+#define PWR_Regulator_Voltage_Scale2   ((uint32_t)0x00008000)
 
+#define PWR_Regulator_Voltage_Scale3   ((uint32_t)0x00004000)
 
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE)
 
+#define PWR_FLAG_WU   PWR_CSR_WUF
 
+#define PWR_FLAG_SB   PWR_CSR_SBF
 
+#define PWR_FLAG_PVDO   PWR_CSR_PVDO
 
+#define PWR_FLAG_BRR   PWR_CSR_BRR
 
+#define PWR_FLAG_VOSRDY   PWR_CSR_VOSRDY
 
+#define PWR_FLAG_ODRDY   PWR_CSR_ODRDY
 
+#define PWR_FLAG_ODSWRDY   PWR_CSR_ODSWRDY
 
+#define PWR_FLAG_UDRDY   PWR_CSR_UDSWRDY
 
+#define PWR_FLAG_REGRDY   PWR_FLAG_VOSRDY
 
#define IS_PWR_GET_FLAG(FLAG)
 
#define IS_PWR_CLEAR_FLAG(FLAG)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void PWR_DeInit (void)
 Deinitializes the PWR peripheral registers to their default reset values. More...
 
void PWR_BackupAccessCmd (FunctionalState NewState)
 Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup SRAM). More...
 
void PWR_PVDLevelConfig (uint32_t PWR_PVDLevel)
 Configures the voltage threshold detected by the Power Voltage Detector(PVD). More...
 
void PWR_PVDCmd (FunctionalState NewState)
 Enables or disables the Power Voltage Detector(PVD). More...
 
void PWR_WakeUpPinCmd (FunctionalState NewState)
 Enables or disables the WakeUp Pin functionality. More...
 
void PWR_BackupRegulatorCmd (FunctionalState NewState)
 Enables or disables the Backup Regulator. More...
 
void PWR_MainRegulatorModeConfig (uint32_t PWR_Regulator_Voltage)
 Configures the main internal regulator output voltage. More...
 
void PWR_OverDriveCmd (FunctionalState NewState)
 Enables or disables the Over-Drive. More...
 
void PWR_OverDriveSWCmd (FunctionalState NewState)
 Enables or disables the Over-Drive switching. More...
 
void PWR_UnderDriveCmd (FunctionalState NewState)
 Enables or disables the Under-Drive mode. More...
 
void PWR_MainRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Main Regulator low voltage mode. More...
 
void PWR_LowRegulatorLowVoltageCmd (FunctionalState NewState)
 Enables or disables the Low Power Regulator low voltage mode. More...
 
void PWR_FlashPowerDownCmd (FunctionalState NewState)
 Enables or disables the Flash Power Down in STOP mode. More...
 
void PWR_EnterSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters STOP mode. More...
 
void PWR_EnterUnderDriveSTOPMode (uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
 Enters in Under-Drive STOP mode. More...
 
void PWR_EnterSTANDBYMode (void)
 Enters STANDBY mode. More...
 
FlagStatus PWR_GetFlagStatus (uint32_t PWR_FLAG)
 Checks whether the specified PWR flag is set or not. More...
 
void PWR_ClearFlag (uint32_t PWR_FLAG)
 Clears the PWR's pending flags. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the PWR firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
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stm32f4xx_pwr.h
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+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_PWR_H
+
31 #define __STM32F4xx_PWR_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
58 #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
+
59 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
+
60 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
+
61 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
+
62 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
+
63 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
+
64 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
+
65 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
+
66 
+
67 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+
68  ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+
69  ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+
70  ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+
71 
+
79 #define PWR_MainRegulator_ON ((uint32_t)0x00000000)
+
80 #define PWR_LowPowerRegulator_ON PWR_CR_LPDS
+
81 
+
82 /* --- PWR_Legacy ---*/
+
83 #define PWR_Regulator_ON PWR_MainRegulator_ON
+
84 #define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
+
85 
+
86 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
+
87  ((REGULATOR) == PWR_LowPowerRegulator_ON))
+
88 
+
96 #define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
+
97 #define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
+
98 
+
99 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
+
100  ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
+
101 
+
109 #define PWR_STOPEntry_WFI ((uint8_t)0x01)
+
110 #define PWR_STOPEntry_WFE ((uint8_t)0x02)
+
111 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
112 
+
119 #define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
+
120 #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
+
121 #define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
+
122 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
+
123  ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
+
124  ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
+
125 
+
132 #define PWR_FLAG_WU PWR_CSR_WUF
+
133 #define PWR_FLAG_SB PWR_CSR_SBF
+
134 #define PWR_FLAG_PVDO PWR_CSR_PVDO
+
135 #define PWR_FLAG_BRR PWR_CSR_BRR
+
136 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
+
137 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
+
138 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
+
139 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
+
140 
+
141 /* --- FLAG Legacy ---*/
+
142 #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
+
143 
+
144 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+
145  ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
+
146  ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
+
147  ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
+
148 
+
149 
+
150 #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+
151  ((FLAG) == PWR_FLAG_UDRDY))
+
152 
+
161 /* Exported macro ------------------------------------------------------------*/
+
162 /* Exported functions --------------------------------------------------------*/
+
163 
+
164 /* Function used to set the PWR configuration to the default reset state ******/
+
165 void PWR_DeInit(void);
+
166 
+
167 /* Backup Domain Access function **********************************************/
+
168 void PWR_BackupAccessCmd(FunctionalState NewState);
+
169 
+
170 /* PVD configuration functions ************************************************/
+
171 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+
172 void PWR_PVDCmd(FunctionalState NewState);
+
173 
+
174 /* WakeUp pins configuration functions ****************************************/
+
175 void PWR_WakeUpPinCmd(FunctionalState NewState);
+
176 
+
177 /* Main and Backup Regulators configuration functions *************************/
+
178 void PWR_BackupRegulatorCmd(FunctionalState NewState);
+
179 void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
+
180 void PWR_OverDriveCmd(FunctionalState NewState);
+
181 void PWR_OverDriveSWCmd(FunctionalState NewState);
+
182 void PWR_UnderDriveCmd(FunctionalState NewState);
+
183 void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
+
184 void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
+
185 
+
186 /* FLASH Power Down configuration functions ***********************************/
+
187 void PWR_FlashPowerDownCmd(FunctionalState NewState);
+
188 
+
189 /* Low Power modes configuration functions ************************************/
+
190 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+
191 void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+
192 void PWR_EnterSTANDBYMode(void);
+
193 
+
194 /* Flags management functions *************************************************/
+
195 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+
196 void PWR_ClearFlag(uint32_t PWR_FLAG);
+
197 
+
198 #ifdef __cplusplus
+
199 }
+
200 #endif
+
201 
+
202 #endif /* __STM32F4xx_PWR_H */
+
203 
+
212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
PWR_GetFlagStatus
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
Checks whether the specified PWR flag is set or not.
Definition: stm32f4xx_pwr.c:874
+
PWR_EnterSTOPMode
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters STOP mode.
Definition: stm32f4xx_pwr.c:701
+
PWR_BackupAccessCmd
void PWR_BackupAccessCmd(FunctionalState NewState)
Enables or disables access to the backup domain (RTC registers, RTC backup data registers and backup ...
Definition: stm32f4xx_pwr.c:157
+
PWR_MainRegulatorModeConfig
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
Configures the main internal regulator output voltage.
Definition: stm32f4xx_pwr.c:383
+
PWR_PVDCmd
void PWR_PVDCmd(FunctionalState NewState)
Enables or disables the Power Voltage Detector(PVD).
Definition: stm32f4xx_pwr.c:230
+
PWR_LowRegulatorLowVoltageCmd
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
Enables or disables the Low Power Regulator low voltage mode.
Definition: stm32f4xx_pwr.c:513
+
PWR_OverDriveCmd
void PWR_OverDriveCmd(FunctionalState NewState)
Enables or disables the Over-Drive.
Definition: stm32f4xx_pwr.c:418
+
PWR_UnderDriveCmd
void PWR_UnderDriveCmd(FunctionalState NewState)
Enables or disables the Under-Drive mode.
Definition: stm32f4xx_pwr.c:463
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
PWR_EnterSTANDBYMode
void PWR_EnterSTANDBYMode(void)
Enters STANDBY mode.
Definition: stm32f4xx_pwr.c:814
+
PWR_DeInit
void PWR_DeInit(void)
Deinitializes the PWR peripheral registers to their default reset values.
Definition: stm32f4xx_pwr.c:142
+
PWR_OverDriveSWCmd
void PWR_OverDriveSWCmd(FunctionalState NewState)
Enables or disables the Over-Drive switching.
Definition: stm32f4xx_pwr.c:436
+
PWR_FlashPowerDownCmd
void PWR_FlashPowerDownCmd(FunctionalState NewState)
Enables or disables the Flash Power Down in STOP mode.
Definition: stm32f4xx_pwr.c:555
+
PWR_EnterUnderDriveSTOPMode
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
Enters in Under-Drive STOP mode.
Definition: stm32f4xx_pwr.c:765
+
PWR_PVDLevelConfig
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
Definition: stm32f4xx_pwr.c:205
+
PWR_WakeUpPinCmd
void PWR_WakeUpPinCmd(FunctionalState NewState)
Enables or disables the WakeUp Pin functionality.
Definition: stm32f4xx_pwr.c:264
+
PWR_BackupRegulatorCmd
void PWR_BackupRegulatorCmd(FunctionalState NewState)
Enables or disables the Backup Regulator.
Definition: stm32f4xx_pwr.c:361
+
PWR_ClearFlag
void PWR_ClearFlag(uint32_t PWR_FLAG)
Clears the PWR's pending flags.
Definition: stm32f4xx_pwr.c:902
+
PWR_MainRegulatorLowVoltageCmd
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
Enables or disables the Main Regulator low voltage mode.
Definition: stm32f4xx_pwr.c:489
+
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+ + diff --git a/stm32f4xx__rcc_8c.html b/stm32f4xx__rcc_8c.html new file mode 100644 index 0000000..b6f6da5 --- /dev/null +++ b/stm32f4xx__rcc_8c.html @@ -0,0 +1,414 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_rcc.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_rcc.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: +More...

+
#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_rcc.c:
+
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+Macros

+#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
 
+#define CR_OFFSET   (RCC_OFFSET + 0x00)
 
+#define HSION_BitNumber   0x00
 
+#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
 
+#define CSSON_BitNumber   0x13
 
+#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
 
+#define PLLON_BitNumber   0x18
 
+#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
 
+#define PLLI2SON_BitNumber   0x1A
 
+#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
 
+#define PLLSAION_BitNumber   0x1C
 
+#define CR_PLLSAION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
 
+#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
 
+#define I2SSRC_BitNumber   0x17
 
+#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
 
+#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
 
+#define RTCEN_BitNumber   0x0F
 
+#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
 
+#define BDRST_BitNumber   0x10
 
+#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
 
+#define CSR_OFFSET   (RCC_OFFSET + 0x74)
 
+#define LSION_BitNumber   0x00
 
+#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
 
+#define DCKCFGR_OFFSET   (RCC_OFFSET + 0x8C)
 
+#define TIMPRE_BitNumber   0x18
 
+#define DCKCFGR_TIMPRE_BB   (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
 
+#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)
 
+#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)
 
+#define FLAG_MASK   ((uint8_t)0x1F)
 
+#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
 
+#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
 
+#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
 
+#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state. More...
 
void RCC_HSEConfig (uint8_t RCC_HSE)
 Configures the External High Speed oscillator (HSE). More...
 
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up. More...
 
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value. More...
 
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI). More...
 
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE). More...
 
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI). More...
 
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 Configures the main PLL clock source, multiplication and division factors. More...
 
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the main PLL. More...
 
void RCC_PLLI2SCmd (FunctionalState NewState)
 Enables or disables the PLLI2S. More...
 
void RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
 Configures the PLLSAI clock multiplication and division factors. More...
 
void RCC_PLLSAICmd (FunctionalState NewState)
 Enables or disables the PLLSAI. More...
 
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System. More...
 
void RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 Selects the clock source to output on MCO1 pin(PA8). More...
 
void RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 Selects the clock source to output on MCO2 pin(PC9). More...
 
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK). More...
 
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock. More...
 
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK). More...
 
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1). More...
 
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2). More...
 
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...
 
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
 Configures the SAI clock Divider coming from PLLI2S. More...
 
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
 Configures the SAI clock Divider coming from PLLSAI. More...
 
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
 Configures SAI1BlockA clock source selection. More...
 
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
 Configures SAI1BlockB clock source selection. More...
 
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
 Configures the LTDC clock Divider coming from PLLSAI. More...
 
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
 Configures the Timers clocks prescalers selection. More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_LSEModeConfig (uint8_t Mode)
 Configures the External Low Speed oscillator mode (LSE mode). More...
 
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts. More...
 
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not. More...
 
void RCC_ClearFlag (void)
 Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...
 
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not. More...
 
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Internal/external clocks, PLL, CSS and MCO configuration
    • +
  • System, AHB and APB busses clocks configuration
    • +
  • Peripheral clocks configuration
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                     ##### RCC specific features #####
+===============================================================================
+   [..]  
+     After reset the device is running from Internal High Speed oscillator 
+     (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+     and I-Cache are disabled, and all peripherals are off except internal
+     SRAM, Flash and JTAG.
+     (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+         all peripherals mapped on these busses are running at HSI speed.
+     (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+     (+) All GPIOs are in input floating state, except the JTAG pins which
+         are assigned to be used for debug purpose.
+   [..]          
+     Once the device started from reset, the user application has to:        
+     (+) Configure the clock source to be used to drive the System clock
+         (if the application needs higher frequency/performance)
+     (+) Configure the System clock frequency and Flash settings  
+     (+) Configure the AHB and APB busses prescalers
+     (+) Enable the clock for the peripheral(s) to be used
+     (+) Configure the clock source(s) for peripherals which clocks are not
+         derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)                                
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rcc_8c__incl.map b/stm32f4xx__rcc_8c__incl.map new file mode 100644 index 0000000..386395b --- /dev/null +++ b/stm32f4xx__rcc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rcc_8c__incl.md5 b/stm32f4xx__rcc_8c__incl.md5 new file mode 100644 index 0000000..2692c88 --- /dev/null +++ b/stm32f4xx__rcc_8c__incl.md5 @@ -0,0 +1 @@ +8ce613f73ef18eb0b51f2eff9476e00d \ No newline at end of file diff --git a/stm32f4xx__rcc_8c__incl.png b/stm32f4xx__rcc_8c__incl.png new file mode 100644 index 0000000..a8195b0 Binary files /dev/null and b/stm32f4xx__rcc_8c__incl.png differ diff --git a/stm32f4xx__rcc_8h.html b/stm32f4xx__rcc_8h.html new file mode 100644 index 0000000..07004df --- /dev/null +++ b/stm32f4xx__rcc_8h.html @@ -0,0 +1,988 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_rcc.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + +
+ +
+ + +
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+
+Classes | +Macros | +Functions
+
+
stm32f4xx_rcc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the RCC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_rcc.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+

Go to the source code of this file.

+ + + + +

+Classes

struct  RCC_ClocksTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RCC_HSE_OFF   ((uint8_t)0x00)
 
+#define RCC_HSE_ON   ((uint8_t)0x01)
 
+#define RCC_HSE_Bypass   ((uint8_t)0x05)
 
#define IS_RCC_HSE(HSE)
 
+#define RCC_LSE_LOWPOWER_MODE   ((uint8_t)0x00)
 
+#define RCC_LSE_HIGHDRIVE_MODE   ((uint8_t)0x01)
 
#define IS_RCC_LSE_MODE(MODE)
 
+#define RCC_PLLSource_HSI   ((uint32_t)0x00000000)
 
+#define RCC_PLLSource_HSE   ((uint32_t)0x00400000)
 
#define IS_RCC_PLL_SOURCE(SOURCE)
 
+#define IS_RCC_PLLM_VALUE(VALUE)   ((VALUE) <= 63)
 
+#define IS_RCC_PLLN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLP_VALUE(VALUE)   (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
 
+#define IS_RCC_PLLQ_VALUE(VALUE)   ((4 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLI2SN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLI2SR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
+#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((VALUE) <= 63)
 
+#define IS_RCC_PLLI2SQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLSAIN_VALUE(VALUE)   ((192 <= (VALUE)) && ((VALUE) <= 432))
 
+#define IS_RCC_PLLSAIQ_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 15))
 
+#define IS_RCC_PLLSAIR_VALUE(VALUE)   ((2 <= (VALUE)) && ((VALUE) <= 7))
 
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE)   ((1 <= (VALUE)) && ((VALUE) <= 32))
 
+#define RCC_PLLSAIDivR_Div2   ((uint32_t)0x00000000)
 
+#define RCC_PLLSAIDivR_Div4   ((uint32_t)0x00010000)
 
+#define RCC_PLLSAIDivR_Div8   ((uint32_t)0x00020000)
 
+#define RCC_PLLSAIDivR_Div16   ((uint32_t)0x00030000)
 
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE)
 
+#define RCC_SYSCLKSource_HSI   ((uint32_t)0x00000000)
 
+#define RCC_SYSCLKSource_HSE   ((uint32_t)0x00000001)
 
+#define RCC_SYSCLKSource_PLLCLK   ((uint32_t)0x00000002)
 
#define IS_RCC_SYSCLK_SOURCE(SOURCE)
 
+#define RCC_SYSCLK_Div1   ((uint32_t)0x00000000)
 
+#define RCC_SYSCLK_Div2   ((uint32_t)0x00000080)
 
+#define RCC_SYSCLK_Div4   ((uint32_t)0x00000090)
 
+#define RCC_SYSCLK_Div8   ((uint32_t)0x000000A0)
 
+#define RCC_SYSCLK_Div16   ((uint32_t)0x000000B0)
 
+#define RCC_SYSCLK_Div64   ((uint32_t)0x000000C0)
 
+#define RCC_SYSCLK_Div128   ((uint32_t)0x000000D0)
 
+#define RCC_SYSCLK_Div256   ((uint32_t)0x000000E0)
 
+#define RCC_SYSCLK_Div512   ((uint32_t)0x000000F0)
 
#define IS_RCC_HCLK(HCLK)
 
+#define RCC_HCLK_Div1   ((uint32_t)0x00000000)
 
+#define RCC_HCLK_Div2   ((uint32_t)0x00001000)
 
+#define RCC_HCLK_Div4   ((uint32_t)0x00001400)
 
+#define RCC_HCLK_Div8   ((uint32_t)0x00001800)
 
+#define RCC_HCLK_Div16   ((uint32_t)0x00001C00)
 
#define IS_RCC_PCLK(PCLK)
 
+#define RCC_IT_LSIRDY   ((uint8_t)0x01)
 
+#define RCC_IT_LSERDY   ((uint8_t)0x02)
 
+#define RCC_IT_HSIRDY   ((uint8_t)0x04)
 
+#define RCC_IT_HSERDY   ((uint8_t)0x08)
 
+#define RCC_IT_PLLRDY   ((uint8_t)0x10)
 
+#define RCC_IT_PLLI2SRDY   ((uint8_t)0x20)
 
+#define RCC_IT_PLLSAIRDY   ((uint8_t)0x40)
 
+#define RCC_IT_CSS   ((uint8_t)0x80)
 
+#define IS_RCC_IT(IT)   ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
 
#define IS_RCC_GET_IT(IT)
 
+#define IS_RCC_CLEAR_IT(IT)   ((IT) != 0x00)
 
+#define RCC_LSE_OFF   ((uint8_t)0x00)
 
+#define RCC_LSE_ON   ((uint8_t)0x01)
 
+#define RCC_LSE_Bypass   ((uint8_t)0x04)
 
#define IS_RCC_LSE(LSE)
 
+#define RCC_RTCCLKSource_LSE   ((uint32_t)0x00000100)
 
+#define RCC_RTCCLKSource_LSI   ((uint32_t)0x00000200)
 
+#define RCC_RTCCLKSource_HSE_Div2   ((uint32_t)0x00020300)
 
+#define RCC_RTCCLKSource_HSE_Div3   ((uint32_t)0x00030300)
 
+#define RCC_RTCCLKSource_HSE_Div4   ((uint32_t)0x00040300)
 
+#define RCC_RTCCLKSource_HSE_Div5   ((uint32_t)0x00050300)
 
+#define RCC_RTCCLKSource_HSE_Div6   ((uint32_t)0x00060300)
 
+#define RCC_RTCCLKSource_HSE_Div7   ((uint32_t)0x00070300)
 
+#define RCC_RTCCLKSource_HSE_Div8   ((uint32_t)0x00080300)
 
+#define RCC_RTCCLKSource_HSE_Div9   ((uint32_t)0x00090300)
 
+#define RCC_RTCCLKSource_HSE_Div10   ((uint32_t)0x000A0300)
 
+#define RCC_RTCCLKSource_HSE_Div11   ((uint32_t)0x000B0300)
 
+#define RCC_RTCCLKSource_HSE_Div12   ((uint32_t)0x000C0300)
 
+#define RCC_RTCCLKSource_HSE_Div13   ((uint32_t)0x000D0300)
 
+#define RCC_RTCCLKSource_HSE_Div14   ((uint32_t)0x000E0300)
 
+#define RCC_RTCCLKSource_HSE_Div15   ((uint32_t)0x000F0300)
 
+#define RCC_RTCCLKSource_HSE_Div16   ((uint32_t)0x00100300)
 
+#define RCC_RTCCLKSource_HSE_Div17   ((uint32_t)0x00110300)
 
+#define RCC_RTCCLKSource_HSE_Div18   ((uint32_t)0x00120300)
 
+#define RCC_RTCCLKSource_HSE_Div19   ((uint32_t)0x00130300)
 
+#define RCC_RTCCLKSource_HSE_Div20   ((uint32_t)0x00140300)
 
+#define RCC_RTCCLKSource_HSE_Div21   ((uint32_t)0x00150300)
 
+#define RCC_RTCCLKSource_HSE_Div22   ((uint32_t)0x00160300)
 
+#define RCC_RTCCLKSource_HSE_Div23   ((uint32_t)0x00170300)
 
+#define RCC_RTCCLKSource_HSE_Div24   ((uint32_t)0x00180300)
 
+#define RCC_RTCCLKSource_HSE_Div25   ((uint32_t)0x00190300)
 
+#define RCC_RTCCLKSource_HSE_Div26   ((uint32_t)0x001A0300)
 
+#define RCC_RTCCLKSource_HSE_Div27   ((uint32_t)0x001B0300)
 
+#define RCC_RTCCLKSource_HSE_Div28   ((uint32_t)0x001C0300)
 
+#define RCC_RTCCLKSource_HSE_Div29   ((uint32_t)0x001D0300)
 
+#define RCC_RTCCLKSource_HSE_Div30   ((uint32_t)0x001E0300)
 
+#define RCC_RTCCLKSource_HSE_Div31   ((uint32_t)0x001F0300)
 
+#define IS_RCC_RTCCLK_SOURCE(SOURCE)
 
+#define RCC_I2S2CLKSource_PLLI2S   ((uint8_t)0x00)
 
+#define RCC_I2S2CLKSource_Ext   ((uint8_t)0x01)
 
+#define IS_RCC_I2SCLK_SOURCE(SOURCE)   (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
 
+#define RCC_SAIACLKSource_PLLSAI   ((uint32_t)0x00000000)
 
+#define RCC_SAIACLKSource_PLLI2S   ((uint32_t)0x00100000)
 
+#define RCC_SAIACLKSource_Ext   ((uint32_t)0x00200000)
 
#define IS_RCC_SAIACLK_SOURCE(SOURCE)
 
+#define RCC_SAIBCLKSource_PLLSAI   ((uint32_t)0x00000000)
 
+#define RCC_SAIBCLKSource_PLLI2S   ((uint32_t)0x00400000)
 
+#define RCC_SAIBCLKSource_Ext   ((uint32_t)0x00800000)
 
#define IS_RCC_SAIBCLK_SOURCE(SOURCE)
 
+#define RCC_TIMPrescDesactivated   ((uint8_t)0x00)
 
+#define RCC_TIMPrescActivated   ((uint8_t)0x01)
 
+#define IS_RCC_TIMCLK_PRESCALER(VALUE)   (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
 
+#define RCC_AHB1Periph_GPIOA   ((uint32_t)0x00000001)
 
+#define RCC_AHB1Periph_GPIOB   ((uint32_t)0x00000002)
 
+#define RCC_AHB1Periph_GPIOC   ((uint32_t)0x00000004)
 
+#define RCC_AHB1Periph_GPIOD   ((uint32_t)0x00000008)
 
+#define RCC_AHB1Periph_GPIOE   ((uint32_t)0x00000010)
 
+#define RCC_AHB1Periph_GPIOF   ((uint32_t)0x00000020)
 
+#define RCC_AHB1Periph_GPIOG   ((uint32_t)0x00000040)
 
+#define RCC_AHB1Periph_GPIOH   ((uint32_t)0x00000080)
 
+#define RCC_AHB1Periph_GPIOI   ((uint32_t)0x00000100)
 
+#define RCC_AHB1Periph_GPIOJ   ((uint32_t)0x00000200)
 
+#define RCC_AHB1Periph_GPIOK   ((uint32_t)0x00000400)
 
+#define RCC_AHB1Periph_CRC   ((uint32_t)0x00001000)
 
+#define RCC_AHB1Periph_FLITF   ((uint32_t)0x00008000)
 
+#define RCC_AHB1Periph_SRAM1   ((uint32_t)0x00010000)
 
+#define RCC_AHB1Periph_SRAM2   ((uint32_t)0x00020000)
 
+#define RCC_AHB1Periph_BKPSRAM   ((uint32_t)0x00040000)
 
+#define RCC_AHB1Periph_SRAM3   ((uint32_t)0x00080000)
 
+#define RCC_AHB1Periph_CCMDATARAMEN   ((uint32_t)0x00100000)
 
+#define RCC_AHB1Periph_DMA1   ((uint32_t)0x00200000)
 
+#define RCC_AHB1Periph_DMA2   ((uint32_t)0x00400000)
 
+#define RCC_AHB1Periph_DMA2D   ((uint32_t)0x00800000)
 
+#define RCC_AHB1Periph_ETH_MAC   ((uint32_t)0x02000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Tx   ((uint32_t)0x04000000)
 
+#define RCC_AHB1Periph_ETH_MAC_Rx   ((uint32_t)0x08000000)
 
+#define RCC_AHB1Periph_ETH_MAC_PTP   ((uint32_t)0x10000000)
 
+#define RCC_AHB1Periph_OTG_HS   ((uint32_t)0x20000000)
 
+#define RCC_AHB1Periph_OTG_HS_ULPI   ((uint32_t)0x40000000)
 
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH)   ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH)   ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH)   ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
 
+#define RCC_AHB2Periph_DCMI   ((uint32_t)0x00000001)
 
+#define RCC_AHB2Periph_CRYP   ((uint32_t)0x00000010)
 
+#define RCC_AHB2Periph_HASH   ((uint32_t)0x00000020)
 
+#define RCC_AHB2Periph_RNG   ((uint32_t)0x00000040)
 
+#define RCC_AHB2Periph_OTG_FS   ((uint32_t)0x00000080)
 
+#define IS_RCC_AHB2_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
 
+#define RCC_AHB3Periph_FSMC   ((uint32_t)0x00000001)
 
+#define IS_RCC_AHB3_PERIPH(PERIPH)   ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
 
+#define RCC_APB1Periph_TIM2   ((uint32_t)0x00000001)
 
+#define RCC_APB1Periph_TIM3   ((uint32_t)0x00000002)
 
+#define RCC_APB1Periph_TIM4   ((uint32_t)0x00000004)
 
+#define RCC_APB1Periph_TIM5   ((uint32_t)0x00000008)
 
+#define RCC_APB1Periph_TIM6   ((uint32_t)0x00000010)
 
+#define RCC_APB1Periph_TIM7   ((uint32_t)0x00000020)
 
+#define RCC_APB1Periph_TIM12   ((uint32_t)0x00000040)
 
+#define RCC_APB1Periph_TIM13   ((uint32_t)0x00000080)
 
+#define RCC_APB1Periph_TIM14   ((uint32_t)0x00000100)
 
+#define RCC_APB1Periph_WWDG   ((uint32_t)0x00000800)
 
+#define RCC_APB1Periph_SPI2   ((uint32_t)0x00004000)
 
+#define RCC_APB1Periph_SPI3   ((uint32_t)0x00008000)
 
+#define RCC_APB1Periph_USART2   ((uint32_t)0x00020000)
 
+#define RCC_APB1Periph_USART3   ((uint32_t)0x00040000)
 
+#define RCC_APB1Periph_UART4   ((uint32_t)0x00080000)
 
+#define RCC_APB1Periph_UART5   ((uint32_t)0x00100000)
 
+#define RCC_APB1Periph_I2C1   ((uint32_t)0x00200000)
 
+#define RCC_APB1Periph_I2C2   ((uint32_t)0x00400000)
 
+#define RCC_APB1Periph_I2C3   ((uint32_t)0x00800000)
 
+#define RCC_APB1Periph_CAN1   ((uint32_t)0x02000000)
 
+#define RCC_APB1Periph_CAN2   ((uint32_t)0x04000000)
 
+#define RCC_APB1Periph_PWR   ((uint32_t)0x10000000)
 
+#define RCC_APB1Periph_DAC   ((uint32_t)0x20000000)
 
+#define RCC_APB1Periph_UART7   ((uint32_t)0x40000000)
 
+#define RCC_APB1Periph_UART8   ((uint32_t)0x80000000)
 
+#define IS_RCC_APB1_PERIPH(PERIPH)   ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
 
+#define RCC_APB2Periph_TIM1   ((uint32_t)0x00000001)
 
+#define RCC_APB2Periph_TIM8   ((uint32_t)0x00000002)
 
+#define RCC_APB2Periph_USART1   ((uint32_t)0x00000010)
 
+#define RCC_APB2Periph_USART6   ((uint32_t)0x00000020)
 
+#define RCC_APB2Periph_ADC   ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC1   ((uint32_t)0x00000100)
 
+#define RCC_APB2Periph_ADC2   ((uint32_t)0x00000200)
 
+#define RCC_APB2Periph_ADC3   ((uint32_t)0x00000400)
 
+#define RCC_APB2Periph_SDIO   ((uint32_t)0x00000800)
 
+#define RCC_APB2Periph_SPI1   ((uint32_t)0x00001000)
 
+#define RCC_APB2Periph_SPI4   ((uint32_t)0x00002000)
 
+#define RCC_APB2Periph_SYSCFG   ((uint32_t)0x00004000)
 
+#define RCC_APB2Periph_TIM9   ((uint32_t)0x00010000)
 
+#define RCC_APB2Periph_TIM10   ((uint32_t)0x00020000)
 
+#define RCC_APB2Periph_TIM11   ((uint32_t)0x00040000)
 
+#define RCC_APB2Periph_SPI5   ((uint32_t)0x00100000)
 
+#define RCC_APB2Periph_SPI6   ((uint32_t)0x00200000)
 
+#define RCC_APB2Periph_SAI1   ((uint32_t)0x00400000)
 
+#define RCC_APB2Periph_LTDC   ((uint32_t)0x04000000)
 
+#define IS_RCC_APB2_PERIPH(PERIPH)   ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
 
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH)   ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
 
+#define RCC_MCO1Source_HSI   ((uint32_t)0x00000000)
 
+#define RCC_MCO1Source_LSE   ((uint32_t)0x00200000)
 
+#define RCC_MCO1Source_HSE   ((uint32_t)0x00400000)
 
+#define RCC_MCO1Source_PLLCLK   ((uint32_t)0x00600000)
 
+#define RCC_MCO1Div_1   ((uint32_t)0x00000000)
 
+#define RCC_MCO1Div_2   ((uint32_t)0x04000000)
 
+#define RCC_MCO1Div_3   ((uint32_t)0x05000000)
 
+#define RCC_MCO1Div_4   ((uint32_t)0x06000000)
 
+#define RCC_MCO1Div_5   ((uint32_t)0x07000000)
 
#define IS_RCC_MCO1SOURCE(SOURCE)
 
#define IS_RCC_MCO1DIV(DIV)
 
+#define RCC_MCO2Source_SYSCLK   ((uint32_t)0x00000000)
 
+#define RCC_MCO2Source_PLLI2SCLK   ((uint32_t)0x40000000)
 
+#define RCC_MCO2Source_HSE   ((uint32_t)0x80000000)
 
+#define RCC_MCO2Source_PLLCLK   ((uint32_t)0xC0000000)
 
+#define RCC_MCO2Div_1   ((uint32_t)0x00000000)
 
+#define RCC_MCO2Div_2   ((uint32_t)0x20000000)
 
+#define RCC_MCO2Div_3   ((uint32_t)0x28000000)
 
+#define RCC_MCO2Div_4   ((uint32_t)0x30000000)
 
+#define RCC_MCO2Div_5   ((uint32_t)0x38000000)
 
#define IS_RCC_MCO2SOURCE(SOURCE)
 
#define IS_RCC_MCO2DIV(DIV)
 
+#define RCC_FLAG_HSIRDY   ((uint8_t)0x21)
 
+#define RCC_FLAG_HSERDY   ((uint8_t)0x31)
 
+#define RCC_FLAG_PLLRDY   ((uint8_t)0x39)
 
+#define RCC_FLAG_PLLI2SRDY   ((uint8_t)0x3B)
 
+#define RCC_FLAG_PLLSAIRDY   ((uint8_t)0x3D)
 
+#define RCC_FLAG_LSERDY   ((uint8_t)0x41)
 
+#define RCC_FLAG_LSIRDY   ((uint8_t)0x61)
 
+#define RCC_FLAG_BORRST   ((uint8_t)0x79)
 
+#define RCC_FLAG_PINRST   ((uint8_t)0x7A)
 
+#define RCC_FLAG_PORRST   ((uint8_t)0x7B)
 
+#define RCC_FLAG_SFTRST   ((uint8_t)0x7C)
 
+#define RCC_FLAG_IWDGRST   ((uint8_t)0x7D)
 
+#define RCC_FLAG_WWDGRST   ((uint8_t)0x7E)
 
+#define RCC_FLAG_LPWRRST   ((uint8_t)0x7F)
 
#define IS_RCC_FLAG(FLAG)
 
+#define IS_RCC_CALIBRATION_VALUE(VALUE)   ((VALUE) <= 0x1F)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state. More...
 
void RCC_HSEConfig (uint8_t RCC_HSE)
 Configures the External High Speed oscillator (HSE). More...
 
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up. More...
 
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value. More...
 
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI). More...
 
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE). More...
 
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI). More...
 
void RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
 Configures the main PLL clock source, multiplication and division factors. More...
 
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the main PLL. More...
 
+void RCC_PLLI2SConfig (uint32_t PLLI2SN, uint32_t PLLI2SR)
 
void RCC_PLLI2SCmd (FunctionalState NewState)
 Enables or disables the PLLI2S. More...
 
void RCC_PLLSAIConfig (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
 Configures the PLLSAI clock multiplication and division factors. More...
 
void RCC_PLLSAICmd (FunctionalState NewState)
 Enables or disables the PLLSAI. More...
 
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System. More...
 
void RCC_MCO1Config (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
 Selects the clock source to output on MCO1 pin(PA8). More...
 
void RCC_MCO2Config (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
 Selects the clock source to output on MCO2 pin(PC9). More...
 
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK). More...
 
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock. More...
 
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK). More...
 
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1). More...
 
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2). More...
 
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More...
 
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK). More...
 
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock. More...
 
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset. More...
 
void RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource)
 Configures the I2S clock source (I2SCLK). More...
 
void RCC_SAIPLLI2SClkDivConfig (uint32_t RCC_PLLI2SDivQ)
 Configures the SAI clock Divider coming from PLLI2S. More...
 
void RCC_SAIPLLSAIClkDivConfig (uint32_t RCC_PLLSAIDivQ)
 Configures the SAI clock Divider coming from PLLSAI. More...
 
void RCC_SAIBlockACLKConfig (uint32_t RCC_SAIBlockACLKSource)
 Configures SAI1BlockA clock source selection. More...
 
void RCC_SAIBlockBCLKConfig (uint32_t RCC_SAIBlockBCLKSource)
 Configures SAI1BlockB clock source selection. More...
 
void RCC_LTDCCLKDivConfig (uint32_t RCC_PLLSAIDivR)
 Configures the LTDC clock Divider coming from PLLSAI. More...
 
void RCC_TIMCLKPresConfig (uint32_t RCC_TIMCLKPrescaler)
 Configures the Timers clocks prescalers selection. More...
 
void RCC_AHB1PeriphClockCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock. More...
 
void RCC_AHB2PeriphClockCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock. More...
 
void RCC_AHB3PeriphClockCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock. More...
 
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock. More...
 
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock. More...
 
void RCC_AHB1PeriphResetCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Forces or releases AHB1 peripheral reset. More...
 
void RCC_AHB2PeriphResetCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Forces or releases AHB2 peripheral reset. More...
 
void RCC_AHB3PeriphResetCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Forces or releases AHB3 peripheral reset. More...
 
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset. More...
 
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset. More...
 
void RCC_AHB1PeriphClockLPModeCmd (uint32_t RCC_AHB1Periph, FunctionalState NewState)
 Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB2PeriphClockLPModeCmd (uint32_t RCC_AHB2Periph, FunctionalState NewState)
 Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_AHB3PeriphClockLPModeCmd (uint32_t RCC_AHB3Periph, FunctionalState NewState)
 Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. More...
 
void RCC_LSEModeConfig (uint8_t Mode)
 Configures the External Low Speed oscillator mode (LSE mode). More...
 
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts. More...
 
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not. More...
 
void RCC_ClearFlag (void)
 Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...
 
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not. More...
 
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the RCC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rcc_8h__dep__incl.map b/stm32f4xx__rcc_8h__dep__incl.map new file mode 100644 index 0000000..69b0837 --- /dev/null +++ b/stm32f4xx__rcc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rcc_8h__dep__incl.md5 b/stm32f4xx__rcc_8h__dep__incl.md5 new file mode 100644 index 0000000..7bab753 --- /dev/null +++ b/stm32f4xx__rcc_8h__dep__incl.md5 @@ -0,0 +1 @@ +2575ea332e2ed8bccd6cc8940da2fa86 \ No newline at end of file diff --git a/stm32f4xx__rcc_8h__dep__incl.png b/stm32f4xx__rcc_8h__dep__incl.png new file mode 100644 index 0000000..6bec0b9 Binary files /dev/null and b/stm32f4xx__rcc_8h__dep__incl.png differ diff --git a/stm32f4xx__rcc_8h__incl.map b/stm32f4xx__rcc_8h__incl.map new file mode 100644 index 0000000..79a9dc3 --- /dev/null +++ b/stm32f4xx__rcc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rcc_8h__incl.md5 b/stm32f4xx__rcc_8h__incl.md5 new file mode 100644 index 0000000..20de7f8 --- /dev/null +++ b/stm32f4xx__rcc_8h__incl.md5 @@ -0,0 +1 @@ +3c3cd63c2c5e0c2b3bec6add7ec3d052 \ No newline at end of file diff --git a/stm32f4xx__rcc_8h__incl.png b/stm32f4xx__rcc_8h__incl.png new file mode 100644 index 0000000..c0719db Binary files /dev/null and b/stm32f4xx__rcc_8h__incl.png differ diff --git a/stm32f4xx__rcc_8h_source.html b/stm32f4xx__rcc_8h_source.html new file mode 100644 index 0000000..d01f304 --- /dev/null +++ b/stm32f4xx__rcc_8h_source.html @@ -0,0 +1,609 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_rcc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + + + +
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+ + +
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+
+
stm32f4xx_rcc.h
+
+
+Go to the documentation of this file.
1 
+
28 /* Define to prevent recursive inclusion -------------------------------------*/
+
29 #ifndef __STM32F4xx_RCC_H
+
30 #define __STM32F4xx_RCC_H
+
31 
+
32 #ifdef __cplusplus
+
33  extern "C" {
+
34 #endif
+
35 
+
36 /* Includes ------------------------------------------------------------------*/
+
37 #include "stm32f4xx.h"
+
38 
+
47 /* Exported types ------------------------------------------------------------*/
+
48 typedef struct
+
49 {
+
50  uint32_t SYSCLK_Frequency;
+
51  uint32_t HCLK_Frequency;
+
52  uint32_t PCLK1_Frequency;
+
53  uint32_t PCLK2_Frequency;
+
54 }RCC_ClocksTypeDef;
+
55 
+
56 /* Exported constants --------------------------------------------------------*/
+
57 
+
65 #define RCC_HSE_OFF ((uint8_t)0x00)
+
66 #define RCC_HSE_ON ((uint8_t)0x01)
+
67 #define RCC_HSE_Bypass ((uint8_t)0x05)
+
68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+
69  ((HSE) == RCC_HSE_Bypass))
+
70 
+
77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
+
78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
+
79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
+
80  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+
81 
+
88 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
+
89 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
+
90 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+
91  ((SOURCE) == RCC_PLLSource_HSE))
+
92 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+
93 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+
94 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+
95 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+
96 
+
97 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+
98 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
99 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
+
100 
+
101 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
102 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+
103 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+
104 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
105 
+
106 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
107 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
108 
+
109 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
+
110 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
+
111 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
+
112 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
+
113 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
+
114  ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
+
115  ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
+
116  ((VALUE) == RCC_PLLSAIDivR_Div16))
+
117 
+
125 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+
126 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+
127 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+
128 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+
129  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+
130  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+
131 
+
138 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+
139 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+
140 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+
141 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+
142 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+
143 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+
144 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+
145 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+
146 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
+
147 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+
148  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+
149  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+
150  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+
151  ((HCLK) == RCC_SYSCLK_Div512))
+
152 
+
159 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+
160 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
+
161 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
+
162 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
+
163 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
+
164 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+
165  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+
166  ((PCLK) == RCC_HCLK_Div16))
+
167 
+
174 #define RCC_IT_LSIRDY ((uint8_t)0x01)
+
175 #define RCC_IT_LSERDY ((uint8_t)0x02)
+
176 #define RCC_IT_HSIRDY ((uint8_t)0x04)
+
177 #define RCC_IT_HSERDY ((uint8_t)0x08)
+
178 #define RCC_IT_PLLRDY ((uint8_t)0x10)
+
179 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
+
180 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
+
181 #define RCC_IT_CSS ((uint8_t)0x80)
+
182 
+
183 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+
184 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+
185  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+
186  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+
187  ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
+
188 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
+
189 
+
197 #define RCC_LSE_OFF ((uint8_t)0x00)
+
198 #define RCC_LSE_ON ((uint8_t)0x01)
+
199 #define RCC_LSE_Bypass ((uint8_t)0x04)
+
200 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+
201  ((LSE) == RCC_LSE_Bypass))
+
202 
+
209 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+
210 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+
211 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
+
212 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
+
213 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
+
214 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
+
215 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
+
216 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
+
217 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
+
218 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
+
219 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
+
220 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
+
221 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
+
222 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
+
223 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
+
224 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
+
225 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
+
226 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
+
227 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
+
228 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
+
229 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
+
230 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
+
231 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
+
232 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
+
233 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
+
234 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
+
235 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
+
236 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
+
237 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
+
238 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
+
239 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
+
240 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
+
241 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+
242  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+
243  ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
+
244  ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
+
245  ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
+
246  ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
+
247  ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
+
248  ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
+
249  ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
+
250  ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
+
251  ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
+
252  ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
+
253  ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
+
254  ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
+
255  ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
+
256  ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
+
257  ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
+
258  ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
+
259  ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
+
260  ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
+
261  ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
+
262  ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
+
263  ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
+
264  ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
+
265  ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
+
266  ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
+
267  ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
+
268  ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
+
269  ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
+
270  ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
+
271  ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
+
272  ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
+
273 
+
280 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
+
281 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
+
282 
+
283 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
+
284 
+
291 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
+
292 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
+
293 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
+
294 
+
295 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
+
296  ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
+
297  ((SOURCE) == RCC_SAIACLKSource_Ext))
+
298 
+
305 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
+
306 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
+
307 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
+
308 
+
309 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
+
310  ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
+
311  ((SOURCE) == RCC_SAIBCLKSource_Ext))
+
312 
+
319 #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
+
320 #define RCC_TIMPrescActivated ((uint8_t)0x01)
+
321 
+
322 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
+
323 
+
330 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
+
331 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
+
332 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
+
333 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
+
334 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
+
335 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
+
336 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
+
337 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
+
338 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
+
339 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
+
340 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
+
341 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
+
342 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
+
343 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
+
344 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
+
345 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
+
346 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
+
347 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
+
348 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
+
349 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
+
350 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
+
351 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
+
352 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
+
353 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
+
354 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
+
355 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
+
356 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
+
357 
+
358 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
+
359 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
+
360 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
+
361 
+
369 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
+
370 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
+
371 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
+
372 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
+
373 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
+
374 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
+
375 
+
382 #if defined (STM32F40_41xxx)
+
383 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
+
384 #endif /* STM32F40_41xxx */
+
385 
+
386 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
387 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+
388 #endif /* STM32F427_437xx || STM32F429_439xx */
+
389 
+
390 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+
391 
+
398 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+
399 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+
400 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+
401 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+
402 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+
403 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+
404 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
+
405 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
+
406 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+
407 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+
408 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+
409 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+
410 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+
411 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+
412 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+
413 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+
414 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+
415 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+
416 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
+
417 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+
418 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
419 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+
420 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+
421 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
+
422 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
+
423 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
+
424 
+
431 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
+
432 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
+
433 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
+
434 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
+
435 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
+
436 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
+
437 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
+
438 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
+
439 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
+
440 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+
441 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
+
442 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
+
443 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
+
444 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
+
445 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
+
446 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
+
447 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
+
448 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
+
449 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
+
450 
+
451 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
+
452 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
+
453 
+
461 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
+
462 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
+
463 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
+
464 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
+
465 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
+
466 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
+
467 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
+
468 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
+
469 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
+
470 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
+
471  ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
+
472 
+
473 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
+
474  ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
+
475  ((DIV) == RCC_MCO1Div_5))
+
476 
+
483 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
+
484 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
+
485 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
+
486 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
+
487 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
+
488 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
+
489 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
+
490 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
+
491 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
+
492 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
+
493  ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
+
494 
+
495 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
+
496  ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
+
497  ((DIV) == RCC_MCO2Div_5))
+
498 
+
505 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+
506 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
+
507 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+
508 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
+
509 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
+
510 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
+
511 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+
512 #define RCC_FLAG_BORRST ((uint8_t)0x79)
+
513 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
+
514 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
+
515 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+
516 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+
517 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+
518 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
519 
+
520 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+
521  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+
522  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
+
523  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+
524  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+
525  ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
+
526  ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
+
527 
+
528 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+
529 
+
537 /* Exported macro ------------------------------------------------------------*/
+
538 /* Exported functions --------------------------------------------------------*/
+
539 
+
540 /* Function used to set the RCC clock configuration to the default reset state */
+
541 void RCC_DeInit(void);
+
542 
+
543 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+
544 void RCC_HSEConfig(uint8_t RCC_HSE);
+
545 ErrorStatus RCC_WaitForHSEStartUp(void);
+
546 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+
547 void RCC_HSICmd(FunctionalState NewState);
+
548 void RCC_LSEConfig(uint8_t RCC_LSE);
+
549 void RCC_LSICmd(FunctionalState NewState);
+
550 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+
551 void RCC_PLLCmd(FunctionalState NewState);
+
552 
+
553 #if defined (STM32F40_41xxx) || defined (STM32F401xx)
+
554 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
+
555 #elif defined (STM32F411xE)
+
556 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
+
557 #elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
558 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
+
559 #else
+
560 #endif /* STM32F40_41xxx || STM32F401xx */
+
561 
+
562 void RCC_PLLI2SCmd(FunctionalState NewState);
+
563 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+
564 void RCC_PLLSAICmd(FunctionalState NewState);
+
565 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+
566 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
+
567 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
+
568 
+
569 /* System, AHB and APB busses clocks configuration functions ******************/
+
570 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+
571 uint8_t RCC_GetSYSCLKSource(void);
+
572 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+
573 void RCC_PCLK1Config(uint32_t RCC_HCLK);
+
574 void RCC_PCLK2Config(uint32_t RCC_HCLK);
+
575 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
576 
+
577 /* Peripheral clocks configuration functions **********************************/
+
578 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+
579 void RCC_RTCCLKCmd(FunctionalState NewState);
+
580 void RCC_BackupResetCmd(FunctionalState NewState);
+
581 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
+
582 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
+
583 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
+
584 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
+
585 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
+
586 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
+
587 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
+
588 
+
589 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+
590 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+
591 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+
592 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
593 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
594 
+
595 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+
596 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+
597 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+
598 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
599 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
600 
+
601 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+
602 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+
603 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+
604 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
605 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
606 
+
607 void RCC_LSEModeConfig(uint8_t Mode);
+
608 
+
609 /* Interrupts and flags management functions **********************************/
+
610 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
611 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+
612 void RCC_ClearFlag(void);
+
613 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+
614 void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
615 
+
616 #ifdef __cplusplus
+
617 }
+
618 #endif
+
619 
+
620 #endif /* __STM32F4xx_RCC_H */
+
621 
+
630 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
RCC_ClocksTypeDef::HCLK_Frequency
uint32_t HCLK_Frequency
Definition: stm32f4xx_rcc.h:51
+
RCC_AHB3PeriphClockCmd
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
Definition: stm32f4xx_rcc.c:1586
+
RCC_ClearFlag
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Definition: stm32f4xx_rcc.c:2227
+
RCC_PCLK1Config
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Definition: stm32f4xx_rcc.c:1014
+
RCC_GetITStatus
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
Definition: stm32f4xx_rcc.c:2247
+
RCC_ClearITPendingBit
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
Definition: stm32f4xx_rcc.c:2281
+
RCC_ClockSecuritySystemCmd
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
Definition: stm32f4xx_rcc.c:671
+
RCC_APB2PeriphClockCmd
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
Definition: stm32f4xx_rcc.c:1683
+
RCC_GetFlagStatus
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
Definition: stm32f4xx_rcc.c:2182
+
RCC_DeInit
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: stm32f4xx_rcc.c:213
+
RCC_ClocksTypeDef::SYSCLK_Frequency
uint32_t SYSCLK_Frequency
Definition: stm32f4xx_rcc.h:50
+
RCC_AHB2PeriphClockCmd
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
Definition: stm32f4xx_rcc.c:1558
+
RCC_AHB3PeriphClockLPModeCmd
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1978
+
RCC_AHB2PeriphClockLPModeCmd
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1950
+
RCC_HSICmd
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
Definition: stm32f4xx_rcc.c:354
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
RCC_RTCCLKConfig
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
Definition: stm32f4xx_rcc.c:1222
+
RCC_SAIPLLI2SClkDivConfig
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
Configures the SAI clock Divider coming from PLLI2S.
Definition: stm32f4xx_rcc.c:1309
+
RCC_APB1PeriphClockLPModeCmd
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:2030
+
RCC_LSICmd
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
Definition: stm32f4xx_rcc.c:419
+
RCC_PLLI2SCmd
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
Definition: stm32f4xx_rcc.c:606
+
RCC_PLLSAICmd
void RCC_PLLSAICmd(FunctionalState NewState)
Enables or disables the PLLSAI.
Definition: stm32f4xx_rcc.c:653
+
RCC_ITConfig
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
Definition: stm32f4xx_rcc.c:2145
+
RCC_PCLK2Config
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
Definition: stm32f4xx_rcc.c:1045
+
RCC_RTCCLKCmd
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
Definition: stm32f4xx_rcc.c:1254
+
RCC_LSEModeConfig
void RCC_LSEModeConfig(uint8_t Mode)
Configures the External Low Speed oscillator mode (LSE mode).
Definition: stm32f4xx_rcc.c:2099
+
RCC_AHB3PeriphResetCmd
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
Definition: stm32f4xx_rcc.c:1779
+
RCC_AdjustHSICalibrationValue
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
Definition: stm32f4xx_rcc.c:318
+
RCC_AHB1PeriphClockLPModeCmd
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1918
+
RCC_PLLSAIConfig
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
Configures the PLLSAI clock multiplication and division factors.
Definition: stm32f4xx_rcc.c:635
+
RCC_PLLConfig
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
Definition: stm32f4xx_rcc.c:462
+
RCC_MCO1Config
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
Definition: stm32f4xx_rcc.c:696
+
RCC_LTDCCLKDivConfig
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
Configures the LTDC clock Divider coming from PLLSAI.
Definition: stm32f4xx_rcc.c:1446
+
RCC_TIMCLKPresConfig
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.
Definition: stm32f4xx_rcc.c:1483
+
RCC_SAIBlockACLKConfig
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
Configures SAI1BlockA clock source selection.
Definition: stm32f4xx_rcc.c:1377
+
RCC_AHB1PeriphClockCmd
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
Definition: stm32f4xx_rcc.c:1526
+
RCC_MCO2Config
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
Definition: stm32f4xx_rcc.c:734
+
RCC_WaitForHSEStartUp
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
Definition: stm32f4xx_rcc.c:287
+
RCC_APB2PeriphClockLPModeCmd
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:2075
+
RCC_I2SCLKConfig
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
Definition: stm32f4xx_rcc.c:1288
+
RCC_AHB2PeriphResetCmd
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
Definition: stm32f4xx_rcc.c:1754
+
RCC_ClocksTypeDef::PCLK1_Frequency
uint32_t PCLK1_Frequency
Definition: stm32f4xx_rcc.h:52
+
RCC_HCLKConfig
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Definition: stm32f4xx_rcc.c:982
+
RCC_GetSYSCLKSource
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
Definition: stm32f4xx_rcc.c:957
+
RCC_APB1PeriphClockCmd
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
Definition: stm32f4xx_rcc.c:1638
+
RCC_HSEConfig
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: stm32f4xx_rcc.c:263
+
RCC_AHB1PeriphResetCmd
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
Definition: stm32f4xx_rcc.c:1725
+
RCC_APB1PeriphResetCmd
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
Definition: stm32f4xx_rcc.c:1828
+
RCC_ClocksTypeDef::PCLK2_Frequency
uint32_t PCLK2_Frequency
Definition: stm32f4xx_rcc.h:53
+
RCC_GetClocksFreq
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Definition: stm32f4xx_rcc.c:1097
+
RCC_SAIBlockBCLKConfig
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
Configures SAI1BlockB clock source selection.
Definition: stm32f4xx_rcc.c:1413
+
RCC_APB2PeriphResetCmd
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
Definition: stm32f4xx_rcc.c:1869
+
RCC_SYSCLKConfig
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Definition: stm32f4xx_rcc.c:929
+
RCC_LSEConfig
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: stm32f4xx_rcc.c:379
+
RCC_SAIPLLSAIClkDivConfig
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
Configures the SAI clock Divider coming from PLLSAI.
Definition: stm32f4xx_rcc.c:1341
+
RCC_ClocksTypeDef
Definition: stm32f4xx_rcc.h:48
+
RCC_BackupResetCmd
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
Definition: stm32f4xx_rcc.c:1271
+
RCC_PLLCmd
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: stm32f4xx_rcc.c:485
+
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+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rng_8c.html b/stm32f4xx__rng_8c.html new file mode 100644 index 0000000..717f5c6 --- /dev/null +++ b/stm32f4xx__rng_8c.html @@ -0,0 +1,182 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_rng.c File Reference + + + + + + + + + + +
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+Functions
+
+
stm32f4xx_rng.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral: +More...

+
#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_rng.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RNG_DeInit (void)
 De-initializes the RNG peripheral registers to their default reset values. More...
 
void RNG_Cmd (FunctionalState NewState)
 Enables or disables the RNG peripheral. More...
 
uint32_t RNG_GetRandomNumber (void)
 Returns a 32-bit random number. More...
 
void RNG_ITConfig (FunctionalState NewState)
 Enables or disables the RNG interrupt. More...
 
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
 Checks whether the specified RNG flag is set or not. More...
 
void RNG_ClearFlag (uint8_t RNG_FLAG)
 Clears the RNG flags. More...
 
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
 Checks whether the specified RNG interrupt has occurred or not. More...
 
void RNG_ClearITPendingBit (uint8_t RNG_IT)
 Clears the RNG interrupt pending bit(s). More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Random Number Generator (RNG) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Get 32 bit Random number
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================      
+                 ##### How to use this driver #####
+ ===================================================================          
+ [..]
+   (#) Enable The RNG controller clock using 
+       RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
+                
+   (#) Activate the RNG peripheral using RNG_Cmd() function.
+            
+   (#) Wait until the 32 bit Random number Generator contains a valid  random data
+      (using polling/interrupt mode). For more details, refer to "Interrupts and 
+      flags management functions" module description.
+             
+   (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
+            
+   (#) To get another 32 bit Random number, go to step 3.       
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rng_8c__incl.map b/stm32f4xx__rng_8c__incl.map new file mode 100644 index 0000000..a083f9f --- /dev/null +++ b/stm32f4xx__rng_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rng_8c__incl.md5 b/stm32f4xx__rng_8c__incl.md5 new file mode 100644 index 0000000..216746b --- /dev/null +++ b/stm32f4xx__rng_8c__incl.md5 @@ -0,0 +1 @@ +983ca10b79ed2d37b3853bf5e0db6c1f \ No newline at end of file diff --git a/stm32f4xx__rng_8c__incl.png b/stm32f4xx__rng_8c__incl.png new file mode 100644 index 0000000..156d482 Binary files /dev/null and b/stm32f4xx__rng_8c__incl.png differ diff --git a/stm32f4xx__rng_8h.html b/stm32f4xx__rng_8h.html new file mode 100644 index 0000000..1478f38 --- /dev/null +++ b/stm32f4xx__rng_8h.html @@ -0,0 +1,184 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_rng.h File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_rng.h File Reference
+
+
+ +

This file contains all the functions prototypes for the Random Number Generator(RNG) firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_rng.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define RNG_FLAG_DRDY   ((uint8_t)0x0001)
 
#define RNG_FLAG_CECS   ((uint8_t)0x0002)
 
#define RNG_FLAG_SECS   ((uint8_t)0x0004)
 
#define IS_RNG_GET_FLAG(RNG_FLAG)
 
#define IS_RNG_CLEAR_FLAG(RNG_FLAG)
 
#define RNG_IT_CEI   ((uint8_t)0x20)
 
#define RNG_IT_SEI   ((uint8_t)0x40)
 
+#define IS_RNG_IT(IT)   ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
 
+#define IS_RNG_GET_IT(RNG_IT)   (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void RNG_DeInit (void)
 De-initializes the RNG peripheral registers to their default reset values. More...
 
void RNG_Cmd (FunctionalState NewState)
 Enables or disables the RNG peripheral. More...
 
uint32_t RNG_GetRandomNumber (void)
 Returns a 32-bit random number. More...
 
void RNG_ITConfig (FunctionalState NewState)
 Enables or disables the RNG interrupt. More...
 
FlagStatus RNG_GetFlagStatus (uint8_t RNG_FLAG)
 Checks whether the specified RNG flag is set or not. More...
 
void RNG_ClearFlag (uint8_t RNG_FLAG)
 Clears the RNG flags. More...
 
ITStatus RNG_GetITStatus (uint8_t RNG_IT)
 Checks whether the specified RNG interrupt has occurred or not. More...
 
void RNG_ClearITPendingBit (uint8_t RNG_IT)
 Clears the RNG interrupt pending bit(s). More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the Random Number Generator(RNG) firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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stm32f4xx_rng.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_RNG_H
+
31 #define __STM32F4xx_RNG_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
58 #define RNG_FLAG_DRDY ((uint8_t)0x0001)
+
59 #define RNG_FLAG_CECS ((uint8_t)0x0002)
+
60 #define RNG_FLAG_SECS ((uint8_t)0x0004)
+
62 #define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
+
63  ((RNG_FLAG) == RNG_FLAG_CECS) || \
+
64  ((RNG_FLAG) == RNG_FLAG_SECS))
+
65 #define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
+
66  ((RNG_FLAG) == RNG_FLAG_SECS))
+
67 
+
74 #define RNG_IT_CEI ((uint8_t)0x20)
+
75 #define RNG_IT_SEI ((uint8_t)0x40)
+
77 #define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
+
78 #define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
+
79 
+
87 /* Exported macro ------------------------------------------------------------*/
+
88 /* Exported functions --------------------------------------------------------*/
+
89 
+
90 /* Function used to set the RNG configuration to the default reset state *****/
+
91 void RNG_DeInit(void);
+
92 
+
93 /* Configuration function *****************************************************/
+
94 void RNG_Cmd(FunctionalState NewState);
+
95 
+
96 /* Get 32 bit Random number function ******************************************/
+
97 uint32_t RNG_GetRandomNumber(void);
+
98 
+
99 /* Interrupts and flags management functions **********************************/
+
100 void RNG_ITConfig(FunctionalState NewState);
+
101 FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
+
102 void RNG_ClearFlag(uint8_t RNG_FLAG);
+
103 ITStatus RNG_GetITStatus(uint8_t RNG_IT);
+
104 void RNG_ClearITPendingBit(uint8_t RNG_IT);
+
105 
+
106 #ifdef __cplusplus
+
107 }
+
108 #endif
+
109 
+
110 #endif /*__STM32F4xx_RNG_H */
+
111 
+
120 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
RNG_DeInit
void RNG_DeInit(void)
De-initializes the RNG peripheral registers to their default reset values.
Definition: stm32f4xx_rng.c:99
+
RNG_GetRandomNumber
uint32_t RNG_GetRandomNumber(void)
Returns a 32-bit random number.
Definition: stm32f4xx_rng.c:176
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
RNG_ClearFlag
void RNG_ClearFlag(uint8_t RNG_FLAG)
Clears the RNG flags.
Definition: stm32f4xx_rng.c:326
+
RNG_Cmd
void RNG_Cmd(FunctionalState NewState)
Enables or disables the RNG peripheral.
Definition: stm32f4xx_rng.c:114
+
RNG_ClearITPendingBit
void RNG_ClearITPendingBit(uint8_t RNG_IT)
Clears the RNG interrupt pending bit(s).
Definition: stm32f4xx_rng.c:372
+
RNG_ITConfig
void RNG_ITConfig(FunctionalState NewState)
Enables or disables the RNG interrupt.
Definition: stm32f4xx_rng.c:267
+
RNG_GetFlagStatus
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
Checks whether the specified RNG flag is set or not.
Definition: stm32f4xx_rng.c:293
+
RNG_GetITStatus
ITStatus RNG_GetITStatus(uint8_t RNG_IT)
Checks whether the specified RNG interrupt has occurred or not.
Definition: stm32f4xx_rng.c:342
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rtc_8c.html b/stm32f4xx__rtc_8c.html new file mode 100644 index 0000000..5952085 --- /dev/null +++ b/stm32f4xx__rtc_8c.html @@ -0,0 +1,581 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_rtc.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions
+
+
stm32f4xx_rtc.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral: +More...

+
#include "stm32f4xx_rtc.h"
+
+Include dependency graph for stm32f4xx_rtc.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_TR_RESERVED_MASK   ((uint32_t)0x007F7F7F)
 
+#define RTC_DR_RESERVED_MASK   ((uint32_t)0x00FFFF3F)
 
+#define RTC_INIT_MASK   ((uint32_t)0xFFFFFFFF)
 
+#define RTC_RSF_MASK   ((uint32_t)0xFFFFFF5F)
 
#define RTC_FLAGS_MASK
 
+#define INITMODE_TIMEOUT   ((uint32_t) 0x00010000)
 
+#define SYNCHRO_TIMEOUT   ((uint32_t) 0x00020000)
 
+#define RECALPF_TIMEOUT   ((uint32_t) 0x00020000)
 
+#define SHPF_TIMEOUT   ((uint32_t) 0x00001000)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_DeInit (void)
 Deinitializes the RTC registers to their default reset values. More...
 
ErrorStatus RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
 Initializes the RTC registers according to the specified parameters in RTC_InitStruct. More...
 
void RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
 Fills each RTC_InitStruct member with its default value. More...
 
void RTC_WriteProtectionCmd (FunctionalState NewState)
 Enables or disables the RTC registers write protection. More...
 
ErrorStatus RTC_EnterInitMode (void)
 Enters the RTC Initialization mode. More...
 
void RTC_ExitInitMode (void)
 Exits the RTC Initialization mode. More...
 
ErrorStatus RTC_WaitForSynchro (void)
 Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock. More...
 
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
 Enables or disables the RTC reference clock detection. More...
 
void RTC_BypassShadowCmd (FunctionalState NewState)
 Enables or Disables the Bypass Shadow feature. More...
 
ErrorStatus RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Set the RTC current time. More...
 
void RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
 Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec). More...
 
void RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Get the RTC current Time. More...
 
uint32_t RTC_GetSubSecond (void)
 Gets the RTC current Calendar Sub seconds value. More...
 
ErrorStatus RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Set the RTC current date. More...
 
void RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
 Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00). More...
 
void RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Get the RTC current date. More...
 
void RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Set the specified RTC Alarm. More...
 
void RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
 Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked). More...
 
void RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Get the RTC Alarm value and masks. More...
 
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
 Enables or disables the specified RTC Alarm. More...
 
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
 Configure the RTC AlarmA/B Sub seconds value and mask.*. More...
 
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
 Gets the RTC Alarm Sub seconds value. More...
 
void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
 Configures the RTC Wakeup clock source. More...
 
void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
 Configures the RTC Wakeup counter. More...
 
uint32_t RTC_GetWakeUpCounter (void)
 Returns the RTC WakeUp timer counter value. More...
 
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
 Enables or Disables the RTC WakeUp timer. More...
 
void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
 Adds or substract one hour from the current time. More...
 
uint32_t RTC_GetStoreOperation (void)
 Returns the RTC Day Light Saving stored operation. More...
 
void RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
 Configures the RTC output source (AFO_ALARM). More...
 
ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
 Configures the Coarse calibration parameters. More...
 
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
 Enables or disables the Coarse calibration process. More...
 
void RTC_CalibOutputCmd (FunctionalState NewState)
 Enables or disables the RTC clock to be output through the relative pin. More...
 
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
 Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). More...
 
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
 Configures the Smooth Calibration Settings. More...
 
void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
 Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge. More...
 
void RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
 Get the RTC TimeStamp value and masks. More...
 
uint32_t RTC_GetTimeStampSubSecond (void)
 Get the RTC timestamp Sub seconds value. More...
 
void RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
 Configures the select Tamper pin edge. More...
 
void RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
 Enables or Disables the Tamper detection. More...
 
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
 Configures the Tampers Filter. More...
 
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
 Configures the Tampers Sampling Frequency. More...
 
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
 Configures the Tampers Pins input Precharge Duration. More...
 
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
 Enables or Disables the TimeStamp on Tamper Detection Event. More...
 
void RTC_TamperPullUpCmd (FunctionalState NewState)
 Enables or Disables the Precharge of Tamper pin. More...
 
void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
 Writes a data in a specified RTC Backup data register. More...
 
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
 Reads data from the specified RTC Backup data Register. More...
 
void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
 Selects the RTC Tamper Pin. More...
 
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
 Selects the RTC TimeStamp Pin. More...
 
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
 Configures the RTC Output Pin mode. More...
 
ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
 Configures the Synchronization Shift Control Settings. More...
 
void RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
 Enables or disables the specified RTC interrupts. More...
 
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
 Checks whether the specified RTC flag is set or not. More...
 
void RTC_ClearFlag (uint32_t RTC_FLAG)
 Clears the RTC's pending flags. More...
 
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
 Checks whether the specified RTC interrupt has occurred or not. More...
 
void RTC_ClearITPendingBit (uint32_t RTC_IT)
 Clears the RTC's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Real-Time Clock (RTC) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization
    • +
  • Calendar (Time and Date) configuration
    • +
  • Alarms (Alarm A and Alarm B) configuration
    • +
  • WakeUp Timer configuration
    • +
  • Daylight Saving configuration
    • +
  • Output pin Configuration
    • +
  • Coarse digital Calibration configuration
    • +
  • Smooth digital Calibration configuration
    • +
  • TimeStamp configuration
    • +
  • Tampers configuration
    • +
  • Backup Data Registers configuration
    • +
  • Shift control synchronisation
    • +
  • RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================
+              ##### Backup Domain Operating Condition #####
+ ===================================================================
+ [..] The real-time clock (RTC), the RTC backup registers, and the backup 
+      SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
+      VDD supply is powered off.
+      To retain the content of the RTC backup registers, backup SRAM, and supply 
+      the RTC when VDD is turned off, VBAT pin can be connected to an optional 
+      standby voltage supplied by a battery or by another source.
+
+ [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
+      off, the VBAT pin powers the following blocks:
+   (#) The RTC
+   (#) The LSE oscillator
+   (#) The backup SRAM when the low power backup regulator is enabled
+   (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
+  
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+      the following functions are available:
+   (#) PC14 and PC15 can be used as either GPIO or LSE pins
+   (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+   (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
+  
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT 
+      because VDD is not present), the following functions are available:
+   (#) PC14 and PC15 can be used as LSE pins only
+   (#) PC13 can be used as the RTC_AF1 pin 
+   (#) PI8 can be used as the RTC_AF2 pin
+  
+            
+                   ##### Backup Domain Reset #####
+ ===================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register 
+      to their reset values. The BKPSRAM is not affected by this reset. The only
+      way of resetting the BKPSRAM is through the Flash interface by requesting 
+      a protection level change from 1 to 0.
+ [..] A backup domain reset is generated when one of the following events occurs:
+   (#) Software reset, triggered by setting the BDRST bit in the 
+       RCC Backup domain control register (RCC_BDCR). You can use the
+       RCC_BackupResetCmd().
+   (#) VDD or VBAT power on, if both supplies have previously been powered off.
+  
+
+                   ##### Backup Domain Access #####
+ ===================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted write 
+      accesses. 
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+   (+) Enable the Power Controller (PWR) APB1 interface clock using the
+       RCC_APB1PeriphClockCmd() function.
+   (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
+   (+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
+   (+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
+  
+  
+                  ##### How to use RTC Driver #####
+ ===================================================================
+ [..] 
+   (+) Enable the RTC domain access (see description in the section above)
+   (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
+       format using the RTC_Init() function.
+  
+ *** Time and Date configuration ***
+ ===================================
+ [..] 
+   (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+       and RTC_SetDate() functions.
+   (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions.
+   (+) Use the RTC_DayLightSavingConfig() function to add or sub one
+       hour to the RTC Calendar.    
+  
+ *** Alarm configuration ***
+ ===========================
+ [..]
+   (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
+   (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
+   (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
+   (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+  
+ *** RTC Wakeup configuration ***
+ ================================
+ [..] 
+   (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+       function.
+   (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function  
+   (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+   (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+       function.
+  
+ *** Outputs configuration ***
+ =============================
+ [..] The RTC has 2 different outputs:
+   (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+       and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the 
+       RTC_OutputConfig() function.                
+   (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on 
+       RTC_AF1 pin, use the RTC_CalibOutputCmd() function.
+  
+ *** Smooth digital Calibration configuration ***
+ ================================================    
+ [..]
+   (+) Configure the RTC Original Digital Calibration Value and the corresponding
+       calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() 
+       function.
+  
+ *** Coarse digital Calibration configuration ***
+ ================================================
+ [..]
+   (+) Configure the RTC Coarse Calibration Value and the corresponding
+       sign using the RTC_CoarseCalibConfig() function.
+   (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function  
+  
+ *** TimeStamp configuration ***
+ ===============================
+ [..]
+   (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC
+      _TimeStampCmd() function.
+   (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp()
+       function.
+   (+) To read the RTC TimeStamp SubSecond register, use the 
+       RTC_GetTimeStampSubSecond() function.
+   (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
+       or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in 
+       RTC_TAFCR register. You can use the  RTC_TamperPinSelection() function to
+       select the corresponding pin.     
+  
+ *** Tamper configuration ***
+ ============================
+ [..]
+   (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
+   (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
+       function. 
+   (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+       filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() 
+       function.
+   (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+       function.
+   (+) Configure the Tamper precharge or discharge duration using 
+       RTC_TamperPinsPrechargeDuration() function.
+   (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+   (+) Enable the Time stamp on Tamper detection event using  
+       TC_TSOnTamperDetecCmd() function.
+   (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 
+       or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR 
+       register. You can use the  RTC_TimeStampPinSelection() function to select 
+       the corresponding pin. 
+  
+ *** Backup Data Registers configuration ***
+ ===========================================
+ [..]
+   (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+       function.  
+   (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+       function.
+   
+
+                  ##### RTC and low power modes #####
+ ===================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate 
+      function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+      RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+      These RTC alternate functions can wake up the system from the Stop and 
+      Standby lowpower modes.
+ [..] The system can also wake up from low power modes without depending 
+      on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+      or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the 
+      Stop or Standby mode at regular intervals.
+      Wakeup from STOP and Standby modes is possible only when the RTC clock source
+      is LSE or LSI.
+  
+
+          ##### Selection of RTC_AF1 alternate functions #####
+ ===================================================================
+ [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
+   (+) AFO_ALARM output
+   (+) AFO_CALIB output
+   (+) AFI_TAMPER
+   (+) AFI_TIMESTAMP
+ 
+ [..]   
+   +-------------------------------------------------------------------------------------------------------------+
+   |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
+   |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
+   |  and function   |          |          |           |              | selection  |  selection   |Configuration |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
+   |   output OD     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      0       |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
+   |   output PP     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      1       |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   | Calibration out |          |          |           |              |    Don't   |     Don't    |              |
+   |   output PP     |     0    |    1     |Don't care | Don't care   |    care    |     care     |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   |  TAMPER input   |          |          |           |              |            |     Don't    |              |
+   |   floating      |     0    |    0     |     1     |      0       |      0     |     care     |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   |  TIMESTAMP and  |          |          |           |              |            |              |              |
+   |  TAMPER input   |     0    |    0     |     1     |      1       |      0     |      0       |  Don't care  |
+   |   floating      |          |          |           |              |            |              |              |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   | TIMESTAMP input |          |          |           |              |    Don't   |              |              |
+   |    floating     |     0    |    0     |     0     |      1       |    care    |      0       |  Don't care  |
+   |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+   |  Standard GPIO  |     0    |    0     |     0     |      0       | Don't care |  Don't care  |  Don't care  |
+   +-------------------------------------------------------------------------------------------------------------+
+
+            
+        #####  Selection of RTC_AF2 alternate functions #####
+ ===================================================================
+ [..] The RTC_AF2 pin (PI8) can be used for the following purposes:
+   (+) AFI_TAMPER
+   (+) AFI_TIMESTAMP
+ [..]
+   +---------------------------------------------------------------------------------------+
+   |     Pin         |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
+   |  configuration  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
+   |  and function   |           |              | selection  |  selection   |Configuration |
+   |-----------------|-----------|--------------|------------|--------------|--------------|
+   |  TAMPER input   |           |              |            |     Don't    |              |
+   |   floating      |     1     |      0       |      1     |     care     |  Don't care  |
+   |-----------------|-----------|--------------|------------|--------------|--------------|
+   |  TIMESTAMP and  |           |              |            |              |              |
+   |  TAMPER input   |     1     |      1       |      1     |      1       |  Don't care  |
+   |   floating      |           |              |            |              |              |
+   |-----------------|-----------|--------------|------------|--------------|--------------|
+   | TIMESTAMP input |           |              |    Don't   |              |              |
+   |    floating     |     0     |      1       |    care    |      1       |  Don't care  |
+   |-----------------|-----------|--------------|------------|--------------|--------------|
+   |  Standard GPIO  |     0     |      0       | Don't care |  Don't care  |  Don't care  |
+   +---------------------------------------------------------------------------------------+   
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rtc_8c__incl.map b/stm32f4xx__rtc_8c__incl.map new file mode 100644 index 0000000..3765640 --- /dev/null +++ b/stm32f4xx__rtc_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rtc_8c__incl.md5 b/stm32f4xx__rtc_8c__incl.md5 new file mode 100644 index 0000000..4c3a229 --- /dev/null +++ b/stm32f4xx__rtc_8c__incl.md5 @@ -0,0 +1 @@ +626d1ae23b4ccd3994beed6a7d35c303 \ No newline at end of file diff --git a/stm32f4xx__rtc_8c__incl.png b/stm32f4xx__rtc_8c__incl.png new file mode 100644 index 0000000..49d1170 Binary files /dev/null and b/stm32f4xx__rtc_8c__incl.png differ diff --git a/stm32f4xx__rtc_8h.html b/stm32f4xx__rtc_8h.html new file mode 100644 index 0000000..18d9acc --- /dev/null +++ b/stm32f4xx__rtc_8h.html @@ -0,0 +1,855 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_rtc.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
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+Classes | +Macros | +Functions
+
+
stm32f4xx_rtc.h File Reference
+
+
+ +

This file contains all the functions prototypes for the RTC firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_rtc.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
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+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Classes

struct  RTC_InitTypeDef
 RTC Init structures definition. More...
 
struct  RTC_TimeTypeDef
 RTC Time structure definition. More...
 
struct  RTC_DateTypeDef
 RTC Date structure definition. More...
 
struct  RTC_AlarmTypeDef
 RTC Alarm structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define RTC_HourFormat_24   ((uint32_t)0x00000000)
 
+#define RTC_HourFormat_12   ((uint32_t)0x00000040)
 
#define IS_RTC_HOUR_FORMAT(FORMAT)
 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FFF)
 
+#define IS_RTC_HOUR12(HOUR)   (((HOUR) > 0) && ((HOUR) <= 12))
 
+#define IS_RTC_HOUR24(HOUR)   ((HOUR) <= 23)
 
+#define IS_RTC_MINUTES(MINUTES)   ((MINUTES) <= 59)
 
+#define IS_RTC_SECONDS(SECONDS)   ((SECONDS) <= 59)
 
+#define RTC_H12_AM   ((uint8_t)0x00)
 
+#define RTC_H12_PM   ((uint8_t)0x40)
 
+#define IS_RTC_H12(PM)   (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
 
+#define IS_RTC_YEAR(YEAR)   ((YEAR) <= 99)
 
+#define RTC_Month_January   ((uint8_t)0x01)
 
+#define RTC_Month_February   ((uint8_t)0x02)
 
+#define RTC_Month_March   ((uint8_t)0x03)
 
+#define RTC_Month_April   ((uint8_t)0x04)
 
+#define RTC_Month_May   ((uint8_t)0x05)
 
+#define RTC_Month_June   ((uint8_t)0x06)
 
+#define RTC_Month_July   ((uint8_t)0x07)
 
+#define RTC_Month_August   ((uint8_t)0x08)
 
+#define RTC_Month_September   ((uint8_t)0x09)
 
+#define RTC_Month_October   ((uint8_t)0x10)
 
+#define RTC_Month_November   ((uint8_t)0x11)
 
+#define RTC_Month_December   ((uint8_t)0x12)
 
+#define IS_RTC_MONTH(MONTH)   (((MONTH) >= 1) && ((MONTH) <= 12))
 
+#define IS_RTC_DATE(DATE)   (((DATE) >= 1) && ((DATE) <= 31))
 
+#define RTC_Weekday_Monday   ((uint8_t)0x01)
 
+#define RTC_Weekday_Tuesday   ((uint8_t)0x02)
 
+#define RTC_Weekday_Wednesday   ((uint8_t)0x03)
 
+#define RTC_Weekday_Thursday   ((uint8_t)0x04)
 
+#define RTC_Weekday_Friday   ((uint8_t)0x05)
 
+#define RTC_Weekday_Saturday   ((uint8_t)0x06)
 
+#define RTC_Weekday_Sunday   ((uint8_t)0x07)
 
#define IS_RTC_WEEKDAY(WEEKDAY)
 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE)   (((DATE) > 0) && ((DATE) <= 31))
 
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY)
 
+#define RTC_AlarmDateWeekDaySel_Date   ((uint32_t)0x00000000)
 
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
 
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL)
 
+#define RTC_AlarmMask_None   ((uint32_t)0x00000000)
 
+#define RTC_AlarmMask_DateWeekDay   ((uint32_t)0x80000000)
 
+#define RTC_AlarmMask_Hours   ((uint32_t)0x00800000)
 
+#define RTC_AlarmMask_Minutes   ((uint32_t)0x00008000)
 
+#define RTC_AlarmMask_Seconds   ((uint32_t)0x00000080)
 
+#define RTC_AlarmMask_All   ((uint32_t)0x80808080)
 
+#define IS_ALARM_MASK(MASK)   (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
 
+#define RTC_Alarm_A   ((uint32_t)0x00000100)
 
+#define RTC_Alarm_B   ((uint32_t)0x00000200)
 
+#define IS_RTC_ALARM(ALARM)   (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
 
+#define IS_RTC_CMD_ALARM(ALARM)   (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
 
#define RTC_AlarmSubSecondMask_All   ((uint32_t)0x00000000)
 
#define RTC_AlarmSubSecondMask_SS14_1   ((uint32_t)0x01000000)
 
#define RTC_AlarmSubSecondMask_SS14_2   ((uint32_t)0x02000000)
 
#define RTC_AlarmSubSecondMask_SS14_3   ((uint32_t)0x03000000)
 
#define RTC_AlarmSubSecondMask_SS14_4   ((uint32_t)0x04000000)
 
#define RTC_AlarmSubSecondMask_SS14_5   ((uint32_t)0x05000000)
 
#define RTC_AlarmSubSecondMask_SS14_6   ((uint32_t)0x06000000)
 
#define RTC_AlarmSubSecondMask_SS14_7   ((uint32_t)0x07000000)
 
#define RTC_AlarmSubSecondMask_SS14_8   ((uint32_t)0x08000000)
 
#define RTC_AlarmSubSecondMask_SS14_9   ((uint32_t)0x09000000)
 
#define RTC_AlarmSubSecondMask_SS14_10   ((uint32_t)0x0A000000)
 
#define RTC_AlarmSubSecondMask_SS14_11   ((uint32_t)0x0B000000)
 
#define RTC_AlarmSubSecondMask_SS14_12   ((uint32_t)0x0C000000)
 
#define RTC_AlarmSubSecondMask_SS14_13   ((uint32_t)0x0D000000)
 
#define RTC_AlarmSubSecondMask_SS14   ((uint32_t)0x0E000000)
 
#define RTC_AlarmSubSecondMask_None   ((uint32_t)0x0F000000)
 
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)
 
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE)   ((VALUE) <= 0x00007FFF)
 
+#define RTC_WakeUpClock_RTCCLK_Div16   ((uint32_t)0x00000000)
 
+#define RTC_WakeUpClock_RTCCLK_Div8   ((uint32_t)0x00000001)
 
+#define RTC_WakeUpClock_RTCCLK_Div4   ((uint32_t)0x00000002)
 
+#define RTC_WakeUpClock_RTCCLK_Div2   ((uint32_t)0x00000003)
 
+#define RTC_WakeUpClock_CK_SPRE_16bits   ((uint32_t)0x00000004)
 
+#define RTC_WakeUpClock_CK_SPRE_17bits   ((uint32_t)0x00000006)
 
#define IS_RTC_WAKEUP_CLOCK(CLOCK)
 
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)   ((COUNTER) <= 0xFFFF)
 
+#define RTC_TimeStampEdge_Rising   ((uint32_t)0x00000000)
 
+#define RTC_TimeStampEdge_Falling   ((uint32_t)0x00000008)
 
#define IS_RTC_TIMESTAMP_EDGE(EDGE)
 
+#define RTC_Output_Disable   ((uint32_t)0x00000000)
 
+#define RTC_Output_AlarmA   ((uint32_t)0x00200000)
 
+#define RTC_Output_AlarmB   ((uint32_t)0x00400000)
 
+#define RTC_Output_WakeUp   ((uint32_t)0x00600000)
 
#define IS_RTC_OUTPUT(OUTPUT)
 
+#define RTC_OutputPolarity_High   ((uint32_t)0x00000000)
 
+#define RTC_OutputPolarity_Low   ((uint32_t)0x00100000)
 
#define IS_RTC_OUTPUT_POL(POL)
 
+#define RTC_CalibSign_Positive   ((uint32_t)0x00000000)
 
+#define RTC_CalibSign_Negative   ((uint32_t)0x00000080)
 
#define IS_RTC_CALIB_SIGN(SIGN)
 
+#define IS_RTC_CALIB_VALUE(VALUE)   ((VALUE) < 0x20)
 
+#define RTC_CalibOutput_512Hz   ((uint32_t)0x00000000)
 
+#define RTC_CalibOutput_1Hz   ((uint32_t)0x00080000)
 
#define IS_RTC_CALIB_OUTPUT(OUTPUT)
 
#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000)
 
#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000)
 
#define RTC_SmoothCalibPeriod_8sec   ((uint32_t)0x00004000)
 
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD)
 
#define RTC_SmoothCalibPlusPulses_Set   ((uint32_t)0x00008000)
 
#define RTC_SmoothCalibPlusPulses_Reset   ((uint32_t)0x00000000)
 
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS)
 
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE)   ((VALUE) <= 0x000001FF)
 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
 
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
 
#define IS_RTC_DAYLIGHT_SAVING(SAVE)
 
+#define RTC_StoreOperation_Reset   ((uint32_t)0x00000000)
 
+#define RTC_StoreOperation_Set   ((uint32_t)0x00040000)
 
#define IS_RTC_STORE_OPERATION(OPERATION)
 
+#define RTC_TamperTrigger_RisingEdge   ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_FallingEdge   ((uint32_t)0x00000001)
 
+#define RTC_TamperTrigger_LowLevel   ((uint32_t)0x00000000)
 
+#define RTC_TamperTrigger_HighLevel   ((uint32_t)0x00000001)
 
#define IS_RTC_TAMPER_TRIGGER(TRIGGER)
 
#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000)
 
#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800)
 
#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000)
 
#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800)
 
#define IS_RTC_TAMPER_FILTER(FILTER)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div32768   ((uint32_t)0x00000000)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div16384   ((uint32_t)0x000000100)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600)
 
#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700)
 
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ)
 
#define RTC_TamperPrechargeDuration_1RTCCLK   ((uint32_t)0x00000000)
 
#define RTC_TamperPrechargeDuration_2RTCCLK   ((uint32_t)0x00002000)
 
#define RTC_TamperPrechargeDuration_4RTCCLK   ((uint32_t)0x00004000)
 
#define RTC_TamperPrechargeDuration_8RTCCLK   ((uint32_t)0x00006000)
 
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION)
 
+#define RTC_Tamper_1   RTC_TAFCR_TAMP1E
 
+#define IS_RTC_TAMPER(TAMPER)   (((TAMPER) == RTC_Tamper_1))
 
+#define RTC_TamperPin_PC13   ((uint32_t)0x00000000)
 
+#define RTC_TamperPin_PI8   ((uint32_t)0x00010000)
 
#define IS_RTC_TAMPER_PIN(PIN)
 
+#define RTC_TimeStampPin_PC13   ((uint32_t)0x00000000)
 
+#define RTC_TimeStampPin_PI8   ((uint32_t)0x00020000)
 
#define IS_RTC_TIMESTAMP_PIN(PIN)
 
+#define RTC_OutputType_OpenDrain   ((uint32_t)0x00000000)
 
+#define RTC_OutputType_PushPull   ((uint32_t)0x00040000)
 
#define IS_RTC_OUTPUT_TYPE(TYPE)
 
+#define RTC_ShiftAdd1S_Reset   ((uint32_t)0x00000000)
 
+#define RTC_ShiftAdd1S_Set   ((uint32_t)0x80000000)
 
#define IS_RTC_SHIFT_ADD1S(SEL)
 
+#define IS_RTC_SHIFT_SUBFS(FS)   ((FS) <= 0x00007FFF)
 
+#define RTC_BKP_DR0   ((uint32_t)0x00000000)
 
+#define RTC_BKP_DR1   ((uint32_t)0x00000001)
 
+#define RTC_BKP_DR2   ((uint32_t)0x00000002)
 
+#define RTC_BKP_DR3   ((uint32_t)0x00000003)
 
+#define RTC_BKP_DR4   ((uint32_t)0x00000004)
 
+#define RTC_BKP_DR5   ((uint32_t)0x00000005)
 
+#define RTC_BKP_DR6   ((uint32_t)0x00000006)
 
+#define RTC_BKP_DR7   ((uint32_t)0x00000007)
 
+#define RTC_BKP_DR8   ((uint32_t)0x00000008)
 
+#define RTC_BKP_DR9   ((uint32_t)0x00000009)
 
+#define RTC_BKP_DR10   ((uint32_t)0x0000000A)
 
+#define RTC_BKP_DR11   ((uint32_t)0x0000000B)
 
+#define RTC_BKP_DR12   ((uint32_t)0x0000000C)
 
+#define RTC_BKP_DR13   ((uint32_t)0x0000000D)
 
+#define RTC_BKP_DR14   ((uint32_t)0x0000000E)
 
+#define RTC_BKP_DR15   ((uint32_t)0x0000000F)
 
+#define RTC_BKP_DR16   ((uint32_t)0x00000010)
 
+#define RTC_BKP_DR17   ((uint32_t)0x00000011)
 
+#define RTC_BKP_DR18   ((uint32_t)0x00000012)
 
+#define RTC_BKP_DR19   ((uint32_t)0x00000013)
 
#define IS_RTC_BKP(BKP)
 
+#define RTC_Format_BIN   ((uint32_t)0x000000000)
 
+#define RTC_Format_BCD   ((uint32_t)0x000000001)
 
+#define IS_RTC_FORMAT(FORMAT)   (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
 
+#define RTC_FLAG_RECALPF   ((uint32_t)0x00010000)
 
+#define RTC_FLAG_TAMP1F   ((uint32_t)0x00002000)
 
+#define RTC_FLAG_TSOVF   ((uint32_t)0x00001000)
 
+#define RTC_FLAG_TSF   ((uint32_t)0x00000800)
 
+#define RTC_FLAG_WUTF   ((uint32_t)0x00000400)
 
+#define RTC_FLAG_ALRBF   ((uint32_t)0x00000200)
 
+#define RTC_FLAG_ALRAF   ((uint32_t)0x00000100)
 
+#define RTC_FLAG_INITF   ((uint32_t)0x00000040)
 
+#define RTC_FLAG_RSF   ((uint32_t)0x00000020)
 
+#define RTC_FLAG_INITS   ((uint32_t)0x00000010)
 
+#define RTC_FLAG_SHPF   ((uint32_t)0x00000008)
 
+#define RTC_FLAG_WUTWF   ((uint32_t)0x00000004)
 
+#define RTC_FLAG_ALRBWF   ((uint32_t)0x00000002)
 
+#define RTC_FLAG_ALRAWF   ((uint32_t)0x00000001)
 
#define IS_RTC_GET_FLAG(FLAG)
 
+#define IS_RTC_CLEAR_FLAG(FLAG)   (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
 
+#define RTC_IT_TS   ((uint32_t)0x00008000)
 
+#define RTC_IT_WUT   ((uint32_t)0x00004000)
 
+#define RTC_IT_ALRB   ((uint32_t)0x00002000)
 
+#define RTC_IT_ALRA   ((uint32_t)0x00001000)
 
+#define RTC_IT_TAMP   ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
 
+#define RTC_IT_TAMP1   ((uint32_t)0x00020000)
 
+#define IS_RTC_CONFIG_IT(IT)   (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
 
#define IS_RTC_GET_IT(IT)
 
+#define IS_RTC_CLEAR_IT(IT)   (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
 
+#define RTC_DigitalCalibConfig   RTC_CoarseCalibConfig
 
+#define RTC_DigitalCalibCmd   RTC_CoarseCalibCmd
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

ErrorStatus RTC_DeInit (void)
 Deinitializes the RTC registers to their default reset values. More...
 
ErrorStatus RTC_Init (RTC_InitTypeDef *RTC_InitStruct)
 Initializes the RTC registers according to the specified parameters in RTC_InitStruct. More...
 
void RTC_StructInit (RTC_InitTypeDef *RTC_InitStruct)
 Fills each RTC_InitStruct member with its default value. More...
 
void RTC_WriteProtectionCmd (FunctionalState NewState)
 Enables or disables the RTC registers write protection. More...
 
ErrorStatus RTC_EnterInitMode (void)
 Enters the RTC Initialization mode. More...
 
void RTC_ExitInitMode (void)
 Exits the RTC Initialization mode. More...
 
ErrorStatus RTC_WaitForSynchro (void)
 Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock. More...
 
ErrorStatus RTC_RefClockCmd (FunctionalState NewState)
 Enables or disables the RTC reference clock detection. More...
 
void RTC_BypassShadowCmd (FunctionalState NewState)
 Enables or Disables the Bypass Shadow feature. More...
 
ErrorStatus RTC_SetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Set the RTC current time. More...
 
void RTC_TimeStructInit (RTC_TimeTypeDef *RTC_TimeStruct)
 Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec). More...
 
void RTC_GetTime (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
 Get the RTC current Time. More...
 
uint32_t RTC_GetSubSecond (void)
 Gets the RTC current Calendar Sub seconds value. More...
 
ErrorStatus RTC_SetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Set the RTC current date. More...
 
void RTC_DateStructInit (RTC_DateTypeDef *RTC_DateStruct)
 Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00). More...
 
void RTC_GetDate (uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
 Get the RTC current date. More...
 
void RTC_SetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Set the specified RTC Alarm. More...
 
void RTC_AlarmStructInit (RTC_AlarmTypeDef *RTC_AlarmStruct)
 Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = all fields are masked). More...
 
void RTC_GetAlarm (uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
 Get the RTC Alarm value and masks. More...
 
ErrorStatus RTC_AlarmCmd (uint32_t RTC_Alarm, FunctionalState NewState)
 Enables or disables the specified RTC Alarm. More...
 
void RTC_AlarmSubSecondConfig (uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
 Configure the RTC AlarmA/B Sub seconds value and mask.*. More...
 
uint32_t RTC_GetAlarmSubSecond (uint32_t RTC_Alarm)
 Gets the RTC Alarm Sub seconds value. More...
 
void RTC_WakeUpClockConfig (uint32_t RTC_WakeUpClock)
 Configures the RTC Wakeup clock source. More...
 
void RTC_SetWakeUpCounter (uint32_t RTC_WakeUpCounter)
 Configures the RTC Wakeup counter. More...
 
uint32_t RTC_GetWakeUpCounter (void)
 Returns the RTC WakeUp timer counter value. More...
 
ErrorStatus RTC_WakeUpCmd (FunctionalState NewState)
 Enables or Disables the RTC WakeUp timer. More...
 
void RTC_DayLightSavingConfig (uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
 Adds or substract one hour from the current time. More...
 
uint32_t RTC_GetStoreOperation (void)
 Returns the RTC Day Light Saving stored operation. More...
 
void RTC_OutputConfig (uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
 Configures the RTC output source (AFO_ALARM). More...
 
ErrorStatus RTC_CoarseCalibConfig (uint32_t RTC_CalibSign, uint32_t Value)
 Configures the Coarse calibration parameters. More...
 
ErrorStatus RTC_CoarseCalibCmd (FunctionalState NewState)
 Enables or disables the Coarse calibration process. More...
 
void RTC_CalibOutputCmd (FunctionalState NewState)
 Enables or disables the RTC clock to be output through the relative pin. More...
 
void RTC_CalibOutputConfig (uint32_t RTC_CalibOutput)
 Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). More...
 
ErrorStatus RTC_SmoothCalibConfig (uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
 Configures the Smooth Calibration Settings. More...
 
void RTC_TimeStampCmd (uint32_t RTC_TimeStampEdge, FunctionalState NewState)
 Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edge. More...
 
void RTC_GetTimeStamp (uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
 Get the RTC TimeStamp value and masks. More...
 
uint32_t RTC_GetTimeStampSubSecond (void)
 Get the RTC timestamp Sub seconds value. More...
 
void RTC_TamperTriggerConfig (uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
 Configures the select Tamper pin edge. More...
 
void RTC_TamperCmd (uint32_t RTC_Tamper, FunctionalState NewState)
 Enables or Disables the Tamper detection. More...
 
void RTC_TamperFilterConfig (uint32_t RTC_TamperFilter)
 Configures the Tampers Filter. More...
 
void RTC_TamperSamplingFreqConfig (uint32_t RTC_TamperSamplingFreq)
 Configures the Tampers Sampling Frequency. More...
 
void RTC_TamperPinsPrechargeDuration (uint32_t RTC_TamperPrechargeDuration)
 Configures the Tampers Pins input Precharge Duration. More...
 
void RTC_TimeStampOnTamperDetectionCmd (FunctionalState NewState)
 Enables or Disables the TimeStamp on Tamper Detection Event. More...
 
void RTC_TamperPullUpCmd (FunctionalState NewState)
 Enables or Disables the Precharge of Tamper pin. More...
 
void RTC_WriteBackupRegister (uint32_t RTC_BKP_DR, uint32_t Data)
 Writes a data in a specified RTC Backup data register. More...
 
uint32_t RTC_ReadBackupRegister (uint32_t RTC_BKP_DR)
 Reads data from the specified RTC Backup data Register. More...
 
void RTC_TamperPinSelection (uint32_t RTC_TamperPin)
 Selects the RTC Tamper Pin. More...
 
void RTC_TimeStampPinSelection (uint32_t RTC_TimeStampPin)
 Selects the RTC TimeStamp Pin. More...
 
void RTC_OutputTypeConfig (uint32_t RTC_OutputType)
 Configures the RTC Output Pin mode. More...
 
ErrorStatus RTC_SynchroShiftConfig (uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
 Configures the Synchronization Shift Control Settings. More...
 
void RTC_ITConfig (uint32_t RTC_IT, FunctionalState NewState)
 Enables or disables the specified RTC interrupts. More...
 
FlagStatus RTC_GetFlagStatus (uint32_t RTC_FLAG)
 Checks whether the specified RTC flag is set or not. More...
 
void RTC_ClearFlag (uint32_t RTC_FLAG)
 Clears the RTC's pending flags. More...
 
ITStatus RTC_GetITStatus (uint32_t RTC_IT)
 Checks whether the specified RTC interrupt has occurred or not. More...
 
void RTC_ClearITPendingBit (uint32_t RTC_IT)
 Clears the RTC's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the RTC firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__rtc_8h__dep__incl.map b/stm32f4xx__rtc_8h__dep__incl.map new file mode 100644 index 0000000..c0b2206 --- /dev/null +++ b/stm32f4xx__rtc_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rtc_8h__dep__incl.md5 b/stm32f4xx__rtc_8h__dep__incl.md5 new file mode 100644 index 0000000..c6059a5 --- /dev/null +++ b/stm32f4xx__rtc_8h__dep__incl.md5 @@ -0,0 +1 @@ +5af75be80b0cf91e0d9adfa45bc9d704 \ No newline at end of file diff --git a/stm32f4xx__rtc_8h__dep__incl.png b/stm32f4xx__rtc_8h__dep__incl.png new file mode 100644 index 0000000..537fb54 Binary files /dev/null and b/stm32f4xx__rtc_8h__dep__incl.png differ diff --git a/stm32f4xx__rtc_8h__incl.map b/stm32f4xx__rtc_8h__incl.map new file mode 100644 index 0000000..33a85ec --- /dev/null +++ b/stm32f4xx__rtc_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__rtc_8h__incl.md5 b/stm32f4xx__rtc_8h__incl.md5 new file mode 100644 index 0000000..1fb5797 --- /dev/null +++ b/stm32f4xx__rtc_8h__incl.md5 @@ -0,0 +1 @@ +0560bf090122e1f990b409a9aac55607 \ No newline at end of file diff --git a/stm32f4xx__rtc_8h__incl.png b/stm32f4xx__rtc_8h__incl.png new file mode 100644 index 0000000..d78360d Binary files /dev/null and b/stm32f4xx__rtc_8h__incl.png differ diff --git a/stm32f4xx__rtc_8h_source.html b/stm32f4xx__rtc_8h_source.html new file mode 100644 index 0000000..174ecb3 --- /dev/null +++ b/stm32f4xx__rtc_8h_source.html @@ -0,0 +1,656 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_rtc.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx_rtc.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_RTC_H
+
31 #define __STM32F4xx_RTC_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
53 typedef struct
+
54 {
+
55  uint32_t RTC_HourFormat;
+
58  uint32_t RTC_AsynchPrediv;
+
61  uint32_t RTC_SynchPrediv;
+
63 }RTC_InitTypeDef;
+
64 
+
68 typedef struct
+
69 {
+
70  uint8_t RTC_Hours;
+
75  uint8_t RTC_Minutes;
+
78  uint8_t RTC_Seconds;
+
81  uint8_t RTC_H12;
+
83 }RTC_TimeTypeDef;
+
84 
+
88 typedef struct
+
89 {
+
90  uint8_t RTC_WeekDay;
+
93  uint8_t RTC_Month;
+
96  uint8_t RTC_Date;
+
99  uint8_t RTC_Year;
+
101 }RTC_DateTypeDef;
+
102 
+
106 typedef struct
+
107 {
+
108  RTC_TimeTypeDef RTC_AlarmTime;
+
110  uint32_t RTC_AlarmMask;
+
113  uint32_t RTC_AlarmDateWeekDaySel;
+
116  uint8_t RTC_AlarmDateWeekDay;
+
121 }RTC_AlarmTypeDef;
+
122 
+
123 /* Exported constants --------------------------------------------------------*/
+
124 
+
133 #define RTC_HourFormat_24 ((uint32_t)0x00000000)
+
134 #define RTC_HourFormat_12 ((uint32_t)0x00000040)
+
135 #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
+
136  ((FORMAT) == RTC_HourFormat_24))
+
137 
+
144 #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
+
145 
+
154 #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
+
155 
+
163 #define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
+
164 #define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
+
165 #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
+
166 #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
+
167 
+
175 #define RTC_H12_AM ((uint8_t)0x00)
+
176 #define RTC_H12_PM ((uint8_t)0x40)
+
177 #define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
178 
+
186 #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
+
187 
+
196 /* Coded in BCD format */
+
197 #define RTC_Month_January ((uint8_t)0x01)
+
198 #define RTC_Month_February ((uint8_t)0x02)
+
199 #define RTC_Month_March ((uint8_t)0x03)
+
200 #define RTC_Month_April ((uint8_t)0x04)
+
201 #define RTC_Month_May ((uint8_t)0x05)
+
202 #define RTC_Month_June ((uint8_t)0x06)
+
203 #define RTC_Month_July ((uint8_t)0x07)
+
204 #define RTC_Month_August ((uint8_t)0x08)
+
205 #define RTC_Month_September ((uint8_t)0x09)
+
206 #define RTC_Month_October ((uint8_t)0x10)
+
207 #define RTC_Month_November ((uint8_t)0x11)
+
208 #define RTC_Month_December ((uint8_t)0x12)
+
209 #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
+
210 #define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
+
211 
+
220 #define RTC_Weekday_Monday ((uint8_t)0x01)
+
221 #define RTC_Weekday_Tuesday ((uint8_t)0x02)
+
222 #define RTC_Weekday_Wednesday ((uint8_t)0x03)
+
223 #define RTC_Weekday_Thursday ((uint8_t)0x04)
+
224 #define RTC_Weekday_Friday ((uint8_t)0x05)
+
225 #define RTC_Weekday_Saturday ((uint8_t)0x06)
+
226 #define RTC_Weekday_Sunday ((uint8_t)0x07)
+
227 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+
228  ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+
229  ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+
230  ((WEEKDAY) == RTC_Weekday_Thursday) || \
+
231  ((WEEKDAY) == RTC_Weekday_Friday) || \
+
232  ((WEEKDAY) == RTC_Weekday_Saturday) || \
+
233  ((WEEKDAY) == RTC_Weekday_Sunday))
+
234 
+
242 #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+
243 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+
244  ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+
245  ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+
246  ((WEEKDAY) == RTC_Weekday_Thursday) || \
+
247  ((WEEKDAY) == RTC_Weekday_Friday) || \
+
248  ((WEEKDAY) == RTC_Weekday_Saturday) || \
+
249  ((WEEKDAY) == RTC_Weekday_Sunday))
+
250 
+
259 #define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
+
260 #define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
+
261 
+
262 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+
263  ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
264 
+
273 #define RTC_AlarmMask_None ((uint32_t)0x00000000)
+
274 #define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
+
275 #define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
+
276 #define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
+
277 #define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
+
278 #define RTC_AlarmMask_All ((uint32_t)0x80808080)
+
279 #define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
280 
+
288 #define RTC_Alarm_A ((uint32_t)0x00000100)
+
289 #define RTC_Alarm_B ((uint32_t)0x00000200)
+
290 #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+
291 #define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
292 
+
300 #define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000)
+
303 #define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000)
+
305 #define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000)
+
307 #define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000)
+
309 #define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000)
+
311 #define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000)
+
313 #define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000)
+
315 #define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000)
+
317 #define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000)
+
319 #define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000)
+
321 #define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000)
+
323 #define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000)
+
325 #define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000)
+
327 #define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000)
+
329 #define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000)
+
331 #define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000)
+
333 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
+
334  ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+
335  ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+
336  ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+
337  ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+
338  ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+
339  ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+
340  ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+
341  ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+
342  ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+
343  ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+
344  ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+
345  ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+
346  ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+
347  ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+
348  ((MASK) == RTC_AlarmSubSecondMask_None))
+
349 
+
357 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
358 
+
366 #define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
+
367 #define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
+
368 #define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
+
369 #define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
+
370 #define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
+
371 #define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
+
372 #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+
373  ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+
374  ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+
375  ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+
376  ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+
377  ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+
378 #define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+
379 
+
386 #define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
+
387 #define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
+
388 #define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+
389  ((EDGE) == RTC_TimeStampEdge_Falling))
+
390 
+
397 #define RTC_Output_Disable ((uint32_t)0x00000000)
+
398 #define RTC_Output_AlarmA ((uint32_t)0x00200000)
+
399 #define RTC_Output_AlarmB ((uint32_t)0x00400000)
+
400 #define RTC_Output_WakeUp ((uint32_t)0x00600000)
+
401 
+
402 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+
403  ((OUTPUT) == RTC_Output_AlarmA) || \
+
404  ((OUTPUT) == RTC_Output_AlarmB) || \
+
405  ((OUTPUT) == RTC_Output_WakeUp))
+
406 
+
414 #define RTC_OutputPolarity_High ((uint32_t)0x00000000)
+
415 #define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
+
416 #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+
417  ((POL) == RTC_OutputPolarity_Low))
+
418 
+
426 #define RTC_CalibSign_Positive ((uint32_t)0x00000000)
+
427 #define RTC_CalibSign_Negative ((uint32_t)0x00000080)
+
428 #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+
429  ((SIGN) == RTC_CalibSign_Negative))
+
430 #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
431 
+
439 #define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
+
440 #define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
+
441 #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+
442  ((OUTPUT) == RTC_CalibOutput_1Hz))
+
443 
+
450 #define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000)
+
452 #define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000)
+
454 #define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000)
+
456 #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+
457  ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+
458  ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+
459 
+
467 #define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000)
+
470 #define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000)
+
472 #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+
473  ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
474 
+
482 #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
483 
+
491 #define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
+
492 #define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
+
493 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+
494  ((SAVE) == RTC_DayLightSaving_ADD1H))
+
495 
+
496 #define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
+
497 #define RTC_StoreOperation_Set ((uint32_t)0x00040000)
+
498 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+
499  ((OPERATION) == RTC_StoreOperation_Set))
+
500 
+
507 #define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
+
508 #define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
+
509 #define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
+
510 #define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
+
511 #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+
512  ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+
513  ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+
514  ((TRIGGER) == RTC_TamperTrigger_HighLevel))
+
515 
+
523 #define RTC_TamperFilter_Disable ((uint32_t)0x00000000)
+
525 #define RTC_TamperFilter_2Sample ((uint32_t)0x00000800)
+
527 #define RTC_TamperFilter_4Sample ((uint32_t)0x00001000)
+
529 #define RTC_TamperFilter_8Sample ((uint32_t)0x00001800)
+
531 #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+
532  ((FILTER) == RTC_TamperFilter_2Sample) || \
+
533  ((FILTER) == RTC_TamperFilter_4Sample) || \
+
534  ((FILTER) == RTC_TamperFilter_8Sample))
+
535 
+
542 #define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000)
+
544 #define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100)
+
546 #define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200)
+
548 #define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300)
+
550 #define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400)
+
552 #define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500)
+
554 #define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600)
+
556 #define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700)
+
558 #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+
559  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+
560  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+
561  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+
562  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+
563  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+
564  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+
565  ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
566 
+
574 #define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)
+
576 #define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)
+
578 #define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)
+
580 #define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)
+
583 #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+
584  ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+
585  ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+
586  ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+
587 
+
594 #define RTC_Tamper_1 RTC_TAFCR_TAMP1E
+
595 #define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
+
596 
+
604 #define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
+
605 #define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
+
606 #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
+
607  ((PIN) == RTC_TamperPin_PI8))
+
608 
+
615 #define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000)
+
616 #define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
+
617 #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
+
618  ((PIN) == RTC_TimeStampPin_PI8))
+
619 
+
626 #define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
+
627 #define RTC_OutputType_PushPull ((uint32_t)0x00040000)
+
628 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+
629  ((TYPE) == RTC_OutputType_PushPull))
+
630 
+
638 #define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
+
639 #define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
+
640 #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+
641  ((SEL) == RTC_ShiftAdd1S_Set))
+
642 
+
649 #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
650 
+
659 #define RTC_BKP_DR0 ((uint32_t)0x00000000)
+
660 #define RTC_BKP_DR1 ((uint32_t)0x00000001)
+
661 #define RTC_BKP_DR2 ((uint32_t)0x00000002)
+
662 #define RTC_BKP_DR3 ((uint32_t)0x00000003)
+
663 #define RTC_BKP_DR4 ((uint32_t)0x00000004)
+
664 #define RTC_BKP_DR5 ((uint32_t)0x00000005)
+
665 #define RTC_BKP_DR6 ((uint32_t)0x00000006)
+
666 #define RTC_BKP_DR7 ((uint32_t)0x00000007)
+
667 #define RTC_BKP_DR8 ((uint32_t)0x00000008)
+
668 #define RTC_BKP_DR9 ((uint32_t)0x00000009)
+
669 #define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+
670 #define RTC_BKP_DR11 ((uint32_t)0x0000000B)
+
671 #define RTC_BKP_DR12 ((uint32_t)0x0000000C)
+
672 #define RTC_BKP_DR13 ((uint32_t)0x0000000D)
+
673 #define RTC_BKP_DR14 ((uint32_t)0x0000000E)
+
674 #define RTC_BKP_DR15 ((uint32_t)0x0000000F)
+
675 #define RTC_BKP_DR16 ((uint32_t)0x00000010)
+
676 #define RTC_BKP_DR17 ((uint32_t)0x00000011)
+
677 #define RTC_BKP_DR18 ((uint32_t)0x00000012)
+
678 #define RTC_BKP_DR19 ((uint32_t)0x00000013)
+
679 #define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
+
680  ((BKP) == RTC_BKP_DR1) || \
+
681  ((BKP) == RTC_BKP_DR2) || \
+
682  ((BKP) == RTC_BKP_DR3) || \
+
683  ((BKP) == RTC_BKP_DR4) || \
+
684  ((BKP) == RTC_BKP_DR5) || \
+
685  ((BKP) == RTC_BKP_DR6) || \
+
686  ((BKP) == RTC_BKP_DR7) || \
+
687  ((BKP) == RTC_BKP_DR8) || \
+
688  ((BKP) == RTC_BKP_DR9) || \
+
689  ((BKP) == RTC_BKP_DR10) || \
+
690  ((BKP) == RTC_BKP_DR11) || \
+
691  ((BKP) == RTC_BKP_DR12) || \
+
692  ((BKP) == RTC_BKP_DR13) || \
+
693  ((BKP) == RTC_BKP_DR14) || \
+
694  ((BKP) == RTC_BKP_DR15) || \
+
695  ((BKP) == RTC_BKP_DR16) || \
+
696  ((BKP) == RTC_BKP_DR17) || \
+
697  ((BKP) == RTC_BKP_DR18) || \
+
698  ((BKP) == RTC_BKP_DR19))
+
699 
+
706 #define RTC_Format_BIN ((uint32_t)0x000000000)
+
707 #define RTC_Format_BCD ((uint32_t)0x000000001)
+
708 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
709 
+
717 #define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
+
718 #define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+
719 #define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
+
720 #define RTC_FLAG_TSF ((uint32_t)0x00000800)
+
721 #define RTC_FLAG_WUTF ((uint32_t)0x00000400)
+
722 #define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
+
723 #define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
+
724 #define RTC_FLAG_INITF ((uint32_t)0x00000040)
+
725 #define RTC_FLAG_RSF ((uint32_t)0x00000020)
+
726 #define RTC_FLAG_INITS ((uint32_t)0x00000010)
+
727 #define RTC_FLAG_SHPF ((uint32_t)0x00000008)
+
728 #define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
+
729 #define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
+
730 #define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
+
731 #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+
732  ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+
733  ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+
734  ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+
735  ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+
736  ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+
737  ((FLAG) == RTC_FLAG_SHPF))
+
738 #define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+
739 
+
746 #define RTC_IT_TS ((uint32_t)0x00008000)
+
747 #define RTC_IT_WUT ((uint32_t)0x00004000)
+
748 #define RTC_IT_ALRB ((uint32_t)0x00002000)
+
749 #define RTC_IT_ALRA ((uint32_t)0x00001000)
+
750 #define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+
751 #define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+
752 
+
753 #define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+
754 #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+
755  ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+
756  ((IT) == RTC_IT_TAMP1))
+
757 #define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
+
758 
+
766 #define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
+
767 #define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
+
768 
+
777 /* Exported macro ------------------------------------------------------------*/
+
778 /* Exported functions --------------------------------------------------------*/
+
779 
+
780 /* Function used to set the RTC configuration to the default reset state *****/
+
781 ErrorStatus RTC_DeInit(void);
+
782 
+
783 /* Initialization and Configuration functions *********************************/
+
784 ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+
785 void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+
786 void RTC_WriteProtectionCmd(FunctionalState NewState);
+
787 ErrorStatus RTC_EnterInitMode(void);
+
788 void RTC_ExitInitMode(void);
+
789 ErrorStatus RTC_WaitForSynchro(void);
+
790 ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+
791 void RTC_BypassShadowCmd(FunctionalState NewState);
+
792 
+
793 /* Time and Date configuration functions **************************************/
+
794 ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+
795 void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+
796 void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+
797 uint32_t RTC_GetSubSecond(void);
+
798 ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
799 void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+
800 void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
801 
+
802 /* Alarms (Alarm A and Alarm B) configuration functions **********************/
+
803 void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+
804 void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+
805 void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+
806 ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+
807 void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+
808 uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
809 
+
810 /* WakeUp Timer configuration functions ***************************************/
+
811 void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+
812 void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+
813 uint32_t RTC_GetWakeUpCounter(void);
+
814 ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
815 
+
816 /* Daylight Saving configuration functions ************************************/
+
817 void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+
818 uint32_t RTC_GetStoreOperation(void);
+
819 
+
820 /* Output pin Configuration function ******************************************/
+
821 void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
822 
+
823 /* Digital Calibration configuration functions *********************************/
+
824 ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
+
825 ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
+
826 void RTC_CalibOutputCmd(FunctionalState NewState);
+
827 void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+
828 ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+
829  uint32_t RTC_SmoothCalibPlusPulses,
+
830  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
831 
+
832 /* TimeStamp configuration functions ******************************************/
+
833 void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+
834 void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+
835  RTC_DateTypeDef* RTC_StampDateStruct);
+
836 uint32_t RTC_GetTimeStampSubSecond(void);
+
837 
+
838 /* Tampers configuration functions ********************************************/
+
839 void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+
840 void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+
841 void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+
842 void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+
843 void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+
844 void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+
845 void RTC_TamperPullUpCmd(FunctionalState NewState);
+
846 
+
847 /* Backup Data Registers configuration functions ******************************/
+
848 void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+
849 uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
850 
+
851 /* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+
852  functions ******************************************************************/
+
853 void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
+
854 void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
+
855 void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
856 
+
857 /* RTC_Shift_control_synchonisation_functions *********************************/
+
858 ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
859 
+
860 /* Interrupts and flags management functions **********************************/
+
861 void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+
862 FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+
863 void RTC_ClearFlag(uint32_t RTC_FLAG);
+
864 ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+
865 void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
866 
+
867 #ifdef __cplusplus
+
868 }
+
869 #endif
+
870 
+
871 #endif /*__STM32F4xx_RTC_H */
+
872 
+
881 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
RTC_TamperPinsPrechargeDuration
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
Configures the Tampers Pins input Precharge Duration.
Definition: stm32f4xx_rtc.c:2219
+
RTC_WaitForSynchro
ErrorStatus RTC_WaitForSynchro(void)
Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are synchronized with RTC APB clock...
Definition: stm32f4xx_rtc.c:619
+
RTC_BypassShadowCmd
void RTC_BypassShadowCmd(FunctionalState NewState)
Enables or Disables the Bypass Shadow feature.
Definition: stm32f4xx_rtc.c:710
+
RTC_GetStoreOperation
uint32_t RTC_GetStoreOperation(void)
Returns the RTC Day Light Saving stored operation.
Definition: stm32f4xx_rtc.c:1658
+
RTC_Init
ErrorStatus RTC_Init(RTC_InitTypeDef *RTC_InitStruct)
Initializes the RTC registers according to the specified parameters in RTC_InitStruct.
Definition: stm32f4xx_rtc.c:457
+
RTC_WakeUpClockConfig
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
Configures the RTC Wakeup clock source.
Definition: stm32f4xx_rtc.c:1494
+
RTC_DateTypeDef::RTC_Date
uint8_t RTC_Date
Definition: stm32f4xx_rtc.h:96
+
RTC_SynchroShiftConfig
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
Configures the Synchronization Shift Control Settings.
Definition: stm32f4xx_rtc.c:2437
+
RTC_ITConfig
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
Enables or disables the specified RTC interrupts.
Definition: stm32f4xx_rtc.c:2557
+
RTC_TimeTypeDef::RTC_Hours
uint8_t RTC_Hours
Definition: stm32f4xx_rtc.h:70
+
RTC_TimeTypeDef::RTC_Seconds
uint8_t RTC_Seconds
Definition: stm32f4xx_rtc.h:78
+
RTC_AlarmStructInit
void RTC_AlarmStructInit(RTC_AlarmTypeDef *RTC_AlarmStruct)
Fills each RTC_AlarmStruct member with its default value (Time = 00h:00mn:00sec / Date = 1st day of t...
Definition: stm32f4xx_rtc.c:1226
+
RTC_TamperTriggerConfig
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
Configures the select Tamper pin edge.
Definition: stm32f4xx_rtc.c:2105
+
RTC_RefClockCmd
ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
Enables or disables the RTC reference clock detection.
Definition: stm32f4xx_rtc.c:662
+
RTC_EnterInitMode
ErrorStatus RTC_EnterInitMode(void)
Enters the RTC Initialization mode.
Definition: stm32f4xx_rtc.c:552
+
RTC_DateTypeDef
RTC Date structure definition.
Definition: stm32f4xx_rtc.h:88
+
RTC_WakeUpCmd
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
Enables or Disables the RTC WakeUp timer.
Definition: stm32f4xx_rtc.c:1554
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
RTC_TamperCmd
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
Enables or Disables the Tamper detection.
Definition: stm32f4xx_rtc.c:2131
+
RTC_AlarmTypeDef::RTC_AlarmTime
RTC_TimeTypeDef RTC_AlarmTime
Definition: stm32f4xx_rtc.h:108
+
RTC_DeInit
ErrorStatus RTC_DeInit(void)
Deinitializes the RTC registers to their default reset values.
Definition: stm32f4xx_rtc.c:375
+
RTC_GetFlagStatus
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
Checks whether the specified RTC flag is set or not.
Definition: stm32f4xx_rtc.c:2605
+
RTC_CalibOutputCmd
void RTC_CalibOutputCmd(FunctionalState NewState)
Enables or disables the RTC clock to be output through the relative pin.
Definition: stm32f4xx_rtc.c:1838
+
RTC_ExitInitMode
void RTC_ExitInitMode(void)
Exits the RTC Initialization mode.
Definition: stm32f4xx_rtc.c:597
+
RTC_TimeTypeDef::RTC_H12
uint8_t RTC_H12
Definition: stm32f4xx_rtc.h:81
+
RTC_GetTimeStamp
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef *RTC_StampTimeStruct, RTC_DateTypeDef *RTC_StampDateStruct)
Get the RTC TimeStamp value and masks.
Definition: stm32f4xx_rtc.c:2026
+
RTC_ClearFlag
void RTC_ClearFlag(uint32_t RTC_FLAG)
Clears the RTC's pending flags.
Definition: stm32f4xx_rtc.c:2641
+
RTC_GetSubSecond
uint32_t RTC_GetSubSecond(void)
Gets the RTC current Calendar Sub seconds value.
Definition: stm32f4xx_rtc.c:920
+
RTC_TimeTypeDef::RTC_Minutes
uint8_t RTC_Minutes
Definition: stm32f4xx_rtc.h:75
+
RTC_SetTime
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Set the RTC current time.
Definition: stm32f4xx_rtc.c:765
+
RTC_InitTypeDef::RTC_HourFormat
uint32_t RTC_HourFormat
Definition: stm32f4xx_rtc.h:55
+
RTC_CoarseCalibConfig
ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
Configures the Coarse calibration parameters.
Definition: stm32f4xx_rtc.c:1751
+
RTC_GetTime
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef *RTC_TimeStruct)
Get the RTC current Time.
Definition: stm32f4xx_rtc.c:887
+
RTC_DateTypeDef::RTC_WeekDay
uint8_t RTC_WeekDay
Definition: stm32f4xx_rtc.h:90
+
RTC_TamperPullUpCmd
void RTC_TamperPullUpCmd(FunctionalState NewState)
Enables or Disables the Precharge of Tamper pin.
Definition: stm32f4xx_rtc.c:2262
+
RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel
uint32_t RTC_AlarmDateWeekDaySel
Definition: stm32f4xx_rtc.h:113
+
RTC_TimeTypeDef
RTC Time structure definition.
Definition: stm32f4xx_rtc.h:68
+
RTC_SmoothCalibConfig
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue)
Configures the Smooth Calibration Settings.
Definition: stm32f4xx_rtc.c:1906
+
RTC_AlarmTypeDef::RTC_AlarmMask
uint32_t RTC_AlarmMask
Definition: stm32f4xx_rtc.h:110
+
RTC_DateStructInit
void RTC_DateStructInit(RTC_DateTypeDef *RTC_DateStruct)
Fills each RTC_DateStruct member with its default value (Monday, January 01 xx00).
Definition: stm32f4xx_rtc.c:1036
+
RTC_SetWakeUpCounter
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
Configures the RTC Wakeup counter.
Definition: stm32f4xx_rtc.c:1521
+
RTC_AlarmSubSecondConfig
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
Configure the RTC AlarmA/B Sub seconds value and mask.*.
Definition: stm32f4xx_rtc.c:1404
+
RTC_CoarseCalibCmd
ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
Enables or disables the Coarse calibration process.
Definition: stm32f4xx_rtc.c:1792
+
RTC_SetDate
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Set the RTC current date.
Definition: stm32f4xx_rtc.c:945
+
RTC_GetTimeStampSubSecond
uint32_t RTC_GetTimeStampSubSecond(void)
Get the RTC timestamp Sub seconds value.
Definition: stm32f4xx_rtc.c:2070
+
RTC_TamperFilterConfig
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
Configures the Tampers Filter.
Definition: stm32f4xx_rtc.c:2162
+
RTC_InitTypeDef::RTC_AsynchPrediv
uint32_t RTC_AsynchPrediv
Definition: stm32f4xx_rtc.h:58
+
RTC_SetAlarm
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Set the specified RTC Alarm.
Definition: stm32f4xx_rtc.c:1115
+
RTC_TimeStampCmd
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
Enables or Disables the RTC TimeStamp functionality with the specified time stamp pin stimulating edg...
Definition: stm32f4xx_rtc.c:1982
+
RTC_GetITStatus
ITStatus RTC_GetITStatus(uint32_t RTC_IT)
Checks whether the specified RTC interrupt has occurred or not.
Definition: stm32f4xx_rtc.c:2661
+
RTC_InitTypeDef::RTC_SynchPrediv
uint32_t RTC_SynchPrediv
Definition: stm32f4xx_rtc.h:61
+
RTC_OutputConfig
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
Configures the RTC output source (AFO_ALARM).
Definition: stm32f4xx_rtc.c:1697
+
RTC_DateTypeDef::RTC_Year
uint8_t RTC_Year
Definition: stm32f4xx_rtc.h:99
+
RTC_ReadBackupRegister
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
Reads data from the specified RTC Backup data Register.
Definition: stm32f4xx_rtc.c:2324
+
RTC_TamperSamplingFreqConfig
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
Configures the Tampers Sampling Frequency.
Definition: stm32f4xx_rtc.c:2196
+
RTC_TimeStructInit
void RTC_TimeStructInit(RTC_TimeTypeDef *RTC_TimeStruct)
Fills each RTC_TimeStruct member with its default value (Time = 00h:00min:00sec). ...
Definition: stm32f4xx_rtc.c:868
+
RTC_GetDate
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef *RTC_DateStruct)
Get the RTC current date.
Definition: stm32f4xx_rtc.c:1055
+
RTC_CalibOutputConfig
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
Definition: stm32f4xx_rtc.c:1870
+
RTC_WriteBackupRegister
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
Writes a data in a specified RTC Backup data register.
Definition: stm32f4xx_rtc.c:2303
+
RTC_AlarmCmd
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
Enables or disables the specified RTC Alarm.
Definition: stm32f4xx_rtc.c:1310
+
RTC_GetWakeUpCounter
uint32_t RTC_GetWakeUpCounter(void)
Returns the RTC WakeUp timer counter value.
Definition: stm32f4xx_rtc.c:1542
+
RTC_GetAlarm
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef *RTC_AlarmStruct)
Get the RTC Alarm value and masks.
Definition: stm32f4xx_rtc.c:1256
+
RTC_ClearITPendingBit
void RTC_ClearITPendingBit(uint32_t RTC_IT)
Clears the RTC's interrupt pending bits.
Definition: stm32f4xx_rtc.c:2701
+
RTC_WriteProtectionCmd
void RTC_WriteProtectionCmd(FunctionalState NewState)
Enables or disables the RTC registers write protection.
Definition: stm32f4xx_rtc.c:525
+
RTC_DateTypeDef::RTC_Month
uint8_t RTC_Month
Definition: stm32f4xx_rtc.h:93
+
RTC_DayLightSavingConfig
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
Adds or substract one hour from the current time.
Definition: stm32f4xx_rtc.c:1631
+
RTC_OutputTypeConfig
void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
Configures the RTC Output Pin mode.
Definition: stm32f4xx_rtc.c:2399
+
RTC_AlarmTypeDef::RTC_AlarmDateWeekDay
uint8_t RTC_AlarmDateWeekDay
Definition: stm32f4xx_rtc.h:116
+
RTC_GetAlarmSubSecond
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
Gets the RTC Alarm Sub seconds value.
Definition: stm32f4xx_rtc.c:1445
+
RTC_TimeStampPinSelection
void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)
Selects the RTC TimeStamp Pin.
Definition: stm32f4xx_rtc.c:2380
+
RTC_StructInit
void RTC_StructInit(RTC_InitTypeDef *RTC_InitStruct)
Fills each RTC_InitStruct member with its default value.
Definition: stm32f4xx_rtc.c:503
+
RTC_InitTypeDef
RTC Init structures definition.
Definition: stm32f4xx_rtc.h:53
+
RTC_AlarmTypeDef
RTC Alarm structure definition.
Definition: stm32f4xx_rtc.h:106
+
RTC_TamperPinSelection
void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
Selects the RTC Tamper Pin.
Definition: stm32f4xx_rtc.c:2363
+
RTC_TimeStampOnTamperDetectionCmd
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
Enables or Disables the TimeStamp on Tamper Detection Event.
Definition: stm32f4xx_rtc.c:2239
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sai_8c.html b/stm32f4xx__sai_8c.html new file mode 100644 index 0000000..2267675 --- /dev/null +++ b/stm32f4xx__sai_8c.html @@ -0,0 +1,308 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_sai.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_sai.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI): +More...

+
#include "stm32f4xx_sai.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_sai.c:
+
+
+ + +
+
+ + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint32_t)0xFF07C010)
 
+#define FRCR_CLEAR_MASK   ((uint32_t)0xFFF88000)
 
+#define SLOTR_CLEAR_MASK   ((uint32_t)0x0000F020)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SAI_DeInit (SAI_TypeDef *SAIx)
 Deinitialize the SAIx peripheral registers to their default reset values. More...
 
void SAI_Init (SAI_Block_TypeDef *SAI_Block_x, SAI_InitTypeDef *SAI_InitStruct)
 Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct. More...
 
void SAI_FrameInit (SAI_Block_TypeDef *SAI_Block_x, SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct. More...
 
void SAI_SlotInit (SAI_Block_TypeDef *SAI_Block_x, SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct. More...
 
void SAI_StructInit (SAI_InitTypeDef *SAI_InitStruct)
 Fills each SAI_InitStruct member with its default value. More...
 
void SAI_FrameStructInit (SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Fills each SAI_FrameInitStruct member with its default value. More...
 
void SAI_SlotStructInit (SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Fills each SAI_SlotInitStruct member with its default value. More...
 
void SAI_Cmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the specified SAI Block peripheral. More...
 
void SAI_MonoModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_Mono_StreoMode)
 Configures the mono mode for the selected SAI block. More...
 
void SAI_TRIStateConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_TRIState)
 Configures the TRIState managment on data line for the selected SAI block. More...
 
void SAI_CompandingModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_CompandingMode)
 Configures the companding mode for the selected SAI block. More...
 
void SAI_MuteModeCmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_MuteValueConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteValue)
 Configure the mute value for the selected SAI block. More...
 
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteCounter)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_FlushFIFO (SAI_Block_TypeDef *SAI_Block_x)
 Reinitialize the FIFO pointer. More...
 
uint32_t SAI_ReceiveData (SAI_Block_TypeDef *SAI_Block_x)
 Returns the most recent received data by the SAI block x peripheral. More...
 
void SAI_SendData (SAI_Block_TypeDef *SAI_Block_x, uint32_t Data)
 Transmits a Data through the SAI block x peripheral. More...
 
void SAI_DMACmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the SAI Block x DMA interface. More...
 
void SAI_ITConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
 Enables or disables the specified SAI Block interrupts. More...
 
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Checks whether the specified SAI block x flag is set or not. More...
 
void SAI_ClearFlag (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Clears the specified SAI Block x flag. More...
 
ITStatus SAI_GetITStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Checks whether the specified SAI Block x interrupt has occurred or not. More...
 
void SAI_ClearITPendingBit (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Clears the SAI Block x interrupt pending bit. More...
 
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the status of EN bit for the specified SAI Block x. More...
 
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the current SAI Block x FIFO filled level. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Serial Audio Interface (SAI):

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Data transfers functions
    • +
  • DMA transfers management
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                    ##### How to use this driver #####
+===============================================================================
+   [..] 
+   
+      (#) Enable peripheral clock using the following functions 
+          RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1
+ 
+      (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks 
+          using RCC_AHB1PeriphClockCmd() function.
+ 
+      (#) Peripherals alternate function: 
+          (++) Connect the pin to the desired peripherals' Alternate 
+               Function (AF) using GPIO_PinAFConfig() function.
+          (++) Configure the desired pin in alternate function by:
+               GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+          (++) Select the type, pull-up/pull-down and output speed via 
+               GPIO_PuPd, GPIO_OType and GPIO_Speed members
+          (++) Call GPIO_Init() function
+          -@@- If an external clock source is used then the I2S CKIN pin should be 
+              also configured in Alternate function Push-pull pull-up mode.
+               
+     (#) The SAI clock can be generated from different clock source :
+         PLL I2S, PLL SAI or external clock source.
+         (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), 
+              RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and 
+              RCC_SAIPLLI2SClkDivConfig() or;
+             
+         (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), 
+              RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and 
+              RCC_SAIPLLSAIClkDivConfig()or;          
+             
+         (++) External clock source is configured using the function 
+              RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the 
+              define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.      
+               
+     (#) Each SAI Block A or B has its own clock generator to make these two blocks 
+         completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and 
+         RCC_SAIBlockBCLKConfig() functions.
+                 
+     (#) Each SAI Block A or B can be configured separetely : 
+         (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, 
+              Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function.   
+              In case of master mode, program the Master clock divider (MCKDIV) using 
+              the following formula :  
+              (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS
+              (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256
+              (+++) MCKDIV = SAI_CK_x / FS * 512
+        (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, 
+             FS Offset using SAI_FrameInit() function.    
+        (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active 
+             using SAI_SlotInit() function. 
+                  
+     (#) Enable the NVIC and the corresponding interrupt using the function 
+         SAI_ITConfig() if you need to use interrupt mode. 
+ 
+     (#) When using the DMA mode 
+         (++) Configure the DMA using DMA_Init() function
+         (++) Active the needed channel Request using SAI_DMACmd() function
+  
+     (#) Enable the SAI using the SAI_Cmd() function.
+  
+     (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+ 
+     (#) The SAI has some specific functions which can be useful depending 
+         on the audio protocol selected.  
+         (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd()
+              function and configure the value transmitted during mute using SAI_MuteValueConfig().  
+         (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig().             
+         (++) Enable the MONO mode without any data preprocessing in memory when the number
+              of slot is equal to 2 using SAI_MonoModeConfig() function.
+         (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig().
+         (++) Choose the behavior of the SD line in output when an inactive slot is sent 
+              on the data line using SAI_TRIStateConfig() function.   
+ [..]               
+  (@)    In master TX mode: enabling the audio block immediately generates the bit clock 
+         for the external slaves even if there is no data in the FIFO, However FS signal 
+         generation is conditioned by the presence of data in the FIFO.
+                
+  (@)    In master RX mode: enabling the audio block immediately generates the bit clock 
+         and FS signal for the external slaves. 
+               
+  (@)    It is mandatory to respect the following conditions in order to avoid bad SAI behavior: 
+           (+@)  First bit Offset <= (SLOT size - Data size)
+           (+@)  Data size <= SLOT size
+           (+@)  Number of SLOT x SLOT size = Frame length
+           (+@)  The number of slots should be even when bit FSDEF in the SAI_xFRCR is set.
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sai_8c__incl.map b/stm32f4xx__sai_8c__incl.map new file mode 100644 index 0000000..787dc6f --- /dev/null +++ b/stm32f4xx__sai_8c__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__sai_8c__incl.md5 b/stm32f4xx__sai_8c__incl.md5 new file mode 100644 index 0000000..e90be83 --- /dev/null +++ b/stm32f4xx__sai_8c__incl.md5 @@ -0,0 +1 @@ +4db06eacfb62ca5abc69c50ca46669a0 \ No newline at end of file diff --git a/stm32f4xx__sai_8c__incl.png b/stm32f4xx__sai_8c__incl.png new file mode 100644 index 0000000..e91385f Binary files /dev/null and b/stm32f4xx__sai_8c__incl.png differ diff --git a/stm32f4xx__sai_8h.html b/stm32f4xx__sai_8h.html new file mode 100644 index 0000000..1c51768 --- /dev/null +++ b/stm32f4xx__sai_8h.html @@ -0,0 +1,554 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_sai.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
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+
stm32f4xx_sai.h File Reference
+
+
+ +

This file contains all the functions prototypes for the SAI firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_sai.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + +

+Classes

struct  SAI_InitTypeDef
 SAI Block Init structure definition. More...
 
struct  SAI_FrameInitTypeDef
 SAI Block Frame Init structure definition. More...
 
struct  SAI_SlotInitTypeDef
 SAI Block Slot Init Structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define IS_SAI_PERIPH(PERIPH)   ((PERIPH) == SAI1)
 
#define IS_SAI_BLOCK_PERIPH(PERIPH)
 
+#define SAI_Mode_MasterTx   ((uint32_t)0x00000000)
 
+#define SAI_Mode_MasterRx   ((uint32_t)0x00000001)
 
+#define SAI_Mode_SlaveTx   ((uint32_t)0x00000002)
 
+#define SAI_Mode_SlaveRx   ((uint32_t)0x00000003)
 
#define IS_SAI_BLOCK_MODE(MODE)
 
+#define SAI_Free_Protocol   ((uint32_t)0x00000000)
 
+#define SAI_SPDIF_Protocol   ((uint32_t)SAI_xCR1_PRTCFG_0)
 
+#define SAI_AC97_Protocol   ((uint32_t)SAI_xCR1_PRTCFG_1)
 
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL)
 
+#define SAI_DataSize_8b   ((uint32_t)0x00000040)
 
+#define SAI_DataSize_10b   ((uint32_t)0x00000060)
 
+#define SAI_DataSize_16b   ((uint32_t)0x00000080)
 
+#define SAI_DataSize_20b   ((uint32_t)0x000000A0)
 
+#define SAI_DataSize_24b   ((uint32_t)0x000000C0)
 
+#define SAI_DataSize_32b   ((uint32_t)0x000000E0)
 
#define IS_SAI_BLOCK_DATASIZE(DATASIZE)
 
+#define SAI_FirstBit_MSB   ((uint32_t)0x00000000)
 
+#define SAI_FirstBit_LSB   ((uint32_t)SAI_xCR1_LSBFIRST)
 
#define IS_SAI_BLOCK_FIRST_BIT(BIT)
 
+#define SAI_ClockStrobing_FallingEdge   ((uint32_t)0x00000000)
 
+#define SAI_ClockStrobing_RisingEdge   ((uint32_t)SAI_xCR1_CKSTR)
 
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK)
 
+#define SAI_Asynchronous   ((uint32_t)0x00000000)
 
+#define SAI_Synchronous   ((uint32_t)SAI_xCR1_SYNCEN_0)
 
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO)
 
+#define SAI_OutputDrive_Disabled   ((uint32_t)0x00000000)
 
+#define SAI_OutputDrive_Enabled   ((uint32_t)SAI_xCR1_OUTDRIV)
 
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE)
 
+#define SAI_MasterDivider_Enabled   ((uint32_t)0x00000000)
 
+#define SAI_MasterDivider_Disabled   ((uint32_t)SAI_xCR1_NODIV)
 
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER)
 
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER)   ((DIVIDER) <= 15)
 
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH)   ((8 <= (LENGTH)) && ((LENGTH) <= 256))
 
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH)   ((1 <= (LENGTH)) && ((LENGTH) <= 128))
 
+#define SAI_FS_StartFrame   ((uint32_t)0x00000000)
 
+#define I2S_FS_ChannelIdentification   ((uint32_t)SAI_xFRCR_FSDEF)
 
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION)
 
+#define SAI_FS_ActiveLow   ((uint32_t)0x00000000)
 
+#define SAI_FS_ActiveHigh   ((uint32_t)SAI_xFRCR_FSPO)
 
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY)
 
+#define SAI_FS_FirstBit   ((uint32_t)0x00000000)
 
+#define SAI_FS_BeforeFirstBit   ((uint32_t)SAI_xFRCR_FSOFF)
 
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET)
 
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET)   ((OFFSET) <= 24)
 
+#define SAI_SlotSize_DataSize   ((uint32_t)0x00000000)
 
+#define SAI_SlotSize_16b   ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
 
+#define SAI_SlotSize_32b   ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
 
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE)
 
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER)   ((1 <= (NUMBER)) && ((NUMBER) <= 16))
 
+#define SAI_Slot_NotActive   ((uint32_t)0x00000000)
 
+#define SAI_SlotActive_0   ((uint32_t)0x00010000)
 
+#define SAI_SlotActive_1   ((uint32_t)0x00020000)
 
+#define SAI_SlotActive_2   ((uint32_t)0x00040000)
 
+#define SAI_SlotActive_3   ((uint32_t)0x00080000)
 
+#define SAI_SlotActive_4   ((uint32_t)0x00100000)
 
+#define SAI_SlotActive_5   ((uint32_t)0x00200000)
 
+#define SAI_SlotActive_6   ((uint32_t)0x00400000)
 
+#define SAI_SlotActive_7   ((uint32_t)0x00800000)
 
+#define SAI_SlotActive_8   ((uint32_t)0x01000000)
 
+#define SAI_SlotActive_9   ((uint32_t)0x02000000)
 
+#define SAI_SlotActive_10   ((uint32_t)0x04000000)
 
+#define SAI_SlotActive_11   ((uint32_t)0x08000000)
 
+#define SAI_SlotActive_12   ((uint32_t)0x10000000)
 
+#define SAI_SlotActive_13   ((uint32_t)0x20000000)
 
+#define SAI_SlotActive_14   ((uint32_t)0x40000000)
 
+#define SAI_SlotActive_15   ((uint32_t)0x80000000)
 
+#define SAI_SlotActive_ALL   ((uint32_t)0xFFFF0000)
 
+#define IS_SAI_SLOT_ACTIVE(ACTIVE)   ((ACTIVE) != 0)
 
+#define SAI_MonoMode   ((uint32_t)SAI_xCR1_MONO)
 
+#define SAI_StreoMode   ((uint32_t)0x00000000)
 
#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE)
 
+#define SAI_Output_NotReleased   ((uint32_t)0x00000000)
 
+#define SAI_Output_Released   ((uint32_t)SAI_xCR2_TRIS)
 
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE)
 
+#define SAI_Threshold_FIFOEmpty   ((uint32_t)0x00000000)
 
+#define SAI_FIFOThreshold_1QuarterFull   ((uint32_t)0x00000001)
 
+#define SAI_FIFOThreshold_HalfFull   ((uint32_t)0x00000002)
 
+#define SAI_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000003)
 
+#define SAI_FIFOThreshold_Full   ((uint32_t)0x00000004)
 
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD)
 
+#define SAI_NoCompanding   ((uint32_t)0x00000000)
 
+#define SAI_ULaw_1CPL_Companding   ((uint32_t)0x00008000)
 
+#define SAI_ALaw_1CPL_Companding   ((uint32_t)0x0000C000)
 
+#define SAI_ULaw_2CPL_Companding   ((uint32_t)0x0000A000)
 
+#define SAI_ALaw_2CPL_Companding   ((uint32_t)0x0000E000)
 
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)
 
+#define SAI_ZeroValue   ((uint32_t)0x00000000)
 
+#define SAI_LastSentValue   ((uint32_t)SAI_xCR2_MUTEVAL)
 
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)
 
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER)   ((COUNTER) <= 63)
 
+#define SAI_IT_OVRUDR   ((uint32_t)SAI_xIMR_OVRUDRIE)
 
+#define SAI_IT_MUTEDET   ((uint32_t)SAI_xIMR_MUTEDETIE)
 
+#define SAI_IT_WCKCFG   ((uint32_t)SAI_xIMR_WCKCFGIE)
 
+#define SAI_IT_FREQ   ((uint32_t)SAI_xIMR_FREQIE)
 
+#define SAI_IT_CNRDY   ((uint32_t)SAI_xIMR_CNRDYIE)
 
+#define SAI_IT_AFSDET   ((uint32_t)SAI_xIMR_AFSDETIE)
 
+#define SAI_IT_LFSDET   ((uint32_t)SAI_xIMR_LFSDETIE)
 
#define IS_SAI_BLOCK_CONFIG_IT(IT)
 
+#define SAI_FLAG_OVRUDR   ((uint32_t)SAI_xSR_OVRUDR)
 
+#define SAI_FLAG_MUTEDET   ((uint32_t)SAI_xSR_MUTEDET)
 
+#define SAI_FLAG_WCKCFG   ((uint32_t)SAI_xSR_WCKCFG)
 
+#define SAI_FLAG_FREQ   ((uint32_t)SAI_xSR_FREQ)
 
+#define SAI_FLAG_CNRDY   ((uint32_t)SAI_xSR_CNRDY)
 
+#define SAI_FLAG_AFSDET   ((uint32_t)SAI_xSR_AFSDET)
 
+#define SAI_FLAG_LFSDET   ((uint32_t)SAI_xSR_LFSDET)
 
#define IS_SAI_BLOCK_GET_FLAG(FLAG)
 
#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG)
 
+#define SAI_FIFOStatus_Empty   ((uint32_t)0x00000000)
 
+#define SAI_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00010000)
 
+#define SAI_FIFOStatus_1QuarterFull   ((uint32_t)0x00020000)
 
+#define SAI_FIFOStatus_HalfFull   ((uint32_t)0x00030000)
 
+#define SAI_FIFOStatus_3QuartersFull   ((uint32_t)0x00040000)
 
+#define SAI_FIFOStatus_Full   ((uint32_t)0x00050000)
 
#define IS_SAI_BLOCK_FIFO_STATUS(STATUS)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SAI_DeInit (SAI_TypeDef *SAIx)
 Deinitialize the SAIx peripheral registers to their default reset values. More...
 
void SAI_Init (SAI_Block_TypeDef *SAI_Block_x, SAI_InitTypeDef *SAI_InitStruct)
 Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct. More...
 
void SAI_FrameInit (SAI_Block_TypeDef *SAI_Block_x, SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruct. More...
 
void SAI_SlotInit (SAI_Block_TypeDef *SAI_Block_x, SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct. More...
 
void SAI_StructInit (SAI_InitTypeDef *SAI_InitStruct)
 Fills each SAI_InitStruct member with its default value. More...
 
void SAI_FrameStructInit (SAI_FrameInitTypeDef *SAI_FrameInitStruct)
 Fills each SAI_FrameInitStruct member with its default value. More...
 
void SAI_SlotStructInit (SAI_SlotInitTypeDef *SAI_SlotInitStruct)
 Fills each SAI_SlotInitStruct member with its default value. More...
 
void SAI_Cmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the specified SAI Block peripheral. More...
 
void SAI_MonoModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_Mono_StreoMode)
 Configures the mono mode for the selected SAI block. More...
 
void SAI_TRIStateConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_TRIState)
 Configures the TRIState managment on data line for the selected SAI block. More...
 
void SAI_CompandingModeConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_CompandingMode)
 Configures the companding mode for the selected SAI block. More...
 
void SAI_MuteModeCmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_MuteValueConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteValue)
 Configure the mute value for the selected SAI block. More...
 
void SAI_MuteFrameCounterConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteCounter)
 Enables or disables the Mute mode for the selected SAI block. More...
 
void SAI_FlushFIFO (SAI_Block_TypeDef *SAI_Block_x)
 Reinitialize the FIFO pointer. More...
 
void SAI_SendData (SAI_Block_TypeDef *SAI_Block_x, uint32_t Data)
 Transmits a Data through the SAI block x peripheral. More...
 
uint32_t SAI_ReceiveData (SAI_Block_TypeDef *SAI_Block_x)
 Returns the most recent received data by the SAI block x peripheral. More...
 
void SAI_DMACmd (SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
 Enables or disables the SAI Block x DMA interface. More...
 
void SAI_ITConfig (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
 Enables or disables the specified SAI Block interrupts. More...
 
FlagStatus SAI_GetFlagStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Checks whether the specified SAI block x flag is set or not. More...
 
void SAI_ClearFlag (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
 Clears the specified SAI Block x flag. More...
 
ITStatus SAI_GetITStatus (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Checks whether the specified SAI Block x interrupt has occurred or not. More...
 
void SAI_ClearITPendingBit (SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
 Clears the SAI Block x interrupt pending bit. More...
 
FunctionalState SAI_GetCmdStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the status of EN bit for the specified SAI Block x. More...
 
uint32_t SAI_GetFIFOStatus (SAI_Block_TypeDef *SAI_Block_x)
 Returns the current SAI Block x FIFO filled level. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the SAI firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sai_8h__dep__incl.map b/stm32f4xx__sai_8h__dep__incl.map new file mode 100644 index 0000000..51dfcbe --- /dev/null +++ b/stm32f4xx__sai_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/stm32f4xx__sai_8h__dep__incl.md5 b/stm32f4xx__sai_8h__dep__incl.md5 new file mode 100644 index 0000000..89d7703 --- /dev/null +++ b/stm32f4xx__sai_8h__dep__incl.md5 @@ -0,0 +1 @@ +2846a3d3e94a513bd228765372960e74 \ No newline at end of file diff --git a/stm32f4xx__sai_8h__dep__incl.png b/stm32f4xx__sai_8h__dep__incl.png new file mode 100644 index 0000000..4d7e273 Binary files /dev/null and b/stm32f4xx__sai_8h__dep__incl.png differ diff --git a/stm32f4xx__sai_8h__incl.map b/stm32f4xx__sai_8h__incl.map new file mode 100644 index 0000000..5fff35e --- /dev/null +++ b/stm32f4xx__sai_8h__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__sai_8h__incl.md5 b/stm32f4xx__sai_8h__incl.md5 new file mode 100644 index 0000000..9a6fdfd --- /dev/null +++ b/stm32f4xx__sai_8h__incl.md5 @@ -0,0 +1 @@ +a6b1ec86fb3cbe100cc3dc5cd29eb7fe \ No newline at end of file diff --git a/stm32f4xx__sai_8h__incl.png b/stm32f4xx__sai_8h__incl.png new file mode 100644 index 0000000..9abccc3 Binary files /dev/null and b/stm32f4xx__sai_8h__incl.png differ diff --git a/stm32f4xx__sai_8h_source.html b/stm32f4xx__sai_8h_source.html new file mode 100644 index 0000000..7f4e662 --- /dev/null +++ b/stm32f4xx__sai_8h_source.html @@ -0,0 +1,451 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_sai.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
stm32f4xx_sai.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_SAI_H
+
31 #define __STM32F4xx_SAI_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t SAI_AudioMode;
+
59  uint32_t SAI_Protocol;
+
62  uint32_t SAI_DataSize;
+
66  uint32_t SAI_FirstBit;
+
70  uint32_t SAI_ClockStrobing;
+
73  uint32_t SAI_Synchro;
+
76  uint32_t SAI_OUTDRIV;
+
81  uint32_t SAI_NoDivider;
+
84  uint32_t SAI_MasterDivider;
+
88  uint32_t SAI_FIFOThreshold;
+
90 }SAI_InitTypeDef;
+
91 
+
96 typedef struct
+
97 {
+
98 
+
99  uint32_t SAI_FrameLength;
+
107  uint32_t SAI_ActiveFrameLength;
+
113  uint32_t SAI_FSDefinition;
+
117  uint32_t SAI_FSPolarity;
+
121  uint32_t SAI_FSOffset;
+
125 }SAI_FrameInitTypeDef;
+
126 
+
131 typedef struct
+
132 {
+
133  uint32_t SAI_FirstBitOffset;
+
137  uint32_t SAI_SlotSize;
+
141  uint32_t SAI_SlotNumber;
+
145  uint32_t SAI_SlotActive;
+
148 }SAI_SlotInitTypeDef;
+
149 
+
150 /* Exported constants --------------------------------------------------------*/
+
151 
+
156 #define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1)
+
157 
+
158 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+
159  ((PERIPH) == SAI1_Block_B))
+
160 
+
161 
+
165 #define SAI_Mode_MasterTx ((uint32_t)0x00000000)
+
166 #define SAI_Mode_MasterRx ((uint32_t)0x00000001)
+
167 #define SAI_Mode_SlaveTx ((uint32_t)0x00000002)
+
168 #define SAI_Mode_SlaveRx ((uint32_t)0x00000003)
+
169 #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \
+
170  ((MODE) == SAI_Mode_MasterRx) || \
+
171  ((MODE) == SAI_Mode_SlaveTx) || \
+
172  ((MODE) == SAI_Mode_SlaveRx))
+
173 
+
181 #define SAI_Free_Protocol ((uint32_t)0x00000000)
+
182 #define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0)
+
183 #define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1)
+
184 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \
+
185  ((PROTOCOL) == SAI_SPDIF_Protocol) || \
+
186  ((PROTOCOL) == SAI_AC97_Protocol))
+
187 
+
195 #define SAI_DataSize_8b ((uint32_t)0x00000040)
+
196 #define SAI_DataSize_10b ((uint32_t)0x00000060)
+
197 #define SAI_DataSize_16b ((uint32_t)0x00000080)
+
198 #define SAI_DataSize_20b ((uint32_t)0x000000A0)
+
199 #define SAI_DataSize_24b ((uint32_t)0x000000C0)
+
200 #define SAI_DataSize_32b ((uint32_t)0x000000E0)
+
201 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \
+
202  ((DATASIZE) == SAI_DataSize_10b) || \
+
203  ((DATASIZE) == SAI_DataSize_16b) || \
+
204  ((DATASIZE) == SAI_DataSize_20b) || \
+
205  ((DATASIZE) == SAI_DataSize_24b) || \
+
206  ((DATASIZE) == SAI_DataSize_32b))
+
207 
+
215 #define SAI_FirstBit_MSB ((uint32_t)0x00000000)
+
216 #define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
+
217 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \
+
218  ((BIT) == SAI_FirstBit_LSB))
+
219 
+
227 #define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000)
+
228 #define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR)
+
229 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \
+
230  ((CLOCK) == SAI_ClockStrobing_RisingEdge))
+
231 
+
239 #define SAI_Asynchronous ((uint32_t)0x00000000)
+
240 #define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0)
+
241 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
+
242  ((SYNCHRO) == SAI_Asynchronous))
+
243 
+
251 #define SAI_OutputDrive_Disabled ((uint32_t)0x00000000)
+
252 #define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV)
+
253 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \
+
254  ((DRIVE) == SAI_OutputDrive_Enabled))
+
255 
+
265 #define SAI_MasterDivider_Enabled ((uint32_t)0x00000000)
+
266 #define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV)
+
267 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \
+
268  ((NODIVIDER) == SAI_MasterDivider_Disabled))
+
269 
+
277 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
+
278 
+
286 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+
287 
+
295 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+
296 
+
305 #define SAI_FS_StartFrame ((uint32_t)0x00000000)
+
306 #define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF)
+
307 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \
+
308  ((DEFINITION) == I2S_FS_ChannelIdentification))
+
309 
+
317 #define SAI_FS_ActiveLow ((uint32_t)0x00000000)
+
318 #define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO)
+
319 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \
+
320  ((POLARITY) == SAI_FS_ActiveHigh))
+
321 
+
329 #define SAI_FS_FirstBit ((uint32_t)0x00000000)
+
330 #define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF)
+
331 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \
+
332  ((OFFSET) == SAI_FS_BeforeFirstBit))
+
333 
+
340 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+
341 
+
349 #define SAI_SlotSize_DataSize ((uint32_t)0x00000000)
+
350 #define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
+
351 #define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+
352 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \
+
353  ((SIZE) == SAI_SlotSize_16b) || \
+
354  ((SIZE) == SAI_SlotSize_32b))
+
355 
+
363 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+
364 
+
372 #define SAI_Slot_NotActive ((uint32_t)0x00000000)
+
373 #define SAI_SlotActive_0 ((uint32_t)0x00010000)
+
374 #define SAI_SlotActive_1 ((uint32_t)0x00020000)
+
375 #define SAI_SlotActive_2 ((uint32_t)0x00040000)
+
376 #define SAI_SlotActive_3 ((uint32_t)0x00080000)
+
377 #define SAI_SlotActive_4 ((uint32_t)0x00100000)
+
378 #define SAI_SlotActive_5 ((uint32_t)0x00200000)
+
379 #define SAI_SlotActive_6 ((uint32_t)0x00400000)
+
380 #define SAI_SlotActive_7 ((uint32_t)0x00800000)
+
381 #define SAI_SlotActive_8 ((uint32_t)0x01000000)
+
382 #define SAI_SlotActive_9 ((uint32_t)0x02000000)
+
383 #define SAI_SlotActive_10 ((uint32_t)0x04000000)
+
384 #define SAI_SlotActive_11 ((uint32_t)0x08000000)
+
385 #define SAI_SlotActive_12 ((uint32_t)0x10000000)
+
386 #define SAI_SlotActive_13 ((uint32_t)0x20000000)
+
387 #define SAI_SlotActive_14 ((uint32_t)0x40000000)
+
388 #define SAI_SlotActive_15 ((uint32_t)0x80000000)
+
389 #define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000)
+
390 
+
391 #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
+
392 
+
401 #define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO)
+
402 #define SAI_StreoMode ((uint32_t)0x00000000)
+
403 #define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\
+
404  ((MODE) == SAI_StreoMode))
+
405 
+
413 #define SAI_Output_NotReleased ((uint32_t)0x00000000)
+
414 #define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS)
+
415 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\
+
416  ((STATE) == SAI_Output_Released))
+
417 
+
425 #define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000)
+
426 #define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001)
+
427 #define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002)
+
428 #define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003)
+
429 #define SAI_FIFOThreshold_Full ((uint32_t)0x00000004)
+
430 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \
+
431  ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \
+
432  ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \
+
433  ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \
+
434  ((THRESHOLD) == SAI_FIFOThreshold_Full))
+
435 
+
443 #define SAI_NoCompanding ((uint32_t)0x00000000)
+
444 #define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000)
+
445 #define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000)
+
446 #define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000)
+
447 #define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000)
+
448 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \
+
449  ((MODE) == SAI_ULaw_1CPL_Companding) || \
+
450  ((MODE) == SAI_ALaw_1CPL_Companding) || \
+
451  ((MODE) == SAI_ULaw_2CPL_Companding) || \
+
452  ((MODE) == SAI_ALaw_2CPL_Companding))
+
453 
+
461 #define SAI_ZeroValue ((uint32_t)0x00000000)
+
462 #define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL)
+
463 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \
+
464  ((VALUE) == SAI_LastSentValue))
+
465 
+
473 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+
474 
+
483 #define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
+
484 #define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
+
485 #define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
+
486 #define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
+
487 #define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
+
488 #define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
+
489 #define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
+
490 
+
491 #define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
+
492  ((IT) == SAI_IT_MUTEDET) || \
+
493  ((IT) == SAI_IT_WCKCFG) || \
+
494  ((IT) == SAI_IT_FREQ) || \
+
495  ((IT) == SAI_IT_CNRDY) || \
+
496  ((IT) == SAI_IT_AFSDET) || \
+
497  ((IT) == SAI_IT_LFSDET))
+
498 
+
506 #define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
+
507 #define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
+
508 #define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
+
509 #define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
+
510 #define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
+
511 #define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
+
512 #define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
+
513 
+
514 #define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+
515  ((FLAG) == SAI_FLAG_MUTEDET) || \
+
516  ((FLAG) == SAI_FLAG_WCKCFG) || \
+
517  ((FLAG) == SAI_FLAG_FREQ) || \
+
518  ((FLAG) == SAI_FLAG_CNRDY) || \
+
519  ((FLAG) == SAI_FLAG_AFSDET) || \
+
520  ((FLAG) == SAI_FLAG_LFSDET))
+
521 
+
522 #define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
+
523  ((FLAG) == SAI_FLAG_MUTEDET) || \
+
524  ((FLAG) == SAI_FLAG_WCKCFG) || \
+
525  ((FLAG) == SAI_FLAG_FREQ) || \
+
526  ((FLAG) == SAI_FLAG_CNRDY) || \
+
527  ((FLAG) == SAI_FLAG_AFSDET) || \
+
528  ((FLAG) == SAI_FLAG_LFSDET))
+
529 
+
536 #define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
+
537 #define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
+
538 #define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
+
539 #define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
+
540 #define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
+
541 #define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
+
542 
+
543 #define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
+
544  ((STATUS) == SAI_FIFOStatus_HalfFull) || \
+
545  ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
+
546  ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
+
547  ((STATUS) == SAI_FIFOStatus_Full) || \
+
548  ((STATUS) == SAI_FIFOStatus_Empty))
+
549 
+
558 /* Exported macro ------------------------------------------------------------*/
+
559 /* Exported functions --------------------------------------------------------*/
+
560 
+
561 /* Function used to set the SAI configuration to the default reset state *****/
+
562 void SAI_DeInit(SAI_TypeDef* SAIx);
+
563 
+
564 /* Initialization and Configuration functions *********************************/
+
565 void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct);
+
566 void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct);
+
567 void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct);
+
568 void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct);
+
569 void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct);
+
570 void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct);
+
571 
+
572 void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
+
573 void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode);
+
574 void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState);
+
575 void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode);
+
576 void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
+
577 void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue);
+
578 void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter);
+
579 void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x);
+
580 
+
581 /* Data transfers functions ***************************************************/
+
582 void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data);
+
583 uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x);
+
584 
+
585 /* DMA transfers management functions *****************************************/
+
586 void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
+
587 
+
588 /* Interrupts and flags management functions **********************************/
+
589 void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
+
590 FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
+
591 void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
+
592 ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
+
593 void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
+
594 FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
+
595 uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
+
596 
+
597 #ifdef __cplusplus
+
598 }
+
599 #endif
+
600 
+
601 #endif /*__STM32F4xx_SAI_H */
+
602 
+
611 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
SAI_SlotInitTypeDef::SAI_FirstBitOffset
uint32_t SAI_FirstBitOffset
Definition: stm32f4xx_sai.h:133
+
SAI_SlotInitTypeDef::SAI_SlotNumber
uint32_t SAI_SlotNumber
Definition: stm32f4xx_sai.h:141
+
SAI_SendData
void SAI_SendData(SAI_Block_TypeDef *SAI_Block_x, uint32_t Data)
Transmits a Data through the SAI block x peripheral.
Definition: stm32f4xx_sai.c:670
+
SAI_ClearFlag
void SAI_ClearFlag(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
Clears the specified SAI Block x flag.
Definition: stm32f4xx_sai.c:922
+
SAI_GetITStatus
ITStatus SAI_GetITStatus(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
Checks whether the specified SAI Block x interrupt has occurred or not.
Definition: stm32f4xx_sai.c:947
+
SAI_ReceiveData
uint32_t SAI_ReceiveData(SAI_Block_TypeDef *SAI_Block_x)
Returns the most recent received data by the SAI block x peripheral.
Definition: stm32f4xx_sai.c:654
+
SAI_FlushFIFO
void SAI_FlushFIFO(SAI_Block_TypeDef *SAI_Block_x)
Reinitialize the FIFO pointer.
Definition: stm32f4xx_sai.c:612
+
SAI_FrameInitTypeDef
SAI Block Frame Init structure definition.
Definition: stm32f4xx_sai.h:96
+
SAI_MuteModeCmd
void SAI_MuteModeCmd(SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
Enables or disables the Mute mode for the selected SAI block.
Definition: stm32f4xx_sai.c:536
+
SAI_Cmd
void SAI_Cmd(SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
Enables or disables the specified SAI Block peripheral.
Definition: stm32f4xx_sai.c:432
+
SAI_FrameInitTypeDef::SAI_FSDefinition
uint32_t SAI_FSDefinition
Definition: stm32f4xx_sai.h:113
+
SAI_DeInit
void SAI_DeInit(SAI_TypeDef *SAIx)
Deinitialize the SAIx peripheral registers to their default reset values.
Definition: stm32f4xx_sai.c:182
+
SAI_InitTypeDef::SAI_AudioMode
uint32_t SAI_AudioMode
Definition: stm32f4xx_sai.h:56
+
SAI_GetFIFOStatus
uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef *SAI_Block_x)
Returns the current SAI Block x FIFO filled level.
Definition: stm32f4xx_sai.c:1049
+
SAI_StructInit
void SAI_StructInit(SAI_InitTypeDef *SAI_InitStruct)
Fills each SAI_InitStruct member with its default value.
Definition: stm32f4xx_sai.c:359
+
SAI_SlotStructInit
void SAI_SlotStructInit(SAI_SlotInitTypeDef *SAI_SlotInitStruct)
Fills each SAI_SlotInitStruct member with its default value.
Definition: stm32f4xx_sai.c:411
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
SAI_GetFlagStatus
FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_FLAG)
Checks whether the specified SAI block x flag is set or not.
Definition: stm32f4xx_sai.c:879
+
SAI_FrameInitTypeDef::SAI_ActiveFrameLength
uint32_t SAI_ActiveFrameLength
Definition: stm32f4xx_sai.h:107
+
SAI_InitTypeDef::SAI_FIFOThreshold
uint32_t SAI_FIFOThreshold
Definition: stm32f4xx_sai.h:88
+
SAI_MonoModeConfig
void SAI_MonoModeConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_Mono_StreoMode)
Configures the mono mode for the selected SAI block.
Definition: stm32f4xx_sai.c:461
+
SAI_ClearITPendingBit
void SAI_ClearITPendingBit(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT)
Clears the SAI Block x interrupt pending bit.
Definition: stm32f4xx_sai.c:994
+
SAI_SlotInitTypeDef::SAI_SlotActive
uint32_t SAI_SlotActive
Definition: stm32f4xx_sai.h:145
+
SAI_InitTypeDef
SAI Block Init structure definition.
Definition: stm32f4xx_sai.h:54
+
SAI_InitTypeDef::SAI_DataSize
uint32_t SAI_DataSize
Definition: stm32f4xx_sai.h:62
+
SAI_Init
void SAI_Init(SAI_Block_TypeDef *SAI_Block_x, SAI_InitTypeDef *SAI_InitStruct)
Initializes the SAI Block x peripheral according to the specified parameters in the SAI_InitStruct...
Definition: stm32f4xx_sai.c:205
+
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f4xx.h:1208
+
SAI_GetCmdStatus
FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef *SAI_Block_x)
Returns the status of EN bit for the specified SAI Block x.
Definition: stm32f4xx_sai.c:1016
+
SAI_InitTypeDef::SAI_MasterDivider
uint32_t SAI_MasterDivider
Definition: stm32f4xx_sai.h:84
+
SAI_InitTypeDef::SAI_Synchro
uint32_t SAI_Synchro
Definition: stm32f4xx_sai.h:73
+
SAI_InitTypeDef::SAI_NoDivider
uint32_t SAI_NoDivider
Definition: stm32f4xx_sai.h:81
+
SAI_MuteValueConfig
void SAI_MuteValueConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteValue)
Configure the mute value for the selected SAI block.
Definition: stm32f4xx_sai.c:567
+
SAI_InitTypeDef::SAI_FirstBit
uint32_t SAI_FirstBit
Definition: stm32f4xx_sai.h:66
+
SAI_FrameStructInit
void SAI_FrameStructInit(SAI_FrameInitTypeDef *SAI_FrameInitStruct)
Fills each SAI_FrameInitStruct member with its default value.
Definition: stm32f4xx_sai.c:390
+
SAI_CompandingModeConfig
void SAI_CompandingModeConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_CompandingMode)
Configures the companding mode for the selected SAI block.
Definition: stm32f4xx_sai.c:512
+
SAI_FrameInitTypeDef::SAI_FSPolarity
uint32_t SAI_FSPolarity
Definition: stm32f4xx_sai.h:117
+
SAI_SlotInitTypeDef::SAI_SlotSize
uint32_t SAI_SlotSize
Definition: stm32f4xx_sai.h:137
+
SAI_MuteFrameCounterConfig
void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_MuteCounter)
Enables or disables the Mute mode for the selected SAI block.
Definition: stm32f4xx_sai.c:589
+
SAI_TRIStateConfig
void SAI_TRIStateConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_TRIState)
Configures the TRIState managment on data line for the selected SAI block.
Definition: stm32f4xx_sai.c:484
+
SAI_FrameInitTypeDef::SAI_FSOffset
uint32_t SAI_FSOffset
Definition: stm32f4xx_sai.h:121
+
SAI_InitTypeDef::SAI_OUTDRIV
uint32_t SAI_OUTDRIV
Definition: stm32f4xx_sai.h:76
+
SAI_SlotInitTypeDef
SAI Block Slot Init Structure definition.
Definition: stm32f4xx_sai.h:131
+
SAI_FrameInit
void SAI_FrameInit(SAI_Block_TypeDef *SAI_Block_x, SAI_FrameInitTypeDef *SAI_FrameInitStruct)
Initializes the SAI Block Audio frame according to the specified parameters in the SAI_FrameInitStruc...
Definition: stm32f4xx_sai.c:272
+
SAI_DMACmd
void SAI_DMACmd(SAI_Block_TypeDef *SAI_Block_x, FunctionalState NewState)
Enables or disables the SAI Block x DMA interface.
Definition: stm32f4xx_sai.c:702
+
SAI_SlotInit
void SAI_SlotInit(SAI_Block_TypeDef *SAI_Block_x, SAI_SlotInitTypeDef *SAI_SlotInitStruct)
Initializes the SAI Block audio Slot according to the specified parameters in the SAI_SlotInitStruct...
Definition: stm32f4xx_sai.c:320
+
SAI_Block_TypeDef
Definition: stm32f4xx.h:1213
+
SAI_InitTypeDef::SAI_Protocol
uint32_t SAI_Protocol
Definition: stm32f4xx_sai.h:59
+
SAI_ITConfig
void SAI_ITConfig(SAI_Block_TypeDef *SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState)
Enables or disables the specified SAI Block interrupts.
Definition: stm32f4xx_sai.c:846
+
SAI_FrameInitTypeDef::SAI_FrameLength
uint32_t SAI_FrameLength
Definition: stm32f4xx_sai.h:99
+
SAI_InitTypeDef::SAI_ClockStrobing
uint32_t SAI_ClockStrobing
Definition: stm32f4xx_sai.h:70
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sdio_8c.html b/stm32f4xx__sdio_8c.html new file mode 100644 index 0000000..3654533 --- /dev/null +++ b/stm32f4xx__sdio_8c.html @@ -0,0 +1,437 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_sdio.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_sdio.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Secure digital input/output interface (SDIO) peripheral: +More...

+
#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_sdio.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_OFFSET   (SDIO_BASE - PERIPH_BASE)
 
+#define CLKCR_OFFSET   (SDIO_OFFSET + 0x04)
 
+#define CLKEN_BitNumber   0x08
 
+#define CLKCR_CLKEN_BB   (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
 
+#define CMD_OFFSET   (SDIO_OFFSET + 0x0C)
 
+#define SDIOSUSPEND_BitNumber   0x0B
 
+#define CMD_SDIOSUSPEND_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
 
+#define ENCMDCOMPL_BitNumber   0x0C
 
+#define CMD_ENCMDCOMPL_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
 
+#define NIEN_BitNumber   0x0D
 
+#define CMD_NIEN_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
 
+#define ATACMD_BitNumber   0x0E
 
+#define CMD_ATACMD_BB   (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
 
+#define DCTRL_OFFSET   (SDIO_OFFSET + 0x2C)
 
+#define DMAEN_BitNumber   0x03
 
+#define DCTRL_DMAEN_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
 
+#define RWSTART_BitNumber   0x08
 
+#define DCTRL_RWSTART_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
 
+#define RWSTOP_BitNumber   0x09
 
+#define DCTRL_RWSTOP_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
 
+#define RWMOD_BitNumber   0x0A
 
+#define DCTRL_RWMOD_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
 
+#define SDIOEN_BitNumber   0x0B
 
+#define DCTRL_SDIOEN_BB   (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
 
+#define CLKCR_CLEAR_MASK   ((uint32_t)0xFFFF8100)
 
+#define PWR_PWRCTRL_MASK   ((uint32_t)0xFFFFFFFC)
 
+#define DCTRL_CLEAR_MASK   ((uint32_t)0xFFFFFF08)
 
+#define CMD_CLEAR_MASK   ((uint32_t)0xFFFFF800)
 
+#define SDIO_RESP_ADDR   ((uint32_t)(SDIO_BASE + 0x14))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SDIO_DeInit (void)
 Deinitializes the SDIO peripheral registers to their default reset values. More...
 
void SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
 Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. More...
 
void SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
 Fills each SDIO_InitStruct member with its default value. More...
 
void SDIO_ClockCmd (FunctionalState NewState)
 Enables or disables the SDIO Clock. More...
 
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
 Sets the power status of the controller. More...
 
uint32_t SDIO_GetPowerState (void)
 Gets the power status of the controller. More...
 
void SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command. More...
 
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Fills each SDIO_CmdInitStruct member with its default value. More...
 
uint8_t SDIO_GetCommandResponse (void)
 Returns command index of last command for which response received. More...
 
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
 Returns response received from the card for the last command. More...
 
void SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. More...
 
void SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Fills each SDIO_DataInitStruct member with its default value. More...
 
uint32_t SDIO_GetDataCounter (void)
 Returns number of remaining data bytes to be transferred. More...
 
uint32_t SDIO_ReadData (void)
 Read one data word from Rx FIFO. More...
 
void SDIO_WriteData (uint32_t Data)
 Write one data word to Tx FIFO. More...
 
uint32_t SDIO_GetFIFOCount (void)
 Returns the number of words left to be written to or read from FIFO. More...
 
void SDIO_StartSDIOReadWait (FunctionalState NewState)
 Starts the SD I/O Read Wait operation. More...
 
void SDIO_StopSDIOReadWait (FunctionalState NewState)
 Stops the SD I/O Read Wait operation. More...
 
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
 Sets one of the two options of inserting read wait interval. More...
 
void SDIO_SetSDIOOperation (FunctionalState NewState)
 Enables or disables the SD I/O Mode Operation. More...
 
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
 Enables or disables the SD I/O Mode suspend command sending. More...
 
void SDIO_CommandCompletionCmd (FunctionalState NewState)
 Enables or disables the command completion signal. More...
 
void SDIO_CEATAITCmd (FunctionalState NewState)
 Enables or disables the CE-ATA interrupt. More...
 
void SDIO_SendCEATACmd (FunctionalState NewState)
 Sends CE-ATA command (CMD61). More...
 
void SDIO_DMACmd (FunctionalState NewState)
 Enables or disables the SDIO DMA request. More...
 
void SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
 Enables or disables the SDIO interrupts. More...
 
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
 Checks whether the specified SDIO flag is set or not. More...
 
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
 Clears the SDIO's pending flags. More...
 
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
 Checks whether the specified SDIO interrupt has occurred or not. More...
 
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
 Clears the SDIO's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Secure digital input/output interface (SDIO) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Command path state machine (CPSM) management
    • +
  • Data path state machine (DPSM) management
    • +
  • SDIO IO Cards mode management
    • +
  • CE-ATA mode management
    • +
  • DMA transfers management
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================
+                 ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL 
+       (PLL48CLK). Before to start working with SDIO peripheral make sure that the
+       PLL is well configured.
+       The SDIO peripheral uses two clock signals:
+       (++) SDIO adapter clock (SDIOCLK = 48 MHz)
+       (++) APB2 bus clock (PCLK2)
+       
+       -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
+           Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
+  
+   (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
+  
+   (#) According to the SDIO mode, enable the GPIO clocks using 
+       RCC_AHB1PeriphClockCmd() function. 
+       The I/O can be one of the following configurations:
+       (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
+       (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
+       (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].      
+  
+   (#) Peripheral alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate Function (AF) 
+           using GPIO_PinAFConfig() function
+       (++) Configure the desired pin in alternate function by: 
+           GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, 
+           GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function
+  
+   (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, 
+       hardware, flow control and the Clock Divider using the SDIO_Init()
+       function.
+  
+   (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) 
+       function.
+                
+   (#) Enable the clock using the SDIO_ClockCmd() function.
+  
+   (#) Enable the NVIC and the corresponding interrupt using the function 
+       SDIO_ITConfig() if you need to use interrupt mode. 
+  
+   (#) When using the DMA mode 
+       (++) Configure the DMA using DMA_Init() function
+       (++) Active the needed channel Request using SDIO_DMACmd() function
+  
+   (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  
+   (#) To control the CPSM (Command Path State Machine) and send 
+       commands to the card use the SDIO_SendCommand(), 
+       SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
+       to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
+       to the selected command to be sent.
+       The parameters that should be filled are:
+       (++) Command Argument
+       (++) Command Index
+       (++) Command Response type
+       (++) Command Wait
+       (++) CPSM Status (Enable or Disable).
+  
+       -@@- To check if the command is well received, read the SDIO_CMDRESP
+           register using the SDIO_GetCommandResponse().
+           The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+           SDIO_GetResponse() function.
+  
+   (#) To control the DPSM (Data Path State Machine) and send/receive 
+       data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
+       SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
+  
+ *** Read Operations ***
+ =======================
+ [..]
+   (#) First, user has to fill the data structure (pointer to
+       SDIO_DataInitTypeDef) according to the selected data type to be received.
+       The parameters that should be filled are:
+       (++) Data TimeOut
+       (++) Data Length
+       (++) Data Block size
+       (++) Data Transfer direction: should be from card (To SDIO)
+       (++) Data Transfer mode
+       (++) DPSM Status (Enable or Disable)
+                                     
+   (#) Configure the SDIO resources to receive the data from the card
+       according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+   (#)  Send the selected Read command (refer to step 11).
+                    
+   (#) Use the SDIO flags/interrupts to check the transfer status.
+  
+ *** Write Operations ***
+ ========================
+ [..]
+   (#) First, user has to fill the data structure (pointer to
+       SDIO_DataInitTypeDef) according to the selected data type to be received.
+       The parameters that should be filled are:
+       (++) Data TimeOut
+       (++) Data Length
+       (++) Data Block size
+       (++) Data Transfer direction:  should be to card (To CARD)
+       (++) Data Transfer mode
+       (++) DPSM Status (Enable or Disable)
+  
+   (#) Configure the SDIO resources to send the data to the card according to 
+       selected transfer mode (Refer to Step 8, 9 and 10).
+                     
+   (#) Send the selected Write command (refer to step 11).
+                    
+   (#) Use the SDIO flags/interrupts to check the transfer status.
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sdio_8c__incl.map b/stm32f4xx__sdio_8c__incl.map new file mode 100644 index 0000000..80ae66a --- /dev/null +++ b/stm32f4xx__sdio_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__sdio_8c__incl.md5 b/stm32f4xx__sdio_8c__incl.md5 new file mode 100644 index 0000000..14e6ff8 --- /dev/null +++ b/stm32f4xx__sdio_8c__incl.md5 @@ -0,0 +1 @@ +3b5a6206705ae8c7bf92d31eca6d489a \ No newline at end of file diff --git a/stm32f4xx__sdio_8c__incl.png b/stm32f4xx__sdio_8c__incl.png new file mode 100644 index 0000000..b9522f8 Binary files /dev/null and b/stm32f4xx__sdio_8c__incl.png differ diff --git a/stm32f4xx__sdio_8h.html b/stm32f4xx__sdio_8h.html new file mode 100644 index 0000000..a15f557 --- /dev/null +++ b/stm32f4xx__sdio_8h.html @@ -0,0 +1,577 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_sdio.h File Reference + + + + + + + + + + +
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+ + + + + + +
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+
+Classes | +Macros | +Functions
+
+
stm32f4xx_sdio.h File Reference
+
+
+ +

This file contains all the functions prototypes for the SDIO firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_sdio.h:
+
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+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
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+

Go to the source code of this file.

+ + + + + + + + +

+Classes

struct  SDIO_InitTypeDef
 
struct  SDIO_CmdInitTypeDef
 
struct  SDIO_DataInitTypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SDIO_ClockEdge_Rising   ((uint32_t)0x00000000)
 
+#define SDIO_ClockEdge_Falling   ((uint32_t)0x00002000)
 
#define IS_SDIO_CLOCK_EDGE(EDGE)
 
+#define SDIO_ClockBypass_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_ClockBypass_Enable   ((uint32_t)0x00000400)
 
#define IS_SDIO_CLOCK_BYPASS(BYPASS)
 
+#define SDIO_ClockPowerSave_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_ClockPowerSave_Enable   ((uint32_t)0x00000200)
 
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE)
 
+#define SDIO_BusWide_1b   ((uint32_t)0x00000000)
 
+#define SDIO_BusWide_4b   ((uint32_t)0x00000800)
 
+#define SDIO_BusWide_8b   ((uint32_t)0x00001000)
 
#define IS_SDIO_BUS_WIDE(WIDE)
 
+#define SDIO_HardwareFlowControl_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_HardwareFlowControl_Enable   ((uint32_t)0x00004000)
 
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL)
 
+#define SDIO_PowerState_OFF   ((uint32_t)0x00000000)
 
+#define SDIO_PowerState_ON   ((uint32_t)0x00000003)
 
+#define IS_SDIO_POWER_STATE(STATE)   (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
 
+#define SDIO_IT_CCRCFAIL   ((uint32_t)0x00000001)
 
+#define SDIO_IT_DCRCFAIL   ((uint32_t)0x00000002)
 
+#define SDIO_IT_CTIMEOUT   ((uint32_t)0x00000004)
 
+#define SDIO_IT_DTIMEOUT   ((uint32_t)0x00000008)
 
+#define SDIO_IT_TXUNDERR   ((uint32_t)0x00000010)
 
+#define SDIO_IT_RXOVERR   ((uint32_t)0x00000020)
 
+#define SDIO_IT_CMDREND   ((uint32_t)0x00000040)
 
+#define SDIO_IT_CMDSENT   ((uint32_t)0x00000080)
 
+#define SDIO_IT_DATAEND   ((uint32_t)0x00000100)
 
+#define SDIO_IT_STBITERR   ((uint32_t)0x00000200)
 
+#define SDIO_IT_DBCKEND   ((uint32_t)0x00000400)
 
+#define SDIO_IT_CMDACT   ((uint32_t)0x00000800)
 
+#define SDIO_IT_TXACT   ((uint32_t)0x00001000)
 
+#define SDIO_IT_RXACT   ((uint32_t)0x00002000)
 
+#define SDIO_IT_TXFIFOHE   ((uint32_t)0x00004000)
 
+#define SDIO_IT_RXFIFOHF   ((uint32_t)0x00008000)
 
+#define SDIO_IT_TXFIFOF   ((uint32_t)0x00010000)
 
+#define SDIO_IT_RXFIFOF   ((uint32_t)0x00020000)
 
+#define SDIO_IT_TXFIFOE   ((uint32_t)0x00040000)
 
+#define SDIO_IT_RXFIFOE   ((uint32_t)0x00080000)
 
+#define SDIO_IT_TXDAVL   ((uint32_t)0x00100000)
 
+#define SDIO_IT_RXDAVL   ((uint32_t)0x00200000)
 
+#define SDIO_IT_SDIOIT   ((uint32_t)0x00400000)
 
+#define SDIO_IT_CEATAEND   ((uint32_t)0x00800000)
 
+#define IS_SDIO_IT(IT)   ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
 
+#define IS_SDIO_CMD_INDEX(INDEX)   ((INDEX) < 0x40)
 
+#define SDIO_Response_No   ((uint32_t)0x00000000)
 
+#define SDIO_Response_Short   ((uint32_t)0x00000040)
 
+#define SDIO_Response_Long   ((uint32_t)0x000000C0)
 
#define IS_SDIO_RESPONSE(RESPONSE)
 
#define SDIO_Wait_No   ((uint32_t)0x00000000)
 
#define SDIO_Wait_IT   ((uint32_t)0x00000100)
 
#define SDIO_Wait_Pend   ((uint32_t)0x00000200)
 
#define IS_SDIO_WAIT(WAIT)
 
+#define SDIO_CPSM_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_CPSM_Enable   ((uint32_t)0x00000400)
 
+#define IS_SDIO_CPSM(CPSM)   (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
 
+#define SDIO_RESP1   ((uint32_t)0x00000000)
 
+#define SDIO_RESP2   ((uint32_t)0x00000004)
 
+#define SDIO_RESP3   ((uint32_t)0x00000008)
 
+#define SDIO_RESP4   ((uint32_t)0x0000000C)
 
#define IS_SDIO_RESP(RESP)
 
+#define IS_SDIO_DATA_LENGTH(LENGTH)   ((LENGTH) <= 0x01FFFFFF)
 
+#define SDIO_DataBlockSize_1b   ((uint32_t)0x00000000)
 
+#define SDIO_DataBlockSize_2b   ((uint32_t)0x00000010)
 
+#define SDIO_DataBlockSize_4b   ((uint32_t)0x00000020)
 
+#define SDIO_DataBlockSize_8b   ((uint32_t)0x00000030)
 
+#define SDIO_DataBlockSize_16b   ((uint32_t)0x00000040)
 
+#define SDIO_DataBlockSize_32b   ((uint32_t)0x00000050)
 
+#define SDIO_DataBlockSize_64b   ((uint32_t)0x00000060)
 
+#define SDIO_DataBlockSize_128b   ((uint32_t)0x00000070)
 
+#define SDIO_DataBlockSize_256b   ((uint32_t)0x00000080)
 
+#define SDIO_DataBlockSize_512b   ((uint32_t)0x00000090)
 
+#define SDIO_DataBlockSize_1024b   ((uint32_t)0x000000A0)
 
+#define SDIO_DataBlockSize_2048b   ((uint32_t)0x000000B0)
 
+#define SDIO_DataBlockSize_4096b   ((uint32_t)0x000000C0)
 
+#define SDIO_DataBlockSize_8192b   ((uint32_t)0x000000D0)
 
+#define SDIO_DataBlockSize_16384b   ((uint32_t)0x000000E0)
 
#define IS_SDIO_BLOCK_SIZE(SIZE)
 
+#define SDIO_TransferDir_ToCard   ((uint32_t)0x00000000)
 
+#define SDIO_TransferDir_ToSDIO   ((uint32_t)0x00000002)
 
#define IS_SDIO_TRANSFER_DIR(DIR)
 
+#define SDIO_TransferMode_Block   ((uint32_t)0x00000000)
 
+#define SDIO_TransferMode_Stream   ((uint32_t)0x00000004)
 
#define IS_SDIO_TRANSFER_MODE(MODE)
 
+#define SDIO_DPSM_Disable   ((uint32_t)0x00000000)
 
+#define SDIO_DPSM_Enable   ((uint32_t)0x00000001)
 
+#define IS_SDIO_DPSM(DPSM)   (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
 
+#define SDIO_FLAG_CCRCFAIL   ((uint32_t)0x00000001)
 
+#define SDIO_FLAG_DCRCFAIL   ((uint32_t)0x00000002)
 
+#define SDIO_FLAG_CTIMEOUT   ((uint32_t)0x00000004)
 
+#define SDIO_FLAG_DTIMEOUT   ((uint32_t)0x00000008)
 
+#define SDIO_FLAG_TXUNDERR   ((uint32_t)0x00000010)
 
+#define SDIO_FLAG_RXOVERR   ((uint32_t)0x00000020)
 
+#define SDIO_FLAG_CMDREND   ((uint32_t)0x00000040)
 
+#define SDIO_FLAG_CMDSENT   ((uint32_t)0x00000080)
 
+#define SDIO_FLAG_DATAEND   ((uint32_t)0x00000100)
 
+#define SDIO_FLAG_STBITERR   ((uint32_t)0x00000200)
 
+#define SDIO_FLAG_DBCKEND   ((uint32_t)0x00000400)
 
+#define SDIO_FLAG_CMDACT   ((uint32_t)0x00000800)
 
+#define SDIO_FLAG_TXACT   ((uint32_t)0x00001000)
 
+#define SDIO_FLAG_RXACT   ((uint32_t)0x00002000)
 
+#define SDIO_FLAG_TXFIFOHE   ((uint32_t)0x00004000)
 
+#define SDIO_FLAG_RXFIFOHF   ((uint32_t)0x00008000)
 
+#define SDIO_FLAG_TXFIFOF   ((uint32_t)0x00010000)
 
+#define SDIO_FLAG_RXFIFOF   ((uint32_t)0x00020000)
 
+#define SDIO_FLAG_TXFIFOE   ((uint32_t)0x00040000)
 
+#define SDIO_FLAG_RXFIFOE   ((uint32_t)0x00080000)
 
+#define SDIO_FLAG_TXDAVL   ((uint32_t)0x00100000)
 
+#define SDIO_FLAG_RXDAVL   ((uint32_t)0x00200000)
 
+#define SDIO_FLAG_SDIOIT   ((uint32_t)0x00400000)
 
+#define SDIO_FLAG_CEATAEND   ((uint32_t)0x00800000)
 
#define IS_SDIO_FLAG(FLAG)
 
+#define IS_SDIO_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
 
#define IS_SDIO_GET_IT(IT)
 
+#define IS_SDIO_CLEAR_IT(IT)   ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
 
+#define SDIO_ReadWaitMode_DATA2   ((uint32_t)0x00000000)
 
+#define SDIO_ReadWaitMode_CLK   ((uint32_t)0x00000001)
 
#define IS_SDIO_READWAIT_MODE(MODE)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SDIO_DeInit (void)
 Deinitializes the SDIO peripheral registers to their default reset values. More...
 
void SDIO_Init (SDIO_InitTypeDef *SDIO_InitStruct)
 Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. More...
 
void SDIO_StructInit (SDIO_InitTypeDef *SDIO_InitStruct)
 Fills each SDIO_InitStruct member with its default value. More...
 
void SDIO_ClockCmd (FunctionalState NewState)
 Enables or disables the SDIO Clock. More...
 
void SDIO_SetPowerState (uint32_t SDIO_PowerState)
 Sets the power status of the controller. More...
 
uint32_t SDIO_GetPowerState (void)
 Gets the power status of the controller. More...
 
void SDIO_SendCommand (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command. More...
 
void SDIO_CmdStructInit (SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
 Fills each SDIO_CmdInitStruct member with its default value. More...
 
uint8_t SDIO_GetCommandResponse (void)
 Returns command index of last command for which response received. More...
 
uint32_t SDIO_GetResponse (uint32_t SDIO_RESP)
 Returns response received from the card for the last command. More...
 
void SDIO_DataConfig (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. More...
 
void SDIO_DataStructInit (SDIO_DataInitTypeDef *SDIO_DataInitStruct)
 Fills each SDIO_DataInitStruct member with its default value. More...
 
uint32_t SDIO_GetDataCounter (void)
 Returns number of remaining data bytes to be transferred. More...
 
uint32_t SDIO_ReadData (void)
 Read one data word from Rx FIFO. More...
 
void SDIO_WriteData (uint32_t Data)
 Write one data word to Tx FIFO. More...
 
uint32_t SDIO_GetFIFOCount (void)
 Returns the number of words left to be written to or read from FIFO. More...
 
void SDIO_StartSDIOReadWait (FunctionalState NewState)
 Starts the SD I/O Read Wait operation. More...
 
void SDIO_StopSDIOReadWait (FunctionalState NewState)
 Stops the SD I/O Read Wait operation. More...
 
void SDIO_SetSDIOReadWaitMode (uint32_t SDIO_ReadWaitMode)
 Sets one of the two options of inserting read wait interval. More...
 
void SDIO_SetSDIOOperation (FunctionalState NewState)
 Enables or disables the SD I/O Mode Operation. More...
 
void SDIO_SendSDIOSuspendCmd (FunctionalState NewState)
 Enables or disables the SD I/O Mode suspend command sending. More...
 
void SDIO_CommandCompletionCmd (FunctionalState NewState)
 Enables or disables the command completion signal. More...
 
void SDIO_CEATAITCmd (FunctionalState NewState)
 Enables or disables the CE-ATA interrupt. More...
 
void SDIO_SendCEATACmd (FunctionalState NewState)
 Sends CE-ATA command (CMD61). More...
 
void SDIO_DMACmd (FunctionalState NewState)
 Enables or disables the SDIO DMA request. More...
 
void SDIO_ITConfig (uint32_t SDIO_IT, FunctionalState NewState)
 Enables or disables the SDIO interrupts. More...
 
FlagStatus SDIO_GetFlagStatus (uint32_t SDIO_FLAG)
 Checks whether the specified SDIO flag is set or not. More...
 
void SDIO_ClearFlag (uint32_t SDIO_FLAG)
 Clears the SDIO's pending flags. More...
 
ITStatus SDIO_GetITStatus (uint32_t SDIO_IT)
 Checks whether the specified SDIO interrupt has occurred or not. More...
 
void SDIO_ClearITPendingBit (uint32_t SDIO_IT)
 Clears the SDIO's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the SDIO firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__sdio_8h__dep__incl.map b/stm32f4xx__sdio_8h__dep__incl.map new file mode 100644 index 0000000..c22bd4c --- /dev/null +++ b/stm32f4xx__sdio_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__sdio_8h__dep__incl.md5 b/stm32f4xx__sdio_8h__dep__incl.md5 new file mode 100644 index 0000000..b3e8555 --- /dev/null +++ b/stm32f4xx__sdio_8h__dep__incl.md5 @@ -0,0 +1 @@ +a75809684f01c927092d6edd1556542c \ No newline at end of file diff --git a/stm32f4xx__sdio_8h__dep__incl.png b/stm32f4xx__sdio_8h__dep__incl.png new file mode 100644 index 0000000..7831ae0 Binary files /dev/null and b/stm32f4xx__sdio_8h__dep__incl.png differ diff --git a/stm32f4xx__sdio_8h__incl.map b/stm32f4xx__sdio_8h__incl.map new file mode 100644 index 0000000..b009ded --- /dev/null +++ b/stm32f4xx__sdio_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__sdio_8h__incl.md5 b/stm32f4xx__sdio_8h__incl.md5 new file mode 100644 index 0000000..b654955 --- /dev/null +++ b/stm32f4xx__sdio_8h__incl.md5 @@ -0,0 +1 @@ +485e186903fa6749284180175de827e8 \ No newline at end of file diff --git a/stm32f4xx__sdio_8h__incl.png b/stm32f4xx__sdio_8h__incl.png new file mode 100644 index 0000000..fe60c51 Binary files /dev/null and b/stm32f4xx__sdio_8h__incl.png differ diff --git a/stm32f4xx__sdio_8h_source.html b/stm32f4xx__sdio_8h_source.html new file mode 100644 index 0000000..69fc6b9 --- /dev/null +++ b/stm32f4xx__sdio_8h_source.html @@ -0,0 +1,465 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_sdio.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + + + +
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+ + +
+ +
+ + +
+
+
+
stm32f4xx_sdio.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_SDIO_H
+
31 #define __STM32F4xx_SDIO_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
50 typedef struct
+
51 {
+
52  uint32_t SDIO_ClockEdge;
+
55  uint32_t SDIO_ClockBypass;
+
59  uint32_t SDIO_ClockPowerSave;
+
63  uint32_t SDIO_BusWide;
+
66  uint32_t SDIO_HardwareFlowControl;
+
69  uint8_t SDIO_ClockDiv;
+
72 } SDIO_InitTypeDef;
+
73 
+
74 typedef struct
+
75 {
+
76  uint32_t SDIO_Argument;
+
81  uint32_t SDIO_CmdIndex;
+
83  uint32_t SDIO_Response;
+
86  uint32_t SDIO_Wait;
+
89  uint32_t SDIO_CPSM;
+
92 } SDIO_CmdInitTypeDef;
+
93 
+
94 typedef struct
+
95 {
+
96  uint32_t SDIO_DataTimeOut;
+
98  uint32_t SDIO_DataLength;
+
100  uint32_t SDIO_DataBlockSize;
+
103  uint32_t SDIO_TransferDir;
+
107  uint32_t SDIO_TransferMode;
+
110  uint32_t SDIO_DPSM;
+
113 } SDIO_DataInitTypeDef;
+
114 
+
115 
+
116 /* Exported constants --------------------------------------------------------*/
+
117 
+
126 #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+
127 #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
+
128 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+
129  ((EDGE) == SDIO_ClockEdge_Falling))
+
130 
+
138 #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+
139 #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
+
140 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+
141  ((BYPASS) == SDIO_ClockBypass_Enable))
+
142 
+
150 #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+
151 #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
+
152 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+
153  ((SAVE) == SDIO_ClockPowerSave_Enable))
+
154 
+
162 #define SDIO_BusWide_1b ((uint32_t)0x00000000)
+
163 #define SDIO_BusWide_4b ((uint32_t)0x00000800)
+
164 #define SDIO_BusWide_8b ((uint32_t)0x00001000)
+
165 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+
166  ((WIDE) == SDIO_BusWide_8b))
+
167 
+
176 #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+
177 #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
+
178 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+
179  ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+
180 
+
188 #define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+
189 #define SDIO_PowerState_ON ((uint32_t)0x00000003)
+
190 #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+
191 
+
200 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+
201 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+
202 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+
203 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+
204 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+
205 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+
206 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+
207 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+
208 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+
209 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+
210 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+
211 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+
212 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
+
213 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
+
214 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+
215 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+
216 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+
217 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+
218 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+
219 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+
220 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+
221 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+
222 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+
223 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+
224 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+
225 
+
233 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+
234 
+
242 #define SDIO_Response_No ((uint32_t)0x00000000)
+
243 #define SDIO_Response_Short ((uint32_t)0x00000040)
+
244 #define SDIO_Response_Long ((uint32_t)0x000000C0)
+
245 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+
246  ((RESPONSE) == SDIO_Response_Short) || \
+
247  ((RESPONSE) == SDIO_Response_Long))
+
248 
+
256 #define SDIO_Wait_No ((uint32_t)0x00000000)
+
257 #define SDIO_Wait_IT ((uint32_t)0x00000100)
+
258 #define SDIO_Wait_Pend ((uint32_t)0x00000200)
+
259 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+
260  ((WAIT) == SDIO_Wait_Pend))
+
261 
+
269 #define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+
270 #define SDIO_CPSM_Enable ((uint32_t)0x00000400)
+
271 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+
272 
+
280 #define SDIO_RESP1 ((uint32_t)0x00000000)
+
281 #define SDIO_RESP2 ((uint32_t)0x00000004)
+
282 #define SDIO_RESP3 ((uint32_t)0x00000008)
+
283 #define SDIO_RESP4 ((uint32_t)0x0000000C)
+
284 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+
285  ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+
286 
+
294 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+
295 
+
303 #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+
304 #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+
305 #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+
306 #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+
307 #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+
308 #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+
309 #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+
310 #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+
311 #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+
312 #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+
313 #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+
314 #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+
315 #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+
316 #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+
317 #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
+
318 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+
319  ((SIZE) == SDIO_DataBlockSize_2b) || \
+
320  ((SIZE) == SDIO_DataBlockSize_4b) || \
+
321  ((SIZE) == SDIO_DataBlockSize_8b) || \
+
322  ((SIZE) == SDIO_DataBlockSize_16b) || \
+
323  ((SIZE) == SDIO_DataBlockSize_32b) || \
+
324  ((SIZE) == SDIO_DataBlockSize_64b) || \
+
325  ((SIZE) == SDIO_DataBlockSize_128b) || \
+
326  ((SIZE) == SDIO_DataBlockSize_256b) || \
+
327  ((SIZE) == SDIO_DataBlockSize_512b) || \
+
328  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+
329  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+
330  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+
331  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+
332  ((SIZE) == SDIO_DataBlockSize_16384b))
+
333 
+
341 #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+
342 #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
+
343 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+
344  ((DIR) == SDIO_TransferDir_ToSDIO))
+
345 
+
353 #define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+
354 #define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
+
355 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+
356  ((MODE) == SDIO_TransferMode_Block))
+
357 
+
365 #define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+
366 #define SDIO_DPSM_Enable ((uint32_t)0x00000001)
+
367 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+
368 
+
376 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+
377 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+
378 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+
379 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+
380 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+
381 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+
382 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+
383 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+
384 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+
385 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+
386 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+
387 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+
388 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+
389 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+
390 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+
391 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+
392 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+
393 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+
394 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+
395 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+
396 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+
397 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+
398 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+
399 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+
400 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+
401  ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+
402  ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+
403  ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+
404  ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+
405  ((FLAG) == SDIO_FLAG_RXOVERR) || \
+
406  ((FLAG) == SDIO_FLAG_CMDREND) || \
+
407  ((FLAG) == SDIO_FLAG_CMDSENT) || \
+
408  ((FLAG) == SDIO_FLAG_DATAEND) || \
+
409  ((FLAG) == SDIO_FLAG_STBITERR) || \
+
410  ((FLAG) == SDIO_FLAG_DBCKEND) || \
+
411  ((FLAG) == SDIO_FLAG_CMDACT) || \
+
412  ((FLAG) == SDIO_FLAG_TXACT) || \
+
413  ((FLAG) == SDIO_FLAG_RXACT) || \
+
414  ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+
415  ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+
416  ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+
417  ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+
418  ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+
419  ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+
420  ((FLAG) == SDIO_FLAG_TXDAVL) || \
+
421  ((FLAG) == SDIO_FLAG_RXDAVL) || \
+
422  ((FLAG) == SDIO_FLAG_SDIOIT) || \
+
423  ((FLAG) == SDIO_FLAG_CEATAEND))
+
424 
+
425 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
426 
+
427 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+
428  ((IT) == SDIO_IT_DCRCFAIL) || \
+
429  ((IT) == SDIO_IT_CTIMEOUT) || \
+
430  ((IT) == SDIO_IT_DTIMEOUT) || \
+
431  ((IT) == SDIO_IT_TXUNDERR) || \
+
432  ((IT) == SDIO_IT_RXOVERR) || \
+
433  ((IT) == SDIO_IT_CMDREND) || \
+
434  ((IT) == SDIO_IT_CMDSENT) || \
+
435  ((IT) == SDIO_IT_DATAEND) || \
+
436  ((IT) == SDIO_IT_STBITERR) || \
+
437  ((IT) == SDIO_IT_DBCKEND) || \
+
438  ((IT) == SDIO_IT_CMDACT) || \
+
439  ((IT) == SDIO_IT_TXACT) || \
+
440  ((IT) == SDIO_IT_RXACT) || \
+
441  ((IT) == SDIO_IT_TXFIFOHE) || \
+
442  ((IT) == SDIO_IT_RXFIFOHF) || \
+
443  ((IT) == SDIO_IT_TXFIFOF) || \
+
444  ((IT) == SDIO_IT_RXFIFOF) || \
+
445  ((IT) == SDIO_IT_TXFIFOE) || \
+
446  ((IT) == SDIO_IT_RXFIFOE) || \
+
447  ((IT) == SDIO_IT_TXDAVL) || \
+
448  ((IT) == SDIO_IT_RXDAVL) || \
+
449  ((IT) == SDIO_IT_SDIOIT) || \
+
450  ((IT) == SDIO_IT_CEATAEND))
+
451 
+
452 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
453 
+
462 #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
+
463 #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
+
464 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+
465  ((MODE) == SDIO_ReadWaitMode_DATA2))
+
466 
+
474 /* Exported macro ------------------------------------------------------------*/
+
475 /* Exported functions --------------------------------------------------------*/
+
476 /* Function used to set the SDIO configuration to the default reset state ****/
+
477 void SDIO_DeInit(void);
+
478 
+
479 /* Initialization and Configuration functions *********************************/
+
480 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+
481 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+
482 void SDIO_ClockCmd(FunctionalState NewState);
+
483 void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+
484 uint32_t SDIO_GetPowerState(void);
+
485 
+
486 /* Command path state machine (CPSM) management functions *********************/
+
487 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+
488 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+
489 uint8_t SDIO_GetCommandResponse(void);
+
490 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
491 
+
492 /* Data path state machine (DPSM) management functions ************************/
+
493 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+
494 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+
495 uint32_t SDIO_GetDataCounter(void);
+
496 uint32_t SDIO_ReadData(void);
+
497 void SDIO_WriteData(uint32_t Data);
+
498 uint32_t SDIO_GetFIFOCount(void);
+
499 
+
500 /* SDIO IO Cards mode management functions ************************************/
+
501 void SDIO_StartSDIOReadWait(FunctionalState NewState);
+
502 void SDIO_StopSDIOReadWait(FunctionalState NewState);
+
503 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+
504 void SDIO_SetSDIOOperation(FunctionalState NewState);
+
505 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+
506 
+
507 /* CE-ATA mode management functions *******************************************/
+
508 void SDIO_CommandCompletionCmd(FunctionalState NewState);
+
509 void SDIO_CEATAITCmd(FunctionalState NewState);
+
510 void SDIO_SendCEATACmd(FunctionalState NewState);
+
511 
+
512 /* DMA transfers management functions *****************************************/
+
513 void SDIO_DMACmd(FunctionalState NewState);
+
514 
+
515 /* Interrupts and flags management functions **********************************/
+
516 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+
517 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+
518 void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+
519 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+
520 void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
521 
+
522 #ifdef __cplusplus
+
523 }
+
524 #endif
+
525 
+
526 #endif /* __STM32F4xx_SDIO_H */
+
527 
+
536 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
SDIO_CmdInitTypeDef
Definition: stm32f4xx_sdio.h:74
+
SDIO_ClearITPendingBit
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
Clears the SDIO's interrupt pending bits.
Definition: stm32f4xx_sdio.c:987
+
SDIO_DataInitTypeDef::SDIO_DataLength
uint32_t SDIO_DataLength
Definition: stm32f4xx_sdio.h:98
+
SDIO_DataInitTypeDef::SDIO_TransferDir
uint32_t SDIO_TransferDir
Definition: stm32f4xx_sdio.h:103
+
SDIO_StopSDIOReadWait
void SDIO_StopSDIOReadWait(FunctionalState NewState)
Stops the SD I/O Read Wait operation.
Definition: stm32f4xx_sdio.c:633
+
SDIO_StructInit
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
Fills each SDIO_InitStruct member with its default value.
Definition: stm32f4xx_sdio.c:317
+
SDIO_DataInitTypeDef::SDIO_TransferMode
uint32_t SDIO_TransferMode
Definition: stm32f4xx_sdio.h:107
+
SDIO_ITConfig
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
Enables or disables the SDIO interrupts.
Definition: stm32f4xx_sdio.c:827
+
SDIO_GetFIFOCount
uint32_t SDIO_GetFIFOCount(void)
Returns the number of words left to be written to or read from FIFO.
Definition: stm32f4xx_sdio.c:590
+
SDIO_CmdStructInit
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Fills each SDIO_CmdInitStruct member with its default value.
Definition: stm32f4xx_sdio.c:435
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
SDIO_CmdInitTypeDef::SDIO_Response
uint32_t SDIO_Response
Definition: stm32f4xx_sdio.h:83
+
SDIO_InitTypeDef::SDIO_ClockPowerSave
uint32_t SDIO_ClockPowerSave
Definition: stm32f4xx_sdio.h:59
+
SDIO_InitTypeDef::SDIO_ClockBypass
uint32_t SDIO_ClockBypass
Definition: stm32f4xx_sdio.h:55
+
SDIO_Init
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct.
Definition: stm32f4xx_sdio.c:279
+
SDIO_SendSDIOSuspendCmd
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
Enables or disables the SD I/O Mode suspend command sending.
Definition: stm32f4xx_sdio.c:677
+
SDIO_InitTypeDef::SDIO_ClockDiv
uint8_t SDIO_ClockDiv
Definition: stm32f4xx_sdio.h:69
+
SDIO_ClearFlag
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
Clears the SDIO's pending flags.
Definition: stm32f4xx_sdio.c:912
+
SDIO_InitTypeDef::SDIO_BusWide
uint32_t SDIO_BusWide
Definition: stm32f4xx_sdio.h:63
+
SDIO_GetResponse
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
Returns response received from the card for the last command.
Definition: stm32f4xx_sdio.c:465
+
SDIO_GetITStatus
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
Checks whether the specified SDIO interrupt has occurred or not.
Definition: stm32f4xx_sdio.c:951
+
SDIO_GetDataCounter
uint32_t SDIO_GetDataCounter(void)
Returns number of remaining data bytes to be transferred.
Definition: stm32f4xx_sdio.c:560
+
SDIO_DataInitTypeDef::SDIO_DPSM
uint32_t SDIO_DPSM
Definition: stm32f4xx_sdio.h:110
+
SDIO_SendCommand
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send...
Definition: stm32f4xx_sdio.c:399
+
SDIO_DeInit
void SDIO_DeInit(void)
Deinitializes the SDIO peripheral registers to their default reset values.
Definition: stm32f4xx_sdio.c:266
+
SDIO_GetFlagStatus
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
Checks whether the specified SDIO flag is set or not.
Definition: stm32f4xx_sdio.c:875
+
SDIO_CmdInitTypeDef::SDIO_Argument
uint32_t SDIO_Argument
Definition: stm32f4xx_sdio.h:76
+
SDIO_DataConfig
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct.
Definition: stm32f4xx_sdio.c:503
+
SDIO_ReadData
uint32_t SDIO_ReadData(void)
Read one data word from Rx FIFO.
Definition: stm32f4xx_sdio.c:570
+
SDIO_StartSDIOReadWait
void SDIO_StartSDIOReadWait(FunctionalState NewState)
Starts the SD I/O Read Wait operation.
Definition: stm32f4xx_sdio.c:619
+
SDIO_CmdInitTypeDef::SDIO_CmdIndex
uint32_t SDIO_CmdIndex
Definition: stm32f4xx_sdio.h:81
+
SDIO_WriteData
void SDIO_WriteData(uint32_t Data)
Write one data word to Tx FIFO.
Definition: stm32f4xx_sdio.c:580
+
SDIO_DataInitTypeDef::SDIO_DataTimeOut
uint32_t SDIO_DataTimeOut
Definition: stm32f4xx_sdio.h:96
+
SDIO_SendCEATACmd
void SDIO_SendCEATACmd(FunctionalState NewState)
Sends CE-ATA command (CMD61).
Definition: stm32f4xx_sdio.c:737
+
SDIO_GetPowerState
uint32_t SDIO_GetPowerState(void)
Gets the power status of the controller.
Definition: stm32f4xx_sdio.c:367
+
SDIO_SetPowerState
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
Sets the power status of the controller.
Definition: stm32f4xx_sdio.c:350
+
SDIO_CmdInitTypeDef::SDIO_CPSM
uint32_t SDIO_CPSM
Definition: stm32f4xx_sdio.h:89
+
SDIO_CmdInitTypeDef::SDIO_Wait
uint32_t SDIO_Wait
Definition: stm32f4xx_sdio.h:86
+
SDIO_GetCommandResponse
uint8_t SDIO_GetCommandResponse(void)
Returns command index of last command for which response received.
Definition: stm32f4xx_sdio.c:450
+
SDIO_DataStructInit
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
Fills each SDIO_DataInitStruct member with its default value.
Definition: stm32f4xx_sdio.c:544
+
SDIO_InitTypeDef
Definition: stm32f4xx_sdio.h:50
+
SDIO_InitTypeDef::SDIO_HardwareFlowControl
uint32_t SDIO_HardwareFlowControl
Definition: stm32f4xx_sdio.h:66
+
SDIO_CommandCompletionCmd
void SDIO_CommandCompletionCmd(FunctionalState NewState)
Enables or disables the command completion signal.
Definition: stm32f4xx_sdio.c:709
+
SDIO_CEATAITCmd
void SDIO_CEATAITCmd(FunctionalState NewState)
Enables or disables the CE-ATA interrupt.
Definition: stm32f4xx_sdio.c:723
+
SDIO_DMACmd
void SDIO_DMACmd(FunctionalState NewState)
Enables or disables the SDIO DMA request.
Definition: stm32f4xx_sdio.c:769
+
SDIO_ClockCmd
void SDIO_ClockCmd(FunctionalState NewState)
Enables or disables the SDIO Clock.
Definition: stm32f4xx_sdio.c:334
+
SDIO_SetSDIOOperation
void SDIO_SetSDIOOperation(FunctionalState NewState)
Enables or disables the SD I/O Mode Operation.
Definition: stm32f4xx_sdio.c:663
+
SDIO_InitTypeDef::SDIO_ClockEdge
uint32_t SDIO_ClockEdge
Definition: stm32f4xx_sdio.h:52
+
SDIO_DataInitTypeDef
Definition: stm32f4xx_sdio.h:94
+
SDIO_DataInitTypeDef::SDIO_DataBlockSize
uint32_t SDIO_DataBlockSize
Definition: stm32f4xx_sdio.h:100
+
SDIO_SetSDIOReadWaitMode
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
Sets one of the two options of inserting read wait interval.
Definition: stm32f4xx_sdio.c:649
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__spi_8c.html b/stm32f4xx__spi_8c.html new file mode 100644 index 0000000..d69e095 --- /dev/null +++ b/stm32f4xx__spi_8c.html @@ -0,0 +1,359 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_spi.c File Reference + + + + + + + + + + +
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+Macros | +Functions
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+
stm32f4xx_spi.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI): +More...

+
#include "stm32f4xx_spi.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_spi.c:
+
+
+ + +
+
+ + + + + + + + + + + + + +

+Macros

+#define CR1_CLEAR_MASK   ((uint16_t)0x3040)
 
+#define I2SCFGR_CLEAR_MASK   ((uint16_t)0xF040)
 
+#define PLLCFGR_PPLR_MASK   ((uint32_t)0x70000000)
 
+#define PLLCFGR_PPLN_MASK   ((uint32_t)0x00007FC0)
 
+#define SPI_CR2_FRF   ((uint16_t)0x0010)
 
+#define SPI_SR_TIFRFE   ((uint16_t)0x0100)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SPI_I2S_DeInit (SPI_TypeDef *SPIx)
 De-initialize the SPIx peripheral registers to their default reset values. More...
 
void SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct. More...
 
void I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
 Fills each SPI_InitStruct member with its default value. More...
 
void I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
 Fills each I2S_InitStruct member with its default value. More...
 
void SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral. More...
 
void I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral (in I2S mode). More...
 
void SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
 Configures the data size for the selected SPI. More...
 
void SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
 Selects the data transfer direction in bidirectional mode for the specified SPI. More...
 
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
 Configures internally by software the NSS pin for the selected SPI. More...
 
void SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SS output for the selected SPI. More...
 
void SPI_TIModeCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void I2S_FullDuplexConfig (SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
 Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct. More...
 
uint16_t SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
 Returns the most recent received data by the SPIx/I2Sx peripheral. More...
 
void SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
 Transmits a Data through the SPIx/I2Sx peripheral. More...
 
void SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the CRC value calculation of the transferred bytes. More...
 
void SPI_TransmitCRC (SPI_TypeDef *SPIx)
 Transmit the SPIx CRC value. More...
 
uint16_t SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
 Returns the transmit or the receive CRC register value for the specified SPI. More...
 
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
 Returns the CRC Polynomial register value for the specified SPI. More...
 
void SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
 Enables or disables the specified SPI/I2S interrupts. More...
 
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Checks whether the specified SPIx/I2Sx flag is set or not. More...
 
void SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Clears the SPIx CRC Error (CRCERR) flag. More...
 
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Checks whether the specified SPIx/I2Sx interrupt has occurred or not. More...
 
void SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Clears the SPIx CRC Error (CRCERR) interrupt pending bit. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Serial peripheral interface (SPI):

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Data transfers functions
    • +
  • Hardware CRC Calculation
    • +
  • DMA transfers management
    • +
  • Interrupts and flags management
    • +
+
+
 ===================================================================
+                  ##### How to use this driver #####
+ ===================================================================
+ [..]
+   (#) Enable peripheral clock using the following functions 
+       RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
+       RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
+       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3
+       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4
+       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5
+       RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6.
+  
+   (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
+       function. In I2S mode, if an external clock source is used then the I2S 
+       CKIN pin GPIO clock should also be enabled.
+  
+   (#) Peripherals alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate Function (AF) 
+            using GPIO_PinAFConfig() function
+       (++) Configure the desired pin in alternate function by: 
+            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, 
+            GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function In I2S mode, if an external clock source is 
+            used then the I2S CKIN pin should be also configured in Alternate 
+            function Push-pull pull-up mode. 
+          
+   (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+       Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+       function.
+       In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio 
+       frequency and Polarity using I2S_Init() function. For I2S mode, make sure 
+       that either:
+       (++) I2S PLL is configured using the functions 
+            RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and 
+            RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or 
+       (++) External clock source is configured using the function 
+            RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly 
+            the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. 
+  
+   (#) Enable the NVIC and the corresponding interrupt using the function 
+       SPI_ITConfig() if you need to use interrupt mode. 
+  
+   (#) When using the DMA mode 
+       (++) Configure the DMA using DMA_Init() function
+       (++) Active the needed channel Request using SPI_I2S_DMACmd() function
+   
+   (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
+       I2S_Cmd().
+   
+   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  
+   (#) Optionally, you can enable/configure the following parameters without
+       re-initialization (i.e there is no need to call again SPI_Init() function):
+       (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+            is programmed as Data direction parameter using the SPI_Init() function
+            it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
+            using the SPI_BiDirectionalLineConfig() function.
+       (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
+            using the SPI_Init() function it can be possible to manage the 
+            NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+       (++) Reconfigure the data size using the SPI_DataSizeConfig() function  
+       (++) Enable or disable the SS output using the SPI_SSOutputCmd() function  
+            
+    (#) To use the CRC Hardware calculation feature refer to the Peripheral 
+        CRC hardware Calculation subsection.
+     
+  
+ [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI 
+      peripheral is able to manage sending and receiving data simultaneously
+      using two data lines. Each SPI peripheral has an extended block called I2Sxext
+      (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+      The extension block is not a full SPI IP, it is used only as I2S slave to
+      implement full duplex mode. The extension block uses the same clock sources
+      as its master.          
+      To configure I2S full duplex you have to:
+              
+      (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. 
+             
+      (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to  
+          I2S_Init() function.
+              
+      (#) Call I2S_Cmd() for SPIx then for its extended block.
+            
+      (#) To configure interrupts or DMA requests and to get/clear flag status, 
+          use I2Sxext instance for the extension block.
+               
+ [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), 
+      I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), 
+      SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), 
+      SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
+                   
+      Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
+              
+      RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);   
+      I2S_StructInit(&I2SInitStruct);
+      I2SInitStruct.Mode = I2S_Mode_MasterTx;     
+      I2S_Init(SPI3, &I2SInitStruct);
+      I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
+      I2S_Cmd(SPI3, ENABLE);
+      I2S_Cmd(SPI3ext, ENABLE);
+      ...
+      while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+      {}
+      SPI_I2S_SendData(SPI3, txdata[i]);
+      ...  
+      while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
+      {}
+      rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
+      ...          
+                
+ [..]       
+   (@) In I2S mode: if an external clock is used as source clock for the I2S,  
+       then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should 
+       be enabled and set to the value of the source clock frequency (in Hz).
+   
+   (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() 
+       just after calling the function SPI_Init().
@attention
+
+<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+
+Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+You may not use this file except in compliance with the License.
+You may obtain a copy of the License at:
+
+       http://www.st.com/software_license_agreement_liberty_v2
+
+Unless required by applicable law or agreed to in writing, software 
+distributed under the License is distributed on an "AS IS" BASIS, 
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__spi_8c__incl.map b/stm32f4xx__spi_8c__incl.map new file mode 100644 index 0000000..2a7a5b4 --- /dev/null +++ b/stm32f4xx__spi_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__spi_8c__incl.md5 b/stm32f4xx__spi_8c__incl.md5 new file mode 100644 index 0000000..56245d4 --- /dev/null +++ b/stm32f4xx__spi_8c__incl.md5 @@ -0,0 +1 @@ +fbf4a6d20fc4c249ff6945ae13f191a9 \ No newline at end of file diff --git a/stm32f4xx__spi_8c__incl.png b/stm32f4xx__spi_8c__incl.png new file mode 100644 index 0000000..bad8583 Binary files /dev/null and b/stm32f4xx__spi_8c__incl.png differ diff --git a/stm32f4xx__spi_8h.html b/stm32f4xx__spi_8h.html new file mode 100644 index 0000000..f0f0e9a --- /dev/null +++ b/stm32f4xx__spi_8h.html @@ -0,0 +1,573 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_spi.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Functions
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+
stm32f4xx_spi.h File Reference
+
+
+ +

This file contains all the functions prototypes for the SPI firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_spi.h:
+
+
+ + +
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

+ + + + + + + + +

+Classes

struct  SPI_InitTypeDef
 SPI Init structure definition. More...
 
struct  I2S_InitTypeDef
 I2S Init structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_SPI_ALL_PERIPH(PERIPH)
 
#define IS_SPI_ALL_PERIPH_EXT(PERIPH)
 
#define IS_SPI_23_PERIPH(PERIPH)
 
#define IS_SPI_23_PERIPH_EXT(PERIPH)
 
#define IS_I2S_EXT_PERIPH(PERIPH)
 
+#define SPI_Direction_2Lines_FullDuplex   ((uint16_t)0x0000)
 
+#define SPI_Direction_2Lines_RxOnly   ((uint16_t)0x0400)
 
+#define SPI_Direction_1Line_Rx   ((uint16_t)0x8000)
 
+#define SPI_Direction_1Line_Tx   ((uint16_t)0xC000)
 
#define IS_SPI_DIRECTION_MODE(MODE)
 
+#define SPI_Mode_Master   ((uint16_t)0x0104)
 
+#define SPI_Mode_Slave   ((uint16_t)0x0000)
 
#define IS_SPI_MODE(MODE)
 
+#define SPI_DataSize_16b   ((uint16_t)0x0800)
 
+#define SPI_DataSize_8b   ((uint16_t)0x0000)
 
#define IS_SPI_DATASIZE(DATASIZE)
 
+#define SPI_CPOL_Low   ((uint16_t)0x0000)
 
+#define SPI_CPOL_High   ((uint16_t)0x0002)
 
#define IS_SPI_CPOL(CPOL)
 
+#define SPI_CPHA_1Edge   ((uint16_t)0x0000)
 
+#define SPI_CPHA_2Edge   ((uint16_t)0x0001)
 
#define IS_SPI_CPHA(CPHA)
 
+#define SPI_NSS_Soft   ((uint16_t)0x0200)
 
+#define SPI_NSS_Hard   ((uint16_t)0x0000)
 
#define IS_SPI_NSS(NSS)
 
+#define SPI_BaudRatePrescaler_2   ((uint16_t)0x0000)
 
+#define SPI_BaudRatePrescaler_4   ((uint16_t)0x0008)
 
+#define SPI_BaudRatePrescaler_8   ((uint16_t)0x0010)
 
+#define SPI_BaudRatePrescaler_16   ((uint16_t)0x0018)
 
+#define SPI_BaudRatePrescaler_32   ((uint16_t)0x0020)
 
+#define SPI_BaudRatePrescaler_64   ((uint16_t)0x0028)
 
+#define SPI_BaudRatePrescaler_128   ((uint16_t)0x0030)
 
+#define SPI_BaudRatePrescaler_256   ((uint16_t)0x0038)
 
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
 
+#define SPI_FirstBit_MSB   ((uint16_t)0x0000)
 
+#define SPI_FirstBit_LSB   ((uint16_t)0x0080)
 
#define IS_SPI_FIRST_BIT(BIT)
 
+#define I2S_Mode_SlaveTx   ((uint16_t)0x0000)
 
+#define I2S_Mode_SlaveRx   ((uint16_t)0x0100)
 
+#define I2S_Mode_MasterTx   ((uint16_t)0x0200)
 
+#define I2S_Mode_MasterRx   ((uint16_t)0x0300)
 
#define IS_I2S_MODE(MODE)
 
+#define I2S_Standard_Phillips   ((uint16_t)0x0000)
 
+#define I2S_Standard_MSB   ((uint16_t)0x0010)
 
+#define I2S_Standard_LSB   ((uint16_t)0x0020)
 
+#define I2S_Standard_PCMShort   ((uint16_t)0x0030)
 
+#define I2S_Standard_PCMLong   ((uint16_t)0x00B0)
 
#define IS_I2S_STANDARD(STANDARD)
 
+#define I2S_DataFormat_16b   ((uint16_t)0x0000)
 
+#define I2S_DataFormat_16bextended   ((uint16_t)0x0001)
 
+#define I2S_DataFormat_24b   ((uint16_t)0x0003)
 
+#define I2S_DataFormat_32b   ((uint16_t)0x0005)
 
#define IS_I2S_DATA_FORMAT(FORMAT)
 
+#define I2S_MCLKOutput_Enable   ((uint16_t)0x0200)
 
+#define I2S_MCLKOutput_Disable   ((uint16_t)0x0000)
 
#define IS_I2S_MCLK_OUTPUT(OUTPUT)
 
+#define I2S_AudioFreq_192k   ((uint32_t)192000)
 
+#define I2S_AudioFreq_96k   ((uint32_t)96000)
 
+#define I2S_AudioFreq_48k   ((uint32_t)48000)
 
+#define I2S_AudioFreq_44k   ((uint32_t)44100)
 
+#define I2S_AudioFreq_32k   ((uint32_t)32000)
 
+#define I2S_AudioFreq_22k   ((uint32_t)22050)
 
+#define I2S_AudioFreq_16k   ((uint32_t)16000)
 
+#define I2S_AudioFreq_11k   ((uint32_t)11025)
 
+#define I2S_AudioFreq_8k   ((uint32_t)8000)
 
+#define I2S_AudioFreq_Default   ((uint32_t)2)
 
#define IS_I2S_AUDIO_FREQ(FREQ)
 
+#define I2S_CPOL_Low   ((uint16_t)0x0000)
 
+#define I2S_CPOL_High   ((uint16_t)0x0008)
 
#define IS_I2S_CPOL(CPOL)
 
+#define SPI_I2S_DMAReq_Tx   ((uint16_t)0x0002)
 
+#define SPI_I2S_DMAReq_Rx   ((uint16_t)0x0001)
 
+#define IS_SPI_I2S_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
 
+#define SPI_NSSInternalSoft_Set   ((uint16_t)0x0100)
 
+#define SPI_NSSInternalSoft_Reset   ((uint16_t)0xFEFF)
 
#define IS_SPI_NSS_INTERNAL(INTERNAL)
 
+#define SPI_CRC_Tx   ((uint8_t)0x00)
 
+#define SPI_CRC_Rx   ((uint8_t)0x01)
 
+#define IS_SPI_CRC(CRC)   (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
 
+#define SPI_Direction_Rx   ((uint16_t)0xBFFF)
 
+#define SPI_Direction_Tx   ((uint16_t)0x4000)
 
#define IS_SPI_DIRECTION(DIRECTION)
 
+#define SPI_I2S_IT_TXE   ((uint8_t)0x71)
 
+#define SPI_I2S_IT_RXNE   ((uint8_t)0x60)
 
+#define SPI_I2S_IT_ERR   ((uint8_t)0x50)
 
+#define I2S_IT_UDR   ((uint8_t)0x53)
 
+#define SPI_I2S_IT_TIFRFE   ((uint8_t)0x58)
 
#define IS_SPI_I2S_CONFIG_IT(IT)
 
+#define SPI_I2S_IT_OVR   ((uint8_t)0x56)
 
+#define SPI_IT_MODF   ((uint8_t)0x55)
 
+#define SPI_IT_CRCERR   ((uint8_t)0x54)
 
+#define IS_SPI_I2S_CLEAR_IT(IT)   (((IT) == SPI_IT_CRCERR))
 
#define IS_SPI_I2S_GET_IT(IT)
 
+#define SPI_I2S_FLAG_RXNE   ((uint16_t)0x0001)
 
+#define SPI_I2S_FLAG_TXE   ((uint16_t)0x0002)
 
+#define I2S_FLAG_CHSIDE   ((uint16_t)0x0004)
 
+#define I2S_FLAG_UDR   ((uint16_t)0x0008)
 
+#define SPI_FLAG_CRCERR   ((uint16_t)0x0010)
 
+#define SPI_FLAG_MODF   ((uint16_t)0x0020)
 
+#define SPI_I2S_FLAG_OVR   ((uint16_t)0x0040)
 
+#define SPI_I2S_FLAG_BSY   ((uint16_t)0x0080)
 
+#define SPI_I2S_FLAG_TIFRFE   ((uint16_t)0x0100)
 
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG)   (((FLAG) == SPI_FLAG_CRCERR))
 
#define IS_SPI_I2S_GET_FLAG(FLAG)
 
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)   ((POLYNOMIAL) >= 0x1)
 
+#define SPI_DMAReq_Tx   SPI_I2S_DMAReq_Tx
 
+#define SPI_DMAReq_Rx   SPI_I2S_DMAReq_Rx
 
+#define SPI_IT_TXE   SPI_I2S_IT_TXE
 
+#define SPI_IT_RXNE   SPI_I2S_IT_RXNE
 
+#define SPI_IT_ERR   SPI_I2S_IT_ERR
 
+#define SPI_IT_OVR   SPI_I2S_IT_OVR
 
+#define SPI_FLAG_RXNE   SPI_I2S_FLAG_RXNE
 
+#define SPI_FLAG_TXE   SPI_I2S_FLAG_TXE
 
+#define SPI_FLAG_OVR   SPI_I2S_FLAG_OVR
 
+#define SPI_FLAG_BSY   SPI_I2S_FLAG_BSY
 
+#define SPI_DeInit   SPI_I2S_DeInit
 
+#define SPI_ITConfig   SPI_I2S_ITConfig
 
+#define SPI_DMACmd   SPI_I2S_DMACmd
 
+#define SPI_SendData   SPI_I2S_SendData
 
+#define SPI_ReceiveData   SPI_I2S_ReceiveData
 
+#define SPI_GetFlagStatus   SPI_I2S_GetFlagStatus
 
+#define SPI_ClearFlag   SPI_I2S_ClearFlag
 
+#define SPI_GetITStatus   SPI_I2S_GetITStatus
 
+#define SPI_ClearITPendingBit   SPI_I2S_ClearITPendingBit
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SPI_I2S_DeInit (SPI_TypeDef *SPIx)
 De-initialize the SPIx peripheral registers to their default reset values. More...
 
void SPI_Init (SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct. More...
 
void I2S_Init (SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
 Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_StructInit (SPI_InitTypeDef *SPI_InitStruct)
 Fills each SPI_InitStruct member with its default value. More...
 
void I2S_StructInit (I2S_InitTypeDef *I2S_InitStruct)
 Fills each I2S_InitStruct member with its default value. More...
 
void SPI_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral. More...
 
void I2S_Cmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the specified SPI peripheral (in I2S mode). More...
 
void SPI_DataSizeConfig (SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
 Configures the data size for the selected SPI. More...
 
void SPI_BiDirectionalLineConfig (SPI_TypeDef *SPIx, uint16_t SPI_Direction)
 Selects the data transfer direction in bidirectional mode for the specified SPI. More...
 
void SPI_NSSInternalSoftwareConfig (SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
 Configures internally by software the NSS pin for the selected SPI. More...
 
void SPI_SSOutputCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SS output for the selected SPI. More...
 
void SPI_TIModeCmd (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void I2S_FullDuplexConfig (SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
 Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the specified parameters in the I2S_InitStruct. More...
 
void SPI_I2S_SendData (SPI_TypeDef *SPIx, uint16_t Data)
 Transmits a Data through the SPIx/I2Sx peripheral. More...
 
uint16_t SPI_I2S_ReceiveData (SPI_TypeDef *SPIx)
 Returns the most recent received data by the SPIx/I2Sx peripheral. More...
 
void SPI_CalculateCRC (SPI_TypeDef *SPIx, FunctionalState NewState)
 Enables or disables the CRC value calculation of the transferred bytes. More...
 
void SPI_TransmitCRC (SPI_TypeDef *SPIx)
 Transmit the SPIx CRC value. More...
 
uint16_t SPI_GetCRC (SPI_TypeDef *SPIx, uint8_t SPI_CRC)
 Returns the transmit or the receive CRC register value for the specified SPI. More...
 
uint16_t SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
 Returns the CRC Polynomial register value for the specified SPI. More...
 
void SPI_I2S_DMACmd (SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
 Enables or disables the SPIx/I2Sx DMA interface. More...
 
void SPI_I2S_ITConfig (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
 Enables or disables the specified SPI/I2S interrupts. More...
 
FlagStatus SPI_I2S_GetFlagStatus (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Checks whether the specified SPIx/I2Sx flag is set or not. More...
 
void SPI_I2S_ClearFlag (SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
 Clears the SPIx CRC Error (CRCERR) flag. More...
 
ITStatus SPI_I2S_GetITStatus (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Checks whether the specified SPIx/I2Sx interrupt has occurred or not. More...
 
void SPI_I2S_ClearITPendingBit (SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
 Clears the SPIx CRC Error (CRCERR) interrupt pending bit. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the SPI firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__spi_8h__dep__incl.map b/stm32f4xx__spi_8h__dep__incl.map new file mode 100644 index 0000000..f877c48 --- /dev/null +++ b/stm32f4xx__spi_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__spi_8h__dep__incl.md5 b/stm32f4xx__spi_8h__dep__incl.md5 new file mode 100644 index 0000000..5ab631d --- /dev/null +++ b/stm32f4xx__spi_8h__dep__incl.md5 @@ -0,0 +1 @@ +015199bfe46edd8b611d07628fbb0edb \ No newline at end of file diff --git a/stm32f4xx__spi_8h__dep__incl.png b/stm32f4xx__spi_8h__dep__incl.png new file mode 100644 index 0000000..f1a86d3 Binary files /dev/null and b/stm32f4xx__spi_8h__dep__incl.png differ diff --git a/stm32f4xx__spi_8h__incl.map b/stm32f4xx__spi_8h__incl.map new file mode 100644 index 0000000..0cabe69 --- /dev/null +++ b/stm32f4xx__spi_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__spi_8h__incl.md5 b/stm32f4xx__spi_8h__incl.md5 new file mode 100644 index 0000000..d811c6f --- /dev/null +++ b/stm32f4xx__spi_8h__incl.md5 @@ -0,0 +1 @@ +33d0ea9dda7b2fa289ef8c8f30046f69 \ No newline at end of file diff --git a/stm32f4xx__spi_8h__incl.png b/stm32f4xx__spi_8h__incl.png new file mode 100644 index 0000000..2f6d05d Binary files /dev/null and b/stm32f4xx__spi_8h__incl.png differ diff --git a/stm32f4xx__spi_8h_source.html b/stm32f4xx__spi_8h_source.html new file mode 100644 index 0000000..fa9614a --- /dev/null +++ b/stm32f4xx__spi_8h_source.html @@ -0,0 +1,449 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_spi.h Source File + + + + + + + + + + +
+
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+
discoverpixy +
+
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+ + + + + + +
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+ + +
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+
+
stm32f4xx_spi.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_SPI_H
+
31 #define __STM32F4xx_SPI_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint16_t SPI_Direction;
+
59  uint16_t SPI_Mode;
+
62  uint16_t SPI_DataSize;
+
65  uint16_t SPI_CPOL;
+
68  uint16_t SPI_CPHA;
+
71  uint16_t SPI_NSS;
+
75  uint16_t SPI_BaudRatePrescaler;
+
81  uint16_t SPI_FirstBit;
+
84  uint16_t SPI_CRCPolynomial;
+
85 }SPI_InitTypeDef;
+
86 
+
91 typedef struct
+
92 {
+
93 
+
94  uint16_t I2S_Mode;
+
97  uint16_t I2S_Standard;
+
100  uint16_t I2S_DataFormat;
+
103  uint16_t I2S_MCLKOutput;
+
106  uint32_t I2S_AudioFreq;
+
109  uint16_t I2S_CPOL;
+
111 }I2S_InitTypeDef;
+
112 
+
113 /* Exported constants --------------------------------------------------------*/
+
114 
+
119 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+
120  ((PERIPH) == SPI2) || \
+
121  ((PERIPH) == SPI3) || \
+
122  ((PERIPH) == SPI4) || \
+
123  ((PERIPH) == SPI5) || \
+
124  ((PERIPH) == SPI6))
+
125 
+
126 #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
+
127  ((PERIPH) == SPI2) || \
+
128  ((PERIPH) == SPI3) || \
+
129  ((PERIPH) == SPI4) || \
+
130  ((PERIPH) == SPI5) || \
+
131  ((PERIPH) == SPI6) || \
+
132  ((PERIPH) == I2S2ext) || \
+
133  ((PERIPH) == I2S3ext))
+
134 
+
135 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+
136  ((PERIPH) == SPI3))
+
137 
+
138 #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
+
139  ((PERIPH) == SPI3) || \
+
140  ((PERIPH) == I2S2ext) || \
+
141  ((PERIPH) == I2S3ext))
+
142 
+
143 #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
+
144  ((PERIPH) == I2S3ext))
+
145 
+
146 
+
151 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+
152 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+
153 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+
154 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+
155 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+
156  ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+
157  ((MODE) == SPI_Direction_1Line_Rx) || \
+
158  ((MODE) == SPI_Direction_1Line_Tx))
+
159 
+
167 #define SPI_Mode_Master ((uint16_t)0x0104)
+
168 #define SPI_Mode_Slave ((uint16_t)0x0000)
+
169 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+
170  ((MODE) == SPI_Mode_Slave))
+
171 
+
179 #define SPI_DataSize_16b ((uint16_t)0x0800)
+
180 #define SPI_DataSize_8b ((uint16_t)0x0000)
+
181 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+
182  ((DATASIZE) == SPI_DataSize_8b))
+
183 
+
191 #define SPI_CPOL_Low ((uint16_t)0x0000)
+
192 #define SPI_CPOL_High ((uint16_t)0x0002)
+
193 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+
194  ((CPOL) == SPI_CPOL_High))
+
195 
+
203 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
+
204 #define SPI_CPHA_2Edge ((uint16_t)0x0001)
+
205 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+
206  ((CPHA) == SPI_CPHA_2Edge))
+
207 
+
215 #define SPI_NSS_Soft ((uint16_t)0x0200)
+
216 #define SPI_NSS_Hard ((uint16_t)0x0000)
+
217 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+
218  ((NSS) == SPI_NSS_Hard))
+
219 
+
227 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+
228 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+
229 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+
230 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+
231 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+
232 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+
233 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+
234 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+
235 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+
236  ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+
237  ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+
238  ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+
239  ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+
240  ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+
241  ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+
242  ((PRESCALER) == SPI_BaudRatePrescaler_256))
+
243 
+
251 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
+
252 #define SPI_FirstBit_LSB ((uint16_t)0x0080)
+
253 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+
254  ((BIT) == SPI_FirstBit_LSB))
+
255 
+
263 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+
264 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+
265 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
+
266 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
+
267 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+
268  ((MODE) == I2S_Mode_SlaveRx) || \
+
269  ((MODE) == I2S_Mode_MasterTx)|| \
+
270  ((MODE) == I2S_Mode_MasterRx))
+
271 
+
280 #define I2S_Standard_Phillips ((uint16_t)0x0000)
+
281 #define I2S_Standard_MSB ((uint16_t)0x0010)
+
282 #define I2S_Standard_LSB ((uint16_t)0x0020)
+
283 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
+
284 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+
285 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+
286  ((STANDARD) == I2S_Standard_MSB) || \
+
287  ((STANDARD) == I2S_Standard_LSB) || \
+
288  ((STANDARD) == I2S_Standard_PCMShort) || \
+
289  ((STANDARD) == I2S_Standard_PCMLong))
+
290 
+
298 #define I2S_DataFormat_16b ((uint16_t)0x0000)
+
299 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+
300 #define I2S_DataFormat_24b ((uint16_t)0x0003)
+
301 #define I2S_DataFormat_32b ((uint16_t)0x0005)
+
302 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+
303  ((FORMAT) == I2S_DataFormat_16bextended) || \
+
304  ((FORMAT) == I2S_DataFormat_24b) || \
+
305  ((FORMAT) == I2S_DataFormat_32b))
+
306 
+
314 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+
315 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+
316 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+
317  ((OUTPUT) == I2S_MCLKOutput_Disable))
+
318 
+
326 #define I2S_AudioFreq_192k ((uint32_t)192000)
+
327 #define I2S_AudioFreq_96k ((uint32_t)96000)
+
328 #define I2S_AudioFreq_48k ((uint32_t)48000)
+
329 #define I2S_AudioFreq_44k ((uint32_t)44100)
+
330 #define I2S_AudioFreq_32k ((uint32_t)32000)
+
331 #define I2S_AudioFreq_22k ((uint32_t)22050)
+
332 #define I2S_AudioFreq_16k ((uint32_t)16000)
+
333 #define I2S_AudioFreq_11k ((uint32_t)11025)
+
334 #define I2S_AudioFreq_8k ((uint32_t)8000)
+
335 #define I2S_AudioFreq_Default ((uint32_t)2)
+
336 
+
337 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+
338  ((FREQ) <= I2S_AudioFreq_192k)) || \
+
339  ((FREQ) == I2S_AudioFreq_Default))
+
340 
+
348 #define I2S_CPOL_Low ((uint16_t)0x0000)
+
349 #define I2S_CPOL_High ((uint16_t)0x0008)
+
350 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+
351  ((CPOL) == I2S_CPOL_High))
+
352 
+
360 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+
361 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+
362 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+
363 
+
371 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+
372 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+
373 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+
374  ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+
375 
+
383 #define SPI_CRC_Tx ((uint8_t)0x00)
+
384 #define SPI_CRC_Rx ((uint8_t)0x01)
+
385 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+
386 
+
394 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
+
395 #define SPI_Direction_Tx ((uint16_t)0x4000)
+
396 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+
397  ((DIRECTION) == SPI_Direction_Tx))
+
398 
+
406 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
+
407 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+
408 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
+
409 #define I2S_IT_UDR ((uint8_t)0x53)
+
410 #define SPI_I2S_IT_TIFRFE ((uint8_t)0x58)
+
411 
+
412 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+
413  ((IT) == SPI_I2S_IT_RXNE) || \
+
414  ((IT) == SPI_I2S_IT_ERR))
+
415 
+
416 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
+
417 #define SPI_IT_MODF ((uint8_t)0x55)
+
418 #define SPI_IT_CRCERR ((uint8_t)0x54)
+
419 
+
420 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
421 
+
422 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
+
423  ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
+
424  ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
+
425  ((IT) == SPI_I2S_IT_TIFRFE))
+
426 
+
434 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+
435 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+
436 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+
437 #define I2S_FLAG_UDR ((uint16_t)0x0008)
+
438 #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+
439 #define SPI_FLAG_MODF ((uint16_t)0x0020)
+
440 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+
441 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+
442 #define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100)
+
443 
+
444 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+
445 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+
446  ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+
447  ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+
448  ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+
449  ((FLAG) == SPI_I2S_FLAG_TIFRFE))
+
450 
+
458 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+
459 
+
467 #define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
+
468 #define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
+
469 #define SPI_IT_TXE SPI_I2S_IT_TXE
+
470 #define SPI_IT_RXNE SPI_I2S_IT_RXNE
+
471 #define SPI_IT_ERR SPI_I2S_IT_ERR
+
472 #define SPI_IT_OVR SPI_I2S_IT_OVR
+
473 #define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
+
474 #define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
+
475 #define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
+
476 #define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
+
477 #define SPI_DeInit SPI_I2S_DeInit
+
478 #define SPI_ITConfig SPI_I2S_ITConfig
+
479 #define SPI_DMACmd SPI_I2S_DMACmd
+
480 #define SPI_SendData SPI_I2S_SendData
+
481 #define SPI_ReceiveData SPI_I2S_ReceiveData
+
482 #define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
+
483 #define SPI_ClearFlag SPI_I2S_ClearFlag
+
484 #define SPI_GetITStatus SPI_I2S_GetITStatus
+
485 #define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
+
486 
+
494 /* Exported macro ------------------------------------------------------------*/
+
495 /* Exported functions --------------------------------------------------------*/
+
496 
+
497 /* Function used to set the SPI configuration to the default reset state *****/
+
498 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
499 
+
500 /* Initialization and Configuration functions *********************************/
+
501 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+
502 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+
503 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+
504 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+
505 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
506 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
507 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+
508 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+
509 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+
510 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
511 void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
512 
+
513 void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
+
514 
+
515 /* Data transfers functions ***************************************************/
+
516 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+
517 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+
518 
+
519 /* Hardware CRC Calculation functions *****************************************/
+
520 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+
521 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+
522 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+
523 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
524 
+
525 /* DMA transfers management functions *****************************************/
+
526 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
527 
+
528 /* Interrupts and flags management functions **********************************/
+
529 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+
530 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
531 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
532 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
533 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
534 
+
535 #ifdef __cplusplus
+
536 }
+
537 #endif
+
538 
+
539 #endif /*__STM32F4xx_SPI_H */
+
540 
+
549 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
I2S_InitTypeDef::I2S_Mode
uint16_t I2S_Mode
Definition: stm32f4xx_spi.h:94
+
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f4xx.h:1257
+
I2S_StructInit
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
Fills each I2S_InitStruct member with its default value.
Definition: stm32f4xx_spi.c:515
+
I2S_Cmd
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral (in I2S mode).
Definition: stm32f4xx_spi.c:569
+
SPI_I2S_GetITStatus
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
Definition: stm32f4xx_spi.c:1234
+
SPI_I2S_SendData
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
Transmits a Data through the SPIx/I2Sx peripheral.
Definition: stm32f4xx_spi.c:824
+
I2S_Init
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the I2S_InitStruct.
Definition: stm32f4xx_spi.c:348
+
SPI_I2S_GetFlagStatus
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Checks whether the specified SPIx/I2Sx flag is set or not.
Definition: stm32f4xx_spi.c:1168
+
SPI_StructInit
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
Fills each SPI_InitStruct member with its default value.
Definition: stm32f4xx_spi.c:487
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
SPI_I2S_ClearITPendingBit
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
Definition: stm32f4xx_spi.c:1289
+
SPI_I2S_ReceiveData
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
Returns the most recent received data by the SPIx/I2Sx peripheral.
Definition: stm32f4xx_spi.c:808
+
SPI_SSOutputCmd
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SS output for the selected SPI.
Definition: stm32f4xx_spi.c:666
+
I2S_InitTypeDef::I2S_CPOL
uint16_t I2S_CPOL
Definition: stm32f4xx_spi.h:109
+
I2S_InitTypeDef::I2S_Standard
uint16_t I2S_Standard
Definition: stm32f4xx_spi.h:97
+
SPI_BiDirectionalLineConfig
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
Selects the data transfer direction in bidirectional mode for the specified SPI.
Definition: stm32f4xx_spi.c:616
+
SPI_InitTypeDef::SPI_CPOL
uint16_t SPI_CPOL
Definition: stm32f4xx_spi.h:65
+
SPI_InitTypeDef::SPI_FirstBit
uint16_t SPI_FirstBit
Definition: stm32f4xx_spi.h:81
+
SPI_InitTypeDef::SPI_BaudRatePrescaler
uint16_t SPI_BaudRatePrescaler
Definition: stm32f4xx_spi.h:75
+
I2S_FullDuplexConfig
void I2S_FullDuplexConfig(SPI_TypeDef *I2Sxext, I2S_InitTypeDef *I2S_InitStruct)
Configures the full duplex mode for the I2Sx peripheral using its extension I2Sxext according to the ...
Definition: stm32f4xx_spi.c:734
+
I2S_InitTypeDef
I2S Init structure definition.
Definition: stm32f4xx_spi.h:91
+
SPI_InitTypeDef::SPI_Mode
uint16_t SPI_Mode
Definition: stm32f4xx_spi.h:59
+
SPI_TransmitCRC
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
Transmit the SPIx CRC value.
Definition: stm32f4xx_spi.c:936
+
SPI_Init
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
Initializes the SPIx peripheral according to the specified parameters in the SPI_InitStruct.
Definition: stm32f4xx_spi.c:284
+
SPI_NSSInternalSoftwareConfig
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
Configures internally by software the NSS pin for the selected SPI.
Definition: stm32f4xx_spi.c:642
+
SPI_InitTypeDef::SPI_CPHA
uint16_t SPI_CPHA
Definition: stm32f4xx_spi.h:68
+
SPI_InitTypeDef::SPI_NSS
uint16_t SPI_NSS
Definition: stm32f4xx_spi.h:71
+
SPI_InitTypeDef
SPI Init structure definition.
Definition: stm32f4xx_spi.h:54
+
SPI_InitTypeDef::SPI_DataSize
uint16_t SPI_DataSize
Definition: stm32f4xx_spi.h:62
+
SPI_I2S_ITConfig
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
Enables or disables the specified SPI/I2S interrupts.
Definition: stm32f4xx_spi.c:1124
+
I2S_InitTypeDef::I2S_DataFormat
uint16_t I2S_DataFormat
Definition: stm32f4xx_spi.h:100
+
SPI_CalculateCRC
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the CRC value calculation of the transferred bytes.
Definition: stm32f4xx_spi.c:914
+
SPI_TIModeCmd
void SPI_TIModeCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
Definition: stm32f4xx_spi.c:697
+
SPI_I2S_DMACmd
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
Enables or disables the SPIx/I2Sx DMA interface.
Definition: stm32f4xx_spi.c:1016
+
SPI_I2S_DeInit
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
De-initialize the SPIx peripheral registers to their default reset values.
Definition: stm32f4xx_spi.c:224
+
SPI_InitTypeDef::SPI_CRCPolynomial
uint16_t SPI_CRCPolynomial
Definition: stm32f4xx_spi.h:84
+
SPI_I2S_ClearFlag
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
Clears the SPIx CRC Error (CRCERR) flag.
Definition: stm32f4xx_spi.c:1209
+
SPI_GetCRCPolynomial
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
Returns the CRC Polynomial register value for the specified SPI.
Definition: stm32f4xx_spi.c:979
+
I2S_InitTypeDef::I2S_AudioFreq
uint32_t I2S_AudioFreq
Definition: stm32f4xx_spi.h:106
+
SPI_GetCRC
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
Returns the transmit or the receive CRC register value for the specified SPI.
Definition: stm32f4xx_spi.c:954
+
SPI_Cmd
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
Enables or disables the specified SPI peripheral.
Definition: stm32f4xx_spi.c:544
+
SPI_DataSizeConfig
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
Configures the data size for the selected SPI.
Definition: stm32f4xx_spi.c:596
+
SPI_InitTypeDef::SPI_Direction
uint16_t SPI_Direction
Definition: stm32f4xx_spi.h:56
+
I2S_InitTypeDef::I2S_MCLKOutput
uint16_t I2S_MCLKOutput
Definition: stm32f4xx_spi.h:103
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__syscfg_8c.html b/stm32f4xx__syscfg_8c.html new file mode 100644 index 0000000..69202bb --- /dev/null +++ b/stm32f4xx__syscfg_8c.html @@ -0,0 +1,198 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_syscfg.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions
+
+
stm32f4xx_syscfg.c File Reference
+
+
+ +

This file provides firmware functions to manage the SYSCFG peripheral. +More...

+
#include "stm32f4xx_syscfg.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_syscfg.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define SYSCFG_OFFSET   (SYSCFG_BASE - PERIPH_BASE)
 
+#define MEMRMP_OFFSET   SYSCFG_OFFSET
 
+#define UFB_MODE_BitNumber   ((uint8_t)0x8)
 
+#define UFB_MODE_BB   (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
 
+#define PMC_OFFSET   (SYSCFG_OFFSET + 0x04)
 
+#define MII_RMII_SEL_BitNumber   ((uint8_t)0x17)
 
+#define PMC_MII_RMII_SEL_BB   (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
 
+#define CMPCR_OFFSET   (SYSCFG_OFFSET + 0x20)
 
+#define CMP_PD_BitNumber   ((uint8_t)0x00)
 
+#define CMPCR_CMP_PD_BB   (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SYSCFG_DeInit (void)
 Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values. More...
 
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
 Changes the mapping of the specified pin. More...
 
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
 Enables or disables the Interal FLASH Bank Swapping. More...
 
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 Selects the GPIO pin used as EXTI Line. More...
 
void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
 Selects the ETHERNET media interface. More...
 
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
 Enables or disables the I/O Compensation Cell. More...
 
FlagStatus SYSCFG_GetCompensationCellStatus (void)
 Checks whether the I/O Compensation Cell ready flag is set or not. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the SYSCFG peripheral.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014 
===============================================================================
+                    ##### How to use this driver #####
+===============================================================================
+   [..] This driver provides functions for:
+           
+      (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
+           
+      (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for 
+          STM32F42xxx/43xxx devices Devices. 
+               
+      (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
+             
+      (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
+ 
+      -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
+          using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__syscfg_8c__incl.map b/stm32f4xx__syscfg_8c__incl.map new file mode 100644 index 0000000..b69739d --- /dev/null +++ b/stm32f4xx__syscfg_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__syscfg_8c__incl.md5 b/stm32f4xx__syscfg_8c__incl.md5 new file mode 100644 index 0000000..2e59164 --- /dev/null +++ b/stm32f4xx__syscfg_8c__incl.md5 @@ -0,0 +1 @@ +37e3717b76d05e5147f421382bc8bb8a \ No newline at end of file diff --git a/stm32f4xx__syscfg_8c__incl.png b/stm32f4xx__syscfg_8c__incl.png new file mode 100644 index 0000000..af23675 Binary files /dev/null and b/stm32f4xx__syscfg_8c__incl.png differ diff --git a/stm32f4xx__syscfg_8h.html b/stm32f4xx__syscfg_8h.html new file mode 100644 index 0000000..d4ae986 --- /dev/null +++ b/stm32f4xx__syscfg_8h.html @@ -0,0 +1,271 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_syscfg.h File Reference + + + + + + + + + + +
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stm32f4xx_syscfg.h File Reference
+
+
+ +

This file contains all the functions prototypes for the SYSCFG firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_syscfg.h:
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Go to the source code of this file.

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+Macros

+#define EXTI_PortSourceGPIOA   ((uint8_t)0x00)
 
+#define EXTI_PortSourceGPIOB   ((uint8_t)0x01)
 
+#define EXTI_PortSourceGPIOC   ((uint8_t)0x02)
 
+#define EXTI_PortSourceGPIOD   ((uint8_t)0x03)
 
+#define EXTI_PortSourceGPIOE   ((uint8_t)0x04)
 
+#define EXTI_PortSourceGPIOF   ((uint8_t)0x05)
 
+#define EXTI_PortSourceGPIOG   ((uint8_t)0x06)
 
+#define EXTI_PortSourceGPIOH   ((uint8_t)0x07)
 
+#define EXTI_PortSourceGPIOI   ((uint8_t)0x08)
 
+#define EXTI_PortSourceGPIOJ   ((uint8_t)0x09)
 
+#define EXTI_PortSourceGPIOK   ((uint8_t)0x0A)
 
#define IS_EXTI_PORT_SOURCE(PORTSOURCE)
 
+#define EXTI_PinSource0   ((uint8_t)0x00)
 
+#define EXTI_PinSource1   ((uint8_t)0x01)
 
+#define EXTI_PinSource2   ((uint8_t)0x02)
 
+#define EXTI_PinSource3   ((uint8_t)0x03)
 
+#define EXTI_PinSource4   ((uint8_t)0x04)
 
+#define EXTI_PinSource5   ((uint8_t)0x05)
 
+#define EXTI_PinSource6   ((uint8_t)0x06)
 
+#define EXTI_PinSource7   ((uint8_t)0x07)
 
+#define EXTI_PinSource8   ((uint8_t)0x08)
 
+#define EXTI_PinSource9   ((uint8_t)0x09)
 
+#define EXTI_PinSource10   ((uint8_t)0x0A)
 
+#define EXTI_PinSource11   ((uint8_t)0x0B)
 
+#define EXTI_PinSource12   ((uint8_t)0x0C)
 
+#define EXTI_PinSource13   ((uint8_t)0x0D)
 
+#define EXTI_PinSource14   ((uint8_t)0x0E)
 
+#define EXTI_PinSource15   ((uint8_t)0x0F)
 
#define IS_EXTI_PIN_SOURCE(PINSOURCE)
 
+#define SYSCFG_MemoryRemap_Flash   ((uint8_t)0x00)
 
+#define SYSCFG_MemoryRemap_SystemFlash   ((uint8_t)0x01)
 
+#define SYSCFG_MemoryRemap_SRAM   ((uint8_t)0x03)
 
+#define SYSCFG_MemoryRemap_SDRAM   ((uint8_t)0x04)
 
+#define SYSCFG_MemoryRemap_FSMC   ((uint8_t)0x02)
 
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP)
 
+#define SYSCFG_ETH_MediaInterface_MII   ((uint32_t)0x00000000)
 
+#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)
 
#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE)
 
+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

void SYSCFG_DeInit (void)
 Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset values. More...
 
void SYSCFG_MemoryRemapConfig (uint8_t SYSCFG_MemoryRemap)
 Changes the mapping of the specified pin. More...
 
void SYSCFG_MemorySwappingBank (FunctionalState NewState)
 Enables or disables the Interal FLASH Bank Swapping. More...
 
void SYSCFG_EXTILineConfig (uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 Selects the GPIO pin used as EXTI Line. More...
 
void SYSCFG_ETH_MediaInterfaceConfig (uint32_t SYSCFG_ETH_MediaInterface)
 Selects the ETHERNET media interface. More...
 
void SYSCFG_CompensationCellCmd (FunctionalState NewState)
 Enables or disables the I/O Compensation Cell. More...
 
FlagStatus SYSCFG_GetCompensationCellStatus (void)
 Checks whether the I/O Compensation Cell ready flag is set or not. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the SYSCFG firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__syscfg_8h__dep__incl.map b/stm32f4xx__syscfg_8h__dep__incl.map new file mode 100644 index 0000000..fd99531 --- /dev/null +++ b/stm32f4xx__syscfg_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__syscfg_8h__dep__incl.md5 b/stm32f4xx__syscfg_8h__dep__incl.md5 new file mode 100644 index 0000000..62ccebd --- /dev/null +++ b/stm32f4xx__syscfg_8h__dep__incl.md5 @@ -0,0 +1 @@ +a534b84848fd9388c14371bd2f962d94 \ No newline at end of file diff --git a/stm32f4xx__syscfg_8h__dep__incl.png b/stm32f4xx__syscfg_8h__dep__incl.png new file mode 100644 index 0000000..dae2091 Binary files /dev/null and b/stm32f4xx__syscfg_8h__dep__incl.png differ diff --git a/stm32f4xx__syscfg_8h__incl.map b/stm32f4xx__syscfg_8h__incl.map new file mode 100644 index 0000000..7a007ae --- /dev/null +++ b/stm32f4xx__syscfg_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__syscfg_8h__incl.md5 b/stm32f4xx__syscfg_8h__incl.md5 new file mode 100644 index 0000000..d30b37b --- /dev/null +++ b/stm32f4xx__syscfg_8h__incl.md5 @@ -0,0 +1 @@ +d229c06ed6d7d678a87e360ba123ed8d \ No newline at end of file diff --git a/stm32f4xx__syscfg_8h__incl.png b/stm32f4xx__syscfg_8h__incl.png new file mode 100644 index 0000000..02fd444 Binary files /dev/null and b/stm32f4xx__syscfg_8h__incl.png differ diff --git a/stm32f4xx__syscfg_8h_source.html b/stm32f4xx__syscfg_8h_source.html new file mode 100644 index 0000000..2c9e9c7 --- /dev/null +++ b/stm32f4xx__syscfg_8h_source.html @@ -0,0 +1,239 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_syscfg.h Source File + + + + + + + + + + +
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stm32f4xx_syscfg.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_SYSCFG_H
+
31 #define __STM32F4xx_SYSCFG_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
58 #define EXTI_PortSourceGPIOA ((uint8_t)0x00)
+
59 #define EXTI_PortSourceGPIOB ((uint8_t)0x01)
+
60 #define EXTI_PortSourceGPIOC ((uint8_t)0x02)
+
61 #define EXTI_PortSourceGPIOD ((uint8_t)0x03)
+
62 #define EXTI_PortSourceGPIOE ((uint8_t)0x04)
+
63 #define EXTI_PortSourceGPIOF ((uint8_t)0x05)
+
64 #define EXTI_PortSourceGPIOG ((uint8_t)0x06)
+
65 #define EXTI_PortSourceGPIOH ((uint8_t)0x07)
+
66 #define EXTI_PortSourceGPIOI ((uint8_t)0x08)
+
67 #define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
+
68 #define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
+
69 
+
70 #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+
71  ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+
72  ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+
73  ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+
74  ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+
75  ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
+
76  ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
+
77  ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
+
78  ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
+
79  ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
+
80  ((PORTSOURCE) == EXTI_PortSourceGPIOK))
+
81 
+
90 #define EXTI_PinSource0 ((uint8_t)0x00)
+
91 #define EXTI_PinSource1 ((uint8_t)0x01)
+
92 #define EXTI_PinSource2 ((uint8_t)0x02)
+
93 #define EXTI_PinSource3 ((uint8_t)0x03)
+
94 #define EXTI_PinSource4 ((uint8_t)0x04)
+
95 #define EXTI_PinSource5 ((uint8_t)0x05)
+
96 #define EXTI_PinSource6 ((uint8_t)0x06)
+
97 #define EXTI_PinSource7 ((uint8_t)0x07)
+
98 #define EXTI_PinSource8 ((uint8_t)0x08)
+
99 #define EXTI_PinSource9 ((uint8_t)0x09)
+
100 #define EXTI_PinSource10 ((uint8_t)0x0A)
+
101 #define EXTI_PinSource11 ((uint8_t)0x0B)
+
102 #define EXTI_PinSource12 ((uint8_t)0x0C)
+
103 #define EXTI_PinSource13 ((uint8_t)0x0D)
+
104 #define EXTI_PinSource14 ((uint8_t)0x0E)
+
105 #define EXTI_PinSource15 ((uint8_t)0x0F)
+
106 #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+
107  ((PINSOURCE) == EXTI_PinSource1) || \
+
108  ((PINSOURCE) == EXTI_PinSource2) || \
+
109  ((PINSOURCE) == EXTI_PinSource3) || \
+
110  ((PINSOURCE) == EXTI_PinSource4) || \
+
111  ((PINSOURCE) == EXTI_PinSource5) || \
+
112  ((PINSOURCE) == EXTI_PinSource6) || \
+
113  ((PINSOURCE) == EXTI_PinSource7) || \
+
114  ((PINSOURCE) == EXTI_PinSource8) || \
+
115  ((PINSOURCE) == EXTI_PinSource9) || \
+
116  ((PINSOURCE) == EXTI_PinSource10) || \
+
117  ((PINSOURCE) == EXTI_PinSource11) || \
+
118  ((PINSOURCE) == EXTI_PinSource12) || \
+
119  ((PINSOURCE) == EXTI_PinSource13) || \
+
120  ((PINSOURCE) == EXTI_PinSource14) || \
+
121  ((PINSOURCE) == EXTI_PinSource15))
+
122 
+
130 #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
+
131 #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
+
132 #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
+
133 #define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
+
134 
+
135 #if defined (STM32F40_41xxx)
+
136 #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
+
137 #endif /* STM32F40_41xxx */
+
138 
+
139 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
140 #define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
+
141 #endif /* STM32F427_437xx || STM32F429_439xx */
+
142 
+
143 #if defined (STM32F40_41xxx)
+
144 #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+
145  ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+
146  ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+
147  ((REMAP) == SYSCFG_MemoryRemap_FSMC))
+
148 #endif /* STM32F40_41xxx */
+
149 
+
150 #if defined (STM32F401xx) || defined (STM32F411xE)
+
151 #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+
152  ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+
153  ((REMAP) == SYSCFG_MemoryRemap_SRAM))
+
154 #endif /* STM32F401xx || STM32F411xE */
+
155 
+
156 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+
157 #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+
158  ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+
159  ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+
160  ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
+
161  ((REMAP) == SYSCFG_MemoryRemap_FMC))
+
162 #endif /* STM32F427_437xx || STM32F429_439xx */
+
163 
+
172 #define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
+
173 #define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
+
174 
+
175 #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
+
176  ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
+
177 
+
185 /* Exported macro ------------------------------------------------------------*/
+
186 /* Exported functions --------------------------------------------------------*/
+
187 
+
188 void SYSCFG_DeInit(void);
+
189 void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
+
190 void SYSCFG_MemorySwappingBank(FunctionalState NewState);
+
191 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+
192 void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
+
193 void SYSCFG_CompensationCellCmd(FunctionalState NewState);
+
194 FlagStatus SYSCFG_GetCompensationCellStatus(void);
+
195 
+
196 #ifdef __cplusplus
+
197 }
+
198 #endif
+
199 
+
200 #endif /*__STM32F4xx_SYSCFG_H */
+
201 
+
210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
SYSCFG_EXTILineConfig
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
Selects the GPIO pin used as EXTI Line.
Definition: stm32f4xx_syscfg.c:162
+
SYSCFG_MemoryRemapConfig
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
Changes the mapping of the specified pin.
Definition: stm32f4xx_syscfg.c:118
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
SYSCFG_GetCompensationCellStatus
FlagStatus SYSCFG_GetCompensationCellStatus(void)
Checks whether the I/O Compensation Cell ready flag is set or not.
Definition: stm32f4xx_syscfg.c:213
+
SYSCFG_ETH_MediaInterfaceConfig
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
Selects the ETHERNET media interface.
Definition: stm32f4xx_syscfg.c:183
+
SYSCFG_CompensationCellCmd
void SYSCFG_CompensationCellCmd(FunctionalState NewState)
Enables or disables the I/O Compensation Cell.
Definition: stm32f4xx_syscfg.c:200
+
SYSCFG_MemorySwappingBank
void SYSCFG_MemorySwappingBank(FunctionalState NewState)
Enables or disables the Interal FLASH Bank Swapping.
Definition: stm32f4xx_syscfg.c:139
+
SYSCFG_DeInit
void SYSCFG_DeInit(void)
Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset...
Definition: stm32f4xx_syscfg.c:100
+
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+ + diff --git a/stm32f4xx__tim_8c.html b/stm32f4xx__tim_8c.html new file mode 100644 index 0000000..19fa8eb --- /dev/null +++ b/stm32f4xx__tim_8c.html @@ -0,0 +1,500 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_tim.c File Reference + + + + + + + + + + +
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stm32f4xx_tim.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the TIM peripheral: +More...

+
#include "stm32f4xx_tim.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_tim.c:
+
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+Macros

+#define SMCR_ETR_MASK   ((uint16_t)0x00FF)
 
+#define CCMR_OFFSET   ((uint16_t)0x0018)
 
+#define CCER_CCE_SET   ((uint16_t)0x0001)
 
+#define CCER_CCNE_SET   ((uint16_t)0x0004)
 
+#define CCMR_OC13M_MASK   ((uint16_t)0xFF8F)
 
+#define CCMR_OC24M_MASK   ((uint16_t)0x8FFF)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_DeInit (TIM_TypeDef *TIMx)
 Deinitializes the TIMx peripheral registers to their default reset values. More...
 
void TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct. More...
 
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Fills each TIM_TimeBaseInitStruct member with its default value. More...
 
void TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
 Configures the TIMx Prescaler. More...
 
void TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
 Specifies the TIMx Counter Mode to be used. More...
 
void TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
 Sets the TIMx Counter Register value. More...
 
void TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
 Sets the TIMx Autoreload Register value. More...
 
uint32_t TIM_GetCounter (TIM_TypeDef *TIMx)
 Gets the TIMx Counter value. More...
 
uint16_t TIM_GetPrescaler (TIM_TypeDef *TIMx)
 Gets the TIMx Prescaler value. More...
 
void TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or Disables the TIMx Update event. More...
 
void TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
 Configures the TIMx Update Request Interrupt source. More...
 
void TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables TIMx peripheral Preload register on ARR. More...
 
void TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
 Selects the TIMx's One Pulse Mode. More...
 
void TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
 Sets the TIMx Clock Division value. More...
 
void TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the specified TIM peripheral. More...
 
void TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
 Fills each TIM_OCInitStruct member with its default value. More...
 
void TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
 Selects the TIM Output Compare Mode. More...
 
void TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
 Sets the TIMx Capture Compare1 Register value. More...
 
void TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
 Sets the TIMx Capture Compare2 Register value. More...
 
void TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
 Sets the TIMx Capture Compare3 Register value. More...
 
void TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
 Sets the TIMx Capture Compare4 Register value. More...
 
void TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 1 waveform to active or inactive level. More...
 
void TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 2 waveform to active or inactive level. More...
 
void TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 3 waveform to active or inactive level. More...
 
void TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 4 waveform to active or inactive level. More...
 
void TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR1. More...
 
void TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR2. More...
 
void TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR3. More...
 
void TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR4. More...
 
void TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 1 Fast feature. More...
 
void TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 2 Fast feature. More...
 
void TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 3 Fast feature. More...
 
void TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 4 Fast feature. More...
 
void TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF1 signal on an external event. More...
 
void TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF2 signal on an external event. More...
 
void TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF3 signal on an external event. More...
 
void TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF4 signal on an external event. More...
 
void TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 1 polarity. More...
 
void TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 1N polarity. More...
 
void TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 2 polarity. More...
 
void TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 2N polarity. More...
 
void TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 3 polarity. More...
 
void TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 3N polarity. More...
 
void TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 4 polarity. More...
 
void TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
 Enables or disables the TIM Capture Compare Channel x. More...
 
void TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
 Enables or disables the TIM Capture Compare Channel xN. More...
 
void TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct. More...
 
void TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
 Fills each TIM_ICInitStruct member with its default value. More...
 
void TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal. More...
 
uint32_t TIM_GetCapture1 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 1 value. More...
 
uint32_t TIM_GetCapture2 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 2 value. More...
 
uint32_t TIM_GetCapture3 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 3 value. More...
 
uint32_t TIM_GetCapture4 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 4 value. More...
 
void TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 1 prescaler. More...
 
void TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 2 prescaler. More...
 
void TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 3 prescaler. More...
 
void TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 4 prescaler. More...
 
void TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). More...
 
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Fills each TIM_BDTRInitStruct member with its default value. More...
 
void TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIM peripheral Main Outputs. More...
 
void TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIM peripheral Commutation event. More...
 
void TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
 Sets or Resets the TIM peripheral Capture Compare Preload Control bit. More...
 
void TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
 Enables or disables the specified TIM interrupts. More...
 
void TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
 Configures the TIMx event to be generate by software. More...
 
FlagStatus TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Checks whether the specified TIM flag is set or not. More...
 
void TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Clears the TIMx's pending flags. More...
 
ITStatus TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Checks whether the TIM interrupt has occurred or not. More...
 
void TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Clears the TIMx's interrupt pending bits. More...
 
void TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
 Configures the TIMx's DMA interface. More...
 
void TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
 Enables or disables the TIMx's DMA Requests. More...
 
void TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIMx peripheral Capture Compare DMA source. More...
 
void TIM_InternalClockConfig (TIM_TypeDef *TIMx)
 Configures the TIMx internal Clock. More...
 
void TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Configures the TIMx Internal Trigger as External Clock. More...
 
void TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
 Configures the TIMx Trigger as External Clock. More...
 
void TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode1. More...
 
void TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode2. More...
 
void TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Selects the Input Trigger source. More...
 
void TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
 Selects the TIMx Trigger Output Mode. More...
 
void TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
 Selects the TIMx Slave Mode. More...
 
void TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
 Sets or Resets the TIMx Master/Slave Mode. More...
 
void TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the TIMx External Trigger (ETR). More...
 
void TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
 Configures the TIMx Encoder Interface. More...
 
void TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIMx's Hall sensor interface. More...
 
void TIM_RemapConfig (TIM_TypeDef *TIMx, uint16_t TIM_Remap)
 Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the TIM peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • TimeBase management
    • +
  • Output Compare management
    • +
  • Input Capture management
    • +
  • Advanced-control timers (TIM1 and TIM8) specific features
    • +
  • Interrupts, DMA and flags management
    • +
  • Clocks management
    • +
  • Synchronization management
    • +
  • Specific interface management
    • +
  • Specific remapping management
    • +
+
+
===============================================================================
+                  #####  How to use this driver #####
+===============================================================================
+   [..]
+   This driver provides functions to configure and program the TIM 
+   of all STM32F4xx devices.
+   These functions are split in 9 groups: 
+    
+     (#) TIM TimeBase management: this group includes all needed functions 
+         to configure the TM Timebase unit:
+       (++) Set/Get Prescaler
+       (++) Set/Get Autoreload  
+       (++) Counter modes configuration
+       (++) Set Clock division  
+       (++) Select the One Pulse mode
+       (++) Update Request Configuration
+       (++) Update Disable Configuration
+       (++) Auto-Preload Configuration 
+       (++) Enable/Disable the counter     
+                  
+     (#) TIM Output Compare management: this group includes all needed 
+         functions to configure the Capture/Compare unit used in Output 
+         compare mode: 
+       (++) Configure each channel, independently, in Output Compare mode
+       (++) Select the output compare modes
+       (++) Select the Polarities of each channel
+       (++) Set/Get the Capture/Compare register values
+       (++) Select the Output Compare Fast mode 
+       (++) Select the Output Compare Forced mode  
+       (++) Output Compare-Preload Configuration 
+       (++) Clear Output Compare Reference
+       (++) Select the OCREF Clear signal
+       (++) Enable/Disable the Capture/Compare Channels    
+                    
+     (#) TIM Input Capture management: this group includes all needed 
+         functions to configure the Capture/Compare unit used in 
+         Input Capture mode:
+       (++) Configure each channel in input capture mode
+       (++) Configure Channel1/2 in PWM Input mode
+       (++) Set the Input Capture Prescaler
+       (++) Get the Capture/Compare values      
+                    
+     (#) Advanced-control timers (TIM1 and TIM8) specific features
+       (++) Configures the Break input, dead time, Lock level, the OSSI,
+            the OSSR State and the AOE(automatic output enable)
+       (++) Enable/Disable the TIM peripheral Main Outputs
+       (++) Select the Commutation event
+       (++) Set/Reset the Capture Compare Preload Control bit
+                               
+     (#) TIM interrupts, DMA and flags management
+       (++) Enable/Disable interrupt sources
+       (++) Get flags status
+       (++) Clear flags/ Pending bits
+       (++) Enable/Disable DMA requests 
+       (++) Configure DMA burst mode
+       (++) Select CaptureCompare DMA request  
+               
+     (#) TIM clocks management: this group includes all needed functions 
+         to configure the clock controller unit:
+       (++) Select internal/External clock
+       (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
+          
+     (#) TIM synchronization management: this group includes all needed 
+         functions to configure the Synchronization unit:
+       (++) Select Input Trigger  
+       (++) Select Output Trigger  
+       (++) Select Master Slave Mode 
+       (++) ETR Configuration when used as external trigger   
+      
+     (#) TIM specific interface management, this group includes all 
+         needed functions to use the specific TIM interface:
+       (++) Encoder Interface Configuration
+       (++) Select Hall Sensor   
+          
+     (#) TIM specific remapping management includes the Remapping 
+         configuration of specific timers
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__tim_8c__incl.map b/stm32f4xx__tim_8c__incl.map new file mode 100644 index 0000000..77ac034 --- /dev/null +++ b/stm32f4xx__tim_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__tim_8c__incl.md5 b/stm32f4xx__tim_8c__incl.md5 new file mode 100644 index 0000000..331eed7 --- /dev/null +++ b/stm32f4xx__tim_8c__incl.md5 @@ -0,0 +1 @@ +d7eb87d006ca44e3aa1aa2a87e62f0ec \ No newline at end of file diff --git a/stm32f4xx__tim_8c__incl.png b/stm32f4xx__tim_8c__incl.png new file mode 100644 index 0000000..681111c Binary files /dev/null and b/stm32f4xx__tim_8c__incl.png differ diff --git a/stm32f4xx__tim_8h.html b/stm32f4xx__tim_8h.html new file mode 100644 index 0000000..705e333 --- /dev/null +++ b/stm32f4xx__tim_8h.html @@ -0,0 +1,1149 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_tim.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Functions
+
+
stm32f4xx_tim.h File Reference
+
+
+ +

This file contains all the functions prototypes for the TIM firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_tim.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Classes

struct  TIM_TimeBaseInitTypeDef
 TIM Time Base Init structure definition. More...
 
struct  TIM_OCInitTypeDef
 TIM Output Compare Init structure definition. More...
 
struct  TIM_ICInitTypeDef
 TIM Input Capture Init structure definition. More...
 
struct  TIM_BDTRInitTypeDef
 BDTR structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_TIM_ALL_PERIPH(PERIPH)
 
#define IS_TIM_LIST1_PERIPH(PERIPH)
 
#define IS_TIM_LIST2_PERIPH(PERIPH)
 
#define IS_TIM_LIST3_PERIPH(PERIPH)
 
#define IS_TIM_LIST4_PERIPH(PERIPH)
 
#define IS_TIM_LIST5_PERIPH(PERIPH)
 
#define IS_TIM_LIST6_PERIPH(TIMx)
 
+#define TIM_OCMode_Timing   ((uint16_t)0x0000)
 
+#define TIM_OCMode_Active   ((uint16_t)0x0010)
 
+#define TIM_OCMode_Inactive   ((uint16_t)0x0020)
 
+#define TIM_OCMode_Toggle   ((uint16_t)0x0030)
 
+#define TIM_OCMode_PWM1   ((uint16_t)0x0060)
 
+#define TIM_OCMode_PWM2   ((uint16_t)0x0070)
 
#define IS_TIM_OC_MODE(MODE)
 
#define IS_TIM_OCM(MODE)
 
+#define TIM_OPMode_Single   ((uint16_t)0x0008)
 
+#define TIM_OPMode_Repetitive   ((uint16_t)0x0000)
 
#define IS_TIM_OPM_MODE(MODE)
 
+#define TIM_Channel_1   ((uint16_t)0x0000)
 
+#define TIM_Channel_2   ((uint16_t)0x0004)
 
+#define TIM_Channel_3   ((uint16_t)0x0008)
 
+#define TIM_Channel_4   ((uint16_t)0x000C)
 
#define IS_TIM_CHANNEL(CHANNEL)
 
#define IS_TIM_PWMI_CHANNEL(CHANNEL)
 
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL)
 
+#define TIM_CKD_DIV1   ((uint16_t)0x0000)
 
+#define TIM_CKD_DIV2   ((uint16_t)0x0100)
 
+#define TIM_CKD_DIV4   ((uint16_t)0x0200)
 
#define IS_TIM_CKD_DIV(DIV)
 
+#define TIM_CounterMode_Up   ((uint16_t)0x0000)
 
+#define TIM_CounterMode_Down   ((uint16_t)0x0010)
 
+#define TIM_CounterMode_CenterAligned1   ((uint16_t)0x0020)
 
+#define TIM_CounterMode_CenterAligned2   ((uint16_t)0x0040)
 
+#define TIM_CounterMode_CenterAligned3   ((uint16_t)0x0060)
 
#define IS_TIM_COUNTER_MODE(MODE)
 
+#define TIM_OCPolarity_High   ((uint16_t)0x0000)
 
+#define TIM_OCPolarity_Low   ((uint16_t)0x0002)
 
#define IS_TIM_OC_POLARITY(POLARITY)
 
+#define TIM_OCNPolarity_High   ((uint16_t)0x0000)
 
+#define TIM_OCNPolarity_Low   ((uint16_t)0x0008)
 
#define IS_TIM_OCN_POLARITY(POLARITY)
 
+#define TIM_OutputState_Disable   ((uint16_t)0x0000)
 
+#define TIM_OutputState_Enable   ((uint16_t)0x0001)
 
#define IS_TIM_OUTPUT_STATE(STATE)
 
+#define TIM_OutputNState_Disable   ((uint16_t)0x0000)
 
+#define TIM_OutputNState_Enable   ((uint16_t)0x0004)
 
#define IS_TIM_OUTPUTN_STATE(STATE)
 
+#define TIM_CCx_Enable   ((uint16_t)0x0001)
 
+#define TIM_CCx_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_CCX(CCX)
 
+#define TIM_CCxN_Enable   ((uint16_t)0x0004)
 
+#define TIM_CCxN_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_CCXN(CCXN)
 
+#define TIM_Break_Enable   ((uint16_t)0x1000)
 
+#define TIM_Break_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_BREAK_STATE(STATE)
 
+#define TIM_BreakPolarity_Low   ((uint16_t)0x0000)
 
+#define TIM_BreakPolarity_High   ((uint16_t)0x2000)
 
#define IS_TIM_BREAK_POLARITY(POLARITY)
 
+#define TIM_AutomaticOutput_Enable   ((uint16_t)0x4000)
 
+#define TIM_AutomaticOutput_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
 
+#define TIM_LOCKLevel_OFF   ((uint16_t)0x0000)
 
+#define TIM_LOCKLevel_1   ((uint16_t)0x0100)
 
+#define TIM_LOCKLevel_2   ((uint16_t)0x0200)
 
+#define TIM_LOCKLevel_3   ((uint16_t)0x0300)
 
#define IS_TIM_LOCK_LEVEL(LEVEL)
 
+#define TIM_OSSIState_Enable   ((uint16_t)0x0400)
 
+#define TIM_OSSIState_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OSSI_STATE(STATE)
 
+#define TIM_OSSRState_Enable   ((uint16_t)0x0800)
 
+#define TIM_OSSRState_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OSSR_STATE(STATE)
 
+#define TIM_OCIdleState_Set   ((uint16_t)0x0100)
 
+#define TIM_OCIdleState_Reset   ((uint16_t)0x0000)
 
#define IS_TIM_OCIDLE_STATE(STATE)
 
+#define TIM_OCNIdleState_Set   ((uint16_t)0x0200)
 
+#define TIM_OCNIdleState_Reset   ((uint16_t)0x0000)
 
#define IS_TIM_OCNIDLE_STATE(STATE)
 
+#define TIM_ICPolarity_Rising   ((uint16_t)0x0000)
 
+#define TIM_ICPolarity_Falling   ((uint16_t)0x0002)
 
+#define TIM_ICPolarity_BothEdge   ((uint16_t)0x000A)
 
#define IS_TIM_IC_POLARITY(POLARITY)
 
#define TIM_ICSelection_DirectTI   ((uint16_t)0x0001)
 
#define TIM_ICSelection_IndirectTI   ((uint16_t)0x0002)
 
#define TIM_ICSelection_TRC   ((uint16_t)0x0003)
 
#define IS_TIM_IC_SELECTION(SELECTION)
 
#define TIM_ICPSC_DIV1   ((uint16_t)0x0000)
 
#define TIM_ICPSC_DIV2   ((uint16_t)0x0004)
 
#define TIM_ICPSC_DIV4   ((uint16_t)0x0008)
 
#define TIM_ICPSC_DIV8   ((uint16_t)0x000C)
 
#define IS_TIM_IC_PRESCALER(PRESCALER)
 
+#define TIM_IT_Update   ((uint16_t)0x0001)
 
+#define TIM_IT_CC1   ((uint16_t)0x0002)
 
+#define TIM_IT_CC2   ((uint16_t)0x0004)
 
+#define TIM_IT_CC3   ((uint16_t)0x0008)
 
+#define TIM_IT_CC4   ((uint16_t)0x0010)
 
+#define TIM_IT_COM   ((uint16_t)0x0020)
 
+#define TIM_IT_Trigger   ((uint16_t)0x0040)
 
+#define TIM_IT_Break   ((uint16_t)0x0080)
 
+#define IS_TIM_IT(IT)   ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
 
#define IS_TIM_GET_IT(IT)
 
+#define TIM_DMABase_CR1   ((uint16_t)0x0000)
 
+#define TIM_DMABase_CR2   ((uint16_t)0x0001)
 
+#define TIM_DMABase_SMCR   ((uint16_t)0x0002)
 
+#define TIM_DMABase_DIER   ((uint16_t)0x0003)
 
+#define TIM_DMABase_SR   ((uint16_t)0x0004)
 
+#define TIM_DMABase_EGR   ((uint16_t)0x0005)
 
+#define TIM_DMABase_CCMR1   ((uint16_t)0x0006)
 
+#define TIM_DMABase_CCMR2   ((uint16_t)0x0007)
 
+#define TIM_DMABase_CCER   ((uint16_t)0x0008)
 
+#define TIM_DMABase_CNT   ((uint16_t)0x0009)
 
+#define TIM_DMABase_PSC   ((uint16_t)0x000A)
 
+#define TIM_DMABase_ARR   ((uint16_t)0x000B)
 
+#define TIM_DMABase_RCR   ((uint16_t)0x000C)
 
+#define TIM_DMABase_CCR1   ((uint16_t)0x000D)
 
+#define TIM_DMABase_CCR2   ((uint16_t)0x000E)
 
+#define TIM_DMABase_CCR3   ((uint16_t)0x000F)
 
+#define TIM_DMABase_CCR4   ((uint16_t)0x0010)
 
+#define TIM_DMABase_BDTR   ((uint16_t)0x0011)
 
+#define TIM_DMABase_DCR   ((uint16_t)0x0012)
 
+#define TIM_DMABase_OR   ((uint16_t)0x0013)
 
#define IS_TIM_DMA_BASE(BASE)
 
+#define TIM_DMABurstLength_1Transfer   ((uint16_t)0x0000)
 
+#define TIM_DMABurstLength_2Transfers   ((uint16_t)0x0100)
 
+#define TIM_DMABurstLength_3Transfers   ((uint16_t)0x0200)
 
+#define TIM_DMABurstLength_4Transfers   ((uint16_t)0x0300)
 
+#define TIM_DMABurstLength_5Transfers   ((uint16_t)0x0400)
 
+#define TIM_DMABurstLength_6Transfers   ((uint16_t)0x0500)
 
+#define TIM_DMABurstLength_7Transfers   ((uint16_t)0x0600)
 
+#define TIM_DMABurstLength_8Transfers   ((uint16_t)0x0700)
 
+#define TIM_DMABurstLength_9Transfers   ((uint16_t)0x0800)
 
+#define TIM_DMABurstLength_10Transfers   ((uint16_t)0x0900)
 
+#define TIM_DMABurstLength_11Transfers   ((uint16_t)0x0A00)
 
+#define TIM_DMABurstLength_12Transfers   ((uint16_t)0x0B00)
 
+#define TIM_DMABurstLength_13Transfers   ((uint16_t)0x0C00)
 
+#define TIM_DMABurstLength_14Transfers   ((uint16_t)0x0D00)
 
+#define TIM_DMABurstLength_15Transfers   ((uint16_t)0x0E00)
 
+#define TIM_DMABurstLength_16Transfers   ((uint16_t)0x0F00)
 
+#define TIM_DMABurstLength_17Transfers   ((uint16_t)0x1000)
 
+#define TIM_DMABurstLength_18Transfers   ((uint16_t)0x1100)
 
#define IS_TIM_DMA_LENGTH(LENGTH)
 
+#define TIM_DMA_Update   ((uint16_t)0x0100)
 
+#define TIM_DMA_CC1   ((uint16_t)0x0200)
 
+#define TIM_DMA_CC2   ((uint16_t)0x0400)
 
+#define TIM_DMA_CC3   ((uint16_t)0x0800)
 
+#define TIM_DMA_CC4   ((uint16_t)0x1000)
 
+#define TIM_DMA_COM   ((uint16_t)0x2000)
 
+#define TIM_DMA_Trigger   ((uint16_t)0x4000)
 
+#define IS_TIM_DMA_SOURCE(SOURCE)   ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
 
+#define TIM_ExtTRGPSC_OFF   ((uint16_t)0x0000)
 
+#define TIM_ExtTRGPSC_DIV2   ((uint16_t)0x1000)
 
+#define TIM_ExtTRGPSC_DIV4   ((uint16_t)0x2000)
 
+#define TIM_ExtTRGPSC_DIV8   ((uint16_t)0x3000)
 
#define IS_TIM_EXT_PRESCALER(PRESCALER)
 
+#define TIM_TS_ITR0   ((uint16_t)0x0000)
 
+#define TIM_TS_ITR1   ((uint16_t)0x0010)
 
+#define TIM_TS_ITR2   ((uint16_t)0x0020)
 
+#define TIM_TS_ITR3   ((uint16_t)0x0030)
 
+#define TIM_TS_TI1F_ED   ((uint16_t)0x0040)
 
+#define TIM_TS_TI1FP1   ((uint16_t)0x0050)
 
+#define TIM_TS_TI2FP2   ((uint16_t)0x0060)
 
+#define TIM_TS_ETRF   ((uint16_t)0x0070)
 
#define IS_TIM_TRIGGER_SELECTION(SELECTION)
 
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION)
 
+#define TIM_TIxExternalCLK1Source_TI1   ((uint16_t)0x0050)
 
+#define TIM_TIxExternalCLK1Source_TI2   ((uint16_t)0x0060)
 
+#define TIM_TIxExternalCLK1Source_TI1ED   ((uint16_t)0x0040)
 
+#define TIM_ExtTRGPolarity_Inverted   ((uint16_t)0x8000)
 
+#define TIM_ExtTRGPolarity_NonInverted   ((uint16_t)0x0000)
 
#define IS_TIM_EXT_POLARITY(POLARITY)
 
+#define TIM_PSCReloadMode_Update   ((uint16_t)0x0000)
 
+#define TIM_PSCReloadMode_Immediate   ((uint16_t)0x0001)
 
#define IS_TIM_PRESCALER_RELOAD(RELOAD)
 
+#define TIM_ForcedAction_Active   ((uint16_t)0x0050)
 
+#define TIM_ForcedAction_InActive   ((uint16_t)0x0040)
 
#define IS_TIM_FORCED_ACTION(ACTION)
 
+#define TIM_EncoderMode_TI1   ((uint16_t)0x0001)
 
+#define TIM_EncoderMode_TI2   ((uint16_t)0x0002)
 
+#define TIM_EncoderMode_TI12   ((uint16_t)0x0003)
 
#define IS_TIM_ENCODER_MODE(MODE)
 
+#define TIM_EventSource_Update   ((uint16_t)0x0001)
 
+#define TIM_EventSource_CC1   ((uint16_t)0x0002)
 
+#define TIM_EventSource_CC2   ((uint16_t)0x0004)
 
+#define TIM_EventSource_CC3   ((uint16_t)0x0008)
 
+#define TIM_EventSource_CC4   ((uint16_t)0x0010)
 
+#define TIM_EventSource_COM   ((uint16_t)0x0020)
 
+#define TIM_EventSource_Trigger   ((uint16_t)0x0040)
 
+#define TIM_EventSource_Break   ((uint16_t)0x0080)
 
+#define IS_TIM_EVENT_SOURCE(SOURCE)   ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
 
#define TIM_UpdateSource_Global   ((uint16_t)0x0000)
 
#define TIM_UpdateSource_Regular   ((uint16_t)0x0001)
 
#define IS_TIM_UPDATE_SOURCE(SOURCE)
 
+#define TIM_OCPreload_Enable   ((uint16_t)0x0008)
 
+#define TIM_OCPreload_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCPRELOAD_STATE(STATE)
 
+#define TIM_OCFast_Enable   ((uint16_t)0x0004)
 
+#define TIM_OCFast_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCFAST_STATE(STATE)
 
+#define TIM_OCClear_Enable   ((uint16_t)0x0080)
 
+#define TIM_OCClear_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_OCCLEAR_STATE(STATE)
 
+#define TIM_TRGOSource_Reset   ((uint16_t)0x0000)
 
+#define TIM_TRGOSource_Enable   ((uint16_t)0x0010)
 
+#define TIM_TRGOSource_Update   ((uint16_t)0x0020)
 
+#define TIM_TRGOSource_OC1   ((uint16_t)0x0030)
 
+#define TIM_TRGOSource_OC1Ref   ((uint16_t)0x0040)
 
+#define TIM_TRGOSource_OC2Ref   ((uint16_t)0x0050)
 
+#define TIM_TRGOSource_OC3Ref   ((uint16_t)0x0060)
 
+#define TIM_TRGOSource_OC4Ref   ((uint16_t)0x0070)
 
#define IS_TIM_TRGO_SOURCE(SOURCE)
 
+#define TIM_SlaveMode_Reset   ((uint16_t)0x0004)
 
+#define TIM_SlaveMode_Gated   ((uint16_t)0x0005)
 
+#define TIM_SlaveMode_Trigger   ((uint16_t)0x0006)
 
+#define TIM_SlaveMode_External1   ((uint16_t)0x0007)
 
#define IS_TIM_SLAVE_MODE(MODE)
 
+#define TIM_MasterSlaveMode_Enable   ((uint16_t)0x0080)
 
+#define TIM_MasterSlaveMode_Disable   ((uint16_t)0x0000)
 
#define IS_TIM_MSM_STATE(STATE)
 
+#define TIM2_TIM8_TRGO   ((uint16_t)0x0000)
 
+#define TIM2_ETH_PTP   ((uint16_t)0x0400)
 
+#define TIM2_USBFS_SOF   ((uint16_t)0x0800)
 
+#define TIM2_USBHS_SOF   ((uint16_t)0x0C00)
 
+#define TIM5_GPIO   ((uint16_t)0x0000)
 
+#define TIM5_LSI   ((uint16_t)0x0040)
 
+#define TIM5_LSE   ((uint16_t)0x0080)
 
+#define TIM5_RTC   ((uint16_t)0x00C0)
 
+#define TIM11_GPIO   ((uint16_t)0x0000)
 
+#define TIM11_HSE   ((uint16_t)0x0002)
 
#define IS_TIM_REMAP(TIM_REMAP)
 
+#define TIM_FLAG_Update   ((uint16_t)0x0001)
 
+#define TIM_FLAG_CC1   ((uint16_t)0x0002)
 
+#define TIM_FLAG_CC2   ((uint16_t)0x0004)
 
+#define TIM_FLAG_CC3   ((uint16_t)0x0008)
 
+#define TIM_FLAG_CC4   ((uint16_t)0x0010)
 
+#define TIM_FLAG_COM   ((uint16_t)0x0020)
 
+#define TIM_FLAG_Trigger   ((uint16_t)0x0040)
 
+#define TIM_FLAG_Break   ((uint16_t)0x0080)
 
+#define TIM_FLAG_CC1OF   ((uint16_t)0x0200)
 
+#define TIM_FLAG_CC2OF   ((uint16_t)0x0400)
 
+#define TIM_FLAG_CC3OF   ((uint16_t)0x0800)
 
+#define TIM_FLAG_CC4OF   ((uint16_t)0x1000)
 
#define IS_TIM_GET_FLAG(FLAG)
 
+#define IS_TIM_IC_FILTER(ICFILTER)   ((ICFILTER) <= 0xF)
 
+#define IS_TIM_EXT_FILTER(EXTFILTER)   ((EXTFILTER) <= 0xF)
 
+#define TIM_DMABurstLength_1Byte   TIM_DMABurstLength_1Transfer
 
+#define TIM_DMABurstLength_2Bytes   TIM_DMABurstLength_2Transfers
 
+#define TIM_DMABurstLength_3Bytes   TIM_DMABurstLength_3Transfers
 
+#define TIM_DMABurstLength_4Bytes   TIM_DMABurstLength_4Transfers
 
+#define TIM_DMABurstLength_5Bytes   TIM_DMABurstLength_5Transfers
 
+#define TIM_DMABurstLength_6Bytes   TIM_DMABurstLength_6Transfers
 
+#define TIM_DMABurstLength_7Bytes   TIM_DMABurstLength_7Transfers
 
+#define TIM_DMABurstLength_8Bytes   TIM_DMABurstLength_8Transfers
 
+#define TIM_DMABurstLength_9Bytes   TIM_DMABurstLength_9Transfers
 
+#define TIM_DMABurstLength_10Bytes   TIM_DMABurstLength_10Transfers
 
+#define TIM_DMABurstLength_11Bytes   TIM_DMABurstLength_11Transfers
 
+#define TIM_DMABurstLength_12Bytes   TIM_DMABurstLength_12Transfers
 
+#define TIM_DMABurstLength_13Bytes   TIM_DMABurstLength_13Transfers
 
+#define TIM_DMABurstLength_14Bytes   TIM_DMABurstLength_14Transfers
 
+#define TIM_DMABurstLength_15Bytes   TIM_DMABurstLength_15Transfers
 
+#define TIM_DMABurstLength_16Bytes   TIM_DMABurstLength_16Transfers
 
+#define TIM_DMABurstLength_17Bytes   TIM_DMABurstLength_17Transfers
 
+#define TIM_DMABurstLength_18Bytes   TIM_DMABurstLength_18Transfers
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TIM_DeInit (TIM_TypeDef *TIMx)
 Deinitializes the TIMx peripheral registers to their default reset values. More...
 
void TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct. More...
 
void TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
 Fills each TIM_TimeBaseInitStruct member with its default value. More...
 
void TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
 Configures the TIMx Prescaler. More...
 
void TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
 Specifies the TIMx Counter Mode to be used. More...
 
void TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
 Sets the TIMx Counter Register value. More...
 
void TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload)
 Sets the TIMx Autoreload Register value. More...
 
uint32_t TIM_GetCounter (TIM_TypeDef *TIMx)
 Gets the TIMx Counter value. More...
 
uint16_t TIM_GetPrescaler (TIM_TypeDef *TIMx)
 Gets the TIMx Prescaler value. More...
 
void TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or Disables the TIMx Update event. More...
 
void TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
 Configures the TIMx Update Request Interrupt source. More...
 
void TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables TIMx peripheral Preload register on ARR. More...
 
void TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
 Selects the TIMx's One Pulse Mode. More...
 
void TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD)
 Sets the TIMx Clock Division value. More...
 
void TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the specified TIM peripheral. More...
 
void TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
 Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct. More...
 
void TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct)
 Fills each TIM_OCInitStruct member with its default value. More...
 
void TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
 Selects the TIM Output Compare Mode. More...
 
void TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1)
 Sets the TIMx Capture Compare1 Register value. More...
 
void TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2)
 Sets the TIMx Capture Compare2 Register value. More...
 
void TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3)
 Sets the TIMx Capture Compare3 Register value. More...
 
void TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4)
 Sets the TIMx Capture Compare4 Register value. More...
 
void TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 1 waveform to active or inactive level. More...
 
void TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 2 waveform to active or inactive level. More...
 
void TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 3 waveform to active or inactive level. More...
 
void TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
 Forces the TIMx output 4 waveform to active or inactive level. More...
 
void TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR1. More...
 
void TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR2. More...
 
void TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR3. More...
 
void TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
 Enables or disables the TIMx peripheral Preload register on CCR4. More...
 
void TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 1 Fast feature. More...
 
void TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 2 Fast feature. More...
 
void TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 3 Fast feature. More...
 
void TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
 Configures the TIMx Output Compare 4 Fast feature. More...
 
void TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF1 signal on an external event. More...
 
void TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF2 signal on an external event. More...
 
void TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF3 signal on an external event. More...
 
void TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
 Clears or safeguards the OCREF4 signal on an external event. More...
 
void TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 1 polarity. More...
 
void TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 1N polarity. More...
 
void TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 2 polarity. More...
 
void TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 2N polarity. More...
 
void TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 3 polarity. More...
 
void TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
 Configures the TIMx Channel 3N polarity. More...
 
void TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
 Configures the TIMx channel 4 polarity. More...
 
void TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
 Enables or disables the TIM Capture Compare Channel x. More...
 
void TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
 Enables or disables the TIM Capture Compare Channel xN. More...
 
void TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct. More...
 
void TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct)
 Fills each TIM_ICInitStruct member with its default value. More...
 
void TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
 Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal. More...
 
uint32_t TIM_GetCapture1 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 1 value. More...
 
uint32_t TIM_GetCapture2 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 2 value. More...
 
uint32_t TIM_GetCapture3 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 3 value. More...
 
uint32_t TIM_GetCapture4 (TIM_TypeDef *TIMx)
 Gets the TIMx Input Capture 4 value. More...
 
void TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 1 prescaler. More...
 
void TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 2 prescaler. More...
 
void TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 3 prescaler. More...
 
void TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
 Sets the TIMx Input Capture 4 prescaler. More...
 
void TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). More...
 
void TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
 Fills each TIM_BDTRInitStruct member with its default value. More...
 
void TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIM peripheral Main Outputs. More...
 
void TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIM peripheral Commutation event. More...
 
void TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState)
 Sets or Resets the TIM peripheral Capture Compare Preload Control bit. More...
 
void TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
 Enables or disables the specified TIM interrupts. More...
 
void TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
 Configures the TIMx event to be generate by software. More...
 
FlagStatus TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Checks whether the specified TIM flag is set or not. More...
 
void TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
 Clears the TIMx's pending flags. More...
 
ITStatus TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Checks whether the TIM interrupt has occurred or not. More...
 
void TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT)
 Clears the TIMx's interrupt pending bits. More...
 
void TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
 Configures the TIMx's DMA interface. More...
 
void TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
 Enables or disables the TIMx's DMA Requests. More...
 
void TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState)
 Selects the TIMx peripheral Capture Compare DMA source. More...
 
void TIM_InternalClockConfig (TIM_TypeDef *TIMx)
 Configures the TIMx internal Clock. More...
 
void TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Configures the TIMx Internal Trigger as External Clock. More...
 
void TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
 Configures the TIMx Trigger as External Clock. More...
 
void TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode1. More...
 
void TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the External clock Mode2. More...
 
void TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
 Selects the Input Trigger source. More...
 
void TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
 Selects the TIMx Trigger Output Mode. More...
 
void TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
 Selects the TIMx Slave Mode. More...
 
void TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
 Sets or Resets the TIMx Master/Slave Mode. More...
 
void TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
 Configures the TIMx External Trigger (ETR). More...
 
void TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
 Configures the TIMx Encoder Interface. More...
 
void TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState)
 Enables or disables the TIMx's Hall sensor interface. More...
 
void TIM_RemapConfig (TIM_TypeDef *TIMx, uint16_t TIM_Remap)
 Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the TIM firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__tim_8h__dep__incl.map b/stm32f4xx__tim_8h__dep__incl.map new file mode 100644 index 0000000..28e73db --- /dev/null +++ b/stm32f4xx__tim_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__tim_8h__dep__incl.md5 b/stm32f4xx__tim_8h__dep__incl.md5 new file mode 100644 index 0000000..41cb04e --- /dev/null +++ b/stm32f4xx__tim_8h__dep__incl.md5 @@ -0,0 +1 @@ +62429d1316f604af0ed2417048db1476 \ No newline at end of file diff --git a/stm32f4xx__tim_8h__dep__incl.png b/stm32f4xx__tim_8h__dep__incl.png new file mode 100644 index 0000000..46c01f9 Binary files /dev/null and b/stm32f4xx__tim_8h__dep__incl.png differ diff --git a/stm32f4xx__tim_8h__incl.map b/stm32f4xx__tim_8h__incl.map new file mode 100644 index 0000000..521897c --- /dev/null +++ b/stm32f4xx__tim_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__tim_8h__incl.md5 b/stm32f4xx__tim_8h__incl.md5 new file mode 100644 index 0000000..49d6f0b --- /dev/null +++ b/stm32f4xx__tim_8h__incl.md5 @@ -0,0 +1 @@ +c89dafc9aa0701265dfda181e88866f0 \ No newline at end of file diff --git a/stm32f4xx__tim_8h__incl.png b/stm32f4xx__tim_8h__incl.png new file mode 100644 index 0000000..32448f9 Binary files /dev/null and b/stm32f4xx__tim_8h__incl.png differ diff --git a/stm32f4xx__tim_8h_source.html b/stm32f4xx__tim_8h_source.html new file mode 100644 index 0000000..debc60e --- /dev/null +++ b/stm32f4xx__tim_8h_source.html @@ -0,0 +1,913 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_tim.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + + + +
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+ + +
+ +
+ + +
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+
+
stm32f4xx_tim.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_TIM_H
+
31 #define __STM32F4xx_TIM_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
55 typedef struct
+
56 {
+
57  uint16_t TIM_Prescaler;
+
60  uint16_t TIM_CounterMode;
+
63  uint32_t TIM_Period;
+
67  uint16_t TIM_ClockDivision;
+
70  uint8_t TIM_RepetitionCounter;
+
78 } TIM_TimeBaseInitTypeDef;
+
79 
+
84 typedef struct
+
85 {
+
86  uint16_t TIM_OCMode;
+
89  uint16_t TIM_OutputState;
+
92  uint16_t TIM_OutputNState;
+
96  uint32_t TIM_Pulse;
+
99  uint16_t TIM_OCPolarity;
+
102  uint16_t TIM_OCNPolarity;
+
106  uint16_t TIM_OCIdleState;
+
110  uint16_t TIM_OCNIdleState;
+
113 } TIM_OCInitTypeDef;
+
114 
+
119 typedef struct
+
120 {
+
121 
+
122  uint16_t TIM_Channel;
+
125  uint16_t TIM_ICPolarity;
+
128  uint16_t TIM_ICSelection;
+
131  uint16_t TIM_ICPrescaler;
+
134  uint16_t TIM_ICFilter;
+
136 } TIM_ICInitTypeDef;
+
137 
+
143 typedef struct
+
144 {
+
145 
+
146  uint16_t TIM_OSSRState;
+
149  uint16_t TIM_OSSIState;
+
152  uint16_t TIM_LOCKLevel;
+
155  uint16_t TIM_DeadTime;
+
159  uint16_t TIM_Break;
+
162  uint16_t TIM_BreakPolarity;
+
165  uint16_t TIM_AutomaticOutput;
+
167 } TIM_BDTRInitTypeDef;
+
168 
+
169 /* Exported constants --------------------------------------------------------*/
+
170 
+
175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
176  ((PERIPH) == TIM2) || \
+
177  ((PERIPH) == TIM3) || \
+
178  ((PERIPH) == TIM4) || \
+
179  ((PERIPH) == TIM5) || \
+
180  ((PERIPH) == TIM6) || \
+
181  ((PERIPH) == TIM7) || \
+
182  ((PERIPH) == TIM8) || \
+
183  ((PERIPH) == TIM9) || \
+
184  ((PERIPH) == TIM10) || \
+
185  ((PERIPH) == TIM11) || \
+
186  ((PERIPH) == TIM12) || \
+
187  (((PERIPH) == TIM13) || \
+
188  ((PERIPH) == TIM14)))
+
189 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */
+
190 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
191  ((PERIPH) == TIM2) || \
+
192  ((PERIPH) == TIM3) || \
+
193  ((PERIPH) == TIM4) || \
+
194  ((PERIPH) == TIM5) || \
+
195  ((PERIPH) == TIM8) || \
+
196  ((PERIPH) == TIM9) || \
+
197  ((PERIPH) == TIM10) || \
+
198  ((PERIPH) == TIM11) || \
+
199  ((PERIPH) == TIM12) || \
+
200  ((PERIPH) == TIM13) || \
+
201  ((PERIPH) == TIM14))
+
202 
+
203 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
+
204 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
205  ((PERIPH) == TIM2) || \
+
206  ((PERIPH) == TIM3) || \
+
207  ((PERIPH) == TIM4) || \
+
208  ((PERIPH) == TIM5) || \
+
209  ((PERIPH) == TIM8) || \
+
210  ((PERIPH) == TIM9) || \
+
211  ((PERIPH) == TIM12))
+
212 /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
+
213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
214  ((PERIPH) == TIM2) || \
+
215  ((PERIPH) == TIM3) || \
+
216  ((PERIPH) == TIM4) || \
+
217  ((PERIPH) == TIM5) || \
+
218  ((PERIPH) == TIM8))
+
219 /* LIST4: TIM1 and TIM8 */
+
220 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
221  ((PERIPH) == TIM8))
+
222 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+
223 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+
224  ((PERIPH) == TIM2) || \
+
225  ((PERIPH) == TIM3) || \
+
226  ((PERIPH) == TIM4) || \
+
227  ((PERIPH) == TIM5) || \
+
228  ((PERIPH) == TIM6) || \
+
229  ((PERIPH) == TIM7) || \
+
230  ((PERIPH) == TIM8))
+
231 /* LIST6: TIM2, TIM5 and TIM11 */
+
232 #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
+
233  ((TIMx) == TIM5) || \
+
234  ((TIMx) == TIM11))
+
235 
+
240 #define TIM_OCMode_Timing ((uint16_t)0x0000)
+
241 #define TIM_OCMode_Active ((uint16_t)0x0010)
+
242 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
+
243 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
+
244 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+
245 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+
246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+
247  ((MODE) == TIM_OCMode_Active) || \
+
248  ((MODE) == TIM_OCMode_Inactive) || \
+
249  ((MODE) == TIM_OCMode_Toggle)|| \
+
250  ((MODE) == TIM_OCMode_PWM1) || \
+
251  ((MODE) == TIM_OCMode_PWM2))
+
252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+
253  ((MODE) == TIM_OCMode_Active) || \
+
254  ((MODE) == TIM_OCMode_Inactive) || \
+
255  ((MODE) == TIM_OCMode_Toggle)|| \
+
256  ((MODE) == TIM_OCMode_PWM1) || \
+
257  ((MODE) == TIM_OCMode_PWM2) || \
+
258  ((MODE) == TIM_ForcedAction_Active) || \
+
259  ((MODE) == TIM_ForcedAction_InActive))
+
260 
+
268 #define TIM_OPMode_Single ((uint16_t)0x0008)
+
269 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+
270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+
271  ((MODE) == TIM_OPMode_Repetitive))
+
272 
+
280 #define TIM_Channel_1 ((uint16_t)0x0000)
+
281 #define TIM_Channel_2 ((uint16_t)0x0004)
+
282 #define TIM_Channel_3 ((uint16_t)0x0008)
+
283 #define TIM_Channel_4 ((uint16_t)0x000C)
+
284 
+
285 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+
286  ((CHANNEL) == TIM_Channel_2) || \
+
287  ((CHANNEL) == TIM_Channel_3) || \
+
288  ((CHANNEL) == TIM_Channel_4))
+
289 
+
290 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+
291  ((CHANNEL) == TIM_Channel_2))
+
292 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+
293  ((CHANNEL) == TIM_Channel_2) || \
+
294  ((CHANNEL) == TIM_Channel_3))
+
295 
+
303 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
+
304 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
+
305 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
+
306 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+
307  ((DIV) == TIM_CKD_DIV2) || \
+
308  ((DIV) == TIM_CKD_DIV4))
+
309 
+
317 #define TIM_CounterMode_Up ((uint16_t)0x0000)
+
318 #define TIM_CounterMode_Down ((uint16_t)0x0010)
+
319 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+
320 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+
321 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+
322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+
323  ((MODE) == TIM_CounterMode_Down) || \
+
324  ((MODE) == TIM_CounterMode_CenterAligned1) || \
+
325  ((MODE) == TIM_CounterMode_CenterAligned2) || \
+
326  ((MODE) == TIM_CounterMode_CenterAligned3))
+
327 
+
335 #define TIM_OCPolarity_High ((uint16_t)0x0000)
+
336 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
+
337 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+
338  ((POLARITY) == TIM_OCPolarity_Low))
+
339 
+
347 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
+
348 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+
349 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+
350  ((POLARITY) == TIM_OCNPolarity_Low))
+
351 
+
359 #define TIM_OutputState_Disable ((uint16_t)0x0000)
+
360 #define TIM_OutputState_Enable ((uint16_t)0x0001)
+
361 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+
362  ((STATE) == TIM_OutputState_Enable))
+
363 
+
371 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
+
372 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
+
373 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+
374  ((STATE) == TIM_OutputNState_Enable))
+
375 
+
383 #define TIM_CCx_Enable ((uint16_t)0x0001)
+
384 #define TIM_CCx_Disable ((uint16_t)0x0000)
+
385 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+
386  ((CCX) == TIM_CCx_Disable))
+
387 
+
395 #define TIM_CCxN_Enable ((uint16_t)0x0004)
+
396 #define TIM_CCxN_Disable ((uint16_t)0x0000)
+
397 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+
398  ((CCXN) == TIM_CCxN_Disable))
+
399 
+
407 #define TIM_Break_Enable ((uint16_t)0x1000)
+
408 #define TIM_Break_Disable ((uint16_t)0x0000)
+
409 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+
410  ((STATE) == TIM_Break_Disable))
+
411 
+
419 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+
420 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
+
421 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+
422  ((POLARITY) == TIM_BreakPolarity_High))
+
423 
+
431 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+
432 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+
433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+
434  ((STATE) == TIM_AutomaticOutput_Disable))
+
435 
+
443 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+
444 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+
445 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+
446 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+
447 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+
448  ((LEVEL) == TIM_LOCKLevel_1) || \
+
449  ((LEVEL) == TIM_LOCKLevel_2) || \
+
450  ((LEVEL) == TIM_LOCKLevel_3))
+
451 
+
459 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
+
460 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
+
461 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+
462  ((STATE) == TIM_OSSIState_Disable))
+
463 
+
471 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
+
472 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
+
473 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+
474  ((STATE) == TIM_OSSRState_Disable))
+
475 
+
483 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
+
484 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+
485 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+
486  ((STATE) == TIM_OCIdleState_Reset))
+
487 
+
495 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+
496 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+
497 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+
498  ((STATE) == TIM_OCNIdleState_Reset))
+
499 
+
507 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+
508 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+
509 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+
510 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+
511  ((POLARITY) == TIM_ICPolarity_Falling)|| \
+
512  ((POLARITY) == TIM_ICPolarity_BothEdge))
+
513 
+
521 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
+
523 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
+
525 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
+
526 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+
527  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+
528  ((SELECTION) == TIM_ICSelection_TRC))
+
529 
+
537 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
+
538 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
+
539 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
+
540 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
+
541 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+
542  ((PRESCALER) == TIM_ICPSC_DIV2) || \
+
543  ((PRESCALER) == TIM_ICPSC_DIV4) || \
+
544  ((PRESCALER) == TIM_ICPSC_DIV8))
+
545 
+
553 #define TIM_IT_Update ((uint16_t)0x0001)
+
554 #define TIM_IT_CC1 ((uint16_t)0x0002)
+
555 #define TIM_IT_CC2 ((uint16_t)0x0004)
+
556 #define TIM_IT_CC3 ((uint16_t)0x0008)
+
557 #define TIM_IT_CC4 ((uint16_t)0x0010)
+
558 #define TIM_IT_COM ((uint16_t)0x0020)
+
559 #define TIM_IT_Trigger ((uint16_t)0x0040)
+
560 #define TIM_IT_Break ((uint16_t)0x0080)
+
561 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
562 
+
563 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+
564  ((IT) == TIM_IT_CC1) || \
+
565  ((IT) == TIM_IT_CC2) || \
+
566  ((IT) == TIM_IT_CC3) || \
+
567  ((IT) == TIM_IT_CC4) || \
+
568  ((IT) == TIM_IT_COM) || \
+
569  ((IT) == TIM_IT_Trigger) || \
+
570  ((IT) == TIM_IT_Break))
+
571 
+
579 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
+
580 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
+
581 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
+
582 #define TIM_DMABase_DIER ((uint16_t)0x0003)
+
583 #define TIM_DMABase_SR ((uint16_t)0x0004)
+
584 #define TIM_DMABase_EGR ((uint16_t)0x0005)
+
585 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+
586 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+
587 #define TIM_DMABase_CCER ((uint16_t)0x0008)
+
588 #define TIM_DMABase_CNT ((uint16_t)0x0009)
+
589 #define TIM_DMABase_PSC ((uint16_t)0x000A)
+
590 #define TIM_DMABase_ARR ((uint16_t)0x000B)
+
591 #define TIM_DMABase_RCR ((uint16_t)0x000C)
+
592 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+
593 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+
594 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+
595 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+
596 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
+
597 #define TIM_DMABase_DCR ((uint16_t)0x0012)
+
598 #define TIM_DMABase_OR ((uint16_t)0x0013)
+
599 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+
600  ((BASE) == TIM_DMABase_CR2) || \
+
601  ((BASE) == TIM_DMABase_SMCR) || \
+
602  ((BASE) == TIM_DMABase_DIER) || \
+
603  ((BASE) == TIM_DMABase_SR) || \
+
604  ((BASE) == TIM_DMABase_EGR) || \
+
605  ((BASE) == TIM_DMABase_CCMR1) || \
+
606  ((BASE) == TIM_DMABase_CCMR2) || \
+
607  ((BASE) == TIM_DMABase_CCER) || \
+
608  ((BASE) == TIM_DMABase_CNT) || \
+
609  ((BASE) == TIM_DMABase_PSC) || \
+
610  ((BASE) == TIM_DMABase_ARR) || \
+
611  ((BASE) == TIM_DMABase_RCR) || \
+
612  ((BASE) == TIM_DMABase_CCR1) || \
+
613  ((BASE) == TIM_DMABase_CCR2) || \
+
614  ((BASE) == TIM_DMABase_CCR3) || \
+
615  ((BASE) == TIM_DMABase_CCR4) || \
+
616  ((BASE) == TIM_DMABase_BDTR) || \
+
617  ((BASE) == TIM_DMABase_DCR) || \
+
618  ((BASE) == TIM_DMABase_OR))
+
619 
+
627 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+
628 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+
629 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+
630 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+
631 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+
632 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+
633 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+
634 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+
635 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+
636 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+
637 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+
638 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+
639 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+
640 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+
641 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+
642 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+
643 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+
644 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+
645 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+
646  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+
647  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+
648  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+
649  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+
650  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+
651  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+
652  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+
653  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+
654  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+
655  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+
656  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+
657  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+
658  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+
659  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+
660  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+
661  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+
662  ((LENGTH) == TIM_DMABurstLength_18Transfers))
+
663 
+
671 #define TIM_DMA_Update ((uint16_t)0x0100)
+
672 #define TIM_DMA_CC1 ((uint16_t)0x0200)
+
673 #define TIM_DMA_CC2 ((uint16_t)0x0400)
+
674 #define TIM_DMA_CC3 ((uint16_t)0x0800)
+
675 #define TIM_DMA_CC4 ((uint16_t)0x1000)
+
676 #define TIM_DMA_COM ((uint16_t)0x2000)
+
677 #define TIM_DMA_Trigger ((uint16_t)0x4000)
+
678 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
679 
+
688 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+
689 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+
690 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+
691 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+
692 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+
693  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+
694  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+
695  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+
696 
+
704 #define TIM_TS_ITR0 ((uint16_t)0x0000)
+
705 #define TIM_TS_ITR1 ((uint16_t)0x0010)
+
706 #define TIM_TS_ITR2 ((uint16_t)0x0020)
+
707 #define TIM_TS_ITR3 ((uint16_t)0x0030)
+
708 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+
709 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+
710 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+
711 #define TIM_TS_ETRF ((uint16_t)0x0070)
+
712 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+
713  ((SELECTION) == TIM_TS_ITR1) || \
+
714  ((SELECTION) == TIM_TS_ITR2) || \
+
715  ((SELECTION) == TIM_TS_ITR3) || \
+
716  ((SELECTION) == TIM_TS_TI1F_ED) || \
+
717  ((SELECTION) == TIM_TS_TI1FP1) || \
+
718  ((SELECTION) == TIM_TS_TI2FP2) || \
+
719  ((SELECTION) == TIM_TS_ETRF))
+
720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+
721  ((SELECTION) == TIM_TS_ITR1) || \
+
722  ((SELECTION) == TIM_TS_ITR2) || \
+
723  ((SELECTION) == TIM_TS_ITR3))
+
724 
+
732 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+
733 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+
734 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+
735 
+
743 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+
744 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+
745 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+
746  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+
747 
+
755 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+
756 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+
757 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+
758  ((RELOAD) == TIM_PSCReloadMode_Immediate))
+
759 
+
767 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
+
768 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+
769 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+
770  ((ACTION) == TIM_ForcedAction_InActive))
+
771 
+
779 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+
780 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+
781 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+
782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+
783  ((MODE) == TIM_EncoderMode_TI2) || \
+
784  ((MODE) == TIM_EncoderMode_TI12))
+
785 
+
794 #define TIM_EventSource_Update ((uint16_t)0x0001)
+
795 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
+
796 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
+
797 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
+
798 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
+
799 #define TIM_EventSource_COM ((uint16_t)0x0020)
+
800 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
+
801 #define TIM_EventSource_Break ((uint16_t)0x0080)
+
802 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
803 
+
812 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
+
815 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
+
816 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+
817  ((SOURCE) == TIM_UpdateSource_Regular))
+
818 
+
826 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
+
827 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
+
828 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+
829  ((STATE) == TIM_OCPreload_Disable))
+
830 
+
838 #define TIM_OCFast_Enable ((uint16_t)0x0004)
+
839 #define TIM_OCFast_Disable ((uint16_t)0x0000)
+
840 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+
841  ((STATE) == TIM_OCFast_Disable))
+
842 
+
851 #define TIM_OCClear_Enable ((uint16_t)0x0080)
+
852 #define TIM_OCClear_Disable ((uint16_t)0x0000)
+
853 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+
854  ((STATE) == TIM_OCClear_Disable))
+
855 
+
863 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+
864 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+
865 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
+
866 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+
867 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+
868 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+
869 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+
870 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+
871 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+
872  ((SOURCE) == TIM_TRGOSource_Enable) || \
+
873  ((SOURCE) == TIM_TRGOSource_Update) || \
+
874  ((SOURCE) == TIM_TRGOSource_OC1) || \
+
875  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+
876  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+
877  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+
878  ((SOURCE) == TIM_TRGOSource_OC4Ref))
+
879 
+
887 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+
888 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+
889 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+
890 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+
891 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+
892  ((MODE) == TIM_SlaveMode_Gated) || \
+
893  ((MODE) == TIM_SlaveMode_Trigger) || \
+
894  ((MODE) == TIM_SlaveMode_External1))
+
895 
+
903 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+
904 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+
905 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+
906  ((STATE) == TIM_MasterSlaveMode_Disable))
+
907 
+
914 #define TIM2_TIM8_TRGO ((uint16_t)0x0000)
+
915 #define TIM2_ETH_PTP ((uint16_t)0x0400)
+
916 #define TIM2_USBFS_SOF ((uint16_t)0x0800)
+
917 #define TIM2_USBHS_SOF ((uint16_t)0x0C00)
+
918 
+
919 #define TIM5_GPIO ((uint16_t)0x0000)
+
920 #define TIM5_LSI ((uint16_t)0x0040)
+
921 #define TIM5_LSE ((uint16_t)0x0080)
+
922 #define TIM5_RTC ((uint16_t)0x00C0)
+
923 
+
924 #define TIM11_GPIO ((uint16_t)0x0000)
+
925 #define TIM11_HSE ((uint16_t)0x0002)
+
926 
+
927 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
+
928  ((TIM_REMAP) == TIM2_ETH_PTP)||\
+
929  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
+
930  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
+
931  ((TIM_REMAP) == TIM5_GPIO)||\
+
932  ((TIM_REMAP) == TIM5_LSI)||\
+
933  ((TIM_REMAP) == TIM5_LSE)||\
+
934  ((TIM_REMAP) == TIM5_RTC)||\
+
935  ((TIM_REMAP) == TIM11_GPIO)||\
+
936  ((TIM_REMAP) == TIM11_HSE))
+
937 
+
945 #define TIM_FLAG_Update ((uint16_t)0x0001)
+
946 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
+
947 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
+
948 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
+
949 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
+
950 #define TIM_FLAG_COM ((uint16_t)0x0020)
+
951 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
+
952 #define TIM_FLAG_Break ((uint16_t)0x0080)
+
953 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+
954 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+
955 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+
956 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+
957 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+
958  ((FLAG) == TIM_FLAG_CC1) || \
+
959  ((FLAG) == TIM_FLAG_CC2) || \
+
960  ((FLAG) == TIM_FLAG_CC3) || \
+
961  ((FLAG) == TIM_FLAG_CC4) || \
+
962  ((FLAG) == TIM_FLAG_COM) || \
+
963  ((FLAG) == TIM_FLAG_Trigger) || \
+
964  ((FLAG) == TIM_FLAG_Break) || \
+
965  ((FLAG) == TIM_FLAG_CC1OF) || \
+
966  ((FLAG) == TIM_FLAG_CC2OF) || \
+
967  ((FLAG) == TIM_FLAG_CC3OF) || \
+
968  ((FLAG) == TIM_FLAG_CC4OF))
+
969 
+
978 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
979 
+
987 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+
988 
+
996 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+
997 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+
998 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+
999 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+
1000 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+
1001 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+
1002 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+
1003 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+
1004 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+
1005 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+
1006 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+
1007 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+
1008 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+
1009 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+
1010 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+
1011 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+
1012 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+
1013 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+
1014 
+
1022 /* Exported macro ------------------------------------------------------------*/
+
1023 /* Exported functions --------------------------------------------------------*/
+
1024 
+
1025 /* TimeBase management ********************************************************/
+
1026 void TIM_DeInit(TIM_TypeDef* TIMx);
+
1027 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+
1028 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+
1029 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+
1030 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+
1031 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+
1032 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+
1033 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+
1034 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+
1035 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1036 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+
1037 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1038 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+
1039 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+
1040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1041 
+
1042 /* Output Compare management **************************************************/
+
1043 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+
1044 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+
1045 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+
1046 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+
1047 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+
1048 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+
1049 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+
1050 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+
1051 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+
1052 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+
1053 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+
1054 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+
1055 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+
1056 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+
1057 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+
1058 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+
1059 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+
1060 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+
1061 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+
1062 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+
1063 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+
1064 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+
1065 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+
1066 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+
1067 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+
1068 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+
1069 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+
1070 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+
1071 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+
1072 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+
1073 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+
1074 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+
1075 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+
1076 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+
1077 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+
1078 
+
1079 /* Input Capture management ***************************************************/
+
1080 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+
1081 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+
1082 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+
1083 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+
1084 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+
1085 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+
1086 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+
1087 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
1088 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
1089 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
1090 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
1091 
+
1092 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/
+
1093 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+
1094 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+
1095 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1096 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1097 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1098 
+
1099 /* Interrupts, DMA and flags management ***************************************/
+
1100 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+
1101 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+
1102 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+
1103 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+
1104 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
1105 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
1106 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+
1107 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+
1108 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1109 
+
1110 /* Clocks management **********************************************************/
+
1111 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+
1112 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+
1113 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+
1114  uint16_t TIM_ICPolarity, uint16_t ICFilter);
+
1115 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+
1116  uint16_t ExtTRGFilter);
+
1117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+
1118  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
1119 
+
1120 /* Synchronization management *************************************************/
+
1121 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+
1122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+
1123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+
1124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+
1125 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+
1126  uint16_t ExtTRGFilter);
+
1127 
+
1128 /* Specific interface management **********************************************/
+
1129 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+
1130  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+
1131 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
1132 
+
1133 /* Specific remapping management **********************************************/
+
1134 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
1135 
+
1136 #ifdef __cplusplus
+
1137 }
+
1138 #endif
+
1139 
+
1140 #endif /*__STM32F4xx_TIM_H */
+
1141 
+
1150 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
TIM_SelectHallSensor
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIMx's Hall sensor interface.
Definition: stm32f4xx_tim.c:3122
+
TIM_CtrlPWMOutputs
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the TIM peripheral Main Outputs.
Definition: stm32f4xx_tim.c:2265
+
TIM_SelectCCDMA
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIMx peripheral Capture Compare DMA source.
Definition: stm32f4xx_tim.c:2644
+
TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
uint8_t TIM_RepetitionCounter
Definition: stm32f4xx_tim.h:70
+
TIM_SetCompare2
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint32_t Compare2)
Sets the TIMx Capture Compare2 Register value.
Definition: stm32f4xx_tim.c:1076
+
TIM_Cmd
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables the specified TIM peripheral.
Definition: stm32f4xx_tim.c:592
+
TIM_ClearOC4Ref
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF4 signal on an external event.
Definition: stm32f4xx_tim.c:1564
+
TIM_OC3FastConfig
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 3 Fast feature.
Definition: stm32f4xx_tim.c:1416
+
TIM_GetPrescaler
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
Gets the TIMx Prescaler value.
Definition: stm32f4xx_tim.c:452
+
TIM_SetIC2Prescaler
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 2 prescaler.
Definition: stm32f4xx_tim.c:2120
+
TIM_OCInitTypeDef::TIM_OCNPolarity
uint16_t TIM_OCNPolarity
Definition: stm32f4xx_tim.h:102
+
TIM_SetIC3Prescaler
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 3 prescaler.
Definition: stm32f4xx_tim.c:2144
+
TIM_OCInitTypeDef::TIM_OCNIdleState
uint16_t TIM_OCNIdleState
Definition: stm32f4xx_tim.h:110
+
TIM_OC3PolarityConfig
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 3 polarity.
Definition: stm32f4xx_tim.c:1701
+
TIM_ICInitTypeDef::TIM_ICFilter
uint16_t TIM_ICFilter
Definition: stm32f4xx_tim.h:134
+
TIM_GetCapture2
uint32_t TIM_GetCapture2(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 2 value.
Definition: stm32f4xx_tim.c:2047
+
TIM_OCStructInit
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
Fills each TIM_OCInitStruct member with its default value.
Definition: stm32f4xx_tim.c:978
+
TIM_OC3Init
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:835
+
TIM_ClearOC1Ref
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF1 signal on an external event.
Definition: stm32f4xx_tim.c:1476
+
TIM_SelectOnePulseMode
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
Selects the TIMx's One Pulse Mode.
Definition: stm32f4xx_tim.c:549
+
TIM_OC3PreloadConfig
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR3.
Definition: stm32f4xx_tim.c:1297
+
TIM_OC2NPolarityConfig
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 2N polarity.
Definition: stm32f4xx_tim.c:1674
+
TIM_ITRxExternalClockConfig
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Configures the TIMx Internal Trigger as External Clock.
Definition: stm32f4xx_tim.c:2704
+
TIM_SelectCOM
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
Selects the TIM peripheral Commutation event.
Definition: stm32f4xx_tim.c:2290
+
TIM_OC4FastConfig
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 4 Fast feature.
Definition: stm32f4xx_tim.c:1446
+
TIM_ForcedOC3Config
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 3 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1181
+
TIM_ETRConfig
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
Definition: stm32f4xx_tim.c:3012
+
TIM_BDTRInitTypeDef::TIM_BreakPolarity
uint16_t TIM_BreakPolarity
Definition: stm32f4xx_tim.h:162
+
TIM_ICInitTypeDef::TIM_ICPolarity
uint16_t TIM_ICPolarity
Definition: stm32f4xx_tim.h:125
+
TIM_ARRPreloadConfig
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or disables TIMx peripheral Preload register on ARR.
Definition: stm32f4xx_tim.c:522
+
TIM_GetCapture3
uint32_t TIM_GetCapture3(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 3 value.
Definition: stm32f4xx_tim.c:2061
+
TIM_CCxCmd
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
Enables or disables the TIM Capture Compare Channel x.
Definition: stm32f4xx_tim.c:1786
+
TIM_ETRClockMode2Config
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode2.
Definition: stm32f4xx_tim.c:2821
+
TIM_ForcedOC2Config
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 2 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1153
+
TIM_PrescalerConfig
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
Configures the TIMx Prescaler.
Definition: stm32f4xx_tim.c:360
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
TIM_OC1Init
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:673
+
TIM_OC2Init
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:754
+
TIM_BDTRInitTypeDef::TIM_OSSIState
uint16_t TIM_OSSIState
Definition: stm32f4xx_tim.h:149
+
TIM_ICStructInit
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
Fills each TIM_ICInitStruct member with its default value.
Definition: stm32f4xx_tim.c:1956
+
TIM_DMACmd
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
Enables or disables the TIMx's DMA Requests.
Definition: stm32f4xx_tim.c:2618
+
TIM_SetCounter
void TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
Sets the TIMx Counter Register value.
Definition: stm32f4xx_tim.c:409
+
TIM_TimeBaseInitTypeDef::TIM_CounterMode
uint16_t TIM_CounterMode
Definition: stm32f4xx_tim.h:60
+
TIM_SetCompare3
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint32_t Compare3)
Sets the TIMx Capture Compare3 Register value.
Definition: stm32f4xx_tim.c:1091
+
TIM_ETRClockMode1Config
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
Configures the External clock Mode1.
Definition: stm32f4xx_tim.c:2774
+
TIM_UpdateDisableConfig
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
Enables or Disables the TIMx Update event.
Definition: stm32f4xx_tim.c:468
+
TIM_ForcedOC1Config
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 1 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1124
+
TIM_ICInit
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct.
Definition: stm32f4xx_tim.c:1900
+
TIM_BDTRInitTypeDef::TIM_Break
uint16_t TIM_Break
Definition: stm32f4xx_tim.h:159
+
TIM_ICInitTypeDef::TIM_ICSelection
uint16_t TIM_ICSelection
Definition: stm32f4xx_tim.h:128
+
TIM_ClearFlag
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Clears the TIMx's pending flags.
Definition: stm32f4xx_tim.c:2485
+
TIM_SetIC4Prescaler
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 4 prescaler.
Definition: stm32f4xx_tim.c:2168
+
TIM_ClearOC3Ref
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF3 signal on an external event.
Definition: stm32f4xx_tim.c:1535
+
TIM_OCInitTypeDef
TIM Output Compare Init structure definition.
Definition: stm32f4xx_tim.h:84
+
TIM_BDTRConfig
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output ena...
Definition: stm32f4xx_tim.c:2221
+
TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition.
Definition: stm32f4xx_tim.h:55
+
TIM_CCPreloadControl
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
Definition: stm32f4xx_tim.c:2315
+
TIM_SelectMasterSlaveMode
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
Sets or Resets the TIMx Master/Slave Mode.
Definition: stm32f4xx_tim.c:2982
+
TIM_ClearOC2Ref
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
Clears or safeguards the OCREF2 signal on an external event.
Definition: stm32f4xx_tim.c:1506
+
TIM_OCInitTypeDef::TIM_OCPolarity
uint16_t TIM_OCPolarity
Definition: stm32f4xx_tim.h:99
+
TIM_TimeBaseInitTypeDef::TIM_ClockDivision
uint16_t TIM_ClockDivision
Definition: stm32f4xx_tim.h:67
+
TIM_SetCompare1
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint32_t Compare1)
Sets the TIMx Capture Compare1 Register value.
Definition: stm32f4xx_tim.c:1060
+
TIM_GetFlagStatus
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
Checks whether the specified TIM flag is set or not.
Definition: stm32f4xx_tim.c:2443
+
TIM_EncoderInterfaceConfig
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
Configures the TIMx Encoder Interface.
Definition: stm32f4xx_tim.c:3070
+
TIM_BDTRInitTypeDef::TIM_LOCKLevel
uint16_t TIM_LOCKLevel
Definition: stm32f4xx_tim.h:152
+
TIM_SetIC1Prescaler
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
Sets the TIMx Input Capture 1 prescaler.
Definition: stm32f4xx_tim.c:2095
+
TIM_SetClockDivision
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
Sets the TIMx Clock Division value.
Definition: stm32f4xx_tim.c:572
+
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:1283
+
TIM_OC1PreloadConfig
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR1.
Definition: stm32f4xx_tim.c:1238
+
TIM_ICInitTypeDef::TIM_ICPrescaler
uint16_t TIM_ICPrescaler
Definition: stm32f4xx_tim.h:131
+
TIM_SelectOCxM
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
Selects the TIM Output Compare Mode.
Definition: stm32f4xx_tim.c:1014
+
TIM_ClearITPendingBit
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Clears the TIMx's interrupt pending bits.
Definition: stm32f4xx_tim.c:2554
+
TIM_OCInitTypeDef::TIM_Pulse
uint32_t TIM_Pulse
Definition: stm32f4xx_tim.h:96
+
TIM_BDTRInitTypeDef::TIM_OSSRState
uint16_t TIM_OSSRState
Definition: stm32f4xx_tim.h:146
+
TIM_OC1NPolarityConfig
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 1N polarity.
Definition: stm32f4xx_tim.c:1620
+
TIM_GetCapture1
uint32_t TIM_GetCapture1(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 1 value.
Definition: stm32f4xx_tim.c:2032
+
TIM_GetCounter
uint32_t TIM_GetCounter(TIM_TypeDef *TIMx)
Gets the TIMx Counter value.
Definition: stm32f4xx_tim.c:438
+
TIM_GenerateEvent
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
Configures the TIMx event to be generate by software.
Definition: stm32f4xx_tim.c:2410
+
TIM_BDTRInitTypeDef::TIM_DeadTime
uint16_t TIM_DeadTime
Definition: stm32f4xx_tim.h:155
+
TIM_UpdateRequestConfig
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
Configures the TIMx Update Request Interrupt source.
Definition: stm32f4xx_tim.c:497
+
TIM_OC1PolarityConfig
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 1 polarity.
Definition: stm32f4xx_tim.c:1593
+
TIM_ICInitTypeDef::TIM_Channel
uint16_t TIM_Channel
Definition: stm32f4xx_tim.h:122
+
TIM_OC4PolarityConfig
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 4 polarity.
Definition: stm32f4xx_tim.c:1755
+
TIM_OCInitTypeDef::TIM_OutputNState
uint16_t TIM_OutputNState
Definition: stm32f4xx_tim.h:92
+
TIM_TIxExternalClockConfig
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter)
Configures the TIMx Trigger as External Clock.
Definition: stm32f4xx_tim.c:2734
+
TIM_CounterModeConfig
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
Specifies the TIMx Counter Mode to be used.
Definition: stm32f4xx_tim.c:383
+
TIM_TimeBaseInit
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeB...
Definition: stm32f4xx_tim.c:288
+
TIM_CCxNCmd
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
Enables or disables the TIM Capture Compare Channel xN.
Definition: stm32f4xx_tim.c:1816
+
TIM_GetITStatus
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
Checks whether the TIM interrupt has occurred or not.
Definition: stm32f4xx_tim.c:2513
+
TIM_ForcedOC4Config
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
Forces the TIMx output 4 waveform to active or inactive level.
Definition: stm32f4xx_tim.c:1210
+
TIM_TimeBaseInitTypeDef::TIM_Prescaler
uint16_t TIM_Prescaler
Definition: stm32f4xx_tim.h:57
+
TIM_OCInitTypeDef::TIM_OCIdleState
uint16_t TIM_OCIdleState
Definition: stm32f4xx_tim.h:106
+
TIM_SelectInputTrigger
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
Selects the Input Trigger source.
Definition: stm32f4xx_tim.c:2892
+
TIM_ICInitTypeDef
TIM Input Capture Init structure definition.
Definition: stm32f4xx_tim.h:119
+
TIM_SelectSlaveMode
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
Selects the TIMx Slave Mode.
Definition: stm32f4xx_tim.c:2959
+
TIM_BDTRStructInit
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
Fills each TIM_BDTRInitStruct member with its default value.
Definition: stm32f4xx_tim.c:2246
+
TIM_OC2PolarityConfig
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
Configures the TIMx channel 2 polarity.
Definition: stm32f4xx_tim.c:1647
+
TIM_TimeBaseInitTypeDef::TIM_Period
uint32_t TIM_Period
Definition: stm32f4xx_tim.h:63
+
TIM_SetAutoreload
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint32_t Autoreload)
Sets the TIMx Autoreload Register value.
Definition: stm32f4xx_tim.c:424
+
TIM_DeInit
void TIM_DeInit(TIM_TypeDef *TIMx)
Deinitializes the TIMx peripheral registers to their default reset values.
Definition: stm32f4xx_tim.c:200
+
TIM_OC1FastConfig
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 1 Fast feature.
Definition: stm32f4xx_tim.c:1355
+
TIM_GetCapture4
uint32_t TIM_GetCapture4(TIM_TypeDef *TIMx)
Gets the TIMx Input Capture 4 value.
Definition: stm32f4xx_tim.c:2075
+
TIM_DMAConfig
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
Configures the TIMx's DMA interface.
Definition: stm32f4xx_tim.c:2591
+
TIM_TimeBaseStructInit
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
Fills each TIM_TimeBaseInitStruct member with its default value.
Definition: stm32f4xx_tim.c:340
+
TIM_ITConfig
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
Enables or disables the specified TIM interrupts.
Definition: stm32f4xx_tim.c:2372
+
TIM_SelectOutputTrigger
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
Selects the TIMx Trigger Output Mode.
Definition: stm32f4xx_tim.c:2935
+
TIM_InternalClockConfig
void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
Configures the TIMx internal Clock.
Definition: stm32f4xx_tim.c:2683
+
TIM_OC2PreloadConfig
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR2.
Definition: stm32f4xx_tim.c:1268
+
TIM_RemapConfig
void TIM_RemapConfig(TIM_TypeDef *TIMx, uint16_t TIM_Remap)
Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
Definition: stm32f4xx_tim.c:3173
+
TIM_OC2FastConfig
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
Configures the TIMx Output Compare 2 Fast feature.
Definition: stm32f4xx_tim.c:1386
+
TIM_BDTRInitTypeDef::TIM_AutomaticOutput
uint16_t TIM_AutomaticOutput
Definition: stm32f4xx_tim.h:165
+
TIM_OC4PreloadConfig
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
Enables or disables the TIMx peripheral Preload register on CCR4.
Definition: stm32f4xx_tim.c:1326
+
TIM_OC3NPolarityConfig
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
Configures the TIMx Channel 3N polarity.
Definition: stm32f4xx_tim.c:1728
+
TIM_OCInitTypeDef::TIM_OutputState
uint16_t TIM_OutputState
Definition: stm32f4xx_tim.h:89
+
TIM_BDTRInitTypeDef
BDTR structure definition.
Definition: stm32f4xx_tim.h:143
+
TIM_SetCompare4
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint32_t Compare4)
Sets the TIMx Capture Compare4 Register value.
Definition: stm32f4xx_tim.c:1106
+
TIM_PWMIConfig
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measur...
Definition: stm32f4xx_tim.c:1975
+
TIM_OCInitTypeDef::TIM_OCMode
uint16_t TIM_OCMode
Definition: stm32f4xx_tim.h:86
+
TIM_OC4Init
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct.
Definition: stm32f4xx_tim.c:915
+
+ +
+Generated on Sun May 10 2015 15:15:17 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__usart_8c.html b/stm32f4xx__usart_8c.html new file mode 100644 index 0000000..8d10c9b --- /dev/null +++ b/stm32f4xx__usart_8c.html @@ -0,0 +1,286 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/src/stm32f4xx_usart.c File Reference + + + + + + + + + + +
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+Macros | +Functions
+
+
stm32f4xx_usart.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART): +More...

+
#include "stm32f4xx_usart.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_usart.c:
+
+
+ + +
+
+ + + + + + + + + +

+Macros

#define CR1_CLEAR_MASK
 
#define CR2_CLOCK_CLEAR_MASK
 
#define CR3_CLEAR_MASK   ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
 
+#define IT_MASK   ((uint16_t)0x001F)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USART_DeInit (USART_TypeDef *USARTx)
 Deinitializes the USARTx peripheral registers to their default reset values. More...
 
void USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
 Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct . More...
 
void USART_StructInit (USART_InitTypeDef *USART_InitStruct)
 Fills each USART_InitStruct member with its default value. More...
 
void USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
 Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct . More...
 
void USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
 Fills each USART_ClockInitStruct member with its default value. More...
 
void USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the specified USART peripheral. More...
 
void USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
 Sets the system clock prescaler. More...
 
void USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's 8x oversampling mode. More...
 
void USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's one bit sampling method. More...
 
void USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
 Transmits single data through the USARTx peripheral. More...
 
uint16_t USART_ReceiveData (USART_TypeDef *USARTx)
 Returns the most recent received data by the USARTx peripheral. More...
 
void USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
 Sets the address of the USART node. More...
 
void USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Determines if the USART is in mute mode or not. More...
 
void USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
 Selects the USART WakeUp method. More...
 
void USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
 Sets the USART LIN Break detection length. More...
 
void USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's LIN mode. More...
 
void USART_SendBreak (USART_TypeDef *USARTx)
 Transmits break characters. More...
 
void USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Half Duplex communication. More...
 
void USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
 Sets the specified USART guard time. More...
 
void USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Smart Card mode. More...
 
void USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables NACK transmission. More...
 
void USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
 Configures the USART's IrDA interface. More...
 
void USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's IrDA interface. More...
 
void USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
 Enables or disables the USART's DMA interface. More...
 
void USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
 Enables or disables the specified USART interrupts. More...
 
FlagStatus USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Checks whether the specified USART flag is set or not. More...
 
void USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Clears the USARTx's pending flags. More...
 
ITStatus USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
 Checks whether the specified USART interrupt has occurred or not. More...
 
void USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
 Clears the USARTx's interrupt pending bits. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Universal synchronous asynchronous receiver transmitter (USART):

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Initialization and Configuration
    • +
  • Data transfers
    • +
  • Multi-Processor Communication
    • +
  • LIN mode
    • +
  • Half-duplex mode
    • +
  • Smartcard mode
    • +
  • IrDA mode
    • +
  • DMA transfers management
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                       ##### How to use this driver #####
+===============================================================================
+   [..]
+     (#) Enable peripheral clock using the following functions
+         RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 
+         RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, 
+         UART4 or UART5.
+ 
+     (#) According to the USART mode, enable the GPIO clocks using 
+         RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
+         or/and SCLK). 
+ 
+     (#) Peripheral's alternate function: 
+       (++) Connect the pin to the desired peripherals' Alternate 
+           Function (AF) using GPIO_PinAFConfig() function
+       (++) Configure the desired pin in alternate function by:
+           GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+       (++) Select the type, pull-up/pull-down and output speed via 
+           GPIO_PuPd, GPIO_OType and GPIO_Speed members
+       (++) Call GPIO_Init() function
+         
+     (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+         flow control and Mode(Receiver/Transmitter) using the USART_Init()
+         function.
+ 
+     (#) For synchronous mode, enable the clock and program the polarity,
+         phase and last bit using the USART_ClockInit() function.
+ 
+     (#) Enable the NVIC and the corresponding interrupt using the function 
+        USART_ITConfig() if you need to use interrupt mode. 
+ 
+     (#) When using the DMA mode 
+       (++) Configure the DMA using DMA_Init() function
+       (++) Active the needed channel Request using USART_DMACmd() function
+  
+     (#) Enable the USART using the USART_Cmd() function.
+  
+     (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+   
+     -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+         for more details
+   
+   [..]        
+   In order to reach higher communication baudrates, it is possible to
+   enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
+   This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
+   and before calling the function USART_Init().
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__usart_8c__incl.map b/stm32f4xx__usart_8c__incl.map new file mode 100644 index 0000000..ed038b4 --- /dev/null +++ b/stm32f4xx__usart_8c__incl.map @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__usart_8c__incl.md5 b/stm32f4xx__usart_8c__incl.md5 new file mode 100644 index 0000000..8cbfd3c --- /dev/null +++ b/stm32f4xx__usart_8c__incl.md5 @@ -0,0 +1 @@ +1d0b6d546db93b5a0076e92ac813de4d \ No newline at end of file diff --git a/stm32f4xx__usart_8c__incl.png b/stm32f4xx__usart_8c__incl.png new file mode 100644 index 0000000..e8c6a96 Binary files /dev/null and b/stm32f4xx__usart_8c__incl.png differ diff --git a/stm32f4xx__usart_8h.html b/stm32f4xx__usart_8h.html new file mode 100644 index 0000000..be75703 --- /dev/null +++ b/stm32f4xx__usart_8h.html @@ -0,0 +1,453 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_usart.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+Classes | +Macros | +Functions
+
+
stm32f4xx_usart.h File Reference
+
+
+ +

This file contains all the functions prototypes for the USART firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_usart.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + +

+Classes

struct  USART_InitTypeDef
 USART Init Structure definition. More...
 
struct  USART_ClockInitTypeDef
 USART Clock Init Structure definition. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IS_USART_ALL_PERIPH(PERIPH)
 
#define IS_USART_1236_PERIPH(PERIPH)
 
+#define USART_WordLength_8b   ((uint16_t)0x0000)
 
+#define USART_WordLength_9b   ((uint16_t)0x1000)
 
#define IS_USART_WORD_LENGTH(LENGTH)
 
+#define USART_StopBits_1   ((uint16_t)0x0000)
 
+#define USART_StopBits_0_5   ((uint16_t)0x1000)
 
+#define USART_StopBits_2   ((uint16_t)0x2000)
 
+#define USART_StopBits_1_5   ((uint16_t)0x3000)
 
#define IS_USART_STOPBITS(STOPBITS)
 
+#define USART_Parity_No   ((uint16_t)0x0000)
 
+#define USART_Parity_Even   ((uint16_t)0x0400)
 
+#define USART_Parity_Odd   ((uint16_t)0x0600)
 
#define IS_USART_PARITY(PARITY)
 
+#define USART_Mode_Rx   ((uint16_t)0x0004)
 
+#define USART_Mode_Tx   ((uint16_t)0x0008)
 
+#define IS_USART_MODE(MODE)   ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
 
+#define USART_HardwareFlowControl_None   ((uint16_t)0x0000)
 
+#define USART_HardwareFlowControl_RTS   ((uint16_t)0x0100)
 
+#define USART_HardwareFlowControl_CTS   ((uint16_t)0x0200)
 
+#define USART_HardwareFlowControl_RTS_CTS   ((uint16_t)0x0300)
 
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)
 
+#define USART_Clock_Disable   ((uint16_t)0x0000)
 
+#define USART_Clock_Enable   ((uint16_t)0x0800)
 
#define IS_USART_CLOCK(CLOCK)
 
+#define USART_CPOL_Low   ((uint16_t)0x0000)
 
+#define USART_CPOL_High   ((uint16_t)0x0400)
 
+#define IS_USART_CPOL(CPOL)   (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
 
+#define USART_CPHA_1Edge   ((uint16_t)0x0000)
 
+#define USART_CPHA_2Edge   ((uint16_t)0x0200)
 
+#define IS_USART_CPHA(CPHA)   (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
 
+#define USART_LastBit_Disable   ((uint16_t)0x0000)
 
+#define USART_LastBit_Enable   ((uint16_t)0x0100)
 
#define IS_USART_LASTBIT(LASTBIT)
 
+#define USART_IT_PE   ((uint16_t)0x0028)
 
+#define USART_IT_TXE   ((uint16_t)0x0727)
 
+#define USART_IT_TC   ((uint16_t)0x0626)
 
+#define USART_IT_RXNE   ((uint16_t)0x0525)
 
+#define USART_IT_ORE_RX   ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
 
+#define USART_IT_IDLE   ((uint16_t)0x0424)
 
+#define USART_IT_LBD   ((uint16_t)0x0846)
 
+#define USART_IT_CTS   ((uint16_t)0x096A)
 
+#define USART_IT_ERR   ((uint16_t)0x0060)
 
+#define USART_IT_ORE_ER   ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
 
+#define USART_IT_NE   ((uint16_t)0x0260)
 
+#define USART_IT_FE   ((uint16_t)0x0160)
 
+#define USART_IT_ORE   USART_IT_ORE_ER
 
#define IS_USART_CONFIG_IT(IT)
 
#define IS_USART_GET_IT(IT)
 
#define IS_USART_CLEAR_IT(IT)
 
+#define USART_DMAReq_Tx   ((uint16_t)0x0080)
 
+#define USART_DMAReq_Rx   ((uint16_t)0x0040)
 
+#define IS_USART_DMAREQ(DMAREQ)   ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
 
+#define USART_WakeUp_IdleLine   ((uint16_t)0x0000)
 
+#define USART_WakeUp_AddressMark   ((uint16_t)0x0800)
 
#define IS_USART_WAKEUP(WAKEUP)
 
+#define USART_LINBreakDetectLength_10b   ((uint16_t)0x0000)
 
+#define USART_LINBreakDetectLength_11b   ((uint16_t)0x0020)
 
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH)
 
+#define USART_IrDAMode_LowPower   ((uint16_t)0x0004)
 
+#define USART_IrDAMode_Normal   ((uint16_t)0x0000)
 
#define IS_USART_IRDA_MODE(MODE)
 
+#define USART_FLAG_CTS   ((uint16_t)0x0200)
 
+#define USART_FLAG_LBD   ((uint16_t)0x0100)
 
+#define USART_FLAG_TXE   ((uint16_t)0x0080)
 
+#define USART_FLAG_TC   ((uint16_t)0x0040)
 
+#define USART_FLAG_RXNE   ((uint16_t)0x0020)
 
+#define USART_FLAG_IDLE   ((uint16_t)0x0010)
 
+#define USART_FLAG_ORE   ((uint16_t)0x0008)
 
+#define USART_FLAG_NE   ((uint16_t)0x0004)
 
+#define USART_FLAG_FE   ((uint16_t)0x0002)
 
+#define USART_FLAG_PE   ((uint16_t)0x0001)
 
#define IS_USART_FLAG(FLAG)
 
+#define IS_USART_CLEAR_FLAG(FLAG)   ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
 
+#define IS_USART_BAUDRATE(BAUDRATE)   (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
 
+#define IS_USART_ADDRESS(ADDRESS)   ((ADDRESS) <= 0xF)
 
+#define IS_USART_DATA(DATA)   ((DATA) <= 0x1FF)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USART_DeInit (USART_TypeDef *USARTx)
 Deinitializes the USARTx peripheral registers to their default reset values. More...
 
void USART_Init (USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
 Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct . More...
 
void USART_StructInit (USART_InitTypeDef *USART_InitStruct)
 Fills each USART_InitStruct member with its default value. More...
 
void USART_ClockInit (USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
 Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitStruct . More...
 
void USART_ClockStructInit (USART_ClockInitTypeDef *USART_ClockInitStruct)
 Fills each USART_ClockInitStruct member with its default value. More...
 
void USART_Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the specified USART peripheral. More...
 
void USART_SetPrescaler (USART_TypeDef *USARTx, uint8_t USART_Prescaler)
 Sets the system clock prescaler. More...
 
void USART_OverSampling8Cmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's 8x oversampling mode. More...
 
void USART_OneBitMethodCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's one bit sampling method. More...
 
void USART_SendData (USART_TypeDef *USARTx, uint16_t Data)
 Transmits single data through the USARTx peripheral. More...
 
uint16_t USART_ReceiveData (USART_TypeDef *USARTx)
 Returns the most recent received data by the USARTx peripheral. More...
 
void USART_SetAddress (USART_TypeDef *USARTx, uint8_t USART_Address)
 Sets the address of the USART node. More...
 
void USART_WakeUpConfig (USART_TypeDef *USARTx, uint16_t USART_WakeUp)
 Selects the USART WakeUp method. More...
 
void USART_ReceiverWakeUpCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Determines if the USART is in mute mode or not. More...
 
void USART_LINBreakDetectLengthConfig (USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
 Sets the USART LIN Break detection length. More...
 
void USART_LINCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's LIN mode. More...
 
void USART_SendBreak (USART_TypeDef *USARTx)
 Transmits break characters. More...
 
void USART_HalfDuplexCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Half Duplex communication. More...
 
void USART_SmartCardCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's Smart Card mode. More...
 
void USART_SmartCardNACKCmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables NACK transmission. More...
 
void USART_SetGuardTime (USART_TypeDef *USARTx, uint8_t USART_GuardTime)
 Sets the specified USART guard time. More...
 
void USART_IrDAConfig (USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
 Configures the USART's IrDA interface. More...
 
void USART_IrDACmd (USART_TypeDef *USARTx, FunctionalState NewState)
 Enables or disables the USART's IrDA interface. More...
 
void USART_DMACmd (USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
 Enables or disables the USART's DMA interface. More...
 
void USART_ITConfig (USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
 Enables or disables the specified USART interrupts. More...
 
FlagStatus USART_GetFlagStatus (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Checks whether the specified USART flag is set or not. More...
 
void USART_ClearFlag (USART_TypeDef *USARTx, uint16_t USART_FLAG)
 Clears the USARTx's pending flags. More...
 
ITStatus USART_GetITStatus (USART_TypeDef *USARTx, uint16_t USART_IT)
 Checks whether the specified USART interrupt has occurred or not. More...
 
void USART_ClearITPendingBit (USART_TypeDef *USARTx, uint16_t USART_IT)
 Clears the USARTx's interrupt pending bits. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the USART firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/stm32f4xx__usart_8h__dep__incl.map b/stm32f4xx__usart_8h__dep__incl.map new file mode 100644 index 0000000..3da26aa --- /dev/null +++ b/stm32f4xx__usart_8h__dep__incl.map @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__usart_8h__dep__incl.md5 b/stm32f4xx__usart_8h__dep__incl.md5 new file mode 100644 index 0000000..67afcb4 --- /dev/null +++ b/stm32f4xx__usart_8h__dep__incl.md5 @@ -0,0 +1 @@ +61b4ea23d1e043784e1c5c378b37b73d \ No newline at end of file diff --git a/stm32f4xx__usart_8h__dep__incl.png b/stm32f4xx__usart_8h__dep__incl.png new file mode 100644 index 0000000..c73ae77 Binary files /dev/null and b/stm32f4xx__usart_8h__dep__incl.png differ diff --git a/stm32f4xx__usart_8h__incl.map b/stm32f4xx__usart_8h__incl.map new file mode 100644 index 0000000..b869262 --- /dev/null +++ b/stm32f4xx__usart_8h__incl.map @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stm32f4xx__usart_8h__incl.md5 b/stm32f4xx__usart_8h__incl.md5 new file mode 100644 index 0000000..bca3ad5 --- /dev/null +++ b/stm32f4xx__usart_8h__incl.md5 @@ -0,0 +1 @@ +f54dd78567b821f903c5f3f1cb132972 \ No newline at end of file diff --git a/stm32f4xx__usart_8h__incl.png b/stm32f4xx__usart_8h__incl.png new file mode 100644 index 0000000..fed0221 Binary files /dev/null and b/stm32f4xx__usart_8h__incl.png differ diff --git a/stm32f4xx__usart_8h_source.html b/stm32f4xx__usart_8h_source.html new file mode 100644 index 0000000..a78d2ff --- /dev/null +++ b/stm32f4xx__usart_8h_source.html @@ -0,0 +1,376 @@ + + + + + + +discoverpixy: discovery/libs/StmCoreNPheriph/inc/stm32f4xx_usart.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+ + + + + + +
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+ + +
+ +
+ + +
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+
+
stm32f4xx_usart.h
+
+
+Go to the documentation of this file.
1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_USART_H
+
31 #define __STM32F4xx_USART_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 
+
54 typedef struct
+
55 {
+
56  uint32_t USART_BaudRate;
+
62  uint16_t USART_WordLength;
+
65  uint16_t USART_StopBits;
+
68  uint16_t USART_Parity;
+
75  uint16_t USART_Mode;
+
78  uint16_t USART_HardwareFlowControl;
+
81 } USART_InitTypeDef;
+
82 
+
87 typedef struct
+
88 {
+
89 
+
90  uint16_t USART_Clock;
+
93  uint16_t USART_CPOL;
+
96  uint16_t USART_CPHA;
+
99  uint16_t USART_LastBit;
+
102 } USART_ClockInitTypeDef;
+
103 
+
104 /* Exported constants --------------------------------------------------------*/
+
105 
+
110 #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+
111  ((PERIPH) == USART2) || \
+
112  ((PERIPH) == USART3) || \
+
113  ((PERIPH) == UART4) || \
+
114  ((PERIPH) == UART5) || \
+
115  ((PERIPH) == USART6) || \
+
116  ((PERIPH) == UART7) || \
+
117  ((PERIPH) == UART8))
+
118 
+
119 #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+
120  ((PERIPH) == USART2) || \
+
121  ((PERIPH) == USART3) || \
+
122  ((PERIPH) == USART6))
+
123 
+
128 #define USART_WordLength_8b ((uint16_t)0x0000)
+
129 #define USART_WordLength_9b ((uint16_t)0x1000)
+
130 
+
131 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+
132  ((LENGTH) == USART_WordLength_9b))
+
133 
+
141 #define USART_StopBits_1 ((uint16_t)0x0000)
+
142 #define USART_StopBits_0_5 ((uint16_t)0x1000)
+
143 #define USART_StopBits_2 ((uint16_t)0x2000)
+
144 #define USART_StopBits_1_5 ((uint16_t)0x3000)
+
145 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+
146  ((STOPBITS) == USART_StopBits_0_5) || \
+
147  ((STOPBITS) == USART_StopBits_2) || \
+
148  ((STOPBITS) == USART_StopBits_1_5))
+
149 
+
157 #define USART_Parity_No ((uint16_t)0x0000)
+
158 #define USART_Parity_Even ((uint16_t)0x0400)
+
159 #define USART_Parity_Odd ((uint16_t)0x0600)
+
160 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+
161  ((PARITY) == USART_Parity_Even) || \
+
162  ((PARITY) == USART_Parity_Odd))
+
163 
+
171 #define USART_Mode_Rx ((uint16_t)0x0004)
+
172 #define USART_Mode_Tx ((uint16_t)0x0008)
+
173 #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+
174 
+
181 #define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+
182 #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+
183 #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+
184 #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+
185 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+
186  (((CONTROL) == USART_HardwareFlowControl_None) || \
+
187  ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+
188  ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+
189  ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+
190 
+
197 #define USART_Clock_Disable ((uint16_t)0x0000)
+
198 #define USART_Clock_Enable ((uint16_t)0x0800)
+
199 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+
200  ((CLOCK) == USART_Clock_Enable))
+
201 
+
209 #define USART_CPOL_Low ((uint16_t)0x0000)
+
210 #define USART_CPOL_High ((uint16_t)0x0400)
+
211 #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
212 
+
221 #define USART_CPHA_1Edge ((uint16_t)0x0000)
+
222 #define USART_CPHA_2Edge ((uint16_t)0x0200)
+
223 #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
224 
+
233 #define USART_LastBit_Disable ((uint16_t)0x0000)
+
234 #define USART_LastBit_Enable ((uint16_t)0x0100)
+
235 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+
236  ((LASTBIT) == USART_LastBit_Enable))
+
237 
+
245 #define USART_IT_PE ((uint16_t)0x0028)
+
246 #define USART_IT_TXE ((uint16_t)0x0727)
+
247 #define USART_IT_TC ((uint16_t)0x0626)
+
248 #define USART_IT_RXNE ((uint16_t)0x0525)
+
249 #define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
+
250 #define USART_IT_IDLE ((uint16_t)0x0424)
+
251 #define USART_IT_LBD ((uint16_t)0x0846)
+
252 #define USART_IT_CTS ((uint16_t)0x096A)
+
253 #define USART_IT_ERR ((uint16_t)0x0060)
+
254 #define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
+
255 #define USART_IT_NE ((uint16_t)0x0260)
+
256 #define USART_IT_FE ((uint16_t)0x0160)
+
257 
+
261 #define USART_IT_ORE USART_IT_ORE_ER
+
262 
+
266 #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+
267  ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
268  ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+
269  ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+
270 #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+
271  ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
272  ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+
273  ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+
274  ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
+
275  ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+
276 #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+
277  ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+
278 
+
286 #define USART_DMAReq_Tx ((uint16_t)0x0080)
+
287 #define USART_DMAReq_Rx ((uint16_t)0x0040)
+
288 #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
289 
+
298 #define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+
299 #define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+
300 #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+
301  ((WAKEUP) == USART_WakeUp_AddressMark))
+
302 
+
310 #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+
311 #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+
312 #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+
313  (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+
314  ((LENGTH) == USART_LINBreakDetectLength_11b))
+
315 
+
323 #define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+
324 #define USART_IrDAMode_Normal ((uint16_t)0x0000)
+
325 #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+
326  ((MODE) == USART_IrDAMode_Normal))
+
327 
+
335 #define USART_FLAG_CTS ((uint16_t)0x0200)
+
336 #define USART_FLAG_LBD ((uint16_t)0x0100)
+
337 #define USART_FLAG_TXE ((uint16_t)0x0080)
+
338 #define USART_FLAG_TC ((uint16_t)0x0040)
+
339 #define USART_FLAG_RXNE ((uint16_t)0x0020)
+
340 #define USART_FLAG_IDLE ((uint16_t)0x0010)
+
341 #define USART_FLAG_ORE ((uint16_t)0x0008)
+
342 #define USART_FLAG_NE ((uint16_t)0x0004)
+
343 #define USART_FLAG_FE ((uint16_t)0x0002)
+
344 #define USART_FLAG_PE ((uint16_t)0x0001)
+
345 #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+
346  ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+
347  ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+
348  ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+
349  ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
350 
+
351 #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
352 
+
353 #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
+
354 #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+
355 #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
356 
+
365 /* Exported macro ------------------------------------------------------------*/
+
366 /* Exported functions --------------------------------------------------------*/
+
367 
+
368 /* Function used to set the USART configuration to the default reset state ***/
+
369 void USART_DeInit(USART_TypeDef* USARTx);
+
370 
+
371 /* Initialization and Configuration functions *********************************/
+
372 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+
373 void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+
374 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+
375 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+
376 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
377 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+
378 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
379 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
380 
+
381 /* Data transfers functions ***************************************************/
+
382 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+
383 uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
384 
+
385 /* Multi-Processor Communication functions ************************************/
+
386 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+
387 void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+
388 void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
389 
+
390 /* LIN mode functions *********************************************************/
+
391 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+
392 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
393 void USART_SendBreak(USART_TypeDef* USARTx);
+
394 
+
395 /* Half-duplex mode function **************************************************/
+
396 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
397 
+
398 /* Smartcard mode functions ***************************************************/
+
399 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
400 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
401 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
402 
+
403 /* IrDA mode functions ********************************************************/
+
404 void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+
405 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
406 
+
407 /* DMA transfers management functions *****************************************/
+
408 void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
409 
+
410 /* Interrupts and flags management functions **********************************/
+
411 void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+
412 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+
413 void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+
414 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+
415 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
416 
+
417 #ifdef __cplusplus
+
418 }
+
419 #endif
+
420 
+
421 #endif /* __STM32F4xx_USART_H */
+
422 
+
431 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
USART_Init
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
Initializes the USARTx peripheral according to the specified parameters in the USART_InitStruct ...
Definition: stm32f4xx_usart.c:246
+
USART_SmartCardNACKCmd
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables NACK transmission.
Definition: stm32f4xx_usart.c:964
+
USART_ITConfig
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
Enables or disables the specified USART interrupts.
Definition: stm32f4xx_usart.c:1231
+
USART_ClockInitTypeDef
USART Clock Init Structure definition.
Definition: stm32f4xx_usart.h:87
+
USART_OverSampling8Cmd
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's 8x oversampling mode.
Definition: stm32f4xx_usart.c:474
+
USART_ClockInitTypeDef::USART_LastBit
uint16_t USART_LastBit
Definition: stm32f4xx_usart.h:99
+
USART_LINBreakDetectLengthConfig
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
Sets the USART LIN Break detection length.
Definition: stm32f4xx_usart.c:741
+
USART_SetAddress
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
Sets the address of the USART node.
Definition: stm32f4xx_usart.c:625
+
USART_DMACmd
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
Enables or disables the USART's DMA interface.
Definition: stm32f4xx_usart.c:1099
+
USART_ClockInitTypeDef::USART_Clock
uint16_t USART_Clock
Definition: stm32f4xx_usart.h:90
+
USART_ReceiverWakeUpCmd
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Determines if the USART is in mute mode or not.
Definition: stm32f4xx_usart.c:645
+
USART_ClockInitTypeDef::USART_CPHA
uint16_t USART_CPHA
Definition: stm32f4xx_usart.h:96
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
USART_GetFlagStatus
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
Checks whether the specified USART flag is set or not.
Definition: stm32f4xx_usart.c:1295
+
USART_GetITStatus
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
Checks whether the specified USART interrupt has occurred or not.
Definition: stm32f4xx_usart.c:1378
+
USART_WakeUpConfig
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
Selects the USART WakeUp method.
Definition: stm32f4xx_usart.c:672
+
USART_ClearFlag
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
Clears the USARTx's pending flags.
Definition: stm32f4xx_usart.c:1344
+
USART_SmartCardCmd
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Smart Card mode.
Definition: stm32f4xx_usart.c:939
+
USART_SetGuardTime
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
Sets the specified USART guard time.
Definition: stm32f4xx_usart.c:920
+
USART_SendBreak
void USART_SendBreak(USART_TypeDef *USARTx)
Transmits break characters.
Definition: stm32f4xx_usart.c:783
+
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f4xx.h:1327
+
USART_HalfDuplexCmd
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's Half Duplex communication.
Definition: stm32f4xx_usart.c:836
+
USART_InitTypeDef::USART_WordLength
uint16_t USART_WordLength
Definition: stm32f4xx_usart.h:62
+
USART_InitTypeDef::USART_Mode
uint16_t USART_Mode
Definition: stm32f4xx_usart.h:75
+
USART_Cmd
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the specified USART peripheral.
Definition: stm32f4xx_usart.c:427
+
USART_SetPrescaler
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
Sets the system clock prescaler.
Definition: stm32f4xx_usart.c:453
+
USART_InitTypeDef::USART_Parity
uint16_t USART_Parity
Definition: stm32f4xx_usart.h:68
+
USART_ClockStructInit
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
Fills each USART_ClockInitStruct member with its default value.
Definition: stm32f4xx_usart.c:410
+
USART_ClearITPendingBit
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
Clears the USARTx's interrupt pending bits.
Definition: stm32f4xx_usart.c:1452
+
USART_OneBitMethodCmd
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's one bit sampling method.
Definition: stm32f4xx_usart.c:500
+
USART_InitTypeDef
USART Init Structure definition.
Definition: stm32f4xx_usart.h:54
+
USART_StructInit
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
Fills each USART_InitStruct member with its default value.
Definition: stm32f4xx_usart.c:359
+
USART_IrDACmd
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's IrDA interface.
Definition: stm32f4xx_usart.c:1053
+
USART_LINCmd
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
Enables or disables the USART's LIN mode.
Definition: stm32f4xx_usart.c:759
+
USART_ClockInit
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
Initializes the USARTx peripheral Clock according to the specified parameters in the USART_ClockInitS...
Definition: stm32f4xx_usart.c:379
+
USART_DeInit
void USART_DeInit(USART_TypeDef *USARTx)
Deinitializes the USARTx peripheral registers to their default reset values.
Definition: stm32f4xx_usart.c:187
+
USART_ReceiveData
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
Returns the most recent received data by the USARTx peripheral.
Definition: stm32f4xx_usart.c:573
+
USART_SendData
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
Transmits single data through the USARTx peripheral.
Definition: stm32f4xx_usart.c:557
+
USART_ClockInitTypeDef::USART_CPOL
uint16_t USART_CPOL
Definition: stm32f4xx_usart.h:93
+
USART_IrDAConfig
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
Configures the USART's IrDA interface.
Definition: stm32f4xx_usart.c:1035
+
USART_InitTypeDef::USART_HardwareFlowControl
uint16_t USART_HardwareFlowControl
Definition: stm32f4xx_usart.h:78
+
USART_InitTypeDef::USART_BaudRate
uint32_t USART_BaudRate
Definition: stm32f4xx_usart.h:56
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USART_InitTypeDef::USART_StopBits
uint16_t USART_StopBits
Definition: stm32f4xx_usart.h:65
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stm32f4xx_wwdg.c File Reference
+
+
+ +

This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral: +More...

+
#include "stm32f4xx_wwdg.h"
+#include "stm32f4xx_rcc.h"
+
+Include dependency graph for stm32f4xx_wwdg.c:
+
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+ + +
+
+ + + + + + + + + + + + + + + +

+Macros

+#define WWDG_OFFSET   (WWDG_BASE - PERIPH_BASE)
 
+#define CFR_OFFSET   (WWDG_OFFSET + 0x04)
 
+#define EWI_BitNumber   0x09
 
+#define CFR_EWI_BB   (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
 
+#define CFR_WDGTB_MASK   ((uint32_t)0xFFFFFE7F)
 
+#define CFR_W_MASK   ((uint32_t)0xFFFFFF80)
 
+#define BIT_MASK   ((uint8_t)0x7F)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void WWDG_DeInit (void)
 Deinitializes the WWDG peripheral registers to their default reset values. More...
 
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
 Sets the WWDG Prescaler. More...
 
void WWDG_SetWindowValue (uint8_t WindowValue)
 Sets the WWDG window value. More...
 
void WWDG_EnableIT (void)
 Enables the WWDG Early Wakeup interrupt(EWI). More...
 
void WWDG_SetCounter (uint8_t Counter)
 Sets the WWDG counter value. More...
 
void WWDG_Enable (uint8_t Counter)
 Enables WWDG and load the counter value. More...
 
FlagStatus WWDG_GetFlagStatus (void)
 Checks whether the Early Wakeup interrupt flag is set or not. More...
 
void WWDG_ClearFlag (void)
 Clears Early Wakeup interrupt flag. More...
 
+

Detailed Description

+

This file provides firmware functions to manage the following functionalities of the Window watchdog (WWDG) peripheral:

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
    +
  • Prescaler, Refresh window and Counter configuration
    • +
  • WWDG activation
    • +
  • Interrupts and flags management
    • +
+
+
===============================================================================
+                          ##### WWDG features #####
+===============================================================================
+   [..]                                      
+       Once enabled the WWDG generates a system reset on expiry of a programmed
+       time period, unless the program refreshes the counter (downcounter) 
+       before to reach 0x3F value (i.e. a reset is generated when the counter
+       value rolls over from 0x40 to 0x3F). 
+       An MCU reset is also generated if the counter value is refreshed
+       before the counter has reached the refresh window value. This 
+       implies that the counter must be refreshed in a limited window.
+             
+       Once enabled the WWDG cannot be disabled except by a system reset.
+         
+       WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+       reset occurs.
+            
+       The WWDG counter input clock is derived from the APB clock divided 
+       by a programmable prescaler.
+               
+       WWDG counter clock = PCLK1 / Prescaler
+       WWDG timeout = (WWDG counter clock) * (counter value)
+                      
+       Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
+                            
+                     ##### How to use this driver #####
+===============================================================================
+   [..]
+     (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
+             
+     (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
+                            
+     (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
+             
+     (#) Set the WWDG counter value and start it using WWDG_Enable() function.
+         When the WWDG is enabled the counter value should be configured to 
+         a value greater than 0x40 to prevent generating an immediate reset.     
+             
+     (#) Optionally you can enable the Early wakeup interrupt which is 
+         generated when the counter reach 0x40.
+         Once enabled this interrupt cannot be disabled except by a system reset.
+                 
+     (#) Then the application program must refresh the WWDG counter at regular
+         intervals during normal operation to prevent an MCU reset, using
+         WWDG_SetCounter() function. This operation must occur only when
+         the counter value is lower than the refresh window value, 
+         programmed using WWDG_SetWindowValue().
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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stm32f4xx_wwdg.h File Reference
+
+
+ +

This file contains all the functions prototypes for the WWDG firmware library. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for stm32f4xx_wwdg.h:
+
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+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + + + + + +

+Macros

+#define WWDG_Prescaler_1   ((uint32_t)0x00000000)
 
+#define WWDG_Prescaler_2   ((uint32_t)0x00000080)
 
+#define WWDG_Prescaler_4   ((uint32_t)0x00000100)
 
+#define WWDG_Prescaler_8   ((uint32_t)0x00000180)
 
#define IS_WWDG_PRESCALER(PRESCALER)
 
+#define IS_WWDG_WINDOW_VALUE(VALUE)   ((VALUE) <= 0x7F)
 
+#define IS_WWDG_COUNTER(COUNTER)   (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void WWDG_DeInit (void)
 Deinitializes the WWDG peripheral registers to their default reset values. More...
 
void WWDG_SetPrescaler (uint32_t WWDG_Prescaler)
 Sets the WWDG Prescaler. More...
 
void WWDG_SetWindowValue (uint8_t WindowValue)
 Sets the WWDG window value. More...
 
void WWDG_EnableIT (void)
 Enables the WWDG Early Wakeup interrupt(EWI). More...
 
void WWDG_SetCounter (uint8_t Counter)
 Sets the WWDG counter value. More...
 
void WWDG_Enable (uint8_t Counter)
 Enables WWDG and load the counter value. More...
 
FlagStatus WWDG_GetFlagStatus (void)
 Checks whether the Early Wakeup interrupt flag is set or not. More...
 
void WWDG_ClearFlag (void)
 Clears Early Wakeup interrupt flag. More...
 
+

Detailed Description

+

This file contains all the functions prototypes for the WWDG firmware library.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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stm32f4xx_wwdg.h
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1 
+
29 /* Define to prevent recursive inclusion -------------------------------------*/
+
30 #ifndef __STM32F4xx_WWDG_H
+
31 #define __STM32F4xx_WWDG_H
+
32 
+
33 #ifdef __cplusplus
+
34  extern "C" {
+
35 #endif
+
36 
+
37 /* Includes ------------------------------------------------------------------*/
+
38 #include "stm32f4xx.h"
+
39 
+
48 /* Exported types ------------------------------------------------------------*/
+
49 /* Exported constants --------------------------------------------------------*/
+
50 
+
59 #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+
60 #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+
61 #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+
62 #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+
63 #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+
64  ((PRESCALER) == WWDG_Prescaler_2) || \
+
65  ((PRESCALER) == WWDG_Prescaler_4) || \
+
66  ((PRESCALER) == WWDG_Prescaler_8))
+
67 #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+
68 #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
69 
+
78 /* Exported macro ------------------------------------------------------------*/
+
79 /* Exported functions --------------------------------------------------------*/
+
80 
+
81 /* Function used to set the WWDG configuration to the default reset state ****/
+
82 void WWDG_DeInit(void);
+
83 
+
84 /* Prescaler, Refresh window and Counter configuration functions **************/
+
85 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+
86 void WWDG_SetWindowValue(uint8_t WindowValue);
+
87 void WWDG_EnableIT(void);
+
88 void WWDG_SetCounter(uint8_t Counter);
+
89 
+
90 /* WWDG activation function ***************************************************/
+
91 void WWDG_Enable(uint8_t Counter);
+
92 
+
93 /* Interrupts and flags management functions **********************************/
+
94 FlagStatus WWDG_GetFlagStatus(void);
+
95 void WWDG_ClearFlag(void);
+
96 
+
97 #ifdef __cplusplus
+
98 }
+
99 #endif
+
100 
+
101 #endif /* __STM32F4xx_WWDG_H */
+
102 
+
111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
WWDG_Enable
void WWDG_Enable(uint8_t Counter)
Enables WWDG and load the counter value.
Definition: stm32f4xx_wwdg.c:239
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
WWDG_DeInit
void WWDG_DeInit(void)
Deinitializes the WWDG peripheral registers to their default reset values.
Definition: stm32f4xx_wwdg.c:138
+
WWDG_SetCounter
void WWDG_SetCounter(uint8_t Counter)
Sets the WWDG counter value.
Definition: stm32f4xx_wwdg.c:208
+
WWDG_EnableIT
void WWDG_EnableIT(void)
Enables the WWDG Early Wakeup interrupt(EWI).
Definition: stm32f4xx_wwdg.c:196
+
WWDG_SetWindowValue
void WWDG_SetWindowValue(uint8_t WindowValue)
Sets the WWDG window value.
Definition: stm32f4xx_wwdg.c:173
+
WWDG_ClearFlag
void WWDG_ClearFlag(void)
Clears Early Wakeup interrupt flag.
Definition: stm32f4xx_wwdg.c:286
+
WWDG_SetPrescaler
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
Sets the WWDG Prescaler.
Definition: stm32f4xx_wwdg.c:154
+
WWDG_GetFlagStatus
FlagStatus WWDG_GetFlagStatus(void)
Checks whether the Early Wakeup interrupt flag is set or not.
Definition: stm32f4xx_wwdg.c:266
+
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MSBulkInEp (defined in __MassStorageParameter)__MassStorageParameter
MSBulkOutEp (defined in __MassStorageParameter)__MassStorageParameter
MSCapacity (defined in __MassStorageParameter)__MassStorageParameter
MSPageLength (defined in __MassStorageParameter)__MassStorageParameter
MSSenseKey (defined in __MassStorageParameter)__MassStorageParameter
MSWriteProtect (defined in __MassStorageParameter)__MassStorageParameter
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__MassStorageParameter Struct Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_SCSI » USBH_MSC_SCSI_Exported_Types
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+Public Attributes

+uint32_t MSCapacity
 
+uint32_t MSSenseKey
 
+uint16_t MSPageLength
 
+uint8_t MSBulkOutEp
 
+uint8_t MSBulkInEp
 
+uint8_t MSWriteProtect
 
+
The documentation for this struct was generated from the following file:
    +
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pRxTxBuff (defined in _BOTXfer)_BOTXfer
+ +
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+ + diff --git a/struct___b_o_t_xfer.html b/struct___b_o_t_xfer.html new file mode 100644 index 0000000..356fdec --- /dev/null +++ b/struct___b_o_t_xfer.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: _BOTXfer Struct Reference + + + + + + + + + + +
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_BOTXfer Struct Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT » USBH_MSC_BOT_Exported_Types
+
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+ + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t MSCState
 
+uint8_t MSCStateBkp
 
+uint8_t MSCStateCurrent
 
+uint8_t CmdStateMachine
 
+uint8_t BOTState
 
+uint8_t BOTStateBkp
 
+uint8_t * pRxTxBuff
 
+uint16_t DataLength
 
+uint8_t BOTXferErrorCount
 
+uint8_t BOTXferStatus
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h
    • +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___configuration_descriptor-members.html b/struct___configuration_descriptor-members.html new file mode 100644 index 0000000..e66cb3c --- /dev/null +++ b/struct___configuration_descriptor-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_ConfigurationDescriptor Member List
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This is the complete list of members for _ConfigurationDescriptor, including all inherited members.

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bConfigurationValue (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
bDescriptorType (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
bLength (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
bmAttributes (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
bMaxPower (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
bNumInterfaces (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
iConfiguration (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
wTotalLength (defined in _ConfigurationDescriptor)_ConfigurationDescriptor
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___configuration_descriptor.html b/struct___configuration_descriptor.html new file mode 100644 index 0000000..679a527 --- /dev/null +++ b/struct___configuration_descriptor.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: _ConfigurationDescriptor Struct Reference + + + + + + + + + + +
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_ConfigurationDescriptor Struct Reference
USBH_LIB » USBH_LIB_CORE
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+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+uint16_t wTotalLength
 
+uint8_t bNumInterfaces
 
+uint8_t bConfigurationValue
 
+uint8_t iConfiguration
 
+uint8_t bmAttributes
 
+uint8_t bMaxPower
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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buff (defined in _Ctrl)_Ctrl
ep0size (defined in _Ctrl)_Ctrl
errorcount (defined in _Ctrl)_Ctrl
hc_num_in (defined in _Ctrl)_Ctrl
hc_num_out (defined in _Ctrl)_Ctrl
length (defined in _Ctrl)_Ctrl
setup (defined in _Ctrl)_Ctrl
state (defined in _Ctrl)_Ctrl
status (defined in _Ctrl)_Ctrl
timer (defined in _Ctrl)_Ctrl
+ +
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+ + diff --git a/struct___ctrl.html b/struct___ctrl.html new file mode 100644 index 0000000..1e94e95 --- /dev/null +++ b/struct___ctrl.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: _Ctrl Struct Reference + + + + + + + + + + +
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_Ctrl Struct Reference
USBH_LIB » USBH_LIB_CORE » USBH_CORE » USBH_CORE_Exported_Types
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+Collaboration diagram for _Ctrl:
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Collaboration graph
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+Public Attributes

+uint8_t hc_num_in
 
+uint8_t hc_num_out
 
+uint8_t ep0size
 
+uint8_t * buff
 
+uint16_t length
 
+uint8_t errorcount
 
+uint16_t timer
 
+CTRL_STATUS status
 
+USB_Setup_TypeDef setup
 
+CTRL_State state
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h
    • +
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_DCD Member List
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This is the complete list of members for _DCD, including all inherited members.

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class_cb (defined in _DCD)_DCD
device_address (defined in _DCD)_DCD
device_config (defined in _DCD)_DCD
device_state (defined in _DCD)_DCD
device_status (defined in _DCD)_DCD
DevRemoteWakeup (defined in _DCD)_DCD
in_ep (defined in _DCD)_DCD
out_ep (defined in _DCD)_DCD
pConfig_descriptor (defined in _DCD)_DCD
setup_packet (defined in _DCD)_DCD
usr_cb (defined in _DCD)_DCD
usr_device (defined in _DCD)_DCD
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_DCD Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Collaboration diagram for _DCD:
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Collaboration graph
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[legend]
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+Public Attributes

+uint8_t device_config
 
+uint8_t device_state
 
+uint8_t device_status
 
+uint8_t device_address
 
+uint32_t DevRemoteWakeup
 
+USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]
 
+uint8_t setup_packet [8 *3]
 
+USBD_Class_cb_TypeDef * class_cb
 
+USBD_Usr_cb_TypeDef * usr_cb
 
+USBD_DEVICE * usr_device
 
+uint8_t * pConfig_descriptor
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___d_c_d__coll__graph.map b/struct___d_c_d__coll__graph.map new file mode 100644 index 0000000..0169905 --- /dev/null +++ b/struct___d_c_d__coll__graph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/struct___d_c_d__coll__graph.md5 b/struct___d_c_d__coll__graph.md5 new file mode 100644 index 0000000..3b856b6 --- /dev/null +++ b/struct___d_c_d__coll__graph.md5 @@ -0,0 +1 @@ +33525198fd74de153b344d9386171530 \ No newline at end of file diff --git a/struct___d_c_d__coll__graph.png b/struct___d_c_d__coll__graph.png new file mode 100644 index 0000000..2f17fb9 Binary files /dev/null and b/struct___d_c_d__coll__graph.png differ diff --git a/struct___desc_header-members.html b/struct___desc_header-members.html new file mode 100644 index 0000000..f204506 --- /dev/null +++ b/struct___desc_header-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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bDescriptorType (defined in _DescHeader)_DescHeader
bLength (defined in _DescHeader)_DescHeader
+ +
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_DescHeader Struct Reference
USBH_LIB » USBH_LIB_CORE
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+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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_Device_TypeDef Member List
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This is the complete list of members for _Device_TypeDef, including all inherited members.

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GetConfigurationStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetDeviceDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetInterfaceStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetLangIDStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetManufacturerStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetProductStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
GetSerialStrDescriptor (defined in _Device_TypeDef)_Device_TypeDef
+ +
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_Device_TypeDef Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+uint8_t *(* GetDeviceDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetLangIDStrDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetManufacturerStrDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetProductStrDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetSerialStrDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetConfigurationStrDescriptor )(uint8_t speed, uint16_t *length)
 
+uint8_t *(* GetInterfaceStrDescriptor )(uint8_t speed, uint16_t *length)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
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DataIn (defined in _Device_cb)_Device_cb
DataOut (defined in _Device_cb)_Device_cb
DeInit (defined in _Device_cb)_Device_cb
EP0_RxReady (defined in _Device_cb)_Device_cb
EP0_TxSent (defined in _Device_cb)_Device_cb
GetConfigDescriptor (defined in _Device_cb)_Device_cb
Init (defined in _Device_cb)_Device_cb
IsoINIncomplete (defined in _Device_cb)_Device_cb
IsoOUTIncomplete (defined in _Device_cb)_Device_cb
Setup (defined in _Device_cb)_Device_cb
SOF (defined in _Device_cb)_Device_cb
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_Device_cb Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+uint8_t(* Init )(void *pdev, uint8_t cfgidx)
 
+uint8_t(* DeInit )(void *pdev, uint8_t cfgidx)
 
+uint8_t(* Setup )(void *pdev, USB_SETUP_REQ *req)
 
+uint8_t(* EP0_TxSent )(void *pdev)
 
+uint8_t(* EP0_RxReady )(void *pdev)
 
+uint8_t(* DataIn )(void *pdev, uint8_t epnum)
 
+uint8_t(* DataOut )(void *pdev, uint8_t epnum)
 
+uint8_t(* SOF )(void *pdev)
 
+uint8_t(* IsoINIncomplete )(void *pdev)
 
+uint8_t(* IsoOUTIncomplete )(void *pdev)
 
+uint8_t *(* GetConfigDescriptor )(uint8_t speed, uint16_t *length)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
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_DeviceDescriptor Member List
+
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This is the complete list of members for _DeviceDescriptor, including all inherited members.

+ + + + + + + + + + + + + + + +
bcdDevice (defined in _DeviceDescriptor)_DeviceDescriptor
bcdUSB (defined in _DeviceDescriptor)_DeviceDescriptor
bDescriptorType (defined in _DeviceDescriptor)_DeviceDescriptor
bDeviceClass (defined in _DeviceDescriptor)_DeviceDescriptor
bDeviceProtocol (defined in _DeviceDescriptor)_DeviceDescriptor
bDeviceSubClass (defined in _DeviceDescriptor)_DeviceDescriptor
bLength (defined in _DeviceDescriptor)_DeviceDescriptor
bMaxPacketSize (defined in _DeviceDescriptor)_DeviceDescriptor
bNumConfigurations (defined in _DeviceDescriptor)_DeviceDescriptor
idProduct (defined in _DeviceDescriptor)_DeviceDescriptor
idVendor (defined in _DeviceDescriptor)_DeviceDescriptor
iManufacturer (defined in _DeviceDescriptor)_DeviceDescriptor
iProduct (defined in _DeviceDescriptor)_DeviceDescriptor
iSerialNumber (defined in _DeviceDescriptor)_DeviceDescriptor
+ +
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_DeviceDescriptor Struct Reference
USBH_LIB » USBH_LIB_CORE
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+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+uint16_t bcdUSB
 
+uint8_t bDeviceClass
 
+uint8_t bDeviceSubClass
 
+uint8_t bDeviceProtocol
 
+uint8_t bMaxPacketSize
 
+uint16_t idVendor
 
+uint16_t idProduct
 
+uint16_t bcdDevice
 
+uint8_t iManufacturer
 
+uint8_t iProduct
 
+uint8_t iSerialNumber
 
+uint8_t bNumConfigurations
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___device_prop-members.html b/struct___device_prop-members.html new file mode 100644 index 0000000..177b4b8 --- /dev/null +++ b/struct___device_prop-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_DeviceProp Member List
+
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This is the complete list of members for _DeviceProp, including all inherited members.

+ + + + + + + + +
address (defined in _DeviceProp)_DeviceProp
Cfg_Desc (defined in _DeviceProp)_DeviceProp
Dev_Desc (defined in _DeviceProp)_DeviceProp
Ep_Desc (defined in _DeviceProp)_DeviceProp
HID_Desc (defined in _DeviceProp)_DeviceProp
Itf_Desc (defined in _DeviceProp)_DeviceProp
speed (defined in _DeviceProp)_DeviceProp
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___device_prop.html b/struct___device_prop.html new file mode 100644 index 0000000..4778b18 --- /dev/null +++ b/struct___device_prop.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _DeviceProp Struct Reference + + + + + + + + + + +
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_DeviceProp Struct Reference
USBH_LIB » USBH_LIB_CORE » USBH_CORE » USBH_CORE_Exported_Types
+
+
+
+Collaboration diagram for _DeviceProp:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t address
 
+uint8_t speed
 
+USBH_DevDesc_TypeDef Dev_Desc
 
+USBH_CfgDesc_TypeDef Cfg_Desc
 
+USBH_InterfaceDesc_TypeDef Itf_Desc [USBH_MAX_NUM_INTERFACES]
 
+USBH_EpDesc_TypeDef Ep_Desc [USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]
 
+USBH_HIDDesc_TypeDef HID_Desc
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___device_prop__coll__graph.map b/struct___device_prop__coll__graph.map new file mode 100644 index 0000000..b6cdbc1 --- /dev/null +++ b/struct___device_prop__coll__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/struct___device_prop__coll__graph.md5 b/struct___device_prop__coll__graph.md5 new file mode 100644 index 0000000..ea14f04 --- /dev/null +++ b/struct___device_prop__coll__graph.md5 @@ -0,0 +1 @@ +961f6a351ed2a60110937c36873099e9 \ No newline at end of file diff --git a/struct___device_prop__coll__graph.png b/struct___device_prop__coll__graph.png new file mode 100644 index 0000000..b279f7a Binary files /dev/null and b/struct___device_prop__coll__graph.png differ diff --git a/struct___endpoint_descriptor-members.html b/struct___endpoint_descriptor-members.html new file mode 100644 index 0000000..1a1a925 --- /dev/null +++ b/struct___endpoint_descriptor-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_EndpointDescriptor Member List
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This is the complete list of members for _EndpointDescriptor, including all inherited members.

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bDescriptorType (defined in _EndpointDescriptor)_EndpointDescriptor
bEndpointAddress (defined in _EndpointDescriptor)_EndpointDescriptor
bInterval (defined in _EndpointDescriptor)_EndpointDescriptor
bLength (defined in _EndpointDescriptor)_EndpointDescriptor
bmAttributes (defined in _EndpointDescriptor)_EndpointDescriptor
wMaxPacketSize (defined in _EndpointDescriptor)_EndpointDescriptor
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___endpoint_descriptor.html b/struct___endpoint_descriptor.html new file mode 100644 index 0000000..42f529b --- /dev/null +++ b/struct___endpoint_descriptor.html @@ -0,0 +1,127 @@ + + + + + + +discoverpixy: _EndpointDescriptor Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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_EndpointDescriptor Struct Reference
USBH_LIB » USBH_LIB_CORE
+
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+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+uint8_t bEndpointAddress
 
+uint8_t bmAttributes
 
+uint16_t wMaxPacketSize
 
+uint8_t bInterval
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_c_d-members.html b/struct___h_c_d-members.html new file mode 100644 index 0000000..7eed395 --- /dev/null +++ b/struct___h_c_d-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_HCD Member List
+
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This is the complete list of members for _HCD, including all inherited members.

+ + + + + + + + + + +
channel (defined in _HCD)_HCD
ConnSts (defined in _HCD)_HCD
ErrCnt (defined in _HCD)_HCD
hc (defined in _HCD)_HCD
HC_Status (defined in _HCD)_HCD
port_cb (defined in _HCD)_HCD
Rx_Buffer (defined in _HCD)_HCD
URB_State (defined in _HCD)_HCD
XferCnt (defined in _HCD)_HCD
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_c_d.html b/struct___h_c_d.html new file mode 100644 index 0000000..0139200 --- /dev/null +++ b/struct___h_c_d.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: _HCD Struct Reference + + + + + + + + + + +
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_HCD Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
+
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+
+Collaboration diagram for _HCD:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t Rx_Buffer [MAX_DATA_LENGTH]
 
+__IO uint32_t ConnSts
 
+__IO uint32_t ErrCnt [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t XferCnt [USB_OTG_MAX_TX_FIFOS]
 
+__IO HC_STATUS HC_Status [USB_OTG_MAX_TX_FIFOS]
 
+__IO URB_STATE URB_State [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]
 
+uint16_t channel [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_hPort_TypeDef * port_cb
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_c_d__coll__graph.map b/struct___h_c_d__coll__graph.map new file mode 100644 index 0000000..48c61b7 --- /dev/null +++ b/struct___h_c_d__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/struct___h_c_d__coll__graph.md5 b/struct___h_c_d__coll__graph.md5 new file mode 100644 index 0000000..9174336 --- /dev/null +++ b/struct___h_c_d__coll__graph.md5 @@ -0,0 +1 @@ +5a344e90305229febf1d5bc77df3183b \ No newline at end of file diff --git a/struct___h_c_d__coll__graph.png b/struct___h_c_d__coll__graph.png new file mode 100644 index 0000000..d292009 Binary files /dev/null and b/struct___h_c_d__coll__graph.png differ diff --git a/struct___h_i_d___m_o_u_s_e___data-members.html b/struct___h_i_d___m_o_u_s_e___data-members.html new file mode 100644 index 0000000..5bba59d --- /dev/null +++ b/struct___h_i_d___m_o_u_s_e___data-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_HID_MOUSE_Data Member List
+
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+ +

This is the complete list of members for _HID_MOUSE_Data, including all inherited members.

+ + + + + +
button (defined in _HID_MOUSE_Data)_HID_MOUSE_Data
x (defined in _HID_MOUSE_Data)_HID_MOUSE_Data
y (defined in _HID_MOUSE_Data)_HID_MOUSE_Data
z (defined in _HID_MOUSE_Data)_HID_MOUSE_Data
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d___m_o_u_s_e___data.html b/struct___h_i_d___m_o_u_s_e___data.html new file mode 100644 index 0000000..7fdc491 --- /dev/null +++ b/struct___h_i_d___m_o_u_s_e___data.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: _HID_MOUSE_Data Struct Reference + + + + + + + + + + +
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_HID_MOUSE_Data Struct Reference
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_MOUSE » USBH_HID_MOUSE_Exported_Types
+
+
+ + + + + + + + + + +

+Public Attributes

+uint8_t x
 
+uint8_t y
 
+uint8_t z
 
+uint8_t button
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h
    • +
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d___process-members.html b/struct___h_i_d___process-members.html new file mode 100644 index 0000000..2a96bee --- /dev/null +++ b/struct___h_i_d___process-members.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_HID_Process Member List
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This is the complete list of members for _HID_Process, including all inherited members.

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buff (defined in _HID_Process)_HID_Process
cb (defined in _HID_Process)_HID_Process
ctl_state (defined in _HID_Process)_HID_Process
ep_addr (defined in _HID_Process)_HID_Process
hc_num_in (defined in _HID_Process)_HID_Process
hc_num_out (defined in _HID_Process)_HID_Process
HIDIntInEp (defined in _HID_Process)_HID_Process
HIDIntOutEp (defined in _HID_Process)_HID_Process
length (defined in _HID_Process)_HID_Process
poll (defined in _HID_Process)_HID_Process
state (defined in _HID_Process)_HID_Process
timer (defined in _HID_Process)_HID_Process
+ +
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+ + diff --git a/struct___h_i_d___process.html b/struct___h_i_d___process.html new file mode 100644 index 0000000..3f6e62d --- /dev/null +++ b/struct___h_i_d___process.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: _HID_Process Struct Reference + + + + + + + + + + +
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_HID_Process Struct Reference
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE » USBH_HID_CORE_Exported_Types
+
+
+
+Collaboration diagram for _HID_Process:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t buff [64]
 
+uint8_t hc_num_in
 
+uint8_t hc_num_out
 
+HID_State state
 
+uint8_t HIDIntOutEp
 
+uint8_t HIDIntInEp
 
+HID_CtlState ctl_state
 
+uint16_t length
 
+uint8_t ep_addr
 
+uint16_t poll
 
+__IO uint16_t timer
 
+HID_cb_TypeDef * cb
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d___process__coll__graph.map b/struct___h_i_d___process__coll__graph.map new file mode 100644 index 0000000..b92a219 --- /dev/null +++ b/struct___h_i_d___process__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct___h_i_d___process__coll__graph.md5 b/struct___h_i_d___process__coll__graph.md5 new file mode 100644 index 0000000..56f4119 --- /dev/null +++ b/struct___h_i_d___process__coll__graph.md5 @@ -0,0 +1 @@ +520ec008f5eee26d5f872e4425485e1f \ No newline at end of file diff --git a/struct___h_i_d___process__coll__graph.png b/struct___h_i_d___process__coll__graph.png new file mode 100644 index 0000000..cb775d0 Binary files /dev/null and b/struct___h_i_d___process__coll__graph.png differ diff --git a/struct___h_i_d___report-members.html b/struct___h_i_d___report-members.html new file mode 100644 index 0000000..fb09683 --- /dev/null +++ b/struct___h_i_d___report-members.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_HID_Report Member List
+
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This is the complete list of members for _HID_Report, including all inherited members.

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AppUsage (defined in _HID_Report)_HID_Report
Flag (defined in _HID_Report)_HID_Report
LogMax (defined in _HID_Report)_HID_Report
LogMin (defined in _HID_Report)_HID_Report
LogUsage (defined in _HID_Report)_HID_Report
NbrUsage (defined in _HID_Report)_HID_Report
PhyMax (defined in _HID_Report)_HID_Report
PhyMin (defined in _HID_Report)_HID_Report
PhyUsage (defined in _HID_Report)_HID_Report
ReportCnt (defined in _HID_Report)_HID_Report
ReportID (defined in _HID_Report)_HID_Report
ReportSize (defined in _HID_Report)_HID_Report
ReportType (defined in _HID_Report)_HID_Report
Unit (defined in _HID_Report)_HID_Report
UnitExp (defined in _HID_Report)_HID_Report
Usage (defined in _HID_Report)_HID_Report
UsageMax (defined in _HID_Report)_HID_Report
UsageMin (defined in _HID_Report)_HID_Report
UsagePage (defined in _HID_Report)_HID_Report
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d___report.html b/struct___h_i_d___report.html new file mode 100644 index 0000000..c8c5752 --- /dev/null +++ b/struct___h_i_d___report.html @@ -0,0 +1,166 @@ + + + + + + +discoverpixy: _HID_Report Struct Reference + + + + + + + + + + +
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_HID_Report Struct Reference
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE » USBH_HID_CORE_Exported_Types
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t ReportID
 
+uint8_t ReportType
 
+uint16_t UsagePage
 
+uint32_t Usage [2]
 
+uint32_t NbrUsage
 
+uint32_t UsageMin
 
+uint32_t UsageMax
 
+int32_t LogMin
 
+int32_t LogMax
 
+int32_t PhyMin
 
+int32_t PhyMax
 
+int32_t UnitExp
 
+uint32_t Unit
 
+uint32_t ReportSize
 
+uint32_t ReportCnt
 
+uint32_t Flag
 
+uint32_t PhyUsage
 
+uint32_t AppUsage
 
+uint32_t LogUsage
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d_descriptor-members.html b/struct___h_i_d_descriptor-members.html new file mode 100644 index 0000000..4ba8b5e --- /dev/null +++ b/struct___h_i_d_descriptor-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_HIDDescriptor Member List
+
+
+ +

This is the complete list of members for _HIDDescriptor, including all inherited members.

+ + + + + + + + +
bcdHID (defined in _HIDDescriptor)_HIDDescriptor
bCountryCode (defined in _HIDDescriptor)_HIDDescriptor
bDescriptorType (defined in _HIDDescriptor)_HIDDescriptor
bLength (defined in _HIDDescriptor)_HIDDescriptor
bNumDescriptors (defined in _HIDDescriptor)_HIDDescriptor
bReportDescriptorType (defined in _HIDDescriptor)_HIDDescriptor
wItemLength (defined in _HIDDescriptor)_HIDDescriptor
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___h_i_d_descriptor.html b/struct___h_i_d_descriptor.html new file mode 100644 index 0000000..7d3acbf --- /dev/null +++ b/struct___h_i_d_descriptor.html @@ -0,0 +1,130 @@ + + + + + + +discoverpixy: _HIDDescriptor Struct Reference + + + + + + + + + + +
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_HIDDescriptor Struct Reference
USBH_LIB » USBH_LIB_CORE
+
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+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+uint16_t bcdHID
 
+uint8_t bCountryCode
 
+uint8_t bNumDescriptors
 
+uint8_t bReportDescriptorType
 
+uint16_t wItemLength
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___host___type_def-members.html b/struct___host___type_def-members.html new file mode 100644 index 0000000..111d968 --- /dev/null +++ b/struct___host___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_Host_TypeDef Member List
+
+
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This is the complete list of members for _Host_TypeDef, including all inherited members.

+ + + + + + + + + +
class_cb (defined in _Host_TypeDef)_Host_TypeDef
Control (defined in _Host_TypeDef)_Host_TypeDef
device_prop (defined in _Host_TypeDef)_Host_TypeDef
EnumState (defined in _Host_TypeDef)_Host_TypeDef
gState (defined in _Host_TypeDef)_Host_TypeDef
gStateBkp (defined in _Host_TypeDef)_Host_TypeDef
RequestState (defined in _Host_TypeDef)_Host_TypeDef
usr_cb (defined in _Host_TypeDef)_Host_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___host___type_def.html b/struct___host___type_def.html new file mode 100644 index 0000000..a9e13ac --- /dev/null +++ b/struct___host___type_def.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: _Host_TypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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_Host_TypeDef Struct Reference
USBH_LIB » USBH_LIB_CORE » USBH_CORE » USBH_CORE_Exported_Types
+
+
+
+Collaboration diagram for _Host_TypeDef:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Attributes

+HOST_State gState
 
+HOST_State gStateBkp
 
+ENUM_State EnumState
 
+CMD_State RequestState
 
+USBH_Ctrl_TypeDef Control
 
+USBH_Device_TypeDef device_prop
 
+USBH_Class_cb_TypeDef * class_cb
 
+USBH_Usr_cb_TypeDef * usr_cb
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___host___type_def__coll__graph.map b/struct___host___type_def__coll__graph.map new file mode 100644 index 0000000..cea840a --- /dev/null +++ b/struct___host___type_def__coll__graph.map @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/struct___host___type_def__coll__graph.md5 b/struct___host___type_def__coll__graph.md5 new file mode 100644 index 0000000..b701506 --- /dev/null +++ b/struct___host___type_def__coll__graph.md5 @@ -0,0 +1 @@ +e623926e2099132e821509ba3e757b68 \ No newline at end of file diff --git a/struct___host___type_def__coll__graph.png b/struct___host___type_def__coll__graph.png new file mode 100644 index 0000000..c63d9f9 Binary files /dev/null and b/struct___host___type_def__coll__graph.png differ diff --git a/struct___interface_descriptor-members.html b/struct___interface_descriptor-members.html new file mode 100644 index 0000000..8e76ece --- /dev/null +++ b/struct___interface_descriptor-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_InterfaceDescriptor Member List
+
+
+ +

This is the complete list of members for _InterfaceDescriptor, including all inherited members.

+ + + + + + + + + + +
bAlternateSetting (defined in _InterfaceDescriptor)_InterfaceDescriptor
bDescriptorType (defined in _InterfaceDescriptor)_InterfaceDescriptor
bInterfaceClass (defined in _InterfaceDescriptor)_InterfaceDescriptor
bInterfaceNumber (defined in _InterfaceDescriptor)_InterfaceDescriptor
bInterfaceProtocol (defined in _InterfaceDescriptor)_InterfaceDescriptor
bInterfaceSubClass (defined in _InterfaceDescriptor)_InterfaceDescriptor
bLength (defined in _InterfaceDescriptor)_InterfaceDescriptor
bNumEndpoints (defined in _InterfaceDescriptor)_InterfaceDescriptor
iInterface (defined in _InterfaceDescriptor)_InterfaceDescriptor
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct___interface_descriptor.html b/struct___interface_descriptor.html new file mode 100644 index 0000000..4446bbf --- /dev/null +++ b/struct___interface_descriptor.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: _InterfaceDescriptor Struct Reference + + + + + + + + + + +
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+
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_InterfaceDescriptor Struct Reference
USBH_LIB » USBH_LIB_CORE
+
+
+ + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t bLength
 
+uint8_t bDescriptorType
 
+uint8_t bInterfaceNumber
 
+uint8_t bAlternateSetting
 
+uint8_t bNumEndpoints
 
+uint8_t bInterfaceClass
 
+uint8_t bInterfaceSubClass
 
+uint8_t bInterfaceProtocol
 
+uint8_t iInterface
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
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_MSC_Process Member List
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buff (defined in _MSC_Process)_MSC_Process
hc_num_in (defined in _MSC_Process)_MSC_Process
hc_num_out (defined in _MSC_Process)_MSC_Process
maxLun (defined in _MSC_Process)_MSC_Process
MSBulkInEp (defined in _MSC_Process)_MSC_Process
MSBulkInEpSize (defined in _MSC_Process)_MSC_Process
MSBulkOutEp (defined in _MSC_Process)_MSC_Process
MSBulkOutEpSize (defined in _MSC_Process)_MSC_Process
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_MSC_Process Struct Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_CORE » USBH_MSC_CORE_Exported_Types
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+Public Attributes

+uint8_t hc_num_in
 
+uint8_t hc_num_out
 
+uint8_t MSBulkOutEp
 
+uint8_t MSBulkInEp
 
+uint16_t MSBulkInEpSize
 
+uint16_t MSBulkOutEpSize
 
+uint8_t buff [USBH_MSC_MPS_SIZE]
 
+uint8_t maxLun
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_core.h
    • +
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_OTG Member List
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OTG_Mode (defined in _OTG)_OTG
OTG_PrevState (defined in _OTG)_OTG
OTG_State (defined in _OTG)_OTG
+ +
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_OTG Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+uint8_t OTG_State
 
+uint8_t OTG_PrevState
 
+uint8_t OTG_Mode
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
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DAINT (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DAINTMSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DCFG (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DCTL (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DEACHINT (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DEACHMSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DIEPEMPMSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DIEPMSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DINEP1MSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DOEPMSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DOUTEP1MSK (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DSTS (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DTHRCTL (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DVBUSDIS (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
DVBUSPULSE (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
Reserved0C (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
Reserved20 (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
Reserved40 (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
Reserved44 (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
Reserved9 (defined in _USB_OTG_DREGS)_USB_OTG_DREGS
+ +
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+ + diff --git a/struct___u_s_b___o_t_g___d_r_e_g_s.html b/struct___u_s_b___o_t_g___d_r_e_g_s.html new file mode 100644 index 0000000..80f5998 --- /dev/null +++ b/struct___u_s_b___o_t_g___d_r_e_g_s.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: _USB_OTG_DREGS Struct Reference + + + + + + + + + + +
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_USB_OTG_DREGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __device_Registers
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+__IO uint32_t DCFG
 
+__IO uint32_t DCTL
 
+__IO uint32_t DSTS
 
+uint32_t Reserved0C
 
+__IO uint32_t DIEPMSK
 
+__IO uint32_t DOEPMSK
 
+__IO uint32_t DAINT
 
+__IO uint32_t DAINTMSK
 
+uint32_t Reserved20
 
+uint32_t Reserved9
 
+__IO uint32_t DVBUSDIS
 
+__IO uint32_t DVBUSPULSE
 
+__IO uint32_t DTHRCTL
 
+__IO uint32_t DIEPEMPMSK
 
+__IO uint32_t DEACHINT
 
+__IO uint32_t DEACHMSK
 
+uint32_t Reserved40
 
+__IO uint32_t DINEP1MSK
 
+uint32_t Reserved44 [15]
 
+__IO uint32_t DOUTEP1MSK
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
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CID (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
DIEPTXF (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
DIEPTXF0_HNPTXFSIZ (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GAHBCFG (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GCCFG (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GI2CCTL (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GINTMSK (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GINTSTS (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GOTGCTL (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GOTGINT (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GRSTCTL (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GRXFSIZ (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GRXSTSP (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GRXSTSR (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
GUSBCFG (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
HNPTXSTS (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
HPTXFSIZ (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
Reserved34 (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
Reserved40 (defined in _USB_OTG_GREGS)_USB_OTG_GREGS
+ +
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+ + diff --git a/struct___u_s_b___o_t_g___g_r_e_g_s.html b/struct___u_s_b___o_t_g___g_r_e_g_s.html new file mode 100644 index 0000000..488eb65 --- /dev/null +++ b/struct___u_s_b___o_t_g___g_r_e_g_s.html @@ -0,0 +1,166 @@ + + + + + + +discoverpixy: _USB_OTG_GREGS Struct Reference + + + + + + + + + + +
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_USB_OTG_GREGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __USB_OTG_Core_register
+
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+Public Attributes

+__IO uint32_t GOTGCTL
 
+__IO uint32_t GOTGINT
 
+__IO uint32_t GAHBCFG
 
+__IO uint32_t GUSBCFG
 
+__IO uint32_t GRSTCTL
 
+__IO uint32_t GINTSTS
 
+__IO uint32_t GINTMSK
 
+__IO uint32_t GRXSTSR
 
+__IO uint32_t GRXSTSP
 
+__IO uint32_t GRXFSIZ
 
+__IO uint32_t DIEPTXF0_HNPTXFSIZ
 
+__IO uint32_t HNPTXSTS
 
+__IO uint32_t GI2CCTL
 
+uint32_t Reserved34
 
+__IO uint32_t GCCFG
 
+__IO uint32_t CID
 
+uint32_t Reserved40 [48]
 
+__IO uint32_t HPTXFSIZ
 
+__IO uint32_t DIEPTXF [USB_OTG_MAX_TX_FIFOS]
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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HCCHAR (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
HCDMA (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
HCGINTMSK (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
HCINT (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
HCSPLT (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
HCTSIZ (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
Reserved (defined in _USB_OTG_HC_REGS)_USB_OTG_HC_REGS
+ +
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_USB_OTG_HC_REGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __Host_Channel_Specific_Registers
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+Public Attributes

+__IO uint32_t HCCHAR
 
+__IO uint32_t HCSPLT
 
+__IO uint32_t HCINT
 
+__IO uint32_t HCGINTMSK
 
+__IO uint32_t HCTSIZ
 
+__IO uint32_t HCDMA
 
+uint32_t Reserved [2]
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
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_USB_OTG_HREGS Member List
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HAINT (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
HAINTMSK (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
HCFG (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
HFIR (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
HFNUM (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
HPTXSTS (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
Reserved40C (defined in _USB_OTG_HREGS)_USB_OTG_HREGS
+ +
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_USB_OTG_HREGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __Host_Mode_Register_Structures
+
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+Public Attributes

+__IO uint32_t HCFG
 
+__IO uint32_t HFIR
 
+__IO uint32_t HFNUM
 
+uint32_t Reserved40C
 
+__IO uint32_t HPTXSTS
 
+__IO uint32_t HAINT
 
+__IO uint32_t HAINTMSK
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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_USB_OTG_INEPREGS Member List
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DIEPCTL (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
DIEPDMA (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
DIEPINT (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
DIEPTSIZ (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
DTXFSTS (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
Reserved04 (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
Reserved0C (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
Reserved18 (defined in _USB_OTG_INEPREGS)_USB_OTG_INEPREGS
+ +
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_USB_OTG_INEPREGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __IN_Endpoint-Specific_Register
+
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+Public Attributes

+__IO uint32_t DIEPCTL
 
+uint32_t Reserved04
 
+__IO uint32_t DIEPINT
 
+uint32_t Reserved0C
 
+__IO uint32_t DIEPTSIZ
 
+__IO uint32_t DIEPDMA
 
+__IO uint32_t DTXFSTS
 
+uint32_t Reserved18
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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_USB_OTG_OUTEPREGS Member List
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DOEPCTL (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
DOEPDMA (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
DOEPINT (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
DOEPTSIZ (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
DOUTEPFRM (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
Reserved0C (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
Reserved18 (defined in _USB_OTG_OUTEPREGS)_USB_OTG_OUTEPREGS
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_USB_OTG_OUTEPREGS Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __OUT_Endpoint-Specific_Registers
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+Public Attributes

+__IO uint32_t DOEPCTL
 
+__IO uint32_t DOUTEPFRM
 
+__IO uint32_t DOEPINT
 
+uint32_t Reserved0C
 
+__IO uint32_t DOEPTSIZ
 
+__IO uint32_t DOEPDMA
 
+uint32_t Reserved18 [2]
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
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_USB_Setup::_SetupPkt_Struc Member List
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bmRequestType (defined in _USB_Setup::_SetupPkt_Struc)_USB_Setup::_SetupPkt_Struc
bRequest (defined in _USB_Setup::_SetupPkt_Struc)_USB_Setup::_SetupPkt_Struc
wIndex (defined in _USB_Setup::_SetupPkt_Struc)_USB_Setup::_SetupPkt_Struc
wLength (defined in _USB_Setup::_SetupPkt_Struc)_USB_Setup::_SetupPkt_Struc
wValue (defined in _USB_Setup::_SetupPkt_Struc)_USB_Setup::_SetupPkt_Struc
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_USB_Setup::_SetupPkt_Struc Struct Reference
USBH_LIB » USBH_LIB_CORE
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+Collaboration diagram for _USB_Setup::_SetupPkt_Struc:
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Collaboration graph
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[legend]
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+Public Attributes

+uint8_t bmRequestType
 
+uint8_t bRequest
 
+uint16_t_uint8_t wValue
 
+uint16_t_uint8_t wIndex
 
+uint16_t_uint8_t wLength
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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_USBD_USR_PROP Member List
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DeviceConfigured (defined in _USBD_USR_PROP)_USBD_USR_PROP
DeviceConnected (defined in _USBD_USR_PROP)_USBD_USR_PROP
DeviceDisconnected (defined in _USBD_USR_PROP)_USBD_USR_PROP
DeviceReset (defined in _USBD_USR_PROP)_USBD_USR_PROP
DeviceResumed (defined in _USBD_USR_PROP)_USBD_USR_PROP
DeviceSuspended (defined in _USBD_USR_PROP)_USBD_USR_PROP
Init (defined in _USBD_USR_PROP)_USBD_USR_PROP
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_USBD_USR_PROP Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+void(* Init )(void)
 
+void(* DeviceReset )(uint8_t speed)
 
+void(* DeviceConfigured )(void)
 
+void(* DeviceSuspended )(void)
 
+void(* DeviceResumed )(void)
 
+void(* DeviceConnected )(void)
 
+void(* DeviceDisconnected )(void)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
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_USBH_CBW_Block::__CBW Member List
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CBWCB (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWFlags (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWLength (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWLUN (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWSignature (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWTag (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
CBWTransferLength (defined in _USBH_CBW_Block::__CBW)_USBH_CBW_Block::__CBW
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_USBH_CBW_Block::__CBW Struct Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT » USBH_MSC_BOT_Exported_Types
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+uint32_t CBWSignature
 
+uint32_t CBWTag
 
+uint32_t CBWTransferLength
 
+uint8_t CBWFlags
 
+uint8_t CBWLUN
 
+uint8_t CBWLength
 
+uint8_t CBWCB [16]
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h
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_USBH_CSW_Block::__CSW Member List
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This is the complete list of members for _USBH_CSW_Block::__CSW, including all inherited members.

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CSWDataResidue (defined in _USBH_CSW_Block::__CSW)_USBH_CSW_Block::__CSW
CSWSignature (defined in _USBH_CSW_Block::__CSW)_USBH_CSW_Block::__CSW
CSWStatus (defined in _USBH_CSW_Block::__CSW)_USBH_CSW_Block::__CSW
CSWTag (defined in _USBH_CSW_Block::__CSW)_USBH_CSW_Block::__CSW
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_USBH_CSW_Block::__CSW Struct Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT » USBH_MSC_BOT_Exported_Types
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+Public Attributes

+uint32_t CSWSignature
 
+uint32_t CSWTag
 
+uint32_t CSWDataResidue
 
+uint8_t CSWStatus
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h
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DeInit (defined in _USBH_Class_cb)_USBH_Class_cb
Init (defined in _USBH_Class_cb)_USBH_Class_cb
Machine (defined in _USBH_Class_cb)_USBH_Class_cb
Requests (defined in _USBH_Class_cb)_USBH_Class_cb
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_USBH_Class_cb Struct Reference
USBH_LIB » USBH_LIB_CORE » USBH_CORE » USBH_CORE_Exported_Types
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+USBH_Status(* Init )(USB_OTG_CORE_HANDLE *pdev, void *phost)
 
+void(* DeInit )(USB_OTG_CORE_HANDLE *pdev, void *phost)
 
+USBH_Status(* Requests )(USB_OTG_CORE_HANDLE *pdev, void *phost)
 
+USBH_Status(* Machine )(USB_OTG_CORE_HANDLE *pdev, void *phost)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h
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_USBH_USR_PROP Member List
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ConfigurationDescAvailable (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeInit (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeviceAddressAssigned (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeviceAttached (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeviceDescAvailable (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeviceDisconnected (defined in _USBH_USR_PROP)_USBH_USR_PROP
DeviceSpeedDetected (defined in _USBH_USR_PROP)_USBH_USR_PROP
EnumerationDone (defined in _USBH_USR_PROP)_USBH_USR_PROP
Init (defined in _USBH_USR_PROP)_USBH_USR_PROP
ManufacturerString (defined in _USBH_USR_PROP)_USBH_USR_PROP
OverCurrentDetected (defined in _USBH_USR_PROP)_USBH_USR_PROP
ProductString (defined in _USBH_USR_PROP)_USBH_USR_PROP
ResetDevice (defined in _USBH_USR_PROP)_USBH_USR_PROP
SerialNumString (defined in _USBH_USR_PROP)_USBH_USR_PROP
UnrecoveredError (defined in _USBH_USR_PROP)_USBH_USR_PROP
USBH_USR_DeviceNotSupported (defined in _USBH_USR_PROP)_USBH_USR_PROP
USBH_USR_MSC_Application (defined in _USBH_USR_PROP)_USBH_USR_PROP
UserInput (defined in _USBH_USR_PROP)_USBH_USR_PROP
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_USBH_USR_PROP Struct Reference
USBH_LIB » USBH_LIB_CORE » USBH_CORE » USBH_CORE_Exported_Types
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+Public Attributes

+void(* Init )(void)
 
+void(* DeInit )(void)
 
+void(* DeviceAttached )(void)
 
+void(* ResetDevice )(void)
 
+void(* DeviceDisconnected )(void)
 
+void(* OverCurrentDetected )(void)
 
+void(* DeviceSpeedDetected )(uint8_t DeviceSpeed)
 
+void(* DeviceDescAvailable )(void *)
 
+void(* DeviceAddressAssigned )(void)
 
+void(* ConfigurationDescAvailable )(USBH_CfgDesc_TypeDef *, USBH_InterfaceDesc_TypeDef *, USBH_EpDesc_TypeDef *)
 
+void(* ManufacturerString )(void *)
 
+void(* ProductString )(void *)
 
+void(* SerialNumString )(void *)
 
+void(* EnumerationDone )(void)
 
+USBH_USR_Status(* UserInput )(void)
 
+int(* USBH_USR_MSC_Application )(void)
 
+void(* USBH_USR_DeviceNotSupported )(void)
 
+void(* UnrecoveredError )(void)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h
    • +
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ADC_Common_TypeDef Member List
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This is the complete list of members for ADC_Common_TypeDef, including all inherited members.

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CCRADC_Common_TypeDef
CDRADC_Common_TypeDef
CSRADC_Common_TypeDef
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ADC_Common_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
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+Public Attributes

__IO uint32_t CSR
 
__IO uint32_t CCR
 
__IO uint32_t CDR
 
+
The documentation for this struct was generated from the following file: +
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ADC_CommonInitTypeDef Member List
+
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+ +

This is the complete list of members for ADC_CommonInitTypeDef, including all inherited members.

+ + + + + +
ADC_DMAAccessModeADC_CommonInitTypeDef
ADC_ModeADC_CommonInitTypeDef
ADC_PrescalerADC_CommonInitTypeDef
ADC_TwoSamplingDelayADC_CommonInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_a_d_c___common_init_type_def.html b/struct_a_d_c___common_init_type_def.html new file mode 100644 index 0000000..ecd92dd --- /dev/null +++ b/struct_a_d_c___common_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: ADC_CommonInitTypeDef Struct Reference + + + + + + + + + + +
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ADC_CommonInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » ADC
+
+
+ +

ADC Common Init structure definition. + More...

+ +

#include <stm32f4xx_adc.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t ADC_Mode
 
uint32_t ADC_Prescaler
 
uint32_t ADC_DMAAccessMode
 
uint32_t ADC_TwoSamplingDelay
 
+

Detailed Description

+

ADC Common Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t ADC_CommonInitTypeDef::ADC_DMAAccessMode
+
+

Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of ADC_Direct_memory_access_mode_for_multi_mode

+ +
+
+ +
+
+ + + + +
uint32_t ADC_CommonInitTypeDef::ADC_Mode
+
+

Configures the ADC to operate in independent or multi mode. This parameter can be a value of ADC_Common_mode

+ +
+
+ +
+
+ + + + +
uint32_t ADC_CommonInitTypeDef::ADC_Prescaler
+
+

Select the frequency of the clock to the ADC. The clock is common for all the ADCs. This parameter can be a value of ADC_Prescaler

+ +
+
+ +
+
+ + + + +
uint32_t ADC_CommonInitTypeDef::ADC_TwoSamplingDelay
+
+

Configures the Delay between 2 sampling phases. This parameter can be a value of ADC_delay_between_2_sampling_phases

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_a_d_c___init_type_def-members.html b/struct_a_d_c___init_type_def-members.html new file mode 100644 index 0000000..e00c273 --- /dev/null +++ b/struct_a_d_c___init_type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ADC_InitTypeDef Member List
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This is the complete list of members for ADC_InitTypeDef, including all inherited members.

+ + + + + + + + +
ADC_ContinuousConvModeADC_InitTypeDef
ADC_DataAlignADC_InitTypeDef
ADC_ExternalTrigConvADC_InitTypeDef
ADC_ExternalTrigConvEdgeADC_InitTypeDef
ADC_NbrOfConversionADC_InitTypeDef
ADC_ResolutionADC_InitTypeDef
ADC_ScanConvModeADC_InitTypeDef
+ +
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+ + diff --git a/struct_a_d_c___init_type_def.html b/struct_a_d_c___init_type_def.html new file mode 100644 index 0000000..92135a8 --- /dev/null +++ b/struct_a_d_c___init_type_def.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: ADC_InitTypeDef Struct Reference + + + + + + + + + + +
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ADC_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » ADC
+
+
+ +

ADC Init structure definition. + More...

+ +

#include <stm32f4xx_adc.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t ADC_Resolution
 
FunctionalState ADC_ScanConvMode
 
FunctionalState ADC_ContinuousConvMode
 
uint32_t ADC_ExternalTrigConvEdge
 
uint32_t ADC_ExternalTrigConv
 
uint32_t ADC_DataAlign
 
uint8_t ADC_NbrOfConversion
 
+

Detailed Description

+

ADC Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
FunctionalState ADC_InitTypeDef::ADC_ContinuousConvMode
+
+

Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
uint32_t ADC_InitTypeDef::ADC_DataAlign
+
+

Specifies whether the ADC data alignment is left or right. This parameter can be a value of ADC_data_align

+ +
+
+ +
+
+ + + + +
uint32_t ADC_InitTypeDef::ADC_ExternalTrigConv
+
+

Select the external event used to trigger the start of conversion of a regular group. This parameter can be a value of ADC_extrenal_trigger_sources_for_regular_channels_conversion

+ +
+
+ +
+
+ + + + +
uint32_t ADC_InitTypeDef::ADC_ExternalTrigConvEdge
+
+

Select the external trigger edge and enable the trigger of a regular group. This parameter can be a value of ADC_external_trigger_edge_for_regular_channels_conversion

+ +
+
+ +
+
+ + + + +
uint8_t ADC_InitTypeDef::ADC_NbrOfConversion
+
+

Specifies the number of ADC conversions that will be done using the sequencer for regular channel group. This parameter must range from 1 to 16.

+ +
+
+ +
+
+ + + + +
uint32_t ADC_InitTypeDef::ADC_Resolution
+
+

Configures the ADC resolution dual mode. This parameter can be a value of ADC_resolution

+ +
+
+ +
+
+ + + + +
FunctionalState ADC_InitTypeDef::ADC_ScanConvMode
+
+

Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE

+ +
+
+
The documentation for this struct was generated from the following file: +
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This is the complete list of members for ADC_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + +
CR1ADC_TypeDef
CR2ADC_TypeDef
DRADC_TypeDef
HTRADC_TypeDef
JDR1ADC_TypeDef
JDR2ADC_TypeDef
JDR3ADC_TypeDef
JDR4ADC_TypeDef
JOFR1ADC_TypeDef
JOFR2ADC_TypeDef
JOFR3ADC_TypeDef
JOFR4ADC_TypeDef
JSQRADC_TypeDef
LTRADC_TypeDef
SMPR1ADC_TypeDef
SMPR2ADC_TypeDef
SQR1ADC_TypeDef
SQR2ADC_TypeDef
SQR3ADC_TypeDef
SRADC_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_a_d_c___type_def.html b/struct_a_d_c___type_def.html new file mode 100644 index 0000000..8763bd4 --- /dev/null +++ b/struct_a_d_c___type_def.html @@ -0,0 +1,156 @@ + + + + + + +discoverpixy: ADC_TypeDef Struct Reference + + + + + + + + + + +
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ADC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Analog to Digital Converter. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t SR
 
__IO uint32_t CR1
 
__IO uint32_t CR2
 
__IO uint32_t SMPR1
 
__IO uint32_t SMPR2
 
__IO uint32_t JOFR1
 
__IO uint32_t JOFR2
 
__IO uint32_t JOFR3
 
__IO uint32_t JOFR4
 
__IO uint32_t HTR
 
__IO uint32_t LTR
 
__IO uint32_t SQR1
 
__IO uint32_t SQR2
 
__IO uint32_t SQR3
 
__IO uint32_t JSQR
 
__IO uint32_t JDR1
 
__IO uint32_t JDR2
 
__IO uint32_t JDR3
 
__IO uint32_t JDR4
 
__IO uint32_t DR
 
+

Detailed Description

+

Analog to Digital Converter.

+
The documentation for this struct was generated from the following file: +
+ +
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BUTTON_STRUCT Member List
+
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This is the complete list of members for BUTTON_STRUCT, including all inherited members.

+ + + + + + + +
base (defined in BUTTON_STRUCT)BUTTON_STRUCT
bgcolor (defined in BUTTON_STRUCT)BUTTON_STRUCT
callback (defined in BUTTON_STRUCT)BUTTON_STRUCT
font (defined in BUTTON_STRUCT)BUTTON_STRUCT
text (defined in BUTTON_STRUCT)BUTTON_STRUCT
txtcolor (defined in BUTTON_STRUCT)BUTTON_STRUCT
+ +
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BUTTON_STRUCT Struct Reference
Gui » Button
+
+
+ +

#include <button.h>

+
+Collaboration diagram for BUTTON_STRUCT:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Data Fields

TOUCH_AREA_STRUCT base
 Basic geometry of the button. You only need to set the x1, y1, x2, y2 members of this struct. More...
 
uint16_t bgcolor
 The 16-bit background color of the button. More...
 
BUTTON_CALLBACK callback
 Callback. More...
 
uint16_t txtcolor
 The 16-bit text color. More...
 
uint8_t font
 The number of the font to use. More...
 
const char * text
 The label of the button. More...
 
+

Detailed Description

+

Structure to configure the Button

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.map b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.map new file mode 100644 index 0000000..e1958d1 --- /dev/null +++ b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.md5 b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.md5 new file mode 100644 index 0000000..1e54cd6 --- /dev/null +++ b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.md5 @@ -0,0 +1 @@ +c6cb4cc0fbcf95293aff057250b57a3f \ No newline at end of file diff --git a/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.png b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.png new file mode 100644 index 0000000..c68b009 Binary files /dev/null and b/struct_b_u_t_t_o_n___s_t_r_u_c_t__coll__graph.png differ diff --git a/struct_blob_a-members.html b/struct_blob_a-members.html new file mode 100644 index 0000000..1788586 --- /dev/null +++ b/struct_blob_a-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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BlobA() (defined in BlobA)BlobAinline
BlobA(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom) (defined in BlobA)BlobAinline
BlobA() (defined in BlobA)BlobAinline
BlobA(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom) (defined in BlobA)BlobAinline
m_bottom (defined in BlobA)BlobA
m_left (defined in BlobA)BlobA
m_model (defined in BlobA)BlobA
m_right (defined in BlobA)BlobA
m_top (defined in BlobA)BlobA
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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BlobA Struct Reference
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+Public Member Functions

+ BlobA (uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
 
+ BlobA (uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
 
+ + + + + + + + + + + +

+Public Attributes

+uint16_t m_model
 
+uint16_t m_left
 
+uint16_t m_right
 
+uint16_t m_top
 
+uint16_t m_bottom
 
+
The documentation for this struct was generated from the following file: +
+ +
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BlobB() (defined in BlobB)BlobBinline
BlobB(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle) (defined in BlobB)BlobBinline
BlobB() (defined in BlobB)BlobBinline
BlobB(uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle) (defined in BlobB)BlobBinline
m_angle (defined in BlobB)BlobB
m_bottom (defined in BlobB)BlobB
m_left (defined in BlobB)BlobB
m_model (defined in BlobB)BlobB
m_right (defined in BlobB)BlobB
m_top (defined in BlobB)BlobB
+ +
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BlobB Struct Reference
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+Public Member Functions

+ BlobB (uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle)
 
+ BlobB (uint16_t model, uint16_t left, uint16_t right, uint16_t top, uint16_t bottom, int16_t angle)
 
+ + + + + + + + + + + + + +

+Public Attributes

+uint16_t m_model
 
+uint16_t m_left
 
+uint16_t m_right
 
+uint16_t m_top
 
+uint16_t m_bottom
 
+int16_t m_angle
 
+
The documentation for this struct was generated from the following file: +
+ +
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Block Member List
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This is the complete list of members for Block, including all inherited members.

+ + + + + + + + +
angle (defined in Block)Block
height (defined in Block)Block
signature (defined in Block)Block
type (defined in Block)Block
width (defined in Block)Block
x (defined in Block)Block
y (defined in Block)Block
+ +
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Block Struct Reference
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#include <pixy.h>

+ + + + + + + + + + + + + + + + +

+Data Fields

uint16_t type
 
uint16_t signature
 
uint16_t x
 
uint16_t y
 
uint16_t width
 
uint16_t height
 
int16_t angle
 
+

Field Documentation

+ +
+
+ + + + +
int16_t angle
+
+ +
+
+ +
+
+ + + + +
uint16_t height
+
+ +
+
+ +
+
+ + + + +
uint16_t signature
+
+ +
+
+ +
+
+ + + + +
uint16_t type
+
+ +
+
+ +
+
+ + + + +
uint16_t width
+
+ +
+
+ +
+
+ + + + +
uint16_t x
+
+ +
+
+ +
+
+ + + + +
uint16_t y
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___f_i_f_o_mail_box___type_def-members.html b/struct_c_a_n___f_i_f_o_mail_box___type_def-members.html new file mode 100644 index 0000000..ad6b005 --- /dev/null +++ b/struct_c_a_n___f_i_f_o_mail_box___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_FIFOMailBox_TypeDef Member List
+
+
+ +

This is the complete list of members for CAN_FIFOMailBox_TypeDef, including all inherited members.

+ + + + + +
RDHRCAN_FIFOMailBox_TypeDef
RDLRCAN_FIFOMailBox_TypeDef
RDTRCAN_FIFOMailBox_TypeDef
RIRCAN_FIFOMailBox_TypeDef
+ +
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CAN_FIFOMailBox_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Controller Area Network FIFOMailBox. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t RIR
 
__IO uint32_t RDTR
 
__IO uint32_t RDLR
 
__IO uint32_t RDHR
 
+

Detailed Description

+

Controller Area Network FIFOMailBox.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___filter_init_type_def-members.html b/struct_c_a_n___filter_init_type_def-members.html new file mode 100644 index 0000000..d391a44 --- /dev/null +++ b/struct_c_a_n___filter_init_type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_FilterInitTypeDef Member List
+
+
+ +

This is the complete list of members for CAN_FilterInitTypeDef, including all inherited members.

+ + + + + + + + + + +
CAN_FilterActivationCAN_FilterInitTypeDef
CAN_FilterFIFOAssignmentCAN_FilterInitTypeDef
CAN_FilterIdHighCAN_FilterInitTypeDef
CAN_FilterIdLowCAN_FilterInitTypeDef
CAN_FilterMaskIdHighCAN_FilterInitTypeDef
CAN_FilterMaskIdLowCAN_FilterInitTypeDef
CAN_FilterModeCAN_FilterInitTypeDef
CAN_FilterNumberCAN_FilterInitTypeDef
CAN_FilterScaleCAN_FilterInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___filter_init_type_def.html b/struct_c_a_n___filter_init_type_def.html new file mode 100644 index 0000000..05fb5f3 --- /dev/null +++ b/struct_c_a_n___filter_init_type_def.html @@ -0,0 +1,252 @@ + + + + + + +discoverpixy: CAN_FilterInitTypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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CAN_FilterInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » CAN
+
+
+ +

CAN filter init structure definition. + More...

+ +

#include <stm32f4xx_can.h>

+ + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t CAN_FilterIdHigh
 
uint16_t CAN_FilterIdLow
 
uint16_t CAN_FilterMaskIdHigh
 
uint16_t CAN_FilterMaskIdLow
 
uint16_t CAN_FilterFIFOAssignment
 
uint8_t CAN_FilterNumber
 
uint8_t CAN_FilterMode
 
uint8_t CAN_FilterScale
 
FunctionalState CAN_FilterActivation
 
+

Detailed Description

+

CAN filter init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
FunctionalState CAN_FilterInitTypeDef::CAN_FilterActivation
+
+

Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
uint16_t CAN_FilterInitTypeDef::CAN_FilterFIFOAssignment
+
+

Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of CAN_filter_FIFO

+ +
+
+ +
+
+ + + + +
uint16_t CAN_FilterInitTypeDef::CAN_FilterIdHigh
+
+

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

+ +
+
+ +
+
+ + + + +
uint16_t CAN_FilterInitTypeDef::CAN_FilterIdLow
+
+

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

+ +
+
+ +
+
+ + + + +
uint16_t CAN_FilterInitTypeDef::CAN_FilterMaskIdHigh
+
+

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

+ +
+
+ +
+
+ + + + +
uint16_t CAN_FilterInitTypeDef::CAN_FilterMaskIdLow
+
+

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF

+ +
+
+ +
+
+ + + + +
uint8_t CAN_FilterInitTypeDef::CAN_FilterMode
+
+

Specifies the filter mode to be initialized. This parameter can be a value of CAN_filter_mode

+ +
+
+ +
+
+ + + + +
uint8_t CAN_FilterInitTypeDef::CAN_FilterNumber
+
+

Specifies the filter which will be initialized. It ranges from 0 to 13.

+ +
+
+ +
+
+ + + + +
uint8_t CAN_FilterInitTypeDef::CAN_FilterScale
+
+

Specifies the filter scale. This parameter can be a value of CAN_filter_scale

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___filter_register___type_def-members.html b/struct_c_a_n___filter_register___type_def-members.html new file mode 100644 index 0000000..2a03e5a --- /dev/null +++ b/struct_c_a_n___filter_register___type_def-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_FilterRegister_TypeDef Member List
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This is the complete list of members for CAN_FilterRegister_TypeDef, including all inherited members.

+ + + +
FR1CAN_FilterRegister_TypeDef
FR2CAN_FilterRegister_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___filter_register___type_def.html b/struct_c_a_n___filter_register___type_def.html new file mode 100644 index 0000000..e1d58f6 --- /dev/null +++ b/struct_c_a_n___filter_register___type_def.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: CAN_FilterRegister_TypeDef Struct Reference + + + + + + + + + + +
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CAN_FilterRegister_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Controller Area Network FilterRegister. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + +

+Public Attributes

__IO uint32_t FR1
 
__IO uint32_t FR2
 
+

Detailed Description

+

Controller Area Network FilterRegister.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___init_type_def-members.html b/struct_c_a_n___init_type_def-members.html new file mode 100644 index 0000000..0d7d50a --- /dev/null +++ b/struct_c_a_n___init_type_def-members.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_InitTypeDef Member List
+
+
+ +

This is the complete list of members for CAN_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + +
CAN_ABOMCAN_InitTypeDef
CAN_AWUMCAN_InitTypeDef
CAN_BS1CAN_InitTypeDef
CAN_BS2CAN_InitTypeDef
CAN_ModeCAN_InitTypeDef
CAN_NARTCAN_InitTypeDef
CAN_PrescalerCAN_InitTypeDef
CAN_RFLMCAN_InitTypeDef
CAN_SJWCAN_InitTypeDef
CAN_TTCMCAN_InitTypeDef
CAN_TXFPCAN_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___init_type_def.html b/struct_c_a_n___init_type_def.html new file mode 100644 index 0000000..b8ef134 --- /dev/null +++ b/struct_c_a_n___init_type_def.html @@ -0,0 +1,282 @@ + + + + + + +discoverpixy: CAN_InitTypeDef Struct Reference + + + + + + + + + + +
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CAN_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » CAN
+
+
+ +

CAN init structure definition. + More...

+ +

#include <stm32f4xx_can.h>

+ + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t CAN_Prescaler
 
uint8_t CAN_Mode
 
uint8_t CAN_SJW
 
uint8_t CAN_BS1
 
uint8_t CAN_BS2
 
FunctionalState CAN_TTCM
 
FunctionalState CAN_ABOM
 
FunctionalState CAN_AWUM
 
FunctionalState CAN_NART
 
FunctionalState CAN_RFLM
 
FunctionalState CAN_TXFP
 
+

Detailed Description

+

CAN init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_ABOM
+
+

Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_AWUM
+
+

Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
uint8_t CAN_InitTypeDef::CAN_BS1
+
+

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN_time_quantum_in_bit_segment_1

+ +
+
+ +
+
+ + + + +
uint8_t CAN_InitTypeDef::CAN_BS2
+
+

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN_time_quantum_in_bit_segment_2

+ +
+
+ +
+
+ + + + +
uint8_t CAN_InitTypeDef::CAN_Mode
+
+

Specifies the CAN operating mode. This parameter can be a value of CAN_operating_mode

+ +
+
+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_NART
+
+

Enable or disable the non-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
uint16_t CAN_InitTypeDef::CAN_Prescaler
+
+

Specifies the length of a time quantum. It ranges from 1 to 1024.

+ +
+
+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_RFLM
+
+

Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
uint8_t CAN_InitTypeDef::CAN_SJW
+
+

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN_synchronisation_jump_width

+ +
+
+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_TTCM
+
+

Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+ +
+
+ + + + +
FunctionalState CAN_InitTypeDef::CAN_TXFP
+
+

Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_a_n___tx_mail_box___type_def-members.html b/struct_c_a_n___tx_mail_box___type_def-members.html new file mode 100644 index 0000000..5da0baf --- /dev/null +++ b/struct_c_a_n___tx_mail_box___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_TxMailBox_TypeDef Member List
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This is the complete list of members for CAN_TxMailBox_TypeDef, including all inherited members.

+ + + + + +
TDHRCAN_TxMailBox_TypeDef
TDLRCAN_TxMailBox_TypeDef
TDTRCAN_TxMailBox_TypeDef
TIRCAN_TxMailBox_TypeDef
+ +
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+ + diff --git a/struct_c_a_n___tx_mail_box___type_def.html b/struct_c_a_n___tx_mail_box___type_def.html new file mode 100644 index 0000000..02b3d24 --- /dev/null +++ b/struct_c_a_n___tx_mail_box___type_def.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: CAN_TxMailBox_TypeDef Struct Reference + + + + + + + + + + +
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CAN_TxMailBox_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Controller Area Network TxMailBox. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t TIR
 
__IO uint32_t TDTR
 
__IO uint32_t TDLR
 
__IO uint32_t TDHR
 
+

Detailed Description

+

Controller Area Network TxMailBox.

+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_c_a_n___type_def-members.html b/struct_c_a_n___type_def-members.html new file mode 100644 index 0000000..1f5c178 --- /dev/null +++ b/struct_c_a_n___type_def-members.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CAN_TypeDef Member List
+
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This is the complete list of members for CAN_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + +
BTRCAN_TypeDef
ESRCAN_TypeDef
FA1RCAN_TypeDef
FFA1RCAN_TypeDef
FM1RCAN_TypeDef
FMRCAN_TypeDef
FS1RCAN_TypeDef
IERCAN_TypeDef
MCRCAN_TypeDef
MSRCAN_TypeDef
RESERVED0CAN_TypeDef
RESERVED1CAN_TypeDef
RESERVED2CAN_TypeDef
RESERVED3CAN_TypeDef
RESERVED4CAN_TypeDef
RESERVED5CAN_TypeDef
RF0RCAN_TypeDef
RF1RCAN_TypeDef
sFIFOMailBoxCAN_TypeDef
sFilterRegisterCAN_TypeDef
sTxMailBoxCAN_TypeDef
TSRCAN_TypeDef
+ +
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+ + diff --git a/struct_c_a_n___type_def.html b/struct_c_a_n___type_def.html new file mode 100644 index 0000000..a72590c --- /dev/null +++ b/struct_c_a_n___type_def.html @@ -0,0 +1,167 @@ + + + + + + +discoverpixy: CAN_TypeDef Struct Reference + + + + + + + + + + +
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CAN_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Controller Area Network. + More...

+ +

#include <stm32f4xx.h>

+
+Collaboration diagram for CAN_TypeDef:
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Collaboration graph
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[legend]
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+Public Attributes

__IO uint32_t MCR
 
__IO uint32_t MSR
 
__IO uint32_t TSR
 
__IO uint32_t RF0R
 
__IO uint32_t RF1R
 
__IO uint32_t IER
 
__IO uint32_t ESR
 
__IO uint32_t BTR
 
uint32_t RESERVED0 [88]
 
CAN_TxMailBox_TypeDef sTxMailBox [3]
 
CAN_FIFOMailBox_TypeDef sFIFOMailBox [2]
 
uint32_t RESERVED1 [12]
 
__IO uint32_t FMR
 
__IO uint32_t FM1R
 
uint32_t RESERVED2
 
__IO uint32_t FS1R
 
uint32_t RESERVED3
 
__IO uint32_t FFA1R
 
uint32_t RESERVED4
 
__IO uint32_t FA1R
 
uint32_t RESERVED5 [8]
 
CAN_FilterRegister_TypeDef sFilterRegister [28]
 
+

Detailed Description

+

Controller Area Network.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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CHECKBOX_STRUCT Member List
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This is the complete list of members for CHECKBOX_STRUCT, including all inherited members.

+ + + + + +
base (defined in CHECKBOX_STRUCT)CHECKBOX_STRUCT
callback (defined in CHECKBOX_STRUCT)CHECKBOX_STRUCT
checked (defined in CHECKBOX_STRUCT)CHECKBOX_STRUCT
fgcolor (defined in CHECKBOX_STRUCT)CHECKBOX_STRUCT
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CHECKBOX_STRUCT Struct Reference
Gui » Checkbox
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#include <checkbox.h>

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+Collaboration diagram for CHECKBOX_STRUCT:
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Collaboration graph
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+Data Fields

TOUCH_AREA_STRUCT base
 
uint16_t fgcolor
 
bool checked
 
CHECKBOX_CALLBACK callback
 
+
The documentation for this struct was generated from the following file: +
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CRC_TypeDef Member List
+
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This is the complete list of members for CRC_TypeDef, including all inherited members.

+ + + + + + +
CRCRC_TypeDef
DRCRC_TypeDef
IDRCRC_TypeDef
RESERVED0CRC_TypeDef
RESERVED1CRC_TypeDef
+ +
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CRC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

CRC calculation unit. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + +

+Public Attributes

__IO uint32_t DR
 
__IO uint8_t IDR
 
uint8_t RESERVED0
 
uint16_t RESERVED1
 
__IO uint32_t CR
 
+

Detailed Description

+

CRC calculation unit.

+
The documentation for this struct was generated from the following file: +
+ +
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This is the complete list of members for CRYP_Context, including all inherited members.

+ + + + + + + + + + + + + + + + +
CR_CurrentConfigCRYP_Context
CRYP_CSGCMCCMR (defined in CRYP_Context)CRYP_Context
CRYP_CSGCMR (defined in CRYP_Context)CRYP_Context
CRYP_IV0LR (defined in CRYP_Context)CRYP_Context
CRYP_IV0RR (defined in CRYP_Context)CRYP_Context
CRYP_IV1LR (defined in CRYP_Context)CRYP_Context
CRYP_IV1RRCRYP_Context
CRYP_K0LR (defined in CRYP_Context)CRYP_Context
CRYP_K0RR (defined in CRYP_Context)CRYP_Context
CRYP_K1LR (defined in CRYP_Context)CRYP_Context
CRYP_K1RR (defined in CRYP_Context)CRYP_Context
CRYP_K2LR (defined in CRYP_Context)CRYP_Context
CRYP_K2RR (defined in CRYP_Context)CRYP_Context
CRYP_K3LR (defined in CRYP_Context)CRYP_Context
CRYP_K3RR (defined in CRYP_Context)CRYP_Context
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___context.html b/struct_c_r_y_p___context.html new file mode 100644 index 0000000..340916b --- /dev/null +++ b/struct_c_r_y_p___context.html @@ -0,0 +1,186 @@ + + + + + + +discoverpixy: CRYP_Context Struct Reference + + + + + + + + + + +
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CRYP_Context Struct Reference
STM32F4xx_StdPeriph_Driver » CRYP
+
+
+ +

CRYP context swapping structure definition. + More...

+ +

#include <stm32f4xx_cryp.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t CR_CurrentConfig
 
+uint32_t CRYP_IV0LR
 
+uint32_t CRYP_IV0RR
 
+uint32_t CRYP_IV1LR
 
uint32_t CRYP_IV1RR
 
+uint32_t CRYP_K0LR
 
+uint32_t CRYP_K0RR
 
+uint32_t CRYP_K1LR
 
+uint32_t CRYP_K1RR
 
+uint32_t CRYP_K2LR
 
+uint32_t CRYP_K2RR
 
+uint32_t CRYP_K3LR
 
+uint32_t CRYP_K3RR
 
+uint32_t CRYP_CSGCMCCMR [8]
 
+uint32_t CRYP_CSGCMR [8]
 
+

Detailed Description

+

CRYP context swapping structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t CRYP_Context::CR_CurrentConfig
+
+

< Current Configuration IV

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_Context::CRYP_IV1RR
+
+

KEY

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___i_v_init_type_def-members.html b/struct_c_r_y_p___i_v_init_type_def-members.html new file mode 100644 index 0000000..ed44ead --- /dev/null +++ b/struct_c_r_y_p___i_v_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CRYP_IVInitTypeDef Member List
+
+
+ +

This is the complete list of members for CRYP_IVInitTypeDef, including all inherited members.

+ + + + + +
CRYP_IV0LeftCRYP_IVInitTypeDef
CRYP_IV0RightCRYP_IVInitTypeDef
CRYP_IV1LeftCRYP_IVInitTypeDef
CRYP_IV1RightCRYP_IVInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___i_v_init_type_def.html b/struct_c_r_y_p___i_v_init_type_def.html new file mode 100644 index 0000000..476fc51 --- /dev/null +++ b/struct_c_r_y_p___i_v_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: CRYP_IVInitTypeDef Struct Reference + + + + + + + + + + +
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CRYP_IVInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » CRYP
+
+
+ +

CRYP Initialization Vectors (IV) structure definition. + More...

+ +

#include <stm32f4xx_cryp.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t CRYP_IV0Left
 
uint32_t CRYP_IV0Right
 
uint32_t CRYP_IV1Left
 
uint32_t CRYP_IV1Right
 
+

Detailed Description

+

CRYP Initialization Vectors (IV) structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t CRYP_IVInitTypeDef::CRYP_IV0Left
+
+

Init Vector 0 Left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_IVInitTypeDef::CRYP_IV0Right
+
+

Init Vector 0 Right

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_IVInitTypeDef::CRYP_IV1Left
+
+

Init Vector 1 left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_IVInitTypeDef::CRYP_IV1Right
+
+

Init Vector 1 Right

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___init_type_def-members.html b/struct_c_r_y_p___init_type_def-members.html new file mode 100644 index 0000000..259d12b --- /dev/null +++ b/struct_c_r_y_p___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CRYP_InitTypeDef Member List
+
+
+ +

This is the complete list of members for CRYP_InitTypeDef, including all inherited members.

+ + + + + +
CRYP_AlgoDirCRYP_InitTypeDef
CRYP_AlgoModeCRYP_InitTypeDef
CRYP_DataTypeCRYP_InitTypeDef
CRYP_KeySizeCRYP_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___init_type_def.html b/struct_c_r_y_p___init_type_def.html new file mode 100644 index 0000000..eee726c --- /dev/null +++ b/struct_c_r_y_p___init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: CRYP_InitTypeDef Struct Reference + + + + + + + + + + +
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CRYP_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » CRYP
+
+
+ +

CRYP Init structure definition. + More...

+ +

#include <stm32f4xx_cryp.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t CRYP_AlgoDir
 
uint32_t CRYP_AlgoMode
 
uint32_t CRYP_DataType
 
uint32_t CRYP_KeySize
 
+

Detailed Description

+

CRYP Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t CRYP_InitTypeDef::CRYP_AlgoDir
+
+

Encrypt or Decrypt. This parameter can be a value of CRYP_Algorithm_Direction

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_InitTypeDef::CRYP_AlgoMode
+
+

TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. This parameter can be a value of CRYP_Algorithm_Mode

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_InitTypeDef::CRYP_DataType
+
+

32-bit data, 16-bit data, bit data or bit string. This parameter can be a value of CRYP_Data_Type

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_InitTypeDef::CRYP_KeySize
+
+

Used only in AES mode only : 128, 192 or 256 bit key length. This parameter can be a value of CRYP_Key_Size_for_AES_only

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___key_init_type_def-members.html b/struct_c_r_y_p___key_init_type_def-members.html new file mode 100644 index 0000000..017d923 --- /dev/null +++ b/struct_c_r_y_p___key_init_type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CRYP_KeyInitTypeDef Member List
+
+
+ +

This is the complete list of members for CRYP_KeyInitTypeDef, including all inherited members.

+ + + + + + + + + +
CRYP_Key0LeftCRYP_KeyInitTypeDef
CRYP_Key0RightCRYP_KeyInitTypeDef
CRYP_Key1LeftCRYP_KeyInitTypeDef
CRYP_Key1RightCRYP_KeyInitTypeDef
CRYP_Key2LeftCRYP_KeyInitTypeDef
CRYP_Key2RightCRYP_KeyInitTypeDef
CRYP_Key3LeftCRYP_KeyInitTypeDef
CRYP_Key3RightCRYP_KeyInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___key_init_type_def.html b/struct_c_r_y_p___key_init_type_def.html new file mode 100644 index 0000000..7f79aac --- /dev/null +++ b/struct_c_r_y_p___key_init_type_def.html @@ -0,0 +1,237 @@ + + + + + + +discoverpixy: CRYP_KeyInitTypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
+
+
CRYP_KeyInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » CRYP
+
+
+ +

CRYP Key(s) structure definition. + More...

+ +

#include <stm32f4xx_cryp.h>

+ + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t CRYP_Key0Left
 
uint32_t CRYP_Key0Right
 
uint32_t CRYP_Key1Left
 
uint32_t CRYP_Key1Right
 
uint32_t CRYP_Key2Left
 
uint32_t CRYP_Key2Right
 
uint32_t CRYP_Key3Left
 
uint32_t CRYP_Key3Right
 
+

Detailed Description

+

CRYP Key(s) structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key0Left
+
+

Key 0 Left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key0Right
+
+

Key 0 Right

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key1Left
+
+

Key 1 left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key1Right
+
+

Key 1 Right

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key2Left
+
+

Key 2 left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key2Right
+
+

Key 2 Right

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key3Left
+
+

Key 3 left

+ +
+
+ +
+
+ + + + +
uint32_t CRYP_KeyInitTypeDef::CRYP_Key3Right
+
+

Key 3 Right

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___type_def-members.html b/struct_c_r_y_p___type_def-members.html new file mode 100644 index 0000000..139e51f --- /dev/null +++ b/struct_c_r_y_p___type_def-members.html @@ -0,0 +1,138 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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This is the complete list of members for CRYP_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CRCRYP_TypeDef
CSGCM0RCRYP_TypeDef
CSGCM1RCRYP_TypeDef
CSGCM2RCRYP_TypeDef
CSGCM3RCRYP_TypeDef
CSGCM4RCRYP_TypeDef
CSGCM5RCRYP_TypeDef
CSGCM6RCRYP_TypeDef
CSGCM7RCRYP_TypeDef
CSGCMCCM0RCRYP_TypeDef
CSGCMCCM1RCRYP_TypeDef
CSGCMCCM2RCRYP_TypeDef
CSGCMCCM3RCRYP_TypeDef
CSGCMCCM4RCRYP_TypeDef
CSGCMCCM5RCRYP_TypeDef
CSGCMCCM6RCRYP_TypeDef
CSGCMCCM7RCRYP_TypeDef
DMACRCRYP_TypeDef
DOUTCRYP_TypeDef
DRCRYP_TypeDef
IMSCRCRYP_TypeDef
IV0LRCRYP_TypeDef
IV0RRCRYP_TypeDef
IV1LRCRYP_TypeDef
IV1RRCRYP_TypeDef
K0LRCRYP_TypeDef
K0RRCRYP_TypeDef
K1LRCRYP_TypeDef
K1RRCRYP_TypeDef
K2LRCRYP_TypeDef
K2RRCRYP_TypeDef
K3LRCRYP_TypeDef
K3RRCRYP_TypeDef
MISRCRYP_TypeDef
RISRCRYP_TypeDef
SRCRYP_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_c_r_y_p___type_def.html b/struct_c_r_y_p___type_def.html new file mode 100644 index 0000000..47104b8 --- /dev/null +++ b/struct_c_r_y_p___type_def.html @@ -0,0 +1,188 @@ + + + + + + +discoverpixy: CRYP_TypeDef Struct Reference + + + + + + + + + + +
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CRYP_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Crypto Processor. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t DR
 
__IO uint32_t DOUT
 
__IO uint32_t DMACR
 
__IO uint32_t IMSCR
 
__IO uint32_t RISR
 
__IO uint32_t MISR
 
__IO uint32_t K0LR
 
__IO uint32_t K0RR
 
__IO uint32_t K1LR
 
__IO uint32_t K1RR
 
__IO uint32_t K2LR
 
__IO uint32_t K2RR
 
__IO uint32_t K3LR
 
__IO uint32_t K3RR
 
__IO uint32_t IV0LR
 
__IO uint32_t IV0RR
 
__IO uint32_t IV1LR
 
__IO uint32_t IV1RR
 
__IO uint32_t CSGCMCCM0R
 
__IO uint32_t CSGCMCCM1R
 
__IO uint32_t CSGCMCCM2R
 
__IO uint32_t CSGCMCCM3R
 
__IO uint32_t CSGCMCCM4R
 
__IO uint32_t CSGCMCCM5R
 
__IO uint32_t CSGCMCCM6R
 
__IO uint32_t CSGCMCCM7R
 
__IO uint32_t CSGCM0R
 
__IO uint32_t CSGCM1R
 
__IO uint32_t CSGCM2R
 
__IO uint32_t CSGCM3R
 
__IO uint32_t CSGCM4R
 
__IO uint32_t CSGCM5R
 
__IO uint32_t CSGCM6R
 
__IO uint32_t CSGCM7R
 
+

Detailed Description

+

Crypto Processor.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_can_rx_msg-members.html b/struct_can_rx_msg-members.html new file mode 100644 index 0000000..76e1b63 --- /dev/null +++ b/struct_can_rx_msg-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CanRxMsg Member List
+
+
+ +

This is the complete list of members for CanRxMsg, including all inherited members.

+ + + + + + + + +
DataCanRxMsg
DLCCanRxMsg
ExtIdCanRxMsg
FMICanRxMsg
IDECanRxMsg
RTRCanRxMsg
StdIdCanRxMsg
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_can_rx_msg.html b/struct_can_rx_msg.html new file mode 100644 index 0000000..41fef58 --- /dev/null +++ b/struct_can_rx_msg.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: CanRxMsg Struct Reference + + + + + + + + + + +
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CanRxMsg Struct Reference
STM32F4xx_StdPeriph_Driver » CAN
+
+
+ +

CAN Rx message structure definition. + More...

+ +

#include <stm32f4xx_can.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t StdId
 
uint32_t ExtId
 
uint8_t IDE
 
uint8_t RTR
 
uint8_t DLC
 
uint8_t Data [8]
 
uint8_t FMI
 
+

Detailed Description

+

CAN Rx message structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t CanRxMsg::Data[8]
+
+

Contains the data to be received. It ranges from 0 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint8_t CanRxMsg::DLC
+
+

Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8

+ +
+
+ +
+
+ + + + +
uint32_t CanRxMsg::ExtId
+
+

Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.

+ +
+
+ +
+
+ + + + +
uint8_t CanRxMsg::FMI
+
+

Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF

+ +
+
+ +
+
+ + + + +
uint8_t CanRxMsg::IDE
+
+

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN_identifier_type

+ +
+
+ +
+
+ + + + +
uint8_t CanRxMsg::RTR
+
+

Specifies the type of frame for the received message. This parameter can be a value of CAN_remote_transmission_request

+ +
+
+ +
+
+ + + + +
uint32_t CanRxMsg::StdId
+
+

Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_can_tx_msg-members.html b/struct_can_tx_msg-members.html new file mode 100644 index 0000000..50e701c --- /dev/null +++ b/struct_can_tx_msg-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CanTxMsg Member List
+
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This is the complete list of members for CanTxMsg, including all inherited members.

+ + + + + + + +
DataCanTxMsg
DLCCanTxMsg
ExtIdCanTxMsg
IDECanTxMsg
RTRCanTxMsg
StdIdCanTxMsg
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_can_tx_msg.html b/struct_can_tx_msg.html new file mode 100644 index 0000000..1ecd6b9 --- /dev/null +++ b/struct_can_tx_msg.html @@ -0,0 +1,207 @@ + + + + + + +discoverpixy: CanTxMsg Struct Reference + + + + + + + + + + +
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CanTxMsg Struct Reference
STM32F4xx_StdPeriph_Driver » CAN
+
+
+ +

CAN Tx message structure definition. + More...

+ +

#include <stm32f4xx_can.h>

+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t StdId
 
uint32_t ExtId
 
uint8_t IDE
 
uint8_t RTR
 
uint8_t DLC
 
uint8_t Data [8]
 
+

Detailed Description

+

CAN Tx message structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t CanTxMsg::Data[8]
+
+

Contains the data to be transmitted. It ranges from 0 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint8_t CanTxMsg::DLC
+
+

Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8

+ +
+
+ +
+
+ + + + +
uint32_t CanTxMsg::ExtId
+
+

Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.

+ +
+
+ +
+
+ + + + +
uint8_t CanTxMsg::IDE
+
+

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN_identifier_type

+ +
+
+ +
+
+ + + + +
uint8_t CanTxMsg::RTR
+
+

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN_remote_transmission_request

+ +
+
+ +
+
+ + + + +
uint32_t CanTxMsg::StdId
+
+

Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_color_signature-members.html b/struct_color_signature-members.html new file mode 100644 index 0000000..2245e5f --- /dev/null +++ b/struct_color_signature-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ColorSignature Member List
+
+
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This is the complete list of members for ColorSignature, including all inherited members.

+ + + + + + + + + + + +
ColorSignature() (defined in ColorSignature)ColorSignatureinline
ColorSignature() (defined in ColorSignature)ColorSignatureinline
m_rgb (defined in ColorSignature)ColorSignature
m_type (defined in ColorSignature)ColorSignature
m_uMax (defined in ColorSignature)ColorSignature
m_uMean (defined in ColorSignature)ColorSignature
m_uMin (defined in ColorSignature)ColorSignature
m_vMax (defined in ColorSignature)ColorSignature
m_vMean (defined in ColorSignature)ColorSignature
m_vMin (defined in ColorSignature)ColorSignature
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_color_signature.html b/struct_color_signature.html new file mode 100644 index 0000000..6d6a3eb --- /dev/null +++ b/struct_color_signature.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: ColorSignature Struct Reference + + + + + + + + + + +
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ColorSignature Struct Reference
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+Public Attributes

+int32_t m_uMin
 
+int32_t m_uMax
 
+int32_t m_uMean
 
+int32_t m_vMin
 
+int32_t m_vMax
 
+int32_t m_vMean
 
+uint32_t m_rgb
 
+uint32_t m_type
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_core_debug___type-members.html b/struct_core_debug___type-members.html new file mode 100644 index 0000000..284def9 --- /dev/null +++ b/struct_core_debug___type-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CoreDebug_Type Member List
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This is the complete list of members for CoreDebug_Type, including all inherited members.

+ + + + + +
DCRDRCoreDebug_Type
DCRSRCoreDebug_Type
DEMCRCoreDebug_Type
DHCSRCoreDebug_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_core_debug___type.html b/struct_core_debug___type.html new file mode 100644 index 0000000..480a6b1 --- /dev/null +++ b/struct_core_debug___type.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: CoreDebug_Type Struct Reference + + + + + + + + + + +
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CoreDebug_Type Struct Reference
Defines and Type Definitions » Core Debug Registers (CoreDebug)
+
+
+ +

Structure type to access the Core Debug Register (CoreDebug). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t DHCSR
 
__O uint32_t DCRSR
 
__IO uint32_t DCRDR
 
__IO uint32_t DEMCR
 
+

Detailed Description

+

Structure type to access the Core Debug Register (CoreDebug).

+

Member Data Documentation

+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DCRDR
+
+

Offset: 0x008 (R/W) Debug Core Register Data Register

+ +
+
+ +
+
+ + + + +
__O uint32_t CoreDebug_Type::DCRSR
+
+

Offset: 0x004 ( /W) Debug Core Register Selector Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DEMCR
+
+

Offset: 0x00C (R/W) Debug Exception and Monitor Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t CoreDebug_Type::DHCSR
+
+

Offset: 0x000 (R/W) Debug Halting Control and Status Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_a_c___init_type_def-members.html b/struct_d_a_c___init_type_def-members.html new file mode 100644 index 0000000..3005f38 --- /dev/null +++ b/struct_d_a_c___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DAC_InitTypeDef Member List
+
+
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This is the complete list of members for DAC_InitTypeDef, including all inherited members.

+ + + + + +
DAC_LFSRUnmask_TriangleAmplitudeDAC_InitTypeDef
DAC_OutputBufferDAC_InitTypeDef
DAC_TriggerDAC_InitTypeDef
DAC_WaveGenerationDAC_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_a_c___init_type_def.html b/struct_d_a_c___init_type_def.html new file mode 100644 index 0000000..63ace9f --- /dev/null +++ b/struct_d_a_c___init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: DAC_InitTypeDef Struct Reference + + + + + + + + + + +
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DAC_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DAC
+
+
+ +

DAC Init structure definition. + More...

+ +

#include <stm32f4xx_dac.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t DAC_Trigger
 
uint32_t DAC_WaveGeneration
 
uint32_t DAC_LFSRUnmask_TriangleAmplitude
 
uint32_t DAC_OutputBuffer
 
+

Detailed Description

+

DAC Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t DAC_InitTypeDef::DAC_LFSRUnmask_TriangleAmplitude
+
+

Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of DAC_lfsrunmask_triangleamplitude

+ +
+
+ +
+
+ + + + +
uint32_t DAC_InitTypeDef::DAC_OutputBuffer
+
+

Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of DAC_output_buffer

+ +
+
+ +
+
+ + + + +
uint32_t DAC_InitTypeDef::DAC_Trigger
+
+

Specifies the external trigger for the selected DAC channel. This parameter can be a value of DAC_trigger_selection

+ +
+
+ +
+
+ + + + +
uint32_t DAC_InitTypeDef::DAC_WaveGeneration
+
+

Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of DAC_wave_generation

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_a_c___type_def-members.html b/struct_d_a_c___type_def-members.html new file mode 100644 index 0000000..641efba --- /dev/null +++ b/struct_d_a_c___type_def-members.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DAC_TypeDef Member List
+
+
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This is the complete list of members for DAC_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + +
CRDAC_TypeDef
DHR12L1DAC_TypeDef
DHR12L2DAC_TypeDef
DHR12LDDAC_TypeDef
DHR12R1DAC_TypeDef
DHR12R2DAC_TypeDef
DHR12RDDAC_TypeDef
DHR8R1DAC_TypeDef
DHR8R2DAC_TypeDef
DHR8RDDAC_TypeDef
DOR1DAC_TypeDef
DOR2DAC_TypeDef
SRDAC_TypeDef
SWTRIGRDAC_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_a_c___type_def.html b/struct_d_a_c___type_def.html new file mode 100644 index 0000000..0e07625 --- /dev/null +++ b/struct_d_a_c___type_def.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: DAC_TypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
+
+
DAC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Digital to Analog Converter. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t SWTRIGR
 
__IO uint32_t DHR12R1
 
__IO uint32_t DHR12L1
 
__IO uint32_t DHR8R1
 
__IO uint32_t DHR12R2
 
__IO uint32_t DHR12L2
 
__IO uint32_t DHR8R2
 
__IO uint32_t DHR12RD
 
__IO uint32_t DHR12LD
 
__IO uint32_t DHR8RD
 
__IO uint32_t DOR1
 
__IO uint32_t DOR2
 
__IO uint32_t SR
 
+

Detailed Description

+

Digital to Analog Converter.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_b_g_m_c_u___type_def-members.html b/struct_d_b_g_m_c_u___type_def-members.html new file mode 100644 index 0000000..33d8b1a --- /dev/null +++ b/struct_d_b_g_m_c_u___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DBGMCU_TypeDef Member List
+
+
+ +

This is the complete list of members for DBGMCU_TypeDef, including all inherited members.

+ + + + + +
APB1FZDBGMCU_TypeDef
APB2FZDBGMCU_TypeDef
CRDBGMCU_TypeDef
IDCODEDBGMCU_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_b_g_m_c_u___type_def.html b/struct_d_b_g_m_c_u___type_def.html new file mode 100644 index 0000000..225e221 --- /dev/null +++ b/struct_d_b_g_m_c_u___type_def.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: DBGMCU_TypeDef Struct Reference + + + + + + + + + + +
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DBGMCU_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Debug MCU. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t IDCODE
 
__IO uint32_t CR
 
__IO uint32_t APB1FZ
 
__IO uint32_t APB2FZ
 
+

Detailed Description

+

Debug MCU.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___c_r_o_p_init_type_def-members.html b/struct_d_c_m_i___c_r_o_p_init_type_def-members.html new file mode 100644 index 0000000..0a31833 --- /dev/null +++ b/struct_d_c_m_i___c_r_o_p_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DCMI_CROPInitTypeDef Member List
+
+
+ +

This is the complete list of members for DCMI_CROPInitTypeDef, including all inherited members.

+ + + + + +
DCMI_CaptureCountDCMI_CROPInitTypeDef
DCMI_HorizontalOffsetCountDCMI_CROPInitTypeDef
DCMI_VerticalLineCountDCMI_CROPInitTypeDef
DCMI_VerticalStartLineDCMI_CROPInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___c_r_o_p_init_type_def.html b/struct_d_c_m_i___c_r_o_p_init_type_def.html new file mode 100644 index 0000000..9672308 --- /dev/null +++ b/struct_d_c_m_i___c_r_o_p_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: DCMI_CROPInitTypeDef Struct Reference + + + + + + + + + + +
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DCMI_CROPInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DCMI
+
+
+ +

DCMI CROP Init structure definition. + More...

+ +

#include <stm32f4xx_dcmi.h>

+ + + + + + + + + + +

+Public Attributes

uint16_t DCMI_VerticalStartLine
 
uint16_t DCMI_HorizontalOffsetCount
 
uint16_t DCMI_VerticalLineCount
 
uint16_t DCMI_CaptureCount
 
+

Detailed Description

+

DCMI CROP Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t DCMI_CROPInitTypeDef::DCMI_CaptureCount
+
+

Specifies the number of pixel clocks to be captured from the starting point on the same line. This parameter can be a value between 0x00 and 0x3FFF

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_CROPInitTypeDef::DCMI_HorizontalOffsetCount
+
+

Specifies the number of pixel clocks to count before starting a capture. This parameter can be a value between 0x00 and 0x3FFF

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_CROPInitTypeDef::DCMI_VerticalLineCount
+
+

Specifies the number of lines to be captured from the starting point. This parameter can be a value between 0x00 and 0x3FFF

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_CROPInitTypeDef::DCMI_VerticalStartLine
+
+

Specifies the Vertical start line count from which the image capture will start. This parameter can be a value between 0x00 and 0x1FFF

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___codes_init_type_def-members.html b/struct_d_c_m_i___codes_init_type_def-members.html new file mode 100644 index 0000000..ff9f6f8 --- /dev/null +++ b/struct_d_c_m_i___codes_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DCMI_CodesInitTypeDef Member List
+
+
+ +

This is the complete list of members for DCMI_CodesInitTypeDef, including all inherited members.

+ + + + + +
DCMI_FrameEndCodeDCMI_CodesInitTypeDef
DCMI_FrameStartCodeDCMI_CodesInitTypeDef
DCMI_LineEndCodeDCMI_CodesInitTypeDef
DCMI_LineStartCodeDCMI_CodesInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___codes_init_type_def.html b/struct_d_c_m_i___codes_init_type_def.html new file mode 100644 index 0000000..962269c --- /dev/null +++ b/struct_d_c_m_i___codes_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: DCMI_CodesInitTypeDef Struct Reference + + + + + + + + + + +
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+
DCMI_CodesInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DCMI
+
+
+ +

DCMI Embedded Synchronisation CODE Init structure definition. + More...

+ +

#include <stm32f4xx_dcmi.h>

+ + + + + + + + + + +

+Public Attributes

uint8_t DCMI_FrameStartCode
 
uint8_t DCMI_LineStartCode
 
uint8_t DCMI_LineEndCode
 
uint8_t DCMI_FrameEndCode
 
+

Detailed Description

+

DCMI Embedded Synchronisation CODE Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t DCMI_CodesInitTypeDef::DCMI_FrameEndCode
+
+

Specifies the code of the frame end delimiter.

+ +
+
+ +
+
+ + + + +
uint8_t DCMI_CodesInitTypeDef::DCMI_FrameStartCode
+
+

Specifies the code of the frame start delimiter.

+ +
+
+ +
+
+ + + + +
uint8_t DCMI_CodesInitTypeDef::DCMI_LineEndCode
+
+

Specifies the code of the line end delimiter.

+ +
+
+ +
+
+ + + + +
uint8_t DCMI_CodesInitTypeDef::DCMI_LineStartCode
+
+

Specifies the code of the line start delimiter.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___init_type_def-members.html b/struct_d_c_m_i___init_type_def-members.html new file mode 100644 index 0000000..9111f9a --- /dev/null +++ b/struct_d_c_m_i___init_type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
+
DCMI_InitTypeDef Member List
+
+
+ +

This is the complete list of members for DCMI_InitTypeDef, including all inherited members.

+ + + + + + + + +
DCMI_CaptureModeDCMI_InitTypeDef
DCMI_CaptureRateDCMI_InitTypeDef
DCMI_ExtendedDataModeDCMI_InitTypeDef
DCMI_HSPolarityDCMI_InitTypeDef
DCMI_PCKPolarityDCMI_InitTypeDef
DCMI_SynchroModeDCMI_InitTypeDef
DCMI_VSPolarityDCMI_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___init_type_def.html b/struct_d_c_m_i___init_type_def.html new file mode 100644 index 0000000..33935e7 --- /dev/null +++ b/struct_d_c_m_i___init_type_def.html @@ -0,0 +1,222 @@ + + + + + + +discoverpixy: DCMI_InitTypeDef Struct Reference + + + + + + + + + + +
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DCMI_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DCMI
+
+
+ +

DCMI Init structure definition. + More...

+ +

#include <stm32f4xx_dcmi.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t DCMI_CaptureMode
 
uint16_t DCMI_SynchroMode
 
uint16_t DCMI_PCKPolarity
 
uint16_t DCMI_VSPolarity
 
uint16_t DCMI_HSPolarity
 
uint16_t DCMI_CaptureRate
 
uint16_t DCMI_ExtendedDataMode
 
+

Detailed Description

+

DCMI Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_CaptureMode
+
+

Specifies the Capture Mode: Continuous or Snapshot. This parameter can be a value of DCMI_Capture_Mode

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_CaptureRate
+
+

Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of DCMI_Capture_Rate

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_ExtendedDataMode
+
+

Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of DCMI_Extended_Data_Mode

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_HSPolarity
+
+

Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of DCMI_HSYNC_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_PCKPolarity
+
+

Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of DCMI_PIXCK_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_SynchroMode
+
+

Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of DCMI_Synchronization_Mode

+ +
+
+ +
+
+ + + + +
uint16_t DCMI_InitTypeDef::DCMI_VSPolarity
+
+

Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of DCMI_VSYNC_Polarity

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___type_def-members.html b/struct_d_c_m_i___type_def-members.html new file mode 100644 index 0000000..b662bf9 --- /dev/null +++ b/struct_d_c_m_i___type_def-members.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DCMI_TypeDef Member List
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This is the complete list of members for DCMI_TypeDef, including all inherited members.

+ + + + + + + + + + + + +
CRDCMI_TypeDef
CWSIZERDCMI_TypeDef
CWSTRTRDCMI_TypeDef
DRDCMI_TypeDef
ESCRDCMI_TypeDef
ESURDCMI_TypeDef
ICRDCMI_TypeDef
IERDCMI_TypeDef
MISRDCMI_TypeDef
RISRDCMI_TypeDef
SRDCMI_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_c_m_i___type_def.html b/struct_d_c_m_i___type_def.html new file mode 100644 index 0000000..7dc7a48 --- /dev/null +++ b/struct_d_c_m_i___type_def.html @@ -0,0 +1,138 @@ + + + + + + +discoverpixy: DCMI_TypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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DCMI_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

DCMI. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t RISR
 
__IO uint32_t IER
 
__IO uint32_t MISR
 
__IO uint32_t ICR
 
__IO uint32_t ESCR
 
__IO uint32_t ESUR
 
__IO uint32_t CWSTRTR
 
__IO uint32_t CWSIZER
 
__IO uint32_t DR
 
+

Detailed Description

+

DCMI.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t-members.html b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..5db109f --- /dev/null +++ b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DIRECTORY_STRUCT Member List
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This is the complete list of members for DIRECTORY_STRUCT, including all inherited members.

+ + + + +
files (defined in DIRECTORY_STRUCT)DIRECTORY_STRUCT
num_files (defined in DIRECTORY_STRUCT)DIRECTORY_STRUCT
path (defined in DIRECTORY_STRUCT)DIRECTORY_STRUCT
+ +
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+ + diff --git a/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t.html b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t.html new file mode 100644 index 0000000..52f2978 --- /dev/null +++ b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t.html @@ -0,0 +1,158 @@ + + + + + + +discoverpixy: DIRECTORY_STRUCT Struct Reference + + + + + + + + + + +
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+Data Fields
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DIRECTORY_STRUCT Struct Reference
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#include <filesystem.h>

+
+Collaboration diagram for DIRECTORY_STRUCT:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + +

+Data Fields

const char * path
 
uint16_t num_files
 
FILE_STRUCT * files
 
+

Field Documentation

+ +
+
+ + + + +
FILE_STRUCT* files
+
+ +
+
+ +
+
+ + + + +
uint16_t num_files
+
+ +
+
+ +
+
+ + + + +
const char* path
+
+ +
+
+
The documentation for this struct was generated from the following file: +
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.map b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.map new file mode 100644 index 0000000..7b5800a --- /dev/null +++ b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.md5 b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.md5 new file mode 100644 index 0000000..bd55800 --- /dev/null +++ b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.md5 @@ -0,0 +1 @@ +5ab8596ea46aa92ed89e65bb121cf88c \ No newline at end of file diff --git a/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.png b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.png new file mode 100644 index 0000000..ed64cae Binary files /dev/null and b/struct_d_i_r_e_c_t_o_r_y___s_t_r_u_c_t__coll__graph.png differ diff --git a/struct_d_m_a2_d___b_g___init_type_def-members.html b/struct_d_m_a2_d___b_g___init_type_def-members.html new file mode 100644 index 0000000..13439a7 --- /dev/null +++ b/struct_d_m_a2_d___b_g___init_type_def-members.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA2D_BG_InitTypeDef Member List
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+ +

This is the complete list of members for DMA2D_BG_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + +
DMA2D_BG_CLUT_CMDMA2D_BG_InitTypeDef
DMA2D_BG_CLUT_SIZEDMA2D_BG_InitTypeDef
DMA2D_BGC_BLUEDMA2D_BG_InitTypeDef
DMA2D_BGC_GREENDMA2D_BG_InitTypeDef
DMA2D_BGC_REDDMA2D_BG_InitTypeDef
DMA2D_BGCMDMA2D_BG_InitTypeDef
DMA2D_BGCMARDMA2D_BG_InitTypeDef
DMA2D_BGMADMA2D_BG_InitTypeDef
DMA2D_BGODMA2D_BG_InitTypeDef
DMA2D_BGPFC_ALPHA_MODEDMA2D_BG_InitTypeDef
DMA2D_BGPFC_ALPHA_VALUEDMA2D_BG_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a2_d___b_g___init_type_def.html b/struct_d_m_a2_d___b_g___init_type_def.html new file mode 100644 index 0000000..1d75c0c --- /dev/null +++ b/struct_d_m_a2_d___b_g___init_type_def.html @@ -0,0 +1,275 @@ + + + + + + +discoverpixy: DMA2D_BG_InitTypeDef Struct Reference + + + + + + + + + + +
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DMA2D_BG_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DMA2D
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t DMA2D_BGMA
 
uint32_t DMA2D_BGO
 
uint32_t DMA2D_BGCM
 
uint32_t DMA2D_BG_CLUT_CM
 
uint32_t DMA2D_BG_CLUT_SIZE
 
uint32_t DMA2D_BGPFC_ALPHA_MODE
 
uint32_t DMA2D_BGPFC_ALPHA_VALUE
 
uint32_t DMA2D_BGC_BLUE
 
uint32_t DMA2D_BGC_GREEN
 
uint32_t DMA2D_BGC_RED
 
uint32_t DMA2D_BGCMAR
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BG_CLUT_CM
+
+

configures the DMA2D background CLUT color mode. This parameter can be one value of DMA2D_FG_CLUT_CM

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BG_CLUT_SIZE
+
+

configures the DMA2D background CLUT size. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGC_BLUE
+
+

Specifies the DMA2D background blue value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGC_GREEN
+
+

Specifies the DMA2D background green value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGC_RED
+
+

Specifies the DMA2D background red value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGCM
+
+

configures the DMA2D background color mode . This parameter can be one value of DMA2D_FGCM

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGCMAR
+
+

Configures the DMA2D background CLUT memory address. This parameter must range from 0x00000000 to 0xFFFFFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGMA
+
+

configures the DMA2D background memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGO
+
+

configures the DMA2D background offset. This parameter must be range from 0x0000 to 0x3FFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGPFC_ALPHA_MODE
+
+

configures the DMA2D background alpha mode. This parameter can be one value of DMA2D_FGPFC_ALPHA_MODE

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_BG_InitTypeDef::DMA2D_BGPFC_ALPHA_VALUE
+
+

Specifies the DMA2D background alpha value must be range from 0x00 to 0xFF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_d_m_a2_d___f_g___init_type_def-members.html b/struct_d_m_a2_d___f_g___init_type_def-members.html new file mode 100644 index 0000000..5d5e358 --- /dev/null +++ b/struct_d_m_a2_d___f_g___init_type_def-members.html @@ -0,0 +1,113 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA2D_FG_InitTypeDef Member List
+
+
+ +

This is the complete list of members for DMA2D_FG_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + +
DMA2D_FG_CLUT_CMDMA2D_FG_InitTypeDef
DMA2D_FG_CLUT_SIZEDMA2D_FG_InitTypeDef
DMA2D_FGC_BLUEDMA2D_FG_InitTypeDef
DMA2D_FGC_GREENDMA2D_FG_InitTypeDef
DMA2D_FGC_REDDMA2D_FG_InitTypeDef
DMA2D_FGCMDMA2D_FG_InitTypeDef
DMA2D_FGCMARDMA2D_FG_InitTypeDef
DMA2D_FGMADMA2D_FG_InitTypeDef
DMA2D_FGODMA2D_FG_InitTypeDef
DMA2D_FGPFC_ALPHA_MODEDMA2D_FG_InitTypeDef
DMA2D_FGPFC_ALPHA_VALUEDMA2D_FG_InitTypeDef
+ +
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+ + diff --git a/struct_d_m_a2_d___f_g___init_type_def.html b/struct_d_m_a2_d___f_g___init_type_def.html new file mode 100644 index 0000000..723d998 --- /dev/null +++ b/struct_d_m_a2_d___f_g___init_type_def.html @@ -0,0 +1,275 @@ + + + + + + +discoverpixy: DMA2D_FG_InitTypeDef Struct Reference + + + + + + + + + + +
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+
DMA2D_FG_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DMA2D
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t DMA2D_FGMA
 
uint32_t DMA2D_FGO
 
uint32_t DMA2D_FGCM
 
uint32_t DMA2D_FG_CLUT_CM
 
uint32_t DMA2D_FG_CLUT_SIZE
 
uint32_t DMA2D_FGPFC_ALPHA_MODE
 
uint32_t DMA2D_FGPFC_ALPHA_VALUE
 
uint32_t DMA2D_FGC_BLUE
 
uint32_t DMA2D_FGC_GREEN
 
uint32_t DMA2D_FGC_RED
 
uint32_t DMA2D_FGCMAR
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FG_CLUT_CM
+
+

configures the DMA2D foreground CLUT color mode. This parameter can be one value of DMA2D_FG_CLUT_CM

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FG_CLUT_SIZE
+
+

configures the DMA2D foreground CLUT size. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGC_BLUE
+
+

Specifies the DMA2D foreground blue value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGC_GREEN
+
+

Specifies the DMA2D foreground green value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGC_RED
+
+

Specifies the DMA2D foreground red value must be range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGCM
+
+

configures the DMA2D foreground color mode . This parameter can be one value of DMA2D_FGCM

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGCMAR
+
+

Configures the DMA2D foreground CLUT memory address. This parameter must range from 0x00000000 to 0xFFFFFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGMA
+
+

configures the DMA2D foreground memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGO
+
+

configures the DMA2D foreground offset. This parameter must be range from 0x0000 to 0x3FFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGPFC_ALPHA_MODE
+
+

configures the DMA2D foreground alpha mode. This parameter can be one value of DMA2D_FGPFC_ALPHA_MODE

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_FG_InitTypeDef::DMA2D_FGPFC_ALPHA_VALUE
+
+

Specifies the DMA2D foreground alpha value must be range from 0x00 to 0xFF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a2_d___init_type_def-members.html b/struct_d_m_a2_d___init_type_def-members.html new file mode 100644 index 0000000..0c27ead --- /dev/null +++ b/struct_d_m_a2_d___init_type_def-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA2D_InitTypeDef Member List
+
+
+ +

This is the complete list of members for DMA2D_InitTypeDef, including all inherited members.

+ + + + + + + + + + + +
DMA2D_CModeDMA2D_InitTypeDef
DMA2D_ModeDMA2D_InitTypeDef
DMA2D_NumberOfLineDMA2D_InitTypeDef
DMA2D_OutputAlphaDMA2D_InitTypeDef
DMA2D_OutputBlueDMA2D_InitTypeDef
DMA2D_OutputGreenDMA2D_InitTypeDef
DMA2D_OutputMemoryAddDMA2D_InitTypeDef
DMA2D_OutputOffsetDMA2D_InitTypeDef
DMA2D_OutputRedDMA2D_InitTypeDef
DMA2D_PixelPerLineDMA2D_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a2_d___init_type_def.html b/struct_d_m_a2_d___init_type_def.html new file mode 100644 index 0000000..4d9b0ca --- /dev/null +++ b/struct_d_m_a2_d___init_type_def.html @@ -0,0 +1,289 @@ + + + + + + +discoverpixy: DMA2D_InitTypeDef Struct Reference + + + + + + + + + + +
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DMA2D_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DMA2D
+
+
+ +

DMA2D Init structure definition. + More...

+ +

#include <stm32f4xx_dma2d.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t DMA2D_Mode
 
uint32_t DMA2D_CMode
 
uint32_t DMA2D_OutputBlue
 
uint32_t DMA2D_OutputGreen
 
uint32_t DMA2D_OutputRed
 
uint32_t DMA2D_OutputAlpha
 
uint32_t DMA2D_OutputMemoryAdd
 
uint32_t DMA2D_OutputOffset
 
uint32_t DMA2D_NumberOfLine
 
uint32_t DMA2D_PixelPerLine
 
+

Detailed Description

+

DMA2D Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_CMode
+
+

configures the color format of the output image. This parameter can be one value of DMA2D_CMODE

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_Mode
+
+

configures the DMA2D transfer mode. This parameter can be one value of DMA2D_MODE

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_NumberOfLine
+
+

Configures the number of line of the area to be transfered. This parameter must range from 0x0000 to 0xFFFF

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputAlpha
+
+

configures the alpha channel of the output color. This parameter must range:

    +
  • from 0x00 to 0xFF if ARGB8888 color mode is slected
    • +
  • from 0x00 to 0x01 if ARGB1555 color mode is slected
    • +
  • from 0x00 to 0x0F if ARGB4444 color mode is slected
    • +
+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputBlue
+
+

configures the blue value of the output image. This parameter must range:

    +
  • from 0x00 to 0xFF if ARGB8888 color mode is slected
    • +
  • from 0x00 to 0xFF if RGB888 color mode is slected
    • +
  • from 0x00 to 0x1F if RGB565 color mode is slected
    • +
  • from 0x00 to 0x1F if ARGB1555 color mode is slected
    • +
  • from 0x00 to 0x0F if ARGB4444 color mode is slected
    • +
+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputGreen
+
+

configures the green value of the output image. This parameter must range:

    +
  • from 0x00 to 0xFF if ARGB8888 color mode is slected
    • +
  • from 0x00 to 0xFF if RGB888 color mode is slected
    • +
  • from 0x00 to 0x2F if RGB565 color mode is slected
    • +
  • from 0x00 to 0x1F if ARGB1555 color mode is slected
    • +
  • from 0x00 to 0x0F if ARGB4444 color mode is slected
    • +
+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputMemoryAdd
+
+

Specifies the memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputOffset
+
+

Specifies the Offset value. This parameter must be range from 0x0000 to 0x3FFF.

+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_OutputRed
+
+

configures the red value of the output image. This parameter must range:

    +
  • from 0x00 to 0xFF if ARGB8888 color mode is slected
    • +
  • from 0x00 to 0xFF if RGB888 color mode is slected
    • +
  • from 0x00 to 0x1F if RGB565 color mode is slected
    • +
  • from 0x00 to 0x1F if ARGB1555 color mode is slected
    • +
  • from 0x00 to 0x0F if ARGB4444 color mode is slected
    • +
+ +
+
+ +
+
+ + + + +
uint32_t DMA2D_InitTypeDef::DMA2D_PixelPerLine
+
+

Configures the number pixel per line of the area to be transfered. This parameter must range from 0x0000 to 0x3FFF

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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DMA2D_TypeDef Member List
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This is the complete list of members for DMA2D_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + +
AMTCRDMA2D_TypeDef
BGCLUTDMA2D_TypeDef
BGCMARDMA2D_TypeDef
BGCOLRDMA2D_TypeDef
BGMARDMA2D_TypeDef
BGORDMA2D_TypeDef
BGPFCCRDMA2D_TypeDef
CRDMA2D_TypeDef
FGCLUTDMA2D_TypeDef
FGCMARDMA2D_TypeDef
FGCOLRDMA2D_TypeDef
FGMARDMA2D_TypeDef
FGORDMA2D_TypeDef
FGPFCCRDMA2D_TypeDef
IFCRDMA2D_TypeDef
ISRDMA2D_TypeDef
LWRDMA2D_TypeDef
NLRDMA2D_TypeDef
OCOLRDMA2D_TypeDef
OMARDMA2D_TypeDef
OORDMA2D_TypeDef
OPFCCRDMA2D_TypeDef
RESERVEDDMA2D_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a2_d___type_def.html b/struct_d_m_a2_d___type_def.html new file mode 100644 index 0000000..30334c2 --- /dev/null +++ b/struct_d_m_a2_d___type_def.html @@ -0,0 +1,162 @@ + + + + + + +discoverpixy: DMA2D_TypeDef Struct Reference + + + + + + + + + + +
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DMA2D_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

DMA2D Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t ISR
 
__IO uint32_t IFCR
 
__IO uint32_t FGMAR
 
__IO uint32_t FGOR
 
__IO uint32_t BGMAR
 
__IO uint32_t BGOR
 
__IO uint32_t FGPFCCR
 
__IO uint32_t FGCOLR
 
__IO uint32_t BGPFCCR
 
__IO uint32_t BGCOLR
 
__IO uint32_t FGCMAR
 
__IO uint32_t BGCMAR
 
__IO uint32_t OPFCCR
 
__IO uint32_t OCOLR
 
__IO uint32_t OMAR
 
__IO uint32_t OOR
 
__IO uint32_t NLR
 
__IO uint32_t LWR
 
__IO uint32_t AMTCR
 
uint32_t RESERVED [236]
 
__IO uint32_t FGCLUT [256]
 
__IO uint32_t BGCLUT [256]
 
+

Detailed Description

+

DMA2D Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___init_type_def-members.html b/struct_d_m_a___init_type_def-members.html new file mode 100644 index 0000000..6b27423 --- /dev/null +++ b/struct_d_m_a___init_type_def-members.html @@ -0,0 +1,117 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA_InitTypeDef Member List
+
+
+ +

This is the complete list of members for DMA_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + +
DMA_BufferSizeDMA_InitTypeDef
DMA_ChannelDMA_InitTypeDef
DMA_DIRDMA_InitTypeDef
DMA_FIFOModeDMA_InitTypeDef
DMA_FIFOThresholdDMA_InitTypeDef
DMA_Memory0BaseAddrDMA_InitTypeDef
DMA_MemoryBurstDMA_InitTypeDef
DMA_MemoryDataSizeDMA_InitTypeDef
DMA_MemoryIncDMA_InitTypeDef
DMA_ModeDMA_InitTypeDef
DMA_PeripheralBaseAddrDMA_InitTypeDef
DMA_PeripheralBurstDMA_InitTypeDef
DMA_PeripheralDataSizeDMA_InitTypeDef
DMA_PeripheralIncDMA_InitTypeDef
DMA_PriorityDMA_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___init_type_def.html b/struct_d_m_a___init_type_def.html new file mode 100644 index 0000000..c6a8f98 --- /dev/null +++ b/struct_d_m_a___init_type_def.html @@ -0,0 +1,342 @@ + + + + + + +discoverpixy: DMA_InitTypeDef Struct Reference + + + + + + + + + + +
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DMA_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » DMA
+
+
+ +

DMA Init structure definition. + More...

+ +

#include <stm32f4xx_dma.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t DMA_Channel
 
uint32_t DMA_PeripheralBaseAddr
 
uint32_t DMA_Memory0BaseAddr
 
uint32_t DMA_DIR
 
uint32_t DMA_BufferSize
 
uint32_t DMA_PeripheralInc
 
uint32_t DMA_MemoryInc
 
uint32_t DMA_PeripheralDataSize
 
uint32_t DMA_MemoryDataSize
 
uint32_t DMA_Mode
 
uint32_t DMA_Priority
 
uint32_t DMA_FIFOMode
 
uint32_t DMA_FIFOThreshold
 
uint32_t DMA_MemoryBurst
 
uint32_t DMA_PeripheralBurst
 
+

Detailed Description

+

DMA Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_BufferSize
+
+

Specifies the buffer size, in data unit, of the specified Stream. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction.

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_Channel
+
+

Specifies the channel used for the specified stream. This parameter can be a value of DMA_channel

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_DIR
+
+

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA_data_transfer_direction

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_FIFOMode
+
+

Specifies if the FIFO mode or Direct mode will be used for the specified Stream. This parameter can be a value of DMA_fifo_direct_mode

Note
The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected Stream
+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_FIFOThreshold
+
+

Specifies the FIFO threshold level. This parameter can be a value of DMA_fifo_threshold_level

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_Memory0BaseAddr
+
+

Specifies the memory 0 base address for DMAy Streamx. This memory is the default memory used when double buffer mode is not enabled.

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_MemoryBurst
+
+

Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of DMA_memory_burst

Note
The burst mode is possible only if the address Increment mode is enabled.
+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_MemoryDataSize
+
+

Specifies the Memory data width. This parameter can be a value of DMA_memory_data_size

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_MemoryInc
+
+

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA_memory_incremented_mode

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_Mode
+
+

Specifies the operation mode of the DMAy Streamx. This parameter can be a value of DMA_circular_normal_mode

Note
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream
+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_PeripheralBaseAddr
+
+

Specifies the peripheral base address for DMAy Streamx.

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_PeripheralBurst
+
+

Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of DMA_peripheral_burst

Note
The burst mode is possible only if the address Increment mode is enabled.
+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_PeripheralDataSize
+
+

Specifies the Peripheral data width. This parameter can be a value of DMA_peripheral_data_size

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_PeripheralInc
+
+

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA_peripheral_incremented_mode

+ +
+
+ +
+
+ + + + +
uint32_t DMA_InitTypeDef::DMA_Priority
+
+

Specifies the software priority for the DMAy Streamx. This parameter can be a value of DMA_priority_level

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___stream___type_def-members.html b/struct_d_m_a___stream___type_def-members.html new file mode 100644 index 0000000..3882f4d --- /dev/null +++ b/struct_d_m_a___stream___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA_Stream_TypeDef Member List
+
+
+ +

This is the complete list of members for DMA_Stream_TypeDef, including all inherited members.

+ + + + + + + +
CRDMA_Stream_TypeDef
FCRDMA_Stream_TypeDef
M0ARDMA_Stream_TypeDef
M1ARDMA_Stream_TypeDef
NDTRDMA_Stream_TypeDef
PARDMA_Stream_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___stream___type_def.html b/struct_d_m_a___stream___type_def.html new file mode 100644 index 0000000..72c584b --- /dev/null +++ b/struct_d_m_a___stream___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: DMA_Stream_TypeDef Struct Reference + + + + + + + + + + +
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DMA_Stream_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

DMA Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t NDTR
 
__IO uint32_t PAR
 
__IO uint32_t M0AR
 
__IO uint32_t M1AR
 
__IO uint32_t FCR
 
+

Detailed Description

+

DMA Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___type_def-members.html b/struct_d_m_a___type_def-members.html new file mode 100644 index 0000000..99840fb --- /dev/null +++ b/struct_d_m_a___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DMA_TypeDef Member List
+
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This is the complete list of members for DMA_TypeDef, including all inherited members.

+ + + + + +
HIFCRDMA_TypeDef
HISRDMA_TypeDef
LIFCRDMA_TypeDef
LISRDMA_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_d_m_a___type_def.html b/struct_d_m_a___type_def.html new file mode 100644 index 0000000..d7b0c1a --- /dev/null +++ b/struct_d_m_a___type_def.html @@ -0,0 +1,117 @@ + + + + + + +discoverpixy: DMA_TypeDef Struct Reference + + + + + + + + + + +
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DMA_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ + + + + + + + + + +

+Public Attributes

__IO uint32_t LISR
 
__IO uint32_t HISR
 
__IO uint32_t LIFCR
 
__IO uint32_t HIFCR
 
+
The documentation for this struct was generated from the following file: +
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+ + diff --git a/struct_d_w_t___type-members.html b/struct_d_w_t___type-members.html new file mode 100644 index 0000000..7904429 --- /dev/null +++ b/struct_d_w_t___type-members.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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DWT_Type Member List
+
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This is the complete list of members for DWT_Type, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + +
COMP0DWT_Type
COMP1DWT_Type
COMP2DWT_Type
COMP3DWT_Type
CPICNTDWT_Type
CTRLDWT_Type
CYCCNTDWT_Type
EXCCNTDWT_Type
FOLDCNTDWT_Type
FUNCTION0DWT_Type
FUNCTION1DWT_Type
FUNCTION2DWT_Type
FUNCTION3DWT_Type
LSUCNTDWT_Type
MASK0DWT_Type
MASK1DWT_Type
MASK2DWT_Type
MASK3DWT_Type
PCSRDWT_Type
RESERVED0 (defined in DWT_Type)DWT_Type
RESERVED1 (defined in DWT_Type)DWT_Type
RESERVED2 (defined in DWT_Type)DWT_Type
SLEEPCNTDWT_Type
+ +
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DWT_Type Struct Reference
Defines and Type Definitions » Data Watchpoint and Trace (DWT)
+
+
+ +

Structure type to access the Data Watchpoint and Trace Register (DWT). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CTRL
 
__IO uint32_t CYCCNT
 
__IO uint32_t CPICNT
 
__IO uint32_t EXCCNT
 
__IO uint32_t SLEEPCNT
 
__IO uint32_t LSUCNT
 
__IO uint32_t FOLDCNT
 
__I uint32_t PCSR
 
__IO uint32_t COMP0
 
__IO uint32_t MASK0
 
__IO uint32_t FUNCTION0
 
+uint32_t RESERVED0 [1]
 
__IO uint32_t COMP1
 
__IO uint32_t MASK1
 
__IO uint32_t FUNCTION1
 
+uint32_t RESERVED1 [1]
 
__IO uint32_t COMP2
 
__IO uint32_t MASK2
 
__IO uint32_t FUNCTION2
 
+uint32_t RESERVED2 [1]
 
__IO uint32_t COMP3
 
__IO uint32_t MASK3
 
__IO uint32_t FUNCTION3
 
+

Detailed Description

+

Structure type to access the Data Watchpoint and Trace Register (DWT).

+

Member Data Documentation

+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP0
+
+

Offset: 0x020 (R/W) Comparator Register 0

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP1
+
+

Offset: 0x030 (R/W) Comparator Register 1

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP2
+
+

Offset: 0x040 (R/W) Comparator Register 2

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::COMP3
+
+

Offset: 0x050 (R/W) Comparator Register 3

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CPICNT
+
+

Offset: 0x008 (R/W) CPI Count Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CTRL
+
+

Offset: 0x000 (R/W) Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::CYCCNT
+
+

Offset: 0x004 (R/W) Cycle Count Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::EXCCNT
+
+

Offset: 0x00C (R/W) Exception Overhead Count Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FOLDCNT
+
+

Offset: 0x018 (R/W) Folded-instruction Count Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION0
+
+

Offset: 0x028 (R/W) Function Register 0

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION1
+
+

Offset: 0x038 (R/W) Function Register 1

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION2
+
+

Offset: 0x048 (R/W) Function Register 2

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::FUNCTION3
+
+

Offset: 0x058 (R/W) Function Register 3

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::LSUCNT
+
+

Offset: 0x014 (R/W) LSU Count Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK0
+
+

Offset: 0x024 (R/W) Mask Register 0

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK1
+
+

Offset: 0x034 (R/W) Mask Register 1

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK2
+
+

Offset: 0x044 (R/W) Mask Register 2

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::MASK3
+
+

Offset: 0x054 (R/W) Mask Register 3

+ +
+
+ +
+
+ + + + +
__I uint32_t DWT_Type::PCSR
+
+

Offset: 0x01C (R/ ) Program Counter Sample Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t DWT_Type::SLEEPCNT
+
+

Offset: 0x010 (R/W) Sleep Count Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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ETH_TypeDef Member List
+
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This is the complete list of members for ETH_TypeDef, including all inherited members.

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DMABMR (defined in ETH_TypeDef)ETH_TypeDef
DMACHRBAR (defined in ETH_TypeDef)ETH_TypeDef
DMACHRDR (defined in ETH_TypeDef)ETH_TypeDef
DMACHTBAR (defined in ETH_TypeDef)ETH_TypeDef
DMACHTDR (defined in ETH_TypeDef)ETH_TypeDef
DMAIER (defined in ETH_TypeDef)ETH_TypeDef
DMAMFBOCR (defined in ETH_TypeDef)ETH_TypeDef
DMAOMR (defined in ETH_TypeDef)ETH_TypeDef
DMARDLAR (defined in ETH_TypeDef)ETH_TypeDef
DMARPDR (defined in ETH_TypeDef)ETH_TypeDef
DMARSWTR (defined in ETH_TypeDef)ETH_TypeDef
DMASR (defined in ETH_TypeDef)ETH_TypeDef
DMATDLAR (defined in ETH_TypeDef)ETH_TypeDef
DMATPDR (defined in ETH_TypeDef)ETH_TypeDef
MACA0HR (defined in ETH_TypeDef)ETH_TypeDef
MACA0LR (defined in ETH_TypeDef)ETH_TypeDef
MACA1HR (defined in ETH_TypeDef)ETH_TypeDef
MACA1LR (defined in ETH_TypeDef)ETH_TypeDef
MACA2HR (defined in ETH_TypeDef)ETH_TypeDef
MACA2LR (defined in ETH_TypeDef)ETH_TypeDef
MACA3HR (defined in ETH_TypeDef)ETH_TypeDef
MACA3LR (defined in ETH_TypeDef)ETH_TypeDef
MACCR (defined in ETH_TypeDef)ETH_TypeDef
MACFCR (defined in ETH_TypeDef)ETH_TypeDef
MACFFR (defined in ETH_TypeDef)ETH_TypeDef
MACHTHR (defined in ETH_TypeDef)ETH_TypeDef
MACHTLR (defined in ETH_TypeDef)ETH_TypeDef
MACIMR (defined in ETH_TypeDef)ETH_TypeDef
MACMIIAR (defined in ETH_TypeDef)ETH_TypeDef
MACMIIDR (defined in ETH_TypeDef)ETH_TypeDef
MACPMTCSR (defined in ETH_TypeDef)ETH_TypeDef
MACRWUFFR (defined in ETH_TypeDef)ETH_TypeDef
MACSR (defined in ETH_TypeDef)ETH_TypeDef
MACVLANTR (defined in ETH_TypeDef)ETH_TypeDef
MMCCR (defined in ETH_TypeDef)ETH_TypeDef
MMCRFAECR (defined in ETH_TypeDef)ETH_TypeDef
MMCRFCECR (defined in ETH_TypeDef)ETH_TypeDef
MMCRGUFCR (defined in ETH_TypeDef)ETH_TypeDef
MMCRIMR (defined in ETH_TypeDef)ETH_TypeDef
MMCRIR (defined in ETH_TypeDef)ETH_TypeDef
MMCTGFCR (defined in ETH_TypeDef)ETH_TypeDef
MMCTGFMSCCR (defined in ETH_TypeDef)ETH_TypeDef
MMCTGFSCCR (defined in ETH_TypeDef)ETH_TypeDef
MMCTIMR (defined in ETH_TypeDef)ETH_TypeDef
MMCTIR (defined in ETH_TypeDef)ETH_TypeDef
PTPSSIR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSAR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSCR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSHR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSHUR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSLR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSLUR (defined in ETH_TypeDef)ETH_TypeDef
PTPTSSR (defined in ETH_TypeDef)ETH_TypeDef
PTPTTHR (defined in ETH_TypeDef)ETH_TypeDef
PTPTTLR (defined in ETH_TypeDef)ETH_TypeDef
RESERVED0 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED1 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED10 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED2 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED3 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED4 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED5 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED6 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED7 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED8 (defined in ETH_TypeDef)ETH_TypeDef
RESERVED9 (defined in ETH_TypeDef)ETH_TypeDef
+ +
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+ + diff --git a/struct_e_t_h___type_def.html b/struct_e_t_h___type_def.html new file mode 100644 index 0000000..5db3973 --- /dev/null +++ b/struct_e_t_h___type_def.html @@ -0,0 +1,314 @@ + + + + + + +discoverpixy: ETH_TypeDef Struct Reference + + + + + + + + + + +
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ETH_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Ethernet MAC. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+__IO uint32_t MACCR
 
+__IO uint32_t MACFFR
 
+__IO uint32_t MACHTHR
 
+__IO uint32_t MACHTLR
 
+__IO uint32_t MACMIIAR
 
+__IO uint32_t MACMIIDR
 
+__IO uint32_t MACFCR
 
+__IO uint32_t MACVLANTR
 
+uint32_t RESERVED0 [2]
 
+__IO uint32_t MACRWUFFR
 
+__IO uint32_t MACPMTCSR
 
+uint32_t RESERVED1 [2]
 
+__IO uint32_t MACSR
 
+__IO uint32_t MACIMR
 
+__IO uint32_t MACA0HR
 
+__IO uint32_t MACA0LR
 
+__IO uint32_t MACA1HR
 
+__IO uint32_t MACA1LR
 
+__IO uint32_t MACA2HR
 
+__IO uint32_t MACA2LR
 
+__IO uint32_t MACA3HR
 
+__IO uint32_t MACA3LR
 
+uint32_t RESERVED2 [40]
 
+__IO uint32_t MMCCR
 
+__IO uint32_t MMCRIR
 
+__IO uint32_t MMCTIR
 
+__IO uint32_t MMCRIMR
 
+__IO uint32_t MMCTIMR
 
+uint32_t RESERVED3 [14]
 
+__IO uint32_t MMCTGFSCCR
 
+__IO uint32_t MMCTGFMSCCR
 
+uint32_t RESERVED4 [5]
 
+__IO uint32_t MMCTGFCR
 
+uint32_t RESERVED5 [10]
 
+__IO uint32_t MMCRFCECR
 
+__IO uint32_t MMCRFAECR
 
+uint32_t RESERVED6 [10]
 
+__IO uint32_t MMCRGUFCR
 
+uint32_t RESERVED7 [334]
 
+__IO uint32_t PTPTSCR
 
+__IO uint32_t PTPSSIR
 
+__IO uint32_t PTPTSHR
 
+__IO uint32_t PTPTSLR
 
+__IO uint32_t PTPTSHUR
 
+__IO uint32_t PTPTSLUR
 
+__IO uint32_t PTPTSAR
 
+__IO uint32_t PTPTTHR
 
+__IO uint32_t PTPTTLR
 
+__IO uint32_t RESERVED8
 
+__IO uint32_t PTPTSSR
 
+uint32_t RESERVED9 [565]
 
+__IO uint32_t DMABMR
 
+__IO uint32_t DMATPDR
 
+__IO uint32_t DMARPDR
 
+__IO uint32_t DMARDLAR
 
+__IO uint32_t DMATDLAR
 
+__IO uint32_t DMASR
 
+__IO uint32_t DMAOMR
 
+__IO uint32_t DMAIER
 
+__IO uint32_t DMAMFBOCR
 
+__IO uint32_t DMARSWTR
 
+uint32_t RESERVED10 [8]
 
+__IO uint32_t DMACHTDR
 
+__IO uint32_t DMACHRDR
 
+__IO uint32_t DMACHTBAR
 
+__IO uint32_t DMACHRBAR
 
+

Detailed Description

+

Ethernet MAC.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_e_x_t_i___init_type_def-members.html b/struct_e_x_t_i___init_type_def-members.html new file mode 100644 index 0000000..180221a --- /dev/null +++ b/struct_e_x_t_i___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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EXTI_InitTypeDef Member List
+
+
+ +

This is the complete list of members for EXTI_InitTypeDef, including all inherited members.

+ + + + + +
EXTI_LineEXTI_InitTypeDef
EXTI_LineCmdEXTI_InitTypeDef
EXTI_ModeEXTI_InitTypeDef
EXTI_TriggerEXTI_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_e_x_t_i___init_type_def.html b/struct_e_x_t_i___init_type_def.html new file mode 100644 index 0000000..d30fa82 --- /dev/null +++ b/struct_e_x_t_i___init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: EXTI_InitTypeDef Struct Reference + + + + + + + + + + +
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EXTI_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » EXTI
+
+
+ +

EXTI Init Structure definition. + More...

+ +

#include <stm32f4xx_exti.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t EXTI_Line
 
EXTIMode_TypeDef EXTI_Mode
 
EXTITrigger_TypeDef EXTI_Trigger
 
FunctionalState EXTI_LineCmd
 
+

Detailed Description

+

EXTI Init Structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t EXTI_InitTypeDef::EXTI_Line
+
+

Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination value of EXTI_Lines

+ +
+
+ +
+
+ + + + +
FunctionalState EXTI_InitTypeDef::EXTI_LineCmd
+
+

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

+ +
+
+ +
+
+ + + + +
EXTIMode_TypeDef EXTI_InitTypeDef::EXTI_Mode
+
+

Specifies the mode for the EXTI lines. This parameter can be a value of EXTIMode_TypeDef

+ +
+
+ +
+
+ + + + +
EXTITrigger_TypeDef EXTI_InitTypeDef::EXTI_Trigger
+
+

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of EXTITrigger_TypeDef

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_e_x_t_i___type_def-members.html b/struct_e_x_t_i___type_def-members.html new file mode 100644 index 0000000..46caa64 --- /dev/null +++ b/struct_e_x_t_i___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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EXTI_TypeDef Member List
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This is the complete list of members for EXTI_TypeDef, including all inherited members.

+ + + + + + + +
EMREXTI_TypeDef
FTSREXTI_TypeDef
IMREXTI_TypeDef
PREXTI_TypeDef
RTSREXTI_TypeDef
SWIEREXTI_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_e_x_t_i___type_def.html b/struct_e_x_t_i___type_def.html new file mode 100644 index 0000000..bdf12e7 --- /dev/null +++ b/struct_e_x_t_i___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: EXTI_TypeDef Struct Reference + + + + + + + + + + +
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EXTI_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

External Interrupt/Event Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t IMR
 
__IO uint32_t EMR
 
__IO uint32_t RTSR
 
__IO uint32_t FTSR
 
__IO uint32_t SWIER
 
__IO uint32_t PR
 
+

Detailed Description

+

External Interrupt/Event Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t-members.html b/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..9309270 --- /dev/null +++ b/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FILE_DATE_STRUCT Member List
+
+
+ +

This is the complete list of members for FILE_DATE_STRUCT, including all inherited members.

+ + + + +
day (defined in FILE_DATE_STRUCT)FILE_DATE_STRUCT
month (defined in FILE_DATE_STRUCT)FILE_DATE_STRUCT
year (defined in FILE_DATE_STRUCT)FILE_DATE_STRUCT
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t.html b/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t.html new file mode 100644 index 0000000..01da369 --- /dev/null +++ b/struct_f_i_l_e___d_a_t_e___s_t_r_u_c_t.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: FILE_DATE_STRUCT Struct Reference + + + + + + + + + + +
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+Data Fields
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FILE_DATE_STRUCT Struct Reference
+
+
+ +

#include <filesystem.h>

+ + + + + + + + +

+Data Fields

unsigned year: 7
 
unsigned month: 4
 
unsigned day: 5
 
+

Field Documentation

+ +
+
+ + + + +
unsigned day
+
+ +
+
+ +
+
+ + + + +
unsigned month
+
+ +
+
+ +
+
+ + + + +
unsigned year
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_i_l_e___h_a_n_d_l_e-members.html b/struct_f_i_l_e___h_a_n_d_l_e-members.html new file mode 100644 index 0000000..1fb5a55 --- /dev/null +++ b/struct_f_i_l_e___h_a_n_d_l_e-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FILE_HANDLE Member List
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This is the complete list of members for FILE_HANDLE, including all inherited members.

+ + + + +
fname (defined in FILE_HANDLE)FILE_HANDLE
fpos (defined in FILE_HANDLE)FILE_HANDLE
fsize (defined in FILE_HANDLE)FILE_HANDLE
+ +
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FILE_HANDLE Struct Reference
+
+
+ +

#include <filesystem.h>

+ + + + + + + + +

+Data Fields

const char * fname
 
uint32_t fpos
 
uint32_t fsize
 
+

Field Documentation

+ +
+
+ + + + +
const char* fname
+
+ +
+
+ +
+
+ + + + +
uint32_t fpos
+
+ +
+
+ +
+
+ + + + +
uint32_t fsize
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.map b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.map new file mode 100644 index 0000000..7650bfb --- /dev/null +++ b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.md5 b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.md5 new file mode 100644 index 0000000..40854a2 --- /dev/null +++ b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.md5 @@ -0,0 +1 @@ +2ff91c881d4adce73540778853d5558b \ No newline at end of file diff --git a/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.png b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.png new file mode 100644 index 0000000..f4d13bb Binary files /dev/null and b/struct_f_i_l_e___h_a_n_d_l_e__inherit__graph.png differ diff --git a/struct_f_i_l_e___s_t_r_u_c_t-members.html b/struct_f_i_l_e___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..2c0fed6 --- /dev/null +++ b/struct_f_i_l_e___s_t_r_u_c_t-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FILE_STRUCT Member List
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This is the complete list of members for FILE_STRUCT, including all inherited members.

+ + + + + + +
fattrib (defined in FILE_STRUCT)FILE_STRUCT
fdate (defined in FILE_STRUCT)FILE_STRUCT
fname (defined in FILE_STRUCT)FILE_STRUCT
fsize (defined in FILE_STRUCT)FILE_STRUCT
ftime (defined in FILE_STRUCT)FILE_STRUCT
+ +
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FILE_STRUCT Struct Reference
+
+
+ +

#include <filesystem.h>

+
+Collaboration diagram for FILE_STRUCT:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + +

+Data Fields

uint32_t fsize
 
FILE_DATE_STRUCT fdate
 
FILE_TIME_STRUCT ftime
 
uint8_t fattrib
 
char * fname
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t fattrib
+
+ +
+
+ +
+
+ + + + +
FILE_DATE_STRUCT fdate
+
+ +
+
+ +
+
+ + + + +
char* fname
+
+ +
+
+ +
+
+ + + + +
uint32_t fsize
+
+ +
+
+ +
+
+ + + + +
FILE_TIME_STRUCT ftime
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.map b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.map new file mode 100644 index 0000000..a58b182 --- /dev/null +++ b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.md5 b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.md5 new file mode 100644 index 0000000..54856e1 --- /dev/null +++ b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.md5 @@ -0,0 +1 @@ +8f154924bbc9f076a171ee3626c9f0c9 \ No newline at end of file diff --git a/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.png b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.png new file mode 100644 index 0000000..930a9f2 Binary files /dev/null and b/struct_f_i_l_e___s_t_r_u_c_t__coll__graph.png differ diff --git a/struct_f_i_l_e___t_i_m_e___s_t_r_u_c_t-members.html b/struct_f_i_l_e___t_i_m_e___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..4066fe2 --- /dev/null +++ b/struct_f_i_l_e___t_i_m_e___s_t_r_u_c_t-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FILE_TIME_STRUCT Member List
+
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+ +

This is the complete list of members for FILE_TIME_STRUCT, including all inherited members.

+ + + + +
hour (defined in FILE_TIME_STRUCT)FILE_TIME_STRUCT
min (defined in FILE_TIME_STRUCT)FILE_TIME_STRUCT
sec (defined in FILE_TIME_STRUCT)FILE_TIME_STRUCT
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Data Fields
+
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FILE_TIME_STRUCT Struct Reference
+
+
+ +

#include <filesystem.h>

+ + + + + + + + +

+Data Fields

unsigned hour: 5
 
unsigned min: 6
 
unsigned sec: 5
 
+

Field Documentation

+ +
+
+ + + + +
unsigned hour
+
+ +
+
+ +
+
+ + + + +
unsigned min
+
+ +
+
+ +
+
+ + + + +
unsigned sec
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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FLASH_TypeDef Member List
+
+
+ +

This is the complete list of members for FLASH_TypeDef, including all inherited members.

+ + + + + + + + +
ACRFLASH_TypeDef
CRFLASH_TypeDef
KEYRFLASH_TypeDef
OPTCRFLASH_TypeDef
OPTCR1FLASH_TypeDef
OPTKEYRFLASH_TypeDef
SRFLASH_TypeDef
+ +
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FLASH_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
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FLASH Registers. + More...

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#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t ACR
 
__IO uint32_t KEYR
 
__IO uint32_t OPTKEYR
 
__IO uint32_t SR
 
__IO uint32_t CR
 
__IO uint32_t OPTCR
 
__IO uint32_t OPTCR1
 
+

Detailed Description

+

FLASH Registers.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank1___type_def-members.html b/struct_f_s_m_c___bank1___type_def-members.html new file mode 100644 index 0000000..941a82e --- /dev/null +++ b/struct_f_s_m_c___bank1___type_def-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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BTCRFSMC_Bank1_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank1___type_def.html b/struct_f_s_m_c___bank1___type_def.html new file mode 100644 index 0000000..daccedb --- /dev/null +++ b/struct_f_s_m_c___bank1___type_def.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: FSMC_Bank1_TypeDef Struct Reference + + + + + + + + + + +
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FSMC_Bank1_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Flexible Static Memory Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + +

+Public Attributes

__IO uint32_t BTCR [8]
 
+

Detailed Description

+

Flexible Static Memory Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank1_e___type_def-members.html b/struct_f_s_m_c___bank1_e___type_def-members.html new file mode 100644 index 0000000..1ca3762 --- /dev/null +++ b/struct_f_s_m_c___bank1_e___type_def-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_Bank1E_TypeDef Member List
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BWTRFSMC_Bank1E_TypeDef
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+ + diff --git a/struct_f_s_m_c___bank1_e___type_def.html b/struct_f_s_m_c___bank1_e___type_def.html new file mode 100644 index 0000000..f52252f --- /dev/null +++ b/struct_f_s_m_c___bank1_e___type_def.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: FSMC_Bank1E_TypeDef Struct Reference + + + + + + + + + + +
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FSMC_Bank1E_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Flexible Static Memory Controller Bank1E. + More...

+ +

#include <stm32f4xx.h>

+ + + + +

+Public Attributes

__IO uint32_t BWTR [7]
 
+

Detailed Description

+

Flexible Static Memory Controller Bank1E.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank2___type_def-members.html b/struct_f_s_m_c___bank2___type_def-members.html new file mode 100644 index 0000000..41f2bf5 --- /dev/null +++ b/struct_f_s_m_c___bank2___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ECCR2FSMC_Bank2_TypeDef
PATT2FSMC_Bank2_TypeDef
PCR2FSMC_Bank2_TypeDef
PMEM2FSMC_Bank2_TypeDef
RESERVED0FSMC_Bank2_TypeDef
SR2FSMC_Bank2_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank2___type_def.html b/struct_f_s_m_c___bank2___type_def.html new file mode 100644 index 0000000..f63841e --- /dev/null +++ b/struct_f_s_m_c___bank2___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: FSMC_Bank2_TypeDef Struct Reference + + + + + + + + + + +
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FSMC_Bank2_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Flexible Static Memory Controller Bank2. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t PCR2
 
__IO uint32_t SR2
 
__IO uint32_t PMEM2
 
__IO uint32_t PATT2
 
uint32_t RESERVED0
 
__IO uint32_t ECCR2
 
+

Detailed Description

+

Flexible Static Memory Controller Bank2.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank3___type_def-members.html b/struct_f_s_m_c___bank3___type_def-members.html new file mode 100644 index 0000000..6f4c23b --- /dev/null +++ b/struct_f_s_m_c___bank3___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_Bank3_TypeDef Member List
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This is the complete list of members for FSMC_Bank3_TypeDef, including all inherited members.

+ + + + + + + +
ECCR3FSMC_Bank3_TypeDef
PATT3FSMC_Bank3_TypeDef
PCR3FSMC_Bank3_TypeDef
PMEM3FSMC_Bank3_TypeDef
RESERVED0FSMC_Bank3_TypeDef
SR3FSMC_Bank3_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank3___type_def.html b/struct_f_s_m_c___bank3___type_def.html new file mode 100644 index 0000000..04e3daf --- /dev/null +++ b/struct_f_s_m_c___bank3___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: FSMC_Bank3_TypeDef Struct Reference + + + + + + + + + + +
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FSMC_Bank3_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Flexible Static Memory Controller Bank3. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t PCR3
 
__IO uint32_t SR3
 
__IO uint32_t PMEM3
 
__IO uint32_t PATT3
 
uint32_t RESERVED0
 
__IO uint32_t ECCR3
 
+

Detailed Description

+

Flexible Static Memory Controller Bank3.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank4___type_def-members.html b/struct_f_s_m_c___bank4___type_def-members.html new file mode 100644 index 0000000..c56b2eb --- /dev/null +++ b/struct_f_s_m_c___bank4___type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_Bank4_TypeDef Member List
+
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+ +

This is the complete list of members for FSMC_Bank4_TypeDef, including all inherited members.

+ + + + + + +
PATT4FSMC_Bank4_TypeDef
PCR4FSMC_Bank4_TypeDef
PIO4FSMC_Bank4_TypeDef
PMEM4FSMC_Bank4_TypeDef
SR4FSMC_Bank4_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___bank4___type_def.html b/struct_f_s_m_c___bank4___type_def.html new file mode 100644 index 0000000..056bcbf --- /dev/null +++ b/struct_f_s_m_c___bank4___type_def.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: FSMC_Bank4_TypeDef Struct Reference + + + + + + + + + + +
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FSMC_Bank4_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Flexible Static Memory Controller Bank4. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + +

+Public Attributes

__IO uint32_t PCR4
 
__IO uint32_t SR4
 
__IO uint32_t PMEM4
 
__IO uint32_t PATT4
 
__IO uint32_t PIO4
 
+

Detailed Description

+

Flexible Static Memory Controller Bank4.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def-members.html b/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def-members.html new file mode 100644 index 0000000..bfee7f3 --- /dev/null +++ b/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_NAND_PCCARDTimingInitTypeDef Member List
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This is the complete list of members for FSMC_NAND_PCCARDTimingInitTypeDef, including all inherited members.

+ + + + + +
FSMC_HiZSetupTimeFSMC_NAND_PCCARDTimingInitTypeDef
FSMC_HoldSetupTimeFSMC_NAND_PCCARDTimingInitTypeDef
FSMC_SetupTimeFSMC_NAND_PCCARDTimingInitTypeDef
FSMC_WaitSetupTimeFSMC_NAND_PCCARDTimingInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def.html b/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def.html new file mode 100644 index 0000000..ed39cfd --- /dev/null +++ b/struct_f_s_m_c___n_a_n_d___p_c_c_a_r_d_timing_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: FSMC_NAND_PCCARDTimingInitTypeDef Struct Reference + + + + + + + + + + +
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FSMC_NAND_PCCARDTimingInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+ +

Timing parameters For FSMC NAND and PCCARD Banks. + More...

+ +

#include <stm32f4xx_fsmc.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t FSMC_SetupTime
 
uint32_t FSMC_WaitSetupTime
 
uint32_t FSMC_HoldSetupTime
 
uint32_t FSMC_HiZSetupTime
 
+

Detailed Description

+

Timing parameters For FSMC NAND and PCCARD Banks.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HiZSetupTime
+
+

Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_HoldSetupTime
+
+

Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_SetupTime
+
+

Defines the number of HCLK cycles to setup address before the command assertion for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NAND_PCCARDTimingInitTypeDef::FSMC_WaitSetupTime
+
+

Defines the minimum number of HCLK cycles to assert the command for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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FSMC_NANDInitTypeDef Member List
+
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+ +

This is the complete list of members for FSMC_NANDInitTypeDef, including all inherited members.

+ + + + + + + + + + +
FSMC_AttributeSpaceTimingStructFSMC_NANDInitTypeDef
FSMC_BankFSMC_NANDInitTypeDef
FSMC_CommonSpaceTimingStructFSMC_NANDInitTypeDef
FSMC_ECCFSMC_NANDInitTypeDef
FSMC_ECCPageSizeFSMC_NANDInitTypeDef
FSMC_MemoryDataWidthFSMC_NANDInitTypeDef
FSMC_TARSetupTimeFSMC_NANDInitTypeDef
FSMC_TCLRSetupTimeFSMC_NANDInitTypeDef
FSMC_WaitfeatureFSMC_NANDInitTypeDef
+ +
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FSMC_NANDInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+ +

FSMC NAND Init structure definition. + More...

+ +

#include <stm32f4xx_fsmc.h>

+
+Collaboration diagram for FSMC_NANDInitTypeDef:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t FSMC_Bank
 
uint32_t FSMC_Waitfeature
 
uint32_t FSMC_MemoryDataWidth
 
uint32_t FSMC_ECC
 
uint32_t FSMC_ECCPageSize
 
uint32_t FSMC_TCLRSetupTime
 
uint32_t FSMC_TARSetupTime
 
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
 
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
 
+

Detailed Description

+

FSMC NAND Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_NANDInitTypeDef::FSMC_AttributeSpaceTimingStruct
+
+

FSMC Attribute Space Timing

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_Bank
+
+

Specifies the NAND memory bank that will be used. This parameter can be a value of FSMC_NAND_Bank

+ +
+
+ +
+
+ + + + +
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_NANDInitTypeDef::FSMC_CommonSpaceTimingStruct
+
+

FSMC Common Space Timing

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_ECC
+
+

Enables or disables the ECC computation. This parameter can be any value of FSMC_ECC

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_ECCPageSize
+
+

Defines the page size for the extended ECC. This parameter can be any value of FSMC_ECC_Page_Size

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_MemoryDataWidth
+
+

Specifies the external memory device width. This parameter can be any value of FSMC_Data_Width

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_TARSetupTime
+
+

Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_TCLRSetupTime
+
+

Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NANDInitTypeDef::FSMC_Waitfeature
+
+

Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of FSMC_Wait_feature

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.map b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.map new file mode 100644 index 0000000..60a4563 --- /dev/null +++ b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.md5 b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.md5 new file mode 100644 index 0000000..b65552c --- /dev/null +++ b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.md5 @@ -0,0 +1 @@ +d2625bff4d60e5c9e0c95ea95de00407 \ No newline at end of file diff --git a/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.png b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.png new file mode 100644 index 0000000..52841fa Binary files /dev/null and b/struct_f_s_m_c___n_a_n_d_init_type_def__coll__graph.png differ diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def-members.html b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def-members.html new file mode 100644 index 0000000..14d28d7 --- /dev/null +++ b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def-members.html @@ -0,0 +1,117 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_NORSRAMInitTypeDef Member List
+
+
+ +

This is the complete list of members for FSMC_NORSRAMInitTypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + +
FSMC_AsynchronousWaitFSMC_NORSRAMInitTypeDef
FSMC_BankFSMC_NORSRAMInitTypeDef
FSMC_BurstAccessModeFSMC_NORSRAMInitTypeDef
FSMC_DataAddressMuxFSMC_NORSRAMInitTypeDef
FSMC_ExtendedModeFSMC_NORSRAMInitTypeDef
FSMC_MemoryDataWidthFSMC_NORSRAMInitTypeDef
FSMC_MemoryTypeFSMC_NORSRAMInitTypeDef
FSMC_ReadWriteTimingStructFSMC_NORSRAMInitTypeDef
FSMC_WaitSignalFSMC_NORSRAMInitTypeDef
FSMC_WaitSignalActiveFSMC_NORSRAMInitTypeDef
FSMC_WaitSignalPolarityFSMC_NORSRAMInitTypeDef
FSMC_WrapModeFSMC_NORSRAMInitTypeDef
FSMC_WriteBurstFSMC_NORSRAMInitTypeDef
FSMC_WriteOperationFSMC_NORSRAMInitTypeDef
FSMC_WriteTimingStructFSMC_NORSRAMInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def.html b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def.html new file mode 100644 index 0000000..5f9f82c --- /dev/null +++ b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def.html @@ -0,0 +1,349 @@ + + + + + + +discoverpixy: FSMC_NORSRAMInitTypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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FSMC_NORSRAMInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+ +

FSMC NOR/SRAM Init structure definition. + More...

+ +

#include <stm32f4xx_fsmc.h>

+
+Collaboration diagram for FSMC_NORSRAMInitTypeDef:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t FSMC_Bank
 
uint32_t FSMC_DataAddressMux
 
uint32_t FSMC_MemoryType
 
uint32_t FSMC_MemoryDataWidth
 
uint32_t FSMC_BurstAccessMode
 
uint32_t FSMC_AsynchronousWait
 
uint32_t FSMC_WaitSignalPolarity
 
uint32_t FSMC_WrapMode
 
uint32_t FSMC_WaitSignalActive
 
uint32_t FSMC_WriteOperation
 
uint32_t FSMC_WaitSignal
 
uint32_t FSMC_ExtendedMode
 
uint32_t FSMC_WriteBurst
 
FSMC_NORSRAMTimingInitTypeDef * FSMC_ReadWriteTimingStruct
 
FSMC_NORSRAMTimingInitTypeDef * FSMC_WriteTimingStruct
 
+

Detailed Description

+

FSMC NOR/SRAM Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_AsynchronousWait
+
+

Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of FSMC_AsynchronousWait

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_Bank
+
+

Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of FSMC_NORSRAM_Bank

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_BurstAccessMode
+
+

Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of FSMC_Burst_Access_Mode

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_DataAddressMux
+
+

Specifies whether the address and data values are multiplexed on the data bus or not. This parameter can be a value of FSMC_Data_Address_Bus_Multiplexing

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_ExtendedMode
+
+

Enables or disables the extended mode. This parameter can be a value of FSMC_Extended_Mode

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryDataWidth
+
+

Specifies the external memory device width. This parameter can be a value of FSMC_Data_Width

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_MemoryType
+
+

Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of FSMC_Memory_Type

+ +
+
+ +
+
+ + + + +
FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_ReadWriteTimingStruct
+
+

Timing Parameters for write and read access if the Extended Mode is not used

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignal
+
+

Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of FSMC_Wait_Signal

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalActive
+
+

Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of FSMC_Wait_Timing

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WaitSignalPolarity
+
+

Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of FSMC_Wait_Signal_Polarity

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WrapMode
+
+

Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of FSMC_Wrap_Mode

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteBurst
+
+

Enables or disables the write burst operation. This parameter can be a value of FSMC_Write_Burst

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMInitTypeDef::FSMC_WriteOperation
+
+

Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of FSMC_Write_Operation

+ +
+
+ +
+
+ + + + +
FSMC_NORSRAMTimingInitTypeDef* FSMC_NORSRAMInitTypeDef::FSMC_WriteTimingStruct
+
+

Timing Parameters for write access if the Extended Mode is used

+ +
+
+
The documentation for this struct was generated from the following file: +
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+ + diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.map b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.map new file mode 100644 index 0000000..24d9494 --- /dev/null +++ b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.md5 b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.md5 new file mode 100644 index 0000000..a0e8f61 --- /dev/null +++ b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.md5 @@ -0,0 +1 @@ +12054d373c620f8199ef475b6d809185 \ No newline at end of file diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.png b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.png new file mode 100644 index 0000000..5d191ae Binary files /dev/null and b/struct_f_s_m_c___n_o_r_s_r_a_m_init_type_def__coll__graph.png differ diff --git a/struct_f_s_m_c___n_o_r_s_r_a_m_timing_init_type_def-members.html b/struct_f_s_m_c___n_o_r_s_r_a_m_timing_init_type_def-members.html new file mode 100644 index 0000000..3df9675 --- /dev/null +++ b/struct_f_s_m_c___n_o_r_s_r_a_m_timing_init_type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_NORSRAMTimingInitTypeDef Member List
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This is the complete list of members for FSMC_NORSRAMTimingInitTypeDef, including all inherited members.

+ + + + + + + + +
FSMC_AccessModeFSMC_NORSRAMTimingInitTypeDef
FSMC_AddressHoldTimeFSMC_NORSRAMTimingInitTypeDef
FSMC_AddressSetupTimeFSMC_NORSRAMTimingInitTypeDef
FSMC_BusTurnAroundDurationFSMC_NORSRAMTimingInitTypeDef
FSMC_CLKDivisionFSMC_NORSRAMTimingInitTypeDef
FSMC_DataLatencyFSMC_NORSRAMTimingInitTypeDef
FSMC_DataSetupTimeFSMC_NORSRAMTimingInitTypeDef
+ +
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FSMC_NORSRAMTimingInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+ +

Timing parameters For NOR/SRAM Banks. + More...

+ +

#include <stm32f4xx_fsmc.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t FSMC_AddressSetupTime
 
uint32_t FSMC_AddressHoldTime
 
uint32_t FSMC_DataSetupTime
 
uint32_t FSMC_BusTurnAroundDuration
 
uint32_t FSMC_CLKDivision
 
uint32_t FSMC_DataLatency
 
uint32_t FSMC_AccessMode
 
+

Detailed Description

+

Timing parameters For NOR/SRAM Banks.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AccessMode
+
+

Specifies the asynchronous access mode. This parameter can be a value of FSMC_Access_Mode

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressHoldTime
+
+

Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF.

Note
This parameter is not used with synchronous NOR Flash memories.
+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_AddressSetupTime
+
+

Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF.

Note
This parameter is not used with synchronous NOR Flash memories.
+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_BusTurnAroundDuration
+
+

Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF.

Note
This parameter is only used for multiplexed NOR Flash memories.
+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_CLKDivision
+
+

Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF.

Note
This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses.
+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataLatency
+
+

Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below:

    +
  • It must be set to 0 in case of a CRAM
    • +
  • It is don't care in asynchronous NOR, SRAM or ROM accesses
    • +
  • It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable
    • +
+ +
+
+ +
+
+ + + + +
uint32_t FSMC_NORSRAMTimingInitTypeDef::FSMC_DataSetupTime
+
+

Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF.

Note
This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories.
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_f_s_m_c___p_c_c_a_r_d_init_type_def-members.html b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def-members.html new file mode 100644 index 0000000..e1f738b --- /dev/null +++ b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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FSMC_PCCARDInitTypeDef Member List
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This is the complete list of members for FSMC_PCCARDInitTypeDef, including all inherited members.

+ + + + + + + +
FSMC_AttributeSpaceTimingStructFSMC_PCCARDInitTypeDef
FSMC_CommonSpaceTimingStructFSMC_PCCARDInitTypeDef
FSMC_IOSpaceTimingStructFSMC_PCCARDInitTypeDef
FSMC_TARSetupTimeFSMC_PCCARDInitTypeDef
FSMC_TCLRSetupTimeFSMC_PCCARDInitTypeDef
FSMC_WaitfeatureFSMC_PCCARDInitTypeDef
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FSMC_PCCARDInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » FSMC
+
+
+ +

FSMC PCCARD Init structure definition. + More...

+ +

#include <stm32f4xx_fsmc.h>

+
+Collaboration diagram for FSMC_PCCARDInitTypeDef:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t FSMC_Waitfeature
 
uint32_t FSMC_TCLRSetupTime
 
uint32_t FSMC_TARSetupTime
 
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_CommonSpaceTimingStruct
 
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_AttributeSpaceTimingStruct
 
FSMC_NAND_PCCARDTimingInitTypeDef * FSMC_IOSpaceTimingStruct
 
+

Detailed Description

+

FSMC PCCARD Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_AttributeSpaceTimingStruct
+
+

FSMC Attribute Space Timing

+ +
+
+ +
+
+ + + + +
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_CommonSpaceTimingStruct
+
+

FSMC Common Space Timing

+ +
+
+ +
+
+ + + + +
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_PCCARDInitTypeDef::FSMC_IOSpaceTimingStruct
+
+

FSMC IO Space Timing

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_PCCARDInitTypeDef::FSMC_TARSetupTime
+
+

Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_PCCARDInitTypeDef::FSMC_TCLRSetupTime
+
+

Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t FSMC_PCCARDInitTypeDef::FSMC_Waitfeature
+
+

Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of FSMC_Wait_feature

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.map b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.map new file mode 100644 index 0000000..3b3435a --- /dev/null +++ b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.md5 b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.md5 new file mode 100644 index 0000000..b44662a --- /dev/null +++ b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.md5 @@ -0,0 +1 @@ +db1b99e1da0e86be0914b267ad1c14d0 \ No newline at end of file diff --git a/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.png b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.png new file mode 100644 index 0000000..9f28558 Binary files /dev/null and b/struct_f_s_m_c___p_c_c_a_r_d_init_type_def__coll__graph.png differ diff --git a/struct_fpoint-members.html b/struct_fpoint-members.html new file mode 100644 index 0000000..0bd5c3d --- /dev/null +++ b/struct_fpoint-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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Fpoint() (defined in Fpoint)Fpointinline
Fpoint(float x, float y) (defined in Fpoint)Fpointinline
Fpoint() (defined in Fpoint)Fpointinline
Fpoint(float x, float y) (defined in Fpoint)Fpointinline
m_x (defined in Fpoint)Fpoint
m_y (defined in Fpoint)Fpoint
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Fpoint Struct Reference
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+ Fpoint (float x, float y)
 
+ Fpoint (float x, float y)
 
+ + + + + +

+Public Attributes

+float m_x
 
+float m_y
 
+
The documentation for this struct was generated from the following file: +
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Frame8() (defined in Frame8)Frame8inline
Frame8(uint8_t *pixels, uint16_t width, uint16_t height) (defined in Frame8)Frame8inline
Frame8() (defined in Frame8)Frame8inline
Frame8(uint8_t *pixels, uint16_t width, uint16_t height) (defined in Frame8)Frame8inline
m_height (defined in Frame8)Frame8
m_pixels (defined in Frame8)Frame8
m_width (defined in Frame8)Frame8
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+ Frame8 (uint8_t *pixels, uint16_t width, uint16_t height)
 
+ Frame8 (uint8_t *pixels, uint16_t width, uint16_t height)
 
+ + + + + + + +

+Public Attributes

+uint8_t * m_pixels
 
+int16_t m_width
 
+int16_t m_height
 
+
The documentation for this struct was generated from the following file: +
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This is the complete list of members for GPIO_InitTypeDef, including all inherited members.

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GPIO_ModeGPIO_InitTypeDef
GPIO_OTypeGPIO_InitTypeDef
GPIO_PinGPIO_InitTypeDef
GPIO_PuPdGPIO_InitTypeDef
GPIO_SpeedGPIO_InitTypeDef
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+ + diff --git a/struct_g_p_i_o___init_type_def.html b/struct_g_p_i_o___init_type_def.html new file mode 100644 index 0000000..ac34231 --- /dev/null +++ b/struct_g_p_i_o___init_type_def.html @@ -0,0 +1,192 @@ + + + + + + +discoverpixy: GPIO_InitTypeDef Struct Reference + + + + + + + + + + +
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GPIO_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » GPIO
+
+
+ +

GPIO Init structure definition. + More...

+ +

#include <stm32f4xx_gpio.h>

+ + + + + + + + + + + + +

+Public Attributes

uint32_t GPIO_Pin
 
GPIOMode_TypeDef GPIO_Mode
 
GPIOSpeed_TypeDef GPIO_Speed
 
GPIOOType_TypeDef GPIO_OType
 
GPIOPuPd_TypeDef GPIO_PuPd
 
+

Detailed Description

+

GPIO Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
GPIOMode_TypeDef GPIO_InitTypeDef::GPIO_Mode
+
+

Specifies the operating mode for the selected pins. This parameter can be a value of GPIOMode_TypeDef

+ +
+
+ +
+
+ + + + +
GPIOOType_TypeDef GPIO_InitTypeDef::GPIO_OType
+
+

Specifies the operating output type for the selected pins. This parameter can be a value of GPIOOType_TypeDef

+ +
+
+ +
+
+ + + + +
uint32_t GPIO_InitTypeDef::GPIO_Pin
+
+

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO_pins_define

+ +
+
+ +
+
+ + + + +
GPIOPuPd_TypeDef GPIO_InitTypeDef::GPIO_PuPd
+
+

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of GPIOPuPd_TypeDef

+ +
+
+ +
+
+ + + + +
GPIOSpeed_TypeDef GPIO_InitTypeDef::GPIO_Speed
+
+

Specifies the speed for the selected pins. This parameter can be a value of GPIOSpeed_TypeDef

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_g_p_i_o___type_def-members.html b/struct_g_p_i_o___type_def-members.html new file mode 100644 index 0000000..737ce06 --- /dev/null +++ b/struct_g_p_i_o___type_def-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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GPIO_TypeDef Member List
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This is the complete list of members for GPIO_TypeDef, including all inherited members.

+ + + + + + + + + + + +
AFRGPIO_TypeDef
BSRRHGPIO_TypeDef
BSRRLGPIO_TypeDef
IDRGPIO_TypeDef
LCKRGPIO_TypeDef
MODERGPIO_TypeDef
ODRGPIO_TypeDef
OSPEEDRGPIO_TypeDef
OTYPERGPIO_TypeDef
PUPDRGPIO_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_g_p_i_o___type_def.html b/struct_g_p_i_o___type_def.html new file mode 100644 index 0000000..4b73488 --- /dev/null +++ b/struct_g_p_i_o___type_def.html @@ -0,0 +1,136 @@ + + + + + + +discoverpixy: GPIO_TypeDef Struct Reference + + + + + + + + + + +
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GPIO_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

General Purpose I/O. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t MODER
 
__IO uint32_t OTYPER
 
__IO uint32_t OSPEEDR
 
__IO uint32_t PUPDR
 
__IO uint32_t IDR
 
__IO uint32_t ODR
 
__IO uint16_t BSRRL
 
__IO uint16_t BSRRH
 
__IO uint32_t LCKR
 
__IO uint32_t AFR [2]
 
+

Detailed Description

+

General Purpose I/O.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___context-members.html b/struct_h_a_s_h___context-members.html new file mode 100644 index 0000000..1e34d8a --- /dev/null +++ b/struct_h_a_s_h___context-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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HASH_Context Member List
+
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This is the complete list of members for HASH_Context, including all inherited members.

+ + + + + +
HASH_CR (defined in HASH_Context)HASH_Context
HASH_CSR (defined in HASH_Context)HASH_Context
HASH_IMR (defined in HASH_Context)HASH_Context
HASH_STR (defined in HASH_Context)HASH_Context
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___context.html b/struct_h_a_s_h___context.html new file mode 100644 index 0000000..c91aa4f --- /dev/null +++ b/struct_h_a_s_h___context.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: HASH_Context Struct Reference + + + + + + + + + + +
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HASH_Context Struct Reference
STM32F4xx_StdPeriph_Driver » HASH
+
+
+ +

HASH context swapping structure definition. + More...

+ +

#include <stm32f4xx_hash.h>

+ + + + + + + + + + +

+Public Attributes

+uint32_t HASH_IMR
 
+uint32_t HASH_STR
 
+uint32_t HASH_CR
 
+uint32_t HASH_CSR [54]
 
+

Detailed Description

+

HASH context swapping structure definition.

+
The documentation for this struct was generated from the following file: +
+ +
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HASH_DIGEST_TypeDef Member List
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This is the complete list of members for HASH_DIGEST_TypeDef, including all inherited members.

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HRHASH_DIGEST_TypeDef
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+ + diff --git a/struct_h_a_s_h___d_i_g_e_s_t___type_def.html b/struct_h_a_s_h___d_i_g_e_s_t___type_def.html new file mode 100644 index 0000000..cd6acc1 --- /dev/null +++ b/struct_h_a_s_h___d_i_g_e_s_t___type_def.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: HASH_DIGEST_TypeDef Struct Reference + + + + + + + + + + +
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HASH_DIGEST_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
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+ +

HASH_DIGEST. + More...

+ +

#include <stm32f4xx.h>

+ + + + +

+Public Attributes

__IO uint32_t HR [8]
 
+

Detailed Description

+

HASH_DIGEST.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___init_type_def-members.html b/struct_h_a_s_h___init_type_def-members.html new file mode 100644 index 0000000..8c02714 --- /dev/null +++ b/struct_h_a_s_h___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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HASH_InitTypeDef Member List
+
+
+ +

This is the complete list of members for HASH_InitTypeDef, including all inherited members.

+ + + + + +
HASH_AlgoModeHASH_InitTypeDef
HASH_AlgoSelectionHASH_InitTypeDef
HASH_DataTypeHASH_InitTypeDef
HASH_HMACKeyTypeHASH_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___init_type_def.html b/struct_h_a_s_h___init_type_def.html new file mode 100644 index 0000000..914c5c3 --- /dev/null +++ b/struct_h_a_s_h___init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: HASH_InitTypeDef Struct Reference + + + + + + + + + + +
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HASH_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » HASH
+
+
+ +

HASH Init structure definition. + More...

+ +

#include <stm32f4xx_hash.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t HASH_AlgoSelection
 
uint32_t HASH_AlgoMode
 
uint32_t HASH_DataType
 
uint32_t HASH_HMACKeyType
 
+

Detailed Description

+

HASH Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t HASH_InitTypeDef::HASH_AlgoMode
+
+

HASH or HMAC. This parameter can be a value of HASH_processor_Algorithm_Mode

+ +
+
+ +
+
+ + + + +
uint32_t HASH_InitTypeDef::HASH_AlgoSelection
+
+

SHA-1, SHA-224, SHA-256 or MD5. This parameter can be a value of HASH_Algo_Selection

+ +
+
+ +
+
+ + + + +
uint32_t HASH_InitTypeDef::HASH_DataType
+
+

32-bit data, 16-bit data, 8-bit data or bit string. This parameter can be a value of HASH_Data_Type

+ +
+
+ +
+
+ + + + +
uint32_t HASH_InitTypeDef::HASH_HMACKeyType
+
+

HMAC Short key or HMAC Long Key. This parameter can be a value of HASH_HMAC_Long_key_only_for_HMAC_mode

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___msg_digest-members.html b/struct_h_a_s_h___msg_digest-members.html new file mode 100644 index 0000000..08beabc --- /dev/null +++ b/struct_h_a_s_h___msg_digest-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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HASH_MsgDigest Member List
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This is the complete list of members for HASH_MsgDigest, including all inherited members.

+ + +
DataHASH_MsgDigest
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___msg_digest.html b/struct_h_a_s_h___msg_digest.html new file mode 100644 index 0000000..4c778d1 --- /dev/null +++ b/struct_h_a_s_h___msg_digest.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: HASH_MsgDigest Struct Reference + + + + + + + + + + +
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HASH_MsgDigest Struct Reference
STM32F4xx_StdPeriph_Driver » HASH
+
+
+ +

HASH message digest result structure definition. + More...

+ +

#include <stm32f4xx_hash.h>

+ + + + +

+Public Attributes

uint32_t Data [8]
 
+

Detailed Description

+

HASH message digest result structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t HASH_MsgDigest::Data[8]
+
+

Message digest result : 8x 32bit wors for SHA-256, 7x 32bit wors for SHA-224, 5x 32bit words for SHA-1 or 4x 32bit words for MD5

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___type_def-members.html b/struct_h_a_s_h___type_def-members.html new file mode 100644 index 0000000..b7969f3 --- /dev/null +++ b/struct_h_a_s_h___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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HASH_TypeDef Member List
+
+
+ +

This is the complete list of members for HASH_TypeDef, including all inherited members.

+ + + + + + + + + +
CRHASH_TypeDef
CSRHASH_TypeDef
DINHASH_TypeDef
HRHASH_TypeDef
IMRHASH_TypeDef
RESERVEDHASH_TypeDef
SRHASH_TypeDef
STRHASH_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_a_s_h___type_def.html b/struct_h_a_s_h___type_def.html new file mode 100644 index 0000000..a87c146 --- /dev/null +++ b/struct_h_a_s_h___type_def.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: HASH_TypeDef Struct Reference + + + + + + + + + + +
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HASH_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

HASH. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t DIN
 
__IO uint32_t STR
 
__IO uint32_t HR [5]
 
__IO uint32_t IMR
 
__IO uint32_t SR
 
uint32_t RESERVED [52]
 
__IO uint32_t CSR [54]
 
+

Detailed Description

+

HASH.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_h_i_d__cb-members.html b/struct_h_i_d__cb-members.html new file mode 100644 index 0000000..aea1d2c --- /dev/null +++ b/struct_h_i_d__cb-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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This is the complete list of members for HID_cb, including all inherited members.

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Decode (defined in HID_cb)HID_cb
Init (defined in HID_cb)HID_cb
+ +
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+ + diff --git a/struct_h_i_d__cb.html b/struct_h_i_d__cb.html new file mode 100644 index 0000000..09513ee --- /dev/null +++ b/struct_h_i_d__cb.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: HID_cb Struct Reference + + + + + + + + + + +
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HID_cb Struct Reference
USBH_LIB » USBH_CLASS » USBH_HID_CLASS » USBH_HID_CORE » USBH_HID_CORE_Exported_Types
+
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+ + + + + + +

+Public Attributes

+void(* Init )(void)
 
+void(* Decode )(uint8_t *data)
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h
    • +
+
+ +
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+ + diff --git a/struct_hue_pixel-members.html b/struct_hue_pixel-members.html new file mode 100644 index 0000000..ae137f7 --- /dev/null +++ b/struct_hue_pixel-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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HuePixel Member List
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This is the complete list of members for HuePixel, including all inherited members.

+ + + + + + + +
HuePixel() (defined in HuePixel)HuePixelinline
HuePixel(int8_t u, int8_t v) (defined in HuePixel)HuePixelinline
HuePixel() (defined in HuePixel)HuePixelinline
HuePixel(int8_t u, int8_t v) (defined in HuePixel)HuePixelinline
m_u (defined in HuePixel)HuePixel
m_v (defined in HuePixel)HuePixel
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_hue_pixel.html b/struct_hue_pixel.html new file mode 100644 index 0000000..9510f8e --- /dev/null +++ b/struct_hue_pixel.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: HuePixel Struct Reference + + + + + + + + + + +
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HuePixel Struct Reference
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+Public Member Functions

+ HuePixel (int8_t u, int8_t v)
 
+ HuePixel (int8_t u, int8_t v)
 
+ + + + + +

+Public Attributes

+int8_t m_u
 
+int8_t m_v
 
+
The documentation for this struct was generated from the following file: +
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I2C_InitTypeDef Member List
+
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This is the complete list of members for I2C_InitTypeDef, including all inherited members.

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I2C_AckI2C_InitTypeDef
I2C_AcknowledgedAddressI2C_InitTypeDef
I2C_ClockSpeedI2C_InitTypeDef
I2C_DutyCycleI2C_InitTypeDef
I2C_ModeI2C_InitTypeDef
I2C_OwnAddress1I2C_InitTypeDef
+ +
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+ + diff --git a/struct_i2_c___init_type_def.html b/struct_i2_c___init_type_def.html new file mode 100644 index 0000000..4555b6b --- /dev/null +++ b/struct_i2_c___init_type_def.html @@ -0,0 +1,207 @@ + + + + + + +discoverpixy: I2C_InitTypeDef Struct Reference + + + + + + + + + + +
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I2C_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » I2C
+
+
+ +

I2C Init structure definition. + More...

+ +

#include <stm32f4xx_i2c.h>

+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t I2C_ClockSpeed
 
uint16_t I2C_Mode
 
uint16_t I2C_DutyCycle
 
uint16_t I2C_OwnAddress1
 
uint16_t I2C_Ack
 
uint16_t I2C_AcknowledgedAddress
 
+

Detailed Description

+

I2C Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t I2C_InitTypeDef::I2C_Ack
+
+

Enables or disables the acknowledgement. This parameter can be a value of I2C_acknowledgement

+ +
+
+ +
+
+ + + + +
uint16_t I2C_InitTypeDef::I2C_AcknowledgedAddress
+
+

Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of I2C_acknowledged_address

+ +
+
+ +
+
+ + + + +
uint32_t I2C_InitTypeDef::I2C_ClockSpeed
+
+

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz

+ +
+
+ +
+
+ + + + +
uint16_t I2C_InitTypeDef::I2C_DutyCycle
+
+

Specifies the I2C fast mode duty cycle. This parameter can be a value of I2C_duty_cycle_in_fast_mode

+ +
+
+ +
+
+ + + + +
uint16_t I2C_InitTypeDef::I2C_Mode
+
+

Specifies the I2C mode. This parameter can be a value of I2C_mode

+ +
+
+ +
+
+ + + + +
uint16_t I2C_InitTypeDef::I2C_OwnAddress1
+
+

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i2_c___type_def-members.html b/struct_i2_c___type_def-members.html new file mode 100644 index 0000000..e51c75d --- /dev/null +++ b/struct_i2_c___type_def-members.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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I2C_TypeDef Member List
+
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+ +

This is the complete list of members for I2C_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + +
CCRI2C_TypeDef
CR1I2C_TypeDef
CR2I2C_TypeDef
DRI2C_TypeDef
FLTRI2C_TypeDef
OAR1I2C_TypeDef
OAR2I2C_TypeDef
RESERVED0I2C_TypeDef
RESERVED1I2C_TypeDef
RESERVED2I2C_TypeDef
RESERVED3I2C_TypeDef
RESERVED4I2C_TypeDef
RESERVED5I2C_TypeDef
RESERVED6I2C_TypeDef
RESERVED7I2C_TypeDef
RESERVED8I2C_TypeDef
RESERVED9I2C_TypeDef
SR1I2C_TypeDef
SR2I2C_TypeDef
TRISEI2C_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i2_c___type_def.html b/struct_i2_c___type_def.html new file mode 100644 index 0000000..4276daf --- /dev/null +++ b/struct_i2_c___type_def.html @@ -0,0 +1,156 @@ + + + + + + +discoverpixy: I2C_TypeDef Struct Reference + + + + + + + + + + +
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+
+
I2C_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Inter-integrated Circuit Interface. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint16_t CR1
 
uint16_t RESERVED0
 
__IO uint16_t CR2
 
uint16_t RESERVED1
 
__IO uint16_t OAR1
 
uint16_t RESERVED2
 
__IO uint16_t OAR2
 
uint16_t RESERVED3
 
__IO uint16_t DR
 
uint16_t RESERVED4
 
__IO uint16_t SR1
 
uint16_t RESERVED5
 
__IO uint16_t SR2
 
uint16_t RESERVED6
 
__IO uint16_t CCR
 
uint16_t RESERVED7
 
__IO uint16_t TRISE
 
uint16_t RESERVED8
 
__IO uint16_t FLTR
 
uint16_t RESERVED9
 
+

Detailed Description

+

Inter-integrated Circuit Interface.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i2_s___init_type_def-members.html b/struct_i2_s___init_type_def-members.html new file mode 100644 index 0000000..00754ac --- /dev/null +++ b/struct_i2_s___init_type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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I2S_InitTypeDef Member List
+
+
+ +

This is the complete list of members for I2S_InitTypeDef, including all inherited members.

+ + + + + + + +
I2S_AudioFreqI2S_InitTypeDef
I2S_CPOLI2S_InitTypeDef
I2S_DataFormatI2S_InitTypeDef
I2S_MCLKOutputI2S_InitTypeDef
I2S_ModeI2S_InitTypeDef
I2S_StandardI2S_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i2_s___init_type_def.html b/struct_i2_s___init_type_def.html new file mode 100644 index 0000000..5276fbc --- /dev/null +++ b/struct_i2_s___init_type_def.html @@ -0,0 +1,207 @@ + + + + + + +discoverpixy: I2S_InitTypeDef Struct Reference + + + + + + + + + + +
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I2S_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SPI
+
+
+ +

I2S Init structure definition. + More...

+ +

#include <stm32f4xx_spi.h>

+ + + + + + + + + + + + + + +

+Public Attributes

uint16_t I2S_Mode
 
uint16_t I2S_Standard
 
uint16_t I2S_DataFormat
 
uint16_t I2S_MCLKOutput
 
uint32_t I2S_AudioFreq
 
uint16_t I2S_CPOL
 
+

Detailed Description

+

I2S Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t I2S_InitTypeDef::I2S_AudioFreq
+
+

Specifies the frequency selected for the I2S communication. This parameter can be a value of I2S_Audio_Frequency

+ +
+
+ +
+
+ + + + +
uint16_t I2S_InitTypeDef::I2S_CPOL
+
+

Specifies the idle state of the I2S clock. This parameter can be a value of I2S_Clock_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t I2S_InitTypeDef::I2S_DataFormat
+
+

Specifies the data format for the I2S communication. This parameter can be a value of I2S_Data_Format

+ +
+
+ +
+
+ + + + +
uint16_t I2S_InitTypeDef::I2S_MCLKOutput
+
+

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of I2S_MCLK_Output

+ +
+
+ +
+
+ + + + +
uint16_t I2S_InitTypeDef::I2S_Mode
+
+

Specifies the I2S operating mode. This parameter can be a value of I2S_Mode

+ +
+
+ +
+
+ + + + +
uint16_t I2S_InitTypeDef::I2S_Standard
+
+

Specifies the standard used for the I2S communication. This parameter can be a value of I2S_Standard

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i_t_m___type-members.html b/struct_i_t_m___type-members.html new file mode 100644 index 0000000..466f1b0 --- /dev/null +++ b/struct_i_t_m___type-members.html @@ -0,0 +1,132 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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ITM_Type Member List
+
+
+ +

This is the complete list of members for ITM_Type, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CID0ITM_Type
CID1ITM_Type
CID2ITM_Type
CID3ITM_Type
IMCRITM_Type
IRRITM_Type
IWRITM_Type
LARITM_Type
LSRITM_Type
PID0ITM_Type
PID1ITM_Type
PID2ITM_Type
PID3ITM_Type
PID4ITM_Type
PID5ITM_Type
PID6ITM_Type
PID7ITM_Type
PORTITM_Type
RESERVED0 (defined in ITM_Type)ITM_Type
RESERVED1 (defined in ITM_Type)ITM_Type
RESERVED2 (defined in ITM_Type)ITM_Type
RESERVED3 (defined in ITM_Type)ITM_Type
RESERVED4 (defined in ITM_Type)ITM_Type
RESERVED5 (defined in ITM_Type)ITM_Type
TCRITM_Type
TERITM_Type
TPRITM_Type
u16ITM_Type
u32ITM_Type
u8ITM_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i_t_m___type.html b/struct_i_t_m___type.html new file mode 100644 index 0000000..4d7c29a --- /dev/null +++ b/struct_i_t_m___type.html @@ -0,0 +1,496 @@ + + + + + + +discoverpixy: ITM_Type Struct Reference + + + + + + + + + + +
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ITM_Type Struct Reference
Defines and Type Definitions » Instrumentation Trace Macrocell (ITM)
+
+
+ +

Structure type to access the Instrumentation Trace Macrocell Register (ITM). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

union {
   __O uint8_t   u8
 
   __O uint16_t   u16
 
   __O uint32_t   u32
 
} PORT [32]
 
+uint32_t RESERVED0 [864]
 
__IO uint32_t TER
 
+uint32_t RESERVED1 [15]
 
__IO uint32_t TPR
 
+uint32_t RESERVED2 [15]
 
__IO uint32_t TCR
 
+uint32_t RESERVED3 [29]
 
__O uint32_t IWR
 
__I uint32_t IRR
 
__IO uint32_t IMCR
 
+uint32_t RESERVED4 [43]
 
__O uint32_t LAR
 
__I uint32_t LSR
 
+uint32_t RESERVED5 [6]
 
__I uint32_t PID4
 
__I uint32_t PID5
 
__I uint32_t PID6
 
__I uint32_t PID7
 
__I uint32_t PID0
 
__I uint32_t PID1
 
__I uint32_t PID2
 
__I uint32_t PID3
 
__I uint32_t CID0
 
__I uint32_t CID1
 
__I uint32_t CID2
 
__I uint32_t CID3
 
+

Detailed Description

+

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

+

Member Data Documentation

+ +
+
+ + + + +
__I uint32_t ITM_Type::CID0
+
+

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::CID1
+
+

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::CID2
+
+

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::CID3
+
+

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::IMCR
+
+

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::IRR
+
+

Offset: 0xEFC (R/ ) ITM Integration Read Register

+ +
+
+ +
+
+ + + + +
__O uint32_t ITM_Type::IWR
+
+

Offset: 0xEF8 ( /W) ITM Integration Write Register

+ +
+
+ +
+
+ + + + +
__O uint32_t ITM_Type::LAR
+
+

Offset: 0xFB0 ( /W) ITM Lock Access Register

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::LSR
+
+

Offset: 0xFB4 (R/ ) ITM Lock Status Register

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID0
+
+

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID1
+
+

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID2
+
+

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID3
+
+

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID4
+
+

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID5
+
+

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID6
+
+

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

+ +
+
+ +
+
+ + + + +
__I uint32_t ITM_Type::PID7
+
+

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

+ +
+
+ +
+
+ + + + +
__O { ... } ITM_Type::PORT[32]
+
+

Offset: 0x000 ( /W) ITM Stimulus Port Registers

+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TCR
+
+

Offset: 0xE80 (R/W) ITM Trace Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TER
+
+

Offset: 0xE00 (R/W) ITM Trace Enable Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t ITM_Type::TPR
+
+

Offset: 0xE40 (R/W) ITM Trace Privilege Register

+ +
+
+ +
+
+ + + + +
__O uint16_t ITM_Type::u16
+
+

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

+ +
+
+ +
+
+ + + + +
__O uint32_t ITM_Type::u32
+
+

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

+ +
+
+ +
+
+ + + + +
__O uint8_t ITM_Type::u8
+
+

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_i_w_d_g___type_def-members.html b/struct_i_w_d_g___type_def-members.html new file mode 100644 index 0000000..2baa33c --- /dev/null +++ b/struct_i_w_d_g___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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IWDG_TypeDef Member List
+
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This is the complete list of members for IWDG_TypeDef, including all inherited members.

+ + + + + +
KRIWDG_TypeDef
PRIWDG_TypeDef
RLRIWDG_TypeDef
SRIWDG_TypeDef
+ +
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+ + diff --git a/struct_i_w_d_g___type_def.html b/struct_i_w_d_g___type_def.html new file mode 100644 index 0000000..19c06b8 --- /dev/null +++ b/struct_i_w_d_g___type_def.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: IWDG_TypeDef Struct Reference + + + + + + + + + + +
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IWDG_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Independent WATCHDOG. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t KR
 
__IO uint32_t PR
 
__IO uint32_t RLR
 
__IO uint32_t SR
 
+

Detailed Description

+

Independent WATCHDOG.

+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_l_i_s302_d_l___filter_config_type_def-members.html b/struct_l_i_s302_d_l___filter_config_type_def-members.html new file mode 100644 index 0000000..8b29a9e --- /dev/null +++ b/struct_l_i_s302_d_l___filter_config_type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LIS302DL_FilterConfigTypeDef Member List
+
+
+ +

This is the complete list of members for LIS302DL_FilterConfigTypeDef, including all inherited members.

+ + + + +
HighPassFilter_CutOff_Frequency (defined in LIS302DL_FilterConfigTypeDef)LIS302DL_FilterConfigTypeDef
HighPassFilter_Data_Selection (defined in LIS302DL_FilterConfigTypeDef)LIS302DL_FilterConfigTypeDef
HighPassFilter_Interrupt (defined in LIS302DL_FilterConfigTypeDef)LIS302DL_FilterConfigTypeDef
+ +
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LIS302DL_FilterConfigTypeDef Struct Reference
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Types
+
+
+ + + + + + + + +

+Public Attributes

+uint8_t HighPassFilter_Data_Selection
 
+uint8_t HighPassFilter_CutOff_Frequency
 
+uint8_t HighPassFilter_Interrupt
 
+
The documentation for this struct was generated from the following file: +
+ +
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LIS302DL_InitTypeDef Member List
+
+
+ +

This is the complete list of members for LIS302DL_InitTypeDef, including all inherited members.

+ + + + + + +
Axes_Enable (defined in LIS302DL_InitTypeDef)LIS302DL_InitTypeDef
Full_Scale (defined in LIS302DL_InitTypeDef)LIS302DL_InitTypeDef
Output_DataRate (defined in LIS302DL_InitTypeDef)LIS302DL_InitTypeDef
Power_Mode (defined in LIS302DL_InitTypeDef)LIS302DL_InitTypeDef
Self_Test (defined in LIS302DL_InitTypeDef)LIS302DL_InitTypeDef
+ +
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+ + diff --git a/struct_l_i_s302_d_l___init_type_def.html b/struct_l_i_s302_d_l___init_type_def.html new file mode 100644 index 0000000..11db149 --- /dev/null +++ b/struct_l_i_s302_d_l___init_type_def.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: LIS302DL_InitTypeDef Struct Reference + + + + + + + + + + +
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+
LIS302DL_InitTypeDef Struct Reference
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Types
+
+
+ + + + + + + + + + + + +

+Public Attributes

+uint8_t Power_Mode
 
+uint8_t Output_DataRate
 
+uint8_t Axes_Enable
 
+uint8_t Full_Scale
 
+uint8_t Self_Test
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_i_s302_d_l___interrupt_config_type_def-members.html b/struct_l_i_s302_d_l___interrupt_config_type_def-members.html new file mode 100644 index 0000000..4ac0677 --- /dev/null +++ b/struct_l_i_s302_d_l___interrupt_config_type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LIS302DL_InterruptConfigTypeDef Member List
+
+
+ +

This is the complete list of members for LIS302DL_InterruptConfigTypeDef, including all inherited members.

+ + + + +
DoubleClick_Axes (defined in LIS302DL_InterruptConfigTypeDef)LIS302DL_InterruptConfigTypeDef
Latch_Request (defined in LIS302DL_InterruptConfigTypeDef)LIS302DL_InterruptConfigTypeDef
SingleClick_Axes (defined in LIS302DL_InterruptConfigTypeDef)LIS302DL_InterruptConfigTypeDef
+ +
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+Public Attributes | +List of all members
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LIS302DL_InterruptConfigTypeDef Struct Reference
Utilities » STM32F4_DISCOVERY » STM32F4_DISCOVERY_LIS302DL » STM32F4_DISCOVERY_LIS302DL_Exported_Types
+
+
+ + + + + + + + +

+Public Attributes

+uint8_t Latch_Request
 
+uint8_t SingleClick_Axes
 
+uint8_t DoubleClick_Axes
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___c_l_u_t___init_type_def-members.html b/struct_l_t_d_c___c_l_u_t___init_type_def-members.html new file mode 100644 index 0000000..4eb1b63 --- /dev/null +++ b/struct_l_t_d_c___c_l_u_t___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_CLUT_InitTypeDef Member List
+
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+ +

This is the complete list of members for LTDC_CLUT_InitTypeDef, including all inherited members.

+ + + + + +
LTDC_BlueValueLTDC_CLUT_InitTypeDef
LTDC_CLUTAdressLTDC_CLUT_InitTypeDef
LTDC_GreenValueLTDC_CLUT_InitTypeDef
LTDC_RedValueLTDC_CLUT_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___c_l_u_t___init_type_def.html b/struct_l_t_d_c___c_l_u_t___init_type_def.html new file mode 100644 index 0000000..0f29905 --- /dev/null +++ b/struct_l_t_d_c___c_l_u_t___init_type_def.html @@ -0,0 +1,170 @@ + + + + + + +discoverpixy: LTDC_CLUT_InitTypeDef Struct Reference + + + + + + + + + + +
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LTDC_CLUT_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ + + + + + + + + + +

+Public Attributes

uint32_t LTDC_CLUTAdress
 
uint32_t LTDC_BlueValue
 
uint32_t LTDC_GreenValue
 
uint32_t LTDC_RedValue
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_CLUT_InitTypeDef::LTDC_BlueValue
+
+

Configures the blue value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_CLUT_InitTypeDef::LTDC_CLUTAdress
+
+

Configures the CLUT address. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_CLUT_InitTypeDef::LTDC_GreenValue
+
+

Configures the green value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_CLUT_InitTypeDef::LTDC_RedValue
+
+

Configures the red value. This parameter must range from 0x00 to 0xFF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___color_keying___init_type_def-members.html b/struct_l_t_d_c___color_keying___init_type_def-members.html new file mode 100644 index 0000000..8b3d1c4 --- /dev/null +++ b/struct_l_t_d_c___color_keying___init_type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_ColorKeying_InitTypeDef Member List
+
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+ +

This is the complete list of members for LTDC_ColorKeying_InitTypeDef, including all inherited members.

+ + + + +
LTDC_ColorKeyBlueLTDC_ColorKeying_InitTypeDef
LTDC_ColorKeyGreenLTDC_ColorKeying_InitTypeDef
LTDC_ColorKeyRedLTDC_ColorKeying_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___color_keying___init_type_def.html b/struct_l_t_d_c___color_keying___init_type_def.html new file mode 100644 index 0000000..8d18b92 --- /dev/null +++ b/struct_l_t_d_c___color_keying___init_type_def.html @@ -0,0 +1,155 @@ + + + + + + +discoverpixy: LTDC_ColorKeying_InitTypeDef Struct Reference + + + + + + + + + + +
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LTDC_ColorKeying_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ + + + + + + + +

+Public Attributes

uint32_t LTDC_ColorKeyBlue
 
uint32_t LTDC_ColorKeyGreen
 
uint32_t LTDC_ColorKeyRed
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyBlue
+
+

Configures the color key blue value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyGreen
+
+

Configures the color key green value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_ColorKeying_InitTypeDef::LTDC_ColorKeyRed
+
+

Configures the color key red value. This parameter must range from 0x00 to 0xFF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___init_type_def-members.html b/struct_l_t_d_c___init_type_def-members.html new file mode 100644 index 0000000..44a0acb --- /dev/null +++ b/struct_l_t_d_c___init_type_def-members.html @@ -0,0 +1,117 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_InitTypeDef Member List
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This is the complete list of members for LTDC_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + +
LTDC_AccumulatedActiveHLTDC_InitTypeDef
LTDC_AccumulatedActiveWLTDC_InitTypeDef
LTDC_AccumulatedHBPLTDC_InitTypeDef
LTDC_AccumulatedVBPLTDC_InitTypeDef
LTDC_BackgroundBlueValueLTDC_InitTypeDef
LTDC_BackgroundGreenValueLTDC_InitTypeDef
LTDC_BackgroundRedValueLTDC_InitTypeDef
LTDC_DEPolarityLTDC_InitTypeDef
LTDC_HorizontalSyncLTDC_InitTypeDef
LTDC_HSPolarityLTDC_InitTypeDef
LTDC_PCPolarityLTDC_InitTypeDef
LTDC_TotalHeighLTDC_InitTypeDef
LTDC_TotalWidthLTDC_InitTypeDef
LTDC_VerticalSyncLTDC_InitTypeDef
LTDC_VSPolarityLTDC_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___init_type_def.html b/struct_l_t_d_c___init_type_def.html new file mode 100644 index 0000000..342284e --- /dev/null +++ b/struct_l_t_d_c___init_type_def.html @@ -0,0 +1,342 @@ + + + + + + +discoverpixy: LTDC_InitTypeDef Struct Reference + + + + + + + + + + +
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LTDC_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ +

LTDC Init structure definition. + More...

+ +

#include <stm32f4xx_ltdc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t LTDC_HSPolarity
 
uint32_t LTDC_VSPolarity
 
uint32_t LTDC_DEPolarity
 
uint32_t LTDC_PCPolarity
 
uint32_t LTDC_HorizontalSync
 
uint32_t LTDC_VerticalSync
 
uint32_t LTDC_AccumulatedHBP
 
uint32_t LTDC_AccumulatedVBP
 
uint32_t LTDC_AccumulatedActiveW
 
uint32_t LTDC_AccumulatedActiveH
 
uint32_t LTDC_TotalWidth
 
uint32_t LTDC_TotalHeigh
 
uint32_t LTDC_BackgroundRedValue
 
uint32_t LTDC_BackgroundGreenValue
 
uint32_t LTDC_BackgroundBlueValue
 
+

Detailed Description

+

LTDC Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_AccumulatedActiveH
+
+

configures the accumulated active heigh. This parameter must range from LTDC_AccumulatedVBP to 0x7FF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_AccumulatedActiveW
+
+

configures the accumulated active width. This parameter must range from LTDC_AccumulatedHBP to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_AccumulatedHBP
+
+

configures the accumulated horizontal back porch width. This parameter must range from LTDC_HorizontalSync to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_AccumulatedVBP
+
+

configures the accumulated vertical back porch heigh. This parameter must range from LTDC_VerticalSync to 0x7FF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_BackgroundBlueValue
+
+

configures the background blue value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_BackgroundGreenValue
+
+

configures the background green value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_BackgroundRedValue
+
+

configures the background red value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_DEPolarity
+
+

configures the data enable polarity. This parameter can be one of value of LTDC_DEPolarity

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_HorizontalSync
+
+

configures the number of Horizontal synchronization width. This parameter must range from 0x000 to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_HSPolarity
+
+

configures the horizontal synchronization polarity. This parameter can be one value of LTDC_HSPolarity

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_PCPolarity
+
+

configures the pixel clock polarity. This parameter can be one of value of LTDC_PCPolarity

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_TotalHeigh
+
+

configures the total heigh. This parameter must range from LTDC_AccumulatedActiveH to 0x7FF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_TotalWidth
+
+

configures the total width. This parameter must range from LTDC_AccumulatedActiveW to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_VerticalSync
+
+

configures the number of Vertical synchronization heigh. This parameter must range from 0x000 to 0x7FF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_InitTypeDef::LTDC_VSPolarity
+
+

configures the vertical synchronization polarity. This parameter can be one value of LTDC_VSPolarity

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___layer___init_type_def-members.html b/struct_l_t_d_c___layer___init_type_def-members.html new file mode 100644 index 0000000..ca4aff8 --- /dev/null +++ b/struct_l_t_d_c___layer___init_type_def-members.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_Layer_InitTypeDef Member List
+
+
+ +

This is the complete list of members for LTDC_Layer_InitTypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + +
LTDC_BlendingFactor_1LTDC_Layer_InitTypeDef
LTDC_BlendingFactor_2LTDC_Layer_InitTypeDef
LTDC_CFBLineLengthLTDC_Layer_InitTypeDef
LTDC_CFBLineNumberLTDC_Layer_InitTypeDef
LTDC_CFBPitchLTDC_Layer_InitTypeDef
LTDC_CFBStartAdressLTDC_Layer_InitTypeDef
LTDC_ConstantAlphaLTDC_Layer_InitTypeDef
LTDC_DefaultColorAlphaLTDC_Layer_InitTypeDef
LTDC_DefaultColorBlueLTDC_Layer_InitTypeDef
LTDC_DefaultColorGreenLTDC_Layer_InitTypeDef
LTDC_DefaultColorRedLTDC_Layer_InitTypeDef
LTDC_HorizontalStartLTDC_Layer_InitTypeDef
LTDC_HorizontalStopLTDC_Layer_InitTypeDef
LTDC_PixelFormatLTDC_Layer_InitTypeDef
LTDC_VerticalStartLTDC_Layer_InitTypeDef
LTDC_VerticalStopLTDC_Layer_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___layer___init_type_def.html b/struct_l_t_d_c___layer___init_type_def.html new file mode 100644 index 0000000..eeeafd3 --- /dev/null +++ b/struct_l_t_d_c___layer___init_type_def.html @@ -0,0 +1,357 @@ + + + + + + +discoverpixy: LTDC_Layer_InitTypeDef Struct Reference + + + + + + + + + + +
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+
+
LTDC_Layer_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ +

LTDC Layer structure definition. + More...

+ +

#include <stm32f4xx_ltdc.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t LTDC_HorizontalStart
 
uint32_t LTDC_HorizontalStop
 
uint32_t LTDC_VerticalStart
 
uint32_t LTDC_VerticalStop
 
uint32_t LTDC_PixelFormat
 
uint32_t LTDC_ConstantAlpha
 
uint32_t LTDC_DefaultColorBlue
 
uint32_t LTDC_DefaultColorGreen
 
uint32_t LTDC_DefaultColorRed
 
uint32_t LTDC_DefaultColorAlpha
 
uint32_t LTDC_BlendingFactor_1
 
uint32_t LTDC_BlendingFactor_2
 
uint32_t LTDC_CFBStartAdress
 
uint32_t LTDC_CFBLineLength
 
uint32_t LTDC_CFBPitch
 
uint32_t LTDC_CFBLineNumber
 
+

Detailed Description

+

LTDC Layer structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_BlendingFactor_1
+
+

Select the blending factor 1. This parameter can be one of value of LTDC_BlendingFactor1

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_BlendingFactor_2
+
+

Select the blending factor 2. This parameter can be one of value of LTDC_BlendingFactor2

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_CFBLineLength
+
+

Configures the color frame buffer line length. This parameter must range from 0x0000 to 0x1FFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_CFBLineNumber
+
+

Specifies the number of line in frame buffer. This parameter must range from 0x000 to 0x7FF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_CFBPitch
+
+

Configures the color frame buffer pitch in bytes. This parameter must range from 0x0000 to 0x1FFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_CFBStartAdress
+
+

Configures the color frame buffer address

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_ConstantAlpha
+
+

Specifies the constant alpha used for blending. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_DefaultColorAlpha
+
+

Configures the default alpha value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_DefaultColorBlue
+
+

Configures the default blue value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_DefaultColorGreen
+
+

Configures the default green value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_DefaultColorRed
+
+

Configures the default red value. This parameter must range from 0x00 to 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_HorizontalStart
+
+

Configures the Window Horizontal Start Position. This parameter must range from 0x000 to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_HorizontalStop
+
+

Configures the Window Horizontal Stop Position. This parameter must range from 0x0000 to 0xFFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_PixelFormat
+
+

Specifies the pixel format. This parameter can be one of value of LTDC_Pixelformat

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_VerticalStart
+
+

Configures the Window vertical Start Position. This parameter must range from 0x000 to 0xFFF.

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_Layer_InitTypeDef::LTDC_VerticalStop
+
+

Configures the Window vaertical Stop Position. This parameter must range from 0x0000 to 0xFFFF.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___layer___type_def-members.html b/struct_l_t_d_c___layer___type_def-members.html new file mode 100644 index 0000000..ce19acf --- /dev/null +++ b/struct_l_t_d_c___layer___type_def-members.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_Layer_TypeDef Member List
+
+
+ +

This is the complete list of members for LTDC_Layer_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + +
BFCRLTDC_Layer_TypeDef
CACRLTDC_Layer_TypeDef
CFBARLTDC_Layer_TypeDef
CFBLNRLTDC_Layer_TypeDef
CFBLRLTDC_Layer_TypeDef
CKCRLTDC_Layer_TypeDef
CLUTWRLTDC_Layer_TypeDef
CRLTDC_Layer_TypeDef
DCCRLTDC_Layer_TypeDef
PFCRLTDC_Layer_TypeDef
RESERVED0LTDC_Layer_TypeDef
RESERVED1LTDC_Layer_TypeDef
WHPCRLTDC_Layer_TypeDef
WVPCRLTDC_Layer_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___layer___type_def.html b/struct_l_t_d_c___layer___type_def.html new file mode 100644 index 0000000..dd51a10 --- /dev/null +++ b/struct_l_t_d_c___layer___type_def.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: LTDC_Layer_TypeDef Struct Reference + + + + + + + + + + +
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+
LTDC_Layer_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

LCD-TFT Display layer x Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t WHPCR
 
__IO uint32_t WVPCR
 
__IO uint32_t CKCR
 
__IO uint32_t PFCR
 
__IO uint32_t CACR
 
__IO uint32_t DCCR
 
__IO uint32_t BFCR
 
uint32_t RESERVED0 [2]
 
__IO uint32_t CFBAR
 
__IO uint32_t CFBLR
 
__IO uint32_t CFBLNR
 
uint32_t RESERVED1 [3]
 
__IO uint32_t CLUTWR
 
+

Detailed Description

+

LCD-TFT Display layer x Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___pos_type_def-members.html b/struct_l_t_d_c___pos_type_def-members.html new file mode 100644 index 0000000..a542015 --- /dev/null +++ b/struct_l_t_d_c___pos_type_def-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
LTDC_PosTypeDef Member List
+
+
+ +

This is the complete list of members for LTDC_PosTypeDef, including all inherited members.

+ + + +
LTDC_POSXLTDC_PosTypeDef
LTDC_POSYLTDC_PosTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___pos_type_def.html b/struct_l_t_d_c___pos_type_def.html new file mode 100644 index 0000000..046d455 --- /dev/null +++ b/struct_l_t_d_c___pos_type_def.html @@ -0,0 +1,147 @@ + + + + + + +discoverpixy: LTDC_PosTypeDef Struct Reference + + + + + + + + + + +
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LTDC_PosTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ +

LTDC Position structure definition. + More...

+ +

#include <stm32f4xx_ltdc.h>

+ + + + + + +

+Public Attributes

uint32_t LTDC_POSX
 
uint32_t LTDC_POSY
 
+

Detailed Description

+

LTDC Position structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_PosTypeDef::LTDC_POSX
+
+

Current X Position

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_PosTypeDef::LTDC_POSY
+
+

Current Y Position

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___r_g_b_type_def-members.html b/struct_l_t_d_c___r_g_b_type_def-members.html new file mode 100644 index 0000000..ab4b26e --- /dev/null +++ b/struct_l_t_d_c___r_g_b_type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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LTDC_RGBTypeDef Member List
+
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+ +

This is the complete list of members for LTDC_RGBTypeDef, including all inherited members.

+ + + + +
LTDC_BlueWidthLTDC_RGBTypeDef
LTDC_GreenWidthLTDC_RGBTypeDef
LTDC_RedWidthLTDC_RGBTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___r_g_b_type_def.html b/struct_l_t_d_c___r_g_b_type_def.html new file mode 100644 index 0000000..2af9a02 --- /dev/null +++ b/struct_l_t_d_c___r_g_b_type_def.html @@ -0,0 +1,155 @@ + + + + + + +discoverpixy: LTDC_RGBTypeDef Struct Reference + + + + + + + + + + +
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LTDC_RGBTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » LTDC
+
+
+ + + + + + + + +

+Public Attributes

uint32_t LTDC_BlueWidth
 
uint32_t LTDC_GreenWidth
 
uint32_t LTDC_RedWidth
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t LTDC_RGBTypeDef::LTDC_BlueWidth
+
+

Blue width

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_RGBTypeDef::LTDC_GreenWidth
+
+

Green width

+ +
+
+ +
+
+ + + + +
uint32_t LTDC_RGBTypeDef::LTDC_RedWidth
+
+

Red width

+ +
+
+
The documentation for this struct was generated from the following file: +
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LTDC_TypeDef Member List
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This is the complete list of members for LTDC_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
AWCRLTDC_TypeDef
BCCRLTDC_TypeDef
BPCRLTDC_TypeDef
CDSRLTDC_TypeDef
CPSRLTDC_TypeDef
GCRLTDC_TypeDef
ICRLTDC_TypeDef
IERLTDC_TypeDef
ISRLTDC_TypeDef
LIPCRLTDC_TypeDef
RESERVED0LTDC_TypeDef
RESERVED1LTDC_TypeDef
RESERVED2LTDC_TypeDef
RESERVED3LTDC_TypeDef
SRCRLTDC_TypeDef
SSCRLTDC_TypeDef
TWCRLTDC_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_l_t_d_c___type_def.html b/struct_l_t_d_c___type_def.html new file mode 100644 index 0000000..e25e4a1 --- /dev/null +++ b/struct_l_t_d_c___type_def.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: LTDC_TypeDef Struct Reference + + + + + + + + + + +
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LTDC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

LCD-TFT Display Controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t RESERVED0 [2]
 
__IO uint32_t SSCR
 
__IO uint32_t BPCR
 
__IO uint32_t AWCR
 
__IO uint32_t TWCR
 
__IO uint32_t GCR
 
uint32_t RESERVED1 [2]
 
__IO uint32_t SRCR
 
uint32_t RESERVED2 [1]
 
__IO uint32_t BCCR
 
uint32_t RESERVED3 [1]
 
__IO uint32_t IER
 
__IO uint32_t ISR
 
__IO uint32_t ICR
 
__IO uint32_t LIPCR
 
__IO uint32_t CPSR
 
__IO uint32_t CDSR
 
+

Detailed Description

+

LCD-TFT Display Controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_line-members.html b/struct_line-members.html new file mode 100644 index 0000000..eb61b30 --- /dev/null +++ b/struct_line-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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Line Member List
+
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This is the complete list of members for Line, including all inherited members.

+ + + + + + + +
Line() (defined in Line)Lineinline
Line(float slope, float yi) (defined in Line)Lineinline
Line() (defined in Line)Lineinline
Line(float slope, float yi) (defined in Line)Lineinline
m_slope (defined in Line)Line
m_yi (defined in Line)Line
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_line.html b/struct_line.html new file mode 100644 index 0000000..d3d9483 --- /dev/null +++ b/struct_line.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: Line Struct Reference + + + + + + + + + + +
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Line Struct Reference
+
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+ + + + + + +

+Public Member Functions

+ Line (float slope, float yi)
 
+ Line (float slope, float yi)
 
+ + + + + +

+Public Attributes

+float m_slope
 
+float m_yi
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_m_s_c___machine___type_def-members.html b/struct_m_s_c___machine___type_def-members.html new file mode 100644 index 0000000..92227d8 --- /dev/null +++ b/struct_m_s_c___machine___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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MSC_Machine_TypeDef Member List
+
+
+ +

This is the complete list of members for MSC_Machine_TypeDef, including all inherited members.

+ + + + + + + +
hc_num_in (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
hc_num_out (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
MSBulkInEp (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
MSBulkInEpSize (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
MSBulkOutEp (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
MSBulkOutEpSize (defined in MSC_Machine_TypeDef)MSC_Machine_TypeDef
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_m_s_c___machine___type_def.html b/struct_m_s_c___machine___type_def.html new file mode 100644 index 0000000..1fe0fc8 --- /dev/null +++ b/struct_m_s_c___machine___type_def.html @@ -0,0 +1,192 @@ + + + + + + +discoverpixy: MSC_Machine_TypeDef Struct Reference + + + + + + + + + + +
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+Data Fields
+
+
MSC_Machine_TypeDef Struct Reference
+
+
+ + + + + + + + + + + + + + +

+Data Fields

uint8_t hc_num_in
 
uint8_t hc_num_out
 
uint8_t MSBulkOutEp
 
uint8_t MSBulkInEp
 
uint16_t MSBulkInEpSize
 
uint16_t MSBulkOutEpSize
 
+

Field Documentation

+ +
+
+ + + + +
uint8_t hc_num_in
+
+ +
+
+ +
+
+ + + + +
uint8_t hc_num_out
+
+ +
+
+ +
+
+ + + + +
uint8_t MSBulkInEp
+
+ +
+
+ +
+
+ + + + +
uint16_t MSBulkInEpSize
+
+ +
+
+ +
+
+ + + + +
uint8_t MSBulkOutEp
+
+ +
+
+ +
+
+ + + + +
uint16_t MSBulkOutEpSize
+
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t-members.html b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..6f6dd01 --- /dev/null +++ b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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NUMUPDOWN_STRUCT Member List
+
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+ +

This is the complete list of members for NUMUPDOWN_STRUCT, including all inherited members.

+ + + + + + + + + + +
buttonDown (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
buttonUp (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
callback (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
fgcolor (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
max (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
min (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
value (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
x (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
y (defined in NUMUPDOWN_STRUCT)NUMUPDOWN_STRUCT
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
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+Data Fields
+
+
NUMUPDOWN_STRUCT Struct Reference
Gui » NummericUpDown
+
+
+ +

#include <numupdown.h>

+
+Collaboration diagram for NUMUPDOWN_STRUCT:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Data Fields

uint16_t x
 
uint16_t y
 
uint16_t fgcolor
 
int16_t value
 
int16_t min
 
int16_t max
 
NUMUPDOWN_CALLBACK callback
 
BUTTON_STRUCT buttonUp
 
BUTTON_STRUCT buttonDown
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.map b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.map new file mode 100644 index 0000000..239c57b --- /dev/null +++ b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.md5 b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.md5 new file mode 100644 index 0000000..e4021d4 --- /dev/null +++ b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.md5 @@ -0,0 +1 @@ +7a97714fa46fc0b307af5b2250951771 \ No newline at end of file diff --git a/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.png b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.png new file mode 100644 index 0000000..0fc6edc Binary files /dev/null and b/struct_n_u_m_u_p_d_o_w_n___s_t_r_u_c_t__coll__graph.png differ diff --git a/struct_n_v_i_c___init_type_def-members.html b/struct_n_v_i_c___init_type_def-members.html new file mode 100644 index 0000000..e344758 --- /dev/null +++ b/struct_n_v_i_c___init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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NVIC_InitTypeDef Member List
+
+
+ +

This is the complete list of members for NVIC_InitTypeDef, including all inherited members.

+ + + + + +
NVIC_IRQChannelNVIC_InitTypeDef
NVIC_IRQChannelCmdNVIC_InitTypeDef
NVIC_IRQChannelPreemptionPriorityNVIC_InitTypeDef
NVIC_IRQChannelSubPriorityNVIC_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_n_v_i_c___init_type_def.html b/struct_n_v_i_c___init_type_def.html new file mode 100644 index 0000000..4d4be61 --- /dev/null +++ b/struct_n_v_i_c___init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: NVIC_InitTypeDef Struct Reference + + + + + + + + + + +
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NVIC_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » MISC
+
+
+ +

NVIC Init Structure definition. + More...

+ +

#include <misc.h>

+ + + + + + + + + + +

+Public Attributes

uint8_t NVIC_IRQChannel
 
uint8_t NVIC_IRQChannelPreemptionPriority
 
uint8_t NVIC_IRQChannelSubPriority
 
FunctionalState NVIC_IRQChannelCmd
 
+

Detailed Description

+

NVIC Init Structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t NVIC_InitTypeDef::NVIC_IRQChannel
+
+

Specifies the IRQ channel to be enabled or disabled. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)

+ +
+
+ +
+
+ + + + +
FunctionalState NVIC_InitTypeDef::NVIC_IRQChannelCmd
+
+

Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE

+ +
+
+ +
+
+ + + + +
uint8_t NVIC_InitTypeDef::NVIC_IRQChannelPreemptionPriority
+
+

Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table MISC_NVIC_Priority_Table A lower priority value indicates a higher priority

+ +
+
+ +
+
+ + + + +
uint8_t NVIC_InitTypeDef::NVIC_IRQChannelSubPriority
+
+

Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table MISC_NVIC_Priority_Table A lower priority value indicates a higher priority

+ +
+
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmCoreNPheriph/inc/misc.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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NVIC_Type Member List
+
+
+ +

This is the complete list of members for NVIC_Type, including all inherited members.

+ + + + + + + + + + + + + + +
IABRNVIC_Type
ICERNVIC_Type
ICPRNVIC_Type
IPNVIC_Type
ISERNVIC_Type
ISPRNVIC_Type
RESERVED0 (defined in NVIC_Type)NVIC_Type
RESERVED2 (defined in NVIC_Type)NVIC_Type
RESERVED3 (defined in NVIC_Type)NVIC_Type
RESERVED4 (defined in NVIC_Type)NVIC_Type
RESERVED5 (defined in NVIC_Type)NVIC_Type
RSERVED1 (defined in NVIC_Type)NVIC_Type
STIRNVIC_Type
+ +
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+ + diff --git a/struct_n_v_i_c___type.html b/struct_n_v_i_c___type.html new file mode 100644 index 0000000..1f83d6c --- /dev/null +++ b/struct_n_v_i_c___type.html @@ -0,0 +1,240 @@ + + + + + + +discoverpixy: NVIC_Type Struct Reference + + + + + + + + + + +
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NVIC_Type Struct Reference
Defines and Type Definitions » Nested Vectored Interrupt Controller (NVIC)
+
+
+ +

Structure type to access the Nested Vectored Interrupt Controller (NVIC). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t ISER [8]
 
+uint32_t RESERVED0 [24]
 
__IO uint32_t ICER [8]
 
+uint32_t RSERVED1 [24]
 
__IO uint32_t ISPR [8]
 
+uint32_t RESERVED2 [24]
 
__IO uint32_t ICPR [8]
 
+uint32_t RESERVED3 [24]
 
__IO uint32_t IABR [8]
 
+uint32_t RESERVED4 [56]
 
__IO uint8_t IP [240]
 
+uint32_t RESERVED5 [644]
 
__O uint32_t STIR
 
+

Detailed Description

+

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

+

Member Data Documentation

+ +
+
+ + + + +
__IO uint32_t NVIC_Type::IABR[8]
+
+

Offset: 0x200 (R/W) Interrupt Active bit Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ICER[8]
+
+

Offset: 0x080 (R/W) Interrupt Clear Enable Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ICPR[8]
+
+

Offset: 0x180 (R/W) Interrupt Clear Pending Register

+ +
+
+ +
+
+ + + + +
__IO uint8_t NVIC_Type::IP[240]
+
+

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ISER[8]
+
+

Offset: 0x000 (R/W) Interrupt Set Enable Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t NVIC_Type::ISPR[8]
+
+

Offset: 0x100 (R/W) Interrupt Set Pending Register

+ +
+
+ +
+
+ + + + +
__O uint32_t NVIC_Type::STIR
+
+

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_p_o_i_n_t___s_t_r_u_c_t-members.html b/struct_p_o_i_n_t___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..d9e9743 --- /dev/null +++ b/struct_p_o_i_n_t___s_t_r_u_c_t-members.html @@ -0,0 +1,102 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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POINT_STRUCT Member List
+
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This is the complete list of members for POINT_STRUCT, including all inherited members.

+ + + +
x (defined in POINT_STRUCT)POINT_STRUCT
y (defined in POINT_STRUCT)POINT_STRUCT
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+Data Fields
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POINT_STRUCT Struct Reference
Touch
+
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+ +

#include <touch.h>

+ + + + + + + + +

+Data Fields

uint16_t x
 The X-Coordinate of the point. More...
 
uint16_t y
 The Y-Coordinate of the point. More...
 
+

Detailed Description

+

Struct which represents a 2D point on the display

+

Field Documentation

+ +
+
+ + + + +
uint16_t x
+
+ +

The X-Coordinate of the point.

+ +
+
+ +
+
+ + + + +
uint16_t y
+
+ +

The Y-Coordinate of the point.

+ +
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The documentation for this struct was generated from the following file: +
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PWR_TypeDef Member List
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This is the complete list of members for PWR_TypeDef, including all inherited members.

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CRPWR_TypeDef
CSRPWR_TypeDef
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PWR_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Power Control. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t CSR
 
+

Detailed Description

+

Power Control.

+
The documentation for this struct was generated from the following file: +
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Point16 Member List
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This is the complete list of members for Point16, including all inherited members.

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m_x (defined in Point16)Point16
m_y (defined in Point16)Point16
Point16() (defined in Point16)Point16inline
Point16(int16_t x, int16_t y) (defined in Point16)Point16inline
Point16() (defined in Point16)Point16inline
Point16(int16_t x, int16_t y) (defined in Point16)Point16inline
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Point16 Struct Reference
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+Public Member Functions

+ Point16 (int16_t x, int16_t y)
 
+ Point16 (int16_t x, int16_t y)
 
+ + + + + +

+Public Attributes

+int16_t m_x
 
+int16_t m_y
 
+
The documentation for this struct was generated from the following file: +
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m_x (defined in Point32)Point32
m_y (defined in Point32)Point32
Point32() (defined in Point32)Point32inline
Point32(int32_t x, int32_t y) (defined in Point32)Point32inline
Point32() (defined in Point32)Point32inline
Point32(int32_t x, int32_t y) (defined in Point32)Point32inline
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Point32 Struct Reference
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+Public Member Functions

+ Point32 (int32_t x, int32_t y)
 
+ Point32 (int32_t x, int32_t y)
 
+ + + + + +

+Public Attributes

+int32_t m_x
 
+int32_t m_y
 
+
The documentation for this struct was generated from the following file: +
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ProcInfo Struct Reference
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+Public Attributes

+char * procName
 
+uint8_t * argTypes
 
+char * procInfo
 
+
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procName (defined in ProcModule)ProcModule
procPtr (defined in ProcModule)ProcModule
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ProcModule Struct Reference
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+char * procName
 
+ProcPtr procPtr
 
+uint8_t argTypes [CRP_MAX_ARGS]
 
+char * procInfo
 
+
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chirpProc (defined in ProcTableEntry)ProcTableEntry
extension (defined in ProcTableEntry)ProcTableEntry
procName (defined in ProcTableEntry)ProcTableEntry
procPtr (defined in ProcTableEntry)ProcTableEntry
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ProcTableEntry Struct Reference
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+Public Attributes

+const char * procName
 
+ProcPtr procPtr
 
+ChirpProc chirpProc
 
+const ProcTableExtension * extension
 
+
The documentation for this struct was generated from the following file: +
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argTypes (defined in ProcTableExtension)ProcTableExtension
procInfo (defined in ProcTableExtension)ProcTableExtension
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ProcTableExtension Struct Reference
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+Public Attributes

+uint8_t argTypes [CRP_MAX_ARGS]
 
+char * procInfo
 
+
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QT_FILE_HANDLE Member List
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file (defined in QT_FILE_HANDLE)QT_FILE_HANDLE
fname (defined in FILE_HANDLE)FILE_HANDLE
fpos (defined in FILE_HANDLE)FILE_HANDLE
fsize (defined in FILE_HANDLE)FILE_HANDLE
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QT_FILE_HANDLE Struct Reference
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QFile * file
 
- Data Fields inherited from FILE_HANDLE
const char * fname
 
uint32_t fpos
 
uint32_t fsize
 
+

Field Documentation

+ +
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QFile* file
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consumed (defined in QqueueFields)QqueueFields
data (defined in QqueueFields)QqueueFields
produced (defined in QqueueFields)QqueueFields
readIndex (defined in QqueueFields)QqueueFields
writeIndex (defined in QqueueFields)QqueueFields
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QqueueFields Struct Reference
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+uint16_t readIndex
 
+uint16_t writeIndex
 
+uint16_t produced
 
+uint16_t consumed
 
+Qval data [1]
 
+
The documentation for this struct was generated from the following file: +
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m_col (defined in Qval)Qval
m_u (defined in Qval)Qval
m_v (defined in Qval)Qval
m_y (defined in Qval)Qval
+ +
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+ + diff --git a/struct_qval.html b/struct_qval.html new file mode 100644 index 0000000..ad95388 --- /dev/null +++ b/struct_qval.html @@ -0,0 +1,121 @@ + + + + + + +discoverpixy: Qval Struct Reference + + + + + + + + + + +
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Qval Struct Reference
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+Public Attributes

+uint16_t m_col
 
+int16_t m_v
 
+int16_t m_u
 
+uint16_t m_y
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_c_c___clocks_type_def-members.html b/struct_r_c_c___clocks_type_def-members.html new file mode 100644 index 0000000..9030a7f --- /dev/null +++ b/struct_r_c_c___clocks_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RCC_ClocksTypeDef Member List
+
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+ +

This is the complete list of members for RCC_ClocksTypeDef, including all inherited members.

+ + + + + +
HCLK_FrequencyRCC_ClocksTypeDef
PCLK1_FrequencyRCC_ClocksTypeDef
PCLK2_FrequencyRCC_ClocksTypeDef
SYSCLK_FrequencyRCC_ClocksTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_c_c___clocks_type_def.html b/struct_r_c_c___clocks_type_def.html new file mode 100644 index 0000000..fb5a2c2 --- /dev/null +++ b/struct_r_c_c___clocks_type_def.html @@ -0,0 +1,170 @@ + + + + + + +discoverpixy: RCC_ClocksTypeDef Struct Reference + + + + + + + + + + +
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RCC_ClocksTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » RCC
+
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+ + + + + + + + + + +

+Public Attributes

uint32_t SYSCLK_Frequency
 
uint32_t HCLK_Frequency
 
uint32_t PCLK1_Frequency
 
uint32_t PCLK2_Frequency
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t RCC_ClocksTypeDef::HCLK_Frequency
+
+

HCLK clock frequency expressed in Hz

+ +
+
+ +
+
+ + + + +
uint32_t RCC_ClocksTypeDef::PCLK1_Frequency
+
+

PCLK1 clock frequency expressed in Hz

+ +
+
+ +
+
+ + + + +
uint32_t RCC_ClocksTypeDef::PCLK2_Frequency
+
+

PCLK2 clock frequency expressed in Hz

+ +
+
+ +
+
+ + + + +
uint32_t RCC_ClocksTypeDef::SYSCLK_Frequency
+
+

SYSCLK clock frequency expressed in Hz

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_c_c___type_def-members.html b/struct_r_c_c___type_def-members.html new file mode 100644 index 0000000..b459229 --- /dev/null +++ b/struct_r_c_c___type_def-members.html @@ -0,0 +1,134 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RCC_TypeDef Member List
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
AHB1ENRRCC_TypeDef
AHB1LPENRRCC_TypeDef
AHB1RSTRRCC_TypeDef
AHB2ENRRCC_TypeDef
AHB2LPENRRCC_TypeDef
AHB2RSTRRCC_TypeDef
AHB3ENRRCC_TypeDef
AHB3LPENRRCC_TypeDef
AHB3RSTRRCC_TypeDef
APB1ENRRCC_TypeDef
APB1LPENRRCC_TypeDef
APB1RSTRRCC_TypeDef
APB2ENRRCC_TypeDef
APB2LPENRRCC_TypeDef
APB2RSTRRCC_TypeDef
BDCRRCC_TypeDef
CFGRRCC_TypeDef
CIRRCC_TypeDef
CRRCC_TypeDef
CSRRCC_TypeDef
DCKCFGRRCC_TypeDef
PLLCFGRRCC_TypeDef
PLLI2SCFGRRCC_TypeDef
PLLSAICFGRRCC_TypeDef
RESERVED0RCC_TypeDef
RESERVED1RCC_TypeDef
RESERVED2RCC_TypeDef
RESERVED3RCC_TypeDef
RESERVED4RCC_TypeDef
RESERVED5RCC_TypeDef
RESERVED6RCC_TypeDef
SSCGRRCC_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_c_c___type_def.html b/struct_r_c_c___type_def.html new file mode 100644 index 0000000..e2a083c --- /dev/null +++ b/struct_r_c_c___type_def.html @@ -0,0 +1,180 @@ + + + + + + +discoverpixy: RCC_TypeDef Struct Reference + + + + + + + + + + +
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RCC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Reset and Clock Control. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t PLLCFGR
 
__IO uint32_t CFGR
 
__IO uint32_t CIR
 
__IO uint32_t AHB1RSTR
 
__IO uint32_t AHB2RSTR
 
__IO uint32_t AHB3RSTR
 
uint32_t RESERVED0
 
__IO uint32_t APB1RSTR
 
__IO uint32_t APB2RSTR
 
uint32_t RESERVED1 [2]
 
__IO uint32_t AHB1ENR
 
__IO uint32_t AHB2ENR
 
__IO uint32_t AHB3ENR
 
uint32_t RESERVED2
 
__IO uint32_t APB1ENR
 
__IO uint32_t APB2ENR
 
uint32_t RESERVED3 [2]
 
__IO uint32_t AHB1LPENR
 
__IO uint32_t AHB2LPENR
 
__IO uint32_t AHB3LPENR
 
uint32_t RESERVED4
 
__IO uint32_t APB1LPENR
 
__IO uint32_t APB2LPENR
 
uint32_t RESERVED5 [2]
 
__IO uint32_t BDCR
 
__IO uint32_t CSR
 
uint32_t RESERVED6 [2]
 
__IO uint32_t SSCGR
 
__IO uint32_t PLLI2SCFGR
 
__IO uint32_t PLLSAICFGR
 
__IO uint32_t DCKCFGR
 
+

Detailed Description

+

Reset and Clock Control.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_g_b_pixel-members.html b/struct_r_g_b_pixel-members.html new file mode 100644 index 0000000..a9aba09 --- /dev/null +++ b/struct_r_g_b_pixel-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RGBPixel Member List
+
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+ +

This is the complete list of members for RGBPixel, including all inherited members.

+ + + + + + + + +
m_b (defined in RGBPixel)RGBPixel
m_g (defined in RGBPixel)RGBPixel
m_r (defined in RGBPixel)RGBPixel
RGBPixel() (defined in RGBPixel)RGBPixelinline
RGBPixel(uint8_t r, uint8_t g, uint8_t b) (defined in RGBPixel)RGBPixelinline
RGBPixel() (defined in RGBPixel)RGBPixelinline
RGBPixel(uint8_t r, uint8_t g, uint8_t b) (defined in RGBPixel)RGBPixelinline
+ +
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+ + diff --git a/struct_r_g_b_pixel.html b/struct_r_g_b_pixel.html new file mode 100644 index 0000000..0f194c5 --- /dev/null +++ b/struct_r_g_b_pixel.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: RGBPixel Struct Reference + + + + + + + + + + +
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RGBPixel Struct Reference
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+Public Member Functions

+ RGBPixel (uint8_t r, uint8_t g, uint8_t b)
 
+ RGBPixel (uint8_t r, uint8_t g, uint8_t b)
 
+ + + + + + + +

+Public Attributes

+uint8_t m_r
 
+uint8_t m_g
 
+uint8_t m_b
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_n_g___type_def-members.html b/struct_r_n_g___type_def-members.html new file mode 100644 index 0000000..7dd2927 --- /dev/null +++ b/struct_r_n_g___type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RNG_TypeDef Member List
+
+
+ +

This is the complete list of members for RNG_TypeDef, including all inherited members.

+ + + + +
CRRNG_TypeDef
DRRNG_TypeDef
SRRNG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_n_g___type_def.html b/struct_r_n_g___type_def.html new file mode 100644 index 0000000..a7a229a --- /dev/null +++ b/struct_r_n_g___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: RNG_TypeDef Struct Reference + + + + + + + + + + +
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RNG_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

RNG. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t SR
 
__IO uint32_t DR
 
+

Detailed Description

+

RNG.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___alarm_type_def-members.html b/struct_r_t_c___alarm_type_def-members.html new file mode 100644 index 0000000..0b8878a --- /dev/null +++ b/struct_r_t_c___alarm_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RTC_AlarmTypeDef Member List
+
+
+ +

This is the complete list of members for RTC_AlarmTypeDef, including all inherited members.

+ + + + + +
RTC_AlarmDateWeekDayRTC_AlarmTypeDef
RTC_AlarmDateWeekDaySelRTC_AlarmTypeDef
RTC_AlarmMaskRTC_AlarmTypeDef
RTC_AlarmTimeRTC_AlarmTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___alarm_type_def.html b/struct_r_t_c___alarm_type_def.html new file mode 100644 index 0000000..3a81012 --- /dev/null +++ b/struct_r_t_c___alarm_type_def.html @@ -0,0 +1,184 @@ + + + + + + +discoverpixy: RTC_AlarmTypeDef Struct Reference + + + + + + + + + + +
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RTC_AlarmTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » RTC
+
+
+ +

RTC Alarm structure definition. + More...

+ +

#include <stm32f4xx_rtc.h>

+
+Collaboration diagram for RTC_AlarmTypeDef:
+
+
Collaboration graph
+ + +
[legend]
+ + + + + + + + + + +

+Public Attributes

RTC_TimeTypeDef RTC_AlarmTime
 
uint32_t RTC_AlarmMask
 
uint32_t RTC_AlarmDateWeekDaySel
 
uint8_t RTC_AlarmDateWeekDay
 
+

Detailed Description

+

RTC Alarm structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t RTC_AlarmTypeDef::RTC_AlarmDateWeekDay
+
+

Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of RTC_WeekDay_Definitions

+ +
+
+ +
+
+ + + + +
uint32_t RTC_AlarmTypeDef::RTC_AlarmDateWeekDaySel
+
+

Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of RTC_AlarmDateWeekDay_Definitions

+ +
+
+ +
+
+ + + + +
uint32_t RTC_AlarmTypeDef::RTC_AlarmMask
+
+

Specifies the RTC Alarm Masks. This parameter can be a value of RTC_AlarmMask_Definitions

+ +
+
+ +
+
+ + + + +
RTC_TimeTypeDef RTC_AlarmTypeDef::RTC_AlarmTime
+
+

Specifies the RTC Alarm Time members.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___alarm_type_def__coll__graph.map b/struct_r_t_c___alarm_type_def__coll__graph.map new file mode 100644 index 0000000..38f8550 --- /dev/null +++ b/struct_r_t_c___alarm_type_def__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_r_t_c___alarm_type_def__coll__graph.md5 b/struct_r_t_c___alarm_type_def__coll__graph.md5 new file mode 100644 index 0000000..7530bab --- /dev/null +++ b/struct_r_t_c___alarm_type_def__coll__graph.md5 @@ -0,0 +1 @@ +f735029b890b51abec2bcb774b8b544b \ No newline at end of file diff --git a/struct_r_t_c___alarm_type_def__coll__graph.png b/struct_r_t_c___alarm_type_def__coll__graph.png new file mode 100644 index 0000000..9f25990 Binary files /dev/null and b/struct_r_t_c___alarm_type_def__coll__graph.png differ diff --git a/struct_r_t_c___date_type_def-members.html b/struct_r_t_c___date_type_def-members.html new file mode 100644 index 0000000..e5bcce0 --- /dev/null +++ b/struct_r_t_c___date_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RTC_DateTypeDef Member List
+
+
+ +

This is the complete list of members for RTC_DateTypeDef, including all inherited members.

+ + + + + +
RTC_DateRTC_DateTypeDef
RTC_MonthRTC_DateTypeDef
RTC_WeekDayRTC_DateTypeDef
RTC_YearRTC_DateTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___date_type_def.html b/struct_r_t_c___date_type_def.html new file mode 100644 index 0000000..0aa1a7c --- /dev/null +++ b/struct_r_t_c___date_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: RTC_DateTypeDef Struct Reference + + + + + + + + + + +
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RTC_DateTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » RTC
+
+
+ +

RTC Date structure definition. + More...

+ +

#include <stm32f4xx_rtc.h>

+ + + + + + + + + + +

+Public Attributes

uint8_t RTC_WeekDay
 
uint8_t RTC_Month
 
uint8_t RTC_Date
 
uint8_t RTC_Year
 
+

Detailed Description

+

RTC Date structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t RTC_DateTypeDef::RTC_Date
+
+

Specifies the RTC Date. This parameter must be set to a value in the 1-31 range.

+ +
+
+ +
+
+ + + + +
uint8_t RTC_DateTypeDef::RTC_Month
+
+

Specifies the RTC Date Month (in BCD format). This parameter can be a value of RTC_Month_Date_Definitions

+ +
+
+ +
+
+ + + + +
uint8_t RTC_DateTypeDef::RTC_WeekDay
+
+

Specifies the RTC Date WeekDay. This parameter can be a value of RTC_WeekDay_Definitions

+ +
+
+ +
+
+ + + + +
uint8_t RTC_DateTypeDef::RTC_Year
+
+

Specifies the RTC Date Year. This parameter must be set to a value in the 0-99 range.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___init_type_def-members.html b/struct_r_t_c___init_type_def-members.html new file mode 100644 index 0000000..3c67d49 --- /dev/null +++ b/struct_r_t_c___init_type_def-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RTC_InitTypeDef Member List
+
+
+ +

This is the complete list of members for RTC_InitTypeDef, including all inherited members.

+ + + + +
RTC_AsynchPredivRTC_InitTypeDef
RTC_HourFormatRTC_InitTypeDef
RTC_SynchPredivRTC_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___init_type_def.html b/struct_r_t_c___init_type_def.html new file mode 100644 index 0000000..4dcd50c --- /dev/null +++ b/struct_r_t_c___init_type_def.html @@ -0,0 +1,162 @@ + + + + + + +discoverpixy: RTC_InitTypeDef Struct Reference + + + + + + + + + + +
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RTC_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » RTC
+
+
+ +

RTC Init structures definition. + More...

+ +

#include <stm32f4xx_rtc.h>

+ + + + + + + + +

+Public Attributes

uint32_t RTC_HourFormat
 
uint32_t RTC_AsynchPrediv
 
uint32_t RTC_SynchPrediv
 
+

Detailed Description

+

RTC Init structures definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t RTC_InitTypeDef::RTC_AsynchPrediv
+
+

Specifies the RTC Asynchronous Predivider value. This parameter must be set to a value lower than 0x7F

+ +
+
+ +
+
+ + + + +
uint32_t RTC_InitTypeDef::RTC_HourFormat
+
+

Specifies the RTC Hour Format. This parameter can be a value of RTC_Hour_Formats

+ +
+
+ +
+
+ + + + +
uint32_t RTC_InitTypeDef::RTC_SynchPrediv
+
+

Specifies the RTC Synchronous Predivider value. This parameter must be set to a value lower than 0x7FFF

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___time_type_def-members.html b/struct_r_t_c___time_type_def-members.html new file mode 100644 index 0000000..7783446 --- /dev/null +++ b/struct_r_t_c___time_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RTC_TimeTypeDef Member List
+
+
+ +

This is the complete list of members for RTC_TimeTypeDef, including all inherited members.

+ + + + + +
RTC_H12RTC_TimeTypeDef
RTC_HoursRTC_TimeTypeDef
RTC_MinutesRTC_TimeTypeDef
RTC_SecondsRTC_TimeTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___time_type_def.html b/struct_r_t_c___time_type_def.html new file mode 100644 index 0000000..6c35b55 --- /dev/null +++ b/struct_r_t_c___time_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: RTC_TimeTypeDef Struct Reference + + + + + + + + + + +
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RTC_TimeTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » RTC
+
+
+ +

RTC Time structure definition. + More...

+ +

#include <stm32f4xx_rtc.h>

+ + + + + + + + + + +

+Public Attributes

uint8_t RTC_Hours
 
uint8_t RTC_Minutes
 
uint8_t RTC_Seconds
 
uint8_t RTC_H12
 
+

Detailed Description

+

RTC Time structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint8_t RTC_TimeTypeDef::RTC_H12
+
+

Specifies the RTC AM/PM Time. This parameter can be a value of RTC_AM_PM_Definitions

+ +
+
+ +
+
+ + + + +
uint8_t RTC_TimeTypeDef::RTC_Hours
+
+

Specifies the RTC Time Hour. This parameter must be set to a value in the 0-12 range if the RTC_HourFormat_12 is selected or 0-23 range if the RTC_HourFormat_24 is selected.

+ +
+
+ +
+
+ + + + +
uint8_t RTC_TimeTypeDef::RTC_Minutes
+
+

Specifies the RTC Time Minutes. This parameter must be set to a value in the 0-59 range.

+ +
+
+ +
+
+ + + + +
uint8_t RTC_TimeTypeDef::RTC_Seconds
+
+

Specifies the RTC Time Seconds. This parameter must be set to a value in the 0-59 range.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___type_def-members.html b/struct_r_t_c___type_def-members.html new file mode 100644 index 0000000..00a58c6 --- /dev/null +++ b/struct_r_t_c___type_def-members.html @@ -0,0 +1,142 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RTC_TypeDef Member List
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ALRMARRTC_TypeDef
ALRMASSRRTC_TypeDef
ALRMBRRTC_TypeDef
ALRMBSSRRTC_TypeDef
BKP0RRTC_TypeDef
BKP10RRTC_TypeDef
BKP11RRTC_TypeDef
BKP12RRTC_TypeDef
BKP13RRTC_TypeDef
BKP14RRTC_TypeDef
BKP15RRTC_TypeDef
BKP16RRTC_TypeDef
BKP17RRTC_TypeDef
BKP18RRTC_TypeDef
BKP19RRTC_TypeDef
BKP1RRTC_TypeDef
BKP2RRTC_TypeDef
BKP3RRTC_TypeDef
BKP4RRTC_TypeDef
BKP5RRTC_TypeDef
BKP6RRTC_TypeDef
BKP7RRTC_TypeDef
BKP8RRTC_TypeDef
BKP9RRTC_TypeDef
CALIBRRTC_TypeDef
CALRRTC_TypeDef
CRRTC_TypeDef
DRRTC_TypeDef
ISRRTC_TypeDef
PRERRTC_TypeDef
RESERVED7RTC_TypeDef
SHIFTRRTC_TypeDef
SSRRTC_TypeDef
TAFCRRTC_TypeDef
TRRTC_TypeDef
TSDRRTC_TypeDef
TSSSRRTC_TypeDef
TSTRRTC_TypeDef
WPRRTC_TypeDef
WUTRRTC_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_r_t_c___type_def.html b/struct_r_t_c___type_def.html new file mode 100644 index 0000000..348409a --- /dev/null +++ b/struct_r_t_c___type_def.html @@ -0,0 +1,196 @@ + + + + + + +discoverpixy: RTC_TypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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RTC_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Real-Time Clock. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t TR
 
__IO uint32_t DR
 
__IO uint32_t CR
 
__IO uint32_t ISR
 
__IO uint32_t PRER
 
__IO uint32_t WUTR
 
__IO uint32_t CALIBR
 
__IO uint32_t ALRMAR
 
__IO uint32_t ALRMBR
 
__IO uint32_t WPR
 
__IO uint32_t SSR
 
__IO uint32_t SHIFTR
 
__IO uint32_t TSTR
 
__IO uint32_t TSDR
 
__IO uint32_t TSSSR
 
__IO uint32_t CALR
 
__IO uint32_t TAFCR
 
__IO uint32_t ALRMASSR
 
__IO uint32_t ALRMBSSR
 
uint32_t RESERVED7
 
__IO uint32_t BKP0R
 
__IO uint32_t BKP1R
 
__IO uint32_t BKP2R
 
__IO uint32_t BKP3R
 
__IO uint32_t BKP4R
 
__IO uint32_t BKP5R
 
__IO uint32_t BKP6R
 
__IO uint32_t BKP7R
 
__IO uint32_t BKP8R
 
__IO uint32_t BKP9R
 
__IO uint32_t BKP10R
 
__IO uint32_t BKP11R
 
__IO uint32_t BKP12R
 
__IO uint32_t BKP13R
 
__IO uint32_t BKP14R
 
__IO uint32_t BKP15R
 
__IO uint32_t BKP16R
 
__IO uint32_t BKP17R
 
__IO uint32_t BKP18R
 
__IO uint32_t BKP19R
 
+

Detailed Description

+

Real-Time Clock.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_rect_a-members.html b/struct_rect_a-members.html new file mode 100644 index 0000000..76f1fc2 --- /dev/null +++ b/struct_rect_a-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RectA Member List
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This is the complete list of members for RectA, including all inherited members.

+ + + + + + + + + +
m_height (defined in RectA)RectA
m_width (defined in RectA)RectA
m_xOffset (defined in RectA)RectA
m_yOffset (defined in RectA)RectA
RectA() (defined in RectA)RectAinline
RectA(uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height) (defined in RectA)RectAinline
RectA() (defined in RectA)RectAinline
RectA(uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height) (defined in RectA)RectAinline
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_rect_a.html b/struct_rect_a.html new file mode 100644 index 0000000..314f0e2 --- /dev/null +++ b/struct_rect_a.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: RectA Struct Reference + + + + + + + + + + +
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RectA Struct Reference
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+Public Member Functions

+ RectA (uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height)
 
+ RectA (uint16_t xOffset, uint16_t yOffset, uint16_t width, uint16_t height)
 
+ + + + + + + + + +

+Public Attributes

+uint16_t m_xOffset
 
+uint16_t m_yOffset
 
+uint16_t m_width
 
+uint16_t m_height
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_rect_b-members.html b/struct_rect_b-members.html new file mode 100644 index 0000000..61499ac --- /dev/null +++ b/struct_rect_b-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RectB Member List
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This is the complete list of members for RectB, including all inherited members.

+ + + + + + + + + +
m_bottom (defined in RectB)RectB
m_left (defined in RectB)RectB
m_right (defined in RectB)RectB
m_top (defined in RectB)RectB
RectB() (defined in RectB)RectBinline
RectB(uint16_t left, uint16_t right, uint16_t top, uint16_t bottom) (defined in RectB)RectBinline
RectB() (defined in RectB)RectBinline
RectB(uint16_t left, uint16_t right, uint16_t top, uint16_t bottom) (defined in RectB)RectBinline
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_rect_b.html b/struct_rect_b.html new file mode 100644 index 0000000..92bbecc --- /dev/null +++ b/struct_rect_b.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: RectB Struct Reference + + + + + + + + + + +
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+Public Member Functions | +Public Attributes | +List of all members
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RectB Struct Reference
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+Public Member Functions

+ RectB (uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
 
+ RectB (uint16_t left, uint16_t right, uint16_t top, uint16_t bottom)
 
+ + + + + + + + + +

+Public Attributes

+uint16_t m_left
 
+uint16_t m_right
 
+uint16_t m_top
 
+uint16_t m_bottom
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_runtime_signature-members.html b/struct_runtime_signature-members.html new file mode 100644 index 0000000..9c80a2e --- /dev/null +++ b/struct_runtime_signature-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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RuntimeSignature Member List
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This is the complete list of members for RuntimeSignature, including all inherited members.

+ + + + + + +
m_rgbSat (defined in RuntimeSignature)RuntimeSignature
m_uMax (defined in RuntimeSignature)RuntimeSignature
m_uMin (defined in RuntimeSignature)RuntimeSignature
m_vMax (defined in RuntimeSignature)RuntimeSignature
m_vMin (defined in RuntimeSignature)RuntimeSignature
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_runtime_signature.html b/struct_runtime_signature.html new file mode 100644 index 0000000..22c692e --- /dev/null +++ b/struct_runtime_signature.html @@ -0,0 +1,124 @@ + + + + + + +discoverpixy: RuntimeSignature Struct Reference + + + + + + + + + + +
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RuntimeSignature Struct Reference
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+Public Attributes

+int32_t m_uMin
 
+int32_t m_uMax
 
+int32_t m_vMin
 
+int32_t m_vMax
 
+uint32_t m_rgbSat
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___block___type_def-members.html b/struct_s_a_i___block___type_def-members.html new file mode 100644 index 0000000..5092951 --- /dev/null +++ b/struct_s_a_i___block___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
SAI_Block_TypeDef Member List
+
+
+ +

This is the complete list of members for SAI_Block_TypeDef, including all inherited members.

+ + + + + + + + + +
CLRFRSAI_Block_TypeDef
CR1SAI_Block_TypeDef
CR2SAI_Block_TypeDef
DRSAI_Block_TypeDef
FRCRSAI_Block_TypeDef
IMRSAI_Block_TypeDef
SLOTRSAI_Block_TypeDef
SRSAI_Block_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___block___type_def.html b/struct_s_a_i___block___type_def.html new file mode 100644 index 0000000..9480364 --- /dev/null +++ b/struct_s_a_i___block___type_def.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: SAI_Block_TypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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SAI_Block_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t CR1
 
__IO uint32_t CR2
 
__IO uint32_t FRCR
 
__IO uint32_t SLOTR
 
__IO uint32_t IMR
 
__IO uint32_t SR
 
__IO uint32_t CLRFR
 
__IO uint32_t DR
 
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___frame_init_type_def-members.html b/struct_s_a_i___frame_init_type_def-members.html new file mode 100644 index 0000000..7d19bbb --- /dev/null +++ b/struct_s_a_i___frame_init_type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
SAI_FrameInitTypeDef Member List
+
+
+ +

This is the complete list of members for SAI_FrameInitTypeDef, including all inherited members.

+ + + + + + +
SAI_ActiveFrameLengthSAI_FrameInitTypeDef
SAI_FrameLengthSAI_FrameInitTypeDef
SAI_FSDefinitionSAI_FrameInitTypeDef
SAI_FSOffsetSAI_FrameInitTypeDef
SAI_FSPolaritySAI_FrameInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___frame_init_type_def.html b/struct_s_a_i___frame_init_type_def.html new file mode 100644 index 0000000..f03cc9a --- /dev/null +++ b/struct_s_a_i___frame_init_type_def.html @@ -0,0 +1,194 @@ + + + + + + +discoverpixy: SAI_FrameInitTypeDef Struct Reference + + + + + + + + + + +
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SAI_FrameInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SAI
+
+
+ +

SAI Block Frame Init structure definition. + More...

+ +

#include <stm32f4xx_sai.h>

+ + + + + + + + + + + + +

+Public Attributes

uint32_t SAI_FrameLength
 
uint32_t SAI_ActiveFrameLength
 
uint32_t SAI_FSDefinition
 
uint32_t SAI_FSPolarity
 
uint32_t SAI_FSOffset
 
+

Detailed Description

+

SAI Block Frame Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SAI_FrameInitTypeDef::SAI_ActiveFrameLength
+
+

Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between 1 and 128.

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_FrameInitTypeDef::SAI_FrameLength
+
+

Specifies the Frame Length, the number of SCK clocks for each audio frame. This parameter must be a number between 8 and 256.

Note
If master Clock MCLK_x pin is declared as an output, the frame length should be Aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock.
+
+this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_FrameInitTypeDef::SAI_FSDefinition
+
+

Specifies the Frame Synchronization definition. This parameter can be a value of SAI_Block_FS_Definition

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_FrameInitTypeDef::SAI_FSOffset
+
+

Specifies the Frame Synchronization Offset. This parameter can be a value of SAI_Block_FS_Offset

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_FrameInitTypeDef::SAI_FSPolarity
+
+

Specifies the Frame Synchronization Polarity. This parameter can be a value of SAI_Block_FS_Polarity

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___init_type_def-members.html b/struct_s_a_i___init_type_def-members.html new file mode 100644 index 0000000..4aa4333 --- /dev/null +++ b/struct_s_a_i___init_type_def-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SAI_InitTypeDef Member List
+
+
+ +

This is the complete list of members for SAI_InitTypeDef, including all inherited members.

+ + + + + + + + + + + +
SAI_AudioModeSAI_InitTypeDef
SAI_ClockStrobingSAI_InitTypeDef
SAI_DataSizeSAI_InitTypeDef
SAI_FIFOThresholdSAI_InitTypeDef
SAI_FirstBitSAI_InitTypeDef
SAI_MasterDividerSAI_InitTypeDef
SAI_NoDividerSAI_InitTypeDef
SAI_OUTDRIVSAI_InitTypeDef
SAI_ProtocolSAI_InitTypeDef
SAI_SynchroSAI_InitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___init_type_def.html b/struct_s_a_i___init_type_def.html new file mode 100644 index 0000000..37a7950 --- /dev/null +++ b/struct_s_a_i___init_type_def.html @@ -0,0 +1,267 @@ + + + + + + +discoverpixy: SAI_InitTypeDef Struct Reference + + + + + + + + + + +
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SAI_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SAI
+
+
+ +

SAI Block Init structure definition. + More...

+ +

#include <stm32f4xx_sai.h>

+ + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint32_t SAI_AudioMode
 
uint32_t SAI_Protocol
 
uint32_t SAI_DataSize
 
uint32_t SAI_FirstBit
 
uint32_t SAI_ClockStrobing
 
uint32_t SAI_Synchro
 
uint32_t SAI_OUTDRIV
 
uint32_t SAI_NoDivider
 
uint32_t SAI_MasterDivider
 
uint32_t SAI_FIFOThreshold
 
+

Detailed Description

+

SAI Block Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_AudioMode
+
+

Specifies the SAI Block Audio Mode. This parameter can be a value of SAI_Block_Mode

+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_ClockStrobing
+
+

Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of SAI_Block_Clock_Strobing

+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_DataSize
+
+

Specifies the SAI Block data size. This parameter can be a value of SAI_Block_Data_Size

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_FIFOThreshold
+
+

Specifies SAI Block FIFO Threshold. This parameter can be a value of SAI_Block_Fifo_Threshold

+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_FirstBit
+
+

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SAI_Block_MSB_LSB_transmission

Note
this value has no meaning when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_MasterDivider
+
+

Specifies SAI Block Master Clock Divider.

Note
the Master Clock Frequency is calculated accordingly to the following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)
+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_NoDivider
+
+

Specifies whether Master Clock will be divided or not. This parameter can be a value of SAI_Block_NoDivider

+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_OUTDRIV
+
+

Specifies when SAI Block outputs are driven. This parameter can be a value of SAI_Block_Output_Drive

Note
this value has to be set before enabling the audio block but after the audio block configuration.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_Protocol
+
+

Specifies the SAI Block Protocol. This parameter can be a value of SAI_Block_Protocol

+ +
+
+ +
+
+ + + + +
uint32_t SAI_InitTypeDef::SAI_Synchro
+
+

Specifies SAI Block synchronization This parameter can be a value of SAI_Block_Synchronization

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___slot_init_type_def-members.html b/struct_s_a_i___slot_init_type_def-members.html new file mode 100644 index 0000000..e0e4b5f --- /dev/null +++ b/struct_s_a_i___slot_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SAI_SlotInitTypeDef Member List
+
+
+ +

This is the complete list of members for SAI_SlotInitTypeDef, including all inherited members.

+ + + + + +
SAI_FirstBitOffsetSAI_SlotInitTypeDef
SAI_SlotActiveSAI_SlotInitTypeDef
SAI_SlotNumberSAI_SlotInitTypeDef
SAI_SlotSizeSAI_SlotInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___slot_init_type_def.html b/struct_s_a_i___slot_init_type_def.html new file mode 100644 index 0000000..ce653c5 --- /dev/null +++ b/struct_s_a_i___slot_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: SAI_SlotInitTypeDef Struct Reference + + + + + + + + + + +
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SAI_SlotInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SAI
+
+
+ +

SAI Block Slot Init Structure definition. + More...

+ +

#include <stm32f4xx_sai.h>

+ + + + + + + + + + +

+Public Attributes

uint32_t SAI_FirstBitOffset
 
uint32_t SAI_SlotSize
 
uint32_t SAI_SlotNumber
 
uint32_t SAI_SlotActive
 
+

Detailed Description

+

SAI Block Slot Init Structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SAI_SlotInitTypeDef::SAI_FirstBitOffset
+
+

Specifies the position of first data transfer bit in the slot. This parameter must be a number between 0 and 24.

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_SlotInitTypeDef::SAI_SlotActive
+
+

Specifies the slots in audio frame that will be activated. This parameter can be a value of @ ref SAI_Block_Slot_Active

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_SlotInitTypeDef::SAI_SlotNumber
+
+

Specifies the number of slot in the audio frame. This parameter must be a number between 1 and 16.

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+ +
+
+ + + + +
uint32_t SAI_SlotInitTypeDef::SAI_SlotSize
+
+

Specifies the Slot Size. This parameter can be a value of SAI_Block_Slot_Size

Note
this value is ignored when AC'97 or SPDIF protocols are selected.
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___type_def-members.html b/struct_s_a_i___type_def-members.html new file mode 100644 index 0000000..df0acab --- /dev/null +++ b/struct_s_a_i___type_def-members.html @@ -0,0 +1,103 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SAI_TypeDef Member List
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This is the complete list of members for SAI_TypeDef, including all inherited members.

+ + +
GCRSAI_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_a_i___type_def.html b/struct_s_a_i___type_def.html new file mode 100644 index 0000000..dc05540 --- /dev/null +++ b/struct_s_a_i___type_def.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: SAI_TypeDef Struct Reference + + + + + + + + + + +
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SAI_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Serial Audio Interface. + More...

+ +

#include <stm32f4xx.h>

+ + + + +

+Public Attributes

__IO uint32_t GCR
 
+

Detailed Description

+

Serial Audio Interface.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_c_b___type-members.html b/struct_s_c_b___type-members.html new file mode 100644 index 0000000..71232bd --- /dev/null +++ b/struct_s_c_b___type-members.html @@ -0,0 +1,123 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SCB_Type Member List
+
+
+ +

This is the complete list of members for SCB_Type, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + +
ADRSCB_Type
AFSRSCB_Type
AIRCRSCB_Type
BFARSCB_Type
CCRSCB_Type
CFSRSCB_Type
CPACRSCB_Type
CPUIDSCB_Type
DFRSCB_Type
DFSRSCB_Type
HFSRSCB_Type
ICSRSCB_Type
ISARSCB_Type
MMFARSCB_Type
MMFRSCB_Type
PFRSCB_Type
RESERVED0 (defined in SCB_Type)SCB_Type
SCRSCB_Type
SHCSRSCB_Type
SHPSCB_Type
VTORSCB_Type
+ +
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+ + diff --git a/struct_s_c_b___type.html b/struct_s_c_b___type.html new file mode 100644 index 0000000..7ae3008 --- /dev/null +++ b/struct_s_c_b___type.html @@ -0,0 +1,420 @@ + + + + + + +discoverpixy: SCB_Type Struct Reference + + + + + + + + + + +
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SCB_Type Struct Reference
Defines and Type Definitions » System Control Block (SCB)
+
+
+ +

Structure type to access the System Control Block (SCB). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__I uint32_t CPUID
 
__IO uint32_t ICSR
 
__IO uint32_t VTOR
 
__IO uint32_t AIRCR
 
__IO uint32_t SCR
 
__IO uint32_t CCR
 
__IO uint8_t SHP [12]
 
__IO uint32_t SHCSR
 
__IO uint32_t CFSR
 
__IO uint32_t HFSR
 
__IO uint32_t DFSR
 
__IO uint32_t MMFAR
 
__IO uint32_t BFAR
 
__IO uint32_t AFSR
 
__I uint32_t PFR [2]
 
__I uint32_t DFR
 
__I uint32_t ADR
 
__I uint32_t MMFR [4]
 
__I uint32_t ISAR [5]
 
+uint32_t RESERVED0 [5]
 
__IO uint32_t CPACR
 
+

Detailed Description

+

Structure type to access the System Control Block (SCB).

+

Member Data Documentation

+ +
+
+ + + + +
__I uint32_t SCB_Type::ADR
+
+

Offset: 0x04C (R/ ) Auxiliary Feature Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::AFSR
+
+

Offset: 0x03C (R/W) Auxiliary Fault Status Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::AIRCR
+
+

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::BFAR
+
+

Offset: 0x038 (R/W) BusFault Address Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CCR
+
+

Offset: 0x014 (R/W) Configuration Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CFSR
+
+

Offset: 0x028 (R/W) Configurable Fault Status Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::CPACR
+
+

Offset: 0x088 (R/W) Coprocessor Access Control Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::CPUID
+
+

Offset: 0x000 (R/ ) CPUID Base Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::DFR
+
+

Offset: 0x048 (R/ ) Debug Feature Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::DFSR
+
+

Offset: 0x030 (R/W) Debug Fault Status Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::HFSR
+
+

Offset: 0x02C (R/W) HardFault Status Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::ICSR
+
+

Offset: 0x004 (R/W) Interrupt Control and State Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::ISAR[5]
+
+

Offset: 0x060 (R/ ) Instruction Set Attributes Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::MMFAR
+
+

Offset: 0x034 (R/W) MemManage Fault Address Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::MMFR[4]
+
+

Offset: 0x050 (R/ ) Memory Model Feature Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCB_Type::PFR[2]
+
+

Offset: 0x040 (R/ ) Processor Feature Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::SCR
+
+

Offset: 0x010 (R/W) System Control Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::SHCSR
+
+

Offset: 0x024 (R/W) System Handler Control and State Register

+ +
+
+ +
+
+ + + + +
__IO uint8_t SCB_Type::SHP[12]
+
+

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

+ +
+
+ +
+
+ + + + +
__IO uint32_t SCB_Type::VTOR
+
+

Offset: 0x008 (R/W) Vector Table Offset Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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This is the complete list of members for SCREEN_S, including all inherited members.

+ + + + + +
next (defined in SCREEN_S)SCREEN_S
on_enter (defined in SCREEN_S)SCREEN_S
on_leave (defined in SCREEN_S)SCREEN_S
on_update (defined in SCREEN_S)SCREEN_S
+ +
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+Data Fields
+
+
SCREEN_S Struct Reference
Gui » Screen
+
+
+ +

#include <screen.h>

+
+Collaboration diagram for SCREEN_S:
+
+
Collaboration graph
+
[legend]
+ + + + + + + + + + +

+Data Fields

SCREEN_CALLBACK on_enter
 
SCREEN_CALLBACK on_leave
 
SCREEN_CALLBACK on_update
 
struct SCREEN_S * next
 
+
The documentation for this struct was generated from the following file: +
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+ + diff --git a/struct_s_c_r_e_e_n___s__coll__graph.map b/struct_s_c_r_e_e_n___s__coll__graph.map new file mode 100644 index 0000000..7649de4 --- /dev/null +++ b/struct_s_c_r_e_e_n___s__coll__graph.map @@ -0,0 +1,2 @@ + + diff --git a/struct_s_c_r_e_e_n___s__coll__graph.md5 b/struct_s_c_r_e_e_n___s__coll__graph.md5 new file mode 100644 index 0000000..bd46937 --- /dev/null +++ b/struct_s_c_r_e_e_n___s__coll__graph.md5 @@ -0,0 +1 @@ +39965adfd89384552de2ccf4090fdf85 \ No newline at end of file diff --git a/struct_s_c_r_e_e_n___s__coll__graph.png b/struct_s_c_r_e_e_n___s__coll__graph.png new file mode 100644 index 0000000..623c6f4 Binary files /dev/null and b/struct_s_c_r_e_e_n___s__coll__graph.png differ diff --git a/struct_s_cn_s_c_b___type-members.html b/struct_s_cn_s_c_b___type-members.html new file mode 100644 index 0000000..3485928 --- /dev/null +++ b/struct_s_cn_s_c_b___type-members.html @@ -0,0 +1,105 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SCnSCB_Type Member List
+
+
+ +

This is the complete list of members for SCnSCB_Type, including all inherited members.

+ + + + +
ACTLRSCnSCB_Type
ICTRSCnSCB_Type
RESERVED0 (defined in SCnSCB_Type)SCnSCB_Type
+ +
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SCnSCB_Type Struct Reference
Defines and Type Definitions » System Controls not in SCB (SCnSCB)
+
+
+ +

Structure type to access the System Control and ID Register not in the SCB. + More...

+ +

#include <core_cm4.h>

+ + + + + + + + +

+Public Attributes

+uint32_t RESERVED0 [1]
 
__I uint32_t ICTR
 
__IO uint32_t ACTLR
 
+

Detailed Description

+

Structure type to access the System Control and ID Register not in the SCB.

+

Member Data Documentation

+ +
+
+ + + + +
__IO uint32_t SCnSCB_Type::ACTLR
+
+

Offset: 0x008 (R/W) Auxiliary Control Register

+ +
+
+ +
+
+ + + + +
__I uint32_t SCnSCB_Type::ICTR
+
+

Offset: 0x004 (R/ ) Interrupt Controller Type Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_s_d_i_o___cmd_init_type_def-members.html b/struct_s_d_i_o___cmd_init_type_def-members.html new file mode 100644 index 0000000..22b8ef5 --- /dev/null +++ b/struct_s_d_i_o___cmd_init_type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SDIO_CmdInitTypeDef Member List
+
+
+ +

This is the complete list of members for SDIO_CmdInitTypeDef, including all inherited members.

+ + + + + + +
SDIO_ArgumentSDIO_CmdInitTypeDef
SDIO_CmdIndexSDIO_CmdInitTypeDef
SDIO_CPSMSDIO_CmdInitTypeDef
SDIO_ResponseSDIO_CmdInitTypeDef
SDIO_WaitSDIO_CmdInitTypeDef
+ +
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SDIO_CmdInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SDIO
+
+
+ + + + + + + + + + + + +

+Public Attributes

uint32_t SDIO_Argument
 
uint32_t SDIO_CmdIndex
 
uint32_t SDIO_Response
 
uint32_t SDIO_Wait
 
uint32_t SDIO_CPSM
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SDIO_CmdInitTypeDef::SDIO_Argument
+
+

Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_CmdInitTypeDef::SDIO_CmdIndex
+
+

Specifies the SDIO command index. It must be lower than 0x40.

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_CmdInitTypeDef::SDIO_CPSM
+
+

Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of SDIO_CPSM_State

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_CmdInitTypeDef::SDIO_Response
+
+

Specifies the SDIO response type. This parameter can be a value of SDIO_Response_Type

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_CmdInitTypeDef::SDIO_Wait
+
+

Specifies whether SDIO wait for interrupt request is enabled or disabled. This parameter can be a value of SDIO_Wait_Interrupt_State

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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SDIO_DataInitTypeDef Member List
+
+
+ +

This is the complete list of members for SDIO_DataInitTypeDef, including all inherited members.

+ + + + + + + +
SDIO_DataBlockSizeSDIO_DataInitTypeDef
SDIO_DataLengthSDIO_DataInitTypeDef
SDIO_DataTimeOutSDIO_DataInitTypeDef
SDIO_DPSMSDIO_DataInitTypeDef
SDIO_TransferDirSDIO_DataInitTypeDef
SDIO_TransferModeSDIO_DataInitTypeDef
+ +
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+ + diff --git a/struct_s_d_i_o___data_init_type_def.html b/struct_s_d_i_o___data_init_type_def.html new file mode 100644 index 0000000..02dc093 --- /dev/null +++ b/struct_s_d_i_o___data_init_type_def.html @@ -0,0 +1,200 @@ + + + + + + +discoverpixy: SDIO_DataInitTypeDef Struct Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
+
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SDIO_DataInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SDIO
+
+
+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t SDIO_DataTimeOut
 
uint32_t SDIO_DataLength
 
uint32_t SDIO_DataBlockSize
 
uint32_t SDIO_TransferDir
 
uint32_t SDIO_TransferMode
 
uint32_t SDIO_DPSM
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_DataBlockSize
+
+

Specifies the data block size for block transfer. This parameter can be a value of SDIO_Data_Block_Size

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_DataLength
+
+

Specifies the number of data bytes to be transferred.

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_DataTimeOut
+
+

Specifies the data timeout period in card bus clock periods.

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_DPSM
+
+

Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of SDIO_DPSM_State

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_TransferDir
+
+

Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of SDIO_Transfer_Direction

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_DataInitTypeDef::SDIO_TransferMode
+
+

Specifies whether data transfer is in stream or block mode. This parameter can be a value of SDIO_Transfer_Type

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_s_d_i_o___init_type_def-members.html b/struct_s_d_i_o___init_type_def-members.html new file mode 100644 index 0000000..72e3f39 --- /dev/null +++ b/struct_s_d_i_o___init_type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SDIO_InitTypeDef Member List
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This is the complete list of members for SDIO_InitTypeDef, including all inherited members.

+ + + + + + + +
SDIO_BusWideSDIO_InitTypeDef
SDIO_ClockBypassSDIO_InitTypeDef
SDIO_ClockDivSDIO_InitTypeDef
SDIO_ClockEdgeSDIO_InitTypeDef
SDIO_ClockPowerSaveSDIO_InitTypeDef
SDIO_HardwareFlowControlSDIO_InitTypeDef
+ +
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SDIO_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SDIO
+
+
+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t SDIO_ClockEdge
 
uint32_t SDIO_ClockBypass
 
uint32_t SDIO_ClockPowerSave
 
uint32_t SDIO_BusWide
 
uint32_t SDIO_HardwareFlowControl
 
uint8_t SDIO_ClockDiv
 
+

Member Data Documentation

+ +
+
+ + + + +
uint32_t SDIO_InitTypeDef::SDIO_BusWide
+
+

Specifies the SDIO bus width. This parameter can be a value of SDIO_Bus_Wide

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_InitTypeDef::SDIO_ClockBypass
+
+

Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of SDIO_Clock_Bypass

+ +
+
+ +
+
+ + + + +
uint8_t SDIO_InitTypeDef::SDIO_ClockDiv
+
+

Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF.

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_InitTypeDef::SDIO_ClockEdge
+
+

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SDIO_Clock_Edge

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_InitTypeDef::SDIO_ClockPowerSave
+
+

Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of SDIO_Clock_Power_Save

+ +
+
+ +
+
+ + + + +
uint32_t SDIO_InitTypeDef::SDIO_HardwareFlowControl
+
+

Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of SDIO_Hardware_Flow_Control

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
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+ + diff --git a/struct_s_d_i_o___type_def-members.html b/struct_s_d_i_o___type_def-members.html new file mode 100644 index 0000000..9376729 --- /dev/null +++ b/struct_s_d_i_o___type_def-members.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+ + + + + + + + + + + + + + + + + + + + + +
ARGSDIO_TypeDef
CLKCRSDIO_TypeDef
CMDSDIO_TypeDef
DCOUNTSDIO_TypeDef
DCTRLSDIO_TypeDef
DLENSDIO_TypeDef
DTIMERSDIO_TypeDef
FIFOSDIO_TypeDef
FIFOCNTSDIO_TypeDef
ICRSDIO_TypeDef
MASKSDIO_TypeDef
POWERSDIO_TypeDef
RESERVED0SDIO_TypeDef
RESERVED1SDIO_TypeDef
RESP1SDIO_TypeDef
RESP2SDIO_TypeDef
RESP3SDIO_TypeDef
RESP4SDIO_TypeDef
RESPCMDSDIO_TypeDef
STASDIO_TypeDef
+ +
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+ + diff --git a/struct_s_d_i_o___type_def.html b/struct_s_d_i_o___type_def.html new file mode 100644 index 0000000..8b6d4cc --- /dev/null +++ b/struct_s_d_i_o___type_def.html @@ -0,0 +1,156 @@ + + + + + + +discoverpixy: SDIO_TypeDef Struct Reference + + + + + + + + + + +
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SDIO_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

SD host Interface. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t POWER
 
__IO uint32_t CLKCR
 
__IO uint32_t ARG
 
__IO uint32_t CMD
 
__I uint32_t RESPCMD
 
__I uint32_t RESP1
 
__I uint32_t RESP2
 
__I uint32_t RESP3
 
__I uint32_t RESP4
 
__IO uint32_t DTIMER
 
__IO uint32_t DLEN
 
__IO uint32_t DCTRL
 
__I uint32_t DCOUNT
 
__I uint32_t STA
 
__IO uint32_t ICR
 
__IO uint32_t MASK
 
uint32_t RESERVED0 [2]
 
__I uint32_t FIFOCNT
 
uint32_t RESERVED1 [13]
 
__IO uint32_t FIFO
 
+

Detailed Description

+

SD host Interface.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_linked_segment-members.html b/struct_s_linked_segment-members.html new file mode 100644 index 0000000..295efb8 --- /dev/null +++ b/struct_s_linked_segment-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SLinkedSegment Member List
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This is the complete list of members for SLinkedSegment, including all inherited members.

+ + + + + +
next (defined in SLinkedSegment)SLinkedSegment
segment (defined in SLinkedSegment)SLinkedSegment
SLinkedSegment(const SSegment &segmentInit) (defined in SLinkedSegment)SLinkedSegmentinline
SLinkedSegment(const SSegment &segmentInit) (defined in SLinkedSegment)SLinkedSegmentinline
+ +
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SLinkedSegment Struct Reference
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+Collaboration diagram for SLinkedSegment:
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Collaboration graph
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[legend]
+ + + + + + +

+Public Member Functions

+ SLinkedSegment (const SSegment &segmentInit)
 
+ SLinkedSegment (const SSegment &segmentInit)
 
+ + + + + +

+Public Attributes

+SSegment segment
 
+SLinkedSegment * next
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/Pixy/src/blob.h
    • +
+
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+ + diff --git a/struct_s_linked_segment__coll__graph.map b/struct_s_linked_segment__coll__graph.map new file mode 100644 index 0000000..7e2bcf4 --- /dev/null +++ b/struct_s_linked_segment__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/struct_s_linked_segment__coll__graph.md5 b/struct_s_linked_segment__coll__graph.md5 new file mode 100644 index 0000000..415db03 --- /dev/null +++ b/struct_s_linked_segment__coll__graph.md5 @@ -0,0 +1 @@ +60be2446a4357b486b61dbca0c59f8b2 \ No newline at end of file diff --git a/struct_s_linked_segment__coll__graph.png b/struct_s_linked_segment__coll__graph.png new file mode 100644 index 0000000..27a3bdb Binary files /dev/null and b/struct_s_linked_segment__coll__graph.png differ diff --git a/struct_s_moment_stats-members.html b/struct_s_moment_stats-members.html new file mode 100644 index 0000000..c8a7496 --- /dev/null +++ b/struct_s_moment_stats-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SMomentStats Member List
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angle (defined in SMomentStats)SMomentStats
area (defined in SMomentStats)SMomentStats
centroidX (defined in SMomentStats)SMomentStats
centroidY (defined in SMomentStats)SMomentStats
majorDiameter (defined in SMomentStats)SMomentStats
minorDiameter (defined in SMomentStats)SMomentStats
+ +
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SMomentStats Struct Reference
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+Public Attributes

+int area
 
+float centroidX
 
+float centroidY
 
+float angle
 
+float majorDiameter
 
+float minorDiameter
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/Pixy/src/blob.h
    • +
+
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Add(const SMoments &moments) (defined in SMoments)SMomentsinline
Add(const SMoments &moments) (defined in SMoments)SMomentsinline
area (defined in SMoments)SMoments
computeAxes (defined in SMoments)SMomentsstatic
Reset() (defined in SMoments)SMomentsinline
Reset() (defined in SMoments)SMomentsinline
+ +
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SMoments Struct Reference
+
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+Public Member Functions

+void Reset ()
 
+void Add (const SMoments &moments)
 
+void Reset ()
 
+void Add (const SMoments &moments)
 
+ + + +

+Public Attributes

+int area
 
+ + + +

+Static Public Attributes

+static bool computeAxes
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/Pixy/src/blob.h
    • +
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_p_i___init_type_def-members.html b/struct_s_p_i___init_type_def-members.html new file mode 100644 index 0000000..3231b3d --- /dev/null +++ b/struct_s_p_i___init_type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SPI_InitTypeDef Member List
+
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This is the complete list of members for SPI_InitTypeDef, including all inherited members.

+ + + + + + + + + + +
SPI_BaudRatePrescalerSPI_InitTypeDef
SPI_CPHASPI_InitTypeDef
SPI_CPOLSPI_InitTypeDef
SPI_CRCPolynomialSPI_InitTypeDef
SPI_DataSizeSPI_InitTypeDef
SPI_DirectionSPI_InitTypeDef
SPI_FirstBitSPI_InitTypeDef
SPI_ModeSPI_InitTypeDef
SPI_NSSSPI_InitTypeDef
+ +
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+ + diff --git a/struct_s_p_i___init_type_def.html b/struct_s_p_i___init_type_def.html new file mode 100644 index 0000000..e2054f9 --- /dev/null +++ b/struct_s_p_i___init_type_def.html @@ -0,0 +1,252 @@ + + + + + + +discoverpixy: SPI_InitTypeDef Struct Reference + + + + + + + + + + +
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SPI_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » SPI
+
+
+ +

SPI Init structure definition. + More...

+ +

#include <stm32f4xx_spi.h>

+ + + + + + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t SPI_Direction
 
uint16_t SPI_Mode
 
uint16_t SPI_DataSize
 
uint16_t SPI_CPOL
 
uint16_t SPI_CPHA
 
uint16_t SPI_NSS
 
uint16_t SPI_BaudRatePrescaler
 
uint16_t SPI_FirstBit
 
uint16_t SPI_CRCPolynomial
 
+

Detailed Description

+

SPI Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_BaudRatePrescaler
+
+

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI_BaudRate_Prescaler

Note
The communication clock is derived from the master clock. The slave clock does not need to be set.
+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_CPHA
+
+

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI_Clock_Phase

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_CPOL
+
+

Specifies the serial clock steady state. This parameter can be a value of SPI_Clock_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_CRCPolynomial
+
+

Specifies the polynomial used for the CRC calculation.

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_DataSize
+
+

Specifies the SPI data size. This parameter can be a value of SPI_data_size

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_Direction
+
+

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of SPI_data_direction

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_FirstBit
+
+

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI_MSB_LSB_transmission

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_Mode
+
+

Specifies the SPI operating mode. This parameter can be a value of SPI_mode

+ +
+
+ +
+
+ + + + +
uint16_t SPI_InitTypeDef::SPI_NSS
+
+

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI_Slave_Select_management

+ +
+
+
The documentation for this struct was generated from the following file: +
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SPI_TypeDef Member List
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This is the complete list of members for SPI_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + +
CR1SPI_TypeDef
CR2SPI_TypeDef
CRCPRSPI_TypeDef
DRSPI_TypeDef
I2SCFGRSPI_TypeDef
I2SPRSPI_TypeDef
RESERVED0SPI_TypeDef
RESERVED1SPI_TypeDef
RESERVED2SPI_TypeDef
RESERVED3SPI_TypeDef
RESERVED4SPI_TypeDef
RESERVED5SPI_TypeDef
RESERVED6SPI_TypeDef
RESERVED7SPI_TypeDef
RESERVED8SPI_TypeDef
RXCRCRSPI_TypeDef
SRSPI_TypeDef
TXCRCRSPI_TypeDef
+ +
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SPI_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Serial Peripheral Interface. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint16_t CR1
 
uint16_t RESERVED0
 
__IO uint16_t CR2
 
uint16_t RESERVED1
 
__IO uint16_t SR
 
uint16_t RESERVED2
 
__IO uint16_t DR
 
uint16_t RESERVED3
 
__IO uint16_t CRCPR
 
uint16_t RESERVED4
 
__IO uint16_t RXCRCR
 
uint16_t RESERVED5
 
__IO uint16_t TXCRCR
 
uint16_t RESERVED6
 
__IO uint16_t I2SCFGR
 
uint16_t RESERVED7
 
__IO uint16_t I2SPR
 
uint16_t RESERVED8
 
+

Detailed Description

+

Serial Peripheral Interface.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_s_segment-members.html b/struct_s_segment-members.html new file mode 100644 index 0000000..428c0bd --- /dev/null +++ b/struct_s_segment-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SSegment Member List
+
+
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This is the complete list of members for SSegment, including all inherited members.

+ + + + + + + + +
endCol (defined in SSegment)SSegment
GetMoments(SMoments &moments) const (defined in SSegment)SSegmentinline
GetMoments(SMoments &moments) const (defined in SSegment)SSegmentinline
invalid_row (defined in SSegment)SSegmentstatic
model (defined in SSegment)SSegment
row (defined in SSegment)SSegment
startCol (defined in SSegment)SSegment
+ +
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SSegment Struct Reference
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+Public Member Functions

+void GetMoments (SMoments &moments) const
 
+void GetMoments (SMoments &moments) const
 
+ + + + + + + + + +

+Public Attributes

+unsigned char model: 3
 
+unsigned short row: 9
 
+unsigned short startCol: 10
 
+unsigned short endCol: 10
 
+ + + +

+Static Public Attributes

+static const short invalid_row = 0x1ff
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/Pixy/src/blob.h
    • +
+
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SYSCFG_TypeDef Member List
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This is the complete list of members for SYSCFG_TypeDef, including all inherited members.

+ + + + + + +
CMPCRSYSCFG_TypeDef
EXTICRSYSCFG_TypeDef
MEMRMPSYSCFG_TypeDef
PMCSYSCFG_TypeDef
RESERVEDSYSCFG_TypeDef
+ +
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+ + diff --git a/struct_s_y_s_c_f_g___type_def.html b/struct_s_y_s_c_f_g___type_def.html new file mode 100644 index 0000000..fa0c078 --- /dev/null +++ b/struct_s_y_s_c_f_g___type_def.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: SYSCFG_TypeDef Struct Reference + + + + + + + + + + +
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SYSCFG_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

System configuration controller. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + +

+Public Attributes

__IO uint32_t MEMRMP
 
__IO uint32_t PMC
 
__IO uint32_t EXTICR [4]
 
uint32_t RESERVED [2]
 
__IO uint32_t CMPCR
 
+

Detailed Description

+

System configuration controller.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_sys_tick___type-members.html b/struct_sys_tick___type-members.html new file mode 100644 index 0000000..6310ec5 --- /dev/null +++ b/struct_sys_tick___type-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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SysTick_Type Member List
+
+
+ +

This is the complete list of members for SysTick_Type, including all inherited members.

+ + + + + +
CALIBSysTick_Type
CTRLSysTick_Type
LOADSysTick_Type
VALSysTick_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_sys_tick___type.html b/struct_sys_tick___type.html new file mode 100644 index 0000000..7a9b800 --- /dev/null +++ b/struct_sys_tick___type.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: SysTick_Type Struct Reference + + + + + + + + + + +
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SysTick_Type Struct Reference
Defines and Type Definitions » System Tick Timer (SysTick)
+
+
+ +

Structure type to access the System Timer (SysTick). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + +

+Public Attributes

__IO uint32_t CTRL
 
__IO uint32_t LOAD
 
__IO uint32_t VAL
 
__I uint32_t CALIB
 
+

Detailed Description

+

Structure type to access the System Timer (SysTick).

+

Member Data Documentation

+ +
+
+ + + + +
__I uint32_t SysTick_Type::CALIB
+
+

Offset: 0x00C (R/ ) SysTick Calibration Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::CTRL
+
+

Offset: 0x000 (R/W) SysTick Control and Status Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::LOAD
+
+

Offset: 0x004 (R/W) SysTick Reload Value Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t SysTick_Type::VAL
+
+

Offset: 0x008 (R/W) SysTick Current Value Register

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___b_d_t_r_init_type_def-members.html b/struct_t_i_m___b_d_t_r_init_type_def-members.html new file mode 100644 index 0000000..e94b631 --- /dev/null +++ b/struct_t_i_m___b_d_t_r_init_type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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TIM_BDTRInitTypeDef Member List
+
+
+ +

This is the complete list of members for TIM_BDTRInitTypeDef, including all inherited members.

+ + + + + + + + +
TIM_AutomaticOutputTIM_BDTRInitTypeDef
TIM_BreakTIM_BDTRInitTypeDef
TIM_BreakPolarityTIM_BDTRInitTypeDef
TIM_DeadTimeTIM_BDTRInitTypeDef
TIM_LOCKLevelTIM_BDTRInitTypeDef
TIM_OSSIStateTIM_BDTRInitTypeDef
TIM_OSSRStateTIM_BDTRInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___b_d_t_r_init_type_def.html b/struct_t_i_m___b_d_t_r_init_type_def.html new file mode 100644 index 0000000..11e20c6 --- /dev/null +++ b/struct_t_i_m___b_d_t_r_init_type_def.html @@ -0,0 +1,223 @@ + + + + + + +discoverpixy: TIM_BDTRInitTypeDef Struct Reference + + + + + + + + + + +
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TIM_BDTRInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » TIM
+
+
+ +

BDTR structure definition. + More...

+ +

#include <stm32f4xx_tim.h>

+ + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t TIM_OSSRState
 
uint16_t TIM_OSSIState
 
uint16_t TIM_LOCKLevel
 
uint16_t TIM_DeadTime
 
uint16_t TIM_Break
 
uint16_t TIM_BreakPolarity
 
uint16_t TIM_AutomaticOutput
 
+

Detailed Description

+

BDTR structure definition.

+
Note
This structure is used only with TIM1 and TIM8.
+

Member Data Documentation

+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_AutomaticOutput
+
+

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of TIM_AOE_Bit_Set_Reset

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_Break
+
+

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of TIM_Break_Input_enable_disable

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_BreakPolarity
+
+

Specifies the TIM Break Input pin polarity. This parameter can be a value of TIM_Break_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_DeadTime
+
+

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between 0x00 and 0xFF

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_LOCKLevel
+
+

Specifies the LOCK level parameters. This parameter can be a value of TIM_Lock_level

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_OSSIState
+
+

Specifies the Off-State used in Idle state. This parameter can be a value of TIM_OSSI_Off_State_Selection_for_Idle_mode_state

+ +
+
+ +
+
+ + + + +
uint16_t TIM_BDTRInitTypeDef::TIM_OSSRState
+
+

Specifies the Off-State selection used in Run mode. This parameter can be a value of TIM_OSSR_Off_State_Selection_for_Run_mode_state

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___i_c_init_type_def-members.html b/struct_t_i_m___i_c_init_type_def-members.html new file mode 100644 index 0000000..78aa34b --- /dev/null +++ b/struct_t_i_m___i_c_init_type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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TIM_ICInitTypeDef Member List
+
+
+ +

This is the complete list of members for TIM_ICInitTypeDef, including all inherited members.

+ + + + + + +
TIM_ChannelTIM_ICInitTypeDef
TIM_ICFilterTIM_ICInitTypeDef
TIM_ICPolarityTIM_ICInitTypeDef
TIM_ICPrescalerTIM_ICInitTypeDef
TIM_ICSelectionTIM_ICInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___i_c_init_type_def.html b/struct_t_i_m___i_c_init_type_def.html new file mode 100644 index 0000000..addecda --- /dev/null +++ b/struct_t_i_m___i_c_init_type_def.html @@ -0,0 +1,192 @@ + + + + + + +discoverpixy: TIM_ICInitTypeDef Struct Reference + + + + + + + + + + +
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TIM_ICInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » TIM
+
+
+ +

TIM Input Capture Init structure definition. + More...

+ +

#include <stm32f4xx_tim.h>

+ + + + + + + + + + + + +

+Public Attributes

uint16_t TIM_Channel
 
uint16_t TIM_ICPolarity
 
uint16_t TIM_ICSelection
 
uint16_t TIM_ICPrescaler
 
uint16_t TIM_ICFilter
 
+

Detailed Description

+

TIM Input Capture Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t TIM_ICInitTypeDef::TIM_Channel
+
+

Specifies the TIM channel. This parameter can be a value of TIM_Channel

+ +
+
+ +
+
+ + + + +
uint16_t TIM_ICInitTypeDef::TIM_ICFilter
+
+

Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF

+ +
+
+ +
+
+ + + + +
uint16_t TIM_ICInitTypeDef::TIM_ICPolarity
+
+

Specifies the active edge of the input signal. This parameter can be a value of TIM_Input_Capture_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t TIM_ICInitTypeDef::TIM_ICPrescaler
+
+

Specifies the Input Capture Prescaler. This parameter can be a value of TIM_Input_Capture_Prescaler

+ +
+
+ +
+
+ + + + +
uint16_t TIM_ICInitTypeDef::TIM_ICSelection
+
+

Specifies the input. This parameter can be a value of TIM_Input_Capture_Selection

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___o_c_init_type_def-members.html b/struct_t_i_m___o_c_init_type_def-members.html new file mode 100644 index 0000000..30b6639 --- /dev/null +++ b/struct_t_i_m___o_c_init_type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
+
TIM_OCInitTypeDef Member List
+
+
+ +

This is the complete list of members for TIM_OCInitTypeDef, including all inherited members.

+ + + + + + + + + +
TIM_OCIdleStateTIM_OCInitTypeDef
TIM_OCModeTIM_OCInitTypeDef
TIM_OCNIdleStateTIM_OCInitTypeDef
TIM_OCNPolarityTIM_OCInitTypeDef
TIM_OCPolarityTIM_OCInitTypeDef
TIM_OutputNStateTIM_OCInitTypeDef
TIM_OutputStateTIM_OCInitTypeDef
TIM_PulseTIM_OCInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___o_c_init_type_def.html b/struct_t_i_m___o_c_init_type_def.html new file mode 100644 index 0000000..b8897b6 --- /dev/null +++ b/struct_t_i_m___o_c_init_type_def.html @@ -0,0 +1,237 @@ + + + + + + +discoverpixy: TIM_OCInitTypeDef Struct Reference + + + + + + + + + + +
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TIM_OCInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » TIM
+
+
+ +

TIM Output Compare Init structure definition. + More...

+ +

#include <stm32f4xx_tim.h>

+ + + + + + + + + + + + + + + + + + +

+Public Attributes

uint16_t TIM_OCMode
 
uint16_t TIM_OutputState
 
uint16_t TIM_OutputNState
 
uint32_t TIM_Pulse
 
uint16_t TIM_OCPolarity
 
uint16_t TIM_OCNPolarity
 
uint16_t TIM_OCIdleState
 
uint16_t TIM_OCNIdleState
 
+

Detailed Description

+

TIM Output Compare Init structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OCIdleState
+
+

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM_Output_Compare_Idle_State

Note
This parameter is valid only for TIM1 and TIM8.
+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OCMode
+
+

Specifies the TIM mode. This parameter can be a value of TIM_Output_Compare_and_PWM_modes

+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OCNIdleState
+
+

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM_Output_Compare_N_Idle_State

Note
This parameter is valid only for TIM1 and TIM8.
+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OCNPolarity
+
+

Specifies the complementary output polarity. This parameter can be a value of TIM_Output_Compare_N_Polarity

Note
This parameter is valid only for TIM1 and TIM8.
+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OCPolarity
+
+

Specifies the output polarity. This parameter can be a value of TIM_Output_Compare_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OutputNState
+
+

Specifies the TIM complementary Output Compare state. This parameter can be a value of TIM_Output_Compare_N_State

Note
This parameter is valid only for TIM1 and TIM8.
+ +
+
+ +
+
+ + + + +
uint16_t TIM_OCInitTypeDef::TIM_OutputState
+
+

Specifies the TIM Output Compare state. This parameter can be a value of TIM_Output_Compare_State

+ +
+
+ +
+
+ + + + +
uint32_t TIM_OCInitTypeDef::TIM_Pulse
+
+

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___time_base_init_type_def-members.html b/struct_t_i_m___time_base_init_type_def-members.html new file mode 100644 index 0000000..4cbeb4d --- /dev/null +++ b/struct_t_i_m___time_base_init_type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
+
TIM_TimeBaseInitTypeDef Member List
+
+
+ +

This is the complete list of members for TIM_TimeBaseInitTypeDef, including all inherited members.

+ + + + + + +
TIM_ClockDivisionTIM_TimeBaseInitTypeDef
TIM_CounterModeTIM_TimeBaseInitTypeDef
TIM_PeriodTIM_TimeBaseInitTypeDef
TIM_PrescalerTIM_TimeBaseInitTypeDef
TIM_RepetitionCounterTIM_TimeBaseInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___time_base_init_type_def.html b/struct_t_i_m___time_base_init_type_def.html new file mode 100644 index 0000000..14d0807 --- /dev/null +++ b/struct_t_i_m___time_base_init_type_def.html @@ -0,0 +1,197 @@ + + + + + + +discoverpixy: TIM_TimeBaseInitTypeDef Struct Reference + + + + + + + + + + +
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TIM_TimeBaseInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » TIM
+
+
+ +

TIM Time Base Init structure definition. + More...

+ +

#include <stm32f4xx_tim.h>

+ + + + + + + + + + + + +

+Public Attributes

uint16_t TIM_Prescaler
 
uint16_t TIM_CounterMode
 
uint32_t TIM_Period
 
uint16_t TIM_ClockDivision
 
uint8_t TIM_RepetitionCounter
 
+

Detailed Description

+

TIM Time Base Init structure definition.

+
Note
This structure is used with all TIMx except for TIM6 and TIM7.
+

Member Data Documentation

+ +
+
+ + + + +
uint16_t TIM_TimeBaseInitTypeDef::TIM_ClockDivision
+
+

Specifies the clock division. This parameter can be a value of TIM_Clock_Division_CKD

+ +
+
+ +
+
+ + + + +
uint16_t TIM_TimeBaseInitTypeDef::TIM_CounterMode
+
+

Specifies the counter mode. This parameter can be a value of TIM_Counter_Mode

+ +
+
+ +
+
+ + + + +
uint32_t TIM_TimeBaseInitTypeDef::TIM_Period
+
+

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF.

+ +
+
+ +
+
+ + + + +
uint16_t TIM_TimeBaseInitTypeDef::TIM_Prescaler
+
+

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF

+ +
+
+ +
+
+ + + + +
uint8_t TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
+
+

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

    +
  • the number of PWM periods in edge-aligned mode
    • +
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.
    Note
    This parameter is valid only for TIM1 and TIM8.
    +
    • +
+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___type_def-members.html b/struct_t_i_m___type_def-members.html new file mode 100644 index 0000000..a28a6ec --- /dev/null +++ b/struct_t_i_m___type_def-members.html @@ -0,0 +1,138 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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TIM_TypeDef Member List
+
+
+ +

This is the complete list of members for TIM_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ARRTIM_TypeDef
BDTRTIM_TypeDef
CCERTIM_TypeDef
CCMR1TIM_TypeDef
CCMR2TIM_TypeDef
CCR1TIM_TypeDef
CCR2TIM_TypeDef
CCR3TIM_TypeDef
CCR4TIM_TypeDef
CNTTIM_TypeDef
CR1TIM_TypeDef
CR2TIM_TypeDef
DCRTIM_TypeDef
DIERTIM_TypeDef
DMARTIM_TypeDef
EGRTIM_TypeDef
ORTIM_TypeDef
PSCTIM_TypeDef
RCRTIM_TypeDef
RESERVED0TIM_TypeDef
RESERVED1TIM_TypeDef
RESERVED10TIM_TypeDef
RESERVED11TIM_TypeDef
RESERVED12TIM_TypeDef
RESERVED13TIM_TypeDef
RESERVED14TIM_TypeDef
RESERVED2TIM_TypeDef
RESERVED3TIM_TypeDef
RESERVED4TIM_TypeDef
RESERVED5TIM_TypeDef
RESERVED6TIM_TypeDef
RESERVED7TIM_TypeDef
RESERVED8TIM_TypeDef
RESERVED9TIM_TypeDef
SMCRTIM_TypeDef
SRTIM_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_i_m___type_def.html b/struct_t_i_m___type_def.html new file mode 100644 index 0000000..aa851e8 --- /dev/null +++ b/struct_t_i_m___type_def.html @@ -0,0 +1,188 @@ + + + + + + +discoverpixy: TIM_TypeDef Struct Reference + + + + + + + + + + +
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TIM_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

TIM. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint16_t CR1
 
uint16_t RESERVED0
 
__IO uint16_t CR2
 
uint16_t RESERVED1
 
__IO uint16_t SMCR
 
uint16_t RESERVED2
 
__IO uint16_t DIER
 
uint16_t RESERVED3
 
__IO uint16_t SR
 
uint16_t RESERVED4
 
__IO uint16_t EGR
 
uint16_t RESERVED5
 
__IO uint16_t CCMR1
 
uint16_t RESERVED6
 
__IO uint16_t CCMR2
 
uint16_t RESERVED7
 
__IO uint16_t CCER
 
uint16_t RESERVED8
 
__IO uint32_t CNT
 
__IO uint16_t PSC
 
uint16_t RESERVED9
 
__IO uint32_t ARR
 
__IO uint16_t RCR
 
uint16_t RESERVED10
 
__IO uint32_t CCR1
 
__IO uint32_t CCR2
 
__IO uint32_t CCR3
 
__IO uint32_t CCR4
 
__IO uint16_t BDTR
 
uint16_t RESERVED11
 
__IO uint16_t DCR
 
uint16_t RESERVED12
 
__IO uint16_t DMAR
 
uint16_t RESERVED13
 
__IO uint16_t OR
 
uint16_t RESERVED14
 
+

Detailed Description

+

TIM.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t-members.html b/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t-members.html new file mode 100644 index 0000000..68b9214 --- /dev/null +++ b/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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TOUCH_AREA_STRUCT Member List
+
+
+ +

This is the complete list of members for TOUCH_AREA_STRUCT, including all inherited members.

+ + + + + + + + +
callback (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
flags (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
hookedActions (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
x1 (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
x2 (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
y1 (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
y2 (defined in TOUCH_AREA_STRUCT)TOUCH_AREA_STRUCT
+ +
+Generated on Sun May 10 2015 15:17:29 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t.html b/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t.html new file mode 100644 index 0000000..bdf71c1 --- /dev/null +++ b/struct_t_o_u_c_h___a_r_e_a___s_t_r_u_c_t.html @@ -0,0 +1,230 @@ + + + + + + +discoverpixy: TOUCH_AREA_STRUCT Struct Reference + + + + + + + + + + +
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+Data Fields
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+
TOUCH_AREA_STRUCT Struct Reference
Touch
+
+
+ +

#include <touch.h>

+ + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

TOUCH_ACTION hookedActions
 Actions to listen to. More...
 
uint16_t x1
 Top Left X-Coordinate of Area. More...
 
uint16_t y1
 Top Left Y-Coordinate of Area. More...
 
uint16_t x2
 Bottom Right X-Coordinate of Area. More...
 
uint16_t y2
 Bottom Right Y-Coordinate of Area. More...
 
TOUCH_CALLBACK callback
 Callback. More...
 
uint8_t flags
 For internal Used, don't change, don't initialize. More...
 
+

Detailed Description

+

Structure to configure a Touch Area

+

Field Documentation

+ +
+
+ + + + +
TOUCH_CALLBACK callback
+
+ +

Callback.

+ +
+
+ +
+
+ + + + +
uint8_t flags
+
+ +

For internal Used, don't change, don't initialize.

+ +
+
+ +
+
+ + + + +
TOUCH_ACTION hookedActions
+
+ +

Actions to listen to.

+ +
+
+ +
+
+ + + + +
uint16_t x1
+
+ +

Top Left X-Coordinate of Area.

+ +
+
+ +
+
+ + + + +
uint16_t x2
+
+ +

Bottom Right X-Coordinate of Area.

+ +
+
+ +
+
+ + + + +
uint16_t y1
+
+ +

Top Left Y-Coordinate of Area.

+ +
+
+ +
+
+ + + + +
uint16_t y2
+
+ +

Bottom Right Y-Coordinate of Area.

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_t_p_i___type-members.html b/struct_t_p_i___type-members.html new file mode 100644 index 0000000..dfa9b85 --- /dev/null +++ b/struct_t_p_i___type-members.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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TPI_Type Member List
+
+
+ +

This is the complete list of members for TPI_Type, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + +
ACPRTPI_Type
CLAIMCLRTPI_Type
CLAIMSETTPI_Type
CSPSRTPI_Type
DEVIDTPI_Type
DEVTYPETPI_Type
FFCRTPI_Type
FFSRTPI_Type
FIFO0TPI_Type
FIFO1TPI_Type
FSCRTPI_Type
ITATBCTR0TPI_Type
ITATBCTR2TPI_Type
ITCTRLTPI_Type
RESERVED0 (defined in TPI_Type)TPI_Type
RESERVED1 (defined in TPI_Type)TPI_Type
RESERVED2 (defined in TPI_Type)TPI_Type
RESERVED3 (defined in TPI_Type)TPI_Type
RESERVED4 (defined in TPI_Type)TPI_Type
RESERVED5 (defined in TPI_Type)TPI_Type
RESERVED7 (defined in TPI_Type)TPI_Type
SPPRTPI_Type
SSPSRTPI_Type
TRIGGERTPI_Type
+ +
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+ + diff --git a/struct_t_p_i___type.html b/struct_t_p_i___type.html new file mode 100644 index 0000000..ffcb091 --- /dev/null +++ b/struct_t_p_i___type.html @@ -0,0 +1,393 @@ + + + + + + +discoverpixy: TPI_Type Struct Reference + + + + + + + + + + +
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TPI_Type Struct Reference
Defines and Type Definitions » Trace Port Interface (TPI)
+
+
+ +

Structure type to access the Trace Port Interface Register (TPI). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint32_t SSPSR
 
__IO uint32_t CSPSR
 
+uint32_t RESERVED0 [2]
 
__IO uint32_t ACPR
 
+uint32_t RESERVED1 [55]
 
__IO uint32_t SPPR
 
+uint32_t RESERVED2 [131]
 
__I uint32_t FFSR
 
__IO uint32_t FFCR
 
__I uint32_t FSCR
 
+uint32_t RESERVED3 [759]
 
__I uint32_t TRIGGER
 
__I uint32_t FIFO0
 
__I uint32_t ITATBCTR2
 
+uint32_t RESERVED4 [1]
 
__I uint32_t ITATBCTR0
 
__I uint32_t FIFO1
 
__IO uint32_t ITCTRL
 
+uint32_t RESERVED5 [39]
 
__IO uint32_t CLAIMSET
 
__IO uint32_t CLAIMCLR
 
+uint32_t RESERVED7 [8]
 
__I uint32_t DEVID
 
__I uint32_t DEVTYPE
 
+

Detailed Description

+

Structure type to access the Trace Port Interface Register (TPI).

+

Member Data Documentation

+ +
+
+ + + + +
__IO uint32_t TPI_Type::ACPR
+
+

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CLAIMCLR
+
+

Offset: 0xFA4 (R/W) Claim tag clear

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CLAIMSET
+
+

Offset: 0xFA0 (R/W) Claim tag set

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::CSPSR
+
+

Offset: 0x004 (R/W) Current Parallel Port Size Register

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::DEVID
+
+

Offset: 0xFC8 (R/ ) TPIU_DEVID

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::DEVTYPE
+
+

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::FFCR
+
+

Offset: 0x304 (R/W) Formatter and Flush Control Register

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FFSR
+
+

Offset: 0x300 (R/ ) Formatter and Flush Status Register

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FIFO0
+
+

Offset: 0xEEC (R/ ) Integration ETM Data

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FIFO1
+
+

Offset: 0xEFC (R/ ) Integration ITM Data

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::FSCR
+
+

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::ITATBCTR0
+
+

Offset: 0xEF8 (R/ ) ITATBCTR0

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::ITATBCTR2
+
+

Offset: 0xEF0 (R/ ) ITATBCTR2

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::ITCTRL
+
+

Offset: 0xF00 (R/W) Integration Mode Control

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::SPPR
+
+

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

+ +
+
+ +
+
+ + + + +
__IO uint32_t TPI_Type::SSPSR
+
+

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

+ +
+
+ +
+
+ + + + +
__I uint32_t TPI_Type::TRIGGER
+
+

Offset: 0xEE8 (R/ ) TRIGGER

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_a_r_t___clock_init_type_def-members.html b/struct_u_s_a_r_t___clock_init_type_def-members.html new file mode 100644 index 0000000..d1cd63a --- /dev/null +++ b/struct_u_s_a_r_t___clock_init_type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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USART_ClockInitTypeDef Member List
+
+
+ +

This is the complete list of members for USART_ClockInitTypeDef, including all inherited members.

+ + + + + +
USART_ClockUSART_ClockInitTypeDef
USART_CPHAUSART_ClockInitTypeDef
USART_CPOLUSART_ClockInitTypeDef
USART_LastBitUSART_ClockInitTypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_a_r_t___clock_init_type_def.html b/struct_u_s_a_r_t___clock_init_type_def.html new file mode 100644 index 0000000..0e3ced9 --- /dev/null +++ b/struct_u_s_a_r_t___clock_init_type_def.html @@ -0,0 +1,177 @@ + + + + + + +discoverpixy: USART_ClockInitTypeDef Struct Reference + + + + + + + + + + +
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USART_ClockInitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » USART
+
+
+ +

USART Clock Init Structure definition. + More...

+ +

#include <stm32f4xx_usart.h>

+ + + + + + + + + + +

+Public Attributes

uint16_t USART_Clock
 
uint16_t USART_CPOL
 
uint16_t USART_CPHA
 
uint16_t USART_LastBit
 
+

Detailed Description

+

USART Clock Init Structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint16_t USART_ClockInitTypeDef::USART_Clock
+
+

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of USART_Clock

+ +
+
+ +
+
+ + + + +
uint16_t USART_ClockInitTypeDef::USART_CPHA
+
+

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART_Clock_Phase

+ +
+
+ +
+
+ + + + +
uint16_t USART_ClockInitTypeDef::USART_CPOL
+
+

Specifies the steady state of the serial clock. This parameter can be a value of USART_Clock_Polarity

+ +
+
+ +
+
+ + + + +
uint16_t USART_ClockInitTypeDef::USART_LastBit
+
+

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART_Last_Bit

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_a_r_t___init_type_def-members.html b/struct_u_s_a_r_t___init_type_def-members.html new file mode 100644 index 0000000..3563055 --- /dev/null +++ b/struct_u_s_a_r_t___init_type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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USART_InitTypeDef Member List
+
+
+ +

This is the complete list of members for USART_InitTypeDef, including all inherited members.

+ + + + + + + +
USART_BaudRateUSART_InitTypeDef
USART_HardwareFlowControlUSART_InitTypeDef
USART_ModeUSART_InitTypeDef
USART_ParityUSART_InitTypeDef
USART_StopBitsUSART_InitTypeDef
USART_WordLengthUSART_InitTypeDef
+ +
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+ + diff --git a/struct_u_s_a_r_t___init_type_def.html b/struct_u_s_a_r_t___init_type_def.html new file mode 100644 index 0000000..e872cad --- /dev/null +++ b/struct_u_s_a_r_t___init_type_def.html @@ -0,0 +1,210 @@ + + + + + + +discoverpixy: USART_InitTypeDef Struct Reference + + + + + + + + + + +
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USART_InitTypeDef Struct Reference
STM32F4xx_StdPeriph_Driver » USART
+
+
+ +

USART Init Structure definition. + More...

+ +

#include <stm32f4xx_usart.h>

+ + + + + + + + + + + + + + +

+Public Attributes

uint32_t USART_BaudRate
 
uint16_t USART_WordLength
 
uint16_t USART_StopBits
 
uint16_t USART_Parity
 
uint16_t USART_Mode
 
uint16_t USART_HardwareFlowControl
 
+

Detailed Description

+

USART Init Structure definition.

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t USART_InitTypeDef::USART_BaudRate
+
+

This member configures the USART communication baud rate. The baud rate is computed using the following formula:

    +
  • IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
    • +
  • FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register.
    • +
+ +
+
+ +
+
+ + + + +
uint16_t USART_InitTypeDef::USART_HardwareFlowControl
+
+

Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of USART_Hardware_Flow_Control

+ +
+
+ +
+
+ + + + +
uint16_t USART_InitTypeDef::USART_Mode
+
+

Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART_Mode

+ +
+
+ +
+
+ + + + +
uint16_t USART_InitTypeDef::USART_Parity
+
+

Specifies the parity mode. This parameter can be a value of USART_Parity

Note
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).
+ +
+
+ +
+
+ + + + +
uint16_t USART_InitTypeDef::USART_StopBits
+
+

Specifies the number of stop bits transmitted. This parameter can be a value of USART_Stop_Bits

+ +
+
+ +
+
+ + + + +
uint16_t USART_InitTypeDef::USART_WordLength
+
+

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USART_Word_Length

+ +
+
+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_a_r_t___type_def-members.html b/struct_u_s_a_r_t___type_def-members.html new file mode 100644 index 0000000..43efea4 --- /dev/null +++ b/struct_u_s_a_r_t___type_def-members.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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USART_TypeDef Member List
+
+
+ +

This is the complete list of members for USART_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + +
BRRUSART_TypeDef
CR1USART_TypeDef
CR2USART_TypeDef
CR3USART_TypeDef
DRUSART_TypeDef
GTPRUSART_TypeDef
RESERVED0USART_TypeDef
RESERVED1USART_TypeDef
RESERVED2USART_TypeDef
RESERVED3USART_TypeDef
RESERVED4USART_TypeDef
RESERVED5USART_TypeDef
RESERVED6USART_TypeDef
SRUSART_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_a_r_t___type_def.html b/struct_u_s_a_r_t___type_def.html new file mode 100644 index 0000000..a6665d4 --- /dev/null +++ b/struct_u_s_a_r_t___type_def.html @@ -0,0 +1,144 @@ + + + + + + +discoverpixy: USART_TypeDef Struct Reference + + + + + + + + + + +
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USART_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
+
+ +

Universal Synchronous Asynchronous Receiver Transmitter. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

__IO uint16_t SR
 
uint16_t RESERVED0
 
__IO uint16_t DR
 
uint16_t RESERVED1
 
__IO uint16_t BRR
 
uint16_t RESERVED2
 
__IO uint16_t CR1
 
uint16_t RESERVED3
 
__IO uint16_t CR2
 
uint16_t RESERVED4
 
__IO uint16_t CR3
 
uint16_t RESERVED5
 
__IO uint16_t GTPR
 
uint16_t RESERVED6
 
+

Detailed Description

+

Universal Synchronous Asynchronous Receiver Transmitter.

+
The documentation for this struct was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_b___o_t_g__core__cfg-members.html b/struct_u_s_b___o_t_g__core__cfg-members.html new file mode 100644 index 0000000..4295fec --- /dev/null +++ b/struct_u_s_b___o_t_g__core__cfg-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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USB_OTG_core_cfg Member List
+
+
+ +

This is the complete list of members for USB_OTG_core_cfg, including all inherited members.

+ + + + + + + + + + + +
coreID (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
dev_endpoints (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
dma_enable (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
host_channels (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
low_power (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
mps (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
phy_itface (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
Sof_output (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
speed (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
TotalFifoSize (defined in USB_OTG_core_cfg)USB_OTG_core_cfg
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/struct_u_s_b___o_t_g__core__cfg.html b/struct_u_s_b___o_t_g__core__cfg.html new file mode 100644 index 0000000..0174b9a --- /dev/null +++ b/struct_u_s_b___o_t_g__core__cfg.html @@ -0,0 +1,139 @@ + + + + + + +discoverpixy: USB_OTG_core_cfg Struct Reference + + + + + + + + + + +
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USB_OTG_core_cfg Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
+
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint8_t host_channels
 
+uint8_t dev_endpoints
 
+uint8_t speed
 
+uint8_t dma_enable
 
+uint16_t mps
 
+uint16_t TotalFifoSize
 
+uint8_t phy_itface
 
+uint8_t Sof_output
 
+uint8_t low_power
 
+uint8_t coreID
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
+
+ +
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DFIFO (defined in USB_OTG_core_regs)USB_OTG_core_regs
DREGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
GREGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
HC_REGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
HPRT0 (defined in USB_OTG_core_regs)USB_OTG_core_regs
HREGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
INEP_REGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
OUTEP_REGS (defined in USB_OTG_core_regs)USB_OTG_core_regs
PCGCCTL (defined in USB_OTG_core_regs)USB_OTG_core_regs
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USB_OTG_core_regs Struct Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
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+Collaboration diagram for USB_OTG_core_regs:
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Collaboration graph
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[legend]
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+Public Attributes

+USB_OTG_GREGS * GREGS
 
+USB_OTG_DREGS * DREGS
 
+USB_OTG_HREGS * HREGS
 
+USB_OTG_INEPREGS * INEP_REGS [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_OUTEPREGS * OUTEP_REGS [USB_OTG_MAX_TX_FIFOS]
 
+USB_OTG_HC_REGS * HC_REGS [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t * HPRT0
 
+__IO uint32_t * DFIFO [USB_OTG_MAX_TX_FIFOS]
 
+__IO uint32_t * PCGCCTL
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
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ctl_data_len (defined in USB_OTG_ep)USB_OTG_ep
data_pid_start (defined in USB_OTG_ep)USB_OTG_ep
dma_addr (defined in USB_OTG_ep)USB_OTG_ep
even_odd_frame (defined in USB_OTG_ep)USB_OTG_ep
is_in (defined in USB_OTG_ep)USB_OTG_ep
is_stall (defined in USB_OTG_ep)USB_OTG_ep
maxpacket (defined in USB_OTG_ep)USB_OTG_ep
num (defined in USB_OTG_ep)USB_OTG_ep
rem_data_len (defined in USB_OTG_ep)USB_OTG_ep
total_data_len (defined in USB_OTG_ep)USB_OTG_ep
tx_fifo_num (defined in USB_OTG_ep)USB_OTG_ep
type (defined in USB_OTG_ep)USB_OTG_ep
xfer_buff (defined in USB_OTG_ep)USB_OTG_ep
xfer_count (defined in USB_OTG_ep)USB_OTG_ep
xfer_len (defined in USB_OTG_ep)USB_OTG_ep
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USB_OTG_ep Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+uint8_t num
 
+uint8_t is_in
 
+uint8_t is_stall
 
+uint8_t type
 
+uint8_t data_pid_start
 
+uint8_t even_odd_frame
 
+uint16_t tx_fifo_num
 
+uint32_t maxpacket
 
+uint8_t * xfer_buff
 
+uint32_t dma_addr
 
+uint32_t xfer_len
 
+uint32_t xfer_count
 
+uint32_t rem_data_len
 
+uint32_t total_data_len
 
+uint32_t ctl_data_len
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
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Connect (defined in USB_OTG_hPort)USB_OTG_hPort
ConnHandled (defined in USB_OTG_hPort)USB_OTG_hPort
ConnStatus (defined in USB_OTG_hPort)USB_OTG_hPort
Disconnect (defined in USB_OTG_hPort)USB_OTG_hPort
DisconnHandled (defined in USB_OTG_hPort)USB_OTG_hPort
DisconnStatus (defined in USB_OTG_hPort)USB_OTG_hPort
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USB_OTG_hPort Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+void(* Disconnect )(void *phost)
 
+void(* Connect )(void *phost)
 
+uint8_t ConnStatus
 
+uint8_t DisconnStatus
 
+uint8_t ConnHandled
 
+uint8_t DisconnHandled
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
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cfg (defined in USB_OTG_handle)USB_OTG_handle
regs (defined in USB_OTG_handle)USB_OTG_handle
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USB_OTG_handle Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Collaboration diagram for USB_OTG_handle:
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[legend]
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+Public Attributes

+USB_OTG_CORE_CFGS cfg
 
+USB_OTG_CORE_REGS regs
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
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data_pid (defined in USB_OTG_hc)USB_OTG_hc
dev_addr (defined in USB_OTG_hc)USB_OTG_hc
dma_addr (defined in USB_OTG_hc)USB_OTG_hc
do_ping (defined in USB_OTG_hc)USB_OTG_hc
ep_is_in (defined in USB_OTG_hc)USB_OTG_hc
ep_num (defined in USB_OTG_hc)USB_OTG_hc
ep_type (defined in USB_OTG_hc)USB_OTG_hc
max_packet (defined in USB_OTG_hc)USB_OTG_hc
speed (defined in USB_OTG_hc)USB_OTG_hc
toggle_in (defined in USB_OTG_hc)USB_OTG_hc
toggle_out (defined in USB_OTG_hc)USB_OTG_hc
xfer_buff (defined in USB_OTG_hc)USB_OTG_hc
xfer_count (defined in USB_OTG_hc)USB_OTG_hc
xfer_len (defined in USB_OTG_hc)USB_OTG_hc
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USB_OTG_hc Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+uint8_t dev_addr
 
+uint8_t ep_num
 
+uint8_t ep_is_in
 
+uint8_t speed
 
+uint8_t do_ping
 
+uint8_t ep_type
 
+uint16_t max_packet
 
+uint8_t data_pid
 
+uint8_t * xfer_buff
 
+uint32_t xfer_len
 
+uint32_t xfer_count
 
+uint8_t toggle_in
 
+uint8_t toggle_out
 
+uint32_t dma_addr
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
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m_u (defined in UVPixel)UVPixel
m_v (defined in UVPixel)UVPixel
UVPixel() (defined in UVPixel)UVPixelinline
UVPixel(int32_t u, int32_t v) (defined in UVPixel)UVPixelinline
UVPixel() (defined in UVPixel)UVPixelinline
UVPixel(int32_t u, int32_t v) (defined in UVPixel)UVPixelinline
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UVPixel Struct Reference
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+Public Member Functions

+ UVPixel (int32_t u, int32_t v)
 
+ UVPixel (int32_t u, int32_t v)
 
+ + + + + +

+Public Attributes

+int32_t m_u
 
+int32_t m_v
 
+
The documentation for this struct was generated from the following file: +
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WWDG_TypeDef Member List
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CFRWWDG_TypeDef
CRWWDG_TypeDef
SRWWDG_TypeDef
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WWDG_TypeDef Struct Reference
CMSIS » Stm32f4xx » Peripheral_registers_structures
+
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+ +

Window WATCHDOG. + More...

+ +

#include <stm32f4xx.h>

+ + + + + + + + +

+Public Attributes

__IO uint32_t CR
 
__IO uint32_t CFR
 
__IO uint32_t SR
 
+

Detailed Description

+

Window WATCHDOG.

+
The documentation for this struct was generated from the following file: +
+ +
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data (defined in qt_meta_stringdata_MainWindow_t)qt_meta_stringdata_MainWindow_t
stringdata (defined in qt_meta_stringdata_MainWindow_t)qt_meta_stringdata_MainWindow_t
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qt_meta_stringdata_MainWindow_t Struct Reference
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+Data Fields

QByteArrayData data [4]
 
char stringdata [49]
 
+

Field Documentation

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QByteArrayData data[4]
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char stringdata[49]
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The documentation for this struct was generated from the following file: +
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uint16_t_uint8_t::BW Member List
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lsb (defined in uint16_t_uint8_t::BW)uint16_t_uint8_t::BW
msb (defined in uint16_t_uint8_t::BW)uint16_t_uint8_t::BW
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+ + diff --git a/structuint16__t__uint8__t_1_1_b_w.html b/structuint16__t__uint8__t_1_1_b_w.html new file mode 100644 index 0000000..8a015e3 --- /dev/null +++ b/structuint16__t__uint8__t_1_1_b_w.html @@ -0,0 +1,119 @@ + + + + + + +discoverpixy: uint16_t_uint8_t::BW Struct Reference + + + + + + + + + + +
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uint16_t_uint8_t::BW Struct Reference
USBH_LIB » USBH_LIB_CORE
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+Public Attributes

+uint8_t msb
 
+uint8_t lsb
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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usb_setup_req Member List
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This is the complete list of members for usb_setup_req, including all inherited members.

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bmRequest (defined in usb_setup_req)usb_setup_req
bRequest (defined in usb_setup_req)usb_setup_req
wIndex (defined in usb_setup_req)usb_setup_req
wLength (defined in usb_setup_req)usb_setup_req
wValue (defined in usb_setup_req)usb_setup_req
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usb_setup_req Struct Reference
USB_OTG_DRIVER » USB_CORE » USB_CORE_Exported_Types
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+Public Attributes

+uint8_t bmRequest
 
+uint8_t bRequest
 
+uint16_t wValue
 
+uint16_t wIndex
 
+uint16_t wLength
 
+
The documentation for this struct was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h
    • +
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system.c File Reference
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#include "system.h"
+#include "ll_system.h"
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+Include dependency graph for system.c:
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bool system_init ()
 
void system_delay (uint32_t msec)
 
void system_process ()
 
void system_toggle_led ()
 
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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system.h File Reference
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#include <stdbool.h>
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bool system_init ()
 
void system_delay (uint32_t msec)
 
void system_process ()
 
void system_toggle_led ()
 
+
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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system.h
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+Go to the documentation of this file.
1 #ifndef SYSTEM_H
+
2 #define SYSTEM_H
+
3 
+
9 
+
10 
+
11 #include <stdbool.h>
+
12 #include <stdint.h>
+
13 
+
18 bool system_init();
+
19 
+
24 void system_delay(uint32_t msec);
+
25 
+
29 void system_process();
+
30 
+
34 void system_toggle_led();
+
35 
+
38 #endif /* SYSTEM_H */
+
system_delay
void system_delay(uint32_t msec)
Definition: system.c:9
+
system_toggle_led
void system_toggle_led()
Definition: system.c:17
+
system_init
bool system_init()
Definition: system.c:5
+
system_process
void system_process()
Definition: system.c:13
+
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system_stm32f4xx.c File Reference
+
+
+ +

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32F4xx devices, and is generated by the clock configuration tool stm32f4xx_Clock_Configuration_V1.0.0.xls. +More...

+
#include "stm32f4xx.h"
+
+Include dependency graph for system_stm32f4xx.c:
+
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+ + + + + + + + + + + +

+Macros

#define VECT_TAB_OFFSET   0x00
 
+#define PLL_M   8
 
+#define PLL_N   336
 
+#define PLL_P   2
 
+#define PLL_Q   7
 
+ + + + + + + +

+Functions

void SystemInit (void)
 Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. More...
 
void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters. More...
 
+ + + + + +

+Variables

+uint32_t SystemCoreClock = 168000000
 
+__I uint8_t AHBPrescTable [16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
 
+

Detailed Description

+

CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32F4xx devices, and is generated by the clock configuration tool stm32f4xx_Clock_Configuration_V1.0.0.xls.

+
Author
MCD Application Team
+
Version
V1.0.0
+
Date
19-September-2011
    +
  1. This file provides two functions and one global variable to be called from user application:
      +
    • SystemInit(): Setups the system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings), depending on the configuration made in the clock xls tool. This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f4xx.s" file.
      • +
    • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.
      • +
    • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.
      • +
    +
    2. +
  2. After each device reset the HSI (16 MHz) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to configure the system clock before to branch to main program.
    3. +
  3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.
    4. +
  4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define in "stm32f4xx.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.
    5. +
+
+

5. This file configures the system clock as follows:

+

=============================================================================

Supported STM32F4xx device revision | Rev A

+

System Clock source | PLL (HSE)

+

SYSCLK(Hz) | 168000000

+

HCLK(Hz) | 168000000

+

AHB Prescaler | 1

+

APB1 Prescaler | 4

+

APB2 Prescaler | 2

+

HSE Frequency(Hz) | 8000000

+

PLL_M | 8

+

PLL_N | 336

+

PLL_P | 2

+

PLL_Q | 7

+

PLLI2S_N | NA

+

PLLI2S_R | NA

+

I2S input clock | NA

+

VDD(V) | 3.3

+

High Performance mode | Enabled

+

Flash Latency(WS) | 5

+

Prefetch Buffer | OFF

+

Instruction cache | ON

+

Data cache | ON

+

Require 48MHz for USB OTG FS, | Enabled

SDIO and RNG clock |

+

=============================================================================

+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
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system_stm32f4xx.h File Reference
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+ +

CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. +More...

+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + +

+Functions

void SystemInit (void)
 Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable. More...
 
void SystemCoreClockUpdate (void)
 Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters. More...
 
+ + + +

+Variables

uint32_t SystemCoreClock
 
+

Detailed Description

+

CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.

+
Author
MCD Application Team
+
Version
V1.4.0
+
Date
04-August-2014
+
Attention
+

© COPYRIGHT 2014 STMicroelectronics

+

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: 

   http://www.st.com/software_license_agreement_liberty_v2
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+
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system_stm32f4xx.h
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1 
+
39 #ifndef __SYSTEM_STM32F4XX_H
+
40 #define __SYSTEM_STM32F4XX_H
+
41 
+
42 #ifdef __cplusplus
+
43  extern "C" {
+
44 #endif
+
45 
+
59 extern uint32_t SystemCoreClock;
+
86 extern void SystemInit(void);
+
87 extern void SystemCoreClockUpdate(void);
+
92 #ifdef __cplusplus
+
93 }
+
94 #endif
+
95 
+
96 #endif /*__SYSTEM_STM32F4XX_H */
+
97 
+
105 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
SystemCoreClockUpdate
void SystemCoreClockUpdate(void)
Update SystemCoreClock variable according to Clock Register Values. The SystemCoreClock variable cont...
Definition: system_stm32f4xx.c:278
+
SystemCoreClock
uint32_t SystemCoreClock
Definition: system_stm32f4xx.c:173
+
SystemInit
void SystemInit(void)
Setup the microcontroller system Initialize the Embedded Flash Interface, the PLL and update the Syst...
Definition: system_stm32f4xx.c:205
+
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bool tft_init ()
 
void tft_clear (uint16_t color)
 
void tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t tft_num_fonts ()
 
uint8_t tft_font_height (uint8_t fontnum)
 
uint8_t tft_font_width (uint8_t fontnum)
 
void tft_print_line (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *text)
 
void tft_print_formatted (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *format,...)
 
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+ + + + + + +
+
discoverpixy +
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+ + +
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+
+Macros | +Functions
+
+
tft.h File Reference
+
+
+
#include <stdbool.h>
+#include <stdint.h>
+
+Include dependency graph for tft.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
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+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + +

+Macros

#define RGB(r, g, b)   ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3))
 
#define RED   RGB(255,0,0)
 
#define GREEN   RGB(0,255,0)
 
#define BLUE   RGB(0,0,255)
 
#define WHITE   0xF7BE
 
#define BLACK   RGB(0,0,0)
 
#define HEX(h)   (RGB(((h)>>16),((h)>>8),(h)))
 
#define TRANSPARENT   ((uint16_t)0x80C2)
 
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+Functions

bool tft_init ()
 
void tft_clear (uint16_t color)
 
void tft_draw_line (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_pixel (uint16_t x, uint16_t y, uint16_t color)
 
void tft_draw_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_fill_rectangle (uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
 
void tft_draw_bitmap_unscaled (uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
 
void tft_draw_circle (uint16_t x, uint16_t y, uint16_t r, uint16_t color)
 
uint8_t tft_num_fonts ()
 
uint8_t tft_font_height (uint8_t fontnum)
 
uint8_t tft_font_width (uint8_t fontnum)
 
void tft_print_line (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *text)
 
void tft_print_formatted (uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *format,...)
 
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+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
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+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
tft.h
+
+
+Go to the documentation of this file.
1 #ifndef TFT_H
+
2 #define TFT_H
+
3 
+
14 
+
15 
+
16 #include<stdbool.h>
+
17 #include<stdint.h>
+
18 
+
23 #define RGB(r,g,b) ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3))
+
24 
+
25 #define RED RGB(255,0,0)
+
26 #define GREEN RGB(0,255,0)
+
27 #define BLUE RGB(0,0,255)
+
28 #define WHITE 0xF7BE
+
29 #define BLACK RGB(0,0,0)
+
30 
+
35 #define HEX(h) (RGB(((h)>>16),((h)>>8),(h)))
+
36 
+
41 #define TRANSPARENT ((uint16_t)0x80C2)
+
42 
+
48 bool tft_init();
+
49 
+
54 void tft_clear(uint16_t color);
+
55 
+
64 void tft_draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color);
+
65 
+
72 void tft_draw_pixel(uint16_t x,uint16_t y,uint16_t color);
+
73 
+
83 void tft_draw_rectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint16_t color);
+
84 
+
93 void tft_fill_rectangle(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2, uint16_t color);
+
94 
+
104 void tft_draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t* dat);
+
105 
+
113 void tft_draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color);
+
114 
+
119 uint8_t tft_num_fonts();
+
120 
+
126 uint8_t tft_font_height(uint8_t fontnum);
+
127 
+
133 uint8_t tft_font_width(uint8_t fontnum);
+
134 
+
144 void tft_print_line(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char* text);
+
145 
+
155 void tft_print_formatted(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char* format, ...);
+
156 
+
159 #endif /* TFT_H */
+
tft_font_height
uint8_t tft_font_height(uint8_t fontnum)
Definition: tft.c:46
+
tft_font_width
uint8_t tft_font_width(uint8_t fontnum)
Definition: tft.c:50
+
tft_draw_circle
void tft_draw_circle(uint16_t x, uint16_t y, uint16_t r, uint16_t color)
Definition: tft.c:38
+
tft_draw_line
void tft_draw_line(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: tft.c:16
+
tft_print_formatted
void tft_print_formatted(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *format,...)
Definition: tft.c:62
+
tft_print_line
void tft_print_line(uint16_t x, uint16_t y, uint16_t color, uint16_t bgcolor, uint8_t font, const char *text)
Definition: tft.c:54
+
tft_num_fonts
uint8_t tft_num_fonts()
Definition: tft.c:42
+
tft_draw_bitmap_unscaled
void tft_draw_bitmap_unscaled(uint16_t x, uint16_t y, uint16_t width, uint16_t height, const uint16_t *dat)
Definition: tft.c:34
+
tft_draw_pixel
void tft_draw_pixel(uint16_t x, uint16_t y, uint16_t color)
Definition: tft.c:21
+
tft_clear
void tft_clear(uint16_t color)
Definition: tft.c:12
+
tft_fill_rectangle
void tft_fill_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: tft.c:30
+
tft_draw_rectangle
void tft_draw_rectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color)
Definition: tft.c:25
+
tft_init
bool tft_init()
Definition: tft.c:7
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/timer_8hpp_source.html b/timer_8hpp_source.html new file mode 100644 index 0000000..d475470 --- /dev/null +++ b/timer_8hpp_source.html @@ -0,0 +1,143 @@ + + + + + + +discoverpixy: emulator/libs/Pixy/src/timer.hpp Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
timer.hpp
+
+
+
1 //
+
2 // begin license header
+
3 //
+
4 // This file is part of Pixy CMUcam5 or "Pixy" for short
+
5 //
+
6 // All Pixy source code is provided under the terms of the
+
7 // GNU General Public License v2 (http://www.gnu.org/licenses/gpl-2.0.html).
+
8 // Those wishing to use Pixy source code, software and/or
+
9 // technologies under different licensing terms should contact us at
+
10 // cmucam@cs.cmu.edu. Such licensing terms are available for
+
11 // all portions of the Pixy codebase presented here.
+
12 //
+
13 // end license header
+
14 //
+
15 
+
16 #ifndef __TIMER_HPP__
+
17 #define __TIMER_HPP__
+
18 
+
19 #include <stdint.h>
+
20 #include <string>
+
21 #include <boost/chrono.hpp>
+
22 
+
23 namespace util
+
24 {
+
25  class timer
+
26  {
+
27  public:
+
28 
+
29  timer();
+
30 
+
31  void reset();
+
32  uint32_t elapsed();
+
33 
+
34  private:
+
35 
+
36  boost::chrono::steady_clock::time_point epoch_;
+
37  };
+
38 }
+
39 
+
40 #endif
+
util
Definition: timer.hpp:23
+
util::timer
Definition: timer.hpp:25
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/touch_8c.html b/touch_8c.html new file mode 100644 index 0000000..5af3a12 --- /dev/null +++ b/touch_8c.html @@ -0,0 +1,194 @@ + + + + + + +discoverpixy: common/touch/touch.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions | +Variables
+
+
touch.c File Reference
+
+
+
#include "touch.h"
+#include "ll_touch.h"
+#include <stdio.h>
+
+Include dependency graph for touch.c:
+
+
+ + +
+
+ + + +

+Macros

#define NUM_AREAS   50
 
+ + + + + + + + + + + + + +

+Functions

bool touch_init ()
 
bool touch_add_raw_event (uint16_t touchX, uint16_t touchY, TOUCH_STATE state)
 
bool touch_have_empty (unsigned char num)
 
bool touch_register_area (TOUCH_AREA_STRUCT *area)
 
void touch_unregister_area (TOUCH_AREA_STRUCT *area)
 
POINT_STRUCT touch_get_last_point ()
 
+ + + + + + + +

+Variables

TOUCH_AREA_STRUCT * areas [NUM_AREAS] = {NULL}
 
volatile POINT_STRUCT pos
 
volatile TOUCH_STATE oldState =TOUCH_UP
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define NUM_AREAS   50
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
TOUCH_AREA_STRUCT* areas[NUM_AREAS] = {NULL}
+
+ +
+
+ +
+
+ + + + +
volatile TOUCH_STATE oldState =TOUCH_UP
+
+ +
+
+ +
+
+ + + + +
volatile POINT_STRUCT pos
+
+ +
+
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/touch_8c__incl.map b/touch_8c__incl.map new file mode 100644 index 0000000..7c01948 --- /dev/null +++ b/touch_8c__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/touch_8c__incl.md5 b/touch_8c__incl.md5 new file mode 100644 index 0000000..160f5d9 --- /dev/null +++ b/touch_8c__incl.md5 @@ -0,0 +1 @@ +3128455e476f91399bb5c27e9da3efc1 \ No newline at end of file diff --git a/touch_8c__incl.png b/touch_8c__incl.png new file mode 100644 index 0000000..924b4ac Binary files /dev/null and b/touch_8c__incl.png differ diff --git a/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.map b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.map new file mode 100644 index 0000000..ee33ad9 --- /dev/null +++ b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.md5 b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.md5 new file mode 100644 index 0000000..b431667 --- /dev/null +++ b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.md5 @@ -0,0 +1 @@ +c6d5f2ec1641e87d307b10571ba8b529 \ No newline at end of file diff --git a/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.png b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.png new file mode 100644 index 0000000..50d9d92 Binary files /dev/null and b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_cgraph.png differ diff --git a/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.map b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.map new file mode 100644 index 0000000..de1aa9a --- /dev/null +++ b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.md5 b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.md5 new file mode 100644 index 0000000..2102edc --- /dev/null +++ b/touch_8c_a0ff491e3e07321fef794d4f07b103c0f_icgraph.md5 @@ -0,0 +1 @@ +557fe5c7e45ccbae908437361aa09b8f \ No newline at end of file diff --git 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a/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.md5 b/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.md5 new file mode 100644 index 0000000..014c1a8 --- /dev/null +++ b/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.md5 @@ -0,0 +1 @@ +eac3d1a280b68e9bc502a26368f8e995 \ No newline at end of file diff --git a/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.png b/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.png new file mode 100644 index 0000000..81b83a3 Binary files /dev/null and b/touch_8c_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.png differ diff --git a/touch_8h.html b/touch_8h.html new file mode 100644 index 0000000..e7b1205 --- /dev/null +++ b/touch_8h.html @@ -0,0 +1,167 @@ + + + + + + +discoverpixy: common/touch/touch.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Data Structures | +Typedefs | +Enumerations | +Functions
+
+
touch.h File Reference
+
+
+
#include <stdbool.h>
+#include <stdint.h>
+
+Include dependency graph for touch.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + +

+Data Structures

struct  TOUCH_AREA_STRUCT
 
struct  POINT_STRUCT
 
+ + + +

+Typedefs

typedef void(* TOUCH_CALLBACK) (void *touchArea, TOUCH_ACTION triggeredAction)
 
+ + + + + +

+Enumerations

enum  TOUCH_STATE { TOUCH_UP, +TOUCH_DOWN + }
 
enum  TOUCH_ACTION {
+  NONE =0x00, +PEN_DOWN =0x01, +PEN_UP =0x02, +PEN_ENTER =0x04, +
+  PEN_LEAVE =0x08, +PEN_MOVE =0x10 +
+ }
 
+ + + + + + + + + + + + + +

+Functions

bool touch_init ()
 
bool touch_add_raw_event (uint16_t x, uint16_t y, TOUCH_STATE state)
 
bool touch_have_empty (unsigned char num)
 
bool touch_register_area (TOUCH_AREA_STRUCT *area)
 
void touch_unregister_area (TOUCH_AREA_STRUCT *area)
 
POINT_STRUCT touch_get_last_point ()
 
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/touch_8h__dep__incl.map b/touch_8h__dep__incl.map new file mode 100644 index 0000000..ee944c4 --- /dev/null +++ b/touch_8h__dep__incl.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/touch_8h__dep__incl.md5 b/touch_8h__dep__incl.md5 new file mode 100644 index 0000000..da4ad93 --- /dev/null +++ b/touch_8h__dep__incl.md5 @@ -0,0 +1 @@ +9e1ed1b5317f2118c11fbe6188044a5e \ No newline at end of file diff --git a/touch_8h__dep__incl.png b/touch_8h__dep__incl.png new file mode 100644 index 0000000..86d1a91 Binary files /dev/null and b/touch_8h__dep__incl.png differ diff --git a/touch_8h__incl.map b/touch_8h__incl.map new file mode 100644 index 0000000..9a618ef --- /dev/null +++ b/touch_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/touch_8h__incl.md5 b/touch_8h__incl.md5 new file mode 100644 index 0000000..d8f173a --- /dev/null +++ b/touch_8h__incl.md5 @@ -0,0 +1 @@ +479d05c1a1fa3edfad1b2b40929d5241 \ No newline at end of file diff --git a/touch_8h__incl.png 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b/touch_8h_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.png new file mode 100644 index 0000000..81b83a3 Binary files /dev/null and b/touch_8h_ad32e5d122ec3f5f88bc6b2d9f4a629f8_icgraph.png differ diff --git a/touch_8h_source.html b/touch_8h_source.html new file mode 100644 index 0000000..cff402a --- /dev/null +++ b/touch_8h_source.html @@ -0,0 +1,182 @@ + + + + + + +discoverpixy: common/touch/touch.h Source File + + + + + + + + + + +
+
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+
touch.h
+
+
+Go to the documentation of this file.
1 #ifndef TOUCH_H
+
2 #define TOUCH_H
+
3 
+
14 
+
15 
+
16 #include<stdbool.h>
+
17 #include<stdint.h>
+
18 
+
22 typedef enum {
+
23  TOUCH_UP,
+
24  TOUCH_DOWN
+
25 } TOUCH_STATE ;
+
26 
+
31 typedef enum {
+
32  NONE=0x00,
+
33  PEN_DOWN=0x01,
+
34  PEN_UP=0x02,
+
35  PEN_ENTER=0x04,
+
36  PEN_LEAVE=0x08,
+
37  PEN_MOVE=0x10
+
38 } TOUCH_ACTION;
+
39 
+
45 typedef void (*TOUCH_CALLBACK)(void* touchArea, TOUCH_ACTION triggeredAction);
+
46 
+
50 typedef struct {
+
51  TOUCH_ACTION hookedActions;
+
52  uint16_t x1;
+
53  uint16_t y1;
+
54  uint16_t x2;
+
55  uint16_t y2;
+
56  TOUCH_CALLBACK callback;
+
57  uint8_t flags;
+
58 } TOUCH_AREA_STRUCT;
+
59 
+
60 
+
64 typedef struct {
+
65  uint16_t x;
+
66  uint16_t y;
+
67 } POINT_STRUCT;
+
68 
+
74 bool touch_init();
+
75 
+
85 bool touch_add_raw_event(uint16_t x, uint16_t y,TOUCH_STATE state);
+
86 
+
92 bool touch_have_empty(unsigned char num);
+
93 
+
99 bool touch_register_area(TOUCH_AREA_STRUCT* area);
+
100 
+
105 void touch_unregister_area(TOUCH_AREA_STRUCT* area);
+
106 
+
111 POINT_STRUCT touch_get_last_point();
+
112 
+
113 
+
116 #endif /* TOUCH_H */
+
TOUCH_ACTION
TOUCH_ACTION
Definition: touch.h:31
+
touch_register_area
bool touch_register_area(TOUCH_AREA_STRUCT *area)
Definition: touch.c:103
+
PEN_MOVE
Receive an event when the pen moves inside the region (pen is down)
Definition: touch.h:37
+
PEN_DOWN
Receive an event when the pen goes down inside the region.
Definition: touch.h:33
+
TOUCH_CALLBACK
void(* TOUCH_CALLBACK)(void *touchArea, TOUCH_ACTION triggeredAction)
Definition: touch.h:45
+
PEN_UP
Receive an event when the pen goes up inside the region.
Definition: touch.h:34
+
TOUCH_AREA_STRUCT::y1
uint16_t y1
Top Left Y-Coordinate of Area.
Definition: touch.h:53
+
POINT_STRUCT::y
uint16_t y
The Y-Coordinate of the point.
Definition: touch.h:66
+
TOUCH_AREA_STRUCT::flags
uint8_t flags
For internal Used, don't change, don't initialize.
Definition: touch.h:57
+
POINT_STRUCT::x
uint16_t x
The X-Coordinate of the point.
Definition: touch.h:65
+
TOUCH_AREA_STRUCT::x1
uint16_t x1
Top Left X-Coordinate of Area.
Definition: touch.h:52
+
touch_unregister_area
void touch_unregister_area(TOUCH_AREA_STRUCT *area)
Definition: touch.c:118
+
TOUCH_AREA_STRUCT
Definition: touch.h:50
+
touch_add_raw_event
bool touch_add_raw_event(uint16_t x, uint16_t y, TOUCH_STATE state)
Definition: touch.c:16
+
TOUCH_AREA_STRUCT::y2
uint16_t y2
Bottom Right Y-Coordinate of Area.
Definition: touch.h:55
+
TOUCH_UP
The display is currently not touched.
Definition: touch.h:23
+
TOUCH_DOWN
The display is currently touched at some point.
Definition: touch.h:24
+
TOUCH_AREA_STRUCT::callback
TOUCH_CALLBACK callback
Callback.
Definition: touch.h:56
+
TOUCH_AREA_STRUCT::x2
uint16_t x2
Bottom Right X-Coordinate of Area.
Definition: touch.h:54
+
PEN_ENTER
Receive an event when the pen enters the region (pen was down before)
Definition: touch.h:35
+
touch_get_last_point
POINT_STRUCT touch_get_last_point()
Definition: touch.c:131
+
TOUCH_AREA_STRUCT::hookedActions
TOUCH_ACTION hookedActions
Actions to listen to.
Definition: touch.h:51
+
POINT_STRUCT
Definition: touch.h:64
+
TOUCH_STATE
TOUCH_STATE
Definition: touch.h:22
+
touch_have_empty
bool touch_have_empty(unsigned char num)
Definition: touch.c:93
+
NONE
Do not receive any events.
Definition: touch.h:32
+
touch_init
bool touch_init()
Definition: touch.c:11
+
PEN_LEAVE
Receive an event when the pen leaves the region (pen was inside region before)
Definition: touch.h:36
+
+ +
+Generated on Tue May 12 2015 11:11:45 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ui__mainwindow_8h.html b/ui__mainwindow_8h.html new file mode 100644 index 0000000..59ab360 --- /dev/null +++ b/ui__mainwindow_8h.html @@ -0,0 +1,145 @@ + + + + + + +discoverpixy: emulator/qt/ui_mainwindow.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
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+
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+ + +
+
+
+Data Structures | +Namespaces
+
+
ui_mainwindow.h File Reference
+
+
+
#include <QtCore/QVariant>
+#include <QtWidgets/QAction>
+#include <QtWidgets/QApplication>
+#include <QtWidgets/QButtonGroup>
+#include <QtWidgets/QComboBox>
+#include <QtWidgets/QFrame>
+#include <QtWidgets/QHBoxLayout>
+#include <QtWidgets/QHeaderView>
+#include <QtWidgets/QLabel>
+#include <QtWidgets/QMainWindow>
+#include <QtWidgets/QPushButton>
+#include <QtWidgets/QSpacerItem>
+#include <QtWidgets/QVBoxLayout>
+#include <QtWidgets/QWidget>
+
+Include dependency graph for ui_mainwindow.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + +

+Data Structures

class  Ui_MainWindow
 
class  MainWindow
 
+ + + +

+Namespaces

 Ui
 
+
+ +
+Generated on Sun May 10 2015 15:25:38 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/ui__mainwindow_8h__dep__incl.map b/ui__mainwindow_8h__dep__incl.map new file mode 100644 index 0000000..aba4e3c --- /dev/null +++ b/ui__mainwindow_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/ui__mainwindow_8h__dep__incl.md5 b/ui__mainwindow_8h__dep__incl.md5 new file mode 100644 index 0000000..4d4707c --- /dev/null +++ b/ui__mainwindow_8h__dep__incl.md5 @@ -0,0 +1 @@ +34ab5c32528ef7d2a8c2186a1a361a19 \ No newline at end of file diff --git a/ui__mainwindow_8h__dep__incl.png b/ui__mainwindow_8h__dep__incl.png new file mode 100644 index 0000000..f937aff Binary files /dev/null and b/ui__mainwindow_8h__dep__incl.png differ diff --git a/ui__mainwindow_8h__incl.map b/ui__mainwindow_8h__incl.map new file mode 100644 index 0000000..e819b66 --- /dev/null +++ b/ui__mainwindow_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/ui__mainwindow_8h__incl.md5 b/ui__mainwindow_8h__incl.md5 new file mode 100644 index 0000000..edae083 --- /dev/null +++ b/ui__mainwindow_8h__incl.md5 @@ -0,0 +1 @@ +c01695bfbc0735af8305cc32ff7f0ae3 \ No newline at end of file diff --git a/ui__mainwindow_8h__incl.png b/ui__mainwindow_8h__incl.png new file mode 100644 index 0000000..22a7f8f Binary files /dev/null and b/ui__mainwindow_8h__incl.png differ diff --git a/ui__mainwindow_8h_source.html b/ui__mainwindow_8h_source.html new file mode 100644 index 0000000..5bf6cd3 --- /dev/null +++ b/ui__mainwindow_8h_source.html @@ -0,0 +1,237 @@ + + + + + + +discoverpixy: emulator/qt/ui_mainwindow.h Source File + + + + + + + + + + +
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ui_mainwindow.h
+
+
+Go to the documentation of this file.
1 /********************************************************************************
+
2 ** Form generated from reading UI file 'mainwindow.ui'
+
3 **
+
4 ** Created by: Qt User Interface Compiler version 5.4.1
+
5 **
+
6 ** WARNING! All changes made in this file will be lost when recompiling UI file!
+
7 ********************************************************************************/
+
8 
+
9 #ifndef UI_MAINWINDOW_H
+
10 #define UI_MAINWINDOW_H
+
11 
+
12 #include <QtCore/QVariant>
+
13 #include <QtWidgets/QAction>
+
14 #include <QtWidgets/QApplication>
+
15 #include <QtWidgets/QButtonGroup>
+
16 #include <QtWidgets/QComboBox>
+
17 #include <QtWidgets/QFrame>
+
18 #include <QtWidgets/QHBoxLayout>
+
19 #include <QtWidgets/QHeaderView>
+
20 #include <QtWidgets/QLabel>
+
21 #include <QtWidgets/QMainWindow>
+
22 #include <QtWidgets/QPushButton>
+
23 #include <QtWidgets/QSpacerItem>
+
24 #include <QtWidgets/QVBoxLayout>
+
25 #include <QtWidgets/QWidget>
+
26 
+
27 QT_BEGIN_NAMESPACE
+
28 
+
29 class Ui_MainWindow
+
30 {
+
31 public:
+
32  QWidget *centralwidget;
+
33  QVBoxLayout *verticalLayout;
+
34  QHBoxLayout *horizontalLayout;
+
35  QLabel *label;
+
36  QComboBox *cboZoom;
+
37  QSpacerItem *horizontalSpacer;
+
38  QPushButton *btnExit;
+
39  QFrame *line;
+
40  QWidget *widgetDisplay;
+
41 
+
42  void setupUi(QMainWindow *MainWindow)
+
43  {
+
44  if (MainWindow->objectName().isEmpty())
+
45  MainWindow->setObjectName(QStringLiteral("MainWindow"));
+
46  MainWindow->resize(980, 778);
+
47  centralwidget = new QWidget(MainWindow);
+
48  centralwidget->setObjectName(QStringLiteral("centralwidget"));
+
49  verticalLayout = new QVBoxLayout(centralwidget);
+
50  verticalLayout->setObjectName(QStringLiteral("verticalLayout"));
+
51  horizontalLayout = new QHBoxLayout();
+
52  horizontalLayout->setObjectName(QStringLiteral("horizontalLayout"));
+
53  label = new QLabel(centralwidget);
+
54  label->setObjectName(QStringLiteral("label"));
+
55 
+
56  horizontalLayout->addWidget(label);
+
57 
+
58  cboZoom = new QComboBox(centralwidget);
+
59  cboZoom->setObjectName(QStringLiteral("cboZoom"));
+
60 
+
61  horizontalLayout->addWidget(cboZoom);
+
62 
+
63  horizontalSpacer = new QSpacerItem(40, 20, QSizePolicy::Expanding, QSizePolicy::Minimum);
+
64 
+
65  horizontalLayout->addItem(horizontalSpacer);
+
66 
+
67  btnExit = new QPushButton(centralwidget);
+
68  btnExit->setObjectName(QStringLiteral("btnExit"));
+
69 
+
70  horizontalLayout->addWidget(btnExit);
+
71 
+
72 
+
73  verticalLayout->addLayout(horizontalLayout);
+
74 
+
75  line = new QFrame(centralwidget);
+
76  line->setObjectName(QStringLiteral("line"));
+
77  line->setFrameShape(QFrame::HLine);
+
78  line->setFrameShadow(QFrame::Sunken);
+
79 
+
80  verticalLayout->addWidget(line);
+
81 
+
82  widgetDisplay = new QWidget(centralwidget);
+
83  widgetDisplay->setObjectName(QStringLiteral("widgetDisplay"));
+
84  QSizePolicy sizePolicy(QSizePolicy::Preferred, QSizePolicy::Expanding);
+
85  sizePolicy.setHorizontalStretch(0);
+
86  sizePolicy.setVerticalStretch(0);
+
87  sizePolicy.setHeightForWidth(widgetDisplay->sizePolicy().hasHeightForWidth());
+
88  widgetDisplay->setSizePolicy(sizePolicy);
+
89 
+
90  verticalLayout->addWidget(widgetDisplay);
+
91 
+
92  MainWindow->setCentralWidget(centralwidget);
+
93 
+
94  retranslateUi(MainWindow);
+
95  QObject::connect(btnExit, SIGNAL(clicked()), MainWindow, SLOT(close()));
+
96 
+
97  QMetaObject::connectSlotsByName(MainWindow);
+
98  } // setupUi
+
99 
+
100  void retranslateUi(QMainWindow *MainWindow)
+
101  {
+
102  MainWindow->setWindowTitle(QApplication::translate("MainWindow", "DiscoverPixy Emulator", 0));
+
103  label->setText(QApplication::translate("MainWindow", "Zoom", 0));
+
104  cboZoom->clear();
+
105  cboZoom->insertItems(0, QStringList()
+
106  << QApplication::translate("MainWindow", "1x", 0)
+
107  << QApplication::translate("MainWindow", "2x", 0)
+
108  << QApplication::translate("MainWindow", "3x", 0)
+
109  );
+
110  btnExit->setText(QApplication::translate("MainWindow", "Exit", 0));
+
111  } // retranslateUi
+
112 
+
113 };
+
114 
+
115 namespace Ui {
+
116  class MainWindow: public Ui_MainWindow {};
+
117 } // namespace Ui
+
118 
+
119 QT_END_NAMESPACE
+
120 
+
121 #endif // UI_MAINWINDOW_H
+
Ui_MainWindow::horizontalLayout
QHBoxLayout * horizontalLayout
Definition: ui_mainwindow.h:34
+
Ui_MainWindow::centralwidget
QWidget * centralwidget
Definition: ui_mainwindow.h:32
+
Ui_MainWindow::label
QLabel * label
Definition: ui_mainwindow.h:35
+
Ui
Definition: mainwindow.h:8
+
Ui_MainWindow::line
QFrame * line
Definition: ui_mainwindow.h:39
+
Ui_MainWindow::horizontalSpacer
QSpacerItem * horizontalSpacer
Definition: ui_mainwindow.h:37
+
Ui_MainWindow::cboZoom
QComboBox * cboZoom
Definition: ui_mainwindow.h:36
+
Ui_MainWindow::retranslateUi
void retranslateUi(QMainWindow *MainWindow)
Definition: ui_mainwindow.h:100
+
Ui_MainWindow
Definition: ui_mainwindow.h:29
+
Ui_MainWindow::widgetDisplay
QWidget * widgetDisplay
Definition: ui_mainwindow.h:40
+
Ui_MainWindow::verticalLayout
QVBoxLayout * verticalLayout
Definition: ui_mainwindow.h:33
+
Ui_MainWindow::btnExit
QPushButton * btnExit
Definition: ui_mainwindow.h:38
+
Ui::MainWindow
Definition: ui_mainwindow.h:116
+
MainWindow
Definition: mainwindow.h:12
+
Ui_MainWindow::setupUi
void setupUi(QMainWindow *MainWindow)
Definition: ui_mainwindow.h:42
+
+ +
+Generated on Sun May 10 2015 15:25:38 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_a_i_n_t___type_def-members.html b/union___u_s_b___o_t_g___d_a_i_n_t___type_def-members.html new file mode 100644 index 0000000..161f672 --- /dev/null +++ b/union___u_s_b___o_t_g___d_a_i_n_t___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DAINT_TypeDef Member List
+
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+ +

This is the complete list of members for _USB_OTG_DAINT_TypeDef, including all inherited members.

+ + + + + +
d32 (defined in _USB_OTG_DAINT_TypeDef)_USB_OTG_DAINT_TypeDef
ep (defined in _USB_OTG_DAINT_TypeDef)_USB_OTG_DAINT_TypeDef
in (defined in _USB_OTG_DAINT_TypeDef)_USB_OTG_DAINT_TypeDef
out (defined in _USB_OTG_DAINT_TypeDef)_USB_OTG_DAINT_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_a_i_n_t___type_def.html b/union___u_s_b___o_t_g___d_a_i_n_t___type_def.html new file mode 100644 index 0000000..7a53e5c --- /dev/null +++ b/union___u_s_b___o_t_g___d_a_i_n_t___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_DAINT_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DAINT_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   in: 16
 
+   uint32_t   out: 16
 
} ep
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_c_f_g___type_def-members.html b/union___u_s_b___o_t_g___d_c_f_g___type_def-members.html new file mode 100644 index 0000000..2018130 --- /dev/null +++ b/union___u_s_b___o_t_g___d_c_f_g___type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DCFG_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DCFG_TypeDef, including all inherited members.

+ + + + + + + + + + +
b (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
d32 (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
devaddr (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
devspd (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
epmscnt (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
nzstsouthshk (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
perfrint (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
Reserved13_17 (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
Reserved3 (defined in _USB_OTG_DCFG_TypeDef)_USB_OTG_DCFG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_c_f_g___type_def.html b/union___u_s_b___o_t_g___d_c_f_g___type_def.html new file mode 100644 index 0000000..cc52292 --- /dev/null +++ b/union___u_s_b___o_t_g___d_c_f_g___type_def.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _USB_OTG_DCFG_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DCFG_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   devspd: 2
 
+   uint32_t   nzstsouthshk: 1
 
+   uint32_t   Reserved3: 1
 
+   uint32_t   devaddr: 7
 
+   uint32_t   perfrint: 2
 
+   uint32_t   Reserved13_17: 5
 
+   uint32_t   epmscnt: 4
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___d_c_t_l___type_def-members.html new file mode 100644 index 0000000..4bed9e0 --- /dev/null +++ b/union___u_s_b___o_t_g___d_c_t_l___type_def-members.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
_USB_OTG_DCTL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DCTL_TypeDef, including all inherited members.

+ + + + + + + + + + + + + +
b (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
cgnpinnak (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
cgoutnak (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
d32 (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
gnpinnaksts (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
goutnaksts (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
Reserved (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
rmtwkupsig (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
sftdiscon (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
sgnpinnak (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
sgoutnak (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
tstctl (defined in _USB_OTG_DCTL_TypeDef)_USB_OTG_DCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_c_t_l___type_def.html b/union___u_s_b___o_t_g___d_c_t_l___type_def.html new file mode 100644 index 0000000..c2d14b8 --- /dev/null +++ b/union___u_s_b___o_t_g___d_c_t_l___type_def.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: _USB_OTG_DCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   rmtwkupsig: 1
 
+   uint32_t   sftdiscon: 1
 
+   uint32_t   gnpinnaksts: 1
 
+   uint32_t   goutnaksts: 1
 
+   uint32_t   tstctl: 3
 
+   uint32_t   sgnpinnak: 1
 
+   uint32_t   cgnpinnak: 1
 
+   uint32_t   sgoutnak: 1
 
+   uint32_t   cgoutnak: 1
 
+   uint32_t   Reserved: 21
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def-members.html b/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def-members.html new file mode 100644 index 0000000..bdceee2 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DEP0XFRSIZ_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DEP0XFRSIZ_TypeDef, including all inherited members.

+ + + + + + + + + +
b (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
d32 (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
pktcnt (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
Reserved20_28 (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
Reserved31 (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
Reserved7_18 (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
supcnt (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
xfersize (defined in _USB_OTG_DEP0XFRSIZ_TypeDef)_USB_OTG_DEP0XFRSIZ_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def.html b/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def.html new file mode 100644 index 0000000..6ee5b28 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p0_x_f_r_s_i_z___type_def.html @@ -0,0 +1,134 @@ + + + + + + +discoverpixy: _USB_OTG_DEP0XFRSIZ_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DEP0XFRSIZ_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfersize: 7
 
+   uint32_t   Reserved7_18: 12
 
+   uint32_t   pktcnt: 2
 
+   uint32_t   Reserved20_28: 9
 
+   uint32_t   supcnt: 2
 
+   uint32_t   Reserved31
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def-members.html new file mode 100644 index 0000000..e9ff9d4 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def-members.html @@ -0,0 +1,119 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DEPCTL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DEPCTL_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
b (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
cnak (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
d32 (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
dpid (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
epdis (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
epena (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
eptype (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
mps (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
naksts (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
reserved (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
setd0pid (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
setd1pid (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
snak (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
snp (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
stall (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
txfnum (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
usbactep (defined in _USB_OTG_DEPCTL_TypeDef)_USB_OTG_DEPCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def.html b/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def.html new file mode 100644 index 0000000..08a9e19 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p_c_t_l___type_def.html @@ -0,0 +1,161 @@ + + + + + + +discoverpixy: _USB_OTG_DEPCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DEPCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   mps: 11
 
+   uint32_t   reserved: 4
 
+   uint32_t   usbactep: 1
 
+   uint32_t   dpid: 1
 
+   uint32_t   naksts: 1
 
+   uint32_t   eptype: 2
 
+   uint32_t   snp: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   txfnum: 4
 
+   uint32_t   cnak: 1
 
+   uint32_t   snak: 1
 
+   uint32_t   setd0pid: 1
 
+   uint32_t   setd1pid: 1
 
+   uint32_t   epdis: 1
 
+   uint32_t   epena: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def-members.html b/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def-members.html new file mode 100644 index 0000000..d963209 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DEPXFRSIZ_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DEPXFRSIZ_TypeDef, including all inherited members.

+ + + + + + + +
b (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
d32 (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
mc (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
pktcnt (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
Reserved (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
xfersize (defined in _USB_OTG_DEPXFRSIZ_TypeDef)_USB_OTG_DEPXFRSIZ_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def.html b/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def.html new file mode 100644 index 0000000..a0495c6 --- /dev/null +++ b/union___u_s_b___o_t_g___d_e_p_x_f_r_s_i_z___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: _USB_OTG_DEPXFRSIZ_TypeDef Union Reference + + + + + + + + + + +
+
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+
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+
_USB_OTG_DEPXFRSIZ_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfersize: 19
 
+   uint32_t   pktcnt: 10
 
+   uint32_t   mc: 2
 
+   uint32_t   Reserved: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def-members.html b/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def-members.html new file mode 100644 index 0000000..468063e --- /dev/null +++ b/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def-members.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
_USB_OTG_DIEPINTn_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DIEPINTn_TypeDef, including all inherited members.

+ + + + + + + + + + + + + +
ahberr (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
b (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
d32 (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
emptyintr (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
epdisabled (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
inepnakeff (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
intknepmis (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
intktxfemp (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
Reserved08_31 (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
timeout (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
txfifoundrn (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
xfercompl (defined in _USB_OTG_DIEPINTn_TypeDef)_USB_OTG_DIEPINTn_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def.html b/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def.html new file mode 100644 index 0000000..af3ecc8 --- /dev/null +++ b/union___u_s_b___o_t_g___d_i_e_p_i_n_tn___type_def.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: _USB_OTG_DIEPINTn_TypeDef Union Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+Public Attributes | +List of all members
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_USB_OTG_DIEPINTn_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   epdisabled: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   timeout: 1
 
+   uint32_t   intktxfemp: 1
 
+   uint32_t   intknepmis: 1
 
+   uint32_t   inepnakeff: 1
 
+   uint32_t   emptyintr: 1
 
+   uint32_t   txfifoundrn: 1
 
+   uint32_t   Reserved08_31: 23
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def-members.html b/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def-members.html new file mode 100644 index 0000000..bced4cb --- /dev/null +++ b/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DOEPINTn_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DOEPINTn_TypeDef, including all inherited members.

+ + + + + + + + +
ahberr (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
b (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
d32 (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
epdisabled (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
Reserved04_31 (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
setup (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
xfercompl (defined in _USB_OTG_DOEPINTn_TypeDef)_USB_OTG_DOEPINTn_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def.html b/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def.html new file mode 100644 index 0000000..428b673 --- /dev/null +++ b/union___u_s_b___o_t_g___d_o_e_p_i_n_tn___type_def.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: _USB_OTG_DOEPINTn_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DOEPINTn_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   epdisabled: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   setup: 1
 
+   uint32_t   Reserved04_31: 28
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def-members.html new file mode 100644 index 0000000..bad42e3 --- /dev/null +++ b/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DRXSTS_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DRXSTS_TypeDef, including all inherited members.

+ + + + + + + + + +
b (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
bcnt (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
d32 (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
dpid (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
epnum (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
fn (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
pktsts (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
Reserved (defined in _USB_OTG_DRXSTS_TypeDef)_USB_OTG_DRXSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def.html b/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def.html new file mode 100644 index 0000000..3d9df34 --- /dev/null +++ b/union___u_s_b___o_t_g___d_r_x_s_t_s___type_def.html @@ -0,0 +1,134 @@ + + + + + + +discoverpixy: _USB_OTG_DRXSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DRXSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   epnum: 4
 
+   uint32_t   bcnt: 11
 
+   uint32_t   dpid: 2
 
+   uint32_t   pktsts: 4
 
+   uint32_t   fn: 4
 
+   uint32_t   Reserved: 7
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___d_s_t_s___type_def-members.html new file mode 100644 index 0000000..cf864c9 --- /dev/null +++ b/union___u_s_b___o_t_g___d_s_t_s___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DSTS_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DSTS_TypeDef, including all inherited members.

+ + + + + + + + + +
b (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
d32 (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
enumspd (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
errticerr (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
Reserved22_31 (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
Reserved4_7 (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
soffn (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
suspsts (defined in _USB_OTG_DSTS_TypeDef)_USB_OTG_DSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_s_t_s___type_def.html b/union___u_s_b___o_t_g___d_s_t_s___type_def.html new file mode 100644 index 0000000..16177da --- /dev/null +++ b/union___u_s_b___o_t_g___d_s_t_s___type_def.html @@ -0,0 +1,134 @@ + + + + + + +discoverpixy: _USB_OTG_DSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   suspsts: 1
 
+   uint32_t   enumspd: 2
 
+   uint32_t   errticerr: 1
 
+   uint32_t   Reserved4_7: 4
 
+   uint32_t   soffn: 14
 
+   uint32_t   Reserved22_31: 10
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def-members.html new file mode 100644 index 0000000..aea7816 --- /dev/null +++ b/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DTHRCTL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DTHRCTL_TypeDef, including all inherited members.

+ + + + + + + + + + +
b (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
d32 (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
iso_thr_en (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
non_iso_thr_en (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
Reserved11_15 (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
Reserved26_31 (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
rx_thr_en (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
rx_thr_len (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
tx_thr_len (defined in _USB_OTG_DTHRCTL_TypeDef)_USB_OTG_DTHRCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def.html b/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def.html new file mode 100644 index 0000000..b2d04f5 --- /dev/null +++ b/union___u_s_b___o_t_g___d_t_h_r_c_t_l___type_def.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _USB_OTG_DTHRCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DTHRCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   non_iso_thr_en: 1
 
+   uint32_t   iso_thr_en: 1
 
+   uint32_t   tx_thr_len: 9
 
+   uint32_t   Reserved11_15: 5
 
+   uint32_t   rx_thr_en: 1
 
+   uint32_t   rx_thr_len: 9
 
+   uint32_t   Reserved26_31: 6
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def-members.html b/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def-members.html new file mode 100644 index 0000000..3440034 --- /dev/null +++ b/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_DTXFSTSn_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_DTXFSTSn_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_DTXFSTSn_TypeDef)_USB_OTG_DTXFSTSn_TypeDef
d32 (defined in _USB_OTG_DTXFSTSn_TypeDef)_USB_OTG_DTXFSTSn_TypeDef
Reserved (defined in _USB_OTG_DTXFSTSn_TypeDef)_USB_OTG_DTXFSTSn_TypeDef
txfspcavail (defined in _USB_OTG_DTXFSTSn_TypeDef)_USB_OTG_DTXFSTSn_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def.html b/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def.html new file mode 100644 index 0000000..6264acd --- /dev/null +++ b/union___u_s_b___o_t_g___d_t_x_f_s_t_sn___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_DTXFSTSn_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_DTXFSTSn_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   txfspcavail: 16
 
+   uint32_t   Reserved: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___f_s_i_z___type_def-members.html b/union___u_s_b___o_t_g___f_s_i_z___type_def-members.html new file mode 100644 index 0000000..096136e --- /dev/null +++ b/union___u_s_b___o_t_g___f_s_i_z___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_FSIZ_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_FSIZ_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_FSIZ_TypeDef)_USB_OTG_FSIZ_TypeDef
d32 (defined in _USB_OTG_FSIZ_TypeDef)_USB_OTG_FSIZ_TypeDef
depth (defined in _USB_OTG_FSIZ_TypeDef)_USB_OTG_FSIZ_TypeDef
startaddr (defined in _USB_OTG_FSIZ_TypeDef)_USB_OTG_FSIZ_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___f_s_i_z___type_def.html b/union___u_s_b___o_t_g___f_s_i_z___type_def.html new file mode 100644 index 0000000..bfc150c --- /dev/null +++ b/union___u_s_b___o_t_g___f_s_i_z___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_FSIZ_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_FSIZ_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   startaddr: 16
 
+   uint32_t   depth: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def-members.html b/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def-members.html new file mode 100644 index 0000000..184da7a --- /dev/null +++ b/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GAHBCFG_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GAHBCFG_TypeDef, including all inherited members.

+ + + + + + + + + + +
b (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
d32 (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
dmaenable (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
glblintrmsk (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
hburstlen (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
nptxfemplvl_txfemplvl (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
ptxfemplvl (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
Reserved (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
Reserved9_31 (defined in _USB_OTG_GAHBCFG_TypeDef)_USB_OTG_GAHBCFG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def.html b/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def.html new file mode 100644 index 0000000..ecf1e2f --- /dev/null +++ b/union___u_s_b___o_t_g___g_a_h_b_c_f_g___type_def.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _USB_OTG_GAHBCFG_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GAHBCFG_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   glblintrmsk: 1
 
+   uint32_t   hburstlen: 4
 
+   uint32_t   dmaenable: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   nptxfemplvl_txfemplvl: 1
 
+   uint32_t   ptxfemplvl: 1
 
+   uint32_t   Reserved9_31: 23
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_c_c_f_g___type_def-members.html b/union___u_s_b___o_t_g___g_c_c_f_g___type_def-members.html new file mode 100644 index 0000000..6a31fe0 --- /dev/null +++ b/union___u_s_b___o_t_g___g_c_c_f_g___type_def-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GCCFG_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GCCFG_TypeDef, including all inherited members.

+ + + + + + + + + + + +
b (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
d32 (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
disablevbussensing (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
i2cifen (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
pwdn (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
Reserved_in (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
Reserved_out (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
sofouten (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
vbussensingA (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
vbussensingB (defined in _USB_OTG_GCCFG_TypeDef)_USB_OTG_GCCFG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_c_c_f_g___type_def.html b/union___u_s_b___o_t_g___g_c_c_f_g___type_def.html new file mode 100644 index 0000000..e2d67d7 --- /dev/null +++ b/union___u_s_b___o_t_g___g_c_c_f_g___type_def.html @@ -0,0 +1,140 @@ + + + + + + +discoverpixy: _USB_OTG_GCCFG_TypeDef Union Reference + + + + + + + + + + +
+
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_USB_OTG_GCCFG_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   Reserved_in: 16
 
+   uint32_t   pwdn: 1
 
+   uint32_t   i2cifen: 1
 
+   uint32_t   vbussensingA: 1
 
+   uint32_t   vbussensingB: 1
 
+   uint32_t   sofouten: 1
 
+   uint32_t   disablevbussensing: 1
 
+   uint32_t   Reserved_out: 10
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def-members.html new file mode 100644 index 0000000..5d4592f --- /dev/null +++ b/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def-members.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GI2CCTL_TypeDef Member List
+
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+ +

This is the complete list of members for _USB_OTG_GI2CCTL_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + +
ack (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
addr (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
b (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
bsydne (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
d32 (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
dat_se0 (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
i2cdevaddr (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
i2cen (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
i2csuspctl (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
regaddr (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
Reserved (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
rw (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
rwdata (defined in _USB_OTG_GI2CCTL_TypeDef)_USB_OTG_GI2CCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def.html b/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def.html new file mode 100644 index 0000000..cc5033f --- /dev/null +++ b/union___u_s_b___o_t_g___g_i2_c_c_t_l___type_def.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: _USB_OTG_GI2CCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GI2CCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   rwdata: 8
 
+   uint32_t   regaddr: 8
 
+   uint32_t   addr: 7
 
+   uint32_t   i2cen: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   i2csuspctl: 1
 
+   uint32_t   i2cdevaddr: 2
 
+   uint32_t   dat_se0: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   rw: 1
 
+   uint32_t   bsydne: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def-members.html b/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def-members.html new file mode 100644 index 0000000..d1c2d43 --- /dev/null +++ b/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def-members.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GINTMSK_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GINTMSK_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
b (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
conidstschng (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
d32 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
disconnect (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
enumdone (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
eopframe (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
epmismatch (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
erlysuspend (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
ginnakeff (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
goutnakeff (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
hcintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
i2cintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
incomplisoin (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
incomplisoout (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
inepintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
isooutdrop (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
modemismatch (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
nptxfempty (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
otgintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
outepintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
portintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
ptxfempty (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
Reserved0 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
Reserved16 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
Reserved22_23 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
Reserved27 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
Reserved8 (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
rxstsqlvl (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
sessreqintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
sofintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
usbreset (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
usbsuspend (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
wkupintr (defined in _USB_OTG_GINTMSK_TypeDef)_USB_OTG_GINTMSK_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def.html b/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def.html new file mode 100644 index 0000000..4655b59 --- /dev/null +++ b/union___u_s_b___o_t_g___g_i_n_t_m_s_k___type_def.html @@ -0,0 +1,209 @@ + + + + + + +discoverpixy: _USB_OTG_GINTMSK_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GINTMSK_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   Reserved0: 1
 
+   uint32_t   modemismatch: 1
 
+   uint32_t   otgintr: 1
 
+   uint32_t   sofintr: 1
 
+   uint32_t   rxstsqlvl: 1
 
+   uint32_t   nptxfempty: 1
 
+   uint32_t   ginnakeff: 1
 
+   uint32_t   goutnakeff: 1
 
+   uint32_t   Reserved8: 1
 
+   uint32_t   i2cintr: 1
 
+   uint32_t   erlysuspend: 1
 
+   uint32_t   usbsuspend: 1
 
+   uint32_t   usbreset: 1
 
+   uint32_t   enumdone: 1
 
+   uint32_t   isooutdrop: 1
 
+   uint32_t   eopframe: 1
 
+   uint32_t   Reserved16: 1
 
+   uint32_t   epmismatch: 1
 
+   uint32_t   inepintr: 1
 
+   uint32_t   outepintr: 1
 
+   uint32_t   incomplisoin: 1
 
+   uint32_t   incomplisoout: 1
 
+   uint32_t   Reserved22_23: 2
 
+   uint32_t   portintr: 1
 
+   uint32_t   hcintr: 1
 
+   uint32_t   ptxfempty: 1
 
+   uint32_t   Reserved27: 1
 
+   uint32_t   conidstschng: 1
 
+   uint32_t   disconnect: 1
 
+   uint32_t   sessreqintr: 1
 
+   uint32_t   wkupintr: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def-members.html new file mode 100644 index 0000000..fb3f0bc --- /dev/null +++ b/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def-members.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
_USB_OTG_GINTSTS_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GINTSTS_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
b (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
conidstschng (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
curmode (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
d32 (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
disconnect (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
enumdone (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
eopframe (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
epmismatch (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
erlysuspend (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
ginnakeff (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
goutnakeff (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
hcintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
i2cintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
incomplisoin (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
incomplisoout (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
inepint (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
intimerrx (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
isooutdrop (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
modemismatch (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
nptxfempty (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
otgintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
outepintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
portintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
ptxfempty (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
Reserved22_23 (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
Reserved27 (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
Reserved8 (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
rxstsqlvl (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
sessreqintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
sofintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
usbreset (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
usbsuspend (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
wkupintr (defined in _USB_OTG_GINTSTS_TypeDef)_USB_OTG_GINTSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def.html b/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def.html new file mode 100644 index 0000000..0489d2c --- /dev/null +++ b/union___u_s_b___o_t_g___g_i_n_t_s_t_s___type_def.html @@ -0,0 +1,209 @@ + + + + + + +discoverpixy: _USB_OTG_GINTSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GINTSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   curmode: 1
 
+   uint32_t   modemismatch: 1
 
+   uint32_t   otgintr: 1
 
+   uint32_t   sofintr: 1
 
+   uint32_t   rxstsqlvl: 1
 
+   uint32_t   nptxfempty: 1
 
+   uint32_t   ginnakeff: 1
 
+   uint32_t   goutnakeff: 1
 
+   uint32_t   Reserved8: 1
 
+   uint32_t   i2cintr: 1
 
+   uint32_t   erlysuspend: 1
 
+   uint32_t   usbsuspend: 1
 
+   uint32_t   usbreset: 1
 
+   uint32_t   enumdone: 1
 
+   uint32_t   isooutdrop: 1
 
+   uint32_t   eopframe: 1
 
+   uint32_t   intimerrx: 1
 
+   uint32_t   epmismatch: 1
 
+   uint32_t   inepint: 1
 
+   uint32_t   outepintr: 1
 
+   uint32_t   incomplisoin: 1
 
+   uint32_t   incomplisoout: 1
 
+   uint32_t   Reserved22_23: 2
 
+   uint32_t   portintr: 1
 
+   uint32_t   hcintr: 1
 
+   uint32_t   ptxfempty: 1
 
+   uint32_t   Reserved27: 1
 
+   uint32_t   conidstschng: 1
 
+   uint32_t   disconnect: 1
 
+   uint32_t   sessreqintr: 1
 
+   uint32_t   wkupintr: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def-members.html b/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def-members.html new file mode 100644 index 0000000..cf0cb3f --- /dev/null +++ b/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def-members.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GOTGINT_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GOTGINT_TypeDef, including all inherited members.

+ + + + + + + + + + + + + +
adevtoutchng (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
b (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
d32 (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
debdone (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
hstnegdet (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
hstnegsucstschng (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
Reserved0_1 (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
Reserved31_20 (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
Reserved3_7 (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
reserver10_16 (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
sesenddet (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
sesreqsucstschng (defined in _USB_OTG_GOTGINT_TypeDef)_USB_OTG_GOTGINT_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def.html b/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def.html new file mode 100644 index 0000000..3c50617 --- /dev/null +++ b/union___u_s_b___o_t_g___g_o_t_g_i_n_t___type_def.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: _USB_OTG_GOTGINT_TypeDef Union Reference + + + + + + + + + + +
+
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+
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+Public Attributes | +List of all members
+
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_USB_OTG_GOTGINT_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   Reserved0_1: 2
 
+   uint32_t   sesenddet: 1
 
+   uint32_t   Reserved3_7: 5
 
+   uint32_t   sesreqsucstschng: 1
 
+   uint32_t   hstnegsucstschng: 1
 
+   uint32_t   reserver10_16: 7
 
+   uint32_t   hstnegdet: 1
 
+   uint32_t   adevtoutchng: 1
 
+   uint32_t   debdone: 1
 
+   uint32_t   Reserved31_20: 12
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def-members.html new file mode 100644 index 0000000..8415b24 --- /dev/null +++ b/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def-members.html @@ -0,0 +1,114 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GRSTCTL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GRSTCTL_TypeDef, including all inherited members.

+ + + + + + + + + + + + + +
ahbidle (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
b (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
csftrst (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
d32 (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
dmareq (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
hsftrst (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
hstfrm (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
intknqflsh (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
Reserved11_29 (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
rxfflsh (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
txfflsh (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
txfnum (defined in _USB_OTG_GRSTCTL_TypeDef)_USB_OTG_GRSTCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def.html b/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def.html new file mode 100644 index 0000000..78127b5 --- /dev/null +++ b/union___u_s_b___o_t_g___g_r_s_t_c_t_l___type_def.html @@ -0,0 +1,146 @@ + + + + + + +discoverpixy: _USB_OTG_GRSTCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GRSTCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   csftrst: 1
 
+   uint32_t   hsftrst: 1
 
+   uint32_t   hstfrm: 1
 
+   uint32_t   intknqflsh: 1
 
+   uint32_t   rxfflsh: 1
 
+   uint32_t   txfflsh: 1
 
+   uint32_t   txfnum: 5
 
+   uint32_t   Reserved11_29: 19
 
+   uint32_t   dmareq: 1
 
+   uint32_t   ahbidle: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def-members.html new file mode 100644 index 0000000..b755374 --- /dev/null +++ b/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def-members.html @@ -0,0 +1,109 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GRXSTS_TypeDef Member List
+
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+ +

This is the complete list of members for _USB_OTG_GRXSTS_TypeDef, including all inherited members.

+ + + + + + + + +
b (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
bcnt (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
chnum (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
d32 (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
dpid (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
pktsts (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
Reserved (defined in _USB_OTG_GRXSTS_TypeDef)_USB_OTG_GRXSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def.html b/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def.html new file mode 100644 index 0000000..5f01a55 --- /dev/null +++ b/union___u_s_b___o_t_g___g_r_x_s_t_s___type_def.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: _USB_OTG_GRXSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GRXSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   chnum: 4
 
+   uint32_t   bcnt: 11
 
+   uint32_t   dpid: 2
 
+   uint32_t   pktsts: 4
 
+   uint32_t   Reserved: 11
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def-members.html b/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def-members.html new file mode 100644 index 0000000..c90781f --- /dev/null +++ b/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def-members.html @@ -0,0 +1,126 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_GUSBCFG_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_GUSBCFG_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + +
b (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
corrupt_tx (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
d32 (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ddrsel (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
force_dev (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
force_host (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
fsintf (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
hnpcap (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
nptxfrwnden (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
otgutmifssel (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
phyif (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
phylpwrclksel (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
physel (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
Reserved (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
srpcap (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
term_sel_dl_pulse (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
toutcal (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_auto_res (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_clk_sus_m (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_ext_vbus_drv (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_fsls (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_int_vbus_indicator (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
ulpi_utmi_sel (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
usbtrdtim (defined in _USB_OTG_GUSBCFG_TypeDef)_USB_OTG_GUSBCFG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def.html b/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def.html new file mode 100644 index 0000000..e64cb39 --- /dev/null +++ b/union___u_s_b___o_t_g___g_u_s_b_c_f_g___type_def.html @@ -0,0 +1,182 @@ + + + + + + +discoverpixy: _USB_OTG_GUSBCFG_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_GUSBCFG_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   toutcal: 3
 
+   uint32_t   phyif: 1
 
+   uint32_t   ulpi_utmi_sel: 1
 
+   uint32_t   fsintf: 1
 
+   uint32_t   physel: 1
 
+   uint32_t   ddrsel: 1
 
+   uint32_t   srpcap: 1
 
+   uint32_t   hnpcap: 1
 
+   uint32_t   usbtrdtim: 4
 
+   uint32_t   nptxfrwnden: 1
 
+   uint32_t   phylpwrclksel: 1
 
+   uint32_t   otgutmifssel: 1
 
+   uint32_t   ulpi_fsls: 1
 
+   uint32_t   ulpi_auto_res: 1
 
+   uint32_t   ulpi_clk_sus_m: 1
 
+   uint32_t   ulpi_ext_vbus_drv: 1
 
+   uint32_t   ulpi_int_vbus_indicator: 1
 
+   uint32_t   term_sel_dl_pulse: 1
 
+   uint32_t   Reserved: 6
 
+   uint32_t   force_host: 1
 
+   uint32_t   force_dev: 1
 
+   uint32_t   corrupt_tx: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_a_i_n_t___type_def-members.html b/union___u_s_b___o_t_g___h_a_i_n_t___type_def-members.html new file mode 100644 index 0000000..a150fcb --- /dev/null +++ b/union___u_s_b___o_t_g___h_a_i_n_t___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HAINT_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HAINT_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_HAINT_TypeDef)_USB_OTG_HAINT_TypeDef
chint (defined in _USB_OTG_HAINT_TypeDef)_USB_OTG_HAINT_TypeDef
d32 (defined in _USB_OTG_HAINT_TypeDef)_USB_OTG_HAINT_TypeDef
Reserved (defined in _USB_OTG_HAINT_TypeDef)_USB_OTG_HAINT_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_a_i_n_t___type_def.html b/union___u_s_b___o_t_g___h_a_i_n_t___type_def.html new file mode 100644 index 0000000..2e2056c --- /dev/null +++ b/union___u_s_b___o_t_g___h_a_i_n_t___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_HAINT_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HAINT_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   chint: 16
 
+   uint32_t   Reserved: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def-members.html b/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def-members.html new file mode 100644 index 0000000..2545396 --- /dev/null +++ b/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HAINTMSK_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HAINTMSK_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_HAINTMSK_TypeDef)_USB_OTG_HAINTMSK_TypeDef
chint (defined in _USB_OTG_HAINTMSK_TypeDef)_USB_OTG_HAINTMSK_TypeDef
d32 (defined in _USB_OTG_HAINTMSK_TypeDef)_USB_OTG_HAINTMSK_TypeDef
Reserved (defined in _USB_OTG_HAINTMSK_TypeDef)_USB_OTG_HAINTMSK_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def.html b/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def.html new file mode 100644 index 0000000..50f271e --- /dev/null +++ b/union___u_s_b___o_t_g___h_a_i_n_t_m_s_k___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_HAINTMSK_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HAINTMSK_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   chint: 16
 
+   uint32_t   Reserved: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def-members.html b/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def-members.html new file mode 100644 index 0000000..c851002 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def-members.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCCHAR_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCCHAR_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + +
b (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
chdis (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
chen (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
d32 (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
devaddr (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
epdir (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
epnum (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
eptype (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
lspddev (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
mps (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
multicnt (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
oddfrm (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
Reserved (defined in _USB_OTG_HCCHAR_TypeDef)_USB_OTG_HCCHAR_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def.html b/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def.html new file mode 100644 index 0000000..cefab05 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_c_h_a_r___type_def.html @@ -0,0 +1,149 @@ + + + + + + +discoverpixy: _USB_OTG_HCCHAR_TypeDef Union Reference + + + + + + + + + + +
+
+ + + + + + +
+
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_USB_OTG_HCCHAR_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   mps: 11
 
+   uint32_t   epnum: 4
 
+   uint32_t   epdir: 1
 
+   uint32_t   Reserved: 1
 
+   uint32_t   lspddev: 1
 
+   uint32_t   eptype: 2
 
+   uint32_t   multicnt: 2
 
+   uint32_t   devaddr: 7
 
+   uint32_t   oddfrm: 1
 
+   uint32_t   chdis: 1
 
+   uint32_t   chen: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_f_g___type_def-members.html b/union___u_s_b___o_t_g___h_c_f_g___type_def-members.html new file mode 100644 index 0000000..3d8d381 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_f_g___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCFG_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCFG_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_HCFG_TypeDef)_USB_OTG_HCFG_TypeDef
d32 (defined in _USB_OTG_HCFG_TypeDef)_USB_OTG_HCFG_TypeDef
fslspclksel (defined in _USB_OTG_HCFG_TypeDef)_USB_OTG_HCFG_TypeDef
fslssupp (defined in _USB_OTG_HCFG_TypeDef)_USB_OTG_HCFG_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_f_g___type_def.html b/union___u_s_b___o_t_g___h_c_f_g___type_def.html new file mode 100644 index 0000000..8cd6fc3 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_f_g___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_HCFG_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HCFG_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   fslspclksel: 2
 
+   uint32_t   fslssupp: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def-members.html b/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def-members.html new file mode 100644 index 0000000..1f075c9 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def-members.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCGINTMSK_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCGINTMSK_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + +
ack (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
ahberr (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
b (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
bblerr (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
chhltd (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
d32 (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
datatglerr (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
frmovrun (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
nak (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
nyet (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
Reserved (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
stall (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
xacterr (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
xfercompl (defined in _USB_OTG_HCGINTMSK_TypeDef)_USB_OTG_HCGINTMSK_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def.html b/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def.html new file mode 100644 index 0000000..60c16ad --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_g_i_n_t_m_s_k___type_def.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: _USB_OTG_HCGINTMSK_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HCGINTMSK_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   chhltd: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   nak: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   nyet: 1
 
+   uint32_t   xacterr: 1
 
+   uint32_t   bblerr: 1
 
+   uint32_t   frmovrun: 1
 
+   uint32_t   datatglerr: 1
 
+   uint32_t   Reserved: 21
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_i_n_tn___type_def-members.html b/union___u_s_b___o_t_g___h_c_i_n_tn___type_def-members.html new file mode 100644 index 0000000..c568d20 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_i_n_tn___type_def-members.html @@ -0,0 +1,116 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCINTn_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCINTn_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + +
ack (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
ahberr (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
b (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
bblerr (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
chhltd (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
d32 (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
datatglerr (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
frmovrun (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
nak (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
nyet (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
Reserved (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
stall (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
xacterr (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
xfercompl (defined in _USB_OTG_HCINTn_TypeDef)_USB_OTG_HCINTn_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_i_n_tn___type_def.html b/union___u_s_b___o_t_g___h_c_i_n_tn___type_def.html new file mode 100644 index 0000000..8c16c7b --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_i_n_tn___type_def.html @@ -0,0 +1,152 @@ + + + + + + +discoverpixy: _USB_OTG_HCINTn_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HCINTn_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfercompl: 1
 
+   uint32_t   chhltd: 1
 
+   uint32_t   ahberr: 1
 
+   uint32_t   stall: 1
 
+   uint32_t   nak: 1
 
+   uint32_t   ack: 1
 
+   uint32_t   nyet: 1
 
+   uint32_t   xacterr: 1
 
+   uint32_t   bblerr: 1
 
+   uint32_t   frmovrun: 1
 
+   uint32_t   datatglerr: 1
 
+   uint32_t   Reserved: 21
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def-members.html b/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def-members.html new file mode 100644 index 0000000..71f736d --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def-members.html @@ -0,0 +1,110 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCSPLT_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCSPLT_TypeDef, including all inherited members.

+ + + + + + + + + +
b (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
compsplt (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
d32 (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
hubaddr (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
prtaddr (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
Reserved (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
spltena (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
xactpos (defined in _USB_OTG_HCSPLT_TypeDef)_USB_OTG_HCSPLT_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def.html b/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def.html new file mode 100644 index 0000000..fe4893c --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_s_p_l_t___type_def.html @@ -0,0 +1,134 @@ + + + + + + +discoverpixy: _USB_OTG_HCSPLT_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HCSPLT_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   prtaddr: 7
 
+   uint32_t   hubaddr: 7
 
+   uint32_t   xactpos: 2
 
+   uint32_t   compsplt: 1
 
+   uint32_t   Reserved: 14
 
+   uint32_t   spltena: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def-members.html b/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def-members.html new file mode 100644 index 0000000..662528e --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HCTSIZn_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HCTSIZn_TypeDef, including all inherited members.

+ + + + + + + +
b (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
d32 (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
dopng (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
pid (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
pktcnt (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
xfersize (defined in _USB_OTG_HCTSIZn_TypeDef)_USB_OTG_HCTSIZn_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def.html b/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def.html new file mode 100644 index 0000000..fc3da25 --- /dev/null +++ b/union___u_s_b___o_t_g___h_c_t_s_i_zn___type_def.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: _USB_OTG_HCTSIZn_TypeDef Union Reference + + + + + + + + + + +
+
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_USB_OTG_HCTSIZn_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   xfersize: 19
 
+   uint32_t   pktcnt: 10
 
+   uint32_t   pid: 2
 
+   uint32_t   dopng: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_f_n_u_m___type_def-members.html b/union___u_s_b___o_t_g___h_f_n_u_m___type_def-members.html new file mode 100644 index 0000000..7dd9efa --- /dev/null +++ b/union___u_s_b___o_t_g___h_f_n_u_m___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HFNUM_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HFNUM_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_HFNUM_TypeDef)_USB_OTG_HFNUM_TypeDef
d32 (defined in _USB_OTG_HFNUM_TypeDef)_USB_OTG_HFNUM_TypeDef
frnum (defined in _USB_OTG_HFNUM_TypeDef)_USB_OTG_HFNUM_TypeDef
frrem (defined in _USB_OTG_HFNUM_TypeDef)_USB_OTG_HFNUM_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_f_n_u_m___type_def.html b/union___u_s_b___o_t_g___h_f_n_u_m___type_def.html new file mode 100644 index 0000000..7da51fd --- /dev/null +++ b/union___u_s_b___o_t_g___h_f_n_u_m___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_HFNUM_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HFNUM_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   frnum: 16
 
+   uint32_t   frrem: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def-members.html b/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def-members.html new file mode 100644 index 0000000..5d0bbd6 --- /dev/null +++ b/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
_USB_OTG_HFRMINTRVL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HFRMINTRVL_TypeDef, including all inherited members.

+ + + + + +
b (defined in _USB_OTG_HFRMINTRVL_TypeDef)_USB_OTG_HFRMINTRVL_TypeDef
d32 (defined in _USB_OTG_HFRMINTRVL_TypeDef)_USB_OTG_HFRMINTRVL_TypeDef
frint (defined in _USB_OTG_HFRMINTRVL_TypeDef)_USB_OTG_HFRMINTRVL_TypeDef
Reserved (defined in _USB_OTG_HFRMINTRVL_TypeDef)_USB_OTG_HFRMINTRVL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def.html b/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def.html new file mode 100644 index 0000000..4cc29d4 --- /dev/null +++ b/union___u_s_b___o_t_g___h_f_r_m_i_n_t_r_v_l___type_def.html @@ -0,0 +1,122 @@ + + + + + + +discoverpixy: _USB_OTG_HFRMINTRVL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HFRMINTRVL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
+
+ + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   frint: 16
 
+   uint32_t   Reserved: 16
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def-members.html new file mode 100644 index 0000000..d64ccc9 --- /dev/null +++ b/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HNPTXSTS_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_HNPTXSTS_TypeDef, including all inherited members.

+ + + + + + + + + + +
b (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
chnum (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
d32 (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
nptxfspcavail (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
nptxqspcavail (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
nptxqtop (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
nptxqtop_terminate (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
nptxqtop_timer (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
Reserved (defined in _USB_OTG_HNPTXSTS_TypeDef)_USB_OTG_HNPTXSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def.html b/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def.html new file mode 100644 index 0000000..8fe20f3 --- /dev/null +++ b/union___u_s_b___o_t_g___h_n_p_t_x_s_t_s___type_def.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _USB_OTG_HNPTXSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HNPTXSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
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+ + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   nptxfspcavail: 16
 
+   uint32_t   nptxqspcavail: 8
 
+   uint32_t   nptxqtop_terminate: 1
 
+   uint32_t   nptxqtop_timer: 2
 
+   uint32_t   nptxqtop: 2
 
+   uint32_t   chnum: 2
 
+   uint32_t   Reserved: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_p_r_t0___type_def-members.html b/union___u_s_b___o_t_g___h_p_r_t0___type_def-members.html new file mode 100644 index 0000000..f6f3b41 --- /dev/null +++ b/union___u_s_b___o_t_g___h_p_r_t0___type_def-members.html @@ -0,0 +1,119 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HPRT0_TypeDef Member List
+
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+ +

This is the complete list of members for _USB_OTG_HPRT0_TypeDef, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
b (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
d32 (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtconndet (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtconnsts (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtena (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtenchng (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtlnsts (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtovrcurract (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtovrcurrchng (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtpwr (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtres (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtrst (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtspd (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prtsusp (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
prttstctl (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
Reserved19_31 (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
Reserved9 (defined in _USB_OTG_HPRT0_TypeDef)_USB_OTG_HPRT0_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_p_r_t0___type_def.html b/union___u_s_b___o_t_g___h_p_r_t0___type_def.html new file mode 100644 index 0000000..48140b1 --- /dev/null +++ b/union___u_s_b___o_t_g___h_p_r_t0___type_def.html @@ -0,0 +1,161 @@ + + + + + + +discoverpixy: _USB_OTG_HPRT0_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HPRT0_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   prtconnsts: 1
 
+   uint32_t   prtconndet: 1
 
+   uint32_t   prtena: 1
 
+   uint32_t   prtenchng: 1
 
+   uint32_t   prtovrcurract: 1
 
+   uint32_t   prtovrcurrchng: 1
 
+   uint32_t   prtres: 1
 
+   uint32_t   prtsusp: 1
 
+   uint32_t   prtrst: 1
 
+   uint32_t   Reserved9: 1
 
+   uint32_t   prtlnsts: 2
 
+   uint32_t   prtpwr: 1
 
+   uint32_t   prttstctl: 4
 
+   uint32_t   prtspd: 2
 
+   uint32_t   Reserved19_31: 13
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def-members.html b/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def-members.html new file mode 100644 index 0000000..b74b8b9 --- /dev/null +++ b/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def-members.html @@ -0,0 +1,111 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_HPTXSTS_TypeDef Member List
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This is the complete list of members for _USB_OTG_HPTXSTS_TypeDef, including all inherited members.

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b (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
chnum (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
d32 (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxfspcavail (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxqspcavail (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxqtop (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxqtop_odd (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxqtop_terminate (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
ptxqtop_timer (defined in _USB_OTG_HPTXSTS_TypeDef)_USB_OTG_HPTXSTS_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def.html b/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def.html new file mode 100644 index 0000000..d7c9695 --- /dev/null +++ b/union___u_s_b___o_t_g___h_p_t_x_s_t_s___type_def.html @@ -0,0 +1,137 @@ + + + + + + +discoverpixy: _USB_OTG_HPTXSTS_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_HPTXSTS_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   ptxfspcavail: 16
 
+   uint32_t   ptxqspcavail: 8
 
+   uint32_t   ptxqtop_terminate: 1
 
+   uint32_t   ptxqtop_timer: 2
 
+   uint32_t   ptxqtop: 2
 
+   uint32_t   chnum: 2
 
+   uint32_t   ptxqtop_odd: 1
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def-members.html new file mode 100644 index 0000000..6ffd186 --- /dev/null +++ b/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def-members.html @@ -0,0 +1,118 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_OTGCTL_TypeDef Member List
+
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+ +

This is the complete list of members for _USB_OTG_OTGCTL_TypeDef, including all inherited members.

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asesvld (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
b (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
bsesvld (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
conidsts (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
currmod (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
d32 (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
devhnpen (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
hnpreq (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
hstnegscs (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
hstsethnpen (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
Reserved12_15 (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
Reserved17 (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
Reserved21_31 (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
Reserved2_7 (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
sesreq (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
sesreqscs (defined in _USB_OTG_OTGCTL_TypeDef)_USB_OTG_OTGCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def.html b/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def.html new file mode 100644 index 0000000..cbfd8f3 --- /dev/null +++ b/union___u_s_b___o_t_g___o_t_g_c_t_l___type_def.html @@ -0,0 +1,158 @@ + + + + + + +discoverpixy: _USB_OTG_OTGCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_OTGCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   sesreqscs: 1
 
+   uint32_t   sesreq: 1
 
+   uint32_t   Reserved2_7: 6
 
+   uint32_t   hstnegscs: 1
 
+   uint32_t   hnpreq: 1
 
+   uint32_t   hstsethnpen: 1
 
+   uint32_t   devhnpen: 1
 
+   uint32_t   Reserved12_15: 4
 
+   uint32_t   conidsts: 1
 
+   uint32_t   Reserved17: 1
 
+   uint32_t   asesvld: 1
 
+   uint32_t   bsesvld: 1
 
+   uint32_t   currmod: 1
 
+   uint32_t   Reserved21_31: 11
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def-members.html b/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def-members.html new file mode 100644 index 0000000..85e748e --- /dev/null +++ b/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def-members.html @@ -0,0 +1,107 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USB_OTG_PCGCCTL_TypeDef Member List
+
+
+ +

This is the complete list of members for _USB_OTG_PCGCCTL_TypeDef, including all inherited members.

+ + + + + + +
b (defined in _USB_OTG_PCGCCTL_TypeDef)_USB_OTG_PCGCCTL_TypeDef
d32 (defined in _USB_OTG_PCGCCTL_TypeDef)_USB_OTG_PCGCCTL_TypeDef
gatehclk (defined in _USB_OTG_PCGCCTL_TypeDef)_USB_OTG_PCGCCTL_TypeDef
Reserved (defined in _USB_OTG_PCGCCTL_TypeDef)_USB_OTG_PCGCCTL_TypeDef
stoppclk (defined in _USB_OTG_PCGCCTL_TypeDef)_USB_OTG_PCGCCTL_TypeDef
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def.html b/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def.html new file mode 100644 index 0000000..a297f89 --- /dev/null +++ b/union___u_s_b___o_t_g___p_c_g_c_c_t_l___type_def.html @@ -0,0 +1,125 @@ + + + + + + +discoverpixy: _USB_OTG_PCGCCTL_TypeDef Union Reference + + + + + + + + + + +
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_USB_OTG_PCGCCTL_TypeDef Union Reference
USB_OTG_DRIVER » USB_REGS » USB_REGS_Exported_Types » __otg_Core_registers
+
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+ + + + + + + + + + + + + +

+Public Attributes

+uint32_t d32
 
+struct {
+   uint32_t   stoppclk: 1
 
+   uint32_t   gatehclk: 1
 
+   uint32_t   Reserved: 30
 
} b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
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_USB_Setup Member List
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This is the complete list of members for _USB_Setup, including all inherited members.

+ + + +
b (defined in _USB_Setup)_USB_Setup
d8 (defined in _USB_Setup)_USB_Setup
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___setup.html b/union___u_s_b___setup.html new file mode 100644 index 0000000..ffb0ac1 --- /dev/null +++ b/union___u_s_b___setup.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: _USB_Setup Union Reference + + + + + + + + + + +
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_USB_Setup Union Reference
USBH_LIB » USBH_LIB_CORE
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+Collaboration diagram for _USB_Setup:
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Collaboration graph
+ + +
[legend]
+ + + + +

+Classes

struct  _SetupPkt_Struc
 
+ + + + + +

+Public Attributes

+uint8_t d8 [8]
 
+struct _USB_Setup::_SetupPkt_Struc b
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
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+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b___setup__coll__graph.map b/union___u_s_b___setup__coll__graph.map new file mode 100644 index 0000000..cec3c93 --- /dev/null +++ b/union___u_s_b___setup__coll__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/union___u_s_b___setup__coll__graph.md5 b/union___u_s_b___setup__coll__graph.md5 new file mode 100644 index 0000000..48c4c15 --- /dev/null +++ b/union___u_s_b___setup__coll__graph.md5 @@ -0,0 +1 @@ +c8e657536065a73ef4dba15cb124f130 \ No newline at end of file diff --git a/union___u_s_b___setup__coll__graph.png b/union___u_s_b___setup__coll__graph.png new file mode 100644 index 0000000..7291fff Binary files /dev/null and b/union___u_s_b___setup__coll__graph.png differ diff --git a/union___u_s_b_h___c_b_w___block-members.html b/union___u_s_b_h___c_b_w___block-members.html new file mode 100644 index 0000000..6008479 --- /dev/null +++ b/union___u_s_b_h___c_b_w___block-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USBH_CBW_Block Member List
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This is the complete list of members for _USBH_CBW_Block, including all inherited members.

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CBWArray (defined in _USBH_CBW_Block)_USBH_CBW_Block
field (defined in _USBH_CBW_Block)_USBH_CBW_Block
+ +
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_USBH_CBW_Block Union Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT » USBH_MSC_BOT_Exported_Types
+
+
+
+Collaboration diagram for _USBH_CBW_Block:
+
+
Collaboration graph
+ + +
[legend]
+ + + + +

+Classes

struct  __CBW
 
+ + + + + +

+Public Attributes

+struct _USBH_CBW_Block::__CBW field
 
+uint8_t CBWArray [31]
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b_h___c_b_w___block__coll__graph.map b/union___u_s_b_h___c_b_w___block__coll__graph.map new file mode 100644 index 0000000..74826cb --- /dev/null +++ b/union___u_s_b_h___c_b_w___block__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/union___u_s_b_h___c_b_w___block__coll__graph.md5 b/union___u_s_b_h___c_b_w___block__coll__graph.md5 new file mode 100644 index 0000000..3be618b --- /dev/null +++ b/union___u_s_b_h___c_b_w___block__coll__graph.md5 @@ -0,0 +1 @@ +a5dd8643895449aca655bc7a2818e273 \ No newline at end of file diff --git a/union___u_s_b_h___c_b_w___block__coll__graph.png b/union___u_s_b_h___c_b_w___block__coll__graph.png new file mode 100644 index 0000000..d35b5e4 Binary files /dev/null and b/union___u_s_b_h___c_b_w___block__coll__graph.png differ diff --git a/union___u_s_b_h___c_s_w___block-members.html b/union___u_s_b_h___c_s_w___block-members.html new file mode 100644 index 0000000..be2e49f --- /dev/null +++ b/union___u_s_b_h___c_s_w___block-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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_USBH_CSW_Block Member List
+
+
+ +

This is the complete list of members for _USBH_CSW_Block, including all inherited members.

+ + + +
CSWArray (defined in _USBH_CSW_Block)_USBH_CSW_Block
field (defined in _USBH_CSW_Block)_USBH_CSW_Block
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b_h___c_s_w___block.html b/union___u_s_b_h___c_s_w___block.html new file mode 100644 index 0000000..eeccb2f --- /dev/null +++ b/union___u_s_b_h___c_s_w___block.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: _USBH_CSW_Block Union Reference + + + + + + + + + + +
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+Classes | +Public Attributes | +List of all members
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+
_USBH_CSW_Block Union Reference
USBH_LIB » USBH_CLASS » USBH_MSC_CLASS » USBH_MSC_BOT » USBH_MSC_BOT_Exported_Types
+
+
+
+Collaboration diagram for _USBH_CSW_Block:
+
+
Collaboration graph
+ + +
[legend]
+ + + + +

+Classes

struct  __CSW
 
+ + + + + +

+Public Attributes

+struct _USBH_CSW_Block::__CSW field
 
+uint8_t CSWArray [13]
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union___u_s_b_h___c_s_w___block__coll__graph.map b/union___u_s_b_h___c_s_w___block__coll__graph.map new file mode 100644 index 0000000..2e238de --- /dev/null +++ b/union___u_s_b_h___c_s_w___block__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/union___u_s_b_h___c_s_w___block__coll__graph.md5 b/union___u_s_b_h___c_s_w___block__coll__graph.md5 new file mode 100644 index 0000000..a257043 --- /dev/null +++ b/union___u_s_b_h___c_s_w___block__coll__graph.md5 @@ -0,0 +1 @@ +3630bf10d47ff6a14d131dd2166d8083 \ No newline at end of file diff --git a/union___u_s_b_h___c_s_w___block__coll__graph.png b/union___u_s_b_h___c_s_w___block__coll__graph.png new file mode 100644 index 0000000..11735a5 Binary files /dev/null and b/union___u_s_b_h___c_s_w___block__coll__graph.png differ diff --git a/union_a_p_s_r___type-members.html b/union_a_p_s_r___type-members.html new file mode 100644 index 0000000..3b8e018 --- /dev/null +++ b/union_a_p_s_r___type-members.html @@ -0,0 +1,112 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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APSR_Type Member List
+
+
+ +

This is the complete list of members for APSR_Type, including all inherited members.

+ + + + + + + + + + + +
_reserved0APSR_Type
_reserved1APSR_Type
bAPSR_Type
CAPSR_Type
GEAPSR_Type
NAPSR_Type
QAPSR_Type
VAPSR_Type
wAPSR_Type
ZAPSR_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union_a_p_s_r___type.html b/union_a_p_s_r___type.html new file mode 100644 index 0000000..f702dcb --- /dev/null +++ b/union_a_p_s_r___type.html @@ -0,0 +1,268 @@ + + + + + + +discoverpixy: APSR_Type Union Reference + + + + + + + + + + +
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+
+
APSR_Type Union Reference
Defines and Type Definitions » Status and Control Registers
+
+
+ +

Union type to access the Application Program Status Register (APSR). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

struct {
   uint32_t   _reserved0:16
 
   uint32_t   GE:4
 
   uint32_t   _reserved1:7
 
   uint32_t   Q:1
 
   uint32_t   V:1
 
   uint32_t   C:1
 
   uint32_t   Z:1
 
   uint32_t   N:1
 
} b
 
uint32_t w
 
+

Detailed Description

+

Union type to access the Application Program Status Register (APSR).

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t APSR_Type::_reserved0
+
+

bit: 0..15 Reserved

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::_reserved1
+
+

bit: 20..26 Reserved

+ +
+
+ +
+
+ + + + +
struct { ... } APSR_Type::b
+
+

Structure used for bit access

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::C
+
+

bit: 29 Carry condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::GE
+
+

bit: 16..19 Greater than or Equal flags

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::N
+
+

bit: 31 Negative condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::Q
+
+

bit: 27 Saturation condition flag

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::V
+
+

bit: 28 Overflow condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::w
+
+

Type used for word access

+ +
+
+ +
+
+ + + + +
uint32_t APSR_Type::Z
+
+

bit: 30 Zero condition code flag

+ +
+
+
The documentation for this union was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union_c_o_n_t_r_o_l___type-members.html b/union_c_o_n_t_r_o_l___type-members.html new file mode 100644 index 0000000..cc89252 --- /dev/null +++ b/union_c_o_n_t_r_o_l___type-members.html @@ -0,0 +1,108 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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CONTROL_Type Member List
+
+
+ +

This is the complete list of members for CONTROL_Type, including all inherited members.

+ + + + + + + +
_reserved0CONTROL_Type
bCONTROL_Type
FPCACONTROL_Type
nPRIVCONTROL_Type
SPSELCONTROL_Type
wCONTROL_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union_c_o_n_t_r_o_l___type.html b/union_c_o_n_t_r_o_l___type.html new file mode 100644 index 0000000..fe771ba --- /dev/null +++ b/union_c_o_n_t_r_o_l___type.html @@ -0,0 +1,208 @@ + + + + + + +discoverpixy: CONTROL_Type Union Reference + + + + + + + + + + +
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CONTROL_Type Union Reference
Defines and Type Definitions » Status and Control Registers
+
+
+ +

Union type to access the Control Registers (CONTROL). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + +

+Public Attributes

struct {
   uint32_t   nPRIV:1
 
   uint32_t   SPSEL:1
 
   uint32_t   FPCA:1
 
   uint32_t   _reserved0:29
 
} b
 
uint32_t w
 
+

Detailed Description

+

Union type to access the Control Registers (CONTROL).

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t CONTROL_Type::_reserved0
+
+

bit: 3..31 Reserved

+ +
+
+ +
+
+ + + + +
struct { ... } CONTROL_Type::b
+
+

Structure used for bit access

+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::FPCA
+
+

bit: 2 FP extension active flag

+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::nPRIV
+
+

bit: 0 Execution privilege in Thread mode

+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::SPSEL
+
+

bit: 1 Stack to be used

+ +
+
+ +
+
+ + + + +
uint32_t CONTROL_Type::w
+
+

Type used for word access

+ +
+
+
The documentation for this union was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union_i_p_s_r___type-members.html b/union_i_p_s_r___type-members.html new file mode 100644 index 0000000..a8dcfa0 --- /dev/null +++ b/union_i_p_s_r___type-members.html @@ -0,0 +1,106 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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+
+
IPSR_Type Member List
+
+
+ +

This is the complete list of members for IPSR_Type, including all inherited members.

+ + + + + +
_reserved0IPSR_Type
bIPSR_Type
ISRIPSR_Type
wIPSR_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/union_i_p_s_r___type.html b/union_i_p_s_r___type.html new file mode 100644 index 0000000..b6835f8 --- /dev/null +++ b/union_i_p_s_r___type.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: IPSR_Type Union Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
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+
IPSR_Type Union Reference
Defines and Type Definitions » Status and Control Registers
+
+
+ +

Union type to access the Interrupt Program Status Register (IPSR). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + +

+Public Attributes

struct {
   uint32_t   ISR:9
 
   uint32_t   _reserved0:23
 
} b
 
uint32_t w
 
+

Detailed Description

+

Union type to access the Interrupt Program Status Register (IPSR).

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t IPSR_Type::_reserved0
+
+

bit: 9..31 Reserved

+ +
+
+ +
+
+ + + + +
struct { ... } IPSR_Type::b
+
+

Structure used for bit access

+ +
+
+ +
+
+ + + + +
uint32_t IPSR_Type::ISR
+
+

bit: 0.. 8 Exception number

+ +
+
+ +
+
+ + + + +
uint32_t IPSR_Type::w
+
+

Type used for word access

+ +
+
+
The documentation for this union was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/unionuint16__t__uint8__t-members.html b/unionuint16__t__uint8__t-members.html new file mode 100644 index 0000000..aaf019a --- /dev/null +++ b/unionuint16__t__uint8__t-members.html @@ -0,0 +1,104 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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uint16_t_uint8_t Member List
+
+
+ +

This is the complete list of members for uint16_t_uint8_t, including all inherited members.

+ + + +
bw (defined in uint16_t_uint8_t)uint16_t_uint8_t
w (defined in uint16_t_uint8_t)uint16_t_uint8_t
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/unionuint16__t__uint8__t.html b/unionuint16__t__uint8__t.html new file mode 100644 index 0000000..c5df66b --- /dev/null +++ b/unionuint16__t__uint8__t.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: uint16_t_uint8_t Union Reference + + + + + + + + + + +
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+Classes | +Public Attributes | +List of all members
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uint16_t_uint8_t Union Reference
USBH_LIB » USBH_LIB_CORE
+
+
+
+Collaboration diagram for uint16_t_uint8_t:
+
+
Collaboration graph
+ + +
[legend]
+ + + + +

+Classes

struct  BW
 
+ + + + + +

+Public Attributes

+uint16_t w
 
+struct uint16_t_uint8_t::BW bw
 
+
The documentation for this union was generated from the following file:
    +
  • discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h
    • +
+
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/unionuint16__t__uint8__t__coll__graph.map b/unionuint16__t__uint8__t__coll__graph.map new file mode 100644 index 0000000..df68bd9 --- /dev/null +++ b/unionuint16__t__uint8__t__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/unionuint16__t__uint8__t__coll__graph.md5 b/unionuint16__t__uint8__t__coll__graph.md5 new file mode 100644 index 0000000..33db0eb --- /dev/null +++ b/unionuint16__t__uint8__t__coll__graph.md5 @@ -0,0 +1 @@ +47bead7b1db05ea94f4213b2c47f48a3 \ No newline at end of file diff --git a/unionuint16__t__uint8__t__coll__graph.png b/unionuint16__t__uint8__t__coll__graph.png new file mode 100644 index 0000000..3eb3759 Binary files /dev/null and b/unionuint16__t__uint8__t__coll__graph.png differ diff --git a/unionx_p_s_r___type-members.html b/unionx_p_s_r___type-members.html new file mode 100644 index 0000000..2533570 --- /dev/null +++ b/unionx_p_s_r___type-members.html @@ -0,0 +1,115 @@ + + + + + + +discoverpixy: Member List + + + + + + + + + + +
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xPSR_Type Member List
+
+
+ +

This is the complete list of members for xPSR_Type, including all inherited members.

+ + + + + + + + + + + + + + +
_reserved0xPSR_Type
_reserved1xPSR_Type
bxPSR_Type
CxPSR_Type
GExPSR_Type
ISRxPSR_Type
ITxPSR_Type
NxPSR_Type
QxPSR_Type
TxPSR_Type
VxPSR_Type
wxPSR_Type
ZxPSR_Type
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/unionx_p_s_r___type.html b/unionx_p_s_r___type.html new file mode 100644 index 0000000..629edbd --- /dev/null +++ b/unionx_p_s_r___type.html @@ -0,0 +1,313 @@ + + + + + + +discoverpixy: xPSR_Type Union Reference + + + + + + + + + + +
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+Public Attributes | +List of all members
+
+
xPSR_Type Union Reference
Defines and Type Definitions » Status and Control Registers
+
+
+ +

Union type to access the Special-Purpose Program Status Registers (xPSR). + More...

+ +

#include <core_cm4.h>

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

struct {
   uint32_t   ISR:9
 
   uint32_t   _reserved0:7
 
   uint32_t   GE:4
 
   uint32_t   _reserved1:4
 
   uint32_t   T:1
 
   uint32_t   IT:2
 
   uint32_t   Q:1
 
   uint32_t   V:1
 
   uint32_t   C:1
 
   uint32_t   Z:1
 
   uint32_t   N:1
 
} b
 
uint32_t w
 
+

Detailed Description

+

Union type to access the Special-Purpose Program Status Registers (xPSR).

+

Member Data Documentation

+ +
+
+ + + + +
uint32_t xPSR_Type::_reserved0
+
+

bit: 9..15 Reserved

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::_reserved1
+
+

bit: 20..23 Reserved

+ +
+
+ +
+
+ + + + +
struct { ... } xPSR_Type::b
+
+

Structure used for bit access

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::C
+
+

bit: 29 Carry condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::GE
+
+

bit: 16..19 Greater than or Equal flags

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::ISR
+
+

bit: 0.. 8 Exception number

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::IT
+
+

bit: 25..26 saved IT state (read 0)

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::N
+
+

bit: 31 Negative condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::Q
+
+

bit: 27 Saturation condition flag

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::T
+
+

bit: 24 Thumb bit (read 0)

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::V
+
+

bit: 28 Overflow condition code flag

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::w
+
+

Type used for word access

+ +
+
+ +
+
+ + + + +
uint32_t xPSR_Type::Z
+
+

bit: 30 Zero condition code flag

+ +
+
+
The documentation for this union was generated from the following file: +
+ +
+Generated on Sun May 10 2015 15:15:21 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__bsp_8c.html b/usb__bsp_8c.html new file mode 100644 index 0000000..26d0151 --- /dev/null +++ b/usb__bsp_8c.html @@ -0,0 +1,841 @@ + + + + + + +discoverpixy: discovery/src/usb_bsp.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions | +Variables
+
+
usb_bsp.c File Reference
+
+
+
#include "usb_bsp.h"
+#include "stm32f4_discovery.h"
+
+Include dependency graph for usb_bsp.c:
+
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define USE_ACCURATE_TIME
 
#define TIM_MSEC_DELAY   0x01
 
#define TIM_USEC_DELAY   0x02
 
#define HOST_OVRCURR_PORT   GPIOD
 
#define HOST_OVRCURR_LINE   GPIO_Pin_5
 
#define HOST_OVRCURR_PORT_SOURCE   GPIO_PortSourceGPIOD
 
#define HOST_OVRCURR_PIN_SOURCE   GPIO_PinSourceD
 
#define HOST_OVRCURR_PORT_RCC   RCC_APB2Periph_GPIOD
 
#define HOST_OVRCURR_EXTI_LINE   EXTI_Line5
 
#define HOST_OVRCURR_IRQn   EXTI9_5_IRQn
 
#define HOST_POWERSW_PORT_RCC   RCC_AHB1Periph_GPIOC
 
#define HOST_POWERSW_PORT   GPIOC
 
#define HOST_POWERSW_VBUS   GPIO_Pin_0
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

static void BSP_SetTime (uint8_t unit)
 BSP_SetTime Configures TIM2 for delay routine based on TIM2. More...
 
static void BSP_Delay (uint32_t nTime, uint8_t unit)
 BSP_Delay Delay routine based on TIM2. More...
 
static void USB_OTG_BSP_TimeInit (void)
 USB_OTG_BSP_TimeInit Initializes delay unit using Timer2. More...
 
void BSP_Init (void)
 BSP_Init board user initializations. More...
 
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_Init Initilizes BSP configurations. More...
 
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt. More...
 
void USB_OTG_BSP_DriveVBUS (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
 BSP_Drive_VBUS Drives the Vbus signal through IO. More...
 
void USB_OTG_BSP_ConfigVBUS (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_ConfigVBUS Configures the IO for the Vbus and OverCurrent. More...
 
void USB_OTG_BSP_uDelay (const uint32_t usec)
 USB_OTG_BSP_uDelay This function provides delay time in micro sec. More...
 
void USB_OTG_BSP_mDelay (const uint32_t msec)
 USB_OTG_BSP_mDelay This function provides delay time in milli sec. More...
 
void USB_OTG_BSP_TimerIRQ (void)
 USB_OTG_BSP_TimerIRQ Time base IRQ. More...
 
+ + + + + +

+Variables

ErrorStatus HSEStartUpStatus
 
__IO uint32_t BSP_delay = 0
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define HOST_OVRCURR_EXTI_LINE   EXTI_Line5
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_IRQn   EXTI9_5_IRQn
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_LINE   GPIO_Pin_5
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_PIN_SOURCE   GPIO_PinSourceD
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_PORT   GPIOD
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_PORT_RCC   RCC_APB2Periph_GPIOD
+
+ +
+
+ +
+
+ + + + +
#define HOST_OVRCURR_PORT_SOURCE   GPIO_PortSourceGPIOD
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+ +
+
+ +
+
+ + + + +
#define HOST_POWERSW_PORT   GPIOC
+
+ +
+
+ +
+
+ + + + +
#define HOST_POWERSW_PORT_RCC   RCC_AHB1Periph_GPIOC
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+ +
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+ +
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+ + + + +
#define HOST_POWERSW_VBUS   GPIO_Pin_0
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+ +
+
+ +
+
+ + + + +
#define TIM_MSEC_DELAY   0x01
+
+ +
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+ +
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+ + + + +
#define TIM_USEC_DELAY   0x02
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+ +
+
+ +
+
+ + + + +
#define USE_ACCURATE_TIME
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static void BSP_Delay (uint32_t nTime,
uint8_t unit 
)
+ 		+static
+
+ +

BSP_Delay Delay routine based on TIM2.

+
Parameters
+ + + +
nTime: Delay Time
unit: Delay Time unit : mili sec / micro sec
+
+
+
Return values
+ + +
None
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void BSP_Init (void )
+
+ +

BSP_Init board user initializations.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static void BSP_SetTime (uint8_t unit)
+ 		+static
+
+ +

BSP_SetTime Configures TIM2 for delay routine based on TIM2.

+
Parameters
+ + +
unit: msec /usec
+
+
+
Return values
+ + +
None
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void USB_OTG_BSP_ConfigVBUS (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USB_OTG_BSP_ConfigVBUS Configures the IO for the Vbus and OverCurrent.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
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void USB_OTG_BSP_DriveVBUS (USB_OTG_CORE_HANDLE * pdev,
uint8_t state 
)
+
+ +

BSP_Drive_VBUS Drives the Vbus signal through IO.

+
Parameters
+ + +
state: VBUS states
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE * pdev)
+
+ +

USB_OTG_BSP_Init Initilizes BSP configurations.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
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void USB_OTG_BSP_mDelay (const uint32_t msec)
+
+ +

USB_OTG_BSP_mDelay This function provides delay time in milli sec.

+
Parameters
+ + +
msec: Value of delay required in milli sec
+
+
+
Return values
+ + +
None
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+ + + + + + + + +
static void USB_OTG_BSP_TimeInit (void )
+ 		+static
+
+ +

USB_OTG_BSP_TimeInit Initializes delay unit using Timer2.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
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void USB_OTG_BSP_TimerIRQ (void )
+
+ +

USB_OTG_BSP_TimerIRQ Time base IRQ.

+
Parameters
+ + +
None
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+
+
Return values
+ + +
None
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void USB_OTG_BSP_uDelay (const uint32_t usec)
+
+ +

USB_OTG_BSP_uDelay This function provides delay time in micro sec.

+
Parameters
+ + +
usec: Value of delay required in micro sec
+
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Return values
+ + +
None
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Variable Documentation

+ +
+
+ + + + +
__IO uint32_t BSP_delay = 0
+
+ +
+
+ +
+
+ + + + +
ErrorStatus HSEStartUpStatus
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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+5c168498ab1bbfdd5f936a25259c0a03 \ No newline at end of file diff --git a/usb__bsp_8c_acffb89e4346b11dee704fe5a40326a1f_cgraph.png b/usb__bsp_8c_acffb89e4346b11dee704fe5a40326a1f_cgraph.png new file mode 100644 index 0000000..e2a98a3 Binary files /dev/null and b/usb__bsp_8c_acffb89e4346b11dee704fe5a40326a1f_cgraph.png differ diff --git a/usb__bsp_8h.html b/usb__bsp_8h.html new file mode 100644 index 0000000..7a61bd3 --- /dev/null +++ b/usb__bsp_8h.html @@ -0,0 +1,151 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_bsp.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
usb_bsp.h File Reference
+
+
+ +

Specific api's relative to the used hardware platform. +More...

+
#include "usb_core.h"
+#include "stm32f4_discovery.h"
+
+Include dependency graph for usb_bsp.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + +

+Functions

void BSP_Init (void)
 BSP_Init board user initializations. More...
 
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_Init Initilizes BSP configurations. More...
 
void USB_OTG_BSP_uDelay (const uint32_t usec)
 USB_OTG_BSP_uDelay This function provides delay time in micro sec. More...
 
void USB_OTG_BSP_mDelay (const uint32_t msec)
 USB_OTG_BSP_mDelay This function provides delay time in milli sec. More...
 
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt. More...
 
+

Detailed Description

+

Specific api's relative to the used hardware platform.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__bsp_8h__dep__incl.map b/usb__bsp_8h__dep__incl.map new file mode 100644 index 0000000..efd627a --- /dev/null +++ b/usb__bsp_8h__dep__incl.map @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/usb__bsp_8h__dep__incl.md5 b/usb__bsp_8h__dep__incl.md5 new file mode 100644 index 0000000..ae979b5 --- /dev/null +++ b/usb__bsp_8h__dep__incl.md5 @@ -0,0 +1 @@ +f43ee0e1a10dca07a6ba6695f75bf368 \ No newline at end of file diff --git a/usb__bsp_8h__dep__incl.png b/usb__bsp_8h__dep__incl.png new file mode 100644 index 0000000..3ae06a2 Binary files /dev/null and b/usb__bsp_8h__dep__incl.png differ diff --git a/usb__bsp_8h__incl.map b/usb__bsp_8h__incl.map new file mode 100644 index 0000000..a2b3fc5 --- /dev/null +++ b/usb__bsp_8h__incl.map @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__bsp_8h__incl.md5 b/usb__bsp_8h__incl.md5 new file mode 100644 index 0000000..efd234f --- /dev/null +++ b/usb__bsp_8h__incl.md5 @@ -0,0 +1 @@ +395b5ccfb1a4f267d24de13e5bfe23f4 \ No newline at end of file diff --git a/usb__bsp_8h__incl.png b/usb__bsp_8h__incl.png new file mode 100644 index 0000000..e350c24 Binary files /dev/null and b/usb__bsp_8h__incl.png differ diff --git a/usb__bsp_8h_source.html b/usb__bsp_8h_source.html new file mode 100644 index 0000000..54dd25d --- /dev/null +++ b/usb__bsp_8h_source.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_bsp.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usb_bsp.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_BSP__H__
+
24 #define __USB_BSP__H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_core.h"
+
28 #include "stm32f4_discovery.h"
+
29 
+
73 void BSP_Init(void);
+
74 
+
75 void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev);
+
76 void USB_OTG_BSP_uDelay (const uint32_t usec);
+
77 void USB_OTG_BSP_mDelay (const uint32_t msec);
+
78 void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev);
+
79 #ifdef USE_HOST_MODE
+
80 void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev);
+
81 void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state);
+
82 #endif
+
83 
+
87 #endif //__USB_BSP__H__
+
88 
+
96 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
97 
+
USB_OTG_BSP_uDelay
void USB_OTG_BSP_uDelay(const uint32_t usec)
USB_OTG_BSP_uDelay This function provides delay time in micro sec.
Definition: usb_bsp.c:337
+
USB_OTG_BSP_Init
void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_BSP_Init Initilizes BSP configurations.
Definition: usb_bsp.c:55
+
stm32f4_discovery.h
This file contains definitions for STM32F4-Discovery Kit's Leds and push-button hardware resources...
+
BSP_Init
void BSP_Init(void)
BSP_Init board user initializations.
Definition: usb_bsp.c:43
+
USB_OTG_handle
Definition: usb_core.h:287
+
USB_OTG_BSP_mDelay
void USB_OTG_BSP_mDelay(const uint32_t msec)
USB_OTG_BSP_mDelay This function provides delay time in milli sec.
Definition: usb_bsp.c:363
+
usb_core.h
Header of the Core Layer.
+
USB_OTG_BSP_EnableInterrupt
void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_BSP_EnableInterrupt Configures USB Global interrupt.
Definition: usb_bsp.c:217
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__conf_8h_source.html b/usb__conf_8h_source.html new file mode 100644 index 0000000..c5bdef5 --- /dev/null +++ b/usb__conf_8h_source.html @@ -0,0 +1,268 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_Device_Specific/usb_conf.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + +
+ +
+ + +
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+
usb_conf.h
+
+
+
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_CONF__H__
+
24 #define __USB_CONF__H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "stm32f4xx.h"
+
28 
+
43 /* USB Core and PHY interface configuration.
+
44  Tip: To avoid modifying these defines each time you need to change the USB
+
45  configuration, you can declare the needed define in your toolchain
+
46  compiler preprocessor.
+
47  */
+
48 #ifndef USE_USB_OTG_FS
+
49  //#define USE_USB_OTG_FS
+
50 #endif /* USE_USB_OTG_FS */
+
51 
+
52 #ifndef USE_USB_OTG_HS
+
53  //#define USE_USB_OTG_HS
+
54 #endif /* USE_USB_OTG_HS */
+
55 
+
56 #ifndef USE_ULPI_PHY
+
57  //#define USE_ULPI_PHY
+
58 #endif /* USE_ULPI_PHY */
+
59 
+
60 #ifndef USE_EMBEDDED_PHY
+
61  //#define USE_EMBEDDED_PHY
+
62 #endif /* USE_EMBEDDED_PHY */
+
63 
+
64 #ifndef USE_I2C_PHY
+
65  //#define USE_I2C_PHY
+
66 #endif /* USE_I2C_PHY */
+
67 
+
68 
+
69 #ifdef USE_USB_OTG_FS
+
70  #define USB_OTG_FS_CORE
+
71 #endif
+
72 
+
73 #ifdef USE_USB_OTG_HS
+
74  #define USB_OTG_HS_CORE
+
75 #endif
+
76 
+
77 /*******************************************************************************
+
78 * FIFO Size Configuration in Host mode
+
79 *
+
80 * (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or
+
81 * 2x (Largest Packet Size / 4) + 1, If a
+
82 * high-bandwidth channel or multiple isochronous
+
83 * channels are enabled
+
84 *
+
85 * (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size
+
86 * for all supported nonperiodic OUT channels. Typically, a space
+
87 * corresponding to two Largest Packet Size is recommended.
+
88 *
+
89 * (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is
+
90 * the largest maximum packet size for all supported periodic OUT channels.
+
91 * If there is at least one High Bandwidth Isochronous OUT endpoint,
+
92 * then the space must be at least two times the maximum packet size for
+
93 * that channel.
+
94 *******************************************************************************/
+
95 
+
96 /****************** USB OTG HS CONFIGURATION **********************************/
+
97 #ifdef USB_OTG_HS_CORE
+
98  #define RX_FIFO_HS_SIZE 512
+
99  #define TXH_NP_HS_FIFOSIZ 256
+
100  #define TXH_P_HS_FIFOSIZ 256
+
101 
+
102  //#define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
+
103  //#define USB_OTG_HS_SOF_OUTPUT_ENABLED
+
104 
+
105  #ifdef USE_ULPI_PHY
+
106  #define USB_OTG_ULPI_PHY_ENABLED
+
107  #endif
+
108  #ifdef USE_EMBEDDED_PHY
+
109  #define USB_OTG_EMBEDDED_PHY_ENABLED
+
110  #endif
+
111  #ifdef USE_I2C_PHY
+
112  #define USB_OTG_I2C_PHY_ENABLED
+
113  #endif
+
114  #define USB_OTG_HS_INTERNAL_DMA_ENABLED
+
115  #define USB_OTG_EXTERNAL_VBUS_ENABLED
+
116  //#define USB_OTG_INTERNAL_VBUS_ENABLED
+
117 #endif
+
118 
+
119 /****************** USB OTG FS CONFIGURATION **********************************/
+
120 #ifdef USB_OTG_FS_CORE
+
121  #define RX_FIFO_FS_SIZE 128
+
122  #define TXH_NP_FS_FIFOSIZ 96
+
123  #define TXH_P_FS_FIFOSIZ 96
+
124 
+
125  //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
+
126  //#define USB_OTG_FS_SOF_OUTPUT_ENABLED
+
127 #endif
+
128 
+
129 /****************** USB OTG MODE CONFIGURATION ********************************/
+
130 
+
131 //#define USE_HOST_MODE
+
132 //#define USE_DEVICE_MODE
+
133 //#define USE_OTG_MODE
+
134 
+
135 
+
136 #ifndef USB_OTG_FS_CORE
+
137  #ifndef USB_OTG_HS_CORE
+
138  #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
+
139  #endif
+
140 #endif
+
141 
+
142 
+
143 #ifndef USE_DEVICE_MODE
+
144  #ifndef USE_HOST_MODE
+
145  #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
+
146  #endif
+
147 #endif
+
148 
+
149 #ifndef USE_USB_OTG_HS
+
150  #ifndef USE_USB_OTG_FS
+
151  #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
+
152  #endif
+
153 #else //USE_USB_OTG_HS
+
154  #ifndef USE_ULPI_PHY
+
155  #ifndef USE_EMBEDDED_PHY
+
156  #ifndef USE_I2C_PHY
+
157  #error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined"
+
158  #endif
+
159  #endif
+
160  #endif
+
161 #endif
+
162 
+
163 /****************** C Compilers dependant keywords ****************************/
+
164 /* In HS mode and when the DMA is used, all variables and data structures dealing
+
165  with the DMA during the transaction process should be 4-bytes aligned */
+
166 #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+
167  #if defined (__GNUC__) /* GNU Compiler */
+
168  #define __ALIGN_END __attribute__ ((aligned (4)))
+
169  #define __ALIGN_BEGIN
+
170  #else
+
171  #define __ALIGN_END
+
172  #if defined (__CC_ARM) /* ARM Compiler */
+
173  #define __ALIGN_BEGIN __align(4)
+
174  #elif defined (__ICCARM__) /* IAR Compiler */
+
175  #define __ALIGN_BEGIN
+
176  #elif defined (__TASKING__) /* TASKING Compiler */
+
177  #define __ALIGN_BEGIN __align(4)
+
178  #endif /* __CC_ARM */
+
179  #endif /* __GNUC__ */
+
180 #else
+
181  #define __ALIGN_BEGIN
+
182  #define __ALIGN_END
+
183 #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+
184 
+
185 /* __packed keyword used to decrease the data type alignment to 1-byte */
+
186 #if defined (__CC_ARM) /* ARM Compiler */
+
187  #define __packed __packed
+
188 #elif defined (__ICCARM__) /* IAR Compiler */
+
189  #define __packed __packed
+
190 #elif defined ( __GNUC__ ) /* GNU Compiler */
+
191  // #define __packed __attribute__ ((__packed__))
+
192 #elif defined (__TASKING__) /* TASKING Compiler */
+
193  #define __packed __unaligned
+
194 #endif /* __CC_ARM */
+
195 
+
231 #endif //__USB_CONF__H__
+
232 
+
233 
+
241 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
242 
+
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__core_8c.html b/usb__core_8c.html new file mode 100644 index 0000000..0a1118f --- /dev/null +++ b/usb__core_8c.html @@ -0,0 +1,170 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src/usb_core.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
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+ + +
+ +
+ + +
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+
+Functions
+
+
usb_core.c File Reference
+
+
+ +

USB-OTG Core Layer. +More...

+
#include <stdio.h>
+#include "usb_core.h"
+#include "usb_bsp.h"
+
+Include dependency graph for usb_core.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
 USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP. More...
 
void * USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
 USB_OTG_ReadPacket : Reads a packet from the Rx FIFO. More...
 
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 USB_OTG_SelectCore Initialize core registers address. More...
 
USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation. More...
 
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev, uint32_t num)
 USB_OTG_FlushTxFifo : Flush a Tx FIFO. More...
 
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_FlushRxFifo : Flush a Rx FIFO. More...
 
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
 USB_OTG_SetCurrentMode : Set ID line. More...
 
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_GetMode : Get current mode. More...
 
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsDeviceMode : Check if it is device mode. More...
 
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsHostMode : Check if it is host mode. More...
 
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadCoreItr : returns the Core Interrupt register. More...
 
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register. More...
 
+

Detailed Description

+

USB-OTG Core Layer.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__core_8c__incl.map b/usb__core_8c__incl.map new file mode 100644 index 0000000..28ea6c4 --- /dev/null +++ b/usb__core_8c__incl.map @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__core_8c__incl.md5 b/usb__core_8c__incl.md5 new file mode 100644 index 0000000..a042982 --- /dev/null +++ b/usb__core_8c__incl.md5 @@ -0,0 +1 @@ +7d7e6ab2b91e6888820646dc6f5ee480 \ No newline at end of file diff --git a/usb__core_8c__incl.png b/usb__core_8c__incl.png new file mode 100644 index 0000000..fbf20de Binary files /dev/null and b/usb__core_8c__incl.png differ diff --git a/usb__core_8h.html b/usb__core_8h.html new file mode 100644 index 0000000..332493e --- /dev/null +++ b/usb__core_8h.html @@ -0,0 +1,374 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Typedefs | +Enumerations | +Functions
+
+
usb_core.h File Reference
+
+
+ +

Header of the Core Layer. +More...

+
#include "usb_conf.h"
+#include "usb_regs.h"
+#include "usb_defines.h"
+
+Include dependency graph for usb_core.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Classes

struct  USB_OTG_hc
 
struct  USB_OTG_ep
 
struct  USB_OTG_core_cfg
 
struct  usb_setup_req
 
struct  _Device_TypeDef
 
struct  USB_OTG_hPort
 
struct  _Device_cb
 
struct  _USBD_USR_PROP
 
struct  _DCD
 
struct  _HCD
 
struct  _OTG
 
struct  USB_OTG_handle
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USB_OTG_EP0_IDLE   0
 
+#define USB_OTG_EP0_SETUP   1
 
+#define USB_OTG_EP0_DATA_IN   2
 
+#define USB_OTG_EP0_DATA_OUT   3
 
+#define USB_OTG_EP0_STATUS_IN   4
 
+#define USB_OTG_EP0_STATUS_OUT   5
 
+#define USB_OTG_EP0_STALL   6
 
+#define USB_OTG_EP_TX_DIS   0x0000
 
+#define USB_OTG_EP_TX_STALL   0x0010
 
+#define USB_OTG_EP_TX_NAK   0x0020
 
+#define USB_OTG_EP_TX_VALID   0x0030
 
+#define USB_OTG_EP_RX_DIS   0x0000
 
+#define USB_OTG_EP_RX_STALL   0x1000
 
+#define USB_OTG_EP_RX_NAK   0x2000
 
+#define USB_OTG_EP_RX_VALID   0x3000
 
+#define MAX_DATA_LENGTH   0xFF
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

+typedef struct USB_OTG_hc USB_OTG_HC
 
+typedef struct USB_OTG_hc * PUSB_OTG_HC
 
+typedef struct USB_OTG_ep USB_OTG_EP
 
+typedef struct USB_OTG_ep * PUSB_OTG_EP
 
+typedef struct USB_OTG_core_cfg USB_OTG_CORE_CFGS
 
+typedef struct USB_OTG_core_cfg * PUSB_OTG_CORE_CFGS
 
+typedef struct usb_setup_req USB_SETUP_REQ
 
+typedef struct _Device_TypeDef USBD_DEVICE
 
+typedef struct _Device_TypeDef * pUSBD_DEVICE
 
+typedef struct USB_OTG_hPort USB_OTG_hPort_TypeDef
 
+typedef struct _Device_cb USBD_Class_cb_TypeDef
 
+typedef struct _USBD_USR_PROP USBD_Usr_cb_TypeDef
 
+typedef struct _DCD DCD_DEV
 
+typedef struct _DCD * DCD_PDEV
 
+typedef struct _HCD HCD_DEV
 
+typedef struct _HCD * USB_OTG_USBH_PDEV
 
+typedef struct _OTG OTG_DEV
 
+typedef struct _OTG * USB_OTG_USBO_PDEV
 
+typedef struct USB_OTG_handle USB_OTG_CORE_HANDLE
 
+typedef struct USB_OTG_handle * PUSB_OTG_CORE_HANDLE
 
+ + + + + + + + + +

+Enumerations

enum  USB_OTG_STS { USB_OTG_OK = 0, +USB_OTG_FAIL + }
 
enum  HC_STATUS {
+  HC_IDLE = 0, +HC_XFRC, +HC_HALTED, +HC_NAK, +
+  HC_NYET, +HC_STALL, +HC_XACTERR, +HC_BBLERR, +
+  HC_DATATGLERR +
+ }
 
enum  URB_STATE {
+  URB_IDLE = 0, +URB_DONE, +URB_NOTREADY, +URB_ERROR, +
+  URB_STALL +
+ }
 
enum  CTRL_STATUS {
+  CTRL_START = 0, +CTRL_XFRC, +CTRL_HALTED, +CTRL_NAK, +
+  CTRL_STALL, +CTRL_XACTERR, +CTRL_BBLERR, +CTRL_DATATGLERR, +
+  CTRL_FAIL +
+ }
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or host mode operation. More...
 
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 USB_OTG_SelectCore Initialize core registers address. More...
 
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
USB_OTG_STS USB_OTG_DisableGlobalInt (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg. More...
 
void * USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
 USB_OTG_ReadPacket : Reads a packet from the Rx FIFO. More...
 
USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
 USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP. More...
 
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev, uint32_t num)
 USB_OTG_FlushTxFifo : Flush a Tx FIFO. More...
 
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_FlushRxFifo : Flush a Rx FIFO. More...
 
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadCoreItr : returns the Core Interrupt register. More...
 
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register. More...
 
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsHostMode : Check if it is host mode. More...
 
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_IsDeviceMode : Check if it is device mode. More...
 
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev)
 USB_OTG_GetMode : Get current mode. More...
 
+USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev)
 
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
 USB_OTG_SetCurrentMode : Set ID line. More...
 
+

Detailed Description

+

Header of the Core Layer.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__core_8h__dep__incl.map b/usb__core_8h__dep__incl.map new file mode 100644 index 0000000..b7085fa --- /dev/null +++ b/usb__core_8h__dep__incl.map @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__core_8h__dep__incl.md5 b/usb__core_8h__dep__incl.md5 new file mode 100644 index 0000000..06edcca --- /dev/null +++ b/usb__core_8h__dep__incl.md5 @@ -0,0 +1 @@ +64ff8691f620ad8defef14d97cb31a07 \ No newline at end of file diff --git a/usb__core_8h__dep__incl.png b/usb__core_8h__dep__incl.png new file mode 100644 index 0000000..70f2230 Binary files /dev/null and b/usb__core_8h__dep__incl.png differ diff --git a/usb__core_8h__incl.map b/usb__core_8h__incl.map new file mode 100644 index 0000000..0e73b11 --- /dev/null +++ b/usb__core_8h__incl.map @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__core_8h__incl.md5 b/usb__core_8h__incl.md5 new file mode 100644 index 0000000..6142cbf --- /dev/null +++ b/usb__core_8h__incl.md5 @@ -0,0 +1 @@ +8987270cb7a1ddc86fe793db663ecd03 \ No newline at end of file diff --git a/usb__core_8h__incl.png b/usb__core_8h__incl.png new file mode 100644 index 0000000..eec0ac8 Binary files /dev/null and b/usb__core_8h__incl.png differ diff --git a/usb__core_8h_source.html b/usb__core_8h_source.html new file mode 100644 index 0000000..abb0a98 --- /dev/null +++ b/usb__core_8h_source.html @@ -0,0 +1,463 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_core.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usb_core.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_CORE_H__
+
24 #define __USB_CORE_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_conf.h"
+
28 #include "usb_regs.h"
+
29 #include "usb_defines.h"
+
30 
+
31 
+
46 #define USB_OTG_EP0_IDLE 0
+
47 #define USB_OTG_EP0_SETUP 1
+
48 #define USB_OTG_EP0_DATA_IN 2
+
49 #define USB_OTG_EP0_DATA_OUT 3
+
50 #define USB_OTG_EP0_STATUS_IN 4
+
51 #define USB_OTG_EP0_STATUS_OUT 5
+
52 #define USB_OTG_EP0_STALL 6
+
53 
+
54 #define USB_OTG_EP_TX_DIS 0x0000
+
55 #define USB_OTG_EP_TX_STALL 0x0010
+
56 #define USB_OTG_EP_TX_NAK 0x0020
+
57 #define USB_OTG_EP_TX_VALID 0x0030
+
58 
+
59 #define USB_OTG_EP_RX_DIS 0x0000
+
60 #define USB_OTG_EP_RX_STALL 0x1000
+
61 #define USB_OTG_EP_RX_NAK 0x2000
+
62 #define USB_OTG_EP_RX_VALID 0x3000
+
63 
+
66 #define MAX_DATA_LENGTH 0xFF
+
67 
+
73 typedef enum {
+
74  USB_OTG_OK = 0,
+
75  USB_OTG_FAIL
+
76 }USB_OTG_STS;
+
77 
+
78 typedef enum {
+
79  HC_IDLE = 0,
+
80  HC_XFRC,
+
81  HC_HALTED,
+
82  HC_NAK,
+
83  HC_NYET,
+
84  HC_STALL,
+
85  HC_XACTERR,
+
86  HC_BBLERR,
+
87  HC_DATATGLERR,
+
88 }HC_STATUS;
+
89 
+
90 typedef enum {
+
91  URB_IDLE = 0,
+
92  URB_DONE,
+
93  URB_NOTREADY,
+
94  URB_ERROR,
+
95  URB_STALL
+
96 }URB_STATE;
+
97 
+
98 typedef enum {
+
99  CTRL_START = 0,
+
100  CTRL_XFRC,
+
101  CTRL_HALTED,
+
102  CTRL_NAK,
+
103  CTRL_STALL,
+
104  CTRL_XACTERR,
+
105  CTRL_BBLERR,
+
106  CTRL_DATATGLERR,
+
107  CTRL_FAIL
+
108 }CTRL_STATUS;
+
109 
+
110 
+
111 typedef struct USB_OTG_hc
+
112 {
+
113  uint8_t dev_addr ;
+
114  uint8_t ep_num;
+
115  uint8_t ep_is_in;
+
116  uint8_t speed;
+
117  uint8_t do_ping;
+
118  uint8_t ep_type;
+
119  uint16_t max_packet;
+
120  uint8_t data_pid;
+
121  uint8_t *xfer_buff;
+
122  uint32_t xfer_len;
+
123  uint32_t xfer_count;
+
124  uint8_t toggle_in;
+
125  uint8_t toggle_out;
+
126  uint32_t dma_addr;
+
127 }
+
128 USB_OTG_HC , *PUSB_OTG_HC;
+
129 
+
130 typedef struct USB_OTG_ep
+
131 {
+
132  uint8_t num;
+
133  uint8_t is_in;
+
134  uint8_t is_stall;
+
135  uint8_t type;
+
136  uint8_t data_pid_start;
+
137  uint8_t even_odd_frame;
+
138  uint16_t tx_fifo_num;
+
139  uint32_t maxpacket;
+
140  /* transaction level variables*/
+
141  uint8_t *xfer_buff;
+
142  uint32_t dma_addr;
+
143  uint32_t xfer_len;
+
144  uint32_t xfer_count;
+
145  /* Transfer level variables*/
+
146  uint32_t rem_data_len;
+
147  uint32_t total_data_len;
+
148  uint32_t ctl_data_len;
+
149 
+
150 }
+
151 
+
152 USB_OTG_EP , *PUSB_OTG_EP;
+
153 
+
154 
+
155 
+
156 typedef struct USB_OTG_core_cfg
+
157 {
+
158  uint8_t host_channels;
+
159  uint8_t dev_endpoints;
+
160  uint8_t speed;
+
161  uint8_t dma_enable;
+
162  uint16_t mps;
+
163  uint16_t TotalFifoSize;
+
164  uint8_t phy_itface;
+
165  uint8_t Sof_output;
+
166  uint8_t low_power;
+
167  uint8_t coreID;
+
168 
+
169 }
+
170 USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
+
171 
+
172 
+
173 
+
174 typedef struct usb_setup_req {
+
175 
+
176  uint8_t bmRequest;
+
177  uint8_t bRequest;
+
178  uint16_t wValue;
+
179  uint16_t wIndex;
+
180  uint16_t wLength;
+
181 } USB_SETUP_REQ;
+
182 
+
183 typedef struct _Device_TypeDef
+
184 {
+
185  uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
+
186  uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
+
187  uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
+
188  uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
+
189  uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
+
190  uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
+
191  uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
+
192 } USBD_DEVICE, *pUSBD_DEVICE;
+
193 
+
194 typedef struct USB_OTG_hPort
+
195 {
+
196  void (*Disconnect) (void *phost);
+
197  void (*Connect) (void *phost);
+
198  uint8_t ConnStatus;
+
199  uint8_t DisconnStatus;
+
200  uint8_t ConnHandled;
+
201  uint8_t DisconnHandled;
+
202 } USB_OTG_hPort_TypeDef;
+
203 
+
204 typedef struct _Device_cb
+
205 {
+
206  uint8_t (*Init) (void *pdev , uint8_t cfgidx);
+
207  uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
+
208  /* Control Endpoints*/
+
209  uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
+
210  uint8_t (*EP0_TxSent) (void *pdev );
+
211  uint8_t (*EP0_RxReady) (void *pdev );
+
212  /* Class Specific Endpoints*/
+
213  uint8_t (*DataIn) (void *pdev , uint8_t epnum);
+
214  uint8_t (*DataOut) (void *pdev , uint8_t epnum);
+
215  uint8_t (*SOF) (void *pdev);
+
216  uint8_t (*IsoINIncomplete) (void *pdev);
+
217  uint8_t (*IsoOUTIncomplete) (void *pdev);
+
218 
+
219  uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
+
220 #ifdef USB_OTG_HS_CORE
+
221  uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);
+
222 #endif
+
223 
+
224 #ifdef USB_SUPPORT_USER_STRING_DESC
+
225  uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
+
226 #endif
+
227 
+
228 } USBD_Class_cb_TypeDef;
+
229 
+
230 
+
231 
+
232 typedef struct _USBD_USR_PROP
+
233 {
+
234  void (*Init)(void);
+
235  void (*DeviceReset)(uint8_t speed);
+
236  void (*DeviceConfigured)(void);
+
237  void (*DeviceSuspended)(void);
+
238  void (*DeviceResumed)(void);
+
239 
+
240  void (*DeviceConnected)(void);
+
241  void (*DeviceDisconnected)(void);
+
242 
+
243 }
+
244 USBD_Usr_cb_TypeDef;
+
245 
+
246 typedef struct _DCD
+
247 {
+
248  uint8_t device_config;
+
249  uint8_t device_state;
+
250  uint8_t device_status;
+
251  uint8_t device_address;
+
252  uint32_t DevRemoteWakeup;
+
253  USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
+
254  USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
+
255  uint8_t setup_packet [8*3];
+
256  USBD_Class_cb_TypeDef *class_cb;
+
257  USBD_Usr_cb_TypeDef *usr_cb;
+
258  USBD_DEVICE *usr_device;
+
259  uint8_t *pConfig_descriptor;
+
260  }
+
261 DCD_DEV , *DCD_PDEV;
+
262 
+
263 
+
264 typedef struct _HCD
+
265 {
+
266  uint8_t Rx_Buffer [MAX_DATA_LENGTH];
+
267  __IO uint32_t ConnSts;
+
268  __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS];
+
269  __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS];
+
270  __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS];
+
271  __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
+
272  USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
+
273  uint16_t channel [USB_OTG_MAX_TX_FIFOS];
+
274  USB_OTG_hPort_TypeDef *port_cb;
+
275 }
+
276 HCD_DEV , *USB_OTG_USBH_PDEV;
+
277 
+
278 
+
279 typedef struct _OTG
+
280 {
+
281  uint8_t OTG_State;
+
282  uint8_t OTG_PrevState;
+
283  uint8_t OTG_Mode;
+
284 }
+
285 OTG_DEV , *USB_OTG_USBO_PDEV;
+
286 
+
287 typedef struct USB_OTG_handle
+
288 {
+
289  USB_OTG_CORE_CFGS cfg;
+
290  USB_OTG_CORE_REGS regs;
+
291 #ifdef USE_DEVICE_MODE
+
292  DCD_DEV dev;
+
293 #endif
+
294 #ifdef USE_HOST_MODE
+
295  HCD_DEV host;
+
296 #endif
+
297 #ifdef USE_OTG_MODE
+
298  OTG_DEV otg;
+
299 #endif
+
300 }
+
301 USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
+
302 
+
328 USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev);
+
329 USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev,
+
330  USB_OTG_CORE_ID_TypeDef coreID);
+
331 USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
+
332 USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
+
333 void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev ,
+
334  uint8_t *dest,
+
335  uint16_t len);
+
336 USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev ,
+
337  uint8_t *src,
+
338  uint8_t ch_ep_num,
+
339  uint16_t len);
+
340 USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
+
341 USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev);
+
342 
+
343 uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev);
+
344 uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev);
+
345 uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev);
+
346 uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev);
+
347 uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev);
+
348 USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev);
+
349 USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev,
+
350  uint8_t mode);
+
351 
+
352 /*********************** HOST APIs ********************************************/
+
353 #ifdef USE_HOST_MODE
+
354 USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev);
+
355 USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev);
+
356 USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+
357 USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+
358 USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+
359 USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
+
360 uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev);
+
361 uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev);
+
362 uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev);
+
363 void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
+
364 void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
+
365 uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ;
+
366 void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev);
+
367 #endif
+
368 /********************* DEVICE APIs ********************************************/
+
369 #ifdef USE_DEVICE_MODE
+
370 USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev);
+
371 USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev);
+
372 uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
+
373 enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
+
374 USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
+
375 USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
376 USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
377 USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
378 USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
379 USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
380 USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+
381 uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
+
382 uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
+
383 uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
+
384 void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
+
385 uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
+
386 void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
+
387 void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
+
388 void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
+
389 void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
+
390 void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
+
391 uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
+
392 #endif
+
393 
+
397 #endif /* __USB_CORE_H__ */
+
398 
+
399 
+
407 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
408 
+
USB_OTG_IsHostMode
uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsHostMode : Check if it is host mode.
Definition: usb_core.c:610
+
USB_OTG_IsDeviceMode
uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_IsDeviceMode : Check if it is device mode.
Definition: usb_core.c:599
+
usb_setup_req
Definition: usb_core.h:174
+
USB_OTG_DisableGlobalInt
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_DisableGlobalInt Enables the controller's Global Int in the AHB Config reg.
Definition: usb_core.c:481
+
USB_OTG_hPort
Definition: usb_core.h:194
+
__IO
#define __IO
Definition: core_cm4.h:222
+
_USBD_USR_PROP
Definition: usb_core.h:232
+
USB_OTG_SelectCore
USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
USB_OTG_SelectCore Initialize core registers address.
Definition: usb_core.c:216
+
USB_OTG_handle
Definition: usb_core.h:287
+
_OTG
Definition: usb_core.h:279
+
_Device_TypeDef
Definition: usb_core.h:183
+
USB_OTG_CoreInit
USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_CoreInit Initializes the USB_OTG controller registers and prepares the core device mode or ho...
Definition: usb_core.c:322
+
usb_regs.h
hardware registers
+
USB_OTG_ReadOtgItr
uint32_t USB_OTG_ReadOtgItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register.
Definition: usb_core.c:635
+
USB_OTG_ReadCoreItr
uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_ReadCoreItr : returns the Core Interrupt register.
Definition: usb_core.c:621
+
_DCD
Definition: usb_core.h:246
+
USB_OTG_ReadPacket
void * USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *dest, uint16_t len)
USB_OTG_ReadPacket : Reads a packet from the Rx FIFO.
Definition: usb_core.c:192
+
USB_OTG_WritePacket
USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated with the EP.
Definition: usb_core.c:163
+
USB_OTG_EnableGlobalInt
USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_EnableGlobalInt Enables the controller's Global Int in the AHB Config reg.
Definition: usb_core.c:463
+
USB_OTG_core_cfg
Definition: usb_core.h:156
+
USB_OTG_FlushTxFifo
USB_OTG_STS USB_OTG_FlushTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t num)
USB_OTG_FlushTxFifo : Flush a Tx FIFO.
Definition: usb_core.c:498
+
USB_OTG_core_regs
Definition: usb_regs.h:217
+
USB_OTG_ep
Definition: usb_core.h:130
+
usb_defines.h
Header of the Core Layer.
+
USB_OTG_hc
Definition: usb_core.h:111
+
USB_OTG_SetCurrentMode
USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev, uint8_t mode)
USB_OTG_SetCurrentMode : Set ID line.
Definition: usb_core.c:558
+
USB_OTG_FlushRxFifo
USB_OTG_STS USB_OTG_FlushRxFifo(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_FlushRxFifo : Flush a Rx FIFO.
Definition: usb_core.c:528
+
_HCD
Definition: usb_core.h:264
+
USB_OTG_GetMode
uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
USB_OTG_GetMode : Get current mode.
Definition: usb_core.c:588
+
_Device_cb
Definition: usb_core.h:204
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__defines_8h.html b/usb__defines_8h.html new file mode 100644 index 0000000..33655f8 --- /dev/null +++ b/usb__defines_8h.html @@ -0,0 +1,392 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_defines.h File Reference + + + + + + + + + + +
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+Macros | +Enumerations
+
+
usb_defines.h File Reference
+
+
+ +

Header of the Core Layer. +More...

+
#include "usb_conf.h"
+
+Include dependency graph for usb_defines.h:
+
+
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+
+This graph shows which files directly or indirectly include this file:
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USB_OTG_SPEED_PARAM_HIGH   0
 
+#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL   1
 
+#define USB_OTG_SPEED_PARAM_FULL   3
 
+#define USB_OTG_SPEED_HIGH   0
 
+#define USB_OTG_SPEED_FULL   1
 
+#define USB_OTG_ULPI_PHY   1
 
+#define USB_OTG_EMBEDDED_PHY   2
 
+#define USB_OTG_I2C_PHY   3
 
+#define GAHBCFG_TXFEMPTYLVL_EMPTY   1
 
+#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
 
+#define GAHBCFG_GLBINT_ENABLE   1
 
+#define GAHBCFG_INT_DMA_BURST_SINGLE   0
 
+#define GAHBCFG_INT_DMA_BURST_INCR   1
 
+#define GAHBCFG_INT_DMA_BURST_INCR4   3
 
+#define GAHBCFG_INT_DMA_BURST_INCR8   5
 
+#define GAHBCFG_INT_DMA_BURST_INCR16   7
 
+#define GAHBCFG_DMAENABLE   1
 
+#define GAHBCFG_TXFEMPTYLVL_EMPTY   1
 
+#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
 
+#define GRXSTS_PKTSTS_IN   2
 
+#define GRXSTS_PKTSTS_IN_XFER_COMP   3
 
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR   5
 
+#define GRXSTS_PKTSTS_CH_HALTED   7
 
+#define MODE_HNP_SRP_CAPABLE   0
 
+#define MODE_SRP_ONLY_CAPABLE   1
 
+#define MODE_NO_HNP_SRP_CAPABLE   2
 
+#define MODE_SRP_CAPABLE_DEVICE   3
 
+#define MODE_NO_SRP_CAPABLE_DEVICE   4
 
+#define MODE_SRP_CAPABLE_HOST   5
 
+#define MODE_NO_SRP_CAPABLE_HOST   6
 
+#define A_HOST   1
 
+#define A_SUSPEND   2
 
+#define A_PERIPHERAL   3
 
+#define B_PERIPHERAL   4
 
+#define B_HOST   5
 
+#define DEVICE_MODE   0
 
+#define HOST_MODE   1
 
+#define OTG_MODE   2
 
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
 
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
 
+#define DSTS_ENUMSPD_LS_PHY_6MHZ   2
 
+#define DSTS_ENUMSPD_FS_PHY_48MHZ   3
 
+#define DCFG_FRAME_INTERVAL_80   0
 
+#define DCFG_FRAME_INTERVAL_85   1
 
+#define DCFG_FRAME_INTERVAL_90   2
 
+#define DCFG_FRAME_INTERVAL_95   3
 
+#define DEP0CTL_MPS_64   0
 
+#define DEP0CTL_MPS_32   1
 
+#define DEP0CTL_MPS_16   2
 
+#define DEP0CTL_MPS_8   3
 
+#define EP_SPEED_LOW   0
 
+#define EP_SPEED_FULL   1
 
+#define EP_SPEED_HIGH   2
 
+#define EP_TYPE_CTRL   0
 
+#define EP_TYPE_ISOC   1
 
+#define EP_TYPE_BULK   2
 
+#define EP_TYPE_INTR   3
 
+#define EP_TYPE_MSK   3
 
+#define STS_GOUT_NAK   1
 
+#define STS_DATA_UPDT   2
 
+#define STS_XFER_COMP   3
 
+#define STS_SETUP_COMP   4
 
+#define STS_SETUP_UPDT   6
 
+#define HC_PID_DATA0   0
 
+#define HC_PID_DATA2   1
 
+#define HC_PID_DATA1   2
 
+#define HC_PID_SETUP   3
 
+#define HPRT0_PRTSPD_HIGH_SPEED   0
 
+#define HPRT0_PRTSPD_FULL_SPEED   1
 
+#define HPRT0_PRTSPD_LOW_SPEED   2
 
+#define HCFG_30_60_MHZ   0
 
+#define HCFG_48_MHZ   1
 
+#define HCFG_6_MHZ   2
 
+#define HCCHAR_CTRL   0
 
+#define HCCHAR_ISOC   1
 
+#define HCCHAR_BULK   2
 
+#define HCCHAR_INTR   3
 
+#define MIN(a, b)   (((a) < (b)) ? (a) : (b))
 
+#define USB_OTG_READ_REG32(reg)   (*(__IO uint32_t *)reg)
 
+#define USB_OTG_WRITE_REG32(reg, value)   (*(__IO uint32_t *)reg = value)
 
+#define USB_OTG_MODIFY_REG32(reg, clear_mask, set_mask)   USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
 
+ + + + + +

+Enumerations

enum  USB_OTG_CORE_ID_TypeDef { USB_OTG_HS_CORE_ID = 0, +USB_OTG_FS_CORE_ID = 1 + }
 
enum  USB_OTG_SPEED { USB_SPEED_UNKNOWN = 0, +USB_SPEED_LOW, +USB_SPEED_FULL, +USB_SPEED_HIGH + }
 
+

Detailed Description

+

Header of the Core Layer.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__defines_8h__dep__incl.map b/usb__defines_8h__dep__incl.map new file mode 100644 index 0000000..5e11911 --- /dev/null +++ b/usb__defines_8h__dep__incl.map @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__defines_8h__dep__incl.md5 b/usb__defines_8h__dep__incl.md5 new file mode 100644 index 0000000..958f51f --- /dev/null +++ b/usb__defines_8h__dep__incl.md5 @@ -0,0 +1 @@ +ff06f5b003db2228fb442e0cccc5f888 \ No newline at end of file diff --git a/usb__defines_8h__dep__incl.png b/usb__defines_8h__dep__incl.png new file mode 100644 index 0000000..e0801e9 Binary files /dev/null and b/usb__defines_8h__dep__incl.png differ diff --git a/usb__defines_8h__incl.map b/usb__defines_8h__incl.map new file mode 100644 index 0000000..10e5d2d --- /dev/null +++ b/usb__defines_8h__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__defines_8h__incl.md5 b/usb__defines_8h__incl.md5 new file mode 100644 index 0000000..b77759f --- /dev/null +++ b/usb__defines_8h__incl.md5 @@ -0,0 +1 @@ +6d1fa1df6360caf4275555fd5cbd72a1 \ No newline at end of file diff --git a/usb__defines_8h__incl.png b/usb__defines_8h__incl.png new file mode 100644 index 0000000..631ce77 Binary files /dev/null and b/usb__defines_8h__incl.png differ diff --git a/usb__defines_8h_source.html b/usb__defines_8h_source.html new file mode 100644 index 0000000..ed1418a --- /dev/null +++ b/usb__defines_8h_source.html @@ -0,0 +1,228 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_defines.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
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+
usb_defines.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_DEF_H__
+
24 #define __USB_DEF_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_conf.h"
+
28 
+
51 #define USB_OTG_SPEED_PARAM_HIGH 0
+
52 #define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1
+
53 #define USB_OTG_SPEED_PARAM_FULL 3
+
54 
+
55 #define USB_OTG_SPEED_HIGH 0
+
56 #define USB_OTG_SPEED_FULL 1
+
57 
+
58 #define USB_OTG_ULPI_PHY 1
+
59 #define USB_OTG_EMBEDDED_PHY 2
+
60 #define USB_OTG_I2C_PHY 3
+
61 
+
70 #define GAHBCFG_TXFEMPTYLVL_EMPTY 1
+
71 #define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
+
72 #define GAHBCFG_GLBINT_ENABLE 1
+
73 #define GAHBCFG_INT_DMA_BURST_SINGLE 0
+
74 #define GAHBCFG_INT_DMA_BURST_INCR 1
+
75 #define GAHBCFG_INT_DMA_BURST_INCR4 3
+
76 #define GAHBCFG_INT_DMA_BURST_INCR8 5
+
77 #define GAHBCFG_INT_DMA_BURST_INCR16 7
+
78 #define GAHBCFG_DMAENABLE 1
+
79 #define GAHBCFG_TXFEMPTYLVL_EMPTY 1
+
80 #define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
+
81 #define GRXSTS_PKTSTS_IN 2
+
82 #define GRXSTS_PKTSTS_IN_XFER_COMP 3
+
83 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
+
84 #define GRXSTS_PKTSTS_CH_HALTED 7
+
85 
+
93 #define MODE_HNP_SRP_CAPABLE 0
+
94 #define MODE_SRP_ONLY_CAPABLE 1
+
95 #define MODE_NO_HNP_SRP_CAPABLE 2
+
96 #define MODE_SRP_CAPABLE_DEVICE 3
+
97 #define MODE_NO_SRP_CAPABLE_DEVICE 4
+
98 #define MODE_SRP_CAPABLE_HOST 5
+
99 #define MODE_NO_SRP_CAPABLE_HOST 6
+
100 #define A_HOST 1
+
101 #define A_SUSPEND 2
+
102 #define A_PERIPHERAL 3
+
103 #define B_PERIPHERAL 4
+
104 #define B_HOST 5
+
105 #define DEVICE_MODE 0
+
106 #define HOST_MODE 1
+
107 #define OTG_MODE 2
+
108 
+
116 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+
117 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+
118 #define DSTS_ENUMSPD_LS_PHY_6MHZ 2
+
119 #define DSTS_ENUMSPD_FS_PHY_48MHZ 3
+
120 
+
121 #define DCFG_FRAME_INTERVAL_80 0
+
122 #define DCFG_FRAME_INTERVAL_85 1
+
123 #define DCFG_FRAME_INTERVAL_90 2
+
124 #define DCFG_FRAME_INTERVAL_95 3
+
125 
+
126 #define DEP0CTL_MPS_64 0
+
127 #define DEP0CTL_MPS_32 1
+
128 #define DEP0CTL_MPS_16 2
+
129 #define DEP0CTL_MPS_8 3
+
130 
+
131 #define EP_SPEED_LOW 0
+
132 #define EP_SPEED_FULL 1
+
133 #define EP_SPEED_HIGH 2
+
134 
+
135 #define EP_TYPE_CTRL 0
+
136 #define EP_TYPE_ISOC 1
+
137 #define EP_TYPE_BULK 2
+
138 #define EP_TYPE_INTR 3
+
139 #define EP_TYPE_MSK 3
+
140 
+
141 #define STS_GOUT_NAK 1
+
142 #define STS_DATA_UPDT 2
+
143 #define STS_XFER_COMP 3
+
144 #define STS_SETUP_COMP 4
+
145 #define STS_SETUP_UPDT 6
+
146 
+
154 #define HC_PID_DATA0 0
+
155 #define HC_PID_DATA2 1
+
156 #define HC_PID_DATA1 2
+
157 #define HC_PID_SETUP 3
+
158 
+
159 #define HPRT0_PRTSPD_HIGH_SPEED 0
+
160 #define HPRT0_PRTSPD_FULL_SPEED 1
+
161 #define HPRT0_PRTSPD_LOW_SPEED 2
+
162 
+
163 #define HCFG_30_60_MHZ 0
+
164 #define HCFG_48_MHZ 1
+
165 #define HCFG_6_MHZ 2
+
166 
+
167 #define HCCHAR_CTRL 0
+
168 #define HCCHAR_ISOC 1
+
169 #define HCCHAR_BULK 2
+
170 #define HCCHAR_INTR 3
+
171 
+
172 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
+
173 
+
183 typedef enum
+
184 {
+
185  USB_OTG_HS_CORE_ID = 0,
+
186  USB_OTG_FS_CORE_ID = 1
+
187 }USB_OTG_CORE_ID_TypeDef;
+
218 #define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg)
+
219 #define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value)
+
220 #define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \
+
221  USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
+
222 
+
223 /********************************************************************************
+
224  ENUMERATION TYPE
+
225 ********************************************************************************/
+
226 enum USB_OTG_SPEED {
+
227  USB_SPEED_UNKNOWN = 0,
+
228  USB_SPEED_LOW,
+
229  USB_SPEED_FULL,
+
230  USB_SPEED_HIGH
+
231 };
+
232 
+
233 #endif //__USB_DEFINES__H__
+
234 
+
235 
+
243 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
244 
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd_8c.html b/usb__hcd_8c.html new file mode 100644 index 0000000..f2f957e --- /dev/null +++ b/usb__hcd_8c.html @@ -0,0 +1,159 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src/usb_hcd.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
usb_hcd.c File Reference
+
+
+ +

Host Interface Layer. +More...

+
#include "usb_core.h"
+#include "usb_hcd.h"
+#include "usb_conf.h"
+#include "usb_bsp.h"
+
+Include dependency graph for usb_hcd.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 HCD_Init Initialize the HOST portion of the driver. More...
 
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentSpeed Get Current device Speed. More...
 
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev)
 HCD_ResetPort Issues the reset command to device. More...
 
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev)
 HCD_IsDeviceConnected Check if the device is connected. More...
 
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentFrame This function returns the frame number for sof packet. More...
 
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetURB_State This function returns the last URBstate. More...
 
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetXferCnt This function returns the last URBstate. More...
 
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetHCState This function returns the HC Status. More...
 
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_HC_Init This function prepare a HC and start a transfer. More...
 
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_SubmitRequest This function prepare a HC and start a transfer. More...
 
+

Detailed Description

+

Host Interface Layer.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd_8c__incl.map b/usb__hcd_8c__incl.map new file mode 100644 index 0000000..902c472 --- /dev/null +++ b/usb__hcd_8c__incl.map @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__hcd_8c__incl.md5 b/usb__hcd_8c__incl.md5 new file mode 100644 index 0000000..4d2e44c --- /dev/null +++ b/usb__hcd_8c__incl.md5 @@ -0,0 +1 @@ +244df0ec4d4073710d15ce16d4e4a348 \ No newline at end of file diff --git a/usb__hcd_8c__incl.png b/usb__hcd_8c__incl.png new file mode 100644 index 0000000..d54c05d Binary files /dev/null and b/usb__hcd_8c__incl.png differ diff --git a/usb__hcd_8h.html b/usb__hcd_8h.html new file mode 100644 index 0000000..a7ccb2b --- /dev/null +++ b/usb__hcd_8h.html @@ -0,0 +1,166 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_hcd.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
usb_hcd.h File Reference
+
+
+ +

Host layer Header file. +More...

+
#include "usb_regs.h"
+#include "usb_core.h"
+
+Include dependency graph for usb_hcd.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
 HCD_Init Initialize the HOST portion of the driver. More...
 
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_HC_Init This function prepare a HC and start a transfer. More...
 
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
 HCD_SubmitRequest This function prepare a HC and start a transfer. More...
 
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentSpeed Get Current device Speed. More...
 
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev)
 HCD_ResetPort Issues the reset command to device. More...
 
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev)
 HCD_IsDeviceConnected Check if the device is connected. More...
 
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
 HCD_GetCurrentFrame This function returns the frame number for sof packet. More...
 
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetURB_State This function returns the last URBstate. More...
 
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetXferCnt This function returns the last URBstate. More...
 
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
 HCD_GetHCState This function returns the HC Status. More...
 
+

Detailed Description

+

Host layer Header file.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd_8h__dep__incl.map b/usb__hcd_8h__dep__incl.map new file mode 100644 index 0000000..0b84e12 --- /dev/null +++ b/usb__hcd_8h__dep__incl.map @@ -0,0 +1,26 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__hcd_8h__dep__incl.md5 b/usb__hcd_8h__dep__incl.md5 new file mode 100644 index 0000000..bfcd5c2 --- /dev/null +++ b/usb__hcd_8h__dep__incl.md5 @@ -0,0 +1 @@ +9d22069d642553b211e5eeaac1a651fa \ No newline at end of file diff --git a/usb__hcd_8h__dep__incl.png b/usb__hcd_8h__dep__incl.png new file mode 100644 index 0000000..3fb4494 Binary files /dev/null and b/usb__hcd_8h__dep__incl.png differ diff --git a/usb__hcd_8h__incl.map b/usb__hcd_8h__incl.map new file mode 100644 index 0000000..57ff986 --- /dev/null +++ b/usb__hcd_8h__incl.map @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__hcd_8h__incl.md5 b/usb__hcd_8h__incl.md5 new file mode 100644 index 0000000..3658db0 --- /dev/null +++ b/usb__hcd_8h__incl.md5 @@ -0,0 +1 @@ +e342dd40217db737932de6a84c20d42d \ No newline at end of file diff --git a/usb__hcd_8h__incl.png b/usb__hcd_8h__incl.png new file mode 100644 index 0000000..3d75648 Binary files /dev/null and b/usb__hcd_8h__incl.png differ diff --git a/usb__hcd_8h_source.html b/usb__hcd_8h_source.html new file mode 100644 index 0000000..e858f51 --- /dev/null +++ b/usb__hcd_8h_source.html @@ -0,0 +1,142 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_hcd.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usb_hcd.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_HCD_H__
+
24 #define __USB_HCD_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_regs.h"
+
28 #include "usb_core.h"
+
29 
+
30 
+
74 uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev ,
+
75  USB_OTG_CORE_ID_TypeDef coreID);
+
76 uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev ,
+
77  uint8_t hc_num);
+
78 uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev ,
+
79  uint8_t hc_num) ;
+
80 uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev);
+
81 uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev);
+
82 uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev);
+
83 uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ;
+
84 URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
+
85 uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
+
86 HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ;
+
91 #endif //__USB_HCD_H__
+
92 
+
93 
+
101 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
102 
+
HCD_GetXferCnt
uint32_t HCD_GetXferCnt(USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
HCD_GetXferCnt This function returns the last URBstate.
Definition: usb_hcd.c:197
+
HCD_GetCurrentFrame
uint32_t HCD_GetCurrentFrame(USB_OTG_CORE_HANDLE *pdev)
HCD_GetCurrentFrame This function returns the frame number for sof packet.
Definition: usb_hcd.c:173
+
HCD_HC_Init
uint32_t HCD_HC_Init(USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
HCD_HC_Init This function prepare a HC and start a transfer.
Definition: usb_hcd.c:223
+
HCD_ResetPort
uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev)
HCD_ResetPort Issues the reset command to device.
Definition: usb_hcd.c:141
+
HCD_SubmitRequest
uint32_t HCD_SubmitRequest(USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num)
HCD_SubmitRequest This function prepare a HC and start a transfer.
Definition: usb_hcd.c:235
+
USB_OTG_handle
Definition: usb_core.h:287
+
HCD_IsDeviceConnected
uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev)
HCD_IsDeviceConnected Check if the device is connected.
Definition: usb_hcd.c:161
+
usb_regs.h
hardware registers
+
HCD_Init
uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID)
HCD_Init Initialize the HOST portion of the driver.
Definition: usb_hcd.c:91
+
HCD_GetCurrentSpeed
uint32_t HCD_GetCurrentSpeed(USB_OTG_CORE_HANDLE *pdev)
HCD_GetCurrentSpeed Get Current device Speed.
Definition: usb_hcd.c:127
+
usb_core.h
Header of the Core Layer.
+
HCD_GetURB_State
URB_STATE HCD_GetURB_State(USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
HCD_GetURB_State This function returns the last URBstate.
Definition: usb_hcd.c:185
+
HCD_GetHCState
HC_STATUS HCD_GetHCState(USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
HCD_GetHCState This function returns the HC Status.
Definition: usb_hcd.c:211
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd__int_8c.html b/usb__hcd__int_8c.html new file mode 100644 index 0000000..798e3b4 --- /dev/null +++ b/usb__hcd__int_8c.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/src/usb_hcd_int.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions
+
+
usb_hcd_int.c File Reference
+
+
+ +

Host driver interrupt subroutines. +More...

+
#include "usb_core.h"
+#include "usb_defines.h"
+#include "usb_hcd_int.h"
+
+Include dependency graph for usb_hcd_int.c:
+
+
+ + +
+
+ + + + +

+Functions

uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
 HOST_Handle_ISR This function handles all USB Host Interrupts. More...
 
+

Detailed Description

+

Host driver interrupt subroutines.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd__int_8c__incl.map b/usb__hcd__int_8c__incl.map new file mode 100644 index 0000000..3a33cd6 --- /dev/null +++ b/usb__hcd__int_8c__incl.map @@ -0,0 +1,41 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__hcd__int_8c__incl.md5 b/usb__hcd__int_8c__incl.md5 new file mode 100644 index 0000000..a381829 --- /dev/null +++ b/usb__hcd__int_8c__incl.md5 @@ -0,0 +1 @@ +b5650eaba03974ccb9a1aef88527ebfa \ No newline at end of file diff --git a/usb__hcd__int_8c__incl.png b/usb__hcd__int_8c__incl.png new file mode 100644 index 0000000..e25bf7a Binary files /dev/null and b/usb__hcd__int_8c__incl.png differ diff --git a/usb__hcd__int_8h.html b/usb__hcd__int_8h.html new file mode 100644 index 0000000..4eef936 --- /dev/null +++ b/usb__hcd__int_8h.html @@ -0,0 +1,161 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_hcd_int.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Macros | +Functions
+
+
usb_hcd_int.h File Reference
+
+
+ +

Peripheral Device Interface Layer. +More...

+
#include "usb_hcd.h"
+
+Include dependency graph for usb_hcd_int.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + +

+Macros

#define CLEAR_HC_INT(HC_REGS, intr)
 
#define MASK_HOST_INT_CHH(hc_num)
 
#define UNMASK_HOST_INT_CHH(hc_num)
 
#define MASK_HOST_INT_ACK(hc_num)
 
#define UNMASK_HOST_INT_ACK(hc_num)
 
+ + + + + + + + + + +

+Functions

+void ConnectCallback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
+void Disconnect_Callback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
+void Overcurrent_Callback_Handler (USB_OTG_CORE_HANDLE *pdev)
 
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
 HOST_Handle_ISR This function handles all USB Host Interrupts. More...
 
+

Detailed Description

+

Peripheral Device Interface Layer.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__hcd__int_8h__dep__incl.map b/usb__hcd__int_8h__dep__incl.map new file mode 100644 index 0000000..6fe01cc --- /dev/null +++ b/usb__hcd__int_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/usb__hcd__int_8h__dep__incl.md5 b/usb__hcd__int_8h__dep__incl.md5 new file mode 100644 index 0000000..838e1f6 --- /dev/null +++ b/usb__hcd__int_8h__dep__incl.md5 @@ -0,0 +1 @@ +e061cec7a87f18f415d20dc298dc3b69 \ No newline at end of file diff --git a/usb__hcd__int_8h__dep__incl.png b/usb__hcd__int_8h__dep__incl.png new file mode 100644 index 0000000..6479b34 Binary files /dev/null and b/usb__hcd__int_8h__dep__incl.png differ diff --git a/usb__hcd__int_8h__incl.map b/usb__hcd__int_8h__incl.map new file mode 100644 index 0000000..c39df8d --- /dev/null +++ b/usb__hcd__int_8h__incl.map @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__hcd__int_8h__incl.md5 b/usb__hcd__int_8h__incl.md5 new file mode 100644 index 0000000..ca2395e --- /dev/null +++ b/usb__hcd__int_8h__incl.md5 @@ -0,0 +1 @@ +6897835cd6600e8c6559b4d0822b2805 \ No newline at end of file diff --git a/usb__hcd__int_8h__incl.png b/usb__hcd__int_8h__incl.png new file mode 100644 index 0000000..ced493a Binary files /dev/null and b/usb__hcd__int_8h__incl.png differ diff --git a/usb__hcd__int_8h_source.html b/usb__hcd__int_8h_source.html new file mode 100644 index 0000000..197d9da --- /dev/null +++ b/usb__hcd__int_8h_source.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_hcd_int.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usb_hcd_int.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __HCD_INT_H__
+
24 #define __HCD_INT_H__
+
25 
+
26 
+
27 /* Includes ------------------------------------------------------------------*/
+
28 #include "usb_hcd.h"
+
29 
+
30 
+
61 #define CLEAR_HC_INT(HC_REGS, intr) \
+
62  {\
+
63  USB_OTG_HCINTn_TypeDef hcint_clear; \
+
64  hcint_clear.d32 = 0; \
+
65  hcint_clear.b.intr = 1; \
+
66  USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
+
67  }\
+
68 
+
69 #define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
70  GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
71  GINTMSK.b.chhltd = 0; \
+
72  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
73 
+
74 #define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
75  GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
76  GINTMSK.b.chhltd = 1; \
+
77  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
78 
+
79 #define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
80  GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
81  GINTMSK.b.ack = 0; \
+
82  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
83 
+
84 #define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
+
85  GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
+
86  GINTMSK.b.ack = 1; \
+
87  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
+
88 
+
103 /* Callbacks handler */
+
104 void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev);
+
105 void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
+
106 void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
+
107 uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
+
108 
+
115 #endif //__HCD_INT_H__
+
116 
+
117 
+
125 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
126 
+
usb_hcd.h
Host layer Header file.
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_OTG_ISR_Handler
uint32_t USBH_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
HOST_Handle_ISR This function handles all USB Host Interrupts.
Definition: usb_hcd_int.c:114
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__regs_8h.html b/usb__regs_8h.html new file mode 100644 index 0000000..03447ef --- /dev/null +++ b/usb__regs_8h.html @@ -0,0 +1,426 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
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+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Typedefs
+
+
usb_regs.h File Reference
+
+
+ +

hardware registers +More...

+
#include "usb_conf.h"
+
+Include dependency graph for usb_regs.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Classes

struct  _USB_OTG_GREGS
 
struct  _USB_OTG_DREGS
 
struct  _USB_OTG_INEPREGS
 
struct  _USB_OTG_OUTEPREGS
 
struct  _USB_OTG_HREGS
 
struct  _USB_OTG_HC_REGS
 
struct  USB_OTG_core_regs
 
union  _USB_OTG_OTGCTL_TypeDef
 
union  _USB_OTG_GOTGINT_TypeDef
 
union  _USB_OTG_GAHBCFG_TypeDef
 
union  _USB_OTG_GUSBCFG_TypeDef
 
union  _USB_OTG_GRSTCTL_TypeDef
 
union  _USB_OTG_GINTMSK_TypeDef
 
union  _USB_OTG_GINTSTS_TypeDef
 
union  _USB_OTG_DRXSTS_TypeDef
 
union  _USB_OTG_GRXSTS_TypeDef
 
union  _USB_OTG_FSIZ_TypeDef
 
union  _USB_OTG_HNPTXSTS_TypeDef
 
union  _USB_OTG_DTXFSTSn_TypeDef
 
union  _USB_OTG_GI2CCTL_TypeDef
 
union  _USB_OTG_GCCFG_TypeDef
 
union  _USB_OTG_DCFG_TypeDef
 
union  _USB_OTG_DCTL_TypeDef
 
union  _USB_OTG_DSTS_TypeDef
 
union  _USB_OTG_DIEPINTn_TypeDef
 
union  _USB_OTG_DOEPINTn_TypeDef
 
union  _USB_OTG_DAINT_TypeDef
 
union  _USB_OTG_DTHRCTL_TypeDef
 
union  _USB_OTG_DEPCTL_TypeDef
 
union  _USB_OTG_DEPXFRSIZ_TypeDef
 
union  _USB_OTG_DEP0XFRSIZ_TypeDef
 
union  _USB_OTG_HCFG_TypeDef
 
union  _USB_OTG_HFRMINTRVL_TypeDef
 
union  _USB_OTG_HFNUM_TypeDef
 
union  _USB_OTG_HPTXSTS_TypeDef
 
union  _USB_OTG_HPRT0_TypeDef
 
union  _USB_OTG_HAINT_TypeDef
 
union  _USB_OTG_HAINTMSK_TypeDef
 
union  _USB_OTG_HCCHAR_TypeDef
 
union  _USB_OTG_HCSPLT_TypeDef
 
union  _USB_OTG_HCINTn_TypeDef
 
union  _USB_OTG_HCTSIZn_TypeDef
 
union  _USB_OTG_HCGINTMSK_TypeDef
 
union  _USB_OTG_PCGCCTL_TypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USB_OTG_HS_BASE_ADDR   0x40040000
 
+#define USB_OTG_FS_BASE_ADDR   0x50000000
 
+#define USB_OTG_CORE_GLOBAL_REGS_OFFSET   0x000
 
+#define USB_OTG_DEV_GLOBAL_REG_OFFSET   0x800
 
+#define USB_OTG_DEV_IN_EP_REG_OFFSET   0x900
 
+#define USB_OTG_EP_REG_OFFSET   0x20
 
+#define USB_OTG_DEV_OUT_EP_REG_OFFSET   0xB00
 
+#define USB_OTG_HOST_GLOBAL_REG_OFFSET   0x400
 
+#define USB_OTG_HOST_PORT_REGS_OFFSET   0x440
 
+#define USB_OTG_HOST_CHAN_REGS_OFFSET   0x500
 
+#define USB_OTG_CHAN_REGS_OFFSET   0x20
 
+#define USB_OTG_PCGCCTL_OFFSET   0xE00
 
+#define USB_OTG_DATA_FIFO_OFFSET   0x1000
 
+#define USB_OTG_DATA_FIFO_SIZE   0x1000
 
+#define USB_OTG_MAX_TX_FIFOS   15
 
+#define USB_OTG_HS_MAX_PACKET_SIZE   512
 
+#define USB_OTG_FS_MAX_PACKET_SIZE   64
 
+#define USB_OTG_MAX_EP0_SIZE   64
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Typedefs

+typedef struct _USB_OTG_GREGS USB_OTG_GREGS
 
+typedef struct _USB_OTG_DREGS USB_OTG_DREGS
 
+typedef struct _USB_OTG_INEPREGS USB_OTG_INEPREGS
 
+typedef struct _USB_OTG_OUTEPREGS USB_OTG_OUTEPREGS
 
+typedef struct _USB_OTG_HREGS USB_OTG_HREGS
 
+typedef struct _USB_OTG_HC_REGS USB_OTG_HC_REGS
 
+typedef struct USB_OTG_core_regs USB_OTG_CORE_REGS
 
+typedef struct USB_OTG_core_regs * PUSB_OTG_CORE_REGS
 
+typedef union _USB_OTG_OTGCTL_TypeDef USB_OTG_OTGCTL_TypeDef
 
+typedef union _USB_OTG_GOTGINT_TypeDef USB_OTG_GOTGINT_TypeDef
 
+typedef union _USB_OTG_GAHBCFG_TypeDef USB_OTG_GAHBCFG_TypeDef
 
+typedef union _USB_OTG_GUSBCFG_TypeDef USB_OTG_GUSBCFG_TypeDef
 
+typedef union _USB_OTG_GRSTCTL_TypeDef USB_OTG_GRSTCTL_TypeDef
 
+typedef union _USB_OTG_GINTMSK_TypeDef USB_OTG_GINTMSK_TypeDef
 
+typedef union _USB_OTG_GINTSTS_TypeDef USB_OTG_GINTSTS_TypeDef
 
+typedef union _USB_OTG_DRXSTS_TypeDef USB_OTG_DRXSTS_TypeDef
 
+typedef union _USB_OTG_GRXSTS_TypeDef USB_OTG_GRXFSTS_TypeDef
 
+typedef union _USB_OTG_FSIZ_TypeDef USB_OTG_FSIZ_TypeDef
 
+typedef union _USB_OTG_HNPTXSTS_TypeDef USB_OTG_HNPTXSTS_TypeDef
 
+typedef union _USB_OTG_DTXFSTSn_TypeDef USB_OTG_DTXFSTSn_TypeDef
 
+typedef union _USB_OTG_GI2CCTL_TypeDef USB_OTG_GI2CCTL_TypeDef
 
+typedef union _USB_OTG_GCCFG_TypeDef USB_OTG_GCCFG_TypeDef
 
+typedef union _USB_OTG_DCFG_TypeDef USB_OTG_DCFG_TypeDef
 
+typedef union _USB_OTG_DCTL_TypeDef USB_OTG_DCTL_TypeDef
 
+typedef union _USB_OTG_DSTS_TypeDef USB_OTG_DSTS_TypeDef
 
+typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPINTn_TypeDef
 
+typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef
 
+typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPINTn_TypeDef
 
+typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef
 
+typedef union _USB_OTG_DAINT_TypeDef USB_OTG_DAINT_TypeDef
 
+typedef union _USB_OTG_DTHRCTL_TypeDef USB_OTG_DTHRCTL_TypeDef
 
+typedef union _USB_OTG_DEPCTL_TypeDef USB_OTG_DEPCTL_TypeDef
 
+typedef union _USB_OTG_DEPXFRSIZ_TypeDef USB_OTG_DEPXFRSIZ_TypeDef
 
+typedef union _USB_OTG_DEP0XFRSIZ_TypeDef USB_OTG_DEP0XFRSIZ_TypeDef
 
+typedef union _USB_OTG_HCFG_TypeDef USB_OTG_HCFG_TypeDef
 
+typedef union _USB_OTG_HFRMINTRVL_TypeDef USB_OTG_HFRMINTRVL_TypeDef
 
+typedef union _USB_OTG_HFNUM_TypeDef USB_OTG_HFNUM_TypeDef
 
+typedef union _USB_OTG_HPTXSTS_TypeDef USB_OTG_HPTXSTS_TypeDef
 
+typedef union _USB_OTG_HPRT0_TypeDef USB_OTG_HPRT0_TypeDef
 
+typedef union _USB_OTG_HAINT_TypeDef USB_OTG_HAINT_TypeDef
 
+typedef union _USB_OTG_HAINTMSK_TypeDef USB_OTG_HAINTMSK_TypeDef
 
+typedef union _USB_OTG_HCCHAR_TypeDef USB_OTG_HCCHAR_TypeDef
 
+typedef union _USB_OTG_HCSPLT_TypeDef USB_OTG_HCSPLT_TypeDef
 
+typedef union _USB_OTG_HCINTn_TypeDef USB_OTG_HCINTn_TypeDef
 
+typedef union _USB_OTG_HCTSIZn_TypeDef USB_OTG_HCTSIZn_TypeDef
 
+typedef union _USB_OTG_HCGINTMSK_TypeDef USB_OTG_HCGINTMSK_TypeDef
 
+typedef union _USB_OTG_PCGCCTL_TypeDef USB_OTG_PCGCCTL_TypeDef
 
+

Detailed Description

+

hardware registers

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usb__regs_8h__dep__incl.map b/usb__regs_8h__dep__incl.map new file mode 100644 index 0000000..29270d2 --- /dev/null +++ b/usb__regs_8h__dep__incl.map @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__regs_8h__dep__incl.md5 b/usb__regs_8h__dep__incl.md5 new file mode 100644 index 0000000..51db7ee --- /dev/null +++ b/usb__regs_8h__dep__incl.md5 @@ -0,0 +1 @@ +e9cc5b126b186b48d189811eb5795b58 \ No newline at end of file diff --git a/usb__regs_8h__dep__incl.png b/usb__regs_8h__dep__incl.png new file mode 100644 index 0000000..dda85ba Binary files /dev/null and b/usb__regs_8h__dep__incl.png differ diff --git a/usb__regs_8h__incl.map b/usb__regs_8h__incl.map new file mode 100644 index 0000000..d989692 --- /dev/null +++ b/usb__regs_8h__incl.map @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usb__regs_8h__incl.md5 b/usb__regs_8h__incl.md5 new file mode 100644 index 0000000..ce0e8db --- /dev/null +++ b/usb__regs_8h__incl.md5 @@ -0,0 +1 @@ +c54930d9cfa57b7f21db4259f64c5cb7 \ No newline at end of file diff --git a/usb__regs_8h__incl.png b/usb__regs_8h__incl.png new file mode 100644 index 0000000..571c8f8 Binary files /dev/null and b/usb__regs_8h__incl.png differ diff --git a/usb__regs_8h_source.html b/usb__regs_8h_source.html new file mode 100644 index 0000000..e0e49e1 --- /dev/null +++ b/usb__regs_8h_source.html @@ -0,0 +1,1226 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_OTG_Driver/inc/usb_regs.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usb_regs.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USB_OTG_REGS_H__
+
24 #define __USB_OTG_REGS_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_conf.h"
+
28 
+
29 
+
44 #define USB_OTG_HS_BASE_ADDR 0x40040000
+
45 #define USB_OTG_FS_BASE_ADDR 0x50000000
+
46 
+
47 #define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000
+
48 #define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800
+
49 #define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900
+
50 #define USB_OTG_EP_REG_OFFSET 0x20
+
51 #define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00
+
52 #define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400
+
53 #define USB_OTG_HOST_PORT_REGS_OFFSET 0x440
+
54 #define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500
+
55 #define USB_OTG_CHAN_REGS_OFFSET 0x20
+
56 #define USB_OTG_PCGCCTL_OFFSET 0xE00
+
57 #define USB_OTG_DATA_FIFO_OFFSET 0x1000
+
58 #define USB_OTG_DATA_FIFO_SIZE 0x1000
+
59 
+
60 
+
61 #define USB_OTG_MAX_TX_FIFOS 15
+
62 
+
63 #define USB_OTG_HS_MAX_PACKET_SIZE 512
+
64 #define USB_OTG_FS_MAX_PACKET_SIZE 64
+
65 #define USB_OTG_MAX_EP0_SIZE 64
+
66 
+
77 typedef struct _USB_OTG_GREGS //000h
+
78 {
+
79  __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
+
80  __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
+
81  __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
+
82  __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
+
83  __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
+
84  __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
+
85  __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
+
86  __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
+
87  __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
+
88  __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+
89  __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
+
90  __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+
91  __IO uint32_t GI2CCTL; /* I2C Access Register 030h*/
+
92  uint32_t Reserved34; /* PHY Vendor Control Register 034h*/
+
93  __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+
94  __IO uint32_t CID; /* User ID Register 03Ch*/
+
95  uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+
96  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+
97  __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */
+
98 }
+
99 USB_OTG_GREGS;
+
108 typedef struct _USB_OTG_DREGS // 800h
+
109 {
+
110  __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+
111  __IO uint32_t DCTL; /* dev Control Register 804h*/
+
112  __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+
113  uint32_t Reserved0C; /* Reserved 80Ch*/
+
114  __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+
115  __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+
116  __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+
117  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+
118  uint32_t Reserved20; /* Reserved 820h*/
+
119  uint32_t Reserved9; /* Reserved 824h*/
+
120  __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+
121  __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+
122  __IO uint32_t DTHRCTL; /* dev thr 830h*/
+
123  __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+
124  __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+
125  __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+
126  uint32_t Reserved40; /* dedicated EP mask 840h*/
+
127  __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+
128  uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+
129  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+
130 }
+
131 USB_OTG_DREGS;
+
140 typedef struct _USB_OTG_INEPREGS
+
141 {
+
142  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+
143  uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+
144  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+
145  uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+
146  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+
147  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+
148  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+
149  uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+
150 }
+
151 USB_OTG_INEPREGS;
+
160 typedef struct _USB_OTG_OUTEPREGS
+
161 {
+
162  __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+
163  __IO uint32_t DOUTEPFRM; /* dev OUT Endpoint Frame number B00h + (ep_num * 20h) + 04h*/
+
164  __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+
165  uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+
166  __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+
167  __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+
168  uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+
169 }
+
170 USB_OTG_OUTEPREGS;
+
179 typedef struct _USB_OTG_HREGS
+
180 {
+
181  __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+
182  __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+
183  __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+
184  uint32_t Reserved40C; /* Reserved 40Ch*/
+
185  __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+
186  __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+
187  __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+
188 }
+
189 USB_OTG_HREGS;
+
198 typedef struct _USB_OTG_HC_REGS
+
199 {
+
200  __IO uint32_t HCCHAR;
+
201  __IO uint32_t HCSPLT;
+
202  __IO uint32_t HCINT;
+
203  __IO uint32_t HCGINTMSK;
+
204  __IO uint32_t HCTSIZ;
+
205  __IO uint32_t HCDMA;
+
206  uint32_t Reserved[2];
+
207 }
+
208 USB_OTG_HC_REGS;
+
217 typedef struct USB_OTG_core_regs //000h
+
218 {
+
219  USB_OTG_GREGS *GREGS;
+
220  USB_OTG_DREGS *DREGS;
+
221  USB_OTG_HREGS *HREGS;
+
222  USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS];
+
223  USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS];
+
224  USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS];
+
225  __IO uint32_t *HPRT0;
+
226  __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS];
+
227  __IO uint32_t *PCGCCTL;
+
228 }
+
229 USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS;
+
230 typedef union _USB_OTG_OTGCTL_TypeDef
+
231 {
+
232  uint32_t d32;
+
233  struct
+
234  {
+
235 uint32_t sesreqscs :
+
236  1;
+
237 uint32_t sesreq :
+
238  1;
+
239 uint32_t Reserved2_7 :
+
240  6;
+
241 uint32_t hstnegscs :
+
242  1;
+
243 uint32_t hnpreq :
+
244  1;
+
245 uint32_t hstsethnpen :
+
246  1;
+
247 uint32_t devhnpen :
+
248  1;
+
249 uint32_t Reserved12_15 :
+
250  4;
+
251 uint32_t conidsts :
+
252  1;
+
253 uint32_t Reserved17 :
+
254  1;
+
255 uint32_t asesvld :
+
256  1;
+
257 uint32_t bsesvld :
+
258  1;
+
259 uint32_t currmod :
+
260  1;
+
261 uint32_t Reserved21_31 :
+
262  11;
+
263  }
+
264  b;
+
265 } USB_OTG_OTGCTL_TypeDef ;
+
266 typedef union _USB_OTG_GOTGINT_TypeDef
+
267 {
+
268  uint32_t d32;
+
269  struct
+
270  {
+
271 uint32_t Reserved0_1 :
+
272  2;
+
273 uint32_t sesenddet :
+
274  1;
+
275 uint32_t Reserved3_7 :
+
276  5;
+
277 uint32_t sesreqsucstschng :
+
278  1;
+
279 uint32_t hstnegsucstschng :
+
280  1;
+
281 uint32_t reserver10_16 :
+
282  7;
+
283 uint32_t hstnegdet :
+
284  1;
+
285 uint32_t adevtoutchng :
+
286  1;
+
287 uint32_t debdone :
+
288  1;
+
289 uint32_t Reserved31_20 :
+
290  12;
+
291  }
+
292  b;
+
293 } USB_OTG_GOTGINT_TypeDef ;
+
294 typedef union _USB_OTG_GAHBCFG_TypeDef
+
295 {
+
296  uint32_t d32;
+
297  struct
+
298  {
+
299 uint32_t glblintrmsk :
+
300  1;
+
301 uint32_t hburstlen :
+
302  4;
+
303 uint32_t dmaenable :
+
304  1;
+
305 uint32_t Reserved :
+
306  1;
+
307 uint32_t nptxfemplvl_txfemplvl :
+
308  1;
+
309 uint32_t ptxfemplvl :
+
310  1;
+
311 uint32_t Reserved9_31 :
+
312  23;
+
313  }
+
314  b;
+
315 } USB_OTG_GAHBCFG_TypeDef ;
+
316 typedef union _USB_OTG_GUSBCFG_TypeDef
+
317 {
+
318  uint32_t d32;
+
319  struct
+
320  {
+
321 uint32_t toutcal :
+
322  3;
+
323 uint32_t phyif :
+
324  1;
+
325 uint32_t ulpi_utmi_sel :
+
326  1;
+
327 uint32_t fsintf :
+
328  1;
+
329 uint32_t physel :
+
330  1;
+
331 uint32_t ddrsel :
+
332  1;
+
333 uint32_t srpcap :
+
334  1;
+
335 uint32_t hnpcap :
+
336  1;
+
337 uint32_t usbtrdtim :
+
338  4;
+
339 uint32_t nptxfrwnden :
+
340  1;
+
341 uint32_t phylpwrclksel :
+
342  1;
+
343 uint32_t otgutmifssel :
+
344  1;
+
345 uint32_t ulpi_fsls :
+
346  1;
+
347 uint32_t ulpi_auto_res :
+
348  1;
+
349 uint32_t ulpi_clk_sus_m :
+
350  1;
+
351 uint32_t ulpi_ext_vbus_drv :
+
352  1;
+
353 uint32_t ulpi_int_vbus_indicator :
+
354  1;
+
355 uint32_t term_sel_dl_pulse :
+
356  1;
+
357 uint32_t Reserved :
+
358  6;
+
359 uint32_t force_host :
+
360  1;
+
361 uint32_t force_dev :
+
362  1;
+
363 uint32_t corrupt_tx :
+
364  1;
+
365  }
+
366  b;
+
367 } USB_OTG_GUSBCFG_TypeDef ;
+
368 typedef union _USB_OTG_GRSTCTL_TypeDef
+
369 {
+
370  uint32_t d32;
+
371  struct
+
372  {
+
373 uint32_t csftrst :
+
374  1;
+
375 uint32_t hsftrst :
+
376  1;
+
377 uint32_t hstfrm :
+
378  1;
+
379 uint32_t intknqflsh :
+
380  1;
+
381 uint32_t rxfflsh :
+
382  1;
+
383 uint32_t txfflsh :
+
384  1;
+
385 uint32_t txfnum :
+
386  5;
+
387 uint32_t Reserved11_29 :
+
388  19;
+
389 uint32_t dmareq :
+
390  1;
+
391 uint32_t ahbidle :
+
392  1;
+
393  }
+
394  b;
+
395 } USB_OTG_GRSTCTL_TypeDef ;
+
396 typedef union _USB_OTG_GINTMSK_TypeDef
+
397 {
+
398  uint32_t d32;
+
399  struct
+
400  {
+
401 uint32_t Reserved0 :
+
402  1;
+
403 uint32_t modemismatch :
+
404  1;
+
405 uint32_t otgintr :
+
406  1;
+
407 uint32_t sofintr :
+
408  1;
+
409 uint32_t rxstsqlvl :
+
410  1;
+
411 uint32_t nptxfempty :
+
412  1;
+
413 uint32_t ginnakeff :
+
414  1;
+
415 uint32_t goutnakeff :
+
416  1;
+
417 uint32_t Reserved8 :
+
418  1;
+
419 uint32_t i2cintr :
+
420  1;
+
421 uint32_t erlysuspend :
+
422  1;
+
423 uint32_t usbsuspend :
+
424  1;
+
425 uint32_t usbreset :
+
426  1;
+
427 uint32_t enumdone :
+
428  1;
+
429 uint32_t isooutdrop :
+
430  1;
+
431 uint32_t eopframe :
+
432  1;
+
433 uint32_t Reserved16 :
+
434  1;
+
435 uint32_t epmismatch :
+
436  1;
+
437 uint32_t inepintr :
+
438  1;
+
439 uint32_t outepintr :
+
440  1;
+
441 uint32_t incomplisoin :
+
442  1;
+
443 uint32_t incomplisoout :
+
444  1;
+
445 uint32_t Reserved22_23 :
+
446  2;
+
447 uint32_t portintr :
+
448  1;
+
449 uint32_t hcintr :
+
450  1;
+
451 uint32_t ptxfempty :
+
452  1;
+
453 uint32_t Reserved27 :
+
454  1;
+
455 uint32_t conidstschng :
+
456  1;
+
457 uint32_t disconnect :
+
458  1;
+
459 uint32_t sessreqintr :
+
460  1;
+
461 uint32_t wkupintr :
+
462  1;
+
463  }
+
464  b;
+
465 } USB_OTG_GINTMSK_TypeDef ;
+
466 typedef union _USB_OTG_GINTSTS_TypeDef
+
467 {
+
468  uint32_t d32;
+
469  struct
+
470  {
+
471 uint32_t curmode :
+
472  1;
+
473 uint32_t modemismatch :
+
474  1;
+
475 uint32_t otgintr :
+
476  1;
+
477 uint32_t sofintr :
+
478  1;
+
479 uint32_t rxstsqlvl :
+
480  1;
+
481 uint32_t nptxfempty :
+
482  1;
+
483 uint32_t ginnakeff :
+
484  1;
+
485 uint32_t goutnakeff :
+
486  1;
+
487 uint32_t Reserved8 :
+
488  1;
+
489 uint32_t i2cintr :
+
490  1;
+
491 uint32_t erlysuspend :
+
492  1;
+
493 uint32_t usbsuspend :
+
494  1;
+
495 uint32_t usbreset :
+
496  1;
+
497 uint32_t enumdone :
+
498  1;
+
499 uint32_t isooutdrop :
+
500  1;
+
501 uint32_t eopframe :
+
502  1;
+
503 uint32_t intimerrx :
+
504  1;
+
505 uint32_t epmismatch :
+
506  1;
+
507 uint32_t inepint:
+
508  1;
+
509 uint32_t outepintr :
+
510  1;
+
511 uint32_t incomplisoin :
+
512  1;
+
513 uint32_t incomplisoout :
+
514  1;
+
515 uint32_t Reserved22_23 :
+
516  2;
+
517 uint32_t portintr :
+
518  1;
+
519 uint32_t hcintr :
+
520  1;
+
521 uint32_t ptxfempty :
+
522  1;
+
523 uint32_t Reserved27 :
+
524  1;
+
525 uint32_t conidstschng :
+
526  1;
+
527 uint32_t disconnect :
+
528  1;
+
529 uint32_t sessreqintr :
+
530  1;
+
531 uint32_t wkupintr :
+
532  1;
+
533  }
+
534  b;
+
535 } USB_OTG_GINTSTS_TypeDef ;
+
536 typedef union _USB_OTG_DRXSTS_TypeDef
+
537 {
+
538  uint32_t d32;
+
539  struct
+
540  {
+
541 uint32_t epnum :
+
542  4;
+
543 uint32_t bcnt :
+
544  11;
+
545 uint32_t dpid :
+
546  2;
+
547 uint32_t pktsts :
+
548  4;
+
549 uint32_t fn :
+
550  4;
+
551 uint32_t Reserved :
+
552  7;
+
553  }
+
554  b;
+
555 } USB_OTG_DRXSTS_TypeDef ;
+
556 typedef union _USB_OTG_GRXSTS_TypeDef
+
557 {
+
558  uint32_t d32;
+
559  struct
+
560  {
+
561 uint32_t chnum :
+
562  4;
+
563 uint32_t bcnt :
+
564  11;
+
565 uint32_t dpid :
+
566  2;
+
567 uint32_t pktsts :
+
568  4;
+
569 uint32_t Reserved :
+
570  11;
+
571  }
+
572  b;
+
573 } USB_OTG_GRXFSTS_TypeDef ;
+
574 typedef union _USB_OTG_FSIZ_TypeDef
+
575 {
+
576  uint32_t d32;
+
577  struct
+
578  {
+
579 uint32_t startaddr :
+
580  16;
+
581 uint32_t depth :
+
582  16;
+
583  }
+
584  b;
+
585 } USB_OTG_FSIZ_TypeDef ;
+
586 typedef union _USB_OTG_HNPTXSTS_TypeDef
+
587 {
+
588  uint32_t d32;
+
589  struct
+
590  {
+
591 uint32_t nptxfspcavail :
+
592  16;
+
593 uint32_t nptxqspcavail :
+
594  8;
+
595 uint32_t nptxqtop_terminate :
+
596  1;
+
597 uint32_t nptxqtop_timer :
+
598  2;
+
599 uint32_t nptxqtop :
+
600  2;
+
601 uint32_t chnum :
+
602  2;
+
603 uint32_t Reserved :
+
604  1;
+
605  }
+
606  b;
+
607 } USB_OTG_HNPTXSTS_TypeDef ;
+
608 typedef union _USB_OTG_DTXFSTSn_TypeDef
+
609 {
+
610  uint32_t d32;
+
611  struct
+
612  {
+
613 uint32_t txfspcavail :
+
614  16;
+
615 uint32_t Reserved :
+
616  16;
+
617  }
+
618  b;
+
619 } USB_OTG_DTXFSTSn_TypeDef ;
+
620 typedef union _USB_OTG_GI2CCTL_TypeDef
+
621 {
+
622  uint32_t d32;
+
623  struct
+
624  {
+
625 uint32_t rwdata :
+
626  8;
+
627 uint32_t regaddr :
+
628  8;
+
629 uint32_t addr :
+
630  7;
+
631 uint32_t i2cen :
+
632  1;
+
633 uint32_t ack :
+
634  1;
+
635 uint32_t i2csuspctl :
+
636  1;
+
637 uint32_t i2cdevaddr :
+
638  2;
+
639 uint32_t dat_se0:
+
640  1;
+
641 uint32_t Reserved :
+
642  1;
+
643 uint32_t rw :
+
644  1;
+
645 uint32_t bsydne :
+
646  1;
+
647  }
+
648  b;
+
649 } USB_OTG_GI2CCTL_TypeDef ;
+
650 typedef union _USB_OTG_GCCFG_TypeDef
+
651 {
+
652  uint32_t d32;
+
653  struct
+
654  {
+
655 uint32_t Reserved_in :
+
656  16;
+
657 uint32_t pwdn :
+
658  1;
+
659 uint32_t i2cifen :
+
660  1;
+
661 uint32_t vbussensingA :
+
662  1;
+
663 uint32_t vbussensingB :
+
664  1;
+
665 uint32_t sofouten :
+
666  1;
+
667 uint32_t disablevbussensing :
+
668  1;
+
669 uint32_t Reserved_out :
+
670  10;
+
671  }
+
672  b;
+
673 } USB_OTG_GCCFG_TypeDef ;
+
674 
+
675 typedef union _USB_OTG_DCFG_TypeDef
+
676 {
+
677  uint32_t d32;
+
678  struct
+
679  {
+
680 uint32_t devspd :
+
681  2;
+
682 uint32_t nzstsouthshk :
+
683  1;
+
684 uint32_t Reserved3 :
+
685  1;
+
686 uint32_t devaddr :
+
687  7;
+
688 uint32_t perfrint :
+
689  2;
+
690 uint32_t Reserved13_17 :
+
691  5;
+
692 uint32_t epmscnt :
+
693  4;
+
694  }
+
695  b;
+
696 } USB_OTG_DCFG_TypeDef ;
+
697 typedef union _USB_OTG_DCTL_TypeDef
+
698 {
+
699  uint32_t d32;
+
700  struct
+
701  {
+
702 uint32_t rmtwkupsig :
+
703  1;
+
704 uint32_t sftdiscon :
+
705  1;
+
706 uint32_t gnpinnaksts :
+
707  1;
+
708 uint32_t goutnaksts :
+
709  1;
+
710 uint32_t tstctl :
+
711  3;
+
712 uint32_t sgnpinnak :
+
713  1;
+
714 uint32_t cgnpinnak :
+
715  1;
+
716 uint32_t sgoutnak :
+
717  1;
+
718 uint32_t cgoutnak :
+
719  1;
+
720 uint32_t Reserved :
+
721  21;
+
722  }
+
723  b;
+
724 } USB_OTG_DCTL_TypeDef ;
+
725 typedef union _USB_OTG_DSTS_TypeDef
+
726 {
+
727  uint32_t d32;
+
728  struct
+
729  {
+
730 uint32_t suspsts :
+
731  1;
+
732 uint32_t enumspd :
+
733  2;
+
734 uint32_t errticerr :
+
735  1;
+
736 uint32_t Reserved4_7:
+
737  4;
+
738 uint32_t soffn :
+
739  14;
+
740 uint32_t Reserved22_31 :
+
741  10;
+
742  }
+
743  b;
+
744 } USB_OTG_DSTS_TypeDef ;
+
745 typedef union _USB_OTG_DIEPINTn_TypeDef
+
746 {
+
747  uint32_t d32;
+
748  struct
+
749  {
+
750 uint32_t xfercompl :
+
751  1;
+
752 uint32_t epdisabled :
+
753  1;
+
754 uint32_t ahberr :
+
755  1;
+
756 uint32_t timeout :
+
757  1;
+
758 uint32_t intktxfemp :
+
759  1;
+
760 uint32_t intknepmis :
+
761  1;
+
762 uint32_t inepnakeff :
+
763  1;
+
764 uint32_t emptyintr :
+
765  1;
+
766 uint32_t txfifoundrn :
+
767  1;
+
768 uint32_t Reserved08_31 :
+
769  23;
+
770  }
+
771  b;
+
772 } USB_OTG_DIEPINTn_TypeDef ;
+
773 typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ;
+
774 typedef union _USB_OTG_DOEPINTn_TypeDef
+
775 {
+
776  uint32_t d32;
+
777  struct
+
778  {
+
779 uint32_t xfercompl :
+
780  1;
+
781 uint32_t epdisabled :
+
782  1;
+
783 uint32_t ahberr :
+
784  1;
+
785 uint32_t setup :
+
786  1;
+
787 uint32_t Reserved04_31 :
+
788  28;
+
789  }
+
790  b;
+
791 } USB_OTG_DOEPINTn_TypeDef ;
+
792 typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ;
+
793 
+
794 typedef union _USB_OTG_DAINT_TypeDef
+
795 {
+
796  uint32_t d32;
+
797  struct
+
798  {
+
799 uint32_t in :
+
800  16;
+
801 uint32_t out :
+
802  16;
+
803  }
+
804  ep;
+
805 } USB_OTG_DAINT_TypeDef ;
+
806 
+
807 typedef union _USB_OTG_DTHRCTL_TypeDef
+
808 {
+
809  uint32_t d32;
+
810  struct
+
811  {
+
812 uint32_t non_iso_thr_en :
+
813  1;
+
814 uint32_t iso_thr_en :
+
815  1;
+
816 uint32_t tx_thr_len :
+
817  9;
+
818 uint32_t Reserved11_15 :
+
819  5;
+
820 uint32_t rx_thr_en :
+
821  1;
+
822 uint32_t rx_thr_len :
+
823  9;
+
824 uint32_t Reserved26_31 :
+
825  6;
+
826  }
+
827  b;
+
828 } USB_OTG_DTHRCTL_TypeDef ;
+
829 typedef union _USB_OTG_DEPCTL_TypeDef
+
830 {
+
831  uint32_t d32;
+
832  struct
+
833  {
+
834 uint32_t mps :
+
835  11;
+
836 uint32_t reserved :
+
837  4;
+
838 uint32_t usbactep :
+
839  1;
+
840 uint32_t dpid :
+
841  1;
+
842 uint32_t naksts :
+
843  1;
+
844 uint32_t eptype :
+
845  2;
+
846 uint32_t snp :
+
847  1;
+
848 uint32_t stall :
+
849  1;
+
850 uint32_t txfnum :
+
851  4;
+
852 uint32_t cnak :
+
853  1;
+
854 uint32_t snak :
+
855  1;
+
856 uint32_t setd0pid :
+
857  1;
+
858 uint32_t setd1pid :
+
859  1;
+
860 uint32_t epdis :
+
861  1;
+
862 uint32_t epena :
+
863  1;
+
864  }
+
865  b;
+
866 } USB_OTG_DEPCTL_TypeDef ;
+
867 typedef union _USB_OTG_DEPXFRSIZ_TypeDef
+
868 {
+
869  uint32_t d32;
+
870  struct
+
871  {
+
872 uint32_t xfersize :
+
873  19;
+
874 uint32_t pktcnt :
+
875  10;
+
876 uint32_t mc :
+
877  2;
+
878 uint32_t Reserved :
+
879  1;
+
880  }
+
881  b;
+
882 } USB_OTG_DEPXFRSIZ_TypeDef ;
+
883 typedef union _USB_OTG_DEP0XFRSIZ_TypeDef
+
884 {
+
885  uint32_t d32;
+
886  struct
+
887  {
+
888 uint32_t xfersize :
+
889  7;
+
890 uint32_t Reserved7_18 :
+
891  12;
+
892 uint32_t pktcnt :
+
893  2;
+
894 uint32_t Reserved20_28 :
+
895  9;
+
896 uint32_t supcnt :
+
897  2;
+
898  uint32_t Reserved31;
+
899  }
+
900  b;
+
901 } USB_OTG_DEP0XFRSIZ_TypeDef ;
+
902 typedef union _USB_OTG_HCFG_TypeDef
+
903 {
+
904  uint32_t d32;
+
905  struct
+
906  {
+
907 uint32_t fslspclksel :
+
908  2;
+
909 uint32_t fslssupp :
+
910  1;
+
911  }
+
912  b;
+
913 } USB_OTG_HCFG_TypeDef ;
+
914 typedef union _USB_OTG_HFRMINTRVL_TypeDef
+
915 {
+
916  uint32_t d32;
+
917  struct
+
918  {
+
919 uint32_t frint :
+
920  16;
+
921 uint32_t Reserved :
+
922  16;
+
923  }
+
924  b;
+
925 } USB_OTG_HFRMINTRVL_TypeDef ;
+
926 
+
927 typedef union _USB_OTG_HFNUM_TypeDef
+
928 {
+
929  uint32_t d32;
+
930  struct
+
931  {
+
932 uint32_t frnum :
+
933  16;
+
934 uint32_t frrem :
+
935  16;
+
936  }
+
937  b;
+
938 } USB_OTG_HFNUM_TypeDef ;
+
939 typedef union _USB_OTG_HPTXSTS_TypeDef
+
940 {
+
941  uint32_t d32;
+
942  struct
+
943  {
+
944 uint32_t ptxfspcavail :
+
945  16;
+
946 uint32_t ptxqspcavail :
+
947  8;
+
948 uint32_t ptxqtop_terminate :
+
949  1;
+
950 uint32_t ptxqtop_timer :
+
951  2;
+
952 uint32_t ptxqtop :
+
953  2;
+
954 uint32_t chnum :
+
955  2;
+
956 uint32_t ptxqtop_odd :
+
957  1;
+
958  }
+
959  b;
+
960 } USB_OTG_HPTXSTS_TypeDef ;
+
961 typedef union _USB_OTG_HPRT0_TypeDef
+
962 {
+
963  uint32_t d32;
+
964  struct
+
965  {
+
966 uint32_t prtconnsts :
+
967  1;
+
968 uint32_t prtconndet :
+
969  1;
+
970 uint32_t prtena :
+
971  1;
+
972 uint32_t prtenchng :
+
973  1;
+
974 uint32_t prtovrcurract :
+
975  1;
+
976 uint32_t prtovrcurrchng :
+
977  1;
+
978 uint32_t prtres :
+
979  1;
+
980 uint32_t prtsusp :
+
981  1;
+
982 uint32_t prtrst :
+
983  1;
+
984 uint32_t Reserved9 :
+
985  1;
+
986 uint32_t prtlnsts :
+
987  2;
+
988 uint32_t prtpwr :
+
989  1;
+
990 uint32_t prttstctl :
+
991  4;
+
992 uint32_t prtspd :
+
993  2;
+
994 uint32_t Reserved19_31 :
+
995  13;
+
996  }
+
997  b;
+
998 } USB_OTG_HPRT0_TypeDef ;
+
999 typedef union _USB_OTG_HAINT_TypeDef
+
1000 {
+
1001  uint32_t d32;
+
1002  struct
+
1003  {
+
1004 uint32_t chint :
+
1005  16;
+
1006 uint32_t Reserved :
+
1007  16;
+
1008  }
+
1009  b;
+
1010 } USB_OTG_HAINT_TypeDef ;
+
1011 typedef union _USB_OTG_HAINTMSK_TypeDef
+
1012 {
+
1013  uint32_t d32;
+
1014  struct
+
1015  {
+
1016 uint32_t chint :
+
1017  16;
+
1018 uint32_t Reserved :
+
1019  16;
+
1020  }
+
1021  b;
+
1022 } USB_OTG_HAINTMSK_TypeDef ;
+
1023 typedef union _USB_OTG_HCCHAR_TypeDef
+
1024 {
+
1025  uint32_t d32;
+
1026  struct
+
1027  {
+
1028 uint32_t mps :
+
1029  11;
+
1030 uint32_t epnum :
+
1031  4;
+
1032 uint32_t epdir :
+
1033  1;
+
1034 uint32_t Reserved :
+
1035  1;
+
1036 uint32_t lspddev :
+
1037  1;
+
1038 uint32_t eptype :
+
1039  2;
+
1040 uint32_t multicnt :
+
1041  2;
+
1042 uint32_t devaddr :
+
1043  7;
+
1044 uint32_t oddfrm :
+
1045  1;
+
1046 uint32_t chdis :
+
1047  1;
+
1048 uint32_t chen :
+
1049  1;
+
1050  }
+
1051  b;
+
1052 } USB_OTG_HCCHAR_TypeDef ;
+
1053 typedef union _USB_OTG_HCSPLT_TypeDef
+
1054 {
+
1055  uint32_t d32;
+
1056  struct
+
1057  {
+
1058 uint32_t prtaddr :
+
1059  7;
+
1060 uint32_t hubaddr :
+
1061  7;
+
1062 uint32_t xactpos :
+
1063  2;
+
1064 uint32_t compsplt :
+
1065  1;
+
1066 uint32_t Reserved :
+
1067  14;
+
1068 uint32_t spltena :
+
1069  1;
+
1070  }
+
1071  b;
+
1072 } USB_OTG_HCSPLT_TypeDef ;
+
1073 typedef union _USB_OTG_HCINTn_TypeDef
+
1074 {
+
1075  uint32_t d32;
+
1076  struct
+
1077  {
+
1078 uint32_t xfercompl :
+
1079  1;
+
1080 uint32_t chhltd :
+
1081  1;
+
1082 uint32_t ahberr :
+
1083  1;
+
1084 uint32_t stall :
+
1085  1;
+
1086 uint32_t nak :
+
1087  1;
+
1088 uint32_t ack :
+
1089  1;
+
1090 uint32_t nyet :
+
1091  1;
+
1092 uint32_t xacterr :
+
1093  1;
+
1094 uint32_t bblerr :
+
1095  1;
+
1096 uint32_t frmovrun :
+
1097  1;
+
1098 uint32_t datatglerr :
+
1099  1;
+
1100 uint32_t Reserved :
+
1101  21;
+
1102  }
+
1103  b;
+
1104 } USB_OTG_HCINTn_TypeDef ;
+
1105 typedef union _USB_OTG_HCTSIZn_TypeDef
+
1106 {
+
1107  uint32_t d32;
+
1108  struct
+
1109  {
+
1110 uint32_t xfersize :
+
1111  19;
+
1112 uint32_t pktcnt :
+
1113  10;
+
1114 uint32_t pid :
+
1115  2;
+
1116 uint32_t dopng :
+
1117  1;
+
1118  }
+
1119  b;
+
1120 } USB_OTG_HCTSIZn_TypeDef ;
+
1121 typedef union _USB_OTG_HCGINTMSK_TypeDef
+
1122 {
+
1123  uint32_t d32;
+
1124  struct
+
1125  {
+
1126 uint32_t xfercompl :
+
1127  1;
+
1128 uint32_t chhltd :
+
1129  1;
+
1130 uint32_t ahberr :
+
1131  1;
+
1132 uint32_t stall :
+
1133  1;
+
1134 uint32_t nak :
+
1135  1;
+
1136 uint32_t ack :
+
1137  1;
+
1138 uint32_t nyet :
+
1139  1;
+
1140 uint32_t xacterr :
+
1141  1;
+
1142 uint32_t bblerr :
+
1143  1;
+
1144 uint32_t frmovrun :
+
1145  1;
+
1146 uint32_t datatglerr :
+
1147  1;
+
1148 uint32_t Reserved :
+
1149  21;
+
1150  }
+
1151  b;
+
1152 } USB_OTG_HCGINTMSK_TypeDef ;
+
1153 typedef union _USB_OTG_PCGCCTL_TypeDef
+
1154 {
+
1155  uint32_t d32;
+
1156  struct
+
1157  {
+
1158 uint32_t stoppclk :
+
1159  1;
+
1160 uint32_t gatehclk :
+
1161  1;
+
1162 uint32_t Reserved :
+
1163  30;
+
1164  }
+
1165  b;
+
1166 } USB_OTG_PCGCCTL_TypeDef ;
+
1167 
+
1195 #endif //__USB_OTG_REGS_H__
+
1196 
+
1197 
+
1205 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
1206 
+
_USB_OTG_HAINTMSK_TypeDef
Definition: usb_regs.h:1011
+
_USB_OTG_GCCFG_TypeDef
Definition: usb_regs.h:650
+
_USB_OTG_GINTSTS_TypeDef
Definition: usb_regs.h:466
+
_USB_OTG_OTGCTL_TypeDef
Definition: usb_regs.h:230
+
_USB_OTG_GRSTCTL_TypeDef
Definition: usb_regs.h:368
+
_USB_OTG_HREGS
Definition: usb_regs.h:179
+
_USB_OTG_DREGS
Definition: usb_regs.h:108
+
_USB_OTG_HC_REGS
Definition: usb_regs.h:198
+
_USB_OTG_FSIZ_TypeDef
Definition: usb_regs.h:574
+
_USB_OTG_GREGS
Definition: usb_regs.h:77
+
_USB_OTG_HPTXSTS_TypeDef
Definition: usb_regs.h:939
+
_USB_OTG_HCSPLT_TypeDef
Definition: usb_regs.h:1053
+
_USB_OTG_GAHBCFG_TypeDef
Definition: usb_regs.h:294
+
_USB_OTG_DTHRCTL_TypeDef
Definition: usb_regs.h:807
+
_USB_OTG_GI2CCTL_TypeDef
Definition: usb_regs.h:620
+
__IO
#define __IO
Definition: core_cm4.h:222
+
_USB_OTG_DEP0XFRSIZ_TypeDef
Definition: usb_regs.h:883
+
_USB_OTG_HAINT_TypeDef
Definition: usb_regs.h:999
+
_USB_OTG_INEPREGS
Definition: usb_regs.h:140
+
_USB_OTG_HCINTn_TypeDef
Definition: usb_regs.h:1073
+
_USB_OTG_DCTL_TypeDef
Definition: usb_regs.h:697
+
_USB_OTG_HCGINTMSK_TypeDef
Definition: usb_regs.h:1121
+
_USB_OTG_GUSBCFG_TypeDef
Definition: usb_regs.h:316
+
_USB_OTG_DAINT_TypeDef
Definition: usb_regs.h:794
+
_USB_OTG_HCCHAR_TypeDef
Definition: usb_regs.h:1023
+
_USB_OTG_HCTSIZn_TypeDef
Definition: usb_regs.h:1105
+
_USB_OTG_HNPTXSTS_TypeDef
Definition: usb_regs.h:586
+
_USB_OTG_HPRT0_TypeDef
Definition: usb_regs.h:961
+
_USB_OTG_DEPCTL_TypeDef
Definition: usb_regs.h:829
+
_USB_OTG_DCFG_TypeDef
Definition: usb_regs.h:675
+
_USB_OTG_DRXSTS_TypeDef
Definition: usb_regs.h:536
+
USB_OTG_core_regs
Definition: usb_regs.h:217
+
_USB_OTG_PCGCCTL_TypeDef
Definition: usb_regs.h:1153
+
_USB_OTG_DIEPINTn_TypeDef
Definition: usb_regs.h:745
+
_USB_OTG_OUTEPREGS
Definition: usb_regs.h:160
+
_USB_OTG_GINTMSK_TypeDef
Definition: usb_regs.h:396
+
_USB_OTG_DEPXFRSIZ_TypeDef
Definition: usb_regs.h:867
+
_USB_OTG_HFRMINTRVL_TypeDef
Definition: usb_regs.h:914
+
_USB_OTG_HCFG_TypeDef
Definition: usb_regs.h:902
+
_USB_OTG_DTXFSTSn_TypeDef
Definition: usb_regs.h:608
+
_USB_OTG_DSTS_TypeDef
Definition: usb_regs.h:725
+
_USB_OTG_DOEPINTn_TypeDef
Definition: usb_regs.h:774
+
_USB_OTG_HFNUM_TypeDef
Definition: usb_regs.h:927
+
_USB_OTG_GOTGINT_TypeDef
Definition: usb_regs.h:266
+
_USB_OTG_GRXSTS_TypeDef
Definition: usb_regs.h:556
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__conf_8h_source.html b/usbh__conf_8h_source.html new file mode 100644 index 0000000..02255d8 --- /dev/null +++ b/usbh__conf_8h_source.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_Device_Specific/usbh_conf.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usbh_conf.h
+
+
+
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USBH_CONF__H__
+
24 #define __USBH_CONF__H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
40 #define USBH_MAX_NUM_ENDPOINTS 2
+
41 #define USBH_MAX_NUM_INTERFACES 2
+
42 #ifdef USE_USB_OTG_FS
+
43 #define USBH_MSC_MPS_SIZE 0x40
+
44 #else
+
45 #define USBH_MSC_MPS_SIZE 0x200
+
46 #endif
+
47 
+
83 #endif //__USBH_CONF__H__
+
84 
+
85 
+
93 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
94 
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__conf__template_8h_source.html b/usbh__conf__template_8h_source.html new file mode 100644 index 0000000..7eccc4c --- /dev/null +++ b/usbh__conf__template_8h_source.html @@ -0,0 +1,120 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_conf_template.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usbh_conf_template.h
+
+
+
1 
+
22 /* Define to prevent recursive inclusion -------------------------------------*/
+
23 #ifndef __USBH_CONF__H__
+
24 #define __USBH_CONF__H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
40 #define USBH_MAX_NUM_ENDPOINTS 2
+
41 #define USBH_MAX_NUM_INTERFACES 2
+
42 #ifdef USE_USB_OTG_FS
+
43 #define USBH_MSC_MPS_SIZE 0x40
+
44 #else
+
45 #define USBH_MSC_MPS_SIZE 0x200
+
46 #endif
+
47 
+
83 #endif //__USBH_CONF__H__
+
84 
+
85 
+
93 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
94 
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__core_8c.html b/usbh__core_8c.html new file mode 100644 index 0000000..166f0a3 --- /dev/null +++ b/usbh__core_8c.html @@ -0,0 +1,157 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src/usbh_core.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Functions | +Variables
+
+
usbh_core.c File Reference
+
+
+ +

This file implements the functions for the core state machine process the enumeration and the control transfer process. +More...

+
#include "usbh_ioreq.h"
+#include "usb_bsp.h"
+#include "usbh_hcs.h"
+#include "usbh_stdreq.h"
+#include "usbh_core.h"
+
+Include dependency graph for usbh_core.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USBH_Disconnect (void *pdev)
 USBH_Disconnect USB Disconnect callback function from the Interrupt. More...
 
void USBH_Connect (void *pdev)
 USBH_Connect USB Connect callback function from the Interrupt. More...
 
USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_HandleControl Handles the USB control transfer state machine. More...
 
void USBH_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb)
 USBH_Init Host hardware and stack initializations. More...
 
USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_DeInit Re-Initialize Host. More...
 
void USBH_Process (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_Process USB Host core main state machine process. More...
 
void USBH_ErrorHandle (USBH_HOST *phost, USBH_Status errType)
 USBH_ErrorHandle This function handles the Error on Host side. More...
 
+ + + +

+Variables

USB_OTG_hPort_TypeDef USBH_DeviceConnStatus_cb
 
+

Detailed Description

+

This file implements the functions for the core state machine process the enumeration and the control transfer process.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__core_8c__incl.map b/usbh__core_8c__incl.map new file mode 100644 index 0000000..b1b2288 --- /dev/null +++ b/usbh__core_8c__incl.map @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__core_8c__incl.md5 b/usbh__core_8c__incl.md5 new file mode 100644 index 0000000..872afed --- /dev/null +++ b/usbh__core_8c__incl.md5 @@ -0,0 +1 @@ +eed90e420f9ae1fa293f7d0269effbe7 \ No newline at end of file diff --git a/usbh__core_8c__incl.png b/usbh__core_8c__incl.png new file mode 100644 index 0000000..85668e2 Binary files /dev/null and b/usbh__core_8c__incl.png differ diff --git a/usbh__core_8h.html b/usbh__core_8h.html new file mode 100644 index 0000000..af17dc6 --- /dev/null +++ b/usbh__core_8h.html @@ -0,0 +1,289 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+Classes | +Macros | +Typedefs | +Enumerations | +Functions
+
+
usbh_core.h File Reference
+
+
+ +

Header file for usbh_core.c. +More...

+
#include "usb_hcd.h"
+#include "usbh_def.h"
+#include "usbh_conf.h"
+
+Include dependency graph for usbh_core.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + +

+Classes

struct  _Ctrl
 
struct  _DeviceProp
 
struct  _USBH_Class_cb
 
struct  _USBH_USR_PROP
 
struct  _Host_TypeDef
 
+ + + + + + + + + + + + + + + +

+Macros

+#define MSC_CLASS   0x08
 
+#define HID_CLASS   0x03
 
+#define MSC_PROTOCOL   0x50
 
+#define CBI_PROTOCOL   0x01
 
+#define USBH_MAX_ERROR_COUNT   2
 
+#define USBH_DEVICE_ADDRESS_DEFAULT   0
 
+#define USBH_DEVICE_ADDRESS   1
 
+ + + + + + + + + + + + + +

+Typedefs

+typedef struct _Ctrl USBH_Ctrl_TypeDef
 
+typedef struct _DeviceProp USBH_Device_TypeDef
 
+typedef struct _USBH_Class_cb USBH_Class_cb_TypeDef
 
+typedef struct _USBH_USR_PROP USBH_Usr_cb_TypeDef
 
+typedef struct _Host_TypeDef USBH_HOST
 
+typedef struct _Host_TypeDef * pUSBH_HOST
 
+ + + + + + + + + + + + + +

+Enumerations

enum  USBH_Status {
+  USBH_OK = 0, +USBH_BUSY, +USBH_FAIL, +USBH_NOT_SUPPORTED, +
+  USBH_UNRECOVERED_ERROR, +USBH_ERROR_SPEED_UNKNOWN, +USBH_APPLY_DEINIT +
+ }
 
enum  HOST_State {
+  HOST_IDLE =0, +HOST_ISSUE_CORE_RESET, +HOST_DEV_ATTACHED, +HOST_DEV_DISCONNECTED, +
+  HOST_ISSUE_RESET, +HOST_DETECT_DEVICE_SPEED, +HOST_ENUMERATION, +HOST_CLASS_REQUEST, +
+  HOST_CLASS, +HOST_CTRL_XFER, +HOST_USR_INPUT, +HOST_SUSPENDED, +
+  HOST_ERROR_STATE +
+ }
 
enum  ENUM_State {
+  ENUM_IDLE = 0, +ENUM_GET_FULL_DEV_DESC, +ENUM_SET_ADDR, +ENUM_GET_CFG_DESC, +
+  ENUM_GET_FULL_CFG_DESC, +ENUM_GET_MFC_STRING_DESC, +ENUM_GET_PRODUCT_STRING_DESC, +ENUM_GET_SERIALNUM_STRING_DESC, +
+  ENUM_SET_CONFIGURATION, +ENUM_DEV_CONFIGURED +
+ }
 
enum  CTRL_State {
+  CTRL_IDLE =0, +CTRL_SETUP, +CTRL_SETUP_WAIT, +CTRL_DATA_IN, +
+  CTRL_DATA_IN_WAIT, +CTRL_DATA_OUT, +CTRL_DATA_OUT_WAIT, +CTRL_STATUS_IN, +
+  CTRL_STATUS_IN_WAIT, +CTRL_STATUS_OUT, +CTRL_STATUS_OUT_WAIT, +CTRL_ERROR +
+ }
 
enum  USBH_USR_Status { USBH_USR_NO_RESP = 0, +USBH_USR_RESP_OK = 1 + }
 
enum  CMD_State { CMD_IDLE =0, +CMD_SEND, +CMD_WAIT + }
 
+ + + + + + + + + + + + + +

+Functions

void USBH_Init (USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb)
 USBH_Init Host hardware and stack initializations. More...
 
USBH_Status USBH_DeInit (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_DeInit Re-Initialize Host. More...
 
void USBH_Process (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_Process USB Host core main state machine process. More...
 
void USBH_ErrorHandle (USBH_HOST *phost, USBH_Status errType)
 USBH_ErrorHandle This function handles the Error on Host side. More...
 
+

Detailed Description

+

Header file for usbh_core.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__core_8h__dep__incl.map b/usbh__core_8h__dep__incl.map new file mode 100644 index 0000000..ef75e2c --- /dev/null +++ b/usbh__core_8h__dep__incl.map @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__core_8h__dep__incl.md5 b/usbh__core_8h__dep__incl.md5 new file mode 100644 index 0000000..0c4c89a --- /dev/null +++ b/usbh__core_8h__dep__incl.md5 @@ -0,0 +1 @@ +bdf518b581a4a09539d9f5c0874ec140 \ No newline at end of file diff --git a/usbh__core_8h__dep__incl.png b/usbh__core_8h__dep__incl.png new file mode 100644 index 0000000..d359d0b Binary files /dev/null and b/usbh__core_8h__dep__incl.png differ diff --git a/usbh__core_8h__incl.map b/usbh__core_8h__incl.map new file mode 100644 index 0000000..3034b2a --- /dev/null +++ b/usbh__core_8h__incl.map @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__core_8h__incl.md5 b/usbh__core_8h__incl.md5 new file mode 100644 index 0000000..3500c27 --- /dev/null +++ b/usbh__core_8h__incl.md5 @@ -0,0 +1 @@ +8ccc63df6b32b4f5db061d49ddb04661 \ No newline at end of file diff --git a/usbh__core_8h__incl.png b/usbh__core_8h__incl.png new file mode 100644 index 0000000..cb93928 Binary files /dev/null and b/usbh__core_8h__incl.png differ diff --git a/usbh__core_8h_source.html b/usbh__core_8h_source.html new file mode 100644 index 0000000..5edc2fd --- /dev/null +++ b/usbh__core_8h_source.html @@ -0,0 +1,321 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_core.h Source File + + + + + + + + + + +
+
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+
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+
+
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+
+ + +
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+
+
+
usbh_core.h
+
+
+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_CORE_H
+
24 #define __USBH_CORE_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_hcd.h"
+
28 #include "usbh_def.h"
+
29 #include "usbh_conf.h"
+
30 
+
49 #define MSC_CLASS 0x08
+
50 #define HID_CLASS 0x03
+
51 #define MSC_PROTOCOL 0x50
+
52 #define CBI_PROTOCOL 0x01
+
53 
+
54 
+
55 #define USBH_MAX_ERROR_COUNT 2
+
56 #define USBH_DEVICE_ADDRESS_DEFAULT 0
+
57 #define USBH_DEVICE_ADDRESS 1
+
58 
+
59 
+
69 typedef enum {
+
70  USBH_OK = 0,
+
71  USBH_BUSY,
+
72  USBH_FAIL,
+
73  USBH_NOT_SUPPORTED,
+
74  USBH_UNRECOVERED_ERROR,
+
75  USBH_ERROR_SPEED_UNKNOWN,
+
76  USBH_APPLY_DEINIT
+
77 }USBH_Status;
+
78 
+
79 /* Following states are used for gState */
+
80 typedef enum {
+
81  HOST_IDLE =0,
+
82  HOST_ISSUE_CORE_RESET,
+
83  HOST_DEV_ATTACHED,
+
84  HOST_DEV_DISCONNECTED,
+
85  HOST_ISSUE_RESET,
+
86  HOST_DETECT_DEVICE_SPEED,
+
87  HOST_ENUMERATION,
+
88  HOST_CLASS_REQUEST,
+
89  HOST_CLASS,
+
90  HOST_CTRL_XFER,
+
91  HOST_USR_INPUT,
+
92  HOST_SUSPENDED,
+
93  HOST_ERROR_STATE
+
94 }HOST_State;
+
95 
+
96 /* Following states are used for EnumerationState */
+
97 typedef enum {
+
98  ENUM_IDLE = 0,
+
99  ENUM_GET_FULL_DEV_DESC,
+
100  ENUM_SET_ADDR,
+
101  ENUM_GET_CFG_DESC,
+
102  ENUM_GET_FULL_CFG_DESC,
+
103  ENUM_GET_MFC_STRING_DESC,
+
104  ENUM_GET_PRODUCT_STRING_DESC,
+
105  ENUM_GET_SERIALNUM_STRING_DESC,
+
106  ENUM_SET_CONFIGURATION,
+
107  ENUM_DEV_CONFIGURED
+
108 } ENUM_State;
+
109 
+
110 
+
111 
+
112 /* Following states are used for CtrlXferStateMachine */
+
113 typedef enum {
+
114  CTRL_IDLE =0,
+
115  CTRL_SETUP,
+
116  CTRL_SETUP_WAIT,
+
117  CTRL_DATA_IN,
+
118  CTRL_DATA_IN_WAIT,
+
119  CTRL_DATA_OUT,
+
120  CTRL_DATA_OUT_WAIT,
+
121  CTRL_STATUS_IN,
+
122  CTRL_STATUS_IN_WAIT,
+
123  CTRL_STATUS_OUT,
+
124  CTRL_STATUS_OUT_WAIT,
+
125  CTRL_ERROR
+
126 }
+
127 CTRL_State;
+
128 
+
129 typedef enum {
+
130  USBH_USR_NO_RESP = 0,
+
131  USBH_USR_RESP_OK = 1,
+
132 }
+
133 USBH_USR_Status;
+
134 
+
135 /* Following states are used for RequestState */
+
136 typedef enum {
+
137  CMD_IDLE =0,
+
138  CMD_SEND,
+
139  CMD_WAIT
+
140 } CMD_State;
+
141 
+
142 
+
143 
+
144 typedef struct _Ctrl
+
145 {
+
146  uint8_t hc_num_in;
+
147  uint8_t hc_num_out;
+
148  uint8_t ep0size;
+
149  uint8_t *buff;
+
150  uint16_t length;
+
151  uint8_t errorcount;
+
152  uint16_t timer;
+
153  CTRL_STATUS status;
+
154  USB_Setup_TypeDef setup;
+
155  CTRL_State state;
+
156 
+
157 } USBH_Ctrl_TypeDef;
+
158 
+
159 
+
160 
+
161 typedef struct _DeviceProp
+
162 {
+
163 
+
164  uint8_t address;
+
165  uint8_t speed;
+
166  USBH_DevDesc_TypeDef Dev_Desc;
+
167  USBH_CfgDesc_TypeDef Cfg_Desc;
+
168  USBH_InterfaceDesc_TypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES];
+
169  USBH_EpDesc_TypeDef Ep_Desc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS];
+
170  USBH_HIDDesc_TypeDef HID_Desc;
+
171 
+
172 }USBH_Device_TypeDef;
+
173 
+
174 typedef struct _USBH_Class_cb
+
175 {
+
176  USBH_Status (*Init)\
+
177  (USB_OTG_CORE_HANDLE *pdev , void *phost);
+
178  void (*DeInit)\
+
179  (USB_OTG_CORE_HANDLE *pdev , void *phost);
+
180  USBH_Status (*Requests)\
+
181  (USB_OTG_CORE_HANDLE *pdev , void *phost);
+
182  USBH_Status (*Machine)\
+
183  (USB_OTG_CORE_HANDLE *pdev , void *phost);
+
184 
+
185 } USBH_Class_cb_TypeDef;
+
186 
+
187 
+
188 typedef struct _USBH_USR_PROP
+
189 {
+
190  void (*Init)(void); /* HostLibInitialized */
+
191  void (*DeInit)(void); /* HostLibInitialized */
+
192  void (*DeviceAttached)(void); /* DeviceAttached */
+
193  void (*ResetDevice)(void);
+
194  void (*DeviceDisconnected)(void);
+
195  void (*OverCurrentDetected)(void);
+
196  void (*DeviceSpeedDetected)(uint8_t DeviceSpeed); /* DeviceSpeed */
+
197  void (*DeviceDescAvailable)(void *); /* DeviceDescriptor is available */
+
198  void (*DeviceAddressAssigned)(void); /* Address is assigned to USB Device */
+
199  void (*ConfigurationDescAvailable)(USBH_CfgDesc_TypeDef *,
+
200  USBH_InterfaceDesc_TypeDef *,
+
201  USBH_EpDesc_TypeDef *);
+
202  /* Configuration Descriptor available */
+
203  void (*ManufacturerString)(void *); /* ManufacturerString*/
+
204  void (*ProductString)(void *); /* ProductString*/
+
205  void (*SerialNumString)(void *); /* SerialNubString*/
+
206  void (*EnumerationDone)(void); /* Enumeration finished */
+
207  USBH_USR_Status (*UserInput)(void);
+
208  int (*USBH_USR_MSC_Application) (void);
+
209  void (*USBH_USR_DeviceNotSupported)(void); /* Device is not supported*/
+
210  void (*UnrecoveredError)(void);
+
211 
+
212 }
+
213 USBH_Usr_cb_TypeDef;
+
214 
+
215 typedef struct _Host_TypeDef
+
216 {
+
217  HOST_State gState; /* Host State Machine Value */
+
218  HOST_State gStateBkp; /* backup of previous State machine value */
+
219  ENUM_State EnumState; /* Enumeration state Machine */
+
220  CMD_State RequestState;
+
221  USBH_Ctrl_TypeDef Control;
+
222 
+
223  USBH_Device_TypeDef device_prop;
+
224 
+
225  USBH_Class_cb_TypeDef *class_cb;
+
226  USBH_Usr_cb_TypeDef *usr_cb;
+
227 
+
228 
+
229 } USBH_HOST, *pUSBH_HOST;
+
230 
+
256 void USBH_Init(USB_OTG_CORE_HANDLE *pdev,
+
257  USB_OTG_CORE_ID_TypeDef coreID,
+
258  USBH_HOST *phost,
+
259  USBH_Class_cb_TypeDef *class_cb,
+
260  USBH_Usr_cb_TypeDef *usr_cb);
+
261 
+
262 USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev,
+
263  USBH_HOST *phost);
+
264 void USBH_Process(USB_OTG_CORE_HANDLE *pdev ,
+
265  USBH_HOST *phost);
+
266 void USBH_ErrorHandle(USBH_HOST *phost,
+
267  USBH_Status errType);
+
268 
+
273 #endif /* __USBH_CORE_H */
+
274 
+
286 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
287 
+
288 
+
289 
+
USBH_DeInit
USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
USBH_DeInit Re-Initialize Host.
Definition: usbh_core.c:184
+
usb_hcd.h
Host layer Header file.
+
_EndpointDescriptor
Definition: usbh_def.h:268
+
USBH_ErrorHandle
void USBH_ErrorHandle(USBH_HOST *phost, USBH_Status errType)
USBH_ErrorHandle This function handles the Error on Host side.
Definition: usbh_core.c:363
+
USB_OTG_handle
Definition: usb_core.h:287
+
_DeviceDescriptor
Definition: usbh_def.h:202
+
USBH_Process
void USBH_Process(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
USBH_Process USB Host core main state machine process.
Definition: usbh_core.c:210
+
_ConfigurationDescriptor
Definition: usbh_def.h:225
+
_Ctrl
Definition: usbh_core.h:144
+
_DeviceProp
Definition: usbh_core.h:161
+
_USB_Setup
Definition: usbh_def.h:180
+
_HIDDescriptor
Definition: usbh_def.h:239
+
_InterfaceDescriptor
Definition: usbh_def.h:252
+
_Host_TypeDef
Definition: usbh_core.h:215
+
usbh_def.h
Definitions used in the USB host library.
+
USBH_Init
void USBH_Init(USB_OTG_CORE_HANDLE *pdev, USB_OTG_CORE_ID_TypeDef coreID, USBH_HOST *phost, USBH_Class_cb_TypeDef *class_cb, USBH_Usr_cb_TypeDef *usr_cb)
USBH_Init Host hardware and stack initializations.
Definition: usbh_core.c:142
+
_USBH_USR_PROP
Definition: usbh_core.h:188
+
_USBH_Class_cb
Definition: usbh_core.h:174
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__def_8h.html b/usbh__def_8h.html new file mode 100644 index 0000000..5d55a51 --- /dev/null +++ b/usbh__def_8h.html @@ -0,0 +1,404 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h File Reference + + + + + + + + + + +
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+Classes | +Macros | +Typedefs
+
+
usbh_def.h File Reference
+
+
+ +

Definitions used in the USB host library. +More...

+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + +

+Classes

union  uint16_t_uint8_t
 
struct  uint16_t_uint8_t::BW
 
union  _USB_Setup
 
struct  _USB_Setup::_SetupPkt_Struc
 
struct  _DescHeader
 
struct  _DeviceDescriptor
 
struct  _ConfigurationDescriptor
 
struct  _HIDDescriptor
 
struct  _InterfaceDescriptor
 
struct  _EndpointDescriptor
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USBH_NULL   ((void *)0)
 
+#define FALSE   0
 
+#define TRUE   1
 
+#define ValBit(VAR, POS)   (VAR & (1 << POS))
 
+#define SetBit(VAR, POS)   (VAR |= (1 << POS))
 
+#define ClrBit(VAR, POS)   (VAR &= ((1 << POS)^255))
 
#define LE16(addr)
 
+#define USB_LEN_DESC_HDR   0x02
 
+#define USB_LEN_DEV_DESC   0x12
 
+#define USB_LEN_CFG_DESC   0x09
 
+#define USB_LEN_IF_DESC   0x09
 
+#define USB_LEN_EP_DESC   0x07
 
+#define USB_LEN_OTG_DESC   0x03
 
+#define USB_LEN_SETUP_PKT   0x08
 
+#define USB_REQ_DIR_MASK   0x80
 
+#define USB_H2D   0x00
 
+#define USB_D2H   0x80
 
+#define USB_REQ_TYPE_STANDARD   0x00
 
+#define USB_REQ_TYPE_CLASS   0x20
 
+#define USB_REQ_TYPE_VENDOR   0x40
 
+#define USB_REQ_TYPE_RESERVED   0x60
 
+#define USB_REQ_RECIPIENT_DEVICE   0x00
 
+#define USB_REQ_RECIPIENT_INTERFACE   0x01
 
+#define USB_REQ_RECIPIENT_ENDPOINT   0x02
 
+#define USB_REQ_RECIPIENT_OTHER   0x03
 
+#define USB_REQ_GET_STATUS   0x00
 
+#define USB_REQ_CLEAR_FEATURE   0x01
 
+#define USB_REQ_SET_FEATURE   0x03
 
+#define USB_REQ_SET_ADDRESS   0x05
 
+#define USB_REQ_GET_DESCRIPTOR   0x06
 
+#define USB_REQ_SET_DESCRIPTOR   0x07
 
+#define USB_REQ_GET_CONFIGURATION   0x08
 
+#define USB_REQ_SET_CONFIGURATION   0x09
 
+#define USB_REQ_GET_INTERFACE   0x0A
 
+#define USB_REQ_SET_INTERFACE   0x0B
 
+#define USB_REQ_SYNCH_FRAME   0x0C
 
+#define USB_DESC_TYPE_DEVICE   1
 
+#define USB_DESC_TYPE_CONFIGURATION   2
 
+#define USB_DESC_TYPE_STRING   3
 
+#define USB_DESC_TYPE_INTERFACE   4
 
+#define USB_DESC_TYPE_ENDPOINT   5
 
+#define USB_DESC_TYPE_DEVICE_QUALIFIER   6
 
+#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION   7
 
+#define USB_DESC_TYPE_INTERFACE_POWER   8
 
+#define USB_DESC_TYPE_HID   0x21
 
+#define USB_DESC_TYPE_HID_REPORT   0x22
 
+#define USB_DEVICE_DESC_SIZE   18
 
+#define USB_CONFIGURATION_DESC_SIZE   9
 
+#define USB_HID_DESC_SIZE   9
 
+#define USB_INTERFACE_DESC_SIZE   9
 
+#define USB_ENDPOINT_DESC_SIZE   7
 
+#define USB_DESC_DEVICE   ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00)
 
+#define USB_DESC_CONFIGURATION   ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00)
 
+#define USB_DESC_STRING   ((USB_DESC_TYPE_STRING << 8) & 0xFF00)
 
+#define USB_DESC_INTERFACE   ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
 
+#define USB_DESC_ENDPOINT   ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
 
+#define USB_DESC_DEVICE_QUALIFIER   ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00)
 
+#define USB_DESC_OTHER_SPEED_CONFIGURATION   ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00)
 
+#define USB_DESC_INTERFACE_POWER   ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00)
 
+#define USB_DESC_HID_REPORT   ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00)
 
+#define USB_DESC_HID   ((USB_DESC_TYPE_HID << 8) & 0xFF00)
 
+#define USB_EP_TYPE_CTRL   0x00
 
+#define USB_EP_TYPE_ISOC   0x01
 
+#define USB_EP_TYPE_BULK   0x02
 
+#define USB_EP_TYPE_INTR   0x03
 
+#define USB_EP_DIR_OUT   0x00
 
+#define USB_EP_DIR_IN   0x80
 
+#define USB_EP_DIR_MSK   0x80
 
+#define USB_MSC_CLASS   0x08
 
+#define USB_HID_CLASS   0x03
 
+#define HID_BOOT_CODE   0x01
 
+#define HID_KEYBRD_BOOT_CODE   0x01
 
+#define HID_MOUSE_BOOT_CODE   0x02
 
+#define DATA_STAGE_TIMEOUT   5000
 
+#define NODATA_STAGE_TIMEOUT   50
 
#define USBH_CONFIGURATION_DESCRIPTOR_SIZE
 
#define CONFIG_DESC_wTOTAL_LENGTH
 
+ + + + + + + + + + + + + + + +

+Typedefs

+typedef union _USB_Setup USB_Setup_TypeDef
 
+typedef struct _DescHeader USBH_DescHeader_t
 
+typedef struct _DeviceDescriptor USBH_DevDesc_TypeDef
 
+typedef struct _ConfigurationDescriptor USBH_CfgDesc_TypeDef
 
+typedef struct _HIDDescriptor USBH_HIDDesc_TypeDef
 
+typedef struct _InterfaceDescriptor USBH_InterfaceDesc_TypeDef
 
+typedef struct _EndpointDescriptor USBH_EpDesc_TypeDef
 
+

Detailed Description

+

Definitions used in the USB host library.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__def_8h__dep__incl.map b/usbh__def_8h__dep__incl.map new file mode 100644 index 0000000..c82faa4 --- /dev/null +++ b/usbh__def_8h__dep__incl.map @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__def_8h__dep__incl.md5 b/usbh__def_8h__dep__incl.md5 new file mode 100644 index 0000000..d9a8817 --- /dev/null +++ b/usbh__def_8h__dep__incl.md5 @@ -0,0 +1 @@ +282e4eb0273c8115ab2d4016eab0d8fb \ No newline at end of file diff --git a/usbh__def_8h__dep__incl.png b/usbh__def_8h__dep__incl.png new file mode 100644 index 0000000..19ef12f Binary files /dev/null and b/usbh__def_8h__dep__incl.png differ diff --git a/usbh__def_8h_source.html b/usbh__def_8h_source.html new file mode 100644 index 0000000..bffa9f1 --- /dev/null +++ b/usbh__def_8h_source.html @@ -0,0 +1,354 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_def.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
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+
usbh_def.h
+
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+Go to the documentation of this file.
1 
+
34 #ifndef USBH_DEF_H
+
35 #define USBH_DEF_H
+
36 
+
37 #ifndef USBH_NULL
+
38 #define USBH_NULL ((void *)0)
+
39 #endif
+
40 
+
41 #ifndef FALSE
+
42 #define FALSE 0
+
43 #endif
+
44 
+
45 #ifndef TRUE
+
46 #define TRUE 1
+
47 #endif
+
48 
+
49 
+
50 #define ValBit(VAR,POS) (VAR & (1 << POS))
+
51 #define SetBit(VAR,POS) (VAR |= (1 << POS))
+
52 #define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255))
+
53 
+
54 #define LE16(addr) (((u16)(*((u8 *)(addr))))\
+
55  + (((u16)(*(((u8 *)(addr)) + 1))) << 8))
+
56 
+
57 #define USB_LEN_DESC_HDR 0x02
+
58 #define USB_LEN_DEV_DESC 0x12
+
59 #define USB_LEN_CFG_DESC 0x09
+
60 #define USB_LEN_IF_DESC 0x09
+
61 #define USB_LEN_EP_DESC 0x07
+
62 #define USB_LEN_OTG_DESC 0x03
+
63 #define USB_LEN_SETUP_PKT 0x08
+
64 
+
65 /* bmRequestType :D7 Data Phase Transfer Direction */
+
66 #define USB_REQ_DIR_MASK 0x80
+
67 #define USB_H2D 0x00
+
68 #define USB_D2H 0x80
+
69 
+
70 /* bmRequestType D6..5 Type */
+
71 #define USB_REQ_TYPE_STANDARD 0x00
+
72 #define USB_REQ_TYPE_CLASS 0x20
+
73 #define USB_REQ_TYPE_VENDOR 0x40
+
74 #define USB_REQ_TYPE_RESERVED 0x60
+
75 
+
76 /* bmRequestType D4..0 Recipient */
+
77 #define USB_REQ_RECIPIENT_DEVICE 0x00
+
78 #define USB_REQ_RECIPIENT_INTERFACE 0x01
+
79 #define USB_REQ_RECIPIENT_ENDPOINT 0x02
+
80 #define USB_REQ_RECIPIENT_OTHER 0x03
+
81 
+
82 /* Table 9-4. Standard Request Codes */
+
83 /* bRequest , Value */
+
84 #define USB_REQ_GET_STATUS 0x00
+
85 #define USB_REQ_CLEAR_FEATURE 0x01
+
86 #define USB_REQ_SET_FEATURE 0x03
+
87 #define USB_REQ_SET_ADDRESS 0x05
+
88 #define USB_REQ_GET_DESCRIPTOR 0x06
+
89 #define USB_REQ_SET_DESCRIPTOR 0x07
+
90 #define USB_REQ_GET_CONFIGURATION 0x08
+
91 #define USB_REQ_SET_CONFIGURATION 0x09
+
92 #define USB_REQ_GET_INTERFACE 0x0A
+
93 #define USB_REQ_SET_INTERFACE 0x0B
+
94 #define USB_REQ_SYNCH_FRAME 0x0C
+
95 
+
96 /* Table 9-5. Descriptor Types of USB Specifications */
+
97 #define USB_DESC_TYPE_DEVICE 1
+
98 #define USB_DESC_TYPE_CONFIGURATION 2
+
99 #define USB_DESC_TYPE_STRING 3
+
100 #define USB_DESC_TYPE_INTERFACE 4
+
101 #define USB_DESC_TYPE_ENDPOINT 5
+
102 #define USB_DESC_TYPE_DEVICE_QUALIFIER 6
+
103 #define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
+
104 #define USB_DESC_TYPE_INTERFACE_POWER 8
+
105 #define USB_DESC_TYPE_HID 0x21
+
106 #define USB_DESC_TYPE_HID_REPORT 0x22
+
107 
+
108 
+
109 #define USB_DEVICE_DESC_SIZE 18
+
110 #define USB_CONFIGURATION_DESC_SIZE 9
+
111 #define USB_HID_DESC_SIZE 9
+
112 #define USB_INTERFACE_DESC_SIZE 9
+
113 #define USB_ENDPOINT_DESC_SIZE 7
+
114 
+
115 /* Descriptor Type and Descriptor Index */
+
116 /* Use the following values when calling the function USBH_GetDescriptor */
+
117 #define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00)
+
118 #define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00)
+
119 #define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00)
+
120 #define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
+
121 #define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
+
122 #define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00)
+
123 #define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00)
+
124 #define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00)
+
125 #define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00)
+
126 #define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00)
+
127 
+
128 
+
129 #define USB_EP_TYPE_CTRL 0x00
+
130 #define USB_EP_TYPE_ISOC 0x01
+
131 #define USB_EP_TYPE_BULK 0x02
+
132 #define USB_EP_TYPE_INTR 0x03
+
133 
+
134 #define USB_EP_DIR_OUT 0x00
+
135 #define USB_EP_DIR_IN 0x80
+
136 #define USB_EP_DIR_MSK 0x80
+
137 
+
138 /* supported classes */
+
139 #define USB_MSC_CLASS 0x08
+
140 #define USB_HID_CLASS 0x03
+
141 
+
142 /* Interface Descriptor field values for HID Boot Protocol */
+
143 #define HID_BOOT_CODE 0x01
+
144 #define HID_KEYBRD_BOOT_CODE 0x01
+
145 #define HID_MOUSE_BOOT_CODE 0x02
+
146 
+
147 /* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec
+
148  Standard request with no data stage timeout : 50ms */
+
149 #define DATA_STAGE_TIMEOUT 5000
+
150 #define NODATA_STAGE_TIMEOUT 50
+
151 
+
157 #define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \
+
158  + USB_INTERFACE_DESC_SIZE\
+
159  + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE))
+
160 
+
161 
+
162 #define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\
+
163  ConfigurationDescriptor.wTotalLength)
+
164 
+
165 
+
166 /* This Union is copied from usb_core.h */
+
167 typedef union
+
168 {
+
169  uint16_t w;
+
170  struct BW
+
171  {
+
172  uint8_t msb;
+
173  uint8_t lsb;
+
174  }
+
175  bw;
+
176 }
+
177 uint16_t_uint8_t;
+
178 
+
179 
+
180 typedef union _USB_Setup
+
181 {
+
182  uint8_t d8[8];
+
183 
+
184  struct _SetupPkt_Struc
+
185  {
+
186  uint8_t bmRequestType;
+
187  uint8_t bRequest;
+
188  uint16_t_uint8_t wValue;
+
189  uint16_t_uint8_t wIndex;
+
190  uint16_t_uint8_t wLength;
+
191  } b;
+
192 }
+
193 USB_Setup_TypeDef;
+
194 
+
195 typedef struct _DescHeader
+
196 {
+
197  uint8_t bLength;
+
198  uint8_t bDescriptorType;
+
199 }
+
200 USBH_DescHeader_t;
+
201 
+
202 typedef struct _DeviceDescriptor
+
203 {
+
204  uint8_t bLength;
+
205  uint8_t bDescriptorType;
+
206  uint16_t bcdUSB; /* USB Specification Number which device complies too */
+
207  uint8_t bDeviceClass;
+
208  uint8_t bDeviceSubClass;
+
209  uint8_t bDeviceProtocol;
+
210  /* If equal to Zero, each interface specifies its own class
+
211  code if equal to 0xFF, the class code is vendor specified.
+
212  Otherwise field is valid Class Code.*/
+
213  uint8_t bMaxPacketSize;
+
214  uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */
+
215  uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */
+
216  uint16_t bcdDevice; /* Device Release Number */
+
217  uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */
+
218  uint8_t iProduct; /* Index of Product String Descriptor */
+
219  uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */
+
220  uint8_t bNumConfigurations; /* Number of Possible Configurations */
+
221 }
+
222 USBH_DevDesc_TypeDef;
+
223 
+
224 
+
225 typedef struct _ConfigurationDescriptor
+
226 {
+
227  uint8_t bLength;
+
228  uint8_t bDescriptorType;
+
229  uint16_t wTotalLength; /* Total Length of Data Returned */
+
230  uint8_t bNumInterfaces; /* Number of Interfaces */
+
231  uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/
+
232  uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */
+
233  uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/
+
234  uint8_t bMaxPower; /*Maximum Power Consumption */
+
235 }
+
236 USBH_CfgDesc_TypeDef;
+
237 
+
238 
+
239 typedef struct _HIDDescriptor
+
240 {
+
241  uint8_t bLength;
+
242  uint8_t bDescriptorType;
+
243  uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */
+
244  uint8_t bCountryCode; /* specifies the transfer type. */
+
245  uint8_t bNumDescriptors; /* specifies the transfer type. */
+
246  uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */
+
247  uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */
+
248 }
+
249 USBH_HIDDesc_TypeDef;
+
250 
+
251 
+
252 typedef struct _InterfaceDescriptor
+
253 {
+
254  uint8_t bLength;
+
255  uint8_t bDescriptorType;
+
256  uint8_t bInterfaceNumber;
+
257  uint8_t bAlternateSetting; /* Value used to select alternative setting */
+
258  uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */
+
259  uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */
+
260  uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */
+
261  uint8_t bInterfaceProtocol; /* Protocol Code */
+
262  uint8_t iInterface; /* Index of String Descriptor Describing this interface */
+
263 
+
264 }
+
265 USBH_InterfaceDesc_TypeDef;
+
266 
+
267 
+
268 typedef struct _EndpointDescriptor
+
269 {
+
270  uint8_t bLength;
+
271  uint8_t bDescriptorType;
+
272  uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */
+
273  uint8_t bmAttributes; /* specifies the transfer type. */
+
274  uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */
+
275  uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */
+
276 }
+
277 USBH_EpDesc_TypeDef;
+
278 #endif
+
279 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
280 
+
_DescHeader
Definition: usbh_def.h:195
+
_EndpointDescriptor
Definition: usbh_def.h:268
+
_DeviceDescriptor
Definition: usbh_def.h:202
+
_USB_Setup::_SetupPkt_Struc
Definition: usbh_def.h:184
+
uint16_t_uint8_t::BW
Definition: usbh_def.h:170
+
_ConfigurationDescriptor
Definition: usbh_def.h:225
+
uint16_t_uint8_t
Definition: usbh_def.h:167
+
_USB_Setup
Definition: usbh_def.h:180
+
_HIDDescriptor
Definition: usbh_def.h:239
+
_InterfaceDescriptor
Definition: usbh_def.h:252
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hcs_8c.html b/usbh__hcs_8c.html new file mode 100644 index 0000000..e8cfd1f --- /dev/null +++ b/usbh__hcs_8c.html @@ -0,0 +1,141 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src/usbh_hcs.c File Reference + + + + + + + + + + +
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+Functions
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+
usbh_hcs.c File Reference
+
+
+ +

This file implements functions for opening and closing host channels. +More...

+
#include "usbh_hcs.h"
+
+Include dependency graph for usbh_hcs.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Open_Channel Open a pipe. More...
 
uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Modify_Channel Modify a pipe. More...
 
uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
 USBH_Alloc_Channel Allocate a new channel for the pipe. More...
 
uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
 USBH_Free_Pipe Free the USB host channel. More...
 
uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev)
 USBH_DeAllocate_AllChannel Free all USB host channel. More...
 
+

Detailed Description

+

This file implements functions for opening and closing host channels.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hcs_8c__incl.map b/usbh__hcs_8c__incl.map new file mode 100644 index 0000000..2fa1e35 --- /dev/null +++ b/usbh__hcs_8c__incl.map @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hcs_8c__incl.md5 b/usbh__hcs_8c__incl.md5 new file mode 100644 index 0000000..837195c --- /dev/null +++ b/usbh__hcs_8c__incl.md5 @@ -0,0 +1 @@ +2085e551c94a34a29ce4078af8048fe5 \ No newline at end of file diff --git a/usbh__hcs_8c__incl.png b/usbh__hcs_8c__incl.png new file mode 100644 index 0000000..cd75a37 Binary files /dev/null and b/usbh__hcs_8c__incl.png differ diff --git a/usbh__hcs_8h.html b/usbh__hcs_8h.html new file mode 100644 index 0000000..460b356 --- /dev/null +++ b/usbh__hcs_8h.html @@ -0,0 +1,169 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_hcs.h File Reference + + + + + + + + + + +
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usbh_hcs.h File Reference
+
+
+ +

Header file for usbh_hcs.c. +More...

+
#include "usbh_core.h"
+
+Include dependency graph for usbh_hcs.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + +

+Macros

+#define HC_MAX   8
 
+#define HC_OK   0x0000
 
+#define HC_USED   0x8000
 
+#define HC_ERROR   0xFFFF
 
+#define HC_USED_MASK   0x7FFF
 
+ + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
 USBH_Alloc_Channel Allocate a new channel for the pipe. More...
 
uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
 USBH_Free_Pipe Free the USB host channel. More...
 
uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev)
 USBH_DeAllocate_AllChannel Free all USB host channel. More...
 
uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Open_Channel Open a pipe. More...
 
uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 USBH_Modify_Channel Modify a pipe. More...
 
+

Detailed Description

+

Header file for usbh_hcs.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hcs_8h__dep__incl.map b/usbh__hcs_8h__dep__incl.map new file mode 100644 index 0000000..d2cb3c8 --- /dev/null +++ b/usbh__hcs_8h__dep__incl.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/usbh__hcs_8h__dep__incl.md5 b/usbh__hcs_8h__dep__incl.md5 new file mode 100644 index 0000000..aa0818c --- /dev/null +++ b/usbh__hcs_8h__dep__incl.md5 @@ -0,0 +1 @@ +8308620e2cc04a633e7849ba4c35d595 \ No newline at end of file diff --git a/usbh__hcs_8h__dep__incl.png b/usbh__hcs_8h__dep__incl.png new file mode 100644 index 0000000..0a00bd7 Binary files /dev/null and b/usbh__hcs_8h__dep__incl.png differ diff --git a/usbh__hcs_8h__incl.map b/usbh__hcs_8h__incl.map new file mode 100644 index 0000000..8e1905b --- /dev/null +++ b/usbh__hcs_8h__incl.map @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hcs_8h__incl.md5 b/usbh__hcs_8h__incl.md5 new file mode 100644 index 0000000..100d589 --- /dev/null +++ b/usbh__hcs_8h__incl.md5 @@ -0,0 +1 @@ +9f406f8154dc84269eeadc4ebe8d1277 \ No newline at end of file diff --git a/usbh__hcs_8h__incl.png b/usbh__hcs_8h__incl.png new file mode 100644 index 0000000..3ca7967 Binary files /dev/null and b/usbh__hcs_8h__incl.png differ diff --git a/usbh__hcs_8h_source.html b/usbh__hcs_8h_source.html new file mode 100644 index 0000000..433287e --- /dev/null +++ b/usbh__hcs_8h_source.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_hcs.h Source File + + + + + + + + + + +
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usbh_hcs.h
+
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+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_HCS_H
+
24 #define __USBH_HCS_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usbh_core.h"
+
28 
+
29 
+
30 
+
47 #define HC_MAX 8
+
48 
+
49 #define HC_OK 0x0000
+
50 #define HC_USED 0x8000
+
51 #define HC_ERROR 0xFFFF
+
52 #define HC_USED_MASK 0x7FFF
+
53 
+
83 uint8_t USBH_Alloc_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr);
+
84 
+
85 uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx);
+
86 
+
87 uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev);
+
88 
+
89 uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev,
+
90  uint8_t ch_num,
+
91  uint8_t dev_address,
+
92  uint8_t speed,
+
93  uint8_t ep_type,
+
94  uint16_t mps);
+
95 
+
96 uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev,
+
97  uint8_t hc_num,
+
98  uint8_t dev_address,
+
99  uint8_t speed,
+
100  uint8_t ep_type,
+
101  uint16_t mps);
+
108 #endif /* __USBH_HCS_H */
+
109 
+
110 
+
123 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
124 
+
125 
+
USBH_DeAllocate_AllChannel
uint8_t USBH_DeAllocate_AllChannel(USB_OTG_CORE_HANDLE *pdev)
USBH_DeAllocate_AllChannel Free all USB host channel.
Definition: usbh_hcs.c:203
+
usbh_core.h
Header file for usbh_core.c.
+
USBH_Modify_Channel
uint8_t USBH_Modify_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
USBH_Modify_Channel Modify a pipe.
Definition: usbh_hcs.c:134
+
USBH_Alloc_Channel
uint8_t USBH_Alloc_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr)
USBH_Alloc_Channel Allocate a new channel for the pipe.
Definition: usbh_hcs.c:168
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_Free_Channel
uint8_t USBH_Free_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t idx)
USBH_Free_Pipe Free the USB host channel.
Definition: usbh_hcs.c:187
+
USBH_Open_Channel
uint8_t USBH_Open_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
USBH_Open_Channel Open a pipe.
Definition: usbh_hcs.c:96
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__core_8c.html b/usbh__hid__core_8c.html new file mode 100644 index 0000000..5ee9a86 --- /dev/null +++ b/usbh__hid__core_8c.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_core.c File Reference + + + + + + + + + + +
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usbh_hid_core.c File Reference
+
+
+ +

This file is the HID Layer Handlers for USB Host HID class. +More...

+
#include "usbh_hid_core.h"
+#include "usbh_hid_mouse.h"
+#include "usbh_hid_keybd.h"
+
+Include dependency graph for usbh_hid_core.c:
+
+
+ + +
+
+ + + + +

+Functions

USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t *reportBuff)
 USBH_Set_Report Issues Set Report. More...
 
+ + + + + + + +

+Variables

+__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END
 
+__IO uint8_t flag = 0
 
USBH_Class_cb_TypeDef HID_cb
 
+

Detailed Description

+

This file is the HID Layer Handlers for USB Host HID class.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011 
*      
+*          ===================================================================      
+*                                HID Class  Description
+*          =================================================================== 
+*           This module manages the MSC class V1.11 following the "Device Class Definition
+*           for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
+*           This driver implements the following aspects of the specification:
+*             - The Boot Interface Subclass
+*             - The Mouse and Keyboard protocols
+*      
+*
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__core_8c__incl.map b/usbh__hid__core_8c__incl.map new file mode 100644 index 0000000..e1bee4f --- /dev/null +++ b/usbh__hid__core_8c__incl.map @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__core_8c__incl.md5 b/usbh__hid__core_8c__incl.md5 new file mode 100644 index 0000000..3fc93c7 --- /dev/null +++ b/usbh__hid__core_8c__incl.md5 @@ -0,0 +1 @@ +37ee6ed745915979472a9df5c10620c7 \ No newline at end of file diff --git a/usbh__hid__core_8c__incl.png b/usbh__hid__core_8c__incl.png new file mode 100644 index 0000000..f9227b3 Binary files /dev/null and b/usbh__hid__core_8c__incl.png differ diff --git a/usbh__hid__core_8h.html b/usbh__hid__core_8h.html new file mode 100644 index 0000000..ba43396 --- /dev/null +++ b/usbh__hid__core_8h.html @@ -0,0 +1,220 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h File Reference + + + + + + + + + + +
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usbh_hid_core.h File Reference
+
+
+ +

This file contains all the prototypes for the usbh_hid_core.c. +More...

+
#include "usbh_core.h"
+#include "usbh_stdreq.h"
+#include "usb_bsp.h"
+#include "usbh_ioreq.h"
+#include "usbh_hcs.h"
+
+Include dependency graph for usbh_hid_core.h:
+
+
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+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + +

+Classes

struct  HID_cb
 
struct  _HID_Report
 
struct  _HID_Process
 
+ + + + + + + + + + + + + +

+Macros

+#define USB_HID_REQ_GET_REPORT   0x01
 
+#define USB_HID_GET_IDLE   0x02
 
+#define USB_HID_GET_PROTOCOL   0x03
 
+#define USB_HID_SET_REPORT   0x09
 
+#define USB_HID_SET_IDLE   0x0A
 
+#define USB_HID_SET_PROTOCOL   0x0B
 
+ + + + + + + +

+Typedefs

+typedef struct HID_cb HID_cb_TypeDef
 
+typedef struct _HID_Report HID_Report_TypeDef
 
+typedef struct _HID_Process HID_Machine_TypeDef
 
+ + + + + +

+Enumerations

enum  HID_State {
+  HID_IDLE = 0, +HID_SEND_DATA, +HID_BUSY, +HID_GET_DATA, +
+  HID_POLL, +HID_ERROR +
+ }
 
enum  HID_CtlState {
+  HID_REQ_IDLE = 0, +HID_REQ_GET_REPORT_DESC, +HID_REQ_GET_HID_DESC, +HID_REQ_SET_IDLE, +
+  HID_REQ_SET_PROTOCOL, +HID_REQ_SET_REPORT +
+ }
 
+ + + + +

+Functions

USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t *reportBuff)
 USBH_Set_Report Issues Set Report. More...
 
+ + + +

+Variables

+USBH_Class_cb_TypeDef HID_cb
 
+

Detailed Description

+

This file contains all the prototypes for the usbh_hid_core.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__core_8h__dep__incl.map b/usbh__hid__core_8h__dep__incl.map new file mode 100644 index 0000000..5155298 --- /dev/null +++ b/usbh__hid__core_8h__dep__incl.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/usbh__hid__core_8h__dep__incl.md5 b/usbh__hid__core_8h__dep__incl.md5 new file mode 100644 index 0000000..3d6baf7 --- /dev/null +++ b/usbh__hid__core_8h__dep__incl.md5 @@ -0,0 +1 @@ +f11bed409b925ee38ecdb75d8d1f25f0 \ No newline at end of file diff --git a/usbh__hid__core_8h__dep__incl.png b/usbh__hid__core_8h__dep__incl.png new file mode 100644 index 0000000..9aa62a0 Binary files /dev/null and b/usbh__hid__core_8h__dep__incl.png differ diff --git a/usbh__hid__core_8h__incl.map b/usbh__hid__core_8h__incl.map new file mode 100644 index 0000000..d67605d --- /dev/null +++ b/usbh__hid__core_8h__incl.map @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__core_8h__incl.md5 b/usbh__hid__core_8h__incl.md5 new file mode 100644 index 0000000..181c6c6 --- /dev/null +++ b/usbh__hid__core_8h__incl.md5 @@ -0,0 +1 @@ +9957c9adff6982f95bea0938d7a86bb4 \ No newline at end of file diff --git a/usbh__hid__core_8h__incl.png b/usbh__hid__core_8h__incl.png new file mode 100644 index 0000000..e4fe997 Binary files /dev/null and b/usbh__hid__core_8h__incl.png differ diff --git a/usbh__hid__core_8h_source.html b/usbh__hid__core_8h_source.html new file mode 100644 index 0000000..ddbfb5c --- /dev/null +++ b/usbh__hid__core_8h_source.html @@ -0,0 +1,217 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h Source File + + + + + + + + + + +
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usbh_hid_core.h
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1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_HID_CORE_H
+
24 #define __USBH_HID_CORE_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usbh_core.h"
+
28 #include "usbh_stdreq.h"
+
29 #include "usb_bsp.h"
+
30 #include "usbh_ioreq.h"
+
31 #include "usbh_hcs.h"
+
32 
+
56 /* States for HID State Machine */
+
57 typedef enum
+
58 {
+
59  HID_IDLE= 0,
+
60  HID_SEND_DATA,
+
61  HID_BUSY,
+
62  HID_GET_DATA,
+
63  HID_POLL,
+
64  HID_ERROR,
+
65 }
+
66 HID_State;
+
67 
+
68 typedef enum
+
69 {
+
70  HID_REQ_IDLE = 0,
+
71  HID_REQ_GET_REPORT_DESC,
+
72  HID_REQ_GET_HID_DESC,
+
73  HID_REQ_SET_IDLE,
+
74  HID_REQ_SET_PROTOCOL,
+
75  HID_REQ_SET_REPORT,
+
76 
+
77 }
+
78 HID_CtlState;
+
79 
+
80 typedef struct HID_cb
+
81 {
+
82  void (*Init) (void);
+
83  void (*Decode) (uint8_t *data);
+
84 
+
85 } HID_cb_TypeDef;
+
86 
+
87 typedef struct _HID_Report
+
88 {
+
89  uint8_t ReportID;
+
90  uint8_t ReportType;
+
91  uint16_t UsagePage;
+
92  uint32_t Usage[2];
+
93  uint32_t NbrUsage;
+
94  uint32_t UsageMin;
+
95  uint32_t UsageMax;
+
96  int32_t LogMin;
+
97  int32_t LogMax;
+
98  int32_t PhyMin;
+
99  int32_t PhyMax;
+
100  int32_t UnitExp;
+
101  uint32_t Unit;
+
102  uint32_t ReportSize;
+
103  uint32_t ReportCnt;
+
104  uint32_t Flag;
+
105  uint32_t PhyUsage;
+
106  uint32_t AppUsage;
+
107  uint32_t LogUsage;
+
108 }
+
109 HID_Report_TypeDef;
+
110 
+
111 /* Structure for HID process */
+
112 typedef struct _HID_Process
+
113 {
+
114  uint8_t buff[64];
+
115  uint8_t hc_num_in;
+
116  uint8_t hc_num_out;
+
117  HID_State state;
+
118  uint8_t HIDIntOutEp;
+
119  uint8_t HIDIntInEp;
+
120  HID_CtlState ctl_state;
+
121  uint16_t length;
+
122  uint8_t ep_addr;
+
123  uint16_t poll;
+
124  __IO uint16_t timer;
+
125  HID_cb_TypeDef *cb;
+
126 }
+
127 HID_Machine_TypeDef;
+
128 
+
137 #define USB_HID_REQ_GET_REPORT 0x01
+
138 #define USB_HID_GET_IDLE 0x02
+
139 #define USB_HID_GET_PROTOCOL 0x03
+
140 #define USB_HID_SET_REPORT 0x09
+
141 #define USB_HID_SET_IDLE 0x0A
+
142 #define USB_HID_SET_PROTOCOL 0x0B
+
143 
+
157 extern USBH_Class_cb_TypeDef HID_cb;
+
166 USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev,
+
167  USBH_HOST *phost,
+
168  uint8_t reportType,
+
169  uint8_t reportId,
+
170  uint8_t reportLen,
+
171  uint8_t* reportBuff);
+
177 #endif /* __USBH_HID_CORE_H */
+
178 
+
194 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
195 
+
usb_bsp.h
Specific api's relative to the used hardware platform.
+
usbh_core.h
Header file for usbh_core.c.
+
USBH_Set_Report
USBH_Status USBH_Set_Report(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t reportType, uint8_t reportId, uint8_t reportLen, uint8_t *reportBuff)
USBH_Set_Report Issues Set Report.
Definition: usbh_hid_core.c:541
+
usbh_stdreq.h
Header file for usbh_stdreq.c.
+
_HID_Process
Definition: usbh_hid_core.h:112
+
HID_cb
Definition: usbh_hid_core.h:80
+
__IO
#define __IO
Definition: core_cm4.h:222
+
usbh_ioreq.h
Header file for usbh_ioreq.c.
+
USB_OTG_handle
Definition: usb_core.h:287
+
_HID_Report
Definition: usbh_hid_core.h:87
+
usbh_hcs.h
Header file for usbh_hcs.c.
+
_Host_TypeDef
Definition: usbh_core.h:215
+
_USBH_Class_cb
Definition: usbh_core.h:174
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__keybd_8c.html b/usbh__hid__keybd_8c.html new file mode 100644 index 0000000..fb9696d --- /dev/null +++ b/usbh__hid__keybd_8c.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_keybd.c File Reference + + + + + + + + + + +
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usbh_hid_keybd.c File Reference
+
+
+ +

This file is the application layer for USB Host HID Keyboard handling QWERTY and AZERTY Keyboard are supported as per the selection in usbh_hid_keybd.h. +More...

+
#include "usbh_hid_keybd.h"
+
+Include dependency graph for usbh_hid_keybd.c:
+
+
+ + +
+
+ + + +

+Variables

HID_cb_TypeDef HID_KEYBRD_cb
 
+

Detailed Description

+

This file is the application layer for USB Host HID Keyboard handling QWERTY and AZERTY Keyboard are supported as per the selection in usbh_hid_keybd.h.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__keybd_8c__incl.map b/usbh__hid__keybd_8c__incl.map new file mode 100644 index 0000000..45964a4 --- /dev/null +++ b/usbh__hid__keybd_8c__incl.map @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__keybd_8c__incl.md5 b/usbh__hid__keybd_8c__incl.md5 new file mode 100644 index 0000000..2519b84 --- /dev/null +++ b/usbh__hid__keybd_8c__incl.md5 @@ -0,0 +1 @@ +21cf740f61b34a07dbfecb9c563d9149 \ No newline at end of file diff --git a/usbh__hid__keybd_8c__incl.png b/usbh__hid__keybd_8c__incl.png new file mode 100644 index 0000000..0aeb620 Binary files /dev/null and b/usbh__hid__keybd_8c__incl.png differ diff --git a/usbh__hid__keybd_8h.html b/usbh__hid__keybd_8h.html new file mode 100644 index 0000000..ce5da07 --- /dev/null +++ b/usbh__hid__keybd_8h.html @@ -0,0 +1,183 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_keybd.h File Reference + + + + + + + + + + +
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+Macros | +Functions | +Variables
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+
usbh_hid_keybd.h File Reference
+
+
+ +

This file contains all the prototypes for the usbh_hid_keybd.c. +More...

+
#include "usb_conf.h"
+#include "usbh_hid_core.h"
+
+Include dependency graph for usbh_hid_keybd.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define AZERTY_KEYBOARD
 
+#define KBD_LEFT_CTRL   0x01
 
+#define KBD_LEFT_SHIFT   0x02
 
+#define KBD_LEFT_ALT   0x04
 
+#define KBD_LEFT_GUI   0x08
 
+#define KBD_RIGHT_CTRL   0x10
 
+#define KBD_RIGHT_SHIFT   0x20
 
+#define KBD_RIGHT_ALT   0x40
 
+#define KBD_RIGHT_GUI   0x80
 
+#define KBR_MAX_NBR_PRESSED   6
 
+ + + + + +

+Functions

+void USR_KEYBRD_Init (void)
 
+void USR_KEYBRD_ProcessData (uint8_t pbuf)
 
+ + + +

+Variables

+HID_cb_TypeDef HID_KEYBRD_cb
 
+

Detailed Description

+

This file contains all the prototypes for the usbh_hid_keybd.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__keybd_8h__dep__incl.map b/usbh__hid__keybd_8h__dep__incl.map new file mode 100644 index 0000000..0e5dc34 --- /dev/null +++ b/usbh__hid__keybd_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/usbh__hid__keybd_8h__dep__incl.md5 b/usbh__hid__keybd_8h__dep__incl.md5 new file mode 100644 index 0000000..069e5a6 --- /dev/null +++ b/usbh__hid__keybd_8h__dep__incl.md5 @@ -0,0 +1 @@ +b2dd8a6d3da5ac29f9b3ab5c3e900d2d \ No newline at end of file diff --git a/usbh__hid__keybd_8h__dep__incl.png b/usbh__hid__keybd_8h__dep__incl.png new file mode 100644 index 0000000..91a39da Binary files /dev/null and b/usbh__hid__keybd_8h__dep__incl.png differ diff --git a/usbh__hid__keybd_8h__incl.map b/usbh__hid__keybd_8h__incl.map new file mode 100644 index 0000000..f581571 --- /dev/null +++ b/usbh__hid__keybd_8h__incl.map @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__keybd_8h__incl.md5 b/usbh__hid__keybd_8h__incl.md5 new file mode 100644 index 0000000..2d95410 --- /dev/null +++ b/usbh__hid__keybd_8h__incl.md5 @@ -0,0 +1 @@ +25019dc3e35864ed5a7afac896750688 \ No newline at end of file diff --git a/usbh__hid__keybd_8h__incl.png b/usbh__hid__keybd_8h__incl.png new file mode 100644 index 0000000..e396c1b Binary files /dev/null and b/usbh__hid__keybd_8h__incl.png differ diff --git a/usbh__hid__keybd_8h_source.html b/usbh__hid__keybd_8h_source.html new file mode 100644 index 0000000..ea0813d --- /dev/null +++ b/usbh__hid__keybd_8h_source.html @@ -0,0 +1,133 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_keybd.h Source File + + + + + + + + + + +
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usbh_hid_keybd.h
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1 
+
22 /* Define to prevent recursive -----------------------------------------------*/
+
23 #ifndef __USBH_HID_KEYBD_H
+
24 #define __USBH_HID_KEYBD_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_conf.h"
+
28 #include "usbh_hid_core.h"
+
29 
+
60 //#define QWERTY_KEYBOARD
+
61 #define AZERTY_KEYBOARD
+
62 
+
63 #define KBD_LEFT_CTRL 0x01
+
64 #define KBD_LEFT_SHIFT 0x02
+
65 #define KBD_LEFT_ALT 0x04
+
66 #define KBD_LEFT_GUI 0x08
+
67 #define KBD_RIGHT_CTRL 0x10
+
68 #define KBD_RIGHT_SHIFT 0x20
+
69 #define KBD_RIGHT_ALT 0x40
+
70 #define KBD_RIGHT_GUI 0x80
+
71 
+
72 #define KBR_MAX_NBR_PRESSED 6
+
73 
+
89 extern HID_cb_TypeDef HID_KEYBRD_cb;
+
97 void USR_KEYBRD_Init (void);
+
98 void USR_KEYBRD_ProcessData (uint8_t pbuf);
+
103 #endif /* __USBH_HID_KEYBD_H */
+
104 
+
121 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
122 
+
HID_cb
Definition: usbh_hid_core.h:80
+
usbh_hid_core.h
This file contains all the prototypes for the usbh_hid_core.c.
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__mouse_8c.html b/usbh__hid__mouse_8c.html new file mode 100644 index 0000000..bcbd695 --- /dev/null +++ b/usbh__hid__mouse_8c.html @@ -0,0 +1,131 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_mouse.c File Reference + + + + + + + + + + +
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usbh_hid_mouse.c File Reference
+
+
+ +

This file is the application layer for USB Host HID Mouse Handling. +More...

+
#include "usbh_hid_mouse.h"
+
+Include dependency graph for usbh_hid_mouse.c:
+
+
+ + +
+
+ + + + + +

+Variables

+HID_MOUSE_Data_TypeDef HID_MOUSE_Data
 
HID_cb_TypeDef HID_MOUSE_cb
 
+

Detailed Description

+

This file is the application layer for USB Host HID Mouse Handling.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__mouse_8c__incl.map b/usbh__hid__mouse_8c__incl.map new file mode 100644 index 0000000..ffb595e --- /dev/null +++ b/usbh__hid__mouse_8c__incl.map @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__mouse_8c__incl.md5 b/usbh__hid__mouse_8c__incl.md5 new file mode 100644 index 0000000..ac9ac91 --- /dev/null +++ b/usbh__hid__mouse_8c__incl.md5 @@ -0,0 +1 @@ +1ae8a5583abd08249bb10eec4ed4ddec \ No newline at end of file diff --git a/usbh__hid__mouse_8c__incl.png b/usbh__hid__mouse_8c__incl.png new file mode 100644 index 0000000..86f9525 Binary files /dev/null and b/usbh__hid__mouse_8c__incl.png differ diff --git a/usbh__hid__mouse_8h.html b/usbh__hid__mouse_8h.html new file mode 100644 index 0000000..837811e --- /dev/null +++ b/usbh__hid__mouse_8h.html @@ -0,0 +1,164 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h File Reference + + + + + + + + + + +
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usbh_hid_mouse.h File Reference
+
+
+ +

This file contains all the prototypes for the usbh_hid_mouse.c. +More...

+
#include "usbh_hid_core.h"
+
+Include dependency graph for usbh_hid_mouse.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + +

+Classes

struct  _HID_MOUSE_Data
 
+ + + +

+Typedefs

+typedef struct _HID_MOUSE_Data HID_MOUSE_Data_TypeDef
 
+ + + + + +

+Functions

+void USR_MOUSE_Init (void)
 
+void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data)
 
+ + + + + +

+Variables

+HID_cb_TypeDef HID_MOUSE_cb
 
+HID_MOUSE_Data_TypeDef HID_MOUSE_Data
 
+

Detailed Description

+

This file contains all the prototypes for the usbh_hid_mouse.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__hid__mouse_8h__dep__incl.map b/usbh__hid__mouse_8h__dep__incl.map new file mode 100644 index 0000000..97ae0ce --- /dev/null +++ b/usbh__hid__mouse_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/usbh__hid__mouse_8h__dep__incl.md5 b/usbh__hid__mouse_8h__dep__incl.md5 new file mode 100644 index 0000000..a01954b --- /dev/null +++ b/usbh__hid__mouse_8h__dep__incl.md5 @@ -0,0 +1 @@ +1889fbeca547c49e38752fdda01a669c \ No newline at end of file diff --git a/usbh__hid__mouse_8h__dep__incl.png b/usbh__hid__mouse_8h__dep__incl.png new file mode 100644 index 0000000..f636f21 Binary files /dev/null and b/usbh__hid__mouse_8h__dep__incl.png differ diff --git a/usbh__hid__mouse_8h__incl.map b/usbh__hid__mouse_8h__incl.map new file mode 100644 index 0000000..72ec16d --- /dev/null +++ b/usbh__hid__mouse_8h__incl.map @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__hid__mouse_8h__incl.md5 b/usbh__hid__mouse_8h__incl.md5 new file mode 100644 index 0000000..bc10908 --- /dev/null +++ b/usbh__hid__mouse_8h__incl.md5 @@ -0,0 +1 @@ +1d0351a434553b8e7d7fe8f001efb32f \ No newline at end of file diff --git a/usbh__hid__mouse_8h__incl.png b/usbh__hid__mouse_8h__incl.png new file mode 100644 index 0000000..5fd588a Binary files /dev/null and b/usbh__hid__mouse_8h__incl.png differ diff --git a/usbh__hid__mouse_8h_source.html b/usbh__hid__mouse_8h_source.html new file mode 100644 index 0000000..d2eaded --- /dev/null +++ b/usbh__hid__mouse_8h_source.html @@ -0,0 +1,128 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h Source File + + + + + + + + + + +
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usbh_hid_mouse.h
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1 
+
23 /* Define to prevent recursive ----------------------------------------------*/
+
24 #ifndef __USBH_HID_MOUSE_H
+
25 #define __USBH_HID_MOUSE_H
+
26 
+
27 /* Includes ------------------------------------------------------------------*/
+
28 #include "usbh_hid_core.h"
+
29 
+
51 typedef struct _HID_MOUSE_Data
+
52 {
+
53  uint8_t x;
+
54  uint8_t y;
+
55  uint8_t z; /* Not Supported */
+
56  uint8_t button;
+
57 }
+
58 HID_MOUSE_Data_TypeDef;
+
59 
+
82 extern HID_cb_TypeDef HID_MOUSE_cb;
+
83 extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data;
+
91 void USR_MOUSE_Init (void);
+
92 void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data);
+
97 #endif /* __USBH_HID_MOUSE_H */
+
98 
+
114 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
HID_cb
Definition: usbh_hid_core.h:80
+
usbh_hid_core.h
This file contains all the prototypes for the usbh_hid_core.c.
+
_HID_MOUSE_Data
Definition: usbh_hid_mouse.h:51
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__ioreq_8c.html b/usbh__ioreq_8c.html new file mode 100644 index 0000000..1aefb4a --- /dev/null +++ b/usbh__ioreq_8c.html @@ -0,0 +1,150 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src/usbh_ioreq.c File Reference + + + + + + + + + + +
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+
usbh_ioreq.c File Reference
+
+
+ +

This file handles the issuing of the USB transactions. +More...

+
#include "usbh_ioreq.h"
+
+Include dependency graph for usbh_ioreq.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length)
 USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request. More...
 
USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t hc_num)
 USBH_CtlSendSetup Sends the Setup Packet to the Device. More...
 
USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlSendData Sends a data Packet to the Device. More...
 
USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlReceiveData Receives the Device Response to the Setup Packet. More...
 
USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkSendData Sends the Bulk Packet to the device. More...
 
USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkReceiveData Receives IN bulk packet from device. More...
 
USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token. More...
 
USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint. More...
 
+

Detailed Description

+

This file handles the issuing of the USB transactions.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__ioreq_8c__incl.map b/usbh__ioreq_8c__incl.map new file mode 100644 index 0000000..8588d0d --- /dev/null +++ b/usbh__ioreq_8c__incl.map @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__ioreq_8c__incl.md5 b/usbh__ioreq_8c__incl.md5 new file mode 100644 index 0000000..59667e9 --- /dev/null +++ b/usbh__ioreq_8c__incl.md5 @@ -0,0 +1 @@ +c40bcc7bb2b5731c2ab74121e78fe903 \ No newline at end of file diff --git a/usbh__ioreq_8c__incl.png b/usbh__ioreq_8c__incl.png new file mode 100644 index 0000000..9a95a6f Binary files /dev/null and b/usbh__ioreq_8c__incl.png differ diff --git a/usbh__ioreq_8h.html b/usbh__ioreq_8h.html new file mode 100644 index 0000000..66790bf --- /dev/null +++ b/usbh__ioreq_8h.html @@ -0,0 +1,174 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_ioreq.h File Reference + + + + + + + + + + +
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+Macros | +Functions
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+
usbh_ioreq.h File Reference
+
+
+ +

Header file for usbh_ioreq.c. +More...

+
#include "usb_conf.h"
+#include "usbh_core.h"
+#include "usbh_def.h"
+
+Include dependency graph for usbh_ioreq.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + +

+Macros

+#define USBH_SETUP_PKT_SIZE   8
 
+#define USBH_EP0_EP_NUM   0
 
+#define USBH_MAX_PACKET_SIZE   0x40
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

USBH_Status USBH_CtlSendSetup (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t hc_num)
 USBH_CtlSendSetup Sends the Setup Packet to the Device. More...
 
USBH_Status USBH_CtlSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlSendData Sends a data Packet to the Device. More...
 
USBH_Status USBH_CtlReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_CtlReceiveData Receives the Device Response to the Setup Packet. More...
 
USBH_Status USBH_BulkReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkReceiveData Receives IN bulk packet from device. More...
 
USBH_Status USBH_BulkSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
 USBH_BulkSendData Sends the Bulk Packet to the device. More...
 
USBH_Status USBH_InterruptReceiveData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token. More...
 
USBH_Status USBH_InterruptSendData (USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
 USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint. More...
 
USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length)
 USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the request. More...
 
+

Detailed Description

+

Header file for usbh_ioreq.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__ioreq_8h__dep__incl.map b/usbh__ioreq_8h__dep__incl.map new file mode 100644 index 0000000..b0cd0f4 --- /dev/null +++ b/usbh__ioreq_8h__dep__incl.map @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/usbh__ioreq_8h__dep__incl.md5 b/usbh__ioreq_8h__dep__incl.md5 new file mode 100644 index 0000000..c100529 --- /dev/null +++ b/usbh__ioreq_8h__dep__incl.md5 @@ -0,0 +1 @@ +c81d5b8c53d83db989be70631aabf428 \ No newline at end of file diff --git a/usbh__ioreq_8h__dep__incl.png b/usbh__ioreq_8h__dep__incl.png new file mode 100644 index 0000000..0127a6a Binary files /dev/null and b/usbh__ioreq_8h__dep__incl.png differ diff --git a/usbh__ioreq_8h__incl.map b/usbh__ioreq_8h__incl.map new file mode 100644 index 0000000..08d2b8f --- /dev/null +++ b/usbh__ioreq_8h__incl.map @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__ioreq_8h__incl.md5 b/usbh__ioreq_8h__incl.md5 new file mode 100644 index 0000000..f3267ff --- /dev/null +++ b/usbh__ioreq_8h__incl.md5 @@ -0,0 +1 @@ +c8201b7ce7a4a3f1ed15aba5726ae65e \ No newline at end of file diff --git a/usbh__ioreq_8h__incl.png b/usbh__ioreq_8h__incl.png new file mode 100644 index 0000000..3f05025 Binary files /dev/null and b/usbh__ioreq_8h__incl.png differ diff --git a/usbh__ioreq_8h_source.html b/usbh__ioreq_8h_source.html new file mode 100644 index 0000000..7743d51 --- /dev/null +++ b/usbh__ioreq_8h_source.html @@ -0,0 +1,171 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_ioreq.h Source File + + + + + + + + + + +
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usbh_ioreq.h
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1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_IOREQ_H
+
24 #define __USBH_IOREQ_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usb_conf.h"
+
28 #include "usbh_core.h"
+
29 #include "usbh_def.h"
+
30 
+
31 
+
49 #define USBH_SETUP_PKT_SIZE 8
+
50 #define USBH_EP0_EP_NUM 0
+
51 #define USBH_MAX_PACKET_SIZE 0x40
+
52 
+
82 USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev,
+
83  uint8_t *buff,
+
84  uint8_t hc_num);
+
85 
+
86 USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev,
+
87  uint8_t *buff,
+
88  uint8_t length,
+
89  uint8_t hc_num);
+
90 
+
91 USBH_Status USBH_CtlReceiveData( USB_OTG_CORE_HANDLE *pdev,
+
92  uint8_t *buff,
+
93  uint8_t length,
+
94  uint8_t hc_num);
+
95 
+
96 USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev,
+
97  uint8_t *buff,
+
98  uint16_t length,
+
99  uint8_t hc_num);
+
100 
+
101 USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev,
+
102  uint8_t *buff,
+
103  uint16_t length,
+
104  uint8_t hc_num);
+
105 
+
106 USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev,
+
107  uint8_t *buff,
+
108  uint8_t length,
+
109  uint8_t hc_num);
+
110 
+
111 USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev,
+
112  uint8_t *buff,
+
113  uint8_t length,
+
114  uint8_t hc_num);
+
115 
+
116 USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev,
+
117  USBH_HOST *phost,
+
118  uint8_t *buff,
+
119  uint16_t length);
+
124 #endif /* __USBH_IOREQ_H */
+
125 
+
138 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
139 
+
140 
+
USBH_BulkReceiveData
USBH_Status USBH_BulkReceiveData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
USBH_BulkReceiveData Receives IN bulk packet from device.
Definition: usbh_ioreq.c:275
+
usbh_core.h
Header file for usbh_core.c.
+
USBH_InterruptReceiveData
USBH_Status USBH_InterruptReceiveData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
USBH_InterruptReceiveData Receives the Device Response to the Interrupt IN token. ...
Definition: usbh_ioreq.c:308
+
USBH_BulkSendData
USBH_Status USBH_BulkSendData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
USBH_BulkSendData Sends the Bulk Packet to the device.
Definition: usbh_ioreq.c:242
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_CtlSendData
USBH_Status USBH_CtlSendData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
USBH_CtlSendData Sends a data Packet to the Device.
Definition: usbh_ioreq.c:176
+
USBH_CtlReceiveData
USBH_Status USBH_CtlReceiveData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
USBH_CtlReceiveData Receives the Device Response to the Setup Packet.
Definition: usbh_ioreq.c:215
+
USBH_CtlReq
USBH_Status USBH_CtlReq(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length)
USBH_CtlReq USBH_CtlReq sends a control request and provide the status after completion of the reques...
Definition: usbh_ioreq.c:99
+
USBH_CtlSendSetup
USBH_Status USBH_CtlSendSetup(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t hc_num)
USBH_CtlSendSetup Sends the Setup Packet to the Device.
Definition: usbh_ioreq.c:155
+
_Host_TypeDef
Definition: usbh_core.h:215
+
USBH_InterruptSendData
USBH_Status USBH_InterruptSendData(USB_OTG_CORE_HANDLE *pdev, uint8_t *buff, uint8_t length, uint8_t hc_num)
USBH_InterruptSendData Sends the data on Interrupt OUT Endpoint.
Definition: usbh_ioreq.c:346
+
usbh_def.h
Definitions used in the USB host library.
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__bot_8c.html b/usbh__msc__bot_8c.html new file mode 100644 index 0000000..cd14f4f --- /dev/null +++ b/usbh__msc__bot_8c.html @@ -0,0 +1,153 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_bot.c File Reference + + + + + + + + + + +
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usbh_msc_bot.c File Reference
+
+
+ +

This file includes the mass storage related functions. +More...

+
#include "usbh_msc_core.h"
+#include "usbh_msc_scsi.h"
+#include "usbh_msc_bot.h"
+#include "usbh_ioreq.h"
+#include "usbh_def.h"
+#include "usb_hcd_int.h"
+
+Include dependency graph for usbh_msc_bot.c:
+
+
+ + +
+
+ + + + + + + + + + + + + +

+Functions

void USBH_MSC_Init (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_Init Initializes the mass storage parameters. More...
 
void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer. More...
 
USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t direction)
 USBH_MSC_BOT_Abort This function manages the different Error handling for STALL. More...
 
uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer. More...
 
+ + + + + +

+Variables

+__ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData __ALIGN_END
 
+USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam
 
+

Detailed Description

+

This file includes the mass storage related functions.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__bot_8c__incl.map b/usbh__msc__bot_8c__incl.map new file mode 100644 index 0000000..0e95f38 --- /dev/null +++ b/usbh__msc__bot_8c__incl.map @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__msc__bot_8c__incl.md5 b/usbh__msc__bot_8c__incl.md5 new file mode 100644 index 0000000..6428438 --- /dev/null +++ b/usbh__msc__bot_8c__incl.md5 @@ -0,0 +1 @@ +6259d4577f910f5dfdaebf7f6666df71 \ No newline at end of file diff --git a/usbh__msc__bot_8c__incl.png b/usbh__msc__bot_8c__incl.png new file mode 100644 index 0000000..d080a60 Binary files /dev/null and b/usbh__msc__bot_8c__incl.png differ diff --git a/usbh__msc__bot_8h.html b/usbh__msc__bot_8h.html new file mode 100644 index 0000000..6c78b67 --- /dev/null +++ b/usbh__msc__bot_8h.html @@ -0,0 +1,301 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h File Reference + + + + + + + + + + +
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usbh_msc_bot.h File Reference
+
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Header file for usbh_msc_bot.c. +More...

+
#include "usbh_stdreq.h"
+
+Include dependency graph for usbh_msc_bot.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
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Go to the source code of this file.

+ + + + + + + + + + + + +

+Classes

union  _USBH_CBW_Block
 
struct  _USBH_CBW_Block::__CBW
 
struct  _BOTXfer
 
union  _USBH_CSW_Block
 
struct  _USBH_CSW_Block::__CSW
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define USBH_MSC_SEND_CBW   1
 
+#define USBH_MSC_SENT_CBW   2
 
+#define USBH_MSC_BOT_DATAIN_STATE   3
 
+#define USBH_MSC_BOT_DATAOUT_STATE   4
 
+#define USBH_MSC_RECEIVE_CSW_STATE   5
 
+#define USBH_MSC_DECODE_CSW   6
 
+#define USBH_MSC_BOT_ERROR_IN   7
 
+#define USBH_MSC_BOT_ERROR_OUT   8
 
+#define USBH_MSC_BOT_CBW_SIGNATURE   0x43425355
 
+#define USBH_MSC_BOT_CBW_TAG   0x20304050
 
+#define USBH_MSC_BOT_CSW_SIGNATURE   0x53425355
 
+#define USBH_MSC_CSW_DATA_LENGTH   0x000D
 
+#define USBH_MSC_BOT_CBW_PACKET_LENGTH   31
 
+#define USBH_MSC_CSW_LENGTH   13
 
+#define USBH_MSC_CSW_MAX_LENGTH   63
 
+#define USBH_MSC_CSW_CMD_PASSED   0x00
 
+#define USBH_MSC_CSW_CMD_FAILED   0x01
 
+#define USBH_MSC_CSW_PHASE_ERROR   0x02
 
+#define USBH_MSC_SEND_CSW_DISABLE   0
 
+#define USBH_MSC_SEND_CSW_ENABLE   1
 
+#define USBH_MSC_DIR_IN   0
 
+#define USBH_MSC_DIR_OUT   1
 
+#define USBH_MSC_BOTH_DIR   2
 
+#define USBH_MSC_PAGE_LENGTH   512
 
+#define CBW_CB_LENGTH   16
 
+#define CBW_LENGTH   10
 
+#define CBW_LENGTH_TEST_UNIT_READY   6
 
+#define USB_REQ_BOT_RESET   0xFF
 
+#define USB_REQ_GET_MAX_LUN   0xFE
 
#define MAX_BULK_STALL_COUNT_LIMIT
 
+ + + + + + + +

+Typedefs

+typedef union _USBH_CBW_Block HostCBWPkt_TypeDef
 
+typedef struct _BOTXfer USBH_BOTXfer_TypeDef
 
+typedef union _USBH_CSW_Block HostCSWPkt_TypeDef
 
+ + + +

+Enumerations

enum  MSCState {
+  USBH_MSC_BOT_INIT_STATE = 0, +USBH_MSC_BOT_RESET, +USBH_MSC_GET_MAX_LUN, +USBH_MSC_TEST_UNIT_READY, +
+  USBH_MSC_READ_CAPACITY10, +USBH_MSC_MODE_SENSE6, +USBH_MSC_REQUEST_SENSE, +USBH_MSC_BOT_USB_TRANSFERS, +
+  USBH_MSC_DEFAULT_APPLI_STATE, +USBH_MSC_CTRL_ERROR_STATE, +USBH_MSC_UNRECOVERED_STATE +
+ }
 
+ + + + + + + + + + + + + +

+Functions

void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the status to upper layer. More...
 
uint8_t USBH_MSC_DecodeCSW (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
 USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper layer. More...
 
void USBH_MSC_Init (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_Init Initializes the mass storage parameters. More...
 
USBH_Status USBH_MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t direction)
 USBH_MSC_BOT_Abort This function manages the different Error handling for STALL. More...
 
+ + + + + + + +

+Variables

+USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam
 
+HostCBWPkt_TypeDef USBH_MSC_CBWData
 
+HostCSWPkt_TypeDef USBH_MSC_CSWData
 
+

Detailed Description

+

Header file for usbh_msc_bot.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__bot_8h__dep__incl.map b/usbh__msc__bot_8h__dep__incl.map new file mode 100644 index 0000000..b85973d --- /dev/null +++ b/usbh__msc__bot_8h__dep__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/usbh__msc__bot_8h__dep__incl.md5 b/usbh__msc__bot_8h__dep__incl.md5 new file mode 100644 index 0000000..1876bd0 --- /dev/null +++ b/usbh__msc__bot_8h__dep__incl.md5 @@ -0,0 +1 @@ +3cb917714f2561bbd7b8b1f6a0cc7cbe \ No newline at end of file diff --git a/usbh__msc__bot_8h__dep__incl.png b/usbh__msc__bot_8h__dep__incl.png new file mode 100644 index 0000000..5a0aa0b Binary files /dev/null and b/usbh__msc__bot_8h__dep__incl.png differ diff --git a/usbh__msc__bot_8h__incl.map b/usbh__msc__bot_8h__incl.map new file mode 100644 index 0000000..798a641 --- /dev/null +++ b/usbh__msc__bot_8h__incl.map @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__msc__bot_8h__incl.md5 b/usbh__msc__bot_8h__incl.md5 new file mode 100644 index 0000000..d3673cb --- /dev/null +++ b/usbh__msc__bot_8h__incl.md5 @@ -0,0 +1 @@ +6eefffe15e0b9cf5bcddbfd1f3e992f3 \ No newline at end of file diff --git a/usbh__msc__bot_8h__incl.png b/usbh__msc__bot_8h__incl.png new file mode 100644 index 0000000..814efb4 Binary files /dev/null and b/usbh__msc__bot_8h__incl.png differ diff --git a/usbh__msc__bot_8h_source.html b/usbh__msc__bot_8h_source.html new file mode 100644 index 0000000..04cd8b5 --- /dev/null +++ b/usbh__msc__bot_8h_source.html @@ -0,0 +1,243 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h Source File + + + + + + + + + + +
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usbh_msc_bot.h
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1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_MSC_BOT_H__
+
24 #define __USBH_MSC_BOT_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usbh_stdreq.h"
+
28 
+
29 
+
52 typedef union _USBH_CBW_Block
+
53 {
+
54  struct __CBW
+
55  {
+
56  uint32_t CBWSignature;
+
57  uint32_t CBWTag;
+
58  uint32_t CBWTransferLength;
+
59  uint8_t CBWFlags;
+
60  uint8_t CBWLUN;
+
61  uint8_t CBWLength;
+
62  uint8_t CBWCB[16];
+
63 }field;
+
64  uint8_t CBWArray[31];
+
65 }HostCBWPkt_TypeDef;
+
66 
+
67 typedef enum
+
68 {
+
69  USBH_MSC_BOT_INIT_STATE = 0,
+
70  USBH_MSC_BOT_RESET,
+
71  USBH_MSC_GET_MAX_LUN,
+
72  USBH_MSC_TEST_UNIT_READY,
+
73  USBH_MSC_READ_CAPACITY10,
+
74  USBH_MSC_MODE_SENSE6,
+
75  USBH_MSC_REQUEST_SENSE,
+
76  USBH_MSC_BOT_USB_TRANSFERS,
+
77  USBH_MSC_DEFAULT_APPLI_STATE,
+
78  USBH_MSC_CTRL_ERROR_STATE,
+
79  USBH_MSC_UNRECOVERED_STATE
+
80 }
+
81 MSCState;
+
82 
+
83 
+
84 typedef struct _BOTXfer
+
85 {
+
86 uint8_t MSCState;
+
87 uint8_t MSCStateBkp;
+
88 uint8_t MSCStateCurrent;
+
89 uint8_t CmdStateMachine;
+
90 uint8_t BOTState;
+
91 uint8_t BOTStateBkp;
+
92 uint8_t* pRxTxBuff;
+
93 uint16_t DataLength;
+
94 uint8_t BOTXferErrorCount;
+
95 uint8_t BOTXferStatus;
+
96 } USBH_BOTXfer_TypeDef;
+
97 
+
98 
+
99 typedef union _USBH_CSW_Block
+
100 {
+
101  struct __CSW
+
102  {
+
103  uint32_t CSWSignature;
+
104  uint32_t CSWTag;
+
105  uint32_t CSWDataResidue;
+
106  uint8_t CSWStatus;
+
107  }field;
+
108  uint8_t CSWArray[13];
+
109 }HostCSWPkt_TypeDef;
+
110 
+
120 #define USBH_MSC_SEND_CBW 1
+
121 #define USBH_MSC_SENT_CBW 2
+
122 #define USBH_MSC_BOT_DATAIN_STATE 3
+
123 #define USBH_MSC_BOT_DATAOUT_STATE 4
+
124 #define USBH_MSC_RECEIVE_CSW_STATE 5
+
125 #define USBH_MSC_DECODE_CSW 6
+
126 #define USBH_MSC_BOT_ERROR_IN 7
+
127 #define USBH_MSC_BOT_ERROR_OUT 8
+
128 
+
129 
+
130 #define USBH_MSC_BOT_CBW_SIGNATURE 0x43425355
+
131 #define USBH_MSC_BOT_CBW_TAG 0x20304050
+
132 #define USBH_MSC_BOT_CSW_SIGNATURE 0x53425355
+
133 #define USBH_MSC_CSW_DATA_LENGTH 0x000D
+
134 #define USBH_MSC_BOT_CBW_PACKET_LENGTH 31
+
135 #define USBH_MSC_CSW_LENGTH 13
+
136 #define USBH_MSC_CSW_MAX_LENGTH 63
+
137 
+
138 /* CSW Status Definitions */
+
139 #define USBH_MSC_CSW_CMD_PASSED 0x00
+
140 #define USBH_MSC_CSW_CMD_FAILED 0x01
+
141 #define USBH_MSC_CSW_PHASE_ERROR 0x02
+
142 
+
143 #define USBH_MSC_SEND_CSW_DISABLE 0
+
144 #define USBH_MSC_SEND_CSW_ENABLE 1
+
145 
+
146 #define USBH_MSC_DIR_IN 0
+
147 #define USBH_MSC_DIR_OUT 1
+
148 #define USBH_MSC_BOTH_DIR 2
+
149 
+
150 //#define USBH_MSC_PAGE_LENGTH 0x40
+
151 #define USBH_MSC_PAGE_LENGTH 512
+
152 
+
153 
+
154 #define CBW_CB_LENGTH 16
+
155 #define CBW_LENGTH 10
+
156 #define CBW_LENGTH_TEST_UNIT_READY 6
+
157 
+
158 #define USB_REQ_BOT_RESET 0xFF
+
159 #define USB_REQ_GET_MAX_LUN 0xFE
+
160 
+
161 #define MAX_BULK_STALL_COUNT_LIMIT 0x04 /* If STALL is seen on Bulk
+
162  Endpoint continously, this means
+
163  that device and Host has phase error
+
164  Hence a Reset is needed */
+
165 
+
180 extern USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam;
+
181 extern HostCBWPkt_TypeDef USBH_MSC_CBWData;
+
182 extern HostCSWPkt_TypeDef USBH_MSC_CSWData;
+
190 void USBH_MSC_HandleBOTXfer(USB_OTG_CORE_HANDLE *pdev,
+
191  USBH_HOST *phost);
+
192 uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev,
+
193  USBH_HOST *phost);
+
194 void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev);
+
195 USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev,
+
196  USBH_HOST *phost,
+
197  uint8_t direction);
+
202 #endif //__USBH_MSC_BOT_H__
+
203 
+
204 
+
220 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
221 
+
_BOTXfer
Definition: usbh_msc_bot.h:84
+
usbh_stdreq.h
Header file for usbh_stdreq.c.
+
_USBH_CSW_Block::__CSW
Definition: usbh_msc_bot.h:101
+
_USBH_CSW_Block
Definition: usbh_msc_bot.h:99
+
_USBH_CBW_Block::__CBW
Definition: usbh_msc_bot.h:54
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_MSC_DecodeCSW
uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
USBH_MSC_DecodeCSW This function decodes the CSW received by the device and updates the same to upper...
Definition: usbh_msc_bot.c:487
+
USBH_MSC_Init
void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev)
USBH_MSC_Init Initializes the mass storage parameters.
Definition: usbh_msc_bot.c:125
+
USBH_MSC_BOT_Abort
USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t direction)
USBH_MSC_BOT_Abort This function manages the different Error handling for STALL.
Definition: usbh_msc_bot.c:432
+
USBH_MSC_HandleBOTXfer
void USBH_MSC_HandleBOTXfer(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost)
USBH_MSC_HandleBOTXfer This function manages the different states of BOT transfer and updates the sta...
Definition: usbh_msc_bot.c:147
+
_USBH_CBW_Block
Definition: usbh_msc_bot.h:52
+
_Host_TypeDef
Definition: usbh_core.h:215
+
+ +
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+ + diff --git a/usbh__msc__core_8c.html b/usbh__msc__core_8c.html new file mode 100644 index 0000000..f3ee493 --- /dev/null +++ b/usbh__msc__core_8c.html @@ -0,0 +1,528 @@ + + + + + + +discoverpixy: discovery/src/usbh_msc_core.c File Reference + + + + + + + + + + +
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usbh_msc_core.c File Reference
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#include "usbh_msc_core.h"
+#include "usbh_core.h"
+
+Include dependency graph for usbh_msc_core.c:
+
+
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+
+ + + +

+Data Structures

struct  MSC_Machine_TypeDef
 
+ + + + + + + + + + + + + + + + + + + + + + + +

+Functions

static USBH_Status USBH_MSC_InterfaceInit (USB_OTG_CORE_HANDLE *pdev, void *phost)
 
static void USBH_MSC_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev, void *phost)
 
static USBH_Status USBH_MSC_Handle (USB_OTG_CORE_HANDLE *pdev, void *phost)
 
static USBH_Status USBH_MSC_ClassRequest (USB_OTG_CORE_HANDLE *pdev, void *phost)
 
void USBH_LL_systick ()
 
void USBH_LL_setTimer ()
 
uint32_t USBH_LL_getTimer ()
 
int USBH_LL_open ()
 
int USBH_LL_close ()
 
int USBH_LL_send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
int USBH_LL_receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
+ + + + + + + + + + + + + +

+Variables

USB_OTG_CORE_HANDLE USB_OTG_Core
 
USBH_HOST USB_Host
 
USBH_Class_cb_TypeDef USBH_MSC_cb
 
MSC_Machine_TypeDef MSC_Machine
 
volatile uint32_t cnt
 
volatile uint32_t cnt_int
 
+

Function Documentation

+ +
+
+ + + + + + + +
int USBH_LL_close ()
+
+ +
+
+ +
+
+ + + + + + + +
uint32_t USBH_LL_getTimer ()
+
+ +
+
+ +
+
+ + + + + + + +
int USBH_LL_open ()
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int USBH_LL_receive (uint8_t * data,
uint32_t len,
uint16_t timeoutMs 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int USBH_LL_send (const uint8_t * data,
uint32_t len,
uint16_t timeoutMs 
)
+
+ +
+
+ +
+
+ + + + + + + +
void USBH_LL_setTimer ()
+
+ +
+
+ +
+
+ + + + + + + +
void USBH_LL_systick ()
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static USBH_Status USBH_MSC_ClassRequest (USB_OTG_CORE_HANDLE * pdev,
void * phost 
)
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static USBH_Status USBH_MSC_Handle (USB_OTG_CORE_HANDLE * pdev,
void * phost 
)
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
void USBH_MSC_InterfaceDeInit (USB_OTG_CORE_HANDLE * pdev,
void * phost 
)
+ 		+static
+
+ +
+
+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
static USBH_Status USBH_MSC_InterfaceInit (USB_OTG_CORE_HANDLE * pdev,
void * phost 
)
+ 		+static
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
volatile uint32_t cnt
+
+ +
+
+ +
+
+ + + + +
volatile uint32_t cnt_int
+
+ +
+
+ +
+
+ + + + +
MSC_Machine_TypeDef MSC_Machine
+
+ +
+
+ +
+
+ + + + +
USBH_HOST USB_Host
+
+ +
+
+ +
+
+ + + + +
USB_OTG_CORE_HANDLE USB_OTG_Core
+
+ +
+
+ +
+
+ + + + +
USBH_Class_cb_TypeDef USBH_MSC_cb
+
+Initial value:
=
+
{
+
USBH_MSC_InterfaceInit,
+
USBH_MSC_InterfaceDeInit,
+
USBH_MSC_ClassRequest,
+
USBH_MSC_Handle,
+
}
+
USBH_MSC_Handle
static USBH_Status USBH_MSC_Handle(USB_OTG_CORE_HANDLE *pdev, void *phost)
Definition: usbh_msc_core.c:133
+
USBH_MSC_InterfaceInit
static USBH_Status USBH_MSC_InterfaceInit(USB_OTG_CORE_HANDLE *pdev, void *phost)
Definition: usbh_msc_core.c:46
+
USBH_MSC_ClassRequest
static USBH_Status USBH_MSC_ClassRequest(USB_OTG_CORE_HANDLE *pdev, void *phost)
Definition: usbh_msc_core.c:125
+
USBH_MSC_InterfaceDeInit
static void USBH_MSC_InterfaceDeInit(USB_OTG_CORE_HANDLE *pdev, void *phost)
Definition: usbh_msc_core.c:107
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__core_8c__incl.map b/usbh__msc__core_8c__incl.map new file mode 100644 index 0000000..cdeaf7c --- /dev/null +++ b/usbh__msc__core_8c__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/usbh__msc__core_8c__incl.md5 b/usbh__msc__core_8c__incl.md5 new file mode 100644 index 0000000..63adb46 --- /dev/null +++ b/usbh__msc__core_8c__incl.md5 @@ -0,0 +1 @@ +328f9af93c7bd80a3e869de216833ed8 \ No newline at end of file diff --git a/usbh__msc__core_8c__incl.png b/usbh__msc__core_8c__incl.png new file mode 100644 index 0000000..1b083f1 Binary files /dev/null and b/usbh__msc__core_8c__incl.png differ diff --git a/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map new file mode 100644 index 0000000..e6d91f8 --- /dev/null +++ b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 new file mode 100644 index 0000000..a891b8f --- /dev/null +++ b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 @@ -0,0 +1 @@ +be629fde57f0f69e51857d356f441927 \ No newline at end of file diff --git a/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png new file mode 100644 index 0000000..716d1c6 Binary files /dev/null and b/usbh__msc__core_8c_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png differ diff --git a/usbh__msc__core_8h.html b/usbh__msc__core_8h.html new file mode 100644 index 0000000..dd06839 --- /dev/null +++ b/usbh__msc__core_8h.html @@ -0,0 +1,307 @@ + + + + + + +discoverpixy: discovery/src/usbh_msc_core.h File Reference + + + + + + + + + + +
+
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+
discoverpixy +
+
+
+ + + + + + +
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+
+
+Functions | +Variables
+
+
usbh_msc_core.h File Reference
+
+
+
#include "usbh_core.h"
+#include "usbh_stdreq.h"
+#include "usb_bsp.h"
+#include "usbh_ioreq.h"
+#include "usbh_hcs.h"
+
+Include dependency graph for usbh_msc_core.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + +

+Functions

void USBH_LL_systick ()
 
int USBH_LL_open ()
 
int USBH_LL_close ()
 
int USBH_LL_send (const uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
int USBH_LL_receive (uint8_t *data, uint32_t len, uint16_t timeoutMs)
 
void USBH_LL_setTimer ()
 
uint32_t USBH_LL_getTimer ()
 
+ + + +

+Variables

USBH_Class_cb_TypeDef USBH_MSC_cb
 
+

Function Documentation

+ +
+
+ + + + + + + +
int USBH_LL_close ()
+
+ +
+
+ +
+
+ + + + + + + +
uint32_t USBH_LL_getTimer ()
+
+ +
+
+ +
+
+ + + + + + + +
int USBH_LL_open ()
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int USBH_LL_receive (uint8_t * data,
uint32_t len,
uint16_t timeoutMs 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
int USBH_LL_send (const uint8_t * data,
uint32_t len,
uint16_t timeoutMs 
)
+
+ +
+
+ +
+
+ + + + + + + +
void USBH_LL_setTimer ()
+
+ +
+
+ +
+
+ + + + + + + +
void USBH_LL_systick ()
+
+ +

+Here is the caller graph for this function:
+
+
+ + +
+

+ +
+
+

Variable Documentation

+ +
+
+ + + + +
USBH_Class_cb_TypeDef USBH_MSC_cb
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__core_8h__dep__incl.map b/usbh__msc__core_8h__dep__incl.map new file mode 100644 index 0000000..1d91926 --- /dev/null +++ b/usbh__msc__core_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/usbh__msc__core_8h__dep__incl.md5 b/usbh__msc__core_8h__dep__incl.md5 new file mode 100644 index 0000000..9156910 --- /dev/null +++ b/usbh__msc__core_8h__dep__incl.md5 @@ -0,0 +1 @@ +c792f89d8bc36b332112735770f03f54 \ No newline at end of file diff --git a/usbh__msc__core_8h__dep__incl.png b/usbh__msc__core_8h__dep__incl.png new file mode 100644 index 0000000..a7cc84c Binary files /dev/null and b/usbh__msc__core_8h__dep__incl.png differ diff --git a/usbh__msc__core_8h__incl.map b/usbh__msc__core_8h__incl.map new file mode 100644 index 0000000..93dde10 --- /dev/null +++ b/usbh__msc__core_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/usbh__msc__core_8h__incl.md5 b/usbh__msc__core_8h__incl.md5 new file mode 100644 index 0000000..244f203 --- /dev/null +++ b/usbh__msc__core_8h__incl.md5 @@ -0,0 +1 @@ +6654c5cd9726e90a9a9a78c10d55d060 \ No newline at end of file diff --git a/usbh__msc__core_8h__incl.png b/usbh__msc__core_8h__incl.png new file mode 100644 index 0000000..189db14 Binary files /dev/null and b/usbh__msc__core_8h__incl.png differ diff --git a/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map new file mode 100644 index 0000000..e6d91f8 --- /dev/null +++ b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 new file mode 100644 index 0000000..a891b8f --- /dev/null +++ b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.md5 @@ -0,0 +1 @@ +be629fde57f0f69e51857d356f441927 \ No newline at end of file diff --git a/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png new file mode 100644 index 0000000..716d1c6 Binary files /dev/null and b/usbh__msc__core_8h_ac05bcf93a2aae0823c88bdabcc483444_icgraph.png differ diff --git a/usbh__msc__core_8h_source.html b/usbh__msc__core_8h_source.html new file mode 100644 index 0000000..6636142 --- /dev/null +++ b/usbh__msc__core_8h_source.html @@ -0,0 +1,135 @@ + + + + + + +discoverpixy: discovery/src/usbh_msc_core.h Source File + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
+ +
+ + +
+
+
+
usbh_msc_core.h
+
+
+Go to the documentation of this file.
1 
+
2 /* Define to prevent recursive ----------------------------------------------*/
+
3 #ifndef __USBH_MSC_CORE_H
+
4 #define __USBH_MSC_CORE_H
+
5 
+
6 /* Includes ------------------------------------------------------------------*/
+
7 #include "usbh_core.h"
+
8 #include "usbh_stdreq.h"
+
9 #include "usb_bsp.h"
+
10 #include "usbh_ioreq.h"
+
11 #include "usbh_hcs.h"
+
12 
+
13 
+
14 extern USBH_Class_cb_TypeDef USBH_MSC_cb;
+
15 
+
16 void USBH_LL_systick();
+
17 int USBH_LL_open();
+
18 int USBH_LL_close();
+
19 int USBH_LL_send(const uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
20 int USBH_LL_receive(uint8_t *data, uint32_t len, uint16_t timeoutMs);
+
21 void USBH_LL_setTimer();
+
22 uint32_t USBH_LL_getTimer();
+
23 
+
24 
+
25 #endif /* __USBH_MSC_CORE_H */
+
26 
+
27 
+
USBH_LL_open
int USBH_LL_open()
Definition: usbh_msc_core.c:170
+
USBH_LL_getTimer
uint32_t USBH_LL_getTimer()
Definition: usbh_msc_core.c:165
+
USBH_MSC_cb
USBH_Class_cb_TypeDef USBH_MSC_cb
Definition: usbh_msc_core.c:24
+
USBH_LL_send
int USBH_LL_send(const uint8_t *data, uint32_t len, uint16_t timeoutMs)
Definition: usbh_msc_core.c:196
+
USBH_LL_receive
int USBH_LL_receive(uint8_t *data, uint32_t len, uint16_t timeoutMs)
Definition: usbh_msc_core.c:224
+
USBH_LL_close
int USBH_LL_close()
Definition: usbh_msc_core.c:191
+
USBH_LL_systick
void USBH_LL_systick()
Definition: usbh_msc_core.c:155
+
USBH_LL_setTimer
void USBH_LL_setTimer()
Definition: usbh_msc_core.c:161
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__scsi_8c.html b/usbh__msc__scsi_8c.html new file mode 100644 index 0000000..3d492ac --- /dev/null +++ b/usbh__msc__scsi_8c.html @@ -0,0 +1,158 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_scsi.c File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
+
+ + +
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+ + +
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+
+Functions | +Variables
+
+
usbh_msc_scsi.c File Reference
+
+
+ +

This file implements the SCSI commands. +More...

+
#include "usbh_msc_core.h"
+#include "usbh_msc_scsi.h"
+#include "usbh_msc_bot.h"
+#include "usbh_ioreq.h"
+#include "usbh_def.h"
+
+Include dependency graph for usbh_msc_scsi.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device. More...
 
uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes)
 USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *dataBuffer, uint32_t address, uint32_t nbOfbytes)
 USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer. More...
 
+ + + + + +

+Variables

+MassStorageParameter_TypeDef USBH_MSC_Param
 
+__ALIGN_BEGIN uint8_t USBH_DataInBuffer[512] __ALIGN_END
 
+

Detailed Description

+

This file implements the SCSI commands.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__scsi_8c__incl.map b/usbh__msc__scsi_8c__incl.map new file mode 100644 index 0000000..792b233 --- /dev/null +++ b/usbh__msc__scsi_8c__incl.map @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__msc__scsi_8c__incl.md5 b/usbh__msc__scsi_8c__incl.md5 new file mode 100644 index 0000000..45f4061 --- /dev/null +++ b/usbh__msc__scsi_8c__incl.md5 @@ -0,0 +1 @@ +fc638bb56f3e52defc29d538a742bff2 \ No newline at end of file diff --git a/usbh__msc__scsi_8c__incl.png b/usbh__msc__scsi_8c__incl.png new file mode 100644 index 0000000..56f09b2 Binary files /dev/null and b/usbh__msc__scsi_8c__incl.png differ diff --git a/usbh__msc__scsi_8h.html b/usbh__msc__scsi_8h.html new file mode 100644 index 0000000..f7bffcc --- /dev/null +++ b/usbh__msc__scsi_8h.html @@ -0,0 +1,237 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_scsi.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
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+ + + + + + +
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+Classes | +Macros | +Typedefs | +Enumerations | +Functions | +Variables
+
+
usbh_msc_scsi.h File Reference
+
+
+ +

Header file for usbh_msc_scsi.c. +More...

+
#include "usbh_stdreq.h"
+
+Include dependency graph for usbh_msc_scsi.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + +

+Classes

struct  __MassStorageParameter
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

+#define OPCODE_TEST_UNIT_READY   0X00
 
+#define OPCODE_READ_CAPACITY10   0x25
 
+#define OPCODE_MODE_SENSE6   0x1A
 
+#define OPCODE_READ10   0x28
 
+#define OPCODE_WRITE10   0x2A
 
+#define OPCODE_REQUEST_SENSE   0x03
 
+#define DESC_REQUEST_SENSE   0X00
 
+#define ALLOCATION_LENGTH_REQUEST_SENSE   63
 
+#define XFER_LEN_READ_CAPACITY10   8
 
+#define XFER_LEN_MODE_SENSE6   63
 
+#define MASK_MODE_SENSE_WRITE_PROTECT   0x80
 
+#define MODE_SENSE_PAGE_CONTROL_FIELD   0x00
 
+#define MODE_SENSE_PAGE_CODE   0x3F
 
+#define DISK_WRITE_PROTECTED   0x01
 
+ + + +

+Typedefs

+typedef struct __MassStorageParameter MassStorageParameter_TypeDef
 
+ + + + + +

+Enumerations

enum  USBH_MSC_Status_TypeDef { USBH_MSC_OK = 0, +USBH_MSC_FAIL = 1, +USBH_MSC_PHASE_ERROR = 2, +USBH_MSC_BUSY = 3 + }
 
enum  CMD_STATES_TypeDef { CMD_UNINITIALIZED_STATE =0, +CMD_SEND_STATE, +CMD_WAIT_STATUS + }
 
+ + + + + + + + + + + + + + + + + + + + + +

+Functions

uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ReadCapacity10 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_ModeSense6 (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading the WriteProtect Status of the Mass-Storage device. More...
 
uint8_t USBH_MSC_RequestSense (USB_OTG_CORE_HANDLE *pdev)
 USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Write10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
 USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer. More...
 
uint8_t USBH_MSC_Read10 (USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
 USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the status to upper layer. More...
 
+void USBH_MSC_StateMachine (USB_OTG_CORE_HANDLE *pdev)
 
+ + + +

+Variables

+MassStorageParameter_TypeDef USBH_MSC_Param
 
+

Detailed Description

+

Header file for usbh_msc_scsi.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__msc__scsi_8h__dep__incl.map b/usbh__msc__scsi_8h__dep__incl.map new file mode 100644 index 0000000..efade11 --- /dev/null +++ b/usbh__msc__scsi_8h__dep__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/usbh__msc__scsi_8h__dep__incl.md5 b/usbh__msc__scsi_8h__dep__incl.md5 new file mode 100644 index 0000000..1ee93d9 --- /dev/null +++ b/usbh__msc__scsi_8h__dep__incl.md5 @@ -0,0 +1 @@ +84d7c7e1ca0b2495dd9c115f9b19b082 \ No newline at end of file diff --git a/usbh__msc__scsi_8h__dep__incl.png b/usbh__msc__scsi_8h__dep__incl.png new file mode 100644 index 0000000..44d9dc0 Binary files /dev/null and b/usbh__msc__scsi_8h__dep__incl.png differ diff --git a/usbh__msc__scsi_8h__incl.map b/usbh__msc__scsi_8h__incl.map new file mode 100644 index 0000000..7859241 --- /dev/null +++ b/usbh__msc__scsi_8h__incl.map @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__msc__scsi_8h__incl.md5 b/usbh__msc__scsi_8h__incl.md5 new file mode 100644 index 0000000..a620caf --- /dev/null +++ b/usbh__msc__scsi_8h__incl.md5 @@ -0,0 +1 @@ +e539e492a91462b77471db8896e49e55 \ No newline at end of file diff --git a/usbh__msc__scsi_8h__incl.png b/usbh__msc__scsi_8h__incl.png new file mode 100644 index 0000000..2b1f02c Binary files /dev/null and b/usbh__msc__scsi_8h__incl.png differ diff --git a/usbh__msc__scsi_8h_source.html b/usbh__msc__scsi_8h_source.html new file mode 100644 index 0000000..2d9ddfd --- /dev/null +++ b/usbh__msc__scsi_8h_source.html @@ -0,0 +1,180 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_scsi.h Source File + + + + + + + + + + +
+
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usbh_msc_scsi.h
+
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+Go to the documentation of this file.
1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_MSC_SCSI_H__
+
24 #define __USBH_MSC_SCSI_H__
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 #include "usbh_stdreq.h"
+
28 
+
29 
+
51 typedef enum {
+
52  USBH_MSC_OK = 0,
+
53  USBH_MSC_FAIL = 1,
+
54  USBH_MSC_PHASE_ERROR = 2,
+
55  USBH_MSC_BUSY = 3
+
56 }USBH_MSC_Status_TypeDef;
+
57 
+
58 typedef enum {
+
59  CMD_UNINITIALIZED_STATE =0,
+
60  CMD_SEND_STATE,
+
61  CMD_WAIT_STATUS
+
62 } CMD_STATES_TypeDef;
+
63 
+
64 
+
65 
+
66 typedef struct __MassStorageParameter
+
67 {
+
68  uint32_t MSCapacity;
+
69  uint32_t MSSenseKey;
+
70  uint16_t MSPageLength;
+
71  uint8_t MSBulkOutEp;
+
72  uint8_t MSBulkInEp;
+
73  uint8_t MSWriteProtect;
+
74 } MassStorageParameter_TypeDef;
+
87 #define OPCODE_TEST_UNIT_READY 0X00
+
88 #define OPCODE_READ_CAPACITY10 0x25
+
89 #define OPCODE_MODE_SENSE6 0x1A
+
90 #define OPCODE_READ10 0x28
+
91 #define OPCODE_WRITE10 0x2A
+
92 #define OPCODE_REQUEST_SENSE 0x03
+
93 
+
94 #define DESC_REQUEST_SENSE 0X00
+
95 #define ALLOCATION_LENGTH_REQUEST_SENSE 63
+
96 #define XFER_LEN_READ_CAPACITY10 8
+
97 #define XFER_LEN_MODE_SENSE6 63
+
98 
+
99 #define MASK_MODE_SENSE_WRITE_PROTECT 0x80
+
100 #define MODE_SENSE_PAGE_CONTROL_FIELD 0x00
+
101 #define MODE_SENSE_PAGE_CODE 0x3F
+
102 #define DISK_WRITE_PROTECTED 0x01
+
103 
+
117 extern MassStorageParameter_TypeDef USBH_MSC_Param;
+
125 uint8_t USBH_MSC_TestUnitReady(USB_OTG_CORE_HANDLE *pdev);
+
126 uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev);
+
127 uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev);
+
128 uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev);
+
129 uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev,
+
130  uint8_t *,
+
131  uint32_t ,
+
132  uint32_t );
+
133 uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev,
+
134  uint8_t *,
+
135  uint32_t ,
+
136  uint32_t );
+
137 void USBH_MSC_StateMachine(USB_OTG_CORE_HANDLE *pdev);
+
138 
+
143 #endif //__USBH_MSC_SCSI_H__
+
144 
+
145 
+
162 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
163 
+
usbh_stdreq.h
Header file for usbh_stdreq.c.
+
USBH_MSC_ReadCapacity10
uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev)
USBH_MSC_ReadCapacity10 Issue the read capacity command to the device. Once the response received...
Definition: usbh_msc_scsi.c:197
+
__MassStorageParameter
Definition: usbh_msc_scsi.h:66
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_MSC_ModeSense6
uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev)
USBH_MSC_ModeSense6 Issue the Mode Sense6 Command to the device. This function is used for reading th...
Definition: usbh_msc_scsi.c:283
+
USBH_MSC_Write10
uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
USBH_MSC_Write10 Issue the write command to the device. Once the response received, it updates the status to upper layer.
Definition: usbh_msc_scsi.c:471
+
USBH_MSC_RequestSense
uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev)
USBH_MSC_RequestSense Issues the Request Sense command to the device. Once the response received...
Definition: usbh_msc_scsi.c:375
+
USBH_MSC_Read10
uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev, uint8_t *, uint32_t, uint32_t)
USBH_MSC_Read10 Issue the read command to the device. Once the response received, it updates the stat...
Definition: usbh_msc_scsi.c:559
+
USBH_MSC_TestUnitReady
uint8_t USBH_MSC_TestUnitReady(USB_OTG_CORE_HANDLE *pdev)
USBH_MSC_TestUnitReady Issues 'Test unit ready' command to the device. Once the response received...
Definition: usbh_msc_scsi.c:125
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__stdreq_8c.html b/usbh__stdreq_8c.html new file mode 100644 index 0000000..cf69f2b --- /dev/null +++ b/usbh__stdreq_8c.html @@ -0,0 +1,148 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/src/usbh_stdreq.c File Reference + + + + + + + + + + +
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+
usbh_stdreq.c File Reference
+
+
+ +

This file implements the standard requests for device enumeration. +More...

+
#include "usbh_ioreq.h"
+#include "usbh_stdreq.h"
+
+Include dependency graph for usbh_stdreq.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + +

+Functions

USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t length)
 USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status. More...
 
USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t length)
 USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status. More...
 
USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
 USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status. More...
 
USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t *buff, uint16_t length)
 USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status. More...
 
USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t DeviceAddress)
 USBH_SetAddress This command sets the address to the connected device. More...
 
USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t cfg_idx)
 USBH_SetCfg The command sets the configuration value to the connected device. More...
 
USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num)
 USBH_ClrFeature This request is used to clear or disable a specific feature. More...
 
+

Detailed Description

+

This file implements the standard requests for device enumeration.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__stdreq_8c__incl.map b/usbh__stdreq_8c__incl.map new file mode 100644 index 0000000..1660deb --- /dev/null +++ b/usbh__stdreq_8c__incl.map @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__stdreq_8c__incl.md5 b/usbh__stdreq_8c__incl.md5 new file mode 100644 index 0000000..912325f --- /dev/null +++ b/usbh__stdreq_8c__incl.md5 @@ -0,0 +1 @@ +af725de29c597d58e0e1a5d6f879d04a \ No newline at end of file diff --git a/usbh__stdreq_8c__incl.png b/usbh__stdreq_8c__incl.png new file mode 100644 index 0000000..dbb76ec Binary files /dev/null and b/usbh__stdreq_8c__incl.png differ diff --git a/usbh__stdreq_8h.html b/usbh__stdreq_8h.html new file mode 100644 index 0000000..b59b17f --- /dev/null +++ b/usbh__stdreq_8h.html @@ -0,0 +1,184 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_stdreq.h File Reference + + + + + + + + + + +
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+
usbh_stdreq.h File Reference
+
+
+ +

Header file for usbh_stdreq.c. +More...

+
#include "usb_conf.h"
+#include "usb_hcd.h"
+#include "usbh_core.h"
+#include "usbh_def.h"
+
+Include dependency graph for usbh_stdreq.h:
+
+
+ + +
+
+This graph shows which files directly or indirectly include this file:
+
+
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Go to the source code of this file.

+ + + + + + + + + + + + + + +

+Macros

+#define FEATURE_SELECTOR_ENDPOINT   0X00
 
+#define FEATURE_SELECTOR_DEVICE   0X01
 
+#define INTERFACE_DESC_TYPE   0x04
 
+#define ENDPOINT_DESC_TYPE   0x05
 
+#define INTERFACE_DESC_SIZE   0x09
 
+#define USBH_HID_CLASS   0x03
 
+ + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

USBH_Status USBH_GetDescriptor (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t *buff, uint16_t length)
 USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status. More...
 
USBH_Status USBH_Get_DevDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t length)
 USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received, it parses the device descriptor and updates the status. More...
 
USBH_Status USBH_Get_StringDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
 USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received, it parses the string descriptor and updates the status. More...
 
USBH_Status USBH_SetCfg (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t configuration_value)
 USBH_SetCfg The command sets the configuration value to the connected device. More...
 
USBH_Status USBH_Get_CfgDesc (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t length)
 USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received, it parses the configuartion descriptor and updates the status. More...
 
USBH_Status USBH_SetAddress (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t DeviceAddress)
 USBH_SetAddress This command sets the address to the connected device. More...
 
USBH_Status USBH_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num)
 USBH_ClrFeature This request is used to clear or disable a specific feature. More...
 
+USBH_Status USBH_Issue_ClrFeature (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num)
 
+

Detailed Description

+

Header file for usbh_stdreq.c.

+
Author
MCD Application Team
+
Version
V2.0.0
+
Date
22-July-2011
+
Attention
+

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+

© COPYRIGHT 2011 STMicroelectronics

+
+ +
+Generated on Sun May 10 2015 15:15:19 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__stdreq_8h__dep__incl.map b/usbh__stdreq_8h__dep__incl.map new file mode 100644 index 0000000..8f797b1 --- /dev/null +++ b/usbh__stdreq_8h__dep__incl.map @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/usbh__stdreq_8h__dep__incl.md5 b/usbh__stdreq_8h__dep__incl.md5 new file mode 100644 index 0000000..4b75791 --- /dev/null +++ b/usbh__stdreq_8h__dep__incl.md5 @@ -0,0 +1 @@ +46495212b53f48a5d29fa4b12b5966de \ No newline at end of file diff --git a/usbh__stdreq_8h__dep__incl.png b/usbh__stdreq_8h__dep__incl.png new file mode 100644 index 0000000..c68aa5e Binary files /dev/null and b/usbh__stdreq_8h__dep__incl.png differ diff --git a/usbh__stdreq_8h__incl.map b/usbh__stdreq_8h__incl.map new file mode 100644 index 0000000..3b492ec --- /dev/null +++ b/usbh__stdreq_8h__incl.map @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usbh__stdreq_8h__incl.md5 b/usbh__stdreq_8h__incl.md5 new file mode 100644 index 0000000..3708dc5 --- /dev/null +++ b/usbh__stdreq_8h__incl.md5 @@ -0,0 +1 @@ +c2ac3efb5682f082e6d7380b5d60b372 \ No newline at end of file diff --git a/usbh__stdreq_8h__incl.png b/usbh__stdreq_8h__incl.png new file mode 100644 index 0000000..78a1174 Binary files /dev/null and b/usbh__stdreq_8h__incl.png differ diff --git a/usbh__stdreq_8h_source.html b/usbh__stdreq_8h_source.html new file mode 100644 index 0000000..89881e5 --- /dev/null +++ b/usbh__stdreq_8h_source.html @@ -0,0 +1,178 @@ + + + + + + +discoverpixy: discovery/libs/StmUsbHost/STM32_USB_HOST_Library/Core/inc/usbh_stdreq.h Source File + + + + + + + + + + +
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usbh_stdreq.h
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1 
+
22 /* Define to prevent recursive ----------------------------------------------*/
+
23 #ifndef __USBH_STDREQ_H
+
24 #define __USBH_STDREQ_H
+
25 
+
26 /* Includes ------------------------------------------------------------------*/
+
27 
+
28 #include "usb_conf.h"
+
29 #include "usb_hcd.h"
+
30 #include "usbh_core.h"
+
31 #include "usbh_def.h"
+
32 
+
50 /*Standard Feature Selector for clear feature command*/
+
51 #define FEATURE_SELECTOR_ENDPOINT 0X00
+
52 #define FEATURE_SELECTOR_DEVICE 0X01
+
53 
+
54 
+
55 #define INTERFACE_DESC_TYPE 0x04
+
56 #define ENDPOINT_DESC_TYPE 0x05
+
57 #define INTERFACE_DESC_SIZE 0x09
+
58 
+
59 
+
60 #define USBH_HID_CLASS 0x03
+
61 
+
92 USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
+
93  USBH_HOST *phost,
+
94  uint8_t req_type,
+
95  uint16_t value_idx,
+
96  uint8_t* buff,
+
97  uint16_t length );
+
98 
+
99 USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev,
+
100  USBH_HOST *phost,
+
101  uint8_t length);
+
102 
+
103 USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev,
+
104  USBH_HOST *phost,
+
105  uint8_t string_index,
+
106  uint8_t *buff,
+
107  uint16_t length);
+
108 
+
109 USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev,
+
110  USBH_HOST *phost,
+
111  uint16_t configuration_value);
+
112 
+
113 USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev,
+
114  USBH_HOST *phost,
+
115  uint16_t length);
+
116 
+
117 USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev,
+
118  USBH_HOST *phost,
+
119  uint8_t DeviceAddress);
+
120 
+
121 USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
+
122  USBH_HOST *phost,
+
123  uint8_t ep_num, uint8_t hc_num);
+
124 
+
125 USBH_Status USBH_Issue_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
+
126  USBH_HOST *phost,
+
127  uint8_t ep_num);
+
132 #endif /* __USBH_STDREQ_H */
+
133 
+
146 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
147 
+
148 
+
USBH_SetAddress
USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t DeviceAddress)
USBH_SetAddress This command sets the address to the connected device.
Definition: usbh_stdreq.c:240
+
usbh_core.h
Header file for usbh_core.c.
+
usb_hcd.h
Host layer Header file.
+
USB_OTG_handle
Definition: usb_core.h:287
+
USBH_Get_StringDesc
USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
USBH_Get_StringDesc Issues string Descriptor command to the device. Once the response received...
Definition: usbh_stdreq.c:178
+
USBH_Get_DevDesc
USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t length)
USBH_Get_DevDesc Issue Get Device Descriptor command to the device. Once the response received...
Definition: usbh_stdreq.c:110
+
USBH_Get_CfgDesc
USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t length)
USBH_Get_CfgDesc Issues Configuration Descriptor to the device. Once the response received...
Definition: usbh_stdreq.c:142
+
USBH_ClrFeature
USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num)
USBH_ClrFeature This request is used to clear or disable a specific feature.
Definition: usbh_stdreq.c:287
+
USBH_GetDescriptor
USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint8_t req_type, uint16_t value_idx, uint8_t *buff, uint16_t length)
USBH_GetDescriptor Issues Descriptor command to the device. Once the response received, it parses the descriptor and updates the status.
Definition: usbh_stdreq.c:210
+
_Host_TypeDef
Definition: usbh_core.h:215
+
USBH_SetCfg
USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost, uint16_t configuration_value)
USBH_SetCfg The command sets the configuration value to the connected device.
Definition: usbh_stdreq.c:263
+
usbh_def.h
Definitions used in the USB host library.
+
+ +
+Generated on Sun May 10 2015 15:15:18 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__usr_8c.html b/usbh__usr_8c.html new file mode 100644 index 0000000..3e04ee5 --- /dev/null +++ b/usbh__usr_8c.html @@ -0,0 +1,827 @@ + + + + + + +discoverpixy: discovery/src/usbh_usr.c File Reference + + + + + + + + + + +
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usbh_usr.c File Reference
+
+
+
#include "usbh_usr.h"
+#include <stdbool.h>
+#include <string.h>
+
+Include dependency graph for usbh_usr.c:
+
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USBH_USR_Init (void)
 USBH_USR_Init. More...
 
void USBH_USR_DeviceAttached (void)
 USBH_USR_DeviceAttached. More...
 
void USBH_USR_UnrecoveredError (void)
 USBH_USR_UnrecoveredError. More...
 
void USBH_USR_DeviceDisconnected (void)
 USBH_DisconnectEvent Device disconnect event. More...
 
void USBH_USR_ResetDevice (void)
 USBH_USR_ResetUSBDevice. More...
 
void USBH_USR_DeviceSpeedDetected (uint8_t DeviceSpeed)
 USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed. More...
 
void USBH_USR_Device_DescAvailable (void *DeviceDesc)
 USBH_USR_Device_DescAvailable. More...
 
void USBH_USR_DeviceAddressAssigned (void)
 USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address. More...
 
void USBH_USR_Configuration_DescAvailable (USBH_CfgDesc_TypeDef *cfgDesc, USBH_InterfaceDesc_TypeDef *itfDesc, USBH_EpDesc_TypeDef *epDesc)
 USBH_USR_Conf_Desc. More...
 
void USBH_USR_Manufacturer_String (void *ManufacturerString)
 USBH_USR_Manufacturer_String. More...
 
void USBH_USR_Product_String (void *ProductString)
 USBH_USR_Product_String. More...
 
void USBH_USR_SerialNum_String (void *SerialNumString)
 USBH_USR_SerialNum_String. More...
 
void USBH_USR_EnumerationDone (void)
 EnumerationDone User response request is displayed to ask application jump to class. More...
 
void USBH_USR_DeviceNotSupported (void)
 USBH_USR_DeviceNotSupported Device is not supported. More...
 
USBH_USR_Status USBH_USR_UserInput (void)
 USBH_USR_UserInput User Action for application state entry. More...
 
void USBH_USR_OverCurrentDetected (void)
 USBH_USR_OverCurrentDetected Over Current Detected on VBUS. More...
 
int USBH_USR_MSC_Application (void)
 USBH_USR_MSC_Application. More...
 
void USBH_USR_DeInit (void)
 USBH_USR_DeInit Deint User state and associated variables. More...
 
+ + + + + + + + + +

+Variables

USBH_Usr_cb_TypeDef USR_Callbacks
 
bool manufacturer_ok
 
bool product_ok
 
bool serial_ok
 
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void USBH_USR_Configuration_DescAvailable (USBH_CfgDesc_TypeDef * cfgDesc,
USBH_InterfaceDesc_TypeDef * itfDesc,
USBH_EpDesc_TypeDef * epDesc 
)
+
+ +

USBH_USR_Conf_Desc.

+
Parameters
+ + +
Configurationdescriptor
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeInit (void )
+
+ +

USBH_USR_DeInit Deint User state and associated variables.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Device_DescAvailable (void * DeviceDesc)
+
+ +

USBH_USR_Device_DescAvailable.

+
Parameters
+ + +
devicedescriptor
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceAddressAssigned (void )
+
+ +

USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
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+ +
+
+ + + + + + + + +
void USBH_USR_DeviceAttached (void )
+
+ +

USBH_USR_DeviceAttached.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
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+ +
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+ + + + + + + + +
void USBH_USR_DeviceDisconnected (void )
+
+ +

USBH_DisconnectEvent Device disconnect event.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Staus
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceNotSupported (void )
+
+ +

USBH_USR_DeviceNotSupported Device is not supported.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceSpeedDetected (uint8_t DeviceSpeed)
+
+ +

USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed.

+
Parameters
+ + +
Devicespeed:
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
void USBH_USR_EnumerationDone (void )
+
+ +

EnumerationDone User response request is displayed to ask application jump to class.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Init (void )
+
+ +

USBH_USR_Init.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
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+ +
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+ +
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+ + + + + + + + +
void USBH_USR_Manufacturer_String (void * ManufacturerString)
+
+ +

USBH_USR_Manufacturer_String.

+
Parameters
+ + +
ManufacturerString
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
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+ + + + + + + + +
int USBH_USR_MSC_Application (void )
+
+ +

USBH_USR_MSC_Application.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Staus
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_OverCurrentDetected (void )
+
+ +

USBH_USR_OverCurrentDetected Over Current Detected on VBUS.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Product_String (void * ProductString)
+
+ +

USBH_USR_Product_String.

+
Parameters
+ + +
ProductString
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_ResetDevice (void )
+
+ +

USBH_USR_ResetUSBDevice.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_SerialNum_String (void * SerialNumString)
+
+ +

USBH_USR_SerialNum_String.

+
Parameters
+ + +
SerialNum_String
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_UnrecoveredError (void )
+
+ +

USBH_USR_UnrecoveredError.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
USBH_USR_Status USBH_USR_UserInput (void )
+
+ +

USBH_USR_UserInput User Action for application state entry.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
USBH_USR_Status: User response for key button
+
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
bool manufacturer_ok
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+ +
+
+ +
+
+ + + + +
bool product_ok
+
+ +
+
+ +
+
+ + + + +
bool serial_ok
+
+ +
+
+ +
+
+ + + + +
USBH_Usr_cb_TypeDef USR_Callbacks
+
+Initial value:
=
+
{
+
USBH_USR_Init,
+
USBH_USR_DeInit,
+
USBH_USR_DeviceAttached,
+
USBH_USR_ResetDevice,
+
USBH_USR_DeviceDisconnected,
+
USBH_USR_OverCurrentDetected,
+
USBH_USR_DeviceSpeedDetected,
+
USBH_USR_Device_DescAvailable,
+
USBH_USR_DeviceAddressAssigned,
+
USBH_USR_Configuration_DescAvailable,
+
USBH_USR_Manufacturer_String,
+
USBH_USR_Product_String,
+
USBH_USR_SerialNum_String,
+
USBH_USR_EnumerationDone,
+
USBH_USR_UserInput,
+
USBH_USR_MSC_Application,
+
USBH_USR_DeviceNotSupported,
+
USBH_USR_UnrecoveredError
+
}
+
USBH_USR_Manufacturer_String
void USBH_USR_Manufacturer_String(void *ManufacturerString)
USBH_USR_Manufacturer_String.
Definition: usbh_usr.c:142
+
USBH_USR_EnumerationDone
void USBH_USR_EnumerationDone(void)
EnumerationDone User response request is displayed to ask application jump to class.
Definition: usbh_usr.c:173
+
USBH_USR_DeviceAttached
void USBH_USR_DeviceAttached(void)
USBH_USR_DeviceAttached.
Definition: usbh_usr.c:49
+
USBH_USR_ResetDevice
void USBH_USR_ResetDevice(void)
USBH_USR_ResetUSBDevice.
Definition: usbh_usr.c:88
+
USBH_USR_DeviceAddressAssigned
void USBH_USR_DeviceAddressAssigned(void)
USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address.
Definition: usbh_usr.c:120
+
USBH_USR_SerialNum_String
void USBH_USR_SerialNum_String(void *SerialNumString)
USBH_USR_SerialNum_String.
Definition: usbh_usr.c:162
+
USBH_USR_OverCurrentDetected
void USBH_USR_OverCurrentDetected(void)
USBH_USR_OverCurrentDetected Over Current Detected on VBUS.
Definition: usbh_usr.c:209
+
USBH_USR_DeviceSpeedDetected
void USBH_USR_DeviceSpeedDetected(uint8_t DeviceSpeed)
USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed.
Definition: usbh_usr.c:100
+
USBH_USR_Init
void USBH_USR_Init(void)
USBH_USR_Init.
Definition: usbh_usr.c:40
+
USBH_USR_DeviceNotSupported
void USBH_USR_DeviceNotSupported(void)
USBH_USR_DeviceNotSupported Device is not supported.
Definition: usbh_usr.c:184
+
USBH_USR_UserInput
USBH_USR_Status USBH_USR_UserInput(void)
USBH_USR_UserInput User Action for application state entry.
Definition: usbh_usr.c:195
+
USBH_USR_DeviceDisconnected
void USBH_USR_DeviceDisconnected(void)
USBH_DisconnectEvent Device disconnect event.
Definition: usbh_usr.c:76
+
USBH_USR_Device_DescAvailable
void USBH_USR_Device_DescAvailable(void *DeviceDesc)
USBH_USR_Device_DescAvailable.
Definition: usbh_usr.c:109
+
USBH_USR_MSC_Application
int USBH_USR_MSC_Application(void)
USBH_USR_MSC_Application.
Definition: usbh_usr.c:218
+
USBH_USR_Product_String
void USBH_USR_Product_String(void *ProductString)
USBH_USR_Product_String.
Definition: usbh_usr.c:152
+
USBH_USR_Configuration_DescAvailable
void USBH_USR_Configuration_DescAvailable(USBH_CfgDesc_TypeDef *cfgDesc, USBH_InterfaceDesc_TypeDef *itfDesc, USBH_EpDesc_TypeDef *epDesc)
USBH_USR_Conf_Desc.
Definition: usbh_usr.c:130
+
USBH_USR_DeInit
void USBH_USR_DeInit(void)
USBH_USR_DeInit Deint User state and associated variables.
Definition: usbh_usr.c:229
+
USBH_USR_UnrecoveredError
void USBH_USR_UnrecoveredError(void)
USBH_USR_UnrecoveredError.
Definition: usbh_usr.c:66
+
+
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
+ + diff --git a/usbh__usr_8c__incl.map b/usbh__usr_8c__incl.map new file mode 100644 index 0000000..9523939 --- /dev/null +++ b/usbh__usr_8c__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/usbh__usr_8c__incl.md5 b/usbh__usr_8c__incl.md5 new file mode 100644 index 0000000..bcfe897 --- /dev/null +++ b/usbh__usr_8c__incl.md5 @@ -0,0 +1 @@ +7c6008e278b8e5bb4bc3d69e087ee84f \ No newline at end of file diff --git a/usbh__usr_8c__incl.png b/usbh__usr_8c__incl.png new file mode 100644 index 0000000..5c8bc9e Binary files /dev/null and b/usbh__usr_8c__incl.png differ diff --git a/usbh__usr_8h.html b/usbh__usr_8h.html new file mode 100644 index 0000000..8f4bf16 --- /dev/null +++ b/usbh__usr_8h.html @@ -0,0 +1,753 @@ + + + + + + +discoverpixy: discovery/src/usbh_usr.h File Reference + + + + + + + + + + +
+
+ + + + + + +
+
discoverpixy +
+
+
+ + + + + + +
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+ + +
+ +
+ + +
+
+
+Functions | +Variables
+
+
usbh_usr.h File Reference
+
+
+
#include "stm32f4_discovery.h"
+#include "usbh_core.h"
+#include <stdio.h>
+
+Include dependency graph for usbh_usr.h:
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+ + +
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void USBH_USR_Init (void)
 USBH_USR_Init. More...
 
void USBH_USR_DeviceAttached (void)
 USBH_USR_DeviceAttached. More...
 
void USBH_USR_ResetDevice (void)
 USBH_USR_ResetUSBDevice. More...
 
void USBH_USR_DeviceDisconnected (void)
 USBH_DisconnectEvent Device disconnect event. More...
 
void USBH_USR_OverCurrentDetected (void)
 USBH_USR_OverCurrentDetected Over Current Detected on VBUS. More...
 
void USBH_USR_DeviceSpeedDetected (uint8_t DeviceSpeed)
 USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed. More...
 
void USBH_USR_Device_DescAvailable (void *)
 USBH_USR_Device_DescAvailable. More...
 
void USBH_USR_DeviceAddressAssigned (void)
 USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address. More...
 
void USBH_USR_Configuration_DescAvailable (USBH_CfgDesc_TypeDef *cfgDesc, USBH_InterfaceDesc_TypeDef *itfDesc, USBH_EpDesc_TypeDef *epDesc)
 USBH_USR_Conf_Desc. More...
 
void USBH_USR_Manufacturer_String (void *)
 USBH_USR_Manufacturer_String. More...
 
void USBH_USR_Product_String (void *)
 USBH_USR_Product_String. More...
 
void USBH_USR_SerialNum_String (void *)
 USBH_USR_SerialNum_String. More...
 
void USBH_USR_EnumerationDone (void)
 EnumerationDone User response request is displayed to ask application jump to class. More...
 
USBH_USR_Status USBH_USR_UserInput (void)
 USBH_USR_UserInput User Action for application state entry. More...
 
int USBH_USR_MSC_Application (void)
 USBH_USR_MSC_Application. More...
 
void USBH_USR_DeInit (void)
 USBH_USR_DeInit Deint User state and associated variables. More...
 
void USBH_USR_DeviceNotSupported (void)
 USBH_USR_DeviceNotSupported Device is not supported. More...
 
void USBH_USR_UnrecoveredError (void)
 USBH_USR_UnrecoveredError. More...
 
+ + + +

+Variables

USBH_Usr_cb_TypeDef USR_Callbacks
 
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
void USBH_USR_Configuration_DescAvailable (USBH_CfgDesc_TypeDef * cfgDesc,
USBH_InterfaceDesc_TypeDef * itfDesc,
USBH_EpDesc_TypeDef * epDesc 
)
+
+ +

USBH_USR_Conf_Desc.

+
Parameters
+ + +
Configurationdescriptor
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeInit (void )
+
+ +

USBH_USR_DeInit Deint User state and associated variables.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Device_DescAvailable (void * DeviceDesc)
+
+ +

USBH_USR_Device_DescAvailable.

+
Parameters
+ + +
devicedescriptor
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceAddressAssigned (void )
+
+ +

USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceAttached (void )
+
+ +

USBH_USR_DeviceAttached.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceDisconnected (void )
+
+ +

USBH_DisconnectEvent Device disconnect event.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Staus
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceNotSupported (void )
+
+ +

USBH_USR_DeviceNotSupported Device is not supported.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_DeviceSpeedDetected (uint8_t DeviceSpeed)
+
+ +

USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed.

+
Parameters
+ + +
Devicespeed:
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_EnumerationDone (void )
+
+ +

EnumerationDone User response request is displayed to ask application jump to class.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Init (void )
+
+ +

USBH_USR_Init.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Manufacturer_String (void * ManufacturerString)
+
+ +

USBH_USR_Manufacturer_String.

+
Parameters
+ + +
ManufacturerString
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
int USBH_USR_MSC_Application (void )
+
+ +

USBH_USR_MSC_Application.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
Staus
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_OverCurrentDetected (void )
+
+ +

USBH_USR_OverCurrentDetected Over Current Detected on VBUS.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_Product_String (void * ProductString)
+
+ +

USBH_USR_Product_String.

+
Parameters
+ + +
ProductString
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_ResetDevice (void )
+
+ +

USBH_USR_ResetUSBDevice.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_SerialNum_String (void * SerialNumString)
+
+ +

USBH_USR_SerialNum_String.

+
Parameters
+ + +
SerialNum_String
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
void USBH_USR_UnrecoveredError (void )
+
+ +

USBH_USR_UnrecoveredError.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
None
+
+
+ +
+
+ +
+
+ + + + + + + + +
USBH_USR_Status USBH_USR_UserInput (void )
+
+ +

USBH_USR_UserInput User Action for application state entry.

+
Parameters
+ + +
None
+
+
+
Return values
+ + +
USBH_USR_Status: User response for key button
+
+
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
USBH_Usr_cb_TypeDef USR_Callbacks
+
+ +
+
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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usbh_usr.h
+
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+Go to the documentation of this file.
1 
+
2 /* Define to prevent recursive inclusion -------------------------------------*/
+
3 #ifndef __USH_USR_H__
+
4 #define __USH_USR_H__
+
5 
+
6 #ifdef __cplusplus
+
7  extern "C" {
+
8 #endif
+
9 
+
10 /* Includes ------------------------------------------------------------------*/
+
11 #include "stm32f4_discovery.h"
+
12 #include "usbh_core.h"
+
13 #include <stdio.h>
+
14 
+
15 
+
16 /* Exported macros -----------------------------------------------------------*/
+
17 /* Exported variables --------------------------------------------------------*/
+
18 extern USBH_Usr_cb_TypeDef USR_Callbacks;
+
19 
+
20 /* Exported functions ------------------------------------------------------- */
+
21 void USBH_USR_Init(void);
+
22 void USBH_USR_DeviceAttached(void);
+
23 void USBH_USR_ResetDevice(void);
+
24 void USBH_USR_DeviceDisconnected (void);
+
25 void USBH_USR_OverCurrentDetected (void);
+
26 void USBH_USR_DeviceSpeedDetected(uint8_t DeviceSpeed);
+
27 void USBH_USR_Device_DescAvailable(void *);
+
28 void USBH_USR_DeviceAddressAssigned(void);
+
29 void USBH_USR_Configuration_DescAvailable(USBH_CfgDesc_TypeDef * cfgDesc,
+
30  USBH_InterfaceDesc_TypeDef *itfDesc,
+
31  USBH_EpDesc_TypeDef *epDesc);
+
32 void USBH_USR_Manufacturer_String(void *);
+
33 void USBH_USR_Product_String(void *);
+
34 void USBH_USR_SerialNum_String(void *);
+
35 void USBH_USR_EnumerationDone(void);
+
36 USBH_USR_Status USBH_USR_UserInput(void);
+
37 int USBH_USR_MSC_Application(void);
+
38 void USBH_USR_DeInit(void);
+
39 void USBH_USR_DeviceNotSupported(void);
+
40 void USBH_USR_UnrecoveredError(void);
+
41 #ifdef __cplusplus
+
42 }
+
43 #endif
+
44 
+
45 #endif /*__USH_USR_H__*/
+
46 
+
47 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
48 
+
49 
+
50 
+
51 
+
USBH_USR_OverCurrentDetected
void USBH_USR_OverCurrentDetected(void)
USBH_USR_OverCurrentDetected Over Current Detected on VBUS.
Definition: usbh_usr.c:209
+
USBH_USR_ResetDevice
void USBH_USR_ResetDevice(void)
USBH_USR_ResetUSBDevice.
Definition: usbh_usr.c:88
+
USBH_USR_DeInit
void USBH_USR_DeInit(void)
USBH_USR_DeInit Deint User state and associated variables.
Definition: usbh_usr.c:229
+
USBH_USR_DeviceDisconnected
void USBH_USR_DeviceDisconnected(void)
USBH_DisconnectEvent Device disconnect event.
Definition: usbh_usr.c:76
+
USR_Callbacks
USBH_Usr_cb_TypeDef USR_Callbacks
Definition: usbh_usr.c:6
+
USBH_USR_Device_DescAvailable
void USBH_USR_Device_DescAvailable(void *)
USBH_USR_Device_DescAvailable.
Definition: usbh_usr.c:109
+
USBH_USR_DeviceAttached
void USBH_USR_DeviceAttached(void)
USBH_USR_DeviceAttached.
Definition: usbh_usr.c:49
+
USBH_USR_Init
void USBH_USR_Init(void)
USBH_USR_Init.
Definition: usbh_usr.c:40
+
USBH_USR_UnrecoveredError
void USBH_USR_UnrecoveredError(void)
USBH_USR_UnrecoveredError.
Definition: usbh_usr.c:66
+
USBH_USR_Manufacturer_String
void USBH_USR_Manufacturer_String(void *)
USBH_USR_Manufacturer_String.
Definition: usbh_usr.c:142
+
USBH_USR_SerialNum_String
void USBH_USR_SerialNum_String(void *)
USBH_USR_SerialNum_String.
Definition: usbh_usr.c:162
+
USBH_USR_DeviceSpeedDetected
void USBH_USR_DeviceSpeedDetected(uint8_t DeviceSpeed)
USBH_USR_DeviceSpeedDetected Displays the message on LCD for device speed.
Definition: usbh_usr.c:100
+
USBH_USR_DeviceNotSupported
void USBH_USR_DeviceNotSupported(void)
USBH_USR_DeviceNotSupported Device is not supported.
Definition: usbh_usr.c:184
+
USBH_USR_EnumerationDone
void USBH_USR_EnumerationDone(void)
EnumerationDone User response request is displayed to ask application jump to class.
Definition: usbh_usr.c:173
+
USBH_USR_Configuration_DescAvailable
void USBH_USR_Configuration_DescAvailable(USBH_CfgDesc_TypeDef *cfgDesc, USBH_InterfaceDesc_TypeDef *itfDesc, USBH_EpDesc_TypeDef *epDesc)
USBH_USR_Conf_Desc.
Definition: usbh_usr.c:130
+
USBH_USR_Product_String
void USBH_USR_Product_String(void *)
USBH_USR_Product_String.
Definition: usbh_usr.c:152
+
USBH_USR_UserInput
USBH_USR_Status USBH_USR_UserInput(void)
USBH_USR_UserInput User Action for application state entry.
Definition: usbh_usr.c:195
+
USBH_USR_MSC_Application
int USBH_USR_MSC_Application(void)
USBH_USR_MSC_Application.
Definition: usbh_usr.c:218
+
USBH_USR_DeviceAddressAssigned
void USBH_USR_DeviceAddressAssigned(void)
USBH_USR_DeviceAddressAssigned USB device is successfully assigned the Address.
Definition: usbh_usr.c:120
+
+ +
+Generated on Sun May 10 2015 15:30:06 for discoverpixy by   +doxygen + 1.8.9.1 +
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